LTC3717 [Linear]
Wide Operating Range, No RSENSE Step-Down Controller for DDR/QDR Memory Termination; 宽工作范围，无检测电阻降压型控制器，用于DDR / QDR存储器终端
| 型号： | LTC3717 |
| 厂家： | 
Linear |
| 描述： | Wide Operating Range, No RSENSE Step-Down Controller for DDR/QDR Memory Termination |
| 文件： | 总20页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3717
Wide Operating Range,
No RSENSETM Step-Down Controller
for DDR/QDR Memory Termination
U
DESCRIPTIO
FEATURES
The LTC®3717 is a synchronous step-down switching
regulator controller for double data rate (DDR) and Quad
Data RateTM (QDRTM) memory termination. The controller
uses a valley current control architecture to deliver very
low duty cycles without requiring a sense resistor. Oper-
ating frequency is selected by an external resistor and is
compensated for variations in VIN.
■
VOUT = 1/2 VIN (Supply Splitter)
■
Adjustable and Symmetrical Sink/Source
Current Limit up to 20A
■
±0.65% Output Voltage Accuracy
■
Up to 97% Efficiency
■
No Sense Resistor Required
■
Ultrafast Transient Response
■
True Current Mode Control
Forced continuous operation reduces noise and RF inter-
ference. Output voltage is internally set to half of VREF
which is user programmable.
■
2% to 90% Duty Cycle at 200kHz
,
■
t
ON(MIN) ≤ 100ns
■
■
■
■
■
■
■
■
Stable with Ceramic COUT
Dual N-Channel MOSFET Synchronous Drive
Power Good Output Voltage Monitor
Wide VCC Range: 4V to 36V
Adjustable Switching Frequency up to 1.5MHz
Output Overvoltage Protection
Optional Short-Circuit Shutdown Timer
Fault protection is provided by an output overvoltage
comparator and optional short-circuit shutdown timer.
Soft-start capability for supply sequencing is accom-
plished using an external timing capacitor. The regulator
current limit level is symmetrical and user programmable.
Wide supply range allows operation from 4V to 36V at the
VCC input.
Available in a 16U-Pin Narrow SSOP Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
No RSENSE is a trademark of Linear Technology Corporation.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.
APPLICATIO S
■
Bus Termination: DDR and QDR Memory, SSTL,
HSTL, ...
■
Notebook Computers, Desktop Servers
Tracking Power Supply
■
U
TYPICAL APPLICATIO
V
CC
5V TO 28V
Efficiency vs Load Current
R
ON
715k
1µF
V
V
IN
100
90
80
70
60
50
40
30
20
10
0
CC
I
ON
V
= 1.25V
OUT
2.5V TO 5.5V
+
+
C
IN
V
DD
= 2.5V
V
REF
TG
150µF
6.3V
×2
V
IN
= 5V
M1
D2
RUN/SS
Si7840DP
B320A
V
= 2.5V
C
IN
C
C
SS
0.1µF
V
SW
OUT
470pF
1.25V
C
B
0.22µF
L1
0.68µH
C
OUT
I
BOOST
±10A
TH
D
180µF
4V
B
R
C
LTC3717
SGND INTV
CMDSH-3
20k
×2
CC
M2
Si7840DP
D1
B320A
BG
+
C
VCC
4.7µF
PGOOD PGND
0
2
4
6
8
10
12
14
V
FB
3717 F01a
LOAD CURRENT (A)
3717 F01b
Figure 1. High Efficiency DDR Memory Termination Supply
sn3717 3717fs
1
LTC3717
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
Input Supply Voltage (VCC, ION) .................36V to –0.3V
Boosted Topside Driver Supply Voltage
(BOOST) ................................................... 42V to –0.3V
SW Voltage .................................................. 36V to –5V
EXTVCC, (BOOST – SW), RUN/SS,
PGOOD Voltages....................................... 7V to –0.3V
VREF, VRNG Voltages ...............(INTVCC + 0.3V) to –0.3V
ITH, VFB Voltages...................................... 2.7V to –0.3V
TG, BG, INTVCC, EXTVCC Peak Currents.................... 2A
TG, BG, INTVCC, EXTVCC RMS Currents .............. 50mA
Operating Ambient Temperature
TOP VIEW
RUN/SS
PGOOD
1
2
3
4
5
6
7
8
16 BOOST
15 TG
LTC3717EGN
V
14
13
12
11
10
9
SW
RNG
I
TH
PGND
BG
SGND
I
ON
INTV
CC
GN PART
MARKING
V
V
FB
CC
V
EXTV
REF
CC
3717
GN PACKAGE
16-LEAD PLASTIC SSOP
Range (Note 4) ................................... –40°C to 85°C
Junction Temperature (Note 2)............................ 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
I
Input DC Supply Current
Normal
Shutdown Supply Current
Q
1000
15
2000
30
µA
µA
V
= 0V
RUN/SS
V
Feedback Voltage Accuracy
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
Error Amplifier Transconductance
On-Time
I
= 1.2V (Note 3), V = 2.4V
REF
–0.65
0.93
0.65
%
%/V
%
FB
TH
∆V
∆V
V
= 4V to 36V, I = 1.2V (Note 3)
0.002
–0.05
1.13
FB(LINEREG)
FB(LOADREG)
CC
TH
I
I
= 0.5V to 1.9V (Note 3)
= 1.2V (Note 3)
●
–0.3
1.33
TH
g
mS
m(EA)
TH
t
I
I
= 30µA
= 60µA
186
95
233
115
280
135
ns
ns
ON
ON
ON
t
t
Minimum On-Time
I
I
= 180µA
= 30µA
50
100
400
ns
ns
ON(MIN)
OFF(MIN)
ON
ON
Minimum Off-Time
300
V
Maximum Current Sense Threshold (Source)
V
V
V
= 1V, V = V
– 50mV
– 50mV
●
●
●
108
76
148
135
95
185
162
114
222
mV
mV
mV
SENSE(MAX)
RNG
RNG
RNG
FB
REF/2
REF/2
V
PGND
– V
= 0V, V = V
SW
FB
= INTV , V = V
– 50mV
CC FB
REF/2
V
Minimum Current Sense Threshold (Sink)
– V
V
V
V
= 1V, V = V
+ 50mV
+ 50mV
●
●
●
–140
–97
–200
–165
–115
–235
–190
–133
–270
mV
mV
mV
SENSE(MIN)
RNG
RNG
RNG
FB
REF/2
REF/2
V
= 0V, V = V
PGND
SW
FB
= INTV , V = V
+ 50mV
CC FB
REF/2
∆V
∆V
Output Overvoltage Fault Threshold
Output Undervoltage Fault Threshold
RUN Pin Start Threshold
8
10
–25
1.5
4
12
%
%
V
FB(OV)
FB(UV)
V
V
V
●
0.8
2
RUN/SS(ON)
RUN/SS(LE)
RUN/SS(LT)
RUN/SS(C)
RUN/SS(D)
RUN Pin Latchoff Enable Threshold
RUN Pin Latchoff Threshold
Soft-Start Charge Current
RUN/SS Pin Rising
RUN/SS Pin Falling
4.5
4.2
–3
3
V
3.5
–1.2
1.8
V
I
I
–0.5
0.8
µA
Soft-Start Discharge Current
µA
sn3717 3717fs
2
LTC3717
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 15V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
3.4
3.5
2
MAX
3.9
4
UNITS
V
V
V
Undervoltage Lockout Threshold
Undervoltage Lockout Threshold
TG Driver Pull-Up On Resistance
TG Driver Pull-Down On Resistance
BG Driver Pull-Up On Resistance
BG Driver Pull-Down On Resistance
TG Rise Time
V
V
Falling
Rising
●
●
CC(UVLO)
CC
CC
V
CC(UVLOR)
TG R
TG R
BG R
BG R
TG High
TG Low
BG High
BG Low
3
Ω
UP
2
3
Ω
DOWN
UP
3
4
Ω
1
2
Ω
DOWN
TG t
TG t
C
C
C
C
= 3300pF
= 3300pF
= 3300pF
= 3300pF
20
20
20
20
ns
ns
ns
ns
r
f
LOAD
LOAD
LOAD
LOAD
TG Fall Time
BG t
BG t
BG Rise Time
r
f
BG Fall Time
Internal V Regulator
CC
V
Internal V Voltage
6V < V < 30V, V = 4V
EXTVCC
●
●
4.7
4.5
5
5.3
V
%
INTVCC
CC
CC
∆V
Internal V Load Regulation
I
I
I
= 0mA to 20mA, V = 4V
EXTVCC
–0.1
4.7
±2
LDO(LOADREG)
EXTVCC
CC
CC
CC
CC
V
EXTV Switchover Voltage
= 20mA, V
= 20mA, V
Rising
= 5V
V
CC
EXTVCC
EXTVCC
∆V
∆V
EXTV Switch Drop Voltage
150
200
300
mV
mV
EXTVCC
CC
EXTV Switchover Hysteresis
EXTVCC(HYS)
CC
PGOOD Output
∆V
∆V
∆V
PGOOD Upper Threshold
PGOOD Lower Threshold
PGOOD Hysteresis
V
V
V
Rising (0% = 1/3 V
Falling (0% = 1/3 V
)
8
10
–10
1
12
–12
2
%
%
%
V
FBH
FB
REF
)
–8
FBL
FB
REF
Returning (0% = 1/3 V )
REF
FB(HYS)
FB
V
PGOOD Low Voltage
I
= 5mA
0.15
0.4
PGL
PGOOD
Note 1: Absolute Maximum Ratings are those values beyond which the life of
a device may be impaired.
Note 3: The LTC3717 is tested in a feedback loop that adjusts V to achieve
FB
a specified error amplifier output voltage (I ).
TH
Note 2: T is calculated from the ambient temperature T and power
Note4:TheLTC3717Eisguaranteedtomeetperformancespecificationsfrom
0°C to 70°C. Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with statistical
process controls.
J
A
dissipation P as follows:
D
LTC3717EGN: T = T + (P • 130°C/W)
J
A
D
sn3717 3717fs
3
LTC3717
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VOUT/VIN Tracking Ratio vs Input
Efficiency vs Load Current
Voltage
Frequency vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
50.00
49.95
49.90
49.85
49.80
49.75
49.70
49.65
450
400
350
300
250
200
150
100
50
V
IN
V
OUT
= 2.5V
= 1.25V
LOAD = 0A
LOAD = 10A
LOAD = 1A
LOAD = 0A
LOAD = 10A
V
= 1.25V
FIGURE 1 CIRCUIT
OUT
FIGURE 1 CIRCUIT
10 100
FIGURE 1 CIRCUIT
0
0.01
0.1
1
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
INPUT VOLTAGE (V)
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
INPUT VOLTAGE (V)
LOAD CURRENT (A)
3717 G06
3717 G07
3717 G08
Load Regulation
Start-Up Response
Load-Step Transient
0
V
V
= 2.5V
OUT
VOUT
1V/DIV
VOUT
200mV/DIV
IN
= 1.25V
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
IL
IL
2A/DIV
5A/DIV
VIN = 2.5V
4ms/DIV
3718 G09.eps
VIN = 2.5V
20µs/DIV
3718 G10.eps
FIGURE 1 CIRCUIT
VOUT = 1.25V
LOAD = 0.2Ω
FIGURE 1 CIRCUIT
VOUT = 1.25V
LOAD = 500mA TO 10A STEP
FIGURE 1 CIRCUIT
0
1
2
3
4
5
6
7
8
9
10
LOAD CURRENT (A)
3717 G09
On-Time vs VON Voltage
On-Time vs Temperature
On-Time vs ION Current
10k
1000
800
600
400
200
0
300
250
200
150
I
= 30µA
ION
I
= 30µA
ION
1k
100
10
100
50
0
2
3
0
1
1
10
100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
V
VOLTAGE (V)
I
CURRENT (µA)
ON
ON
3717 G13
3717 G11
3717 G12
sn3717 3717fs
4
LTC3717
U W
TYPICAL PERFOR A CE CHARACTERISTICS
RUN/SS Latchoff Thresholds
vs Temperature
RUN/SS Latchoff Thresholds
vs Temperature
INTVCC Load Regulation
3
2
5.0
4.5
4.0
3.5
0
–0.1
–0.2
–0.3
–0.4
–0.5
PULL-DOWN CURRENT
LATCHOFF ENABLE
1
0
PULL-UP CURRENT
–1
LATCHOFF THRESHOLD
–2
3.0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
0
10
20
30
40
50
TEMPERATURE (°C)
TEMPERATURE (°C)
INTV LOAD CURRENT (mA)
CC
3717 G15
3717 G16
3717 G14
Undervoltage Lockout Threshold
vs Temperature
Maximum Current Sense Threshold
vs VRNG Voltage
Maximum Current Sense Threshold
vs RUN/SS Voltage, VRNG = 1V
300
250
200
150
100
50
4.0
3.5
3.0
2.5
160
140
120
100
80
60
40
20
0
2.0
0
2.4
–50 –25
0
25
50
75 100 125
0.50
1.00 1.25 1.50
(V)
1.75 2.00
2.0 2.2
2.6 2.8 3.0 3.2 3.4 3.6
RUN/SS (V)
0.75
TEMPERATURE (C)
V
RNG
3717 G17
3717 G18
3717 G19
Error Amplifier gm
vs Temperature
Maximum Current Sense Threshold
vs Temperature, VRNG = 1V
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
180
160
140
120
100
80
60
40
20
0
–50
110
130
–50
10 30 50
90
–30 –10
70
110
130
10 30 50
90
–30 –10
70
TEMPERATURE (°C)
3717 G21
TEMPERATURE (°C)
3717 G20
sn3717 3717fs
5
LTC3717
U
U
U
PI FU CTIO S
RUN/SS (Pin 1): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
before it is applied to the positive input of the error
amplifier. Reference voltage for output voltage, power
goodthreshold, andshort-circuitshutdownthreshold. Do
not apply more than 3V on VREF. If higher voltages are
used, connect an external resistor (R1 ≥ 160k) from
voltage reference to VREF
.
PGOOD (Pin 2): Power Good Output. Open drain logic
output that is pulled to ground when the output voltage is
not within ±10% of the regulation point.
EXTVCC (Pin 9): External VCC Input. When EXTVCC ex-
ceeds 4.7V, an internal switch connects this pin to INTVCC
and shuts down the internal regulator so that controller
andgatedrivepowerisdrawnfromEXTVCC.Donotexceed
7V at this pin and ensure that EXTVCC < VCC.
V
RNG (Pin 3): Sense Voltage Range Input. The voltage at
this pin is ten times the nominal sense voltage at maxi-
mum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.
VCC (Pin 10): Bias Input Supply. 4V to 36V operating
range. Decouple this pin to PGND with an RC filter (1Ω,
0.1µF).
ITH (Pin 4): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 0.8V corresponding to zero sense
voltage (zero current).
INTVCC (Pin 11): Internal 5V Regulator Output. The driver
and control circuits are powered from this voltage. De-
couple this pin to power ground with a minimum of 4.7µF
low ESR tantalum or ceramic capacitor.
BG (Pin 12): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.
SGND (Pin 5): Signal Ground. All small-signal compo-
nents and compensation components should connect to
this ground, which in turn connects to PGND at one point.
PGND (Pin 13):Power Ground. Connect this pin closely to
the source of the bottom N-channel MOSFET, the (–)
terminal of CVCC and the (–) terminal of CIN.
ION (Pin 6): On-Time Current Input. Tie a resistor from VIN
tothispintosettheone-shottimercurrentandtherebyset
the switching frequency.
SW (Pin 14): Switch Node. The (–) terminal of the boot-
strap capacitor CB connects here. This pin swings from a
diode voltage drop below ground up to a diode voltage
drop above VIN.
VFB (Pin 7): Error Amplifier Feedback Input. This pin
connects to VOUT and divides its voltage to 2/3 • VFB
through precision internal resistors before it is applied to
the input of the error amplifier. Do not apply more than
1.5V on VFB. For higher output voltages, attach an external
resistor R2 (1/2 • R1 at VREF) from VOUT to VFB.
TG (Pin 15): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superim-
posed on the switch node voltage SW.
BOOST (Pin 16): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
VIN + INTVCC.
VREF (Pin 8): Positive Input of Internal Error Amplifier.
This pin connects to an external reference and divides its
voltage to 1/3 VREF through precision internal resisters
sn3717 3717fs
6
LTC3717
U
U
W
FU CTIO AL DIAGRA
R
ON
V
IN
10
V
CC
6
I
ON
9
EXTV
CC
4.7V
+
C
IN
+
–
1.192V
BNGP
5V
REG
BOOST
16
INTV
CC
0.7V
t
ON
=
(10pF)
R
S
C
B
TG
I
ION
Q
I
FCNT
M1
15
SW
14
ON
20k
+
–
+
–
L1
SWITCH
LOGIC
I
V
OUT
CMP
REV
D
B
INTV
CC
11
SHDN
OV
+
C
OUT
C
VCC
1.4V
BG
12
M2
V
RNG
PGND
13
3
×
PGOOD
2
0.7V
5.7µA
1
3
10
V
240k
+
–
REF
7
V
FB
Q2
UV
OV
20k
40k
I
THB
Q1
+
–
Q5
5
SGND
11
30
V
REF
RUN
SHDN
SS
–
+
1.2µA
EA
–
+
6V
0.6V
C
C1
C
SS
I
RUN/SS
1
4
TH
V
REF
8
V
REF
R
C
80k
40k
4
3717 FD
sn3717 3717fs
7
LTC3717
U
OPERATIO
Main Control Loop
Furthermore, in an overvoltage condition, M1 is turned off
and M2 is turned on and held on until the overvoltage
condition clears.
The LTC3717 is a current mode controller for DC/DC
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a
one-shot timer OST. When the top MOSFET is turned off,
the bottom MOSFET is turned on until the current com-
parator ICMP trips, restarting the one-shot timer and initi-
ating the next cycle. Inductor current is determined by
sensing the voltage between the PGND and SW pins using
the bottom MOSFET on-resistance . The voltage on the ITH
pin sets the comparator threshold corresponding to in-
ductor valley current. The error amplifier EA adjusts this
ITH voltage by comparing 2/3 of the feedback signal VFB
from the output voltage with a reference equal to 1/3 of the
VREF voltage. If the load current increases, it causes a drop
in the feedback voltage relative to the reference. The ITH
voltage then rises until the average inductor current again
matches the load current. As a result in normal DDR
operation VOUT is equal to 1/2 of the VREF voltage.
Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing
the pin allows an internal 1.2µA current source to charge
up an external soft-start capacitor CSS. When this voltage
reaches 1.5V, the controller turns on and begins switch-
ing, but with the ITH voltage clamped at approximately
0.6V below the RUN/SS voltage. As CSS continues to
charge, the soft-start current limit is removed.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is re-
chargedfromINTVCC throughanexternalSchottkydiode
DB when the top MOSFET is turned off. When the EXTVCC
pin is grounded, an internal 5V low dropout regulator
supplies the INTVCC power from VCC. If EXTVCC rises
above 4.7V, the internal regulator is turned off, and an
internal switch connects EXTVCC to INTVCC. This allows
ahighefficiencysourceconnectedtoEXTVCC, suchasan
external 5V supply or a secondary output from the
converter, to provide the INTVCC power. Voltages up to
7V can be applied to EXTVCC for additional gate drive. If
the VCC voltage is low and INTVCC drops below 3.4V,
undervoltage lockout circuitry prevents the power
switches from turning on.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an on-
time that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN. The nominal frequency can be adjusted with an
external resistor RON.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point.
W U U
U
APPLICATIO S I FOR ATIO
The basic LTC3717 application circuit is shown in
Figure 1. External component selection is primarily deter-
mined by the maximum load current and begins with the
selection of the sense resistance and power MOSFET
switches. The LTC3717 uses the on-resistance of the syn-
chronous power MOSFET for determining the inductor
current. The desired amount of ripple current and operating
frequency largely determines the inductor value. Finally, CIN
is selected for its ability to handle the large RMS current into
the converter and COUT is chosen with low enough ESR to
meet the output voltage ripple and transient specification.
Maximum Sense Voltage and VRNG Pin
Inductor current is determined by measuring the voltage
across a sense resistance that appears between the PGND
and SW pins. The maximum sense voltage is set by the
voltage applied to the VRNG pin and is equal to approxi-
mately(0.13)VRNGforsourcingcurrentand(0.17)VRNG for
sinking current. The current mode control loop will not
allow the inductor current valleys to exceed (0.13)VRNG
RSENSE for sourcing and (0.17)VRNG/RSENSE for sinking. In
practice, one should allow some margin for variations in
sn3717 3717fs
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LTC3717
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U
the LTC3717 and external component values and a good
guide for selecting the sense resistance is:
the load current. During LTC3717’s normal operation, the
duty cycles for the MOSFETs are:
VRNG
10•IOUT(MAX)
VOUT
RSENSE
=
DTOP
DBOT
=
=
V
IN
V – VOUT
IN
AnexternalresistivedividerfromINTVCC canbeusedtoset
the voltage of the VRNG pin between 0.5V and 2V resulting
innominalsensevoltagesof50mVto200mV.Additionally,
the VRNG pin can be tied to SGND or INTVCC in which case
the nominal sense voltage defaults to 70mV or 140mV,
respectively. The maximum allowed sense voltage is about
1.3timesthisnominalvalueforpositiveoutputcurrentand
1.7 times the nominal value for negative output current.
V
IN
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
P
TOP = DTOP IOUT(MAX)
2 ρT(TOP) RDS(ON)(MAX)
2
+ k VIN IOUT(MAX) CRSS
f
PBOT = DBOT OUT(MAX)
I
2 ρT(BOT) RDS(ON)(MAX)
Power MOSFET Selection
Both MOSFETs have I2R losses and the top MOSFET
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottomMOSFETlossesaregreatestwhenthebottomduty
cycle is near 100%, during a short-circuit or at high input
voltage.
TheLTC3717requirestwoexternalN-channelpowerMOS-
FETs, one for the top (main) switch and one for the bottom
(synchronous)switch.Importantparametersforthepower
MOSFETs are the breakdown voltage V(BR)DSS, threshold
voltage V(GS)TH, on-resistance RDS(ON), reverse transfer
capacitance CRSS and maximum current IDS(MAX)
.
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3717 applications. If the input voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered.
2.0
1.5
1.0
0.5
0
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-
resistance. MOSFET on-resistance is typically specified
with a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
3717 F02
RSENSE
Figure 2. RDS(ON) vs. Temperature
RDS(ON)(MAX)
=
ρT
Operating Frequency
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum junction temperature of 100°C,
using a value ρT = 1.3 is reasonable.
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improvesefficiencybyreducingMOSFETswitchinglosses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
TheoperatingfrequencyofLTC3717applicationsisdeter-
mined implicitly by the one-shot timer that controls the
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APPLICATIO S I FOR ATIO
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin according to:
(0.7V)
tON
=
(10pF)
I
ION
VOUT
f ∆IL(MAX)
VOUT
V
IN(MAX)
L =
1−
Tying a resistor RON from VIN to the ION pin yields an on-
time inversely proportional to VIN. For a step-down con-
verter, this results in approximately constant frequency
operation as the input supply varies:
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot af-
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
orKoolMµ® cores.Avarietyofinductorsdesignedforhigh
current, lowvoltageapplicationsareavailablefrommanu-
facturerssuchasSumida,Panasonic,Coiltronics,Coilcraft
and Toko.
VOUT
(0.7V) RON(10pF)
f =
[HZ]
Because the voltage at the ION pin is about 0.7V, the
currentintothispinisnotexactlyinverselyproportionalto
VIN, especially in applications with lower input voltages.
A more exact equation taking in account the 0.7V drop on
the ION pin is:
Schottky Diode D1 Selection
The Schottky diode D1 shown in Figure 1 conducts during
the dead time between the conduction of the power
MOSFET switches. It is intended to prevent the body diode
ofthebottomMOSFETfromturningonandstoringcharge
during the dead time, which can cause a modest (about
1%) efficiency loss. The diode can be rated for about one
half to one fifth of the full load current since it is on for only
a fraction of the duty cycle. In order for the diode to
be effective, the inductance between it and the bottom
MOSFET must be as small as possible, mandating that
these components be placed adjacently. The diode can be
omitted if the efficiency loss is tolerable.
VOUT (V – 0.7V)
IN
f =
[HZ]
(0.7V) RON(10pF)V
IN
To correct for this error, an additional resistor RON2
connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.
5V
0.7V
RON2
=
RON
Inductor Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
CIN and COUT Selection
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
VOUT
f L
VOUT
V
IN
∆IL =
1−
VOUT
V
IN
V
IN
VOUT
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
IRMS IOUT(MAX)
– 1
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX)/2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
A reasonable starting point is to choose a ripple current
Kool Mµ is a registered trademark of Magnetics, Inc.
sn3717 3717fs
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U
current ratings from capacitor manufacturers are often
basedononly2000hoursoflifewhichmakesitadvisable
to derate the capacitor.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
topMOSFET. Inmostapplications0.1µFto0.47µF, X5Ror
X7R dielectric capacitor is adequate.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step
transients. The output ripple ∆VOUT is approximately
bounded by:
Fault Condition: Current Limit
1
∆VOUT ≤ ∆IL ESR +
8fCOUT
The maximum inductor current is inherently limited in a
currentmodecontrollerbythemaximumsensevoltage.In
the LTC3717, the maximum sense voltage is controlled by
the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limits are:
Since ∆IL increases with input voltage, the output ripple is
highestatmaximuminputvoltage.Typically,oncetheESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESRcharacteristicsbutcanhaveahighvoltagecoefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to signifi-
cant ringing. When used as input capacitors, care must be
taken to ensure that ringing from inrush currents and
switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recom-
mended to reduce the effect of their lead inductance.
VSNS(MAX)
RDS(ON) ρT
1
ILIMIT POSITIVE =
ILIMIT NEGATIVE =
+ ∆IL
2
VSNS(MIN)
RDS(ON) ρT
1
– ∆IL
2
The current limit value should be checked to ensure that
ILIMIT(MIN) >IOUT(MAX).Theminimumvalueofcurrentlimit
generally occurs with the largest VIN at the highest ambi-
ent temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET on-
resistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same amount below the typical value as the maximum
liesaboveit.ConsulttheMOSFETmanufacturerforfurther
guidelines.
Top MOSFET Driver Supply (CB, DB)
Minimum Off-time and Dropout Operation
AnexternalbootstrapcapacitorCBconnectedtotheBOOST
pinsuppliesthegatedrivevoltageforthetopsideMOSFET.
The minimum off-time tOFF(MIN) is the smallest amount of
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APPLICATIO S I FOR ATIO
time that the LTC3717 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 300ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON +tOFF(MIN)).Ifthemaximumdutycycleisreached,
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
1. EXTVCC grounded. INTVCC is always powered from the
internal 5V regulator.
2. EXTVCC connected to an external supply. A high effi-
ciency supply compatible with the MOSFET gate drive
requirements (typically 5V) can improve overall
efficiency.
3. EXTVCC connected to an output derived boost network.
The low voltage output can be boosted using a charge
pump or flyback winding to greater than 4.7V. The system
will start-up using the internal linear regulator until the
boosted output supply is available.
t
ON + tOFF(MIN)
V
= VOUT
IN(MIN)
tON
INTVCC Regulator
External Gate Drive Buffers
An internal P-channel low dropout regulator produces the
5V supply that powers the drivers and internal circuitry
within the LTC3717. The INTVCC pin can supply up to
50mA RMS and must be bypassed to ground with a
minimum of 4.7µF tantalum or other low ESR capacitor.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate drivers. Applica-
tions using large MOSFETs with a high input voltage and
high frequency of operation may cause the LTC3717 to
exceed its maximum junction temperature rating or RMS
current rating. Most of the supply current drives the
MOSFET gates unless an external EXTVCC source is used.
The LTC3717 drivers are adequate for driving up to about
60nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
fromusingexternalgatedrivebufferssuchastheLTC1693.
Alternately, the external buffer circuit shown in Figure 4
can be used. Note that the bipolar devices reduce the
signal swing at the MOSFET gate, and benefit from an
increased EXTVCC voltage of about 6V.
BOOST
INTV
CC
Q1
Q3
FMMT619
In continuous mode operation, this current is IGATECHG
=
FMMT619
GATE
OF M1
10Ω
10Ω
f(Qg(TOP) + Qg(BOT)). The junction temperature can be
estimated from the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3717CGN
is limited to less than 14mA from a 30V supply:
GATE
OF M2
TG
BG
Q2
Q4
FMMT720
FMMT720
SW
PGND
3717 F04
TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C
Figure 4. Optional External Gate Driver
Forlargercurrents, considerusinganexternalsupplywith
the EXTVCC pin.
Soft-Start and Latchoff with the RUN/SS Pin
The RUN/SS pin provides a means to shut down the
LTC3717 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3717 into a low quiescent current shutdown (IQ <
30µA). Releasing the pin allows an internal 1.2µA current
source to charge up the external timing capacitor CSS. If
RUN/SS has been pulled all the way to ground, there is a
delay before starting of about:
EXTVCC Connection
The EXTVCC pin can be used to provide MOSFET gate drive
and control power from the output or another external
source during normal operation. Whenever the EXTVCC
pin is above 4.7V the internal 5V regulator is shut off and
an internal 50mA P-channel switch connects the EXTVCC
pintoINTVCC.INTVCC powerissuppliedfromEXTVCC until
this pin drops below 4.5V. Do not apply more than 7V to
theEXTVCC pinandensurethatEXTVCC ≤ VCC. Thefollow-
ing list summarizes the possible connections for EXTVCC:
1.5V
1.2µA
tDELAY
=
CSS = 1.3s/µF C
SS
(
)
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INTV
CC
When the voltage on RUN/SS reaches 1.5V, the LTC3717
begins operating with a clamp on ITH of approximately
0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF. The pin can be driven from logic as
shown in Figure 5. Diode D1 reduces the start delay while
allowing CSS to charge up slowly for the soft-start func-
tion.
R
*
SS
V
IN
RUN/SS
3.3V OR 5V
RUN/SS
*
D2*
R
SS
D1
2N7002
C
SS
C
SS
3717 F06
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA cur-
rent then begins discharging CSS. If the fault condition
persists until the RUN/SS pin drops to 3.5V, then the con-
troller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.
(5a)
(5b)
Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3717 circuits:
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
resistanceofoneMOSFETcansimplybesummedwiththe
resistances of L and the board traces to obtain the DC I2R
loss.Forexample,ifRDS(ON) =0.01ΩandRL =0.005Ω,the
loss will range from 15mW to 1.5W as the output current
varies from 1A to 10A.
The overcurrent protection timer requires that the soft-
start timing capacitor CSS be made large enough to guar-
antee that the output is in regulation by the time CSS has
reachedthe4Vthreshold.Ingeneral,thiswilldependupon
the size of the output capacitance, output voltage and load
currentcharacteristic.Aminimumsoft-startcapacitorcan
be estimated from:
CSS > COUT VOUT RSENSE (10–4 [F/V s])
Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or
desired. The feature can be overridden by adding a pull-
up current greater than 5µA to the RUN/SS pin. The
additional current prevents the discharge of CSS during a
fault and also shortens the soft-start period. Using a
resistortoVIN asshowninFigure5aissimple, butslightly
increases shutdown current. Connecting a resistor to
INTVCC as shown in Figure 5b eliminates the additional
shutdowncurrent,butrequiresadiodetoisolateCSS .Any
pull-up network must be able to pull RUN/SS above the
4.5V maximum threshold that arms the latchoff circuit
and overcome the 4µA maximum discharge current.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capaci-
tance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Transition Loss (1.7A–1) VIN IOUT CRSS
f
2
3. INTVCC current. This is the sum of the MOSFET driver
and control currents. This loss can be reduced by supply-
ing INTVCC current through the EXTVCC pin from a high
sn3717 3717fs
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APPLICATIO S I FOR ATIO
efficiency source, such as an output derived boost net-
work or alternate supply if available.
1.25V
(250kHz)(0.4)(10A)
1.25V
2.5V
L =
1−
= 0.63µH
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Selectingastandardvalueof0.68µHresultsinamaximum
ripple current of:
1.25V
(250kHz)(0.68µH)
1.25V
2.5V
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
∆IL =
1–
= 3.7A
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (RDS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
θJA = 40°C/W) yields a nominal sense voltage of:
When making adjustments to improve efficiency, the
input current is the best indicator of changes in efficiency.
Ifyoumakeachangeandtheinputcurrentdecreases,then
the efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
VSNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV
TyingVRNG to1.1V willsetthecurrentsensevoltagerange
for a nominal value of 110mV with current limit occurring
at 143mV. To check if the current limit is acceptable,
assume a junction temperature of about 40°C above a
70°C ambient with ρ110°C = 1.4:
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
dischargeCOUT generatingafeedbackerrorsignalusedby
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The ITH pin external components shown in Figure 6
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Application Note 76.
143mV
1
ILIMIT
≥
+ (3.7A) = 12.1A
(1.4)(0.010Ω) 2
and double check the assumed TJ in the MOSFET:
2.5V –1.25V
PBOT
=
(12.1A)2(1.4)(0.010Ω) = 1.02W
2.5V
TJ = 70°C + (1.02W)(40°C/W) = 111°C
Because the top MOSFET is on roughly the same amount
of time as the bottom MOSFET, the same Si4874 can be
used as the synchronous MOSFET.
Design Example
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
As a design example, take a supply with the following
specifications: VIN = VREF = 2.5V, VEXTVCC = 5V, VOUT
=
1.25V ±5%, IOUT(MAX) = 10A, f = 250kHz. First, calculate
the timing resistor with VON = VOUT
:
CIN is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of
0.013Ω to minimize output voltage changes due to induc-
tor ripple current and load steps. For current sinking
applicationswherecurrentflowsbacktotheinputthrough
the top transistor, outputcapacitors with asimilar amount
1.25V(2.5V – 0.7V)
(0.7V)(250kHz)(10pF)2.5V
RON
=
= 514kΩ
and choose the inductor for about 40% ripple current at
the maximum VIN:
of bulk C and ESR should be placed on the input as well.
sn3717 3717fs
14
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• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
(This is typically the case, since VIN is derived from
another DC/DC converter.) The ripple voltage will be only:
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (4A) (0.013Ω) = 52mV
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compactarea.Itmayhelptohavesomecomponentson
the bottom side of the board.
However, a 0A to 10A load step will cause an output
change of up to:
• Place LTC3717 chip with pins 9 to 16 facing the power
components. Keep the components connected to pins
1 to 8 close to LTC3717 (noise sensitive components).
∆VOUT(STEP) =∆ILOAD (ESR)=(10A)(0.013Ω)=130mV
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 6.
•
Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3717.
Use several bigger vias for power components.
PC Board Layout Checklist
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
When laying out a PC board follow one of the two sug-
gested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
C
SS
D
B
0.1µF
CMDSH-3
LTC3717
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
V
= 2.5V
RUN/SS BOOST
IN
C
C
IN
+
IN
R3
R
R4
C
PG
B
D2
22µF
6.3V
X7R
180µF
4V
11k
C
100k
39k
0.22µF
M1
B320A
PGOOD
TG
SW
Si4874
×2
OUT
1.25V
L1
0.68µH
V
±10A
RNG
C1
C
C
OUT3
R
C
20k
OUT1-2
470pF
+
270µF
2V
22µF
6.3V
X7R
M2
Si4874
D1
B320A
I
PGND
BG
TH
×2
C
C2
100pF
SGND
C
VCC
C
0.01µF
ON
+
4.7µF
I
INTV
ON
CC
CC
CC
R
F
1Ω
V
V
V
5V
FB
EXT
C
F
0.1µF
V
EXTV
REF
(OPT)
0.1µF
R
ON
511k
10Ω
3717 F06a
C
, C
: CORNELL DUBILIER ESRE181E04B
IN OUT1-2
L1: SUMIDA CEP125-0R68MC-H
Figure 6. Design Example: 1.25V/±10A at 250kHz
sn3717 3717fs
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• Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
powercomponent.Youcanconnectthecopperareasto
any DC net (VIN, VOUT, GND or to any other DC rail in
your system).
• Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC cur-
rent.
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller. These items are also illustrated in
Figure 7.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and PGND pins.
• Connect the top driver boost capacitor CB closely to the
BOOST and SW pins.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
onepointwhichisthentiedtothePGNDpinclosetothe
source of M2.
• Connect the VCC pin decoupling capacitor CF closely to
the VCC and PGND pins.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
C
C
B
SS
LTC3717
L
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RUN/SS BOOST
PGOOD
TG
SW
D
B
V
+
RNG
M1
C
C1
R
C
I
PGND
BG
TH
V
IN
D2
D1
C
C2
C
M2
SGND
IN
C
C
ION
VCC
–
–
+
I
INTV
ON
CC
CC
CC
C
FB
V
C
OUT
OUT
C
V
V
V
F
FB
R
F
EXTV
REF
R
ON
3717F07
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 7. LTC3717 Layout Diagram
sn3717 3717fs
16
LTC3717
U
TYPICAL APPLICATIO S
1.5V/±10A at 300kHz from 5V to 28V Input
C
SS
D
B
0.1µF
CMDSH-3
LTC3717
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
IN
RUN/SS BOOST
5V TO 28V
C
IN
R
R
R
C
PG
R1
R2
39k
B
10µF
35V
×3
100k
11k
0.22µF
B320A
L1
M1
PGOOD
TG
SW
IRF7811W
V
OUT
1.5V
V
±10A
RNG
C
C1
1.2µH
C
OUT
R
C
20k
680pF
+
270µF
2V
M2
IRF7822
D1
B320A
I
PGND
BG
TH
×2
C
C2
100pF
SGND
C
VCC
C 0.01µF
ON
4.7µF
I
INTV
ON
CC
CC
CC
V
V
V
FB
EXTV
V
3V
REF
REF
10µF
6.3V
X7R
R
ON
510k
3717 TA01
C
: CORNELL DUBILIER ESRE271M02B
OUT
sn3717 3717fs
17
LTC3717
TYPICAL APPLICATIO S
U
High Voltage Half (VIN) Power Supply
C
SS
0.1µF
D
B
CMDSH-3
LTC3717
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
IN
RUN/SS BOOST
5V TO 25V
C
R
IN
C
PG
B
10µF
25V
×2
100k
0.22µF
M1
PGOOD
TG
SW
FDS6680S
V
V
±6A
OUT
IN
/2
L1
1.8µH
V
RNG
C
C1
470pF
R
C
20k
+
C
C
OUT2
OUT1
270µF
10µF
M2
FDS6680S
I
PGND
BG
TH
16V
15V
C
C2
100pF
SGND
C
VCC
4.7µF
C
0.01µF
ON
I
INTV
ON
CC
CC
CC
R
1Ω
F
V
V
V
FB
C
F
0.1µF
EXTV
REF
R
ON
510k
R2
1M
R1 2M
C2
2200pF
3717 TA02
C
C
C
: TAIYO YUDEN TMK432BJ106MM
IN
: SANYO, OS-CON 16SP270
OUT1
OUT2
: TAIYO YUDEN JMK316BJ106ML
L1: TOKO 919AS-1R8N
sn3717 3717fs
18
LTC3717
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
sn3717 3717fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.
19
LTC3717
U
TYPICAL APPLICATIO
Typical Application 1.25V/±3A at 1.4MHz
C
SS
D
B
0.1µF
CMDSH-3
LTC3717
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
IN
RUN/SS BOOST
2.5V
+
+
R
C
PG
C
B
IN
100k
0.22µF
120µF
M1
L1
0.7µH
PGOOD
TG
SW
4V
1/2 Si9802
V
OUT
1.25V
V
RNG
±3A
C
C1
470pF
R
C
C
OUT
33k
120µF
M2
1/2 Si9802
I
PGND
BG
TH
4V
C
C2
100pF
SGND
C
VCC
C
, 0.01µF
ON
4.7µF
I
INTV
ON
CC
CC
CC
V
V
V
5V
FB
EXTV
REF
1µF
R
ON
92k
3717 TA03
C
, C : CORNELL DUBILIER ESRD121M04B
IN OUT
L1: TOKO A921CY-0R7M
RELATED PARTS
PART NUMBER
LTC1625/LTC1775
LTC1628-PG
DESCRIPTION
No R
TM Current Mode Synchronous Step-Down Controller
COMMENTS
97% Efficiency; No Sense Resistor; 99% Duty Cycle
SENSE
Dual, 2-Phase Synchronous Step-Down Controller
Power Good Output; Minimum Input/Output Capacitors;
3.5V ≤ V ≤ 36V
IN
LTC1628-SYNC
LTC1709-7
Dual, 2-Phase Synchronous Step-Down Controller
Synchronizable 150kHz to 300kHz
High Efficiency, 2-Phase Synchronous Step-Down Controller
with 5-Bit VID
Up to 42A Output; 0.925V ≤ V
≤ 2V
OUT
LTC1709-8
LTC1735
High Efficiency, 2-Phase Synchronous Step-Down Controller
High Efficiency, Synchronous Step-Down Controller
Up to 42A Output; VRM 8.4; 1.3V ≤ V
Burst ModeTM Operation; 16-Pin Narrow SSOP;
≤ 3.5V
OUT
3.5V ≤ V ≤ 36V
IN
LTC1736
LTC1772
LTC1773
High Efficiency, Synchronous Step-Down Controller with 5-Bit VID
SOT-23 Step-Down Controller
Mobile VID; 0.925V ≤ V
≤ 2V; 3.5V ≤ V ≤ 36V
OUT IN
Current Mode; 550kHz; Very Small Solution Size
Up to 95% Efficiency, 550kHz, 2.65V ≤ V ≤ 8.5V,
Synchronous Step-Down Controller
IN
0.8V ≤ V
≤ V , Synchronizable to 750kHz
OUT
IN
LTC1778/LTC3778
Wide Operating Range, No R
Dual, Step-Down Controller
Step-Down Synchronous Controllers 4V ≤ V ≤ 36V, True Current Mode Control,
SENSE
IN
2% to 90% Duty Cycle
LTC1874
LTC1876
Current Mode; 550kHz; Small 16-Pin SSOP, V < 9.8V
IN
2-Phase, Dual Synchronous Step-Down Controller with
Step-Up Regulator
2.6V ≤ V ≤ 36V, Power Good Output,
IN
300kHz Operation
LTC3413
Monolithic DDR Memory Termination Regulator
90% Efficiency, ±3A Output, 2MHz Operation
Burst Mode is a registered trademark of Linear Technology Corporation.
sn3717 3717fs
LT/TP 0103 2K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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