LTC3728LCGN#PBF_技术文档

LTC3728L/LTC3728LX

Dual, 550kHz, 2-Phase

Synchronous Regulators

FeaTures

DescripTion

Dual, 180° Phased Controllers Reduce Required

The LTC^®3728L/LTC3728LX are dual high performance

step-down switching regulator controllers that drive all

N-channelsynchronouspowerMOSFETstages.Aconstant-

frequency,currentmodearchitectureallowsphase-lockable

frequency of up to 550kHz. Power loss and noise due to

theESRoftheinputcapacitorsareminimizedbyoperating

the two controller output stages out of phase.

n

Input Capacitance and Power Supply Induced Noise

OPTI-LOOP^®Compensation Minimizes C

n

OUT

n

1ꢀ Output Voltage Accuracy (LTC3728LC)

n

Power Good Output Voltage Indicator

n

Phase-Lockable Fixed Frequency 250kHz to 550kHz

n

Dual N-Channel MOSFET Synchronous Drive

n

Wide V Range: 4.5V to 28V Operation

IN

OPTI-LOOPcompensationallowsthetransientresponseto

be optimized over a wide range of output capacitance and

ESR values. The precision 0.8V reference and power good

output indicator are compatible with future microproces-

sor generations, and a wide 4.5V to 28V (30V maximum)

input supply range encompasses all battery chemistries.

n

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Soft-Start Current Ramping

Foldback Output Current Limiting

Latched Short-Circuit Shutdown with Defeat Option

Output Overvoltage Protection

Low Shutdown I : 20µA

5V and 3.3V Standby Regulators

3 Selectable Operating Modes: Constant-Frequency,

Burst Mode^®Operation and PWM

5mm × 5mm QFN and 28-Lead Narrow SSOP

Packages

Q

A RUN/SS pin for each controller provides both soft-

start and optional timed, short-circuit shutdown. Current

foldback limits MOSFET dissipation during short-circuit

conditions when overcurrent latchoff is disabled. Output

overvoltage protection circuitry latches on the bottom

n

MOSFET until V

returns to normal. The FCB mode

OUT

pin can select among Burst Mode, constant-frequency

mode and continuous inductor current mode or regulate

a secondary winding. The LTC3728L/LTC3728LX include

a power good output pin that indicates when both outputs

are within 7.5% of their designed set point.

applicaTions

n

Notebook and Palmtop Computers

n

Telecom Systems

n

Portable Instruments

n

Battery-Operated Digital Devices

L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, OPTI-LOOP and PolyPhase

are registered trademarks of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

n

DC Power Distribution Systems

Typical applicaTion

V

IN

5.2V TO 28V

C

22µF

50V

IN

1µF

CERAMIC

+

4.7µF

D3

D4

V

PGOOD INTV

IN

CC

CERAMIC

M1

M2

TG1

TG2

L1

3.2µH

L2

3.2µH

BOOST1

SW1

BOOST2

SW2

C

, 0.1µF

C

B2

, 0.1µF

B1

LTC3728L/

LTC3728LX

BG1

BG2

D1

D2

f

IN

500kHz

PLLIN

PGND

+

SENSE1

SENSE2

R

SENSE2

0.01Ω

SENSE1

1000pF

0.01Ω

–

SENSE1

V

SENSE2

V

3.3V

5A

OSENSE1

TH1

OSENSE2

V

OUT2

OUT1

5V

5A

R2

105k

1%

R4

63.4k

1%

I

TH2

C

C2

C1

220pF

C

47µF

6V

C

56µF

6V

RUN/SS1 SGND RUN/SS2

OUT1

OUT

220pF

R

C2

+

R1

20k

1%

R3

20k

1%

R

C1

C

SS2

0.1µF

SS1

0.1µF

15k

SP

M1, M2: FDS6982S

3728 F01

Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter

3728lxff

1

LTC3728L/LTC3728LX

(Note 1)

absoluTe MaxiMuM raTings

Input Supply Voltage (V )........................ 30V to –0.3V

I

, V

Voltages ... 2.7V to –0.3V

IN

TH1, TH2 OSENSE1 OSENSE2

Peak Output Current <10µs (TG1, TG2, BG1, BG2).... 3A

Topside Driver Voltages

(BOOST1, BOOST2).............................. 36V to –0.3V

Switch Voltage (SW1, SW2) ........................ 30V to –5V

INTV Peak Output Current ................................. 40mA

Operating Temperature Range (Note 7)

CC

INTV EXTV , RUN/SS1, RUN/SS2,

LTC3728LC/LTC3728LXC........................ 0°C to 85°C

LTC3728LE/LTC3728LI........................ –40°C to 85°C

Junction Temperature (Note 2) ............................ 125°C

Storage Temperature Range.................. –65°C to 125°C

Reﬂow Peak Body Temperature (UH Package)..... 260°C

Lead Temperature (Soldering, 10 sec)

CC,

CC

(BOOST1-SW1), (BOOST2-SW2), PGOOD .... 7V to –0.3V

+

–

+

–

SENSE1 , SENSE2 , SENSE1 ,

SENSE2 Voltages ........................ (1.1)INTV to –0.3V

CC

PLLIN, PLLFLTR, FCB Voltages............ INTV to –0.3V

(GN Package)....................................................300°C

pin conFiguraTion

TOP VIEW

1

2

PGOOD

TG1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS1

+

SENSE1

32 31 30 29 28 27 26 25

–

3

SW1

SENSE1

V

1

2

3

4

5

6

7

8

24 BOOST1

OSENSE1

4

BOOST1

V

OSENSE1

PLLFLTR

PLLIN

FCB

23

22

21

V

IN

5

V

PLLFLTR

PLLIN

FCB

IN

BG1

6

BG1

EXTV

CC

7

EXTV

CC

33

I

20 INTV

TH1

CC

8

INTV

CC

I

TH1

SGND

3.3V

PGND

19

9

PGND

BG2

SGND

18 BG2

OUT

10

11

12

13

14

3.3V

OUT

I

17 BOOST2

TH2

BOOST2

SW2

I

TH2

9

10 11 12 13 14 15 16

V

OSENSE2

–

TG2

SENSE2

+

RUN/SS2

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

GN PACKAGE

28-LEAD NARROW PLASTIC SSOP

T

JMAX

= 125°C, θ = 34°C/W

JA

T

JMAX

= 125°C, θ = 95°C/W

JA

EXPOSED PAD IS SGND (PIN 33), MUST BE SOLDERED TO PCB

3728lxff

2

LTC3728L/LTC3728LX

orDer inForMaTion

LEAD FREE FINISH

LTC3728LCGN#PBF

LTC3728LEGN#PBF

LTC3728LIGN#PBF

LTC3728LCUH#PBF

LTC3728LEUH#PBF

LTC3728LIUH#PBF

LTC3728LXCUH#PBF

LEAD BASED FINISH

LTC3728LCGN

TAPE AND REEL

PART MARKING

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 85°C

LTC3728LCGN#TRPBF

LTC3728LEGN#TRPBF

LTC3728LIGN#TRPBF

LTC3728LCUH#TRPBF

LTC3728LEUH#TRPBF

LTC3728LIUH#TRPBF

LTC3728LXCUH#TRPBF

TAPE AND REEL

28-Lead Narrow Plastic SSOP

32-Lead (5mm × 5mm) Plastic QFN

PACKAGE DESCRIPTION

–40°C to 85°C

0°C to 85°C

3728L

3728LE

–40°C to 85°C

0°C to 85°C

3728LI

3728LX

PART MARKING

TEMPERATURE RANGE

0°C to 85°C

LTC3728LCGN#TR

LTC3728LEGN#TR

LTC3728LIGN#TR

28-Lead Narrow Plastic SSOP

32-Lead (5mm × 5mm) Plastic QFN

LTC3728LEGN

–40°C to 85°C

0°C to 85°C

LTC3728LIGN

LTC3728LCUH

LTC3728LCUH#TR

LTC3728LEUH#TR

LTC3728LIUH#TR

3728L

LTC3728LEUH

3728LE

3728LI

3728LX

–40°C to 85°C

0°C to 85°C

LTC3728LIUH

LTC3728LXCUH

LTC3728LXCUH#TR

Consult LTC Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3728lxff

3

LTC3728L/LTC3728LX

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_{RUN/SS1, 2}= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loops

V

Regulated Feedback Voltage

(Note 3); I

Voltage = 1.2V (LTC3728LC)

Voltage = 1.2V

●

0.792 0.800 0.808

0.788 0.800 0.812

V

OSENSE1, 2

TH1, 2

(LTC3728LE/LTC3728LX/LTC3728LI)

I

Feedback Current

(Note 3)

–5

–50

nA

VOSENSE1, 2

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 3.6V to 30V (Note 3)

0.002

0.02

%/V

REFLNREG

LOADREG

IN

(Note 3)

Measured in Servo Loop; ΔI Voltage = 1.2V to 0.7V

Measured in Servo Loop; ΔI Voltage = 1.2V to 2.0V

●

0.1

–0.1

0.5

–0.5

%

TH

g

Transconductance Amplifier g

I

= 1.2V; Sink/Source 5µA (Note 3)

= 1.2V (Note 8)

1.3

3

mmho

MHz

m1, 2

m

TH1, 2

Transconductance Amplifier GBW

mGBW1, 2

I

Q

Input DC Supply Current

Normal Mode

(Note 4)

IN

RUN/SS1, 2

V

= 15V; EXTV Tied to V ; V = 5V

450

20

µA

CC

OUT1 OUT1

Shutdown

= 0V

35

V

Forced Continuous Threshold

Forced Continuous Pin Current

●

0.76 0.800

–0.50 –0.18

4.3

0.84

–0.1

4.8

V

µA

V

FCB

I

V

= 0.85V

FCB

V

Burst Inhibit (Constant-Frequency)

Threshold

Measured at FCB Pin

BINHIBIT

UVLO

Undervoltage Lockout

Feedback Overvoltage Lockout

Sense Pins Total Source Current

Maximum Duty Factor

V

Ramping Down

●

3.5

4

V

IN

V

Measured at V

0.84

–90

98

0.86

–60

99.4

1.2

0.88

OVL

OSENSE1, 2

I

(Each Channel); V

In Dropout

–

– = V + + = 0V

SENSE1 , 2

µA

%

µA

V

SENSE

SENSE1 , 2

DF

MAX

I

Soft-Start Charge Current

V

= 1.9V

0.5

1.0

RUN/SS1, 2

V

ON RUN/SS Pin ON Threshold

V Rising

RUN/SS1, RUN/SS2

1.5

2.0

RUN/SS1, 2

LT RUN/SS Pin Latchoff Arming

Threshold

V

Rising from 3V

4.1

4.75

V

RUN/SS1, RUN/SS2

I

RUN/SS Discharge Current

Soft-Short Condition V

RUN/SS1, 2

= 0.5V;

0.5

2

4

5

µA

SCL1, 2

OSENSE1, 2

V

= 4.5V

Shutdown Latch Disable Current

Maximum Current Sense Threshold

V

= 0.5V

1.6

SDLHO

OSENSE1, 2

V

= 0.7V, V

–

= 5V

65

62

75

85

88

mV

SENSE(MAX)

OSENSE1, 2

SENSE1 , 2

–

●

TG Transition Time:

Rise Time

Fall Time

(Note 5)

TG1, 2 t

C

= 3300pF

55

100

ns

r

f

LOAD

= 3300pF

BG Transition Time:

Rise Time

Fall Time

(Note 5)

LOAD

BG1, 2 t

C

= 3300pF

45

100

90

ns

r

f

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

1D

C

= 3300pF Each Driver

80

ns

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

2D

80

ns

LOAD

t

Minimum On-Time

Tested with a Square Wave (Note 6)

100

ON(MIN)

3728lxff

4

LTC3728L/LTC3728LX

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 15V, V_{RUN/SS1, 2}= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

INTV Linear Regulator

CC

INTVCC

V

Internal V Voltage

6V < V < 30V, V = 4V

EXTVCC

4.8

5.0

0.2

100

4.7

0.2

5.2

2.0

200

V

%

CC

IN

INT

INTV Load Regulation

I

= 0 to 20mA, V

= 4V

EXTVCC

LDO

CC

EXT

EXTV Voltage Drop

= 20mA, V

= 5V

EXTVCC

mV

V

CC

EXTV Switchover Voltage

= 20mA, EXTV Ramping Positive

●

4.5

EXTVCC

LDOHYS

CC

EXTV Hysteresis

V

CC

Oscillator and Phase-Locked Loop

f

Nominal Frequency

Lowest Frequency

Highest Frequency

PLLIN Input Resistance

V

= 1.2V

= 0V

360

230

480

400

260

550

50

440

290

590

kHz

kΩ

NOM

LOW

HIGH

PLLFLTR

≥ 2.4V

R

PLLIN

I

Phase Detector Output Current

Sinking Capability

Sourcing Capability

PLLFLTR

f

< f

> f

–15

15

µA

PLLIN

OSC

3.3V Linear Regulator

V

3.3V Regulator Output Voltage

3.3V Regulator Load Regulation

3.3V Regulator Line Regulation

No Load

= 0 to 10mA

●

3.2

3.35

0.5

3.45

2

V

%

3.3OUT

3.3IL

I

3.3

6V < V < 30V

0.05

0.2

3.3VL

IN

PGOOD Output

V

PGOOD Voltage Low

I

= 2mA

= 5V

0.1

0.3

1

V

PGL

PGOOD

I

PGOOD Leakage Current

PGOOD Trip Level, Either Controller

V

µA

PGOOD

V

with Respect to Set Output Voltage

Ramping Negative

Ramping Positive

PG

OSENSE

V

–6

6

–7.5

7.5

–9.5

9.5

%

OSENSE

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 6: The minimum on-time is tested under an ideal condition without

external power FETs. It can be larger when the IC is operating in an

actual circuit. See Minimum On-Time Considerations in the Applications

Information section.

Note 2: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formulas:

D

LTC3728LUH/LTC3728LXUH: T = T + (P • 34°C/W)

Note 7: The LTC3728LC/LTC3728LXC are guaranteed to meet performance

speciﬁcations from 0°C to 85°C. The LTC3728LE is guaranteed to meet

performance speciﬁcations over the –40°C to 85°C operating temperature

range as assured by design, characterization and correlation with statistical

process controls. The LTC3728LI is guaranteed to meet performance

speciﬁcations over the –40°C to 85°C operating temperature range.

J

A

D

LTC3728LGN: T = T + (P • 95°C/W)

J

A

D

Note 3: The IC is tested in a feedback loop that servos V

to a

ITH1, 2

OSENSE1, 2.

speciﬁed voltage and measures the resultant V

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See the Applications Information

section.

Note 8: Guaranteed by design.

3728lxff

5

LTC3728L/LTC3728LX

Typical perForMance characTerisTics

Efficiency vs Output Current

and Mode (Figure 13)

Efficiency vs Output Current

(Figure 13)

Efficiency vs Input Voltage

(Figure 13)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

100

90

80

70

60

50

Burst Mode

OPERATION

V

= 7V

IN

V

= 10V

IN

FORCED

CONTINUOUS

MODE (PWM)

V

IN

= 15V

V

= 20V

IN

CONSTANT

FREQUENCY

(BURST DISABLE)

V

= 15V

= 5V

V

I

= 5V

= 3A

IN

OUT

V

= 5V

OUT

V

f = 250kHz

0.001

0.01

0.1

1

10

0.1

OUTPUT CURRENT (A)

0.001

0.01

1

5

15

25

INPUT VOLTAGE (V)

35

10

OUTPUT CURRENT (A)

3728L G01

3728L G02

3728L G03

Supply Current vs Input Voltage

and Mode (Figure 13)

INTV_CCand EXTV_CCSwitch

Voltage vs Temperature

EXTV_CCVoltage Drop

200

150

100

50

1000

800

600

400

200

0

5.05

5.00

4.95

4.90

4.85

4.80

4.75

4.70

INTV VOLTAGE

CC

BOTH

CONTROLLERS ON

EXTV SWITCHOVER THRESHOLD

CC

SHUTDOWN

0

10

20

30

40

50

TEMPERATURE (°C)

100 125

20

25

–50 –25

0

25

75

0

5

10

15

30

INPUT VOLTAGE (V)

CURRENT (mA)

3728L G05

3728L G06

3728L G04

Maximum Current Sense

Threshold vs Percent of Nominal

Output Voltage (Foldback)

Maximum Current Sense

Threshold vs Duty Factor

Internal 5V LDO Line Regulation

5.1

5.0

75

50

25

0

80

70

60

50

40

30

20

10

0

I

= 1mA

LOAD

4.9

4.8

4.7

4.6

4.5

4.4

20

INPUT VOLTAGE (V)

30

0

5

10

15

25

0

20

40

60

80

100

50

0

25

75

100

DUTY FACTOR (%)

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

3728L G07

3728L G08

3728L G09

3728lxff

6

LTC3728L/LTC3728LX

Typical perForMance characTerisTics

Maximum Current Sense Threshold

vs V_RUN/SS(Soft-Start)

Maximum Current Sense Threshold

vs Sense Common Mode Voltage

Current Sense Threshold

vs I_THVoltage

90

80

76

72

68

64

60

80

60

40

20

V

= 1.6V

SENSE(CM)

70

60

50

40

30

20

10

0

–10

–20

–30

0

1

2

3

4

5

0

0.5

1

1.5

(V)

2

2.5

0

1

2

3

4

5

6

V

(V)

COMMON MODE VOLTAGE (V)

V

ITH

RUN/SS

3728L G11

3728L G12

3728L G10

Load Regulation

V_ITHvs V_RUN/SS

SENSE Pins Total Source Current

0.0

–0.1

–0.2

–0.3

–0.4

2.5

2.0

1.5

1.0

100

50

FCB = 0V

= 15V

V

= 0.7V

OSENSE

V

IN

FIGURE 13

0

–50

–100

0.5

0

1

2

3

4

5

0

2

3

4

5

6

2

4

1

0

6

V

(V)

LOAD CURRENT (A)

V

COMMON MODE VOLTAGE (V)

RUN/SS

SENSE

3728L G13

3728L G14

3728L G15

Maximum Current Sense

Threshold vs Temperature

Dropout Voltage vs Output Current

(Figure 14)

RUN/SS Current vs Temperature

80

78

76

74

72

70

4

3

2

1

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

V

= 5V

OUT

R

SENSE

= 0.015Ω

R

SENSE

= 0.010Ω

0

–50 –25

0

25

50

75 100 125

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

OUTPUT CURRENT (A)

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

3728L G17

3728L G18

3728L G25

3728lxff

7

LTC3728L/LTC3728LX

Typical perForMance characTerisTics

Soft-Start Up (Figure 13)

Load Step (Figure 13)

V

OUT

200mV/DIV

V

OUT

200mV/DIV

5V/DIV

V

RUN/SS

5V/DIV

I

L

2A/DIV

L

2A/DIV

I

L

2A/DIV

3728L G20

3728L G21

3728L G19

V

= 15V

= 5V

PLLFLTR

20µs/DIV

V

= 15V

= 5V

PLLFLTR

20µs/DIV

V

= 15V

= 5V

5ms/DIV

IN

OUT

IN

OUT

IN

OUT

= 0V

LOAD STEP = 0A TO 3A

Burst Mode OPERATION

LOAD STEP = 0A TO 3A

CONTINUOUS MODE

Input Source/Capacitor

Instantaneous Current (Figure 13)

Constant-Frequency (Burst Inhibit)

Operation (Figure 13)

Burst Mode Operation (Figure 13)

I

IN

V

2A/DIV

OUT

20mV/DIV

V

IN

200mV/DIV

V

SW1

10V/DIV

I

L

I

0.5A/DIV

L

V

SW2

0.5A/DIV

10V/DIV

3728L G24

3728L G23

3728L G22

V

I

= 15V

= 5V

PLLFLTR

2µs/DIV

V

I

10µs/DIV

V

I

= 15V

1µs/DIV

= 3.3V

OUT2

IN

OUT

IN

OUT

IN

= 5V, V

OUT1

PLLFLTR

= I

= 0V

= 5V

= 20mA

= 2A

FCB

OUT

OUT5 OUT3.3

3728lxff

8

LTC3728L/LTC3728LX

Typical perForMance characTerisTics

Current Sense Pin Input Current

vs Temperature

EXTV_CCSwitch Resistance

vs Temperature

Oscillator Frequency

vs Temperature

700

35

33

31

29

27

25

10

8

V

= 5V

OUT

600

V

= 2.4V

PLLFLTR

500

400

300

200

100

V

= 1.2V

= 0V

PLLFLTR

6

V

4

PLLFLTR

2

0

50

100 125

50

75 100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

75

–50 –25

0

25

TEMPERATURE (°C)

3728L G28

3728L G26

3728L G27

Undervoltage Lockout

vs Temperature

Shutdown Latch Thresholds

vs Temperature

3.50

3.45

3.40

3.35

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

LATCH ARMING

LATCHOFF

THRESHOLD

3.30

3.25

3.20

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

75

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

3728L G29

3728L G30

3728lxff

9

LTC3728L/LTC3728LX

pin FuncTions

V

, V

: Error Amplifier Feedback Input.

TG2, TG1: High Current Gate Drives for Top N-Channel

OSENSE1

OSENSE2

Receives the remotely sensed feedback voltage for each

controller from an external resistive divider across the

output.

MOSFETs. These are the outputs of floating drivers with

a voltage swing equal to INTV – 0.5V superimposed on

CC

the switch node voltage SW.

PLLFLTR:FilterConnectionforPhase-LockedLoop. Alter-

natively, this pin can be driven with an AC or DC voltage

source to vary the frequency of the internal oscillator.

SW2,SW1:SwitchNodeConnectionstoInductors.Voltage

swing at these pins is from a Schottky diode (external)

voltage drop below ground to V .

IN

PLLIN: External Synchronization Input to Phase Detector.

This pin is internally terminated to SGND with 50kΩ. The

phase-locked loop will force the rising top gate signal of

controller 1 to be synchronized with the rising edge of

the PLLIN signal.

BOOST2, BOOST1: Bootstrapped Supplies to the Top-

side Floating Drivers. Capacitors are connected between

the boost and switch pins and Schottky diodes are tied

between the boost and INTV pins. Voltage swing at the

CC

boost pins is from INTV to (V + INTV ).

CC

IN

CC

FCB: Forced Continuous Control Input. This input acts

on both controllers and is normally used to regulate a

secondary winding. Pulling this pin below 0.8V will force

continuous synchronous operation.

BG2, BG1:HighCurrentGateDrivesforBottom(Synchro-

nous) N-Channel MOSFETs. Voltage swing at these pins

is from ground to INTV .

CC

PGND: Driver Power Ground. Connects to the sources

I

: Error Amplifier Output and Switching Regulator

of bottom (synchronous) N-channel MOSFETs, anodes

TH1, TH2

Compensation Point. Each associated channels’ current

of the Schottky rectifiers and the (–) terminal(s) of C .

IN

comparator trip point increases with this control voltage.

INTV : Output of the Internal 5V Linear Low Dropout

CC

SGND: Small Signal Ground. Common to both con-

trollers, this pin must be routed separately from high

Regulator and the EXTV Switch. The driver and control

CC

circuits are powered from this voltage source. Must be

decoupled to power ground with a minimum of 4.7µF

tantalum or other low ESR capacitor.

currentgroundstothecommon(–)terminalsoftheC

capacitors.

OUT

3.3V : Linear Regulator Output. Capable of supplying

EXTV : External Power Input to an Internal Switch

CC

OUT

10mA DC with peak currents as high as 50mA.

Connected to INTV . This switch closes and supplies

CC

V

power, bypassing the internal low dropout regulator,

CC

NC: No Connect.

wheneverEXTV ishigherthan4.7V.SeeEXTV connec-

CC

–

SENSE2 , SENSE1 : The (–) Input to the Differential Cur-

tion in Applications section. Do not exceed 7V on this pin.

rent Comparators.

V : Main Supply Pin. A bypass capacitor should be tied

IN

+

SENSE2 ,SENSE1 :The(+)InputtotheDifferentialCurrent

Comparators. The I pin voltage and controlled offsets

between this pin and the signal ground pin.

TH

PGOOD: Open-Drain Logic Output. PGOOD is pulled to

–

+

between the SENSE and SENSE pins in conjunction with

set the current trip threshold.

ground when the voltage on either V

within 7.5% of its set point.

pin is not

OSENSE

R

SENSE

RUN/SS2,RUN/SS1:Combinationofsoft-start,runcontrol

inputs and short-circuit detection timers. A capacitor to

ground at each of these pins sets the ramp time to full

output current. Forcing either of these pins back below

1.0V causes the IC to shut down the circuitry required for

thatparticularcontroller.Latchoffovercurrentprotectionis

also invoked via this pin as described in the Applications

Information section.

Exposed Pad (UH Package Only): Signal Ground. Must

be soldered to the PCB, providing a local ground for the

control components of the IC, and be tied to the PGND

pin under the IC.

3728lxff

10

LTC3728L/LTC3728LX

FuncTional DiagraM

3728lxff

11

LTC3728L/LTC3728LX

operaTion ^{(Refer to Functional Diagram)}

Main Control Loop

Low Current Operation

TheICusesaconstant-frequency,currentmodestep-down The FCB pin is a multifunction pin providing two func-

architecture with the two controller channels operating

180 degrees out of phase. During normal operation, each

top MOSFET is turned on when the clock for that channel

sets the RS latch, and turned off when the main current

tions:1)toprovideregulationforasecondarywindingby

temporarily forcing continuous PWM operation on both

controllers; and 2) to select between two modes of low

current operation. When the FCB pin voltage is below

0.8V,thecontrollerforcescontinuousPWMcurrentmode

operation. In this mode, the top and bottom MOSFETs

are alternately turned on to maintain the output voltage

independent of direction of inductor current. When the

comparator, I , resets the RS latch. The peak inductor

1

current at which I resets the RS latch is controlled by

1

the voltage on the I pin, which is the output of each

TH

error amplifier EA. The V

pin receives the voltage

OSENSE

feedback signal, which is compared to the internal refer-

ence voltage by the EA. When the load current increases,

FCB pin is below V

– 2V but greater than 0.8V,

INTVCC

the controller enters Burst Mode operation. Burst Mode

operation sets a minimum output current level before

inhibiting the top switch and turns off the synchronous

MOSFET(s)whentheinductorcurrentgoesnegative.This

combination of requirements will, at low currents, force

it causes a slight decrease in V

relative to the 0.8V

OSENSE

reference, which in turn causes the I voltage to increase

TH

until the average inductor current matches the new load

current. After the top MOSFET has turned off, the bottom

MOSFET is turned on until either the inductor current

the I pin below a voltage threshold that will temporarily

TH

starts to reverse, as indicated by current comparator I ,

inhibit turn-on of both output MOSFETs until the output

2

or the beginning of the next cycle.

voltage drops. There is 60mV of hysteresis in the burst

comparatorBtiedtotheI pin.Thishysteresisproduces

TH

ThetopMOSFETdriversarebiasedfromfloatingbootstrap

output signals to the MOSFETs that turn them on for

several cycles, followed by a variable “sleep” interval

depending upon the load current. The resultant output

voltage ripple is held to a very small value by having the

hystereticcomparatoraftertheerroramplifiergainblock.

capacitor C , which normally is recharged during each off

B

cycle through an external diode when the top MOSFET

turns off. As V decreases to a voltage close to V

,

IN

OUT

the loop may enter dropout and attempt to turn on the

top MOSFET continuously. The dropout detector detects

this and forces the top MOSFET off for about 400ns every

Frequency Synchronization

tenth cycle to allow C to recharge.

B

The phase-locked loop allows the internal oscillator to

be synchronized to an external source via the PLLIN pin.

The output of the phase detector at the PLLFLTR pin is

also the DC frequency control input of the oscillator that

operates over a 260kHz to 550kHz range corresponding

to a DC voltage input from 0V to 2.4V. When locked, the

PLL aligns the turn on of the top MOSFET to the rising

edge of the synchronizing signal. When PLLIN is left

open, the PLLFLTR pin goes low, forcing the oscillator to

minimum frequency.

The main control loop is shut down by pulling the RUN/SS

pin low. Releasing RUN/SS allows an internal 1.2µA cur-

rent source to charge soft-start capacitor C . When C

SS

reaches 1.5V, the main control loop is enabled with the I

TH

voltage clamped at approximately 30% of its maximum

value. As C continues to charge, the I pin voltage is

SS

TH

graduallyreleasedallowingnormal,full-currentoperation.

When both RUN/SS1 and RUN/SS2 are low, all control-

ler functions are shut down, including the 5V and 3.3V

regulators.

3728lxff

12

LTC3728L/LTC3728LX

operaTion ^{(Refer to Functional Diagram)}

Constant-Frequency Operation

Power Good (PGOOD) Pin

When the FCB pin is tied to INTV , Burst Mode opera-

ThePGOODpinisconnectedtoanopendrainofaninternal

MOSFET. TheMOSFETturnsonandpullsthepinlowwhen

either output is not within 7.5% of the nominal output

levelasdeterminedbytheresistivefeedbackdivider.When

both outputs meet the 7.5% requirement, the MOSFET is

turned off within 10µs and the pin is allowed to be pulled

up by an external resistor to a source of up to 7V.

CC

tion is disabled and the forced minimum output current

requirementisremoved.Thisprovidesconstant-frequency,

discontinuous current (preventing reverse inductor cur-

rent) operation over the widest possible output current

range.Thisconstant-frequencyoperationisnotasefficient

as Burst Mode operation, but does provide a lower noise,

constant-frequencyoperatingmodedowntoapproximately

1% of the designed maximum output current.

Foldback Current, Short-Circuit Detection

and Short-Circuit Latchoff

Continuous Current (PWM) Operation

TheRUN/SScapacitorsareusedinitiallytolimittheinrush

current of each switching regulator. After the controller

has been started and been given adequate time to charge

up the output capacitors and provide full load current, the

RUN/SScapacitorisusedinashort-circuittime-outcircuit.

If the output voltage falls to less than 70% of its nominal

output voltage, the RUN/SS capacitor begins discharging

ontheassumptionthattheoutputisinanovercurrentand/

or short-circuit condition. If the condition lasts for a long

enough period as determined by the size of the RUN/SS

capacitor, the controller will be shut down until the RUN/

SSpin(s)voltage(s)arerecycled.Thisbuilt-inlatchoffcan

beoverriddenbyprovidinga>5µApull-upatacompliance

of 5V to the RUN/SS pin(s). This current shortens the soft

start period but also prevents net discharge of the RUN/

SScapacitor(s)duringanovercurrentand/orshort-circuit

condition.Foldbackcurrentlimitingisalsoactivatedwhen

the output voltage falls below 70% of its nominal level

whether or not the short-circuit latchoff circuit is enabled.

Even if a short is present and the short-circuit latchoff is

not enabled, a safe, low output current is provided due to

internal current foldback and actual power wasted is low

due to the efficient nature of the current mode switching

regulator.

Tying the FCB pin to ground will force continuous current

operation. This is the least efficient operating mode, but

may be desirable in certain applications. The output can

source or sink current in this mode. When sinking current

whileinforcedcontinuousoperation,currentwillbeforced

back into the main power supply potentially boosting the

input supply to dangerous voltage levels—BEWARE!

INTV /EXTV Power

CC

Power for the top and bottom MOSFET drivers and most

otherinternalcircuitryisderivedfromtheINTV pin.When

CC

the EXTV pin is left open, an internal 5V low dropout

CC

linear regulator supplies INTV power. If EXTV is taken

CC

above 4.7V, the 5V regulator is turned off and an internal

switch is turned on connecting EXTV to INTV . This al-

CC

lowstheINTV powertobederivedfromahighefficiency

CC

external source such as the output of the regulator itself

or a secondary winding, as described in the Applications

Information section.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient

overshoots (>7.5%) as well as other more serious condi-

tions that may overvoltage the output. In this case, the top

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

3728lxff

13

LTC3728L/LTC3728LX

operaTion ^{(Refer to Functional Diagram)}

THEORY AND BENEFITS OF 2-PHASE OPERATION

This effectively interleaves the current pulses drawn by

the switches, greatly reducing the overlap time where

they add together. The result is a significant reduction

in total RMS input current, which in turn allows less

expensive input capacitors to be used, reduces shielding

requirements for EMI and improves real world operating

efficiency.

The LTC1628 and the LTC3728L family of dual high effi-

ciency DC/DC controllers brings the considerable benefits

of 2-phase operation to portable applications for the first

time. Notebook computers, PDAs, handheld terminals

and automotive electronics will all benefit from the lower

input filtering requirement, reduced electromagnetic in-

terference (EMI) and increased efficiency associated with

2-phase operation.

Figure 3 compares the input waveforms for a representa-

tive single-phase dual switching regulator to the LTC1628

2-phasedualswitchingregulator.Anactualmeasurementof

the RMS input current under these conditions shows that

Why the need for 2-phase operation? Up until the

2-phasefamily,constant-frequencydualswitchingregula-

tors operated both channels in phase (i.e., single-phase

operation). This means that both switches turned on at

the same time, causing current pulses of up to twice the

amplitude of those for one regulator to be drawn from the

input capacitor and battery. These large amplitude current

pulses increased the total RMS current flowing from the

input capacitor, requiring the use of more expensive input

capacitorsandincreasingbothEMIandlossesintheinput

capacitor and battery.

2-phaseoperationdroppedtheinputcurrentfrom2.53A

RMS

to1.55A

.Whilethisisanimpressivereductioninitself,

RMS

2

rememberthatthepowerlossesareproportionaltoI

,

RMS

meaning that the actual power wasted is reduced by a fac-

tor of 2.66. The reduced input ripple voltage also means

less power is lost in the input power path, which could

include batteries, switches, trace/connector resistances

and protection circuitry. Improvements in both conducted

and radiated EMI also directly accrue as a result of the

reduced RMS input current and voltage.

With 2-phase operation, the two channels of the dual-

switchingregulatorareoperated180degreesoutofphase.

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

DC236 F03a

DC236 F03b

I

= 2.53A

I

= 2.53A

RMS

IN(MEAS)

RMS

IN(MEAS)

(a)

(b)

Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators

Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows

Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency

3728lxff

14

LTC3728L/LTC3728LX

operaTion ^{(Refer to Functional Diagram)}

duty cycles which, in turn, are dependent upon the input

channels becomes more critical with 2-phase operation

becauseswitchtransitionsinonechannelcouldpotentially

disrupt the operation of the other channel.

voltage V (Duty Cycle = V /V ). Figure 4 shows how

IN

OUT IN

theRMSinputcurrentvariesforsingle-phaseand2-phase

operation for 3.3V and 5V regulators over a wide input

voltage range.

These 2-phase parts are proof that these hurdles have

been surmounted. They offer unique advantages for the

ever expanding number of high efficiency power supplies

required in portable electronics.

Itcanreadilybeseenthattheadvantagesof2-phaseopera-

tion are not just limited to a narrow operating range, but

in fact extend over a wide region. A good rule of thumb

for most applications is that 2-phase operation will reduce

the input capacitor requirement to that for just one chan-

nel operating at maximum current and 50% duty cycle.

3.0

SINGLE PHASE

DUAL CONTROLLER

2.5

2.0

1.5

1.0

0.5

0

A final question: If 2-phase operation offers such an ad-

vantage over single-phase operation for dual switching

regulators, why hasn’t it been done before? The answer

is that, while simple in concept, it is hard to implement.

Constant-frequency, current mode switching regulators

require an oscillator derived slope compensation signal

to allow stable operation of each regulator at over 50%

duty cycle. This signal is relatively easy to derive in

single-phase dual switching regulators, but required the

development of a new and proprietary technique to allow

2-phase operation. In addition, isolation between the two

2-PHASE

DUAL CONTROLLER

V

O1

V

O2

= 5V/3A

= 3.3V/3A

0

10

20

30

40

INPUT VOLTAGE (V)

3728 F04

Figure 4. RMS Input Current Comparison

3728lxff

15

LTC3728L/LTC3728LX

applicaTions inForMaTion

Figure1onthefirstpageisabasicLTC3728L/LTC3728LX

applicationcircuit.Externalcomponentselectionisdriven

by the load requirement, and begins with the selection of

2.5

2.0

1.5

1.0

0.5

0

R

andtheinductorvalue. Next, thepowerMOSFETs

SENSE

and D1 are selected. Finally, C and C

are selected.

IN

OUT

The circuit shown in Figure 1 can be configured for

operation up to an input voltage of 28V (limited by the

external MOSFETs).

200

300

400

500

600

R

SENSE

Selection for Output Current

OPERATING FREQUENCY (kHz)

3728 F05

R

ischosenbasedontherequiredoutputcurrent.The

SENSE

current comparator has a maximum threshold of 75mV/

Figure 5. PLLFLTR Pin Voltage vs Frequency

R

and an input common mode range of SGND to

CC

SENSE

and Frequency Synchronization in the Applications Infor-

mation section for additional information.

1.1(INTV ). The current comparator threshold sets the

peak of the inductor current, yielding a maximum average

output current I

peak-to-peak ripple current, ΔI .

equal to the peak value less half the

A graph for the voltage applied to the PLLFLTR pin vs

frequency is given in Figure 5. As the operating frequency

isincreasedthegatechargelosseswillbehigher, reducing

efficiency (see Efficiency Considerations). The maximum

switching frequency is approximately 550kHz.

MAX

L

Allowing a margin for variations in the IC and external

component values yields:

50mV

I_MAX

R_SENSE

=

Inductor Value Calculation

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because

of MOSFET gate charge losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

Because of possible PCB layout-induced noise in the

current sensing loop, the AC current sensing ripple of

ΔV

= ΔI • R

also needs to be checked in the

SENSE

design to get good signal-to-noise ratio. In general, for

a reasonably good PCB layout, a 15mV ΔV voltage

SENSE

is recommended as a conservative design starting point.

When using the controller in very low dropout conditions,

themaximumoutputcurrentlevelwillbereducedduetothe

internal compensation required to meet stability criterion

for buck regulators operating at greater than 50% duty

factor. A curve is provided to estimate this reduction in

peak output current level depending upon the operating

duty factor.

The inductor value has a direct effect on ripple current.

The inductor ripple current ΔI decreases with higher

L

inductance or frequency and increases with higher V :

IN









1

V_OUT

∆I_L=

V_OUT1–





(f)(L)

V

IN

Operating Frequency

Accepting larger values of ΔI allows the use of low in-

The IC uses a constant-frequency, phase-lockable ar-

chitecture with the frequency determined by an internal

capacitor. This capacitor is charged by a fixed current plus

an additional current which is proportional to the voltage

applied to the PLLFLTR pin. Refer to Phase-Locked Loop

L

ductances, but results in higher output voltage ripple and

greater core losses. A reasonable starting point for setting

ripple current is ΔI = 30% of maximum output current or

higher for good load transient response and sufficient

ripple current signal in the current loop.

3728lxff

16

LTC3728L/LTC3728LX

applicaTions inForMaTion

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

The peak-to-peak drive levels are set by the INTV

CC

voltage. This voltage is typically 5V during start-up

(see EXTV Pin Connection). Consequently, logic-level

CC

25% of the current limit determined by R

. Lower

threshold MOSFETs must be used in most applications.

SENSE

inductor values (higher ΔI ) will cause this to occur at

The only exception is if low input voltage is expected (V

L

IN

lower load currents, which can cause a dip in efficiency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

< 5V); then, sublogic level threshold MOSFETs (V

GS(TH)

< 3V) should be used. Pay close attention to the BV

DSS

specification for the MOSFETs as well; most of the logic

level MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the

Inductor Core Selection

on-resistance R

, Miller capacitance C

, input

DS(ON)

MILLER

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcing the use of more expensive ferrite, molypermalloy,

orKoolMµ^®cores. Actualcorelossisindependentofcore

size for a fixed inductor value, but it is very dependent

on inductance selected. As inductance increases, core

losses go down. Unfortunately, increased inductance

requires more turns of wire and, therefore, copper losses

will increase.

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

C

MILLER

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

MILLER

along the horizontal axis while the curve is approximately

flat divided by the specified change in V . This result is

DS

then multiplied by the ratio of the application applied V

DS

to the gate charge curve specified V . When the IC is

DS

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

V_OUT

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates hard, which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

MainSwitchDuty Cycle =

V

IN

V – V

IN

OUT

Synchronous SwitchDuty Cycle =

V

IN

The MOSFET power dissipations at maximum output

current are given by:

V_OUT

2

P_MAIN

=

I

1+ d R

+

(

)

(

)

MAX

DS(ON)

Molypermalloy (from Magnetics, Inc.) is a very good, low

loss core material for toroids, but it is more expensive

than ferrite. A reasonable compromise from the same

manufacturer is Kool Mµ. Toroids are very space efficient,

especially when using several layers of wire. Because

they generally lack a bobbin, mounting is more difficult.

However, designs for surface mount are available that do

not increase the height significantly.

V

IN

I

²



MAX

2

V

R

C

•

(

)

(

_DR)(

)







IN

MILLER







1

+

f

( )







V

_{ INTVCC}– V_THMINV_THMIN

2

V – V

IN

OUT

P

=

I

(

1+ d R

DS(ON)

(

)

MAX

SYNC

V

IN

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for each

controller in the LTC3728L/LTC3728LX: One N-channel

MOSFET for the top (main) switch, and one N-channel

MOSFET for the bottom (synchronous) switch.

3728lxff

17

LTC3728L/LTC3728LX

applicaTions inForMaTion

factor of 30% to 70% when compared to a single phase

power supply solution.

where d is the temperature dependency of R

DR

and

DS(ON)

R

(approximately 4Ω) is the effective driver resistance

at the MOSFET’s Miller threshold voltage. V

is the

TH(MIN)

The type of input capacitor, value and ESR rating have

efficiency effects that need to be considered in the selec-

tion process. The capacitance value chosen should be

sufficient to store adequate charge to keep high peak

battery currents down. 20µF to 40µF is usually sufficient

for a 25W output supply operating at 200kHz. The ESR of

the capacitor is important for capacitor power dissipation

as well as overall battery efficiency. All of the power (RMS

ripple current • ESR) not only heats up the capacitor but

wastes power from the battery.

typical MOSFET minimum threshold voltage.

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For V < 20V

IN

the high current efficiency generally improves with larger

MOSFETs, while for V > 20V the transition losses rapidly

IN

increasetothepointthattheuseofahigherR

device

DS(ON)

withlowerC

actuallyprovideshigherefficiency.The

MILLER

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

Medium voltage (20V to 35V) ceramic, tantalum, OS-CON

and switcher-rated electrolytic capacitors can be used

as input capacitors, but each has drawbacks: ceramic

voltage coefficients are very high and may have audible

piezoelectric effects; tantalums need to be surge-rated;

OS-CONs suffer from higher inductance, larger case size

and limited surface-mount applicability; electrolytics’

higher ESR and dryout possibility require several to be

used. Multiphase systems allow the lowest amount of

capacitance overall. As little as one 22µF or two to three

10µF ceramic capacitors are an ideal choice in a 20W to

35W power supply due to their extremely low ESR. Even

though the capacitance at 20V is substantially below their

rating at zero-bias, very low ESR loss makes ceramics

an ideal candidate for highest efficiency battery operated

systems. Also consider parallel ceramic and high quality

electrolytic capacitors as an effective means of achieving

ESR and bulk capacitance goals.

The term (1 + d) is generally given for a MOSFET in the

form of a normalized R

vs Temperature curve, but

DS(ON)

d = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

TheSchottkydiode,D1,showninFigure1conductsduring

the dead time between the conduction of the two power

MOSFETs. This prevents the body diode of the bottom

MOSFET from turning on, storing charge during the dead

time and requiring a reverse-recovery period that could

cost as much as 3% in efficiency at high V . A 1A to 3A

IN

Schottky is generally a good compromise for both regions

of operation due to the relatively small average current.

Larger diodes result in additional transition losses due to

their larger junction capacitance.

C and C

IN

Selection

OUT

Incontinuousmode,thesourcecurrentofthetopN-channel

The selection of C is simplified by the multiphase ar-

MOSFETisasquarewaveofdutycycleV /V .Toprevent

IN

OUT IN

chitecture and its impact on the worst-case RMS current

drawnthroughtheinputnetwork(battery/fuse/capacitor).

It can be shown that the worst-case RMS current occurs

when only one controller is operating. The controller

large voltage transients, a low ESR input capacitor sized

for the maximum RMS current of one channel must be

used. The maximum RMS capacitor current is given by:



^1/2

V_OUTV − V

(

)

IN

OUT





with the highest (V )(I ) product needs to be used

C_INRequiredI_RMS≈ I_MAX

OUT OUT

V

IN

in the subsequent formula to determine the maximum

RMS current requirement. Increasing the output current,

drawn from the other out-of-phase controller, will actually

decreasetheinputRMSripplecurrentfromthismaximum

value (see Figure 4). The out-of-phase technique typically

reduces the input capacitor’s RMS ripple current by a

This formula has a maximum at V = 2V

, where I

RMS

IN

OUT

= I /2. This simple worst-case condition is commonly

OUT

usedfordesignbecauseevensignificantdeviationsdonot

offermuchrelief.Notethatcapacitormanufacturer’sripple

3728lxff

18

LTC3728L/LTC3728LX

applicaTions inForMaTion

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required.Severalcapacitorsmayalsobeparalleledtomeet

size or height requirements in the design. Always consult

the manufacturer if there is any question.

ThefirstconditionrelatestotheripplecurrentintotheESR

oftheoutputcapacitancewhilethesecondtermguarantees

thattheoutputcapacitancedoesnotsignificantlydischarge

duringtheoperatingfrequencyperiodduetoripplecurrent.

The choice of using smaller output capacitance increases

the ripple voltage due to the discharging term but can be

compensated for by using capacitors of very low ESR to

maintain the ripple voltage at or below 50mV. The I_THpin

OPTI-LOOP compensation components can be optimized

to provide stable, high performance transient response

regardless of the output capacitors selected.

ThebenefitoftheLTC3728L/LTC3728LXmultiphaseclock-

ing can be calculated by using the equation above for the

higher power controller and then calculating the loss that

would have resulted if both controller channels switched

on at the same time. The total RMS power lost is lower

when both controllers are operating due to the interleav-

ing of current pulses through the input capacitor’s ESR.

This is why the input capacitor’s requirement calculated

in the previous equation for the worst-case controller is

adequate for the dual controller design. Remember that

input protection fuse resistance, battery resistance and

PC board trace resistance losses are also reduced due to

the reduced peak currents in a multiphase system. The

overall benefit of a multiphase design will only be fully

realized when the source impedance of the power supply/

battery is included in the efficiency testing. The drains of

the two top MOSFETs should be placed within 1cm of each

Manufacturers such as Nichicon, United Chemi-Con and

Sanyo can be considered for high performance through-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest (ESR)

(size) product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON capacitors is recommended to reduce the

inductance effects.

In surface mount applications, multiple capacitors may

need to be used in parallel to meet ESR, RMS cur-

rent handling and load step requirements. Aluminum

electrolytic, dry tantalum and special polymer capaci-

tors are available in surface mount packages. Special

polymer surface mount capacitors offer very low ESR

but have lower storage capacity per unit volume than

other capacitor types. These capacitors offer a very

cost-effective output capacitor solution and are an ideal

choice when combined with a controller having high

loop bandwidth. Tantalum capacitors offer the highest

capacitance density and are often used as output capaci-

tors for switching regulators having controlled soft-start.

Several excellent surge-tested choices are the AVX TPS,

AVX TPSV or the KEMET T510 series of surface mount

tantalums, available in case heights ranging from 2mm

to 4mm. Aluminum electrolytic capacitors can be used

in cost-driven applications providing that consideration

is given to ripple current ratings, temperature and long

term reliability. A typical application will require several

to many aluminum electrolytic capacitors in parallel. A

combination of the aforementioned capacitors will often

result in maximizing performance and minimizing overall

cost. Other capacitor types include Nichicon PL series,

other and share a common C (s). Separating the drains

IN

and C may produce undesirable voltage and current

IN

resonances at V .

IN

The selection of C

is driven by the required effective

OUT

series resistance (ESR). Typically once the ESR require-

ment is satisfied the capacitance is adequate for filtering.

The output ripple (ΔV ) is determined by:

OUT











1

∆V_OUT≈ ∆I_LESR+

8fC

_OUT

Wheref=operatingfrequency, C

=outputcapacitance,

OUT

and ΔI = ripple current in the inductor. The output ripple

L

is highest at maximum input voltage since ΔI increases

L

with input voltage. With ΔI = 0.3I

the output

L

OUT(MAX)

ripple will typically be less than 50mV at the maximum

V assuming:

IN

C

OUT

Recommended ESR < 2 R

SENSE

and C

> 1/(8fR

)

OUT

SENSE

3728lxff

19

LTC3728L/LTC3728LX

applicaTions inForMaTion

Panasonic SP, NEC Neocap, Cornell Dubilier ESRE and

Sprague 595D series. Consult manufacturers for other

specific recommendations.

current drawn from the internal 3.3V linear regulator. To

prevent maximum junction temperature from being ex-

ceeded,theinputsupplycurrentmustbecheckedoperating

in continuous mode at maximum V .

IN

INTV Regulator

CC

EXTV Connection

CC

An internal P-channel low dropout regulator produces

5V at the INTV_CCpin from the V_INsupply pin. INTV_CC

powers the drivers and internal circuitry within the IC.

The INTV_CCpin regulator can supply a peak current of

50mA and must be bypassed to ground with a minimum

of 4.7µF tantalum, 10µF special polymer, or low ESR type

electrolytic capacitor. A 1µF ceramic capacitor placed di-

rectly adjacent to the INTV_CCand PGND IC pins is highly

recommended. Good bypassing is necessary to supply

the high transient currents required by the MOSFET gate

drivers and to prevent interaction between channels.

The IC contains an internal P-channel MOSFET switch

connected between the EXTV and INTV pins. When

CC

thevoltageappliedtoEXTV risesabove4.7V, theinternal

CC

regulator is turned off and the switch closes, connecting

theEXTV pintotheINTV pin,therebysupplyinginternal

CC

power. The switch remains closed as long as the voltage

applied to EXTV remains above 4.5V. This allows the

CC

MOSFET driver and control power to be derived from the

output during normal operation (4.7V < V

< 7V) and

OUT

from the internal regulator when the output is out of regu-

lation (start-up, short-circuit). If more current is required

Higher input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mumjunctiontemperatureratingfortheICtobeexceeded.

The system supply current is normally dominated by the

gate charge current. Additional external loading of the

through the EXTV switch than is specified, an external

CC

Schottky diode can be added between the EXTV and

CC

INTV pins. Do not apply greater than 7V to the EXTV

CC

pin and ensure that EXTV < V .

CC

IN

INTV and 3.3V linear regulators also needs to be taken

Significant efficiency gains can be realized by powering

INTV from the output, since the V current resulting

CC

into account for the power dissipation calculations. The

CC

IN

total INTV current can be supplied by either the 5V in-

from the driver and control currents will be scaled by a

CC

ternal linear regulator or by the EXTV input pin. When

factor of (Duty Cycle)/(Efficiency). For 5V regulators this

CC

the voltage applied to the EXTV pin is less than 4.7V, all

supplymeansconnectingtheEXTV pindirectlytoV

.

OUT

CC

of the INTV current is supplied by the internal 5V linear

However, for 3.3V and other lower voltage regulators,

CC

regulator. Power dissipation for the IC in this case is high-

additional circuitry is required to derive INTV power

CC

est: (V )(I

), and overall efficiency is lowered. The

from the output.

IN INTVCC

gate charge current is dependent on operating frequency

as discussed in the Efficiency Considerations section.

The junction temperature can be estimated by using the

equations given in Note 2 of the Electrical Characteristics.

The following list summarizes the four possible connec-

tions for EXTV :

CC

1.EXTV Left Open (or Grounded). This will cause

CC

INTV to be powered from the internal 5V regulator

For example, the IC V current is thermally limited to less

CC

IN

resulting in an efficiency penalty of up to 10% at high

than 67mA from a 24V supply when not using the EXTV

CC

input voltages.

pin as follows:

2.EXTV Connected Directly to V

. This is the normal

T = 70°C + (67mA)(24V)(34°C/W) = 125°C

CC

OUT

J

connection for a 5V regulator and provides the highest

Use of the EXTV input pin reduces the junction tem-

CC

efficiency.

perature to:

3.EXTV Connected to an External Supply. If an external

CC

T = 70°C + (67mA)(5V)(34°C/W) = 81°C

J

supply is available in the 5V to 7V range, it may be used

The absolute maximum rating for the INTV pin is 40mA.

to power EXTV providing it is compatible with the

CC

Dissipationshouldbecalculatedtoalsoincludeanyadded

MOSFET gate drive requirements.

3728lxff

20

LTC3728L/LTC3728LX

applicaTions inForMaTion

4.EXTV ConnectedtoanOutput-DerivedBoostNetwork.

Output Voltage

CC

For 3.3V and other low voltage regulators, efficiency

The output voltages are each set by an external feedback

resistivedividercarefullyplacedacrosstheoutput capaci-

tor. The resultant feedback signal is compared with the

internal precision 0.800V voltage reference by the error

amplifier. The output voltage is given by the equation:

gains can still be realized by connecting EXTV to an

CC

output-derived voltage that has been boosted to greater

than 4.7V. This can be done with either the inductive

boost winding as shown in Figure 6a or the capacitive

charge pump shown in Figure 6b. The charge pump has

the advantage of simple magnetics.

R2

R1





V_OUT= 0.8V 1+









Topside MOSFET Driver Supply (C , D )

B

where R1 and R2 are defined in Figure 2.

External bootstrap capacitors C connected to the BOOST

B

pins supply the gate drive voltages for the topside MOS-

+

–

SENSE /SENSE Pins

FETs. Capacitor C in the Functional Diagram is charged

B

though external diode D from INTV when the SW pin

B

CC

The common mode input range of the current comparator

is low. When one of the topside MOSFETs is to be turned

sense pins is from 0V to (1.1)INTV . Continuous linear

CC

on, thedriverplacestheC voltageacrossthegate-source

B

operation is guaranteed throughout this range allowing

of the desired MOSFET. This enhances the MOSFET and

output voltage setting from 0.8V to 7.7V, depending upon

turns on the topside switch. The switch node voltage, SW,

the voltage applied to EXTV . A differential NPN input

CC

rises to V and the BOOST pin follows. With the topside

IN

stageisbiasedwithinternalresistorsfromaninternal2.4V

source, as shown in the Functional Diagram. This requires

that current either be sourced or sunk from the SENSE

pinsdependingontheoutputvoltage. Iftheoutputvoltage

is below 2.4V, current will flow out of both SENSE pins to

the main output. The output can be easily preloaded by

MOSFET on, the boost voltage is above the input supply:

V

B

= V + V

. The value of the boost capacitor

BOOST

IN

INTVCC

C needstobe100timesthatofthetotalinputcapacitance

of the topside MOSFET(s). The reverse breakdown of the

external Schottky diode must be greater than V

.

IN(MAX)

When adjusting the gate drive level, the final arbiter is the

total input current for the regulator. If a change is made

and the input current decreases, then the efficiency has

improved. If there is no change in input current, then there

is no change in efficiency.

the V

resistive divider to compensate for the current

OUT

comparator’s negative input bias current. The maximum

current flowing out of each pair of SENSE pins is:

+

–

I

+ I

= (2.4V – V )/24k

SENSE

OUT

+

V

IN

1µF

OPTIONAL EXTV

CONNECTION

CC

+

5V < V

< 7V

SEC

C

IN

0.22µF

BAT85

BAT 85

V

IN

V

SEC

IN

LTC3728L/

LTC3728LX

LTC3728L/

LTC3728LX

+

1µF

V

VN2222LL

TG1

SW

TG1

SW

R

SENSE

N-CH

V

OUT

L1

T1

1:N

EXTV

CC

R6

R5

+

C

BG1

OUT

FCB

BG1

OUT

N-CH

PGND

SGND

PGND

3728 F06b

3728 F06a

Figure 6a. Secondary Output Loop and EXTV_CCConnection

Figure 6b. Capacitive Charge Pump for EXTV_CC

3728lxff

21

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applicaTions inForMaTion

Since V

is servoed to the 0.8V reference voltage,

Each RUN/SS pin has an internal 6V Zener clamp (see the

Functional Diagram).

OSENSE

we can choose R1 in Figure 2 to have a maximum value

to absorb this current.

V

IN

3.3V OR 5V

RUN/SS

*







0.8V

2.4V – V

R

SS

R1

= 24k

(MAX)

D1





_OUT

C

SS

for V

< 2.4V

OUT

Regulating an output voltage of 1.8V, the maximum value

of R1 should be 32k. Note that for an output voltage above

2.4V, R1 has no maximum value necessary to absorb the

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

3728 F07

Figure 7. RUN/SS Pin Interfacing

sensecurrents;however,R1isstillboundedbytheV

feedback current.

OSENSE

Fault Conditions: Overcurrent Latchoff

Soft-Start/Run Function

The RUN/SS pins also provide the ability to latch off the

controller(s) when an overcurrent condition is detected.

The RUN/SS1 and RUN/SS2 pins are multipurpose pins

thatprovideasoft-startfunctionandameanstoshutdown

the LTC3728L/LTC3728LX. Soft-start reduces the input

power source’s surge currents by gradually increasing the

controller’s current limit (proportional to V ). This pin

can also be used for power supply sequencing.

The RUN/SS capacitor, C , is used initially to turn on

SS

and limit the inrush current. After the controller has been

started and been given adequate time to charge up the

outputcapacitorandprovidefullloadcurrent, theRUN/SS

capacitor is used for a short-circuit timer. If the regulator’s

output voltage falls to less than 70% of its nominal value

ITH

An internal 1.2µA current source charges up the C

SS

after C reaches 4.1V, C begins discharging on the as-

SS

capacitor When the voltage on RUN/SS1 (RUN/SS2)

.

sumption that the output is in an overcurrent condition. If

reaches 1.5V, the particular controller is permitted to start

operating. As the voltage on RUN/SS increases from 1.5V

to 3.0V, the internal current limit is increased from 25mV/

theconditionlastsforalongenoughperiodasdetermined

by the size of the C and the specified discharge current,

SS

the controller will be shut down until the RUN/SS pin volt-

age is recycled. If the overload occurs during start-up, the

time can be approximated by:

R

_SENSEto 75mV/R_SENSE. The output current limit ramps up

slowly, taking an additional 1.25s/µF to reach full cur-

rent. The output current thus ramps up slowly, reducing

the starting surge current required from the input power

supply. If RUN/SS has been pulled all the way to ground

there is a delay before starting of approximately:

t

≈ [C (4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA)

LO1

SS

6

= 2.7 • 10 (C )

SS

If the overload occurs after start-up the voltage on C will

SS

begin discharging from the Zener clamp voltage:

1.5V

1.2µA

t_DELAY

=

C_SS= 1.25s /µF C

SS

(

)

6

t

≈ [C (6 – 3.5)]/(1.2µA) = 2.1 • 10 (C )

LO2

SS

This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor to the RUN/SS pin, as shown

in Figure 7. This resistance shortens the soft-start period

and prevents the discharge of the RUN/SS capacitor

during an over current condition. Tying this pull-up resis-

tor to V_IN, as in Figure 7, defeats overcurrent latchoff.

3V − 1.5V

1.2µA

t_IRAMP

=

C_SS= 1.25s /µF C

SS

(

)

By pulling both RUN/SS pins below 1V, the IC is put into

low current shutdown (I_Q= 20µA). The RUN/SS pins

can be driven directly from logic, as shown in Figure 7.

Diode, D1, in Figure 7 reduces the start delay but allows

C_SSto ramp up slowly providing the soft-start function.

Why should you defeat overcurrent latchoff? During the

prototyping stage of a design, there may be a problem

3728lxff

22

LTC3728L/LTC3728LX

applicaTions inForMaTion

with noise pickup or poor layout causing the protection

circuit to latch off. Defeating this feature will easily allow

troubleshooting of the circuit and PC layout. The internal

short-circuit and foldback current limiting still remains

active, thereby protecting the power supply system from

failure. After the design is complete, a decision can be

made whether to enable the latchoff feature.

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

muchhigherthannominallevels.Thecrowbarcauseshuge

currents to ﬂow, that blow the fuse to protect against a

shortedtopMOSFETiftheshortoccurswhilethecontroller

is operating.

The value of the soft-start capacitor C may need to be

SS

A comparator monitors the output for overvoltage con-

ditions. The comparator (OV) detects overvoltage faults

greaterthan7.5%abovethenominaloutputvoltage.When

this condition is sensed, the top MOSFET is turned off

and the bottom MOSFET is turned on until the overvolt-

age condition is cleared. The output of this comparator

is only latched by the overvoltage condition itself and

will, therefore, allow a switching regulator system hav-

ing a poor PC layout to function while the design is being

debugged. The bottom MOSFET remains on continuously

scaled with output voltage, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

–4

C

> (C

)(V ) (10 ) (R

)

SS

OUT

SENSE

The minimum recommended soft-start capacitor of C

0.1µF will be sufficient for most applications.

=

SS

Fault Conditions: Current Limit and Current Foldback

The current comparators have a maximum sense volt-

age of 75mV resulting in a maximum MOSFET current

for as long as the OV condition persists. If V

returns

OUT

to a safe level, normal operation automatically resumes. A

shorted top MOSFET will result in a high current condition

which will open the system fuse. The switching regulator

will regulate properly with a leaky top MOSFET by altering

the duty cycle to accommodate the leakage.

of 75mV/R

. The maximum value of current limit

SENSE

generally occurs with the largest V at the highest ambi-

IN

ent temperature, conditions that cause the highest power

dissipation in the top MOSFET.

Each controller includes current foldback to help further

limit load current when the output is shorted to ground.

The foldback circuit is active even when the overload

shutdown latch previously described is overridden. If the

output falls below 70% of its nominal output level, then

themaximumsensevoltageisprogressivelyloweredfrom

75mV to 25mV. Under short-circuit conditions with very

low duty cycles, the controller will begin cycle skipping

in order to limit the short-circuit current. In this situation,

the bottom MOSFET will be dissipating most of the power

but less than in normal operation. The short-circuit ripple

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal

voltage controlled oscillator and phase detector. This al-

lows the top MOSFET turn-on to be locked to the rising

edge of an external source. The frequency range of the

voltage controlled oscillator is 50% around the center

frequency f . A voltage applied to the PLLFLTR pin of 1.2V

O

corresponds to a frequency of approximately 400kHz. The

nominal operating frequency range of the IC is 260kHz to

550kHz.

current is determined by the minimum on-time t

ON(MIN)

The phase detector used is an edge-sensitive digital type

which provides zero degrees phase shift between the ex-

ternal and internal oscillators. This type of phase detector

willnotlockuponinputfrequenciesclosetotheharmonics

of each controller (typically 100ns), the input voltage and

inductor value:

ΔI

L(SC)

= t

(V /L)

ON(MIN) IN

of the VCO center frequency. The PLL hold-in range, Δf ,

The resulting short-circuit current is:

H

is equal to the capture range, Δf

C:

25mV

R_SENSE

1

2

I_SC=

– ∆I_L(SC)

Δf = Δf = 0.5 f (260kHz-550kHz)

H

C

O

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23

LTC3728L/LTC3728LX

applicaTions inForMaTion

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter network on the PLLFLTR pin.

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

If the external frequency (f

) is greater than the os-

PLLIN

cillator frequency, f , current is sourced continuously,

Thetypicaltestedminimumon-timeis100nsunderanideal

0SC

pullingupthePLLFLTRpin.Whentheexternalfrequencyis conditionwithoutswitchingnoise.However,theminimum

less than f , current is sunk continuously, pulling down

on-time can be affected by PCB switching noise in the

voltage and current loops. With a reasonably good PCB

layout, a minimum 30% inductor current ripple, approxi-

mately 15mV sensing ripple voltage and 200ns minimum

on-time are conservative estimates for starting a design.

0SC

the PLLFLTR pin. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

thephasedifference. Thus, thevoltageonthePLLFLTRpin

is adjusted until the phase and frequency of the external

and internal oscillators are identical. At this stable operat-

ing point, the phase comparator output is open and the

FCB Pin Operation

The FCB pin can be used to regulate a secondary winding

or as a logic-level input. Continuous operation is forced

on both controllers when the FCB pin drops below 0.8V.

During continuous mode, current flows continuously in

the transformer primary. The secondary winding(s) draw

current only when the bottom, synchronous switch is on.

filter capacitor C holds the voltage. The IC’s PLLIN pin

LP

must be driven from a low impedance source such as a

logic gate located close to the pin. When using multiple

ICs for a phase-locked system, the PLLFLTR pin of the

master oscillator should be biased at a voltage that will

guarantee the slave oscillator(s) ability to lock onto the

master’s frequency. A DC voltage of 0.7V to 1.7V applied

to the master oscillator’s PLLFLTR pin is recommended

in order to meet this requirement. The resultant operating

frequency can range from 300kHz to 500kHz.

When primary load currents are low and/or the V /V

IN OUT

ratio is low, the synchronous switch may not be on for a

sufficientamountoftimetotransferpowerfromtheoutput

capacitortothesecondaryload.Forcedcontinuousopera-

tion will support secondary windings providing there is

sufficient synchronous switch duty factor. Thus, the FCB

input pin removes the requirement that power must be

drawn from the inductor primary in order to extract power

from the auxiliary windings. With the loop in continuous

mode, the auxiliary outputs may nominally be loaded

without regard to the primary output load.

The loop filter components (C , R ) smooth out the

LP LP

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components, C and R , determine how fast the loop

LP

acquires lock. Typically, R = 10kΩ and C is 0.01µF

LP

to 0.1µF.

Minimum On-Time Considerations

Minimum on-time, t , is the smallest time dura-

The secondary output voltage, V , is normally set as

SEC

shown in Figure 6a by the turns ratio N of the transformer:

ON(MIN)

V

SEC

@ (N + 1) V

OUT

tion that each controller is capable of turning on the top

MOSFET. It is determined by internal timing delays and the

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

However, if the controller goes into Burst Mode operation

and halts switching due to a light primary load current,

then V

SEC

will droop. An external resistive divider from

SEC

V

to the FCB pin sets a minimum voltage V

:

SEC(MIN)

R6

R5

V_OUT





V_SEC(MIN)≈ 0.8V 1+

t_ON(MIN)

<









V (f)

IN

where R5 and R6 are shown in Figure 2.

3728lxff

24

LTC3728L/LTC3728LX

applicaTions inForMaTion

If V

drops below this level, the FCB voltage forces

The resistive load reduces the DC loop gain while main-

taining the linear control range of the error amplifier. The

maximum output voltage deviation can theoretically be

reduced to half, or alternatively the amount of output

capacitance can be reduced for a particular application.

A complete explanation is included in Design Solutions

10 (see www.linear.com).

SEC

temporary continuous switching operation until V

again above its minimum.

is

SEC

In order to prevent erratic operation if no external connec-

tions are made to the FCB pin, the FCB pin has a 0.18µA

internal current source pulling the pin high. Include this

current when choosing resistor values R5 and R6.

The following table summarizes the possible states avail-

able on the FCB pin:

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

Table 1

FCB Pin

Condition

0V to 0.75V

Forced Continuous Both Controllers

(Current Reversal Allowed— Burst Inhibited)

0.85V < V < 4.3V

Minimum Peak Current Induces

Burst Mode Operation

No Current Reversal Allowed

FCB

%Efficiency = 100% – (L1 + L2 + L3 + ...)

Feedback Resistors

>4.8V

Regulating a Secondary Winding

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Burst Mode Operation Disabled

Constant-Frequency Mode Enabled

No Current Reversal Allowed

No Minimum Peak Current

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3728L/LTC3728LX circuits: 1) IC V current

Voltage Positioning

IN

(including loading on the 3.3V internal regulator), 2) IN-

Voltage positioning can be used to minimize peak-to-peak

output voltage excursions under worst-case transient

loading conditions. The open-loop DC gain of the control

loop is reduced depending upon the maximum load step

specifications. Voltage positioning can easily be added

2

TV regulator current, 3) I R losses, 4) Topside MOSFET

CC

transition losses.

1.The V current has two components: the first is the

IN

DC supply current given in the Electrical Characteristics

table, which excludes MOSFET driver and control cur-

rents; the second is the current drawn from the 3.3V

to either or both controllers by loading the I pin with

TH

a resistive divider having a Thevenin equivalent voltage

source equal to the midpoint operating voltage range of

the error amplifier, or 1.2V (see Figure 8).

linear regulator output. V current typically results in

a small (<0.1%) loss.

IN

2.INTV current is the sum of the MOSFET driver and

CC

controlcurrents.TheMOSFETdrivercurrentresultsfrom

switching the gate capacitance of the power MOSFETs.

Each time a MOSFET gate is switched from low to high

INTV

CC

R

T2

T1

I

TH

LTC3728L/

LTC3728LX

to low again, a packet of charge dQ moves from INTV

R

CC

C

to ground. The resulting dQ/dt is a current out of INTV

C

CC

C

that is typically much larger than the control circuit

current. In continuous mode, I = f(Q + Q ),

3728 F08

GATECHG

T

B

where Q and Q are the gate charges of the topside

T

B

Figure 8. Active Voltage Positioning

Applied to the LTC3728L/LTC3728LX

and bottom side MOSFETs.

3728lxff

25

LTC3728L/LTC3728LX

applicaTions inForMaTion

Supplying INTV power through the EXTV switch

losses can be minimized by making sure that C has ad-

CC

IN

input from an output-derived source will scale the V

equate charge storage and very low ESR at the switching

frequency. A 25W supply will typically require a minimum

of20µFto40µFofcapacitancehavinga maximumof20mΩ

to 50mΩ of ESR. The LTC3728L 2-phase architecture

typically halves this input capacitance requirement over

competingsolutions.Otherlosses,includingSchottkycon-

duction losses during dead time and inductor core losses,

generally account for less than 2% total additional loss.

IN

current required for the driver and control circuits by

a factor of (Duty Cycle)/(Efficiency). For example, in a

20V to 5V application, 10mA of INTV current results

CC

in approximately 2.5mA of V current. This reduces the

IN

mid-current loss from 10% or more (if the driver was

powered directly from V ) to only a few percent.

IN

2

3.I R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resis-

tor, and input and output capacitor ESR. In continuous

mode the average output current flows through L and

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

R

, but is “chopped” between the topside MOSFET

SENSE

andthesynchronousMOSFET. IfthetwoMOSFETshave

load current. When a load step occurs, V

shifts by an

approximately the same R

, then the resistance of

OUT

DS(ON)

amount equal to ΔI

(ESR), where ESR is the effective

oneMOSFETcansimplybesummedwiththeresistances

LOAD

2

series resistance of C . ΔI

also begins to charge or

of L, R

and ESR to obtain I R losses. For example,

DS(ON)

= 40mΩ (sum of both input and output ca-

OUT

LOAD

SENSE

if each R

discharge C

generating the feedback error signal that

= 30mΩ, R = 50mΩ, R

= 10mΩ

OUT

L

SENSE

forces the regulator to adapt to the current change and

and R

ESR

return V

time, V

to its steady-state value. During this recovery

can be monitored for excessive overshoot or

pacitance losses), then the total resistance is 130mΩ.

This results in losses ranging from 3% to 13% as the

output current increases from 1A to 5A for a 5V output,

or a 4% to 20% loss for a 3.3V output. Efficiency var-

OUT

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be

optimized over a wide range of output capacitance and

ies as the inverse square of V

for the same external

OUT

ESR values. The availability of the I pin not only allows

components and output power level. The combined

effects of increasingly lower output voltages and higher

currents required by high performance digital systems

is not doubling, but quadrupling, the importance of loss

terms in the switching regulator system!

TH

optimization of control loop behavior but also provides

a DC coupled and AC filtered closed loop response test

point. The DC step, rise time and settling at this test

point truly reflects the closed loop response. Assuming a

predominantly second order system, phase margin and/

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also be

4.Transition losses apply only to the topside MOSFET(s),

andbecomesignificantonlywhenoperatingathighinput

voltages(typically15Vorgreater). Transitionlossescan

be estimated from:

estimated by examining the rise time at the pin. The I

TH

external components shown in the Figure 1 circuit will

I

²



MAX

2

provide an adequate starting point for most applications.

Transition Loss =

V

•

R

•

(

)

(

)







IN

DR



The I series R -C filter sets the dominant pole-zero

TH

C











1

V

_TH

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the final PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

C

f

+

( )

)

MILLER

5V – V

TH

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these system level losses during the

design phase. The internal battery and fuse resistance

of full-load current having a rise time of 1µs to 10µs will

3728lxff

26

LTC3728L/LTC3728LX

applicaTions inForMaTion

produce output voltage and I pin waveforms that will

Automotive Considerations: Plugging into the

Cigarette Lighter

TH

give a sense of the overall loop stability without break-

ing the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

As battery-powered devices go mobile, there is a natural

interest in plugging into the cigarette lighter in order to

conserveorevenrechargebatterypacksduringoperation.

But before you connect, be advised: you are plugging

into the supply from hell. The main power line in an

automobile is the source of a number of nasty potential

transients, including load-dump, reverse-battery and

double-battery.

is why it is better to look at the I pin signal, which is

TH

in the feedback loop and is the filtered and compensated

Load-dump is the result of a loose battery cable. When the

cable breaks connection, the field collapse in the alterna-

tor can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse-battery is

just what it says, while double-battery is a consequence of

tow truck operators finding that a 24V jump start cranks

cold engines faster than 12V.

control loop response. The gain of the loop will be in-

creased by increasing R and the bandwidth of the loop

C

will be increased by decreasing C . If R is increased by

C

the same factor that C is decreased, the zero frequency

C

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

ThenetworkshowninFigure9isthemoststraightforward

approachtoprotectaDC/DCconverterfromtheravagesof

anautomotivepowerline.Theseriesdiodepreventscurrent

from flowing during reverse-battery, while the transient

suppressor clamps the input voltage during load-dump.

Note that the transient suppressor should not conduct

during double-battery operation, but must still clamp the

input voltage below breakdown of the converter. Although

the LTC3728L/LTC3728LX have a maximum input voltage

of 30V, most applications will also be limited to 30V by

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C , causing a rapid drop in V . No regulator can

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

C

LOAD

to C

is greater than 1:50, the switch rise time

OUT

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10µF capacitor would

the MOSFET BVD .

SS

LOAD

require a 250µs rise time, limiting the charging current

to about 200mA.

50A I RATING

PK

V

IN

12V

LTC3728L/

LTC3728LX

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

1.5KA24A

3728 F09

Figure 9. Automotive Application Protection

3728lxff

27

LTC3728L/LTC3728LX

applicaTions inForMaTion

Design Example

Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields

an output voltage of 1.816V.

As a design example for one channel, assume V = 12V

IN

(nominal), V = 22V(max), V

= 1.8V, I

= 5A and

ThepowerdissipationonthetopsideMOSFETcanbeeasily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

IN

OUT

MAX

f = 300kHz.

results in: R

= 0.035Ω/0.022Ω, C

= 215pF. At

DS(ON)

MILLER

Theinductancevalueischosenfirstbasedona30%ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. Tie the PLLFLTR

maximum input voltage with T(estimated) = 50°C:

1.8V

22V

2

P_MAIN

=

5

( )

1+ (0.005)(50°C – 25°C) •

[

]

pin to a resistive divider from the INTV pin, generating

CC

0.7V for 300kHz operation. The minimum inductance for

5A

2

₂



0.035Ω + 22V

) (

4Ω 215pF •

)(

(

)

(

)









30% ripple current is:













V_OUT

(f)(L)

V_OUT

1





∆I_L=

1–

+

300kHz = 332mW

(

)









V

IN

5 – 2.3 2.3

A 4.7µH inductor will produce 23% ripple current and a

3.3µH will result in 33%. The peak inductor current will be

the maximum DC value plus one half the ripple current, or

5.84A,forthe3.3µHvalue.Increasingtheripplecurrentwill

alsohelpensurethattheminimumon-timeof200nsisnot

A short-circuit to ground will result in a folded back

current of:

25mV 1 120ns(22V)

I_SC=

–

= 2.1A









0.01Ω 2

3.3µH

violated. The minimum on-time occurs at maximum V :

IN

withatypicalvalueofR

andd =(0.005/°C)(20)=0.1.

DS(ON)

V_OUT

1.8V

t_ON(MIN)

=

= 273ns

The resulting power dissipated in the bottom MOSFET is:

V

_IN(MAX)f 22V(300kHz)

22V – 1.8V

22V

= 100mW

2

P

=

2.1A 1.125 0.022Ω

(

) (

)(

)

SYNC

The R

resistor value can be calculated by using the

maximum current sense voltage specification with some

accommodation for tolerances:

SENSE

which is less than under full-load conditions.

C is chosen for an RMS current rating of at least 3A at

60mV

5.84A

IN

R_SENSE

≤

≈ 0.01Ω

temperature assuming only this channel is on. C

is

OUT

chosen with an ESR of 0.02Ω for low output ripple. The

output ripple in continuous mode will be highest at the

maximum input voltage. The output voltage ripple due to

ESR is approximately:

Since the output voltage is below 2.4V, the output resistive

dividerwillneedtobesizedtonotonlysettheoutputvoltage

but also to absorb the SENSE pin’s specified input current.







V

= R (ΔI ) = 0.02Ω(1.67A) = 33mV

ESR L P–P

0.8V

ORIPPLE

R1

= 24k

(MAX)



2.4V – V



_OUT

0.8V

2.4V – 1.8V







= 32k







3728lxff

28

LTC3728L/LTC3728LX

applicaTions inForMaTion

PC Board Layout Checklist

–

+

4. Are the SENSE and SENSE leads routed together

with minimum PC trace spacing? The filter capacitor

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 10. Figure 11 illustrates the cur-

rent waveforms present in the various branches of the

2-phasesynchronousregulatorsoperatinginthecontinu-

ous mode. Check the following in your layout:

+

–

between SENSE and SENSE should be as close as

possible to the IC. Ensure accurate current sensing

with Kelvin connections at the SENSE resistor.

5. Is the INTV decoupling capacitor connected close to

CC

the IC, betweenthe INTV and the power ground pins?

CC

ThiscapacitorcarriestheMOSFETdriverscurrentpeaks.

Anadditional1µFceramiccapacitorplacedimmediately

1. ArethetopN-channelMOSFETsM1andM3locatedwith-

in 1cm of each other with a common drain connection

next to the INTV and PGND pins can help improve

CC

noise performance substantially.

at C ? Do not attempt to split the input decoupling for

IN

the two channels as it can cause a large resonant loop.

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2), and boost nodes (BOOST1, BOOST2) away

from sensitive small-signal nodes, especially from the

opposites channel’s voltage and current sensing feed-

back pins. All of these nodes have very large and fast

moving signals and therefore should be kept on the

output side of the LTC3728L/LTC3728LX and occupy

minimum PC trace area.

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

of C

must return to the combined C

(–) termi-

INTVCC

OUT

nals. The path formed by the top N-channel MOSFET,

Schottky diode and the C capacitor should have short

IN

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible

to the (–) terminals of the input capacitor by placing

the capacitors next to each other and away from the

Schottky loop just described.

7. Use a modified “star ground” technique: a low imped-

ance, large copper area central grounding point on

the same side of the PC board as the input and output

capacitors with tie-ins for the bottom of the INTV

CC

3. Do the LTC3728L/LTC3728LX V

pins’ resistive

OUT

OSENSE

decouplingcapacitor,thebottomofthevoltagefeedback

dividersconnecttothe(+)terminalsofC ?Theresis-

resistive divider and the SGND pin of the IC.

tive divider mustbe connected between the(+) terminal

of C

and signal ground. The R2 and R4 connections

OUT

should not be along the high current input feeds from

the input capacitor(s).

3728lxff

29

LTC3728L/LTC3728LX

applicaTions inForMaTion

R

PU

V

PULL-UP

(<7V)

PGOOD

RUN/SS1

PGOOD

TG1

L1

R

SENSE

+

V

OUT1

SENSE1

–

SENSE1

SW1

R2

C

B1

R1

M1

M2

D1

V

BOOST1

OSENSE1

PLLFLTR

PLLIN

FCB

V

IN

f

IN

C

OUT1

BG1

EXTV

1µF

R

IN

CERAMIC

INTV

CC

C

VIN

GND

LTC3728L/LTC3728LX

INTV

I

TH1

CC

C

IN

V

IN

C

INTVCC

SGND

PGND

BG2

OUT2

D2

1µF

CERAMIC

3.3V

OUT

M4

M3

I

BOOST2

SW2

TH2

C

B2

V

OSENSE2

–

R

R3

R4

SENSE

V

SENSE2

TG2

OUT2

L2

+

RUN/SS2

3728 F10

Figure 10. LTC3728L/LTC3728LX Recommended Printed Circuit Layout Diagram

3728lxff

30

LTC3728L/LTC3728LX

applicaTions inForMaTion

SW1

L1

R

SENSE1

V

OUT1

+

D1

CERAMIC

C

R

L1

OUT1

V

IN

R

IN

+

C

IN

SW2

L2

R

SENSE2

V

OUT2

+

D2

C

R

L2

OUT2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

CERAMIC

3728 F11

Figure 11. Branch Current Waveforms

3728lxff

31

LTC3728L/LTC3728LX

applicaTions inForMaTion

PC Board Layout Debugging

Reduce V from its nominal level to verify operation of

IN

the regulator in dropout. Check the operation of the un-

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductorwhiletestingthecircuit.Monitortheoutputswitch-

ing node (SW pin) to synchronize the oscilloscope to the

internal oscillator and probe the actual output voltage as

well. Check for proper performance over the operating

voltage and current range expected in the application. The

frequencyofoperationshouldbemaintainedovertheinput

voltage range down to dropout and until the output load

dropsbelowthelowcurrentoperationthreshold—typically

10% to 20% of the maximum designed current level in

Burst Mode operation.

dervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawelldesigned, lownoisePCBimplementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required. Only after each

controllerischeckedforitsindividualperformanceshould

bothcontrollersbeturnedonatthesametime.Aparticularly

difficultregionofoperationiswhenonecontrollerchannel

is nearing its current comparator trip point when the other

channel is turning on its top MOSFET. This occurs around

50% duty cycle on either channel due to the phasing of

the internal clocks and may cause minor duty cycle jitter.

for inductive coupling between C , Schottky and the top

IN

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

The output voltage under this improper hookup will still

be maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

Short-circuit testing can be performed to verify proper

overcurrent latchoff, or 5µA can be provided to the RUN/

SS pin(s) by resistors from V to prevent the short-circuit

IN

latchoff from occurring.

3728lxff

32

LTC3728L/LTC3728LX

Typical applicaTions

59k

1M

100k

MBRS1100T3

V

+

PULL-UP

33µF

25V

(<7V)

T1, 1:1.8

10µH

PGOOD

TG1

PGOOD

RUN/SS1

0.015Ω

D1

V

0.1µF

OUT1

+

5V

SENSE1

M1

3A; 4A PEAK

180pF

1000pF

8

–

SW1

SENSE1

105k, 1%

5

20k

1%

Q1

Q2

0.1µF

LT1121

ON/OFF

BOOST1

V

OSENSE1

3

2

1

220k

V

12V

120mA

OUT3

V

IN

PLLFLTR

PLLIN

FCB

150µF, 6.3V

PANASONIC SP

BG1

+

33pF

1µF

25V

10Ω

22µF

50V

100k

CMDSH-3TR

EXTV

CC

0.1µF

GND

LTC3728L/LTC3728LX

INTV

I

CC

TH1

1µF

10V

15k

4.7µF

180µF, 4V

PANASONIC SP

1000pF

V

PGND

BG2

SGND

IN

7V TO

28V

33pF

M2

CMDSH-3TR

3.3V

OUT

Q3

Q4

D2

BOOST2

SW2

I

TH2

15k

0.1µF

V

OSENSE2

–

20k

1%

V

OUT2

3.3V

5A; 6A PEAK

TG2

SENSE2

63.4k

1%

0.01Ω

1000pF

L1

6.3µH

+

RUN/SS2

SENSE2

180pF

0.1µF

3728 F12

V

: 7V TO 28V

IN

: 5V, 3A/3.3V, 6A/12V, 150mA

OUT

SWITCHING FREQUENCY = 250kHz

MI, M2: FDS6982S OR VISHAY Si4810DY

L1: SUMIDA CEP123-6R3MC

T1: 10µH 1:1.8 — DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID

Figure 12. LTC3728L/LTC3728LX High Efficiency Low Noise 5V/3A, 3.3V/5A, 12V/120mA Regulator

3728lxff

33

LTC3728L/LTC3728LX

Typical applicaTions

V

PULL-UP

(<7V)

L1

4.3µH

PGOOD

RUN/SS1

PGOOD

TG1

0.008Ω

0.1µF

V

+

OUT1

SENSE1

5V/4A

180pF

1000pF

105k

1%

–

SENSE1

SW1

20k

1%

0.1µF

Q1

Q2

V

BOOST1

OSENSE1

PIN 4

M1

PLLFLTR

PLLIN

FCB

V

0.01µF

1µF 50V

IN

10k

1000pF

f

SYNC

BG1

100pF

10Ω

22µF

50V

CMDSH-3TR

EXTV

CC

150µF, 6.3V

180µF, 4V

0.1µF

GND

LTC3728L/LTC3728LX

INTV

I

TH1

CC

1µF 50V

8.06k

1µF

4.7µF, 10V

1500pF

1000pF

SGND

PGND

BG2

V

100pF

IN

CMDSH-3TR

7V TO

28V

3.3V

OUT

PIN 4

I

BOOST2

SW2

Q3

Q4

TH2

4.75k

0.1µF

V

OSENSE2

–

20k

1%

M2

V

OUT2

SENSE2

TG2

3.3V/5A

0.008Ω

63.4k

1%

1000pF

L2

4.3µH

+

180pF

RUN/SS2

0.1µF

: 7V TO 28V

3728 F13

V

SWITCHING FREQUENCY = 250kHz TO 550kHz

M1, M2: FDS6982S OR VISHAY Si4810DY

L1, L2: SUMIDA CDEP105-4R3MC-88

OUTPUT CAPACITORS: PANASONIC SP SERIES

IN

: 5V, 4A/3.3V, 5A

OUT

Figure 13. LTC3728L/LTC3728LX 5V/4A, 3.3V/5A Regulator with External Frequency Synchronization

3728lxff

34

LTC3728L/LTC3728LX

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.386 – .393*

(9.804 – 9.982)

.045 .005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 .004

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

(0.38 0.10)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

3728lxff

35

LTC3728L/LTC3728LX

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

0.70 0.05

5.50 0.05

4.10 0.05

3.45 0.05

3.50 REF

(4 SIDES)

3.45 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

0.00 – 0.05

R = 0.115

TYP

0.75 ± 0.05

5.00 ± 0.10

(4 SIDES)

31 32

0.40 ± 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 ± 0.10

3.50 REF

(4-SIDES)

3.45 ± 0.10

(UH32) QFN 0406 REV D

0.200 REF

0.25 0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3728lxff

36

LTC3728L/LTC3728LX

revision hisTory ^{(Revision history begins at Rev F)}

REV

DATE

12/11 Added labels D1 and D2 to the Typical Application.

Corrected pin name for the GN Package Pin 3 to SENSE1 .

Changed Note 3 to Note 8 on g on the Electrical Characteristics Table.

DESCRIPTION

PAGE NUMBER

F

1

2

–

4

mGBW1,2

Added new Note 8: Guaranteed by design.

5

Updated threshold on BINH to 4.3V on the Functional Diagram.

11

36

Updated threshold on EXTV to 4.7V on the Functional Diagram.

CC

Replaced the Related Parts list.

3728lxff

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

37

LTC3728L/LTC3728LX

Typical applicaTion

I

IN

12V

IN

C

IN

I

1

I

IN

*

0°

BUCK: 2.5V/15A

OPEN

PHASMD TG1

180°

I

1

2

3

4

2.5V /30A

O

TG2

U1

LTC3729

I

90°

2

3

I

CLKOUT

I

1.5V /15A

O

90°

BUCK: 1.5V/15A

BUCK: 1.8V/15A

TG1

270°

1.8V /15A

O

U2

TG2

LTC3728L/

LTC3728LX

PLLIN

*INPUT RIPPLE CURRENT CANCELLATION

INCREASES THE RIPPLE FREQUENCY AND

REDUCES THE RMS INPUT RIPPLE CURRENT

THUS, SAVING INPUT CAPACITORS

I

90°

4

3728 F14

Figure 14. Multioutput PolyPhase^®Application

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

2

LTC3880/LTC3880-1 Dual Output PolyPhase Step-Down DC/DC Controller with

Digital Power System Management

I C/PMBus Interface with EEPROM and 16-Bit ADC

V

Up to 24V, 0.5V ≤ V

≤ 5.5V, Analog Control Loop

IN

OUT

LTC3869/LTC3869-2 Dual Output, 2-Phase Synchronous Step-Down DC/DC Controller, PLL Fixed 250kHz to 750kHz Frequency, 4V ≤ V ≤ 38V,

IN

with Accurate Current Share

0.6V ≤ V

≤ 12.5V

OUT

LTC3855

LTC3838

LTC3860

Dual Output, 2-Phase, Synchronous Step-Down DC/DC Controller PLL Fixed Frequency 250kHz to 770kHz, 4.5V ≤ V ≤ 38V,

IN

with Differential Amplifier and DCR Temperature Compensation

0.8V ≤ V

≤ 12V

OUT

Dual, Multiphase, Controlled On-Time, High Frequency

Synchronous Step-Down Controller with Differential Amplifier

Up to 2MHz Operating Frequency, 4V ≤ V ≤ 38V,

IN

0.8V ≤ V

≤ 5.5V, 3mm × 4mm QFN-20, TSSOP-20E

OUT

Dual, Multiphase, Synchronous Step-Down DC/DC Controller with Operates with Power Blocks, DRMOS Devices or

Differential Amplifier and Three-State Output Drive External Drivers/MOSFETs, 3V ≤ V ≤ 24V, t

= 20ns

ON(MIN)

IN

LTC3850/LTC3850-1/ Dual Output, 2-Phase Synchronous Step-Down DC/DC Controller, PLL Fixed 250kHz to 780kHz Frequency, 4V ≤ V ≤ 30V,

IN

LTC3850-2

R

or DCR Current Sensing

0.8V ≤ V

≤ 5.25V

OUT

SENSE

LTC3856

Single Output 2-Channel Synchronous Step-Down DC/DC

PLL Fixed 250kHz to 770kHz Frequency, 4.5V ≤ V ≤ 38V,

IN

Controller with Differential Amplifier and Up to 12-Phase Operation 0.8V ≤ V

≤ 5V

OUT

LTC3829

LTC3853

Single Output 3-Channel Synchronous Step-Down DC/DC

Phase-Lockable Fixed 250kHz to 770kHz Frequency,

≤ 5V

Controller with Differential Amplifier and Up to 6-Phase Operation 4.5V ≤ V ≤ 38V, 0.8V ≤ V

IN

OUT

Triple Output, Multiphase Synchronous Step-Down DC/DC

Controller, R or DCR Current Sensing and Tracking

PLL Fixed 250kHz to 750kHz Frequency, 4V ≤ V ≤ 24V,

IN

V

Up to 13.5V

OUT3

SENSE

3728lxff

LT 1211 REV F • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

38

●

 LINEAR TECHNOLOGY CORPORATION 2002

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3728LCGN#PBF
厂家：	Linear
描述：	LTC3728L and LX - Dual, 550kHz, 2-Phase Synchronous Regulators; Package: SSOP; Pins: 28; Temperature Range: 0°C to 70°C 开关光电二极管
文件：	总38页 (文件大小：449K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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