LTC3738CUHF_技术文档

LTC3738

3-Phase Buck Controller

for Intel VRM9/VRM10 with

Active Voltage Positioning

U

FEATURES

DESCRIPTIO

TheLTC^®3738isa3-phasesynchronousstep-downswitch-

ing regulator controller that drives all N-channel external

power MOSFET stages in a phase-lockable, fixed fre-

quency architecture. The 3-phase technique effectively

triples the fundamental frequency, improving transient

response while operating each controller at an optimal

frequency for efficiency and ease of thermal design. Light

load efficiency is optimized by using a choice of output

Stage Shedding or Pulse Skip mode technology.

■

3-Phase Controller with Onboard MOSFET Drivers

■

Programmable Active Voltage Positioning (AVP)

with True Current Sensing

■

Programmable External Thermal Detection or

Internal Thermal Sensing

■

Precise Output Current Matching Optimizes

Thermal Performance and Solution Size

■

Supports Starting into Precharged V_OUTS

■

Differential Amplifier Accurately Senses V_OUT

PWM, Pulse Skip and Stage Shedding^TMOperation

■

The LTC3738 also allows users to program load slope via

a resistor for AVP control. Both external and internal

thermal sensing are available from the on-chip thermal

detector and comparator.

■

Synchronizable

■

210kHz to 530kHz Per Phase, Fixed Frequency

■

Output Power Good Indicator with Adaptive Blanking

■

Adjustable Soft-Start Current Ramping

■

A differential amplifier provides sensing of both the high

and low sides of the output voltage.

Short-Circuit Shutdown Timer with Defeat Option

OPTI-LOOP^®Compensation Minimizes C_OUT

38-Lead (5mm × 7mm) QFN Package

U

Soft-start and a defeatable, timed short-circuit shutdown

protect the MOSFETs and the load. A foldback current

circuit also provides protection for the external MOSFETs

under short-circuit or overload conditions. An all- “1” VID

detector turns off the regulator after a 1µs timeout.

APPLICATIO S

■

High Performance Notebook Computers

Servers, Desktop Computers and Workstations

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

OPTI-LOOP is a registered trademark of Linear Technology Corporation.

Stage Shedding is a trademark of Linear Technology Corporation.

U.S. Patent Numbers: 5481178, 5994885, 5929620, 6177787, 6144194, 6580258, 6462525,

6593724, 6674274, 6100678 pending on AVP technique.

U

TYPICAL APPLICATIO

VRM10 Step-Down Controller

V

IN

5V TO 28V

5V

V

TG1

SW1

BG1

CC

+

0.8µH

0.002Ω

22µF

×2

LTC3738

10µF

BOOST1

BOOST2

BOOST3

+

–

SENSE1

0.1µF

V

IN

SW3 SW2 SW1

POWER GOOD INDICATOR

MODE SELECTION/SYNC IN

TG2

PGOOD

FCB/SYNC

0.8µH

V

OUT

SW2

BG2

0.8375V TO 1.6000V

PLLFLTR

TSNS

VR_HOTB

OUTEN

THERMAL INPUT

VR HOT INDICATOR

ON/OFF

PGND

+

SENSE2

–

680pF

SENSE2

V

IN

I

TG3

SW3

BG3

TH

0.8µH

0.002Ω

5k

SS

0.1µF

SGND

EAIN

AVP

+

–

SENSE3

100pF

+

470µF

×4

+

–

IN

VID0-VID5

6 VID BITS

3738 TA01

3738f

1

LTC3738

W W U W

U W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

Topside Driver Voltages (BOOST_N)............38V to –0.3V

Switch Voltage (SW_N)...................................32V to –5V

Boosted Driver Voltage (BOOST_N– SW_N)....7V to –0.3V

Peak Output Current <1ms (TG_N, BG_N) ..................... 5A

Supply Voltage (V_CC), PGOOD, VR_HOTB

Pin Voltages ................................................7V to –0.3V

OUTEN, SS, PLLFLTR,

FCB/SYNC Voltages ................................... V_CCto –0.3V

I_THVoltage................................................2.4V to –0.3V

IN⁺, IN^–, VID0-VID5, TSNS .............................. 5V to 0V

AVP, SENSE⁺, SENSE^–.................................. 1.9V to 0V

Operating Ambient Temperature Range....... 0°C to 85°C

Junction Temperature (Note 2)............................. 125°C

Storage Temperature Range ..................–65°C to 125°C

38 37 36 35 34 33 32

FCB/SYNC

PLLFLTR

1

2

3

4

5

6

7

8

9

31 TG1

30 SW1

–

IN

BOOST2

29

28

+

IN

TG2

AVP

27 SW2

EAIN

V

CC

26

39

+

SENSE1

25 BG1

24 PGND

23 BG2

22 BG3

21 SW3

–

SENSE1

+

SENSE2

–

SENSE2 10

–

SENSE3 11

+

20

SENSE3 12

TG3

13 14 15 16 17 18 19

UHF PACKAGE

38-LEAD (7mm × 5mm) PLASTIC QFN

T_JMAX= 125°C, θ_JA= 34°C/W

EXPOSED PAD (PIN 39) IS SGND MUST BE SOLDERED TO PCB

ORDER PART

NUMBER

UHF PART

MARKING

LTC3738CUHF

3738

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= V_OUTEN= V_SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

+

V

Regulated Voltage at IN

(Note 3); VID Code = 110101, V = 1.2V

1.166

1.163

1.175

1.184

1.187

V

REGULATED

SENSEMAX

MATCH

ITH

●

Maximum Current Sense Threshold

V

= 0.5V, V Open,

65

62

75

85

88

mV

EAIN

ITH

– V

,

– = 0.8V, 1.85V

SENSE1

,

SENSE2

SENSE3

I

Current Match

Worst-Case Error at V

–5

5

%

SENSE(MAX)

V

Output Voltage Load Regulation

(Note 3)

LOADREG

Measured in Servo Loop, ∆I Voltage = 1.2V to 0.7V

Measured in Servo Loop, ∆I Voltage = 1.2V to 2V

●

0.1

–0.1

0.5

–0.5

%

TH

V

Output Voltage Line Regulation

V

= 4.5V to 7V

CC

0.03

3.05

1.5

%/V

mmho

MHz

V

REFLNREG

m

g

Transconductance Amplifier g

I

= 1.2V, Sink/Source 25µA (Note 3)

TH

m

Transconductance Amplifier GBW

Forced Continuous Threshold

FCB Bias Current

= 1.2V, (g • Z , Z = Series 1k-100kΩ-1nF)

m L L

mOL

TH

V

●

0.58

0.60

0.2

0.62

0.7

FCB

I

V

= 0.65V

µA

FCB

3738f

2

LTC3738

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= V_OUTEN= V_SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Pulse Skip Threshold

Undervoltage SS Reset

Measured at FCB pin

V

– 1.5 V – 0.7 V – 0.3

V

PSTH

CC

UVR

V

CC

Lowered Until the SS Pin is Pulled Low

3.3

3.8

4.5

I

Input DC Supply Current

Normal Mode

Shutdown

(Note 4)

Q

V

= 5V

2.5

20

mA

µA

CC

V

= 0V

100

0.8

OUTEN

V

OUTEN Pin ON Threshold

Soft-Start Charge Current

SS Pin Arming Threshold

V

, Ramping Positive

0.4

0.6

–1.5

3.8

V

µA

V

OUTEN

I

= 1.9V

–0.8

–2.5

4.5

SS

V

, Ramping Positive Until Short-Circuit

SSARM

Latch-Off is Armed

V

SS Pin Latch-Off Threshold

SS Discharge Current

V

, Ramping Negative

3.3

–1.5

1.5

V

µA

SSLO

SCL

SS

I

Soft-Short Condition V

= 0.3V, V = 4.5V

–5

95

EAIN

SS

Shutdown Latch Disable Current

Total SENSE Pins Source Current

V

EAIN

= 0.3V, V = 4.5V

5

SDLHO

SENSE

SS

+

–

+

–

SENSE1 , SENSE1 , SENSE2 , SENSE2 ,

SENSE3 , SENSE3 All Equal 1.2V

In Dropout

90

120

+

–

DF

Maximum Duty Factor

98.5

%

MAX

TG t t

Top Gate Rise Time

Top Gate Fall Time

C

LOAD

C

LOAD

= 3300pF

30

40

90

ns

R, F

BG t

t

Bottom Gate Rise Time

Bottom Gate Fall Time

C

LOAD

C

LOAD

= 3300pF

30

20

90

ns

R,

F

TG/BG t

BG/TG t

Top Gate Off to Bottom Gate On Delay All Controllers, C

Synchronous Switch-On Delay Time

= 3300pF Each Driver

60

ns

1D

LOAD

Bottom Gate Off to Top Gate On Delay All Controllers, C

Top Switch-On Delay Time

60

2D

LOAD

t

Minimum On-Time

Tested with a Square Wave (Note 5)

120

ON(MIN)

VID Parameters

VID

Maximum Low Level Input Voltage

Minimum High Level Input Voltage

VRM9 Enable Threshold at VID5

VID0 to VID4

0.4

V

IL

0.8

3.5

IH

VID9/VID10

ATTEN

V

– 1

4.5

V

CC

(Note 6)

●

–0.25

0.25

%

ERR

Power Good Output Indication

V

PGOOD Voltage Output Low

PGOOD Output Leakage

PGOOD Trip Thesholds

I

= 2mA

= 5V

0.1

0.3

V

PGL

PGOOD

I

V

±1

µA

PGOOD

V

with Respect to Set Output Voltage,

DIFFOUT

V

Ramping Negative

Ramping Positive

VID Code = 110101

PGOOD Goes Low After V

–7

7

–10

10

–14

14

%

PGTHNEG

PGTHPOS

DIFFOUT

Delay

UVDLY

t

Power Good Blanking

After VID Changes Outside PGOOD Window

100

µs

PGBLNK

3738f

3

LTC3738

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= V_OUTEN= V_SS= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Oscillator and Phase-Locked Loop

f

Nominal Frequency

Lowest Frequency

V

= 1.2V

= 0V

325

190

480

365

220

550

1.2

415

250

630

kHz

V

NOM

LOW

HIGH

PLLFLTR

Highest Frequency

= 2.4V

R

FCB Clock Input Threshold

FCB

I

Phase Detector Output Current

Sinking Capability

Sourcing Capability

PLL LPF

f

< f

20

µA

PLLIN

OSC

> f

R

Controller 2-Controller 1 Phase

Controller 3-Controller 1 Phase

120

240

Deg

RELPHS

No_CPU Detection

No-CPU Shutdown Latency

Differential Amplifier

t

After All VID Bits = “1”

0.5

0

1

µs

NOCPU

A

V

Differential Gain

1.000

0.5

V/V

mV

V

+

–

Input Offset Voltage

IN = IN = 1.2V, Input Referred

OS

CM

Common Mode Input Voltage Range

Common Mode Rejection Ratio

Gain Bandwidth Product

Maximum High Output Voltage

Input Resistance

5

+

–

CMRR

GBP

0V < IN = IN < 5V, Input Referred

70

2

dB

MHz

V

– 0.8

CC

O(MAX)

+

R

Measured at IN Pin

160

kΩ

IN

Active Voltage Positioning

+

I

Sinking Current Ability of AVP Pin

Sourcing Current Ability of AVP Pin

IN = 1.2V

0.250

1.4

mA

mV

SINK

+

IN = 1.2V

SOURCE

+

V

– V

Max Voltage Drops V

to VO

IN = 1.2V, V = 60mV

180

AVP

O(MAX)

AVP

IN

Thermal Detection

V

Thermal Comparator Trip Threshold

Hysteresis

1.67

0.21

V

INT

INT_HYS

TH_TH

Internal Detection Enable Threshold

3.4

V

– 1

CC

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 5: The minimum on-time condition corresponds to an inductor peak-

to-peak ripple current of ≥40% of I (see minimum on-time

MAX

considerations in the Applications Information Section).

Note 2: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formula:

Note 6: ATTEN specification is in addition to the output voltage

accuracy specified at VID code 110101.

D

ERR

T = T + (P × 34°C/W)

J

A

D

Note7:ThisICincludesovertemperatureprotectionthatisintendedtoprotect

the device during momentary overload conditions. Junction temperature will

exceed125°Cwhenovertemperatureprotectionisactive.Continuousoperation

above the specified maximum operating junction temperature may impair

device reliability.

Note 3: The IC is tested in a feedback loop that includes the differential

amplifier driving the VID DAC into the error amplifier and servoing the

resultant voltage to the midrange point for the error amplifier (V = 1.2V).

ITH

Note 4: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

3738f

4

LTC3738

U W

TYPICAL PERFOR A CE CHARACTERISTICS ^T_A^{= 25°C unless otherwise noted.}

Efficiency vs I_OUT

Efficiency vs V_IN

Efficiency vs Frequency

100

90

92

91

92

91

90

89

V

= 12V

IN

FREQUENCY = 210kHz

V

= 5V

FCB/SYNC

V

= 5V

80

70

60

IN

I

= 20A

L

90

V

= OPEN

FCB/SYNC

V

= 10V

= 14V

IN

89

88

87

86

V

= 0V

FCB/SYNC

50

40

88

87

V

IN

I

= 50A

L

30

20

10

0

86

85

84

V

I

= 12V

V

= 12V

IN

OUT

IN

OUT

= 1.2V

= 20A

= 1.2V

FREQUENCY = 210kHz

10 100

INDUCTOR CURRENT (A)

LOAD

85

0.1

14

1

4

7

9

10 11 12 13

(V)

5

6

8

250

300

400

200

450

500

350

V

FREQUENCY (kHz)

IN

3738 G01

3733 G02

3738 G03

Reference Voltage

vs Temperature

Error Amplifier g_m

vs Temperature

Maximum I_SENSEThreshold

vs Temperature

610

605

600

595

590

4.0

3.5

3.0

2.5

2.0

85

80

75

70

65

V

= 1.85V

= 0.8V

O

V

O

–45

0

15 30 45 60 75 90

–45

0

15 30 45 60 75 90

–45

–30 –15

0

15 30 45 60 75 90

–30 –15

TEMPERATURE (°C)

3738 G04

3738 G05

3738 G06

Oscillator Frequency

vs Temperature

Undervoltage Reset Voltage

vs Temperature

Oscillator Frequency vs V_PLLFLTR

600

550

500

450

400

350

300

250

200

150

100

550

500

450

400

350

300

250

200

5.0

4.5

4.0

3.5

3.0

V

= 5V

PLLFLTR

V

= 2.4V

PLLFLTR

V

= 1.2V

= 0V

PLLFLTR

V

PLLFLTR

–45

0

15 30 45 60 75 90

0

0.8

1.2

2.0

2.4

–45

–30 –15

0

15 30 45 60 75 90

–30 –15

0.4

1.6

(V)

TEMPERATURE (°C)

V

TEMPERATURE (°C)

PLLFLTR

3738 G07

3738 G08

3738 G09

3738f

5

LTC3738

TYPICAL PERFOR A CE CHARACTERISTICS ^T_A^{= 25°C unless otherwise noted.}

U W

Short-Circuit Arming and Latchoff

vs Temperature

Shutdown Current

vs Temperature

Supply Current vs Temperature

2.9

2.7

2.5

2.3

2.1

1.9

65

60

55

50

45

40

35

30

25

5.0

4.5

4.0

3.5

3.0

2.5

2.0

ARMING

LATCHOFF

–45

0

15 30 45 60 75 90

–45

–30 –15

0

15 30 45 60 75 90

0

15 30 45 60 75 90

TEMPERATURE (°C)

–30 –15

–45

–30 –15

TEMPERATURE (°C)

3738 G11

3738 G12

3738 G10

Maximum Current Sense

Threshold vs Duty Factor

SS Pull-Up Current

vs Temperature

Peak Current Threshold vs V_ITH

2.5

2.0

1.5

1.0

0.5

0

75

50

25

0

90

80

70

60

50

40

30

20

10

0

–10

–20

–45

0

15 30 45 60 75 90

0

40

60

80

100

0

1.2

(V)

1.6

2.0

2.4

–30 –15

20

0.4

0.8

TEMPERATURE (°C)

DUTY FACTOR (%)

V

ITH

3738 G13

3738 G14

3738 G15

Maximum Duty Factors

vs Temperature

Percentage of Nominal Output

vs Peak I_SENSE(Foldback)

Total I_SENSECurrent vs V_OUT

80

70

60

50

40

30

20

10

0

100

98

96

94

92

90

0

–20

V

= 0V

PLLFLTR

–40

–60

–80

–100

–120

–140

–160

–180

0

40 50 60 70 80 90 100

–45

0

15 30 45 60 75 90

0

0.2 0.4 0.6 0.8

1

2

10 20 30

–30 –15

1.2 1.4 1.6 1.8

(V)

PERCENTAGE OF NOMINAL OUTPUT VOLTAGE (%)

TEMPERATURE (°C)

V

OUT

3738 G16

3738 G17

3738 G18

3738f

6

LTC3738

U W

TYPICAL PERFOR A CE CHARACTERISTICS ^T_A^{= 25°C unless otherwise noted.}

Maximum Current Threshold

Mismatch vs Temperature

(V_AVP– V_IN⁺) vs

–

(V_SENSE⁺– V_SENSE

)

3.0

2.5

2.0

1.5

1.0

0.5

0

180

135

90

45

0

–45

0

15 30 45 60 75 90

–30 –15

–15

0

15

+

30

–

45

60

TEMPERATURE (°C)

V

– V

(mV)

SENSE

3738 G19

3738 G20

Shed Mode at 1A,

Light Load Current

Pulse Skip Mode at 1A,

Light Load Current

V

OUT

10mV/DIV

V

SW1

5V/DIV

V

SW1

5V/DIV

V

SW2

5V/DIV

V

SW3

V

SW3

5V/DIV

3738 G21

3738 G22

V

= 12V

2µs/DIV

V

= 12V

2µs/DIV

IN

= 1.5V

OUT

FCB

OUT

FCB

= V

= OPEN

CC

FREQUENCY = 210kHz

Continuous Mode at 1A,

Light Load Current

Load Transient with AVP

V

OUT

10mV/DIV

INTEL

SPEC

V

OUT

80mV

50mV/DIV

∆I

V

OUT

SW1

100A STEP

5V/DIV

dI/dt > 200A/µs

V

SW2

5V/DIV

V

SW3

3738 G24

5V/DIV

V

C

= 12V

IN

= 1.35V

OUT

3738 G23

= 10 × 330µF/2.5V

V

= 12V

2µs/DIV

IN

SANYO TPE POSCAP

= 1.5V

= GND

OUT

FCB

+ 18 × 22µF/X5R CERAMIC

FREQUENCY = 210kHz

3738f

7

LTC3738

U

PI FU CTIO S

FCB/SYNC (Pin 1): Forced Continuous Control Input. The

voltage applied to this pin sets the operating mode of the

controller. The forced continuous current mode is active

when the applied voltage is less than 0.6V. Pulse skip

mode operation will be active when the pin is allowed to

float and Stage Shedding mode will be active if the pin is

tied to the V_CCpin. When an external clock is present, the

controller will be synchronized to the external clock and

forced continuous mode is selected internally. (Do not

apply voltage to this pin prior to the application of voltage

on the V_CCpin.)

SS (Pin 13): Combination of Soft-Start and Short-Circuit

Detection Timer. A capacitor to ground at this pin sets the

ramp time to full current output as well as the time delay

prior to an output voltage short-circuit shutdown.

I

_TH(Pin 14): Error Amplifier Output and Switching Regu-

lator Compensation Point. All three current comparator’s

thresholds increase with this control voltage.

TSNS (Pin 15): This pin selects external or internal ther-

mal detection. Tying this pin to V_CCwill enable the internal

thermal detector. When the voltage at this pin is less than

V

_CC– 1.6V, the internal thermal detector is disabled and

PLLFLTR (Pin 2): The phase-locked loop’s lowpass filter

is tied to this pin. Alternatively, this pin can be driven with

an AC or DC voltage source to vary the frequency of the

internal oscillator. (Do not apply voltage to this pin prior to

the application of voltage on the V_CCpin.)

IN⁺, IN^–(Pins 4, 3): Inputs to a Precision, Unity-Gain

Differential Amplifier with Internal Precision Resistors.

This provides true remote sensing of both the positive and

negative load terminals for precise output voltage control.

this pin serves as the input to an internal comparator

which is referenced to V_CC/3.

VR_HOTB (Pin 16): This open-collector output is pulled

low when voltage at the TSNS pin is less than V_CC/3. If

TSNS is tied to V_CC, this pin is pulled low when the internal

thermal detector is tripped.

PGND (Pin 24): Driver Power Ground. This pin connects

to the sources of the bottom N-channel external MOSFETs

and the (–) terminals of C_IN.

AVP (Pin 5): Active Voltage Positioning Load Slope Pro-

gramming Pin. A resistor tied between this pin and IN⁺

sets the load slope.

BG1, BG2, BG3 (Pins 25, 23, 22): High Current Gate

DrivesfortheBottomN-ChannelMOSFETs.Voltageswing

at these pins is from ground to V_CC.

EAIN (Pin 6): This is the input to the error amplifier which

compares the VID divided feedback voltage to the internal

0.6V reference voltage.

SENSE1⁺, SENSE2⁺, SENSE3⁺, SENSE1^–, SENSE2^–,

SENSE3^–(Pins 7 to 12): The Inputs to Each Differential

Current Comparator. The I_THpin voltage and built-in

offsetsbetweentheSENSE^–andSENSE⁺pins, inconjunc-

tion with R_SENSE, set the current trip threshold level.

V_CC(Pin 26): Main Supply Pin. Because this pin supplies

both the controller circuit power as well as the high power

pulses supplied to drive the external MOSFET gates, this

pin needs to be very carefully and closely decoupled to the

IC’s PGND pin.

3738f

8

LTC3738

U

PI FU CTIO S

SW1, SW2, SW3 (Pins 30, 27, 21):Switch Node Connec-

tions to Inductors. Voltage swing at these pins is from a

Schottky diode (external) voltage drop below ground to

V_IN(where V_INis the external MOSFET supply rail).

PGOOD (Pin 33): This open-drain output is pulled low

when the output voltage is outside the PGOOD tolerance

window. PGOOD is blanked during VID transitions for

approximately 100µs.

TG1,TG2,TG3(Pins31,28,20):HighCurrentGateDrives

for Top N-Channel MOSFETs. These are the outputs of the

floating drivers with a voltage swing equal to the boost

voltage source superimposed on the switch node voltage

SW.

VID0,VID1,VID2,VID3,VID4,VID5(Pins35,36,37,17,

18, 34): Output Voltage Programming Input Pins. When

VID5 is tied to V_CC, the Intel VRM9 VID table is selected.

When voltage of VID5 is less than V_CC– 2V, VID5 serves

as the fifth VID bit of VRM10.

BOOST1, BOOST2, BOOST3 (Pins 32, 29, 19): Positive

Supply Pins to the Topside Floating Drivers. Bootstrapped

capacitors, charged with external Schottky diodes and a

boostvoltagesourceareconnectedbetweentheBOOSTand

SWpins.VoltageswingattheBOOSTpinsisfromtheboost

source voltage (typically V_CC) to this boost source voltage

+V_IN(where V_INis the external MOSFET supply rail).

OUTEN (Pin 38): On/Off Control of the Controller.

SGND (Pin 39, Exposed Pad): Signal Ground. This pin

must be soldered to the ground plane.

3738f

9

LTC3738

U

W

FU CTIO AL DIAGRA

TSNS

PGOOD

0.66V

EAIN

–

+

2.4V

VR_HOTB

100µs

TCMP

–

+

BLANKING

–

+

2.5µA

V /3

CC

FCB/SYNC

VID TRANSITIONS

0.54V

MUX

+

INTERNAL

THERMAL

DETECTION

FCB

–

0.6V

PHASE DET

PLLFLTR

V

CC

V

IN

R

LP

DUPLICATE FOR SECOND AND THIRD

CONTROLLER CHANNELS

CLK1

D

B

BOOST

TG

C

LP

CLK2

CLK3

OSCILLATOR

DROP

OUT

DET

C

B

+

TOP

BOT

RS

LATCH

FORCED BOT

TOP ON

C

IN

–

+

IN

S

Q

SW

80k

SWITCH

LOGIC

R

Q

–

V

CC

A1

+

BG

IN

FCB

80k

+

PGND

R

SHDN

PRE-AVP

AVP

+

SENSE1

–

+

–

+

–

+

–

SENSE1

SENSE2

SENSE3

–

+

–

+

–

+

–

I

L

I

V

–

+

–

2

1

CC

+

R

AVP

+

SENSE

30k

3mV

R1

8k

SLOPE

COMP

ADDER

R

SENSE

–

C

OUT

SENSE

EAIN

V

FB

30k

5(V

FB

)

–

+

EA

0.600V

45k

V

OUT

2.4V

OV

+

–

0.660V

I

TH

SHED

V

REF

0.600V

V

CC

V

C

CC

C

V

CC

R2 VARIABLE

SHDN

RST

RUN

SOFT-

START

INTERNAL

SUPPLY

R

1.5µA

C

+

5(V

FB

)

SGND

C

CC

VID

SELECTION

6V

VRM9/VRM10 VID DECODER

SS

OUTEN

C

SS

NO_CPU

1µs

100k

VID5 VID0 VID1 VID2 VID3 VID4

3738 F01

Figure 1

3738f

10

LTC3738

U

(Refer to Functional Diagram)

OPERATIO

Main Control Loop

Low Current Operation

The IC uses a constant frequency, current mode step-

down architecture. During normal operation, each top

MOSFET is turned on each cycle when the oscillator sets

the RS latch, and turned off when the main current

comparator, I₁, resets each RS latch. The peak inductor

current at which I₁resets the RS latch is controlled by the

voltage on the I_THpin, which is the output of the error

amplifierEA. TheEAINpinreceivesaportionofthevoltage

feedback signal via the differential amplifier through the

internalVIDDACandiscomparedtotheinternalreference

voltage.Whentheloadcurrentincreases,itcausesaslight

decrease in the EAIN pin voltage relative to the 0.6V

reference, which in turn causes the I_THvoltage to increase

until each inductor’s average current matches one third of

the new load current (assuming all three current sensing

resistors are equal). In pulse skip mode and Stage Shed-

ding mode, after each top MOSFET has turned off, the

bottom MOSFET is turned on until either the inductor

currentstartstoreverse, asindicatedbycurrentcompara-

tor I₂, or the beginning of the next cycle.

The FCB/SYNC pin is a multifunction pin: 1) a logic input

toselectbetweenthreemodesofoperationand2)external

clock input pin for synchronization.

When the FCB/SYNC pin voltage is below 0.6V, the

controller performs as a continuous, PWM current mode

synchronous switching regulator. The top and bottom

MOSFETs are alternately turned on to maintain the output

voltage independent of direction of inductor current.

When the FCB/SYNC pin is below V_CC– 1.5V, but greater

than 0.6V, the controller performs as a pulse skip mode

switching regulator. Pulse skip mode operation turns off

the synchronous MOSFET(s) when the inductor current

goes negative. Switching cycles will be skipped when the

output load current drops below 3% of the maximum

designed load current in order to maintain the output

voltage. Pulseskipoperationprovideslownoise, constant

frequency operation at light load conditions.

When the FCB/SYNC pin is tied to the V_CCpin, Stage

Shedding mode is enabled. This mode provides constant

frequency, discontinuous current operation over the wid-

est possible output current range. At approximately 10%

of maximum designed load current, the second and third

output stages are shut off and the first controller alone is

active in discontinuous current mode. This “stage shed-

ding”optimizesefficiencybyeliminatingthegatecharging

losses and switching losses of the other two output

stages. Additional cycles will be skipped when the output

load current drops below 1% of maximum designed load

current in order to maintain the output voltage. This

constant frequency operation is more efficient than pulse

skip mode operation at very light load conditions.

The top MOSFET drivers are biased from floating boot-

strap capacitor C_B, which is normally recharged during

each off cycle through an external Schottky diode. When

V_INdecreases to a voltage close to V_OUT, however, the

loop may enter dropout and attempt to turn on the top

MOSFET continuously. The dropout detector counts the

number of oscillator cycles that the bottom MOSFET

remains off and periodically forces a brief on period to

allow C_Bto recharge.

The main control loop is shut down by pulling the OUTEN

pinlow.PullingupOUTENallowsaninternal1.5µAcurrent

sourcetochargesoft-startcapacitorC_SSattheSSpin.The

internal I_THvoltage is clamped to the SS voltage while C_SS

is slowly charged up. This “soft-start” clamping prevents

abrupt current from being drawn from the input power

source. When the OUTEN pin is low, all functions are kept

in a controlled state.

3738f

11

LTC3738

U

(Refer to Functional Diagram)

OPERATIO

Tying the FCB/SYNC pin to ground will force continuous

current operation. This is the least efficient operating

mode, but may be desirable in certain applications. The

output can source or sink current in this mode. When

forcing continuous operation and sinking current, this

current will be forced back into the main power supply,

potentially boosting the input supply to dangerous volt-

age levels.

Power Good

The PGOOD pin is connected to the drain of an internal

MOSFET. The MOSFET is turned on when the output

voltage exceeds the PGOOD ±10% tolerance window. The

PGOOD signal is blanked for approximately 100µs during

VID transitions. If a new VID transition occurs before the

previous blanking time expires, the timer is reset.

Short-Circuit Detection

Feeding a clock signal into the FCB/SYNC pin will syn-

chronize the LTC3738 to the external clock. See Fre-

quency Synchronization or Setup for more information.

The SS capacitor is used initially to limit the inrush current

from the input power source. Once the controllers have

been given time, as determined by the capacitor on the SS

pin, to charge up the output capacitors and provide full

load current, the SS capacitor is then used as a short-

circuit timeout circuit. If the output voltage falls to less

than62.5%ofitsnominaloutputvoltage, theSScapacitor

beginsdischarging,assumingthattheoutputisinasevere

overcurrentand/orshort-circuitcondition.Ifthecondition

lasts for a long enough period, as determined by the size

of the SS capacitor, the controller will be shut down until

the OUTEN pin voltage is recycled. This built-in latchoff

canbeoverriddenbyproviding>5µAatacomplianceof4V

to the SS pin. This current shortens the soft-start period

but prevents net discharge of the SS capacitor during a

severeovercurrentand/orshort-circuitcondition.Foldback

current limiting is activated when the output voltage falls

below 62.5% of its nominal level whether or not the short-

circuit latchoff circuit is enabled. Foldback current limit

can be overridden by clamping the EAIN pin such that the

voltage is held above the (62.5%)(0.6V) or 0.375V level

even when the actual output voltage is low.

Frequency Synchronization or Setup

The phase-locked loop allows the internal oscillator to be

synchronized to an external source using the FCB/SYNC

pin. The output of the phase detector at the PLLFLTR pin

is also the DC frequency control input of the oscillator

which operates over a 210kHz to 530kHz range corre-

spondingtoavoltageinputfrom0Vto2.4V.Whenlocked,

the PLL aligns the turn on of the top MOSFET to the rising

edge of the synchronizing signal and forced continuous

mode is set internally. When no frequency information is

suppliedtotheFCB/SYNCpin,PLLFLTRgoeslow,forcing

the oscillator to minimum frequency. A DC source can be

applied to the PLLFLTR pin to externally set the desired

operating frequency.

Differential Amplifier

This amplifier provides true differential output voltage

sensing. Sensing both V_OUT⁺and V_OUT^–benefits regula-

tion in high current applications and/or applications hav-

ing electrical interconnection losses. This sensing also

isolates the physical power ground from the physical

signal ground preventing the possibility of troublesome

“ground loops” on the PC layout and prevents voltage

errors caused by board-to-board interconnects, particu-

larly helpful in VRM designs.

The SS capacitor will be reset if the input voltage, (V_CC) is

allowed to fall below approximately 4V. The capacitor on

the pin will be discharged until the short-circuit arming

latch is disarmed. The SS capacitor will attempt to cycle

through a normal soft-start ramp up after the V_CCsupply

risesabove4V.Thiscircuitpreventspowersupplylatchoff

in the event of input power switching break-before-make

situations.

3738f

12

LTC3738

U

(Refer to Functional Diagram)

OPERATIO

Start-Up

Thermal Detection

The start-up of the LTC3738 is controlled by the voltage

ramp on the SS pin. The start-up is not completed until the

short-circuit arming latch is enabled. During start-up, the

foldback current limit is temporarily defeated and at the

same time no reverse inductor current is allowed. This is

helpful for situations where output voltage has been “pre-

biased” at some voltage before the controller is enabled.

This will prevent sinking current during start-up which

would otherwise pull current from the pre-biased output.

An accurate comparator and a thermal detector are inte-

grated into the LTC3738 for external or internal thermal

detection. Tying TSNS to V_CCwill enable an internal

thermal detector which generates a thermal event at or

above 120°C with 10°C hysteresis. When the voltage at

TSNS is less than V_CC– 1.6V, the internal thermal detector

is disabled and this pin serves as the input to an accurate

comparator which is referenced to V_CC/3 with a hysteresis

of V_CC/24. A thermal event is generated when the voltage

at TSNS is less than V_CC/3. VR_HOTB, an open-collector

outputpin, willbepulledlowwhenathermaleventoccurs.

VID Table and NO_CPU Detection

The LTC3738 has a VID block which is compatible with

VRM9andVRM10. TyingVID5toV_CCwillselecttheVRM9

table. When the voltage at VID5 is less than V_CC– 1.5V, the

VRM10 table is selected and this pin serves as the VID5 bit

of VRM10. There is a built in –25mV output offset for the

VRM10 VID table and a –12.5mV output offset for the

VRM9 VID table.

Active Voltage Positioning

Load slope is programmable in the LTC3738 through

external resistors. The inductor current information for all

three channels is sensed and combined; the final result is

presented as a voltage drop between AVP and IN⁺. This

voltage drop is scaled through two external resistors

attached to IN⁺and then added to the output voltage as the

compensation for load slope. The final load slope is

defined by the inductor current sense resistors and the

two external resistors mentioned above.

The LTC3738 detects the presence of CPU by monitoring

the VID bits. If a VID0-VID4 all “1” condition is detected,

the controller acknowledges a NO_CPU fault. If this fault

condition persists for more than 1µs, the SS pin is pulled

low and the controller is shut down. The LTC3738 will

attempt a normal start-up when the NO_CPU fault is

removed.

3738f

13

LTC3738

W U U

U

APPLICATIO S I FOR ATIO

The basic application circuit is shown on the first page of

this data sheet. External component selection is driven by

the load requirement, and normally begins with the selec-

tion of an inductance value based upon the desired

operating frequency, inductor current and output voltage

ripple requirements. Once the inductors and operating

frequency have been chosen, the current sensing resis-

tors can be calculated. Next, the power MOSFETs and

Schottky diodes are selected. Finally, C_INand C_OUTare

selected according to the required voltage ripple require-

ments. The circuit shown on the first page of this data

sheet can be configured for operation up to a MOSFET

supply voltage of 28V (limited by the external MOSFETs).

Inductor Value Calculation and Output Ripple Current

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

MOSFET gate charge and transition losses. In addition to

this basic tradeoff, the effect of inductor value on ripple

current and low current operation must also be consid-

ered. The PolyPhase approach reduces both input and

output ripple currents while optimizing individual output

stagestorunatalowerfundamentalfrequency,enhancing

efficiency.

Operating Frequency

Theinductorvaluehasadirecteffectonripplecurrent.The

inductor ripple current ∆I_Lper individual section, N,

decreases with higher inductance or frequency and in-

The IC uses a constant frequency architecture with the

frequency determined by an internal capacitor. This ca-

pacitor is charged by a fixed current plus an additional

current which is proportional to the voltage applied to the

PLLFLTR pin. Refer to the Phase-Locked Loop and Fre-

quency Synchronization and Setup sections for additional

information.

creases with higher V_INor V_OUT

:

V_OUTV_OUT

⎛

⎞

⎟

∆I_L=

1−

⎜

fL ⎝

V ⎠

IN

where f is the individual output stage operating frequency.

A graph for the voltage applied to the PLLFLTR pin versus

frequency is given in Figure 2. As the operating frequency

isincreasedthegatechargelosseswillbehigher,reducing

efficiency (see Efficiency Considerations). The maximum

switching frequency is approximately 530kHz.

InaPolyPhaseconverter,thenetripplecurrentseenbythe

output capacitor is much smaller than the individual

inductor ripple currents due to the ripple cancellation. The

details on how to calculate the net output ripple current

can be found in Application Note 77.

550

450

350

250

150

Figure 3 shows the net ripple current seen by the output

capacitors for the different phase configurations. The

outputripplecurrentisplottedforafixedoutputvoltageas

the duty factor is varied between 10% and 90% on the

x-axis. The output ripple current is normalized against the

inductor ripple current at zero duty factor. The graph can

be used in place of tedious calculations. As shown in

Figure 3, the zero output ripple current is obtained when:

0

0.5

1.0

1.5

2.0

2.5

V_OUT

V

IN

k

N

=

where k = 1, 2,...,N – 1

PLLFLTR PIN VOLTAGE (V)

3738 F02

Figure 2. Operating Frequency vs V_PLLFLTR

3738f

14

LTC3738

W U U

APPLICATIO S I FOR ATIO

U

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1-PHASE

2-PHASE

3-PHASE

4-PHASE

6-PHASE

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can

concentrate on copper loss and preventing saturation.

Ferrite core material saturates “hard,” which means that

inductance collapses abruptly when the peak design

current is exceeded. This results in an abrupt increase in

inductor ripple current and consequent output voltage

ripple. Do not allow the core to saturate!

Power MOSFET and Schottky Diode Selection

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY FACTOR (V /V

)

OUT IN

AtleasttwoexternalpowerMOSFETsmustbeselectedfor

each of the three output sections: One N-channel MOSFET

for the top (main) switch and one or more N-channel

MOSFET(s) for the bottom (synchronous) switch. The

number, type and “on” resistance of all MOSFETs selected

takeintoaccountthevoltagestep-downratioaswellasthe

actualposition(mainorsynchronous)inwhichtheMOSFET

will be used. A much smaller and much lower input

capacitance MOSFET should be used for the top MOSFET

in applications that have an output voltage that is less than

3738 F03

Figure 3. Normalized Peak Output Current

vs Duty Factor [I_RMS= 0.3(I_O(P-P)

]

Sothenumberofphasesusedcanbeselectedtominimize

the output ripple current and therefore the output ripple

voltage at the given input and output voltages. In applica-

tions having a highly varying input voltage, additional

phases will produce the best results.

Accepting larger values of ∆I_Lallows the use of low

inductances but can result in higher output voltage ripple.

A reasonable starting point for setting ripple current is

∆I_L= 0.4(I_OUT)/N, where N is the number of channels and

I_OUTis the total load current. Remember, the maximum

∆I_Loccurs at the maximum input voltage. The individual

inductor ripple currents are constant determined by the

inductor, input and output voltages.

1/3oftheinputvoltage. InapplicationswhereV_IN>>V_OUT

,

the top MOSFETs’ “on” resistance is normally less impor-

tant for overall efficiency than its input capacitance at

operating frequencies above 300kHz. MOSFET manufac-

turers have designed special purpose devices that provide

reasonably low “on” resistance with significantly reduced

inputcapacitanceforthemainswitchapplicationinswitch-

ing regulators.

The peak-to-peak MOSFET gate drive levels are set by the

voltage, V_CC, requiring the use of logic-level threshold

MOSFETs in most applications. Pay close attention to the

BV_DSSspecification for the MOSFETs as well; many of the

logic-level MOSFETs are limited to 30V or less.

Inductor Core Selection

Once the value for the inductors is known, the type of

inductor must be selected. High efficiency converters

generally cannot afford the core loss found in low cost

powdered iron cores, forcing the use of ferrite, molyper-

malloyorKoolMµ^®cores. Actualcorelossisindependent

of core size for a fixed inductor value, but it is very

dependent on inductance selected. As inductance in-

creases, core losses go down. Unfortunately, increased

inductance requires more turns of wire and therefore

copper losses will increase.

Selection criteria for the power MOSFETs include the “on”

resistance R_SD(ON), input capacitance, input voltage and

maximum output current.

MOSFET input capacitance is a combination of several

components but can be taken from the typical “gate

charge” curve included on most data sheets (Figure 4).

Kool Mµ is a registered trademark of Magnetics, Inc.

3738f

15

LTC3738

W U U

U

APPLICATIO S I FOR ATIO

V

IN

The power dissipation for the main and synchronous

MOSFETs at maximum output current are given by:

MILLER EFFECT

V

GS

V

DS

a

b

2

V

GS

V_OUT

V

IN

I

MAX

N

⎛

⎜

⎝

⎞

⎟

⎠

Q

IN

P_MAIN

=

1+ δ R

+

(

)

DS(ON)

C

= (Q – Q )/V

B A DS

3738 F04

MILLER

₂I_MAX

2N

V

R

C

•

(

_DR)(

)

Figure 4. Gate Charge Characteristic

IN

MILLER

The curve is generated by forcing a constant input current

into the gate of a common source, current source loaded

stage and then plotting the gate voltage versus time. The

initialslopeistheeffectofthegate-to-sourceandthegate-

to-drain capacitance. The flat portion of the curve is the

result of the Miller capacitance effect of the drain-to-

source capacitance as the drain drops the voltage across

the current source load. The upper sloping line is due to

the drain-to-gate accumulation capacitance and the gate-

to-source capacitance. The Miller charge (the increase in

coulombsonthehorizontalaxisfromatobwhilethecurve

is flat) is specified for a given V_DSdrain voltage, but can be

adjusted for different V_DSvoltages by multiplying by the

ratio of the application V_DSto the curve specified V_DS

values. A way to estimate the C_MILLERterm is to take the

change in gate charge from points a and b on a manufac-

turers data sheet and divide by the stated V_DSvoltage

specified. C_MILLERis the most important selection criteria

fordeterminingthetransitionlossterminthetopMOSFET

but is not directly specified on MOSFET data sheets. C_RSS

and C_OSare specified sometimes but definitions of these

parameters are not included.

⎡

⎢

⎣

⎤

⎥

⎦

1

+

f

( )

V – V_TH(MIN)V_{TH(MIN) ⎥}

⎢ CC

2

V – V_OUT

I

MAX

⎛

⎜

⎝

⎞

⎟

⎠

IN

P_SYNC

=

1+ δ R

DS(ON)

(

)

V

IN

N

where N is the number of output stages, δ is the tempera-

ture dependency of R_DS(ON), R_DRis the effective top driver

resistance (approximately2ΩatV_GS=V_MILLER), V_INisthe

drain potential and the change in drain potential in the

particular application. V_TH(MIN)is the data sheet specified

typical gate threshold voltage specified in the power

MOSFET data sheet. C_MILLERis the calculated capacitance

using the gate charge curve from the MOSFET data sheet

and the technique described above.

BothMOSFETshaveI²RlosseswhilethetopsideN-channel

equationincludesanadditionaltermfortransitionlosses,

which peak at the highest input voltage. For V_IN< 12V, the

high current efficiency generally improves with larger

MOSFETs, while for V_IN> 12V, the transition losses

rapidly increase to the point that the use of a higher

R_DS(ON)device with lower C_RSSactually provides higher

efficiency. The synchronous MOSFET losses are greatest

athighinputvoltagewhenthetopswitchdutyfactorislow

or during a short circuit when the synchronous switch is

on close to 100% of the period.

When the controller is operating in continuous mode the

duty cycles for the top and bottom MOSFETs are given by:

V_OUT

V

IN

Main SwitchDuty Cycle =

The term (1 + δ ) is generally given for a MOSFET in the

form of a normalized R_DS(ON)vs temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

⎛ V – V_OUT

⎝

⎞

IN

Synchronous SwitchDuty Cycle =

⎜

⎟

V

IN

⎠

3738f

16

LTC3738

W U U

APPLICATIO S I FOR ATIO

U

The Schottky diodes shown in the Typical Application on

the first page of this data sheet conduct during the dead

time between the conduction of the two large power

MOSFETs. This prevents the body diode of the bottom

MOSFET from turning on, storing charge during the dead

time and requiring a reverse recovery period which could

cost as much as several percent in efficiency. A 2A to 8A

Schottky is generally a good compromise for both regions

of operation due to the relatively small average current.

Larger diodes result in additional transition losses due to

their larger junction capacitance.

These worst-case conditions are commonly used for de-

signbecauseevensignificantdeviationsdonotoffermuch

relief. Note that capacitor manufacturer’s ripple current

ratings are often based on only 2000 hours of life. This

makes it advisable to further derate the capacitor or to

choose a capacitor rated at a higher temperature than re-

quired. Several capacitors may also be paralleled to meet

size or height requirements in the design. Always consult

the capacitor manufacturer if there is any question.

The Figure 5 graph shows that the peak RMS input current

is reduced linearly, inversely proportional to the number N

of stages used. It is important to note that the efficiency

loss is proportional to the input RMS current squared and

therefore a 3-stage implementation results in 90% less

power loss when compared to a single phase design. Bat-

tery/input protection fuse resistance (if used), PC board

trace and connector resistance losses are also reduced by

the reduction of the input ripple current in a PolyPhase

system. The required amount of input capacitance is

further reduced by the factor, N, due to the effective in-

crease in the frequency of the current pulses.

C_INand C_OUTSelection

InputcapacitanceESRrequirementsandefficiencylosses

are reduced substantially in a multiphase architecture

because the peak current drawn from the input capacitor

is effectively divided by the number of phases used and

power loss is proportional to the RMS current squared. A

3-stage, single output voltage implementation can reduce

input path power loss by 90%.

In continuous mode, the source current of each top

N-channelMOSFETisasquarewaveofdutycycleV_OUT/V_IN.

A low ESR input capacitor sized for the maximum RMS

current must be used. The details of a close form equation

can be found in Application Note 77. Figure 5 shows the

input capacitor ripple current for different phase configu-

rations with the output voltage fixed and input voltage

varied. The input ripple current is normalized against the

DC output current. The graph can be used in place of

tedious calculations. The minimum input ripple current

can be achieved when the product of phase number and

output voltage, N(V_OUT), is approximately equal to the

input voltage V_INor:

Ceramic capacitors are becoming very popular for small

designs but several cautions should be observed. “X7R”,

“X5R” and “Y5V” are examples of a few of the ceramic

materials used as the dielectric layer, and these different

dielectrics have very different effect on the capacitance

value due to the voltage and temperature conditions

0.6

0.5

1-PHASE

0.4

2-PHASE

3-PHASE

4-PHASE

0.3

6-PHASE

V_OUT

V

IN

k

N

=

where k = 1, 2,...,N – 1

0.2

0.1

So the phase number can be chosen to minimize the input

capacitor size for the given input and output voltages.

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

In the graph of Figure 5, the local maximum input RMS

capacitor currents are reached when:

DUTY FACTOR (V /V

)

OUT IN

3738 F05

Figure 5. Normalized Input RMS Ripple Current

vs Duty Factor for One to Six Output Stages

V_OUT2k – 1

=

where k = 1, 2,...,N

V

IN

N

3738f

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APPLICATIO S I FOR ATIO

applied. Physically, if the capacitance value changes due

to applied voltage change, there is a concommitant piezo

effect which results in radiating sound! A load that draws

varying current at an audible rate may cause an attendant

varying input voltage on a ceramic capacitor, resulting in

an audible signal. A secondary issue relates to the energy

flowing back into a ceramic capacitor whose capacitance

value is being reduced by the increasing charge. The

voltage can increase at a considerably higher rate than the

constant current being supplied because the capacitance

value is decreasing as the voltage is increasing! Ceramic

capacitors,whenproperlyselectedandusedhowever,can

provide the lowest overall loss due to their extremely low

ESR.

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo and the Panasonic SP

surface mount types have a good (ESR)(size) product.

Once the ESR requirement for C_OUThas been met, the

RMS current rating generally far exceeds the I_RIPPLE(P-P)

requirement. Ceramic capacitors from AVX, Taiyo Yuden,

Murata and Tokin offer high capacitance value and very

low ESR, especially applicable for low output voltage

applications.

In surface mount applications, multiple capacitors may

have to be paralleled to meet the ESR or RMS current

handlingrequirementsoftheapplication.Aluminumelec-

trolytic and dry tantalum capacitors are both available in

surface mount configurations. New special polymer sur-

face mount capacitors offer very low ESR also but have

muchlowercapacitivedensityperunitvolume.Inthecase

oftantalum,itiscriticalthatthecapacitorsaresurgetested

for use in switching power supplies. Several excellent

choices are the AVX TPS, AVX TPSV, the KEMET T510

series of surface-mount tantalums or the Panasonic SP

series of surface mount special polymer capacitors avail-

able in case heights ranging from 2mm to 4mm. Other

capacitor types include Sanyo POS-CAP, Sanyo OS-CON,

Nichicon PL series and Sprague 595D series. Consult the

manufacturer for other specific recommendations.

The selection of C_OUTis driven by the required effective

series resistance (ESR). Typically once the ESR require-

ment is satisfied the capacitance is adequate for filtering.

The steady-state output ripple (∆V_OUT) is determined by:

⎛

1

⎞

∆V_OUT≈ ∆I_RIPPLEESR +

⎜

⎟

⎝

8NfC_OUT

⎠

where f = operating frequency of each stage, N is the

number of output stages, C_OUT= output capacitance and

∆I_L= ripple current in each inductor. The output ripple is

highest at maximum input voltage since ∆I_Lincreases

withinputvoltage.Theoutputripplewillbelessthan50mV

at max V_INwith ∆I_L= 0.4I_OUT(MAX)assuming:

R_SENSESelection for Output Current

Once the frequency and inductor have been chosen,

R_SENSE1,R_SENSE2,R_SENSE3are determined based on the

required peak inductor current. The current comparator

has a maximum threshold of 75mV/R_SENSEand an input

common mode range of SGND to (1.1) • V_CC. The current

comparator threshold sets the peak inductor current,

yielding a maximum average output current I_MAXequal to

the peak value less half the peak-to-peak ripple current,

∆I_L.

C_OUTrequired ESR < N • R_SENSE

and

C_OUT> 1/(8Nf)(R_SENSE

)

The emergence of very low ESR capacitors in small,

surfacemountpackagesmakesverysmallphysicalimple-

mentations possible. The ability to externally compensate

the switching regulator loop using the I_THpin allows a

much wider selection of output capacitor types. The

impedance characteristics of each capacitor type is sig-

nificantly different than an ideal capacitor and therefore

requires accurate modeling or bench evaluation during

design.

Allowing a margin for variations in the IC and external

component values yields:

50mV

I_MAX

R_SENSE= N

Manufacturers such as Nichicon, United Chemicon and

Sanyoshouldbeconsideredforhighperformancethrough-

The IC works well with values of R_SENSEfrom 0.001Ω to

0.02Ω.

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U

V_CCDecoupling

common, tightly coupled pair of PC traces. The differen-

tial amplifier rejects common mode signals capacitively

orinductivelyradiatedintothefeedbackPCtracesaswell

as ground loop disturbances. The differential amplifier

output signal is divided down through the VID DAC and

is compared with the internal, precision 0.6V voltage

reference by the error amplifier.

TheV_CCpinsuppliespowernotonlytotheinternalcircuits

of the controller but also to the top and bottom gate

drivers and therefore must be bypassed very carefully to

ground with a ceramic capacitor, type X7R or X5R (de-

pending upon the operating temperature environment) of

at least 1µF immediately next to the IC and preferably an

additional 10µF placed very close to the IC due to the

extremely high instantaneous currents involved. The total

capacitance, taking into account the voltage coefficient of

ceramic capacitors, should be 100 times as large as the

total combined gate charge capacitance of ALL of the

MOSFETs being driven. Good bypassing close to the IC is

necessary to supply the high transient currents required

by the MOSFET gate drivers while keeping the 5V supply

quiet enough so as not to disturb the very small-signal

high bandwidth of the current comparators.

The amplifier has a 0 to V_CCcommon mode input range

and an output swing range of 0 to V_CC– 1.2V. The output

uses an NPN emitter follower with 160kΩ feedback

resistance.

Output Voltage

Selection of the VRM9 or VRM10 VID table is through the

VID5pin.TyingVID5toV_CCwillselecttheVRM9 VIDtable.

If the VRM9 VID table is selected (Table 1), output voltage

in 25mV increments is produced from 1.1V to 1.85V.

There is a built-in –12.5mV DC offset for the output

voltage.

Topside MOSFET Driver Supply (C_B, D_B)

Externalbootstrapcapacitors,C_B,connectedtotheBOOST

pins, supply the gate drive voltages for the topside

MOSFETs. Capacitor C_Bin the Functional Diagram is

charged though diode D_Bfrom V_CCwhen the SW pin is

low. When one of the topside MOSFETs turns on, the

driver places the C_Bvoltage across the gate-source of the

desiredMOSFET.ThisenhancestheMOSFETandturnson

the topside switch. The switch node voltage, SW, rises to

V_INand the BOOST pin follows. With the topside MOSFET

IftheVRM10VIDtableisselected(Table2),outputvoltage

in 12.5mV increments is produced from 0.8375V to 1.6V.

There is a built-in –25mV DC offset for output voltage.

Active Voltage Position Control

TheLTC3738sensesinductorcurrentinformationthrough

monitoring voltage drops on the sense resistor R_SENSEof

all three channels. The voltage drops are added together

and applied as V_PRE-AVPbetween the AVP and IN⁺pins,

which are connected through resistor R_PRE-AVP. Then

V_PRE-AVPis scaled through R_AVPand added to output

voltage as the compensation for the load voltage drop. In

summary, the load slope is:

on, the boost voltage is above the input supply (V_BOOST

=

V_CC+ V_IN). The value of the boost capacitor C_Bneeds to be

30 to 100 times that of the total input capacitance of the

topsideMOSFET(s).ThereversebreakdownofD_Bmustbe

greater than V_IN(MAX).

Differential Amplifier

⎛

R_AVP

R_PRE−AVP

⎞

R

SENSE

•

V/A

⎜

⎟

⎝

⎠

The IC has a true remote voltage sense capability. The

sensing connections should be returned from the load,

back to the differential amplifier’s inputs through a

The recommended value for R_AVPis 90Ω to 100Ω.

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Thermal Control

Table 1. VRM9 VID Table

PROCESSOR PINS (0 = L0W, 1 = HIGH)

V

CC(CORE)

When external thermal detection is enabled, the TSNS pin

serves as the input to an accurate comparator which is

referenced to V_CC/3 and has a hysteresis of V_CC/24.

VR_HOTB is pulled low when the voltage at TSNS is less

than V_CC/3. In this case, the input of TSNS is an analog

signal. If necessary, lowpass filter the signal before feed-

ing it into the pin to avoid a false thermal trip.

VID4

1

0

VID3

1

0

1

0

VID2

1

0

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

(V )

DC

Output Off

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

WhenVR_HOTBisreported,theoperationofLTC3738will

not be affected, although there is another thermal sensor

inside the IC for self protection. When the temperature of

the IC is around 140°C, the LTC3738 will shut down and

not start-up again until this overtemperature situation has

beenremoved. Thisselfshutdownfeatureisnottestedbut

is guaranteed by design.

ON/OFF Control

The OUTEN pin provides simple ON/OFF control for the

LTC3738. Driving the OUTEN pin above 0.8V permits the

controller to start operating. Pulling OUTEN below 0.4V

puts the LTC3738 into low current shutdown (I_Q≈ 50µA).

Soft-Start Function

The SS pin provides two functions: 1) soft-start and 2) a

defeatable short-circuit latch off timer. Soft-start reduces

the input power sources’ surge currents by gradually

increasingthecontroller’scurrentlimit(proportionaltoan

internal buffered and clamped V_ITH). The latchoff timer

prevents very short, extreme load transients from tripping

the overcurrent latch. A small pull-up current (>5µA)

supplied to the SS pin will prevent the overcurrent latch

from operating. The following explanation describes how

this function operates.

An internal 1.5µA current source charges up the C_SS

capacitor. As the voltage on SS increases from 0V to 2.4V,

3738f

20

LTC3738

Table 2. VRM10 VID Table

PROCESSOR PINS (0 = LOW, 1 = HIGH)

V

PROCESSOR PINS (0 = LOW, 1 = HIGH)

V

OUT

(V)

VID4

0

1

VID3

1

0

1

VID2

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VID4

1

0

VID3

1

0

1

VID2

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

Off*

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

Off*

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

*Output disabled—same as deasserting the Output Enable input

the internal current limit is increased from 0V/R_SENSEto

75mV/R_SENSE. The output current limit ramps up slowly,

taking 1.6s/µF to reach full current. The output current

thus ramps up slowly, eliminating the starting surge

current required from the input power supply.

The SS pin has an internal 6V zener clamp (see the

Functional Diagram).

Fault Conditions: Overcurrent Latchoff

The SS pin also provides the ability to latch off the

controllerswhenanovercurrentconditionisdetected.The

SS capacitor is used initially to limit the inrush current of

2.4V – 0V

t_IRAMP

=

C_SS= 1.6s/µF C

SS

(

)

1.5µA

all three output stages. After the controllers have been

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The value of the soft-start capacitor C_SSmay need to be

scaled with output current, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

given adequate time to charge up the output capacitor and

provide full load current, the SS capacitor is used for a

short-circuit timer. If the output voltage falls to less than

62.5% of its nominal value, the SS capacitor begins

discharging on the assumption that the output is in an

overcurrent condition. If the condition lasts for a long

enough period, as determined by the size of the SS

capacitor, the controller will be shut down until the RUN

pin voltage is recycled. If the overload occurs during start-

up, the time can be approximated by:

C

_SS> (C_OUT)(V_OUT) (10^–4) (R_SENSE

)

The minimum recommended soft-start capacitor of

C_SS= 0.1µF will be sufficient for most applications.

Current Foldback

In certain applications, it may be desirable to defeat the

internal current foldback function. A negative impedance

is experienced when powering a switching regulator.

That is, the input current is higher at a lower V_INand

decreases as V_INis increased. Current foldback is de-

signed to accommodate a normal, resistive load having

increasing current draw with increasing voltage. The EAIN

pin should be artificially held 62.5% above its nominal

operating level of 0.6V, or 0.375V in order to prevent the

IC from “folding back” the peak current level. A suggested

circuit is shown in Figure 7.

t

_LO1>> (C_SS• 0.6V)/(1.5µA) = 4 • 10⁵(C_SS)

If the overload occurs after start-up, the voltage on the SS

capacitor will continue charging and will provide addi-

tional time before latching off:

t

_LO2>> (C_SS• 3V)/(1.5µA) = 2 • 10⁶(C_SS)

This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor to the SS pin from V_CCas

shown in Figure 6. When V_CCis 5V, a 200k resistance will

prevent the discharge of the SS capacitor during an

overcurrent condition but also shortens the soft-start

period, so a larger SS capacitor value will be required.

The emitter of Q1 will hold up the EAIN pin to a voltage in

the absence of V_OUTthat will prevent the internal sensing

circuitry from reducing the peak output current. Remov-

ing the function in this manner eliminates the external

MOSFET’s protective feature under short-circuit condi-

tions. This technique will also prevent the short-circuit

latchoff function from turning off the part during a short-

circuit event and the output current will only be limited to

Why should you defeat overcurrent latchoff? During the

prototypingstageofadesign,theremaybeaproblemwith

noise pick-up or poor layout causing the protection circuit

to latch off the controller. Defeating this feature allows

troubleshooting of the circuit and PC layout. The internal

foldback current limiting still remains active, thereby

protecting the power supply system from failure. A deci-

sion can be made after the design is complete whether to

rely solely on foldback current limiting or to enable the

latchoff feature by removing the pull-up resistor.

N • 75mV/R_SENSE

.

V

CC

LTC3738

V

SS PIN

Q1

CC

R

SS

EAIN

CALCULATE FOR

0.375V TO 0.55V

3738 F07

C

SS

3738 F06

Figure 7. Foldback Current Elimination

Figure 6. Defeating Overcurrent Latchoff

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Undervoltage Reset

U

R

LP

10k

PHASE

DETECTOR/

OSCILLATOR

2.4V

In the event that the input power source to the IC (V_CC)

drops below 4V, the SS capacitor will be discharged to

ground and the controller will be shut down. When V_CC

rises above 4V, the SS capacitor will be allowed to re-

chargeandinitiateanothersoft-startturn-onattempt.This

may be useful in applications that switch between two

supplies that are not diode connected, but note that this

cannot make up for the resultant interruption of the

regulated output.

C

LP

EXTERNAL

OSC

PLLFLTR

OSC

FCB/SYNC

DIGITAL

PHASE/

FREQUENCY

DETECTOR

3738 F08

Phase-Locked Loop and Frequency Synchronization

Figure 8. Phase-Locked Loop Block Diagram

The IC has a phase-locked loop comprised of an internal

voltage controlled oscillator and phase detector. This

allows the top MOSFET of output stage 1’s turn-on to be

locked to the rising edge of an external source. The

frequency range of the voltage controlled oscillator is

±50% around the center frequency f_O. A voltage applied to

the PLLFLTR pin of 1.2V corresponds to a frequency of

approximately 350kHz. The nominal operating frequency

range of the IC is 210kHz to 530kHz.

stable operating point, the phase comparator output is

open and the filter capacitor C_LPholds the voltage. The IC

FCB/SYNC pin must be driven from a low impedance

source such as a logic gate located close to the pin. When

usingmultipleICsforaphase-lockedsystem,thePLLFLTR

pin of the master oscillator should be biased at a voltage

that will guarantee the slave oscillator(s) ability to lock

onto the master’s frequency. A voltage of 1.7V or below

applied to the master oscillator’s PLLFLTR pin is recom-

mended in order to meet this requirement. The resultant

operating frequency will be approximately 500kHz for

1.7V.

The phase detector used is an edge sensitive digital type

that provides zero degrees phase shift between the

external and internal oscillators. This type of phase

detector will not lock the internal oscillator to harmonics

of the input frequency. The PLL hold-in range, ∆f_H, is

equal to the capture range, ∆f_C:

The loop filter components (C_LP, R_LP) smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components C_LPand R_LPdetermine how fast the loop

acquires lock. Typically R_LP=10k and C_LPranges from

0.01µF to 0.1µF.

∆f_H= ∆f_C= ±0.5 f_O

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter components on the PLLFLTR pin. A simplified block

diagram is shown in Figure 8.

Minimum On-Time Considerations

If the external frequency (f_PLLIN) is greater than the oscil-

lator frequency, f_OSC, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency

is less than f_OSC, current is sunk continuously, pulling

down the PLLFLTR pin. If the external and internal fre-

quencies are the same, but exhibit a phase difference, the

currentsourcesturnonforanamountoftimecorrespond-

ing to the phase difference. Thus, the voltage on the

PLLFLTR pin is adjusted until the phase and frequency of

the external and internal oscillators are identical. At this

Minimum on-time, t_ON(MIN), is the smallest time duration

that the IC is capable of turning on the top MOSFET. It is

determined by internal timing delays and the gate charge

of the top MOSFET. Low duty cycle applications may

approach this minimum on-time limit and care should be

taken to ensure that:

V_OUT

t_{ON MIN}

<

(

)

V f

_IN( )

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Ifthedutycyclefallsbelowwhatcanbeaccommodatedby

the minimum on-time, the IC will begin to skip every other

cycle, resulting in half-frequency operation. The output

voltage will continue to be regulated, but the ripple current

and ripple voltage will increase.

time, V_OUTcan be monitored for excessive overshoot or

ringing, which would indicate a stability problem. The

availability of the I_THpin not only allows optimization of

control loop behavior, but also provides a DC coupled

and AC filtered closed-loop response test point. The DC

step, risetimeandsettlingatthistestpointtrulyreflects

the closed-loop response. Assuming a predominantly

second order system, phase margin and/or damping

factor can be estimated using the percentage of overshoot

seen at this pin. The bandwidth can also be estimated by

examining the rise time at the pin. The I_THexternal com-

ponents shown in the Figure 1 circuit will provide an

adequate starting point for most applications.

The minimum on-time for the IC is generally about 120ns.

However, as the peak sense voltage decreases the mini-

mum on-time gradually increases. This is of particular

concern in forced continuous applications with low ripple

current at light loads. If the duty cycle drops below the

minimum on-time limit in this situation, a significant

amount of cycle skipping can occur with correspondingly

larger current and voltage ripple.

The I_THseries R_C-C_Cfilter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.2 to 5 times their suggested values) to maximize

transient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be decided

upon because the various types and values determine the

loop feedback factor gain and phase. An output current

pulse of 20% to 80% of full load current having a rise time

of<2µswillproduceoutputvoltageandI_THpinwaveforms

that will give a sense of the overall loop stability without

breakingthefeedbackloop. Theinitialoutputvoltagestep,

resulting from the step change in output current, may not

bewithinthebandwidthofthefeedbackloop,sothissignal

cannot be used to determine phase margin. This is why it

is better to look at the I_THpin signal which is in the

feedback loop and is the filtered and compensated control

loop response. The gain of the loop will be increased by

increasing R_Cand the bandwidth of the loop will be

increased by decreasing C_C. If R_Cis increased by the same

factor that C_Cis decreased, the zero frequency will be kept

the same, thereby keeping the phase the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loop system and will demonstrate the actual over-

all supply performance.

If an application can operate close to the minimum on-

timelimit, aninductormustbechosenthatislowenough

in value to provide sufficient ripple amplitude to meet the

minimum on-time requirement. As a general rule, keep

the inductor ripple current equal to or greater than 30%

of I_OUT(MAX)at V_IN(MAX)

.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

Checking Transient Response

The regulator loop response can be checked by looking at

the load transient response. Switching regulators take

several cycles to respond to a step in DC (resistive) load

current. When a load step occurs, V_OUTshifts by an

amount equal to ∆I_LOAD• ESR, where ESR is the effective

series resistance of C_OUT. ∆I_LOADalso begins to charge or

discharge C_OUT, generating the feedback error signal that

forces the regulator to adapt to the current change and

return V_OUTto its steady-state value. During this recovery

A second, more severe transient is caused by switching in

loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C_OUT, causing a rapid drop in V_OUT. No regulator can

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U

Next verify the minimum on-time is not violated. The

minimum on-time occurs at maximum V_CC:

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistanceislowanditisdrivenquickly. IfC_LOADisgreater

than2%ofC_OUT, theswitchrisetimeshouldbecontrolled

so that the load rise time is limited to approximately

1000 •R_SENSE• C_LOAD. Thusa 250µF capacitor and a2mΩ

R_SENSEresistor would require a 500µs rise time, limiting

the charging current to about 1A.

V_OUT

_IN(MAX)( )

1.3V

20V 400kHz

t_{ON MIN}

=

= 162ns

(

)

V

f

(

)

The output voltage will be set by the VID code according

to Table 1.

The power dissipation on the topside MOSFET can be

estimated.UsingaSiliconixSi7390DPforexample,R_DS(ON)

= 13.5mΩ, C_MILLER= 2.1nC/15V = 140pF. At maximum

input voltage with T(estimated) = 50°C:

Design Example (Using Three Phases)

As a design example, assume V_IN= 12V(nominal), V_IN=

20V(max), V_OUT= 1.3V, I_MAX= 45A, f = 400kHz and the

AVP slope is 1mV/A. The inductance value is chosen first

based upon a 30% ripple current assumption. The highest

value of ripple current in each output stage occurs at the

maximum input voltage.

1.3V

20V

2

P_MAIN

≈

15 1+ 0.005 50°C − 25°C

( )

(

)(

)

]

[

⎛

⎞

45A

2 3

( )( )

2

0.0135Ω + 20

2Ω 140pF

)( )

( )

(

⎜

⎟

⎝

⎠

V_OUT

⎛

V_OUT

V

IN

⎞

L =

1−

1

⎛

⎜

⎝

⎞

⎠

⎜

⎟

+

400kHz = 0.51W

f ∆I ⎝

( )

⎠

(

)

⎟

5V – 1.8V 1.8V

1.3V

20V

⎛

⎜

⎝

⎞

⎟

⎠

=

1−

using a Siliconix Si7356DP as bottom side MOSFET.

400kHz 30% 15A

(

)( )(

)

The worst-case power dissipation by the synchronous

MOSFET under normal operating conditions at elevated

ambient temperature and estimated 50°C junction tem-

perature rise is:

≥ 0.68µH

Using L = 0.6µH, a commonly available value results in

34% ripple current. The worst-case output ripple for the

three stages operating in parallel will be less than 11% of

the peak output current.

20V − 1.3V

2

P_SYNC

=

15A 1.25 0.004Ω = 1.05W

) ( )(

(

)

20V

R_SENSE1,R_SENSE2and R_SENSE3can be calculated by using

aconservativemaximumsensecurrentthresholdof65mV

and taking into account half of the ripple current:

Ashortcircuittogroundwillresultinafoldedbackcurrent

of:

⎛

⎞

150ns 20V

25mV

1

(

)

I_SC

≈

+

= 7.5A

65mV

⎜

⎟

2 + 3 mΩ 2

0.6µH

(

)

⎝

⎠

R_SENSE

=

= 0.0037Ω

34%

2

⎛

⎝

⎞

⎟

⎠

15A 1+

⎜

with a typical value of R_DS(ON)and d = (0.005/°C)(50°C) =

0.25.TheresultingpowerdissipatedinthebottomMOSFET

is:

Use a commonly available 0.003Ω sense resistor.

P_SYNC= (7.5A)²(1.25)(0.004Ω) ≈ 0.28W

Take R_AVPas recommended value 100Ω, the R_PREAVPis:

which is less than one third of the normal, full load

conditions. Incidentally, since the load no longer dissi-

pates any power, total system power is decreased by over

90%. Therefore, the system actually cools significantly

100Ω

1mV/A

R_PREAVP= 0.003Ω

= 300Ω

during a shorted condition!

3738f

25

LTC3738

W U U

U

APPLICATIO S I FOR ATIO

PC Board Layout Checklist

6) The filter capacitors between the I_THand SGND pins

should be as close as possible to the pins of the IC.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

IC.Theseitemsarealsoillustratedgraphicallyinthelayout

diagram of Figure 9. Check the following in the PC layout:

Figure 9 illustrates all branch currents in a three-phase

switching regulator. It becomes very clear after studying

the current waveforms why it is critical to keep the high

switchingcurrentpathstoasmallphysicalsize. Highelec-

tricandmagneticfieldswillradiatefromthese“loops”just

as radio stations transmit signals. The output capacitor

ground should return to the negative terminal of the input

capacitor and not share a common ground path with any

switchedcurrentpaths.Thelefthalfofthecircuitgivesrise

to the “noise” generated by a switching regulator. The

ground terminations of the synchronous MOSFETs and

Schottkydiodesshouldreturntothebottomplate(s)ofthe

inputcapacitor(s)withashortisolatedPCtracesincevery

highswitchedcurrentsarepresent.Aseparateisolatedpath

fromthebottomplate(s)oftheinputandoutputcapacitor(s)

should be used to tie in the IC power ground pin (PGND).

This technique keeps inherent signals generated by high

current pulses taking alternate current paths that have

finite impedances during the total period of the switching

regulator.ExternalOPTI-LOOPcompensationallowsover-

compensation for PC layouts which are not optimized but

this is not the recommended design procedure.

1)Arethesignalandpowergroundpathsisolated?Keepthe

SGND at one end of a printed circuit path thus preventing

MOSFETcurrentsfromtravelingundertheIC.TheICsignal

ground pin should be used to hook up all control circuitry

on one side of the IC, routing the copper through SGND,

undertheICcoveringthe“shadow”ofthepackage,connect-

ingtothePGNDpinandthencontinuingontothe(–)plates

of C_INand C_OUT. The V_CCdecoupling capacitor should be

placed immediately adjacent to the IC between the V_CCpin

and PGND. A 1µF ceramic capacitor of the X7R or X5R type

is small enough to fit very close to the IC to minimize the ill

effectsofthelargecurrentpulsesdrawntodrivethebottom

MOSFETs. An additional 5µF to 10uF of ceramic, tantalum

or other very low ESR capacitance is recommended in or-

der to keep the internal IC supply quiet. The power ground

returns to the sources of the bottom N-channel MOSFETs,

anodes of the Schottky diodes and (–) plates of C_IN, which

should have as short lead lengths as possible.

2) Does the IC IN⁺pin connect to the (+) plates of C_OUT

?

A 30pF to 300pF feedforward capacitor between the

DIFFOUT and EAIN pins should be placed as close as

possible to the IC.

Simplified Visual Explanation of How a 3-Phase

Controller Reduces Both Input and Output RMS

Ripple Current

3) Are the SENSE^–and SENSE⁺printed circuit traces for

each channel routed together with minimum PC trace

spacing?ThefiltercapacitorsbetweenSENSE⁺andSENSE^–

for each channel should be as close as possible to the pins

of the IC. Connect the SENSE^–and SENSE⁺pins to the

pads of the sense resistor as illustrated in Figure 10.

Theeffectofmultiphasepowersupplydesignsignificantly

reduces the amount of ripple current in both the input and

output capacitors. The RMS input ripple current is divided

by, and the effective ripple frequency is multiplied up by

the number of phases used (assuming that the input

voltage is greater than the number of phases used times

the output voltage). The output ripple amplitude is also

reduced by,andtheeffectiveripplefrequency isincreased

by the number of phases used. Figure 11 graphically

illustrates the principle.

4) Do the (+) plates of C_INconnect to the drains of the

topside MOSFETs as closely as possible? This capacitor

provides the pulsed current to the MOSFETs.

5) Keep the switching nodes, SWITCH, BOOST and TG

away from sensitive small-signal nodes. Ideally the

SWITCH, BOOST and TG printed circuit traces should be

routedawayandseparatedfromtheICandthe“quiet”side

of the IC.

Theworst-caseinputRMSripplecurrentforasinglestage

design peaks at twice the value of the output voltage. The

worst-case input RMS ripple current for a two stage

design results in peaks at 1/4 and 3/4 of the input voltage,

3738f

26

LTC3738

W U U

APPLICATIO S I FOR ATIO

U

L1

SW1

R

SENSE1

D1

L2

V

OUT

IN

SW2

R

SENSE2

R

IN

+

R

L

D2

C

OUT

C

IN

BOLD LINES INDICATE HIGH,

SWITCHING CURRENT LINES.

KEEP LINES TO A MININMUM

LENGTH

L3

SW3

R

SENSE3

D3

3738 F09

Figure 9. Branch Current Waveforms

INDUCTOR

LTC3738

SENSE

+

SENSE

1000pF

RESISTOR

–

SENSE

3738 F10

OUTPUT CAPACITOR

Figure 10. Kelvin Sensing R_SENSE

3738f

27

LTC3738

W U U

U

APPLICATIO S I FOR ATIO

SINGLE PHASE

subtract current from the (V_CC– V_OUT)/L charging current

resultingfromthestagewhichhasitstopMOSFETon. The

output ripple current for a 3-phase design is:

SW V

I

CIN

V_OUT

f L

( )( )

I_P-P

=

1– 3DC V > 3V_OUT

IN

(

)

I

COUT

The ripple frequency is also increased by three, further

reducingtherequiredoutputcapacitancewhenV_CC<3V_OUT

as illustrated in Figure 3.

TRIPLE PHASE

SW1 V

SW2 V

SW3 V

Efficiency Calculation

To estimate efficiency, the DC loss terms include the input

and output capacitor ESR, each MOSFET R_DS(ON), induc-

tor resistance R_L, the sense resistance R_SENSEand the

forward drop of the Schottky rectifier at the operating

output current and temperature. Typical values for the

design example given previously in this data sheet are:

I

L1

I

L2

I

L3

I

CIN

I

Main MOSFET R_DS(ON)= 13.5mΩ (18mΩ at 90°C)

COUT

3738 F11

Sync MOSFET R_DS(ON)= 4mΩ (5.3mΩ at 90°C)

C_INESR= 20mΩ

C_OUTESR= 3mΩ

R_L= 2mΩ

R_SENSE= 3mΩ

V_SCHOTTKY= 0.8V at 15A (0.7V at 90°C)

V_OUT= 1.3V

V_IN= 12V

I_MAX= 45A

δ = 0.5%°C

Figure 11. Single and Polyphase Current Waveforms

and the worst-case input RMS ripple current for a three

stage design results in peaks at 1/6, 1/2, and 5/6 of the

input voltage. The peaks, however, are at ever decreasing

levels with the addition of more phases. A higher effective

duty factor results because the duty factors “add” as long

as the currents in each stage are balanced. Refer to AN19

for a detailed description of how to calculate RMS current

for the single stage switching regulator.

Figure 5 illustrates the RMS input current drawn from the

input capacitance versus the duty cycle as determined by

the ration of input and output voltage. The peak input RMS

current level of the single phase system is reduced by 2/3

in a 3-phase solution due to the current splitting between

the three stages.

N = 3

f = 400kHz

The main MOSFET is on for the duty factor V_OUT/V_INand

the synchronous MOSFET is on for the rest of the period

or simply (1 – V_OUT/V_IN). Assuming the ripple current is

small, the AC loss in the inductor can be made small if a

good quality inductor is chosen. The average current,

_OUTis used to simplify the calaculations. The equation

below is not exact but should provide a good technique

for the comparison of selected components and give a

The output ripple current is reduced significantly when

compared to the single phase solution using the same

inductance value because the V_OUT/L discharge currents

term from the stages that has their bottom MOSFETs on

I

3738f

28

LTC3738

W U U

APPLICATIO S I FOR ATIO

U

This totals 0.14W at V_IN= 8V, 0.315W at V_IN= 12V and

0.875W at V_IN= 20V.

result that is within 10% to 20% of the final application.

The temperature of the MOSFET’s die temperature may

require interative calculations if one is not familiar typical

performance. A maximum operating junction tempera-

ture of 90° to 100°C for the MOSFETs is recommended

for high reliability applications.

Total of all three synchronous MOSFET’s AC loss:

V

IN

V_DSSPEC

IN

(3)Q_G

(f) = (3)(16nC)

(400kHz)

V_DSSPEC

Common output path DC loss:

This totals 0.085W at V_IN= 8V, 0.128W at V_IN= 12V and

0.213W at V_IN= 20V. The bottom MOSFET does not

experience the Miller capacitance dissipation issue that

the main switch does because the bottom switch turns on

when its drain is close to ground.

2

I

⎛

⎝

⎞

⎟

⎠

MAX

N

P_COMPATH≈ N

R +R

+ C_OUTESRLoss

(

)

⎜

L

SENSE

This totals 3.375W + C_OUTESRloss.

The Schottky rectifier loss assuming 50ns nonoverlap

time:

Total of all three main MOSFET’s DC loss:

2

⎛ V_OUT⎞ I

2 • 3(0.7V)(15A)(50ns)(400kHz)

This totals 1.26W.

⎛

⎜

⎝

⎞

⎟

⎠

MAX

N

P_MAIN= N

1+ δ R_DS(ON)+ C_INESRLoss

(

)

⎜

⎟

⎝ V

⎠

IN

This totals 1.3W + C_INESRloss.

The total output power is (1.3V)(45A) = 58.5W and the

total input power is approximately 67W so the % loss of

each component is as follows:

Total of all three synchronous MOSFET’s DC loss:

2

Main switch AC loss (V_IN= 12V) 0.315W 0.47%

⎛

V_OUT⎞ I

⎛

MAX

⎞

⎟

⎠

P_SYNC= N 1–

1+ δ R

DS(ON)

(

)

⎜

⎟

⎜

⎝

V

IN

⎠

N

Main switch DC loss

1.3W

0.128W 0.2%

3.2W 4.8%

3.375W 5.05%

1.9%

Synchronous switch AC loss

Synchronous switch DC loss

Power path loss

This totals 3.2W.

Total of all three main MOSFET’s AC loss:

45A

(2)(3)

P

_MAIN≈ 3(V )²

(2Ω)(140pF)

IN

The numbers above represent the values at V_IN= 12V.

1

⎛

⎜

⎝

⎞

⎟

⎠

+

(400kHz) = 6.3W

5V – 1.8V 1.8V

3738f

29

LTC3738

U

TYPICAL APPLICATIO

65A Power Supply for VRM10

V

CC

5V

47k

PGOOD

VID0 IN

VID1 IN VID5 IN

1Ω

VID2 IN

V

ON/0FF

CC

100pF

0.1µF

51k

V

OUTEN VID2 VID1 VID0 VID5 PGOOD BOOST1

IN

V

OUT

FCB/SYNC

TG1

M1

M2

L1

L2

0.002Ω

10k

PLLFLTR

SW1

+

10µF

6.3V

×3

V

CC

R

–

AVP

C

D1

IN

BOOST2

TG2

OUT

100Ω

+

0.1µF

S1

S2

–

+

S1

IN

AVP

SW2

30pF

IN

R

220Ω

V

IN

7V TO 21V

PREAVP

10Ω ×6

EAIN

V

M3

M4

CC

+

0.002Ω

10µF

35V

×5

LTC3738

(EXPOSED PAD IS SGND)

IN

68µF

+

S1

SENSE1

BG1

PGND

BG2

1µF

10µF

1000pF

25V

–

+

–

S1

S2

D2

SENSE1

+

S2

SENSE2

–

+

–

S2

S3

SENSE2

BG3

–

SENSE3

SW3

V

IN

+

M5

M6

L3

SENSE3

TG3

0.002Ω

3738 TA02

SS

I

TSNS VR_HOTB VID3 VID4 BOOST3

0.1µF

TH

D3

0.1µF

100pF

200Ω

V

VID4 IN

+

–

CC

S3

VID3 IN

2.2k

V

CC

V

CC

2200pF

V

: 7V TO 21V

OUT

SWITCHING FREQUENCY: 300kHz

C

: SANYO OS-CON 25SP68M

L1 TO L3: 0.6µH PULSE PG0006.601 OR TOKO FDA1055 0.56µH

M1, M3, M5: Si7390DP ×1 OR HAT2168H ×1

M2, M4, M6: Si7356DP ×2 OR HAT2165H ×2

IN

: 0.8V TO 1.55V, 65A

: 330µF/2.5V ×10 SANYO POSCAP 2R5TPE330M9

OUT

D1 TO D3: MBRS340T3

Block Diagram—6-Phase LTC3731/LTC3738 Supply

3-PHASE LTC3731

CLKOUT

V

OUT

CLK

60°

V

IN

VRM9/VRM10

90A TO 120A

FCB/SYNC

3-PHASE LTC3738

3738 TA03

3738f

30

LTC3738

U

PACKAGE DESCRIPTIO

UHF Package

38-Lead Plastic QFN (7mm × 5mm)

(Reference LTC DWG # 05-08-1701)

0.70 ± 0.05

5.50 ± 0.05

(2 SIDES)

4.10 ± 0.05

(2 SIDES)

3.20 ± 0.05

(2 SIDES)

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC

5.20 ± 0.05 (2 SIDES)

6.10 ± 0.05 (2 SIDES)

7.50 ± 0.05 (2 SIDES)

RECOMMENDED SOLDER PAD LAYOUT

3.15 ± 0.10

(2 SIDES)

0.75 ± 0.05

5.00 ± 0.10

(2 SIDES)

0.435 0.18

0.18

37 38

0.00 – 0.05

PIN 1

TOP MARK

(SEE NOTE 6)

1

2

0.23

5.15 ± 0.10

(2 SIDES)

7.00 ± 0.10

(2 SIDES)

0.40 ± 0.10

0.200 REF 0.25 ± 0.05

0.50 BSC

R = 0.115

TYP

(UH) QFN 0303

0.200 REF

0.00 – 0.05

0.75 ± 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

3738f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

31

LTC3738

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

Reduces C and C , Power Good Output Signal, Synchronizable,

LTC1628/LTC1628-PG/ 2-Phase, Dual Output Synchronous Step-Down

IN

OUT

LTC1628-SYNC

DC/DC Controllers

3.5V ≤ V ≤ 36V, I

up to 20A, 0.8V ≤ V

≤ 5V

IN

OUT

LTC1629/

20A to 200A PolyPhase Synchronous Controllers

Expandable from 2-Phase to 12-Phase, Uses All

LTC1629-PG

Surface Mount Components, No Heat Sink, V up to 36V

IN

LTC1702

No R

^TM2-Phase Dual Synchronous Step-Down

550kHz, No Sense Resistor

SENSE

Controller

LTC1703

No R

2-Phase Dual Synchronous Step-Down

Mobile Pentium^®III Processors, 550kHz,

V ≤ 7V

IN

SENSE

Controller with 5-Bit Mobile VID Control

LTC1708-PG

LT^®1709/

LT1709-8

2-Phase, Dual Synchronous Controller with Mobile VID

3.5V ≤ V ≤ 36V, VID Sets V

, PGOOD

IN

OUT1

High Efficiency, 2-Phase Synchronous Step-Down

Switching Regulators with 5-Bit VID

1.3V ≤ V

≤ 3.5V, Current Mode Ensures

OUT

Accurate Current Sharing, 3.5V ≤ V ≤ 36V

IN

LTC1735

LTC1736

LTC1778

High Efficiency Synchronous Step-Down

Switching Regulator

Output Fault Protection, 16-Pin SSOP

High Efficiency Synchronous Controller with 5-Bit Mobile Output Fault Protection, 24-Pin SSOP,

VID Control 3.5V ≤ V ≤ 36V

IN

No R Current Mode Synchronous Step-Down

Up to 97% Efficiency, 4V ≤ V ≤ 36V, 0.8V ≤ V

≤ (0.9)(V ),

OUT IN

SENSE

IN

Controller

I

up to 20A

OUT

LTC1929/

LTC1929-PG

2-Phase Synchronous Controllers

Up to 42A, Uses All Surface Mount Components,

No Heat Sinks, 3.5V ≤ V ≤ 36V

IN

LTC3708

2-Phase, Dual DC/DC Synchronous Buck Controller with Tracks Two or More Supplies, Fast Transient Response, No R

Output Tracking

SENSE

LTC3711

No R

Current Mode Synchronous Step-Down

Up to 97% Efficiency, Ideal for Pentium III Processors,

0.925V ≤ V ≤ 2V, 4V ≤ V ≤ 36V, I up to 20A

SENSE

Controller with Digital 5-Bit Interface

OUT

IN

OUT

LTC3717

LTC3719

DDR/QDR Memory Termination Regulator

V

= 0.5V , ±20A, ±0.65% V

Accuracy

OUT

IN

OUT

2-Phase, 5-Bit VID Current Mode, High Efficiency

Synchronous Step-Down Controller

AMD Hammer-K8 Processors, Wide V Range: 4V to 36V Operation

IN

LTC3729

LTC3731

LTC3732

LTC3733

LTC3734

LTC3735

20A to 200A, 550kHz PolyPhase Synchronous Controller Expandable from 2-Phase to 12-Phase, Uses all Surface Mount

Components, V up to 36V

IN

3-Phase, 600kHz Synchronous Buck

Switching Regulator Controller

Expandable from 3-Phase to 12-Phase, Uses all Surface Mount

Components, V up to 36V

IN

3-Phase, 5-Bit VID, 600kHz Synchronous Buck

Switching Regulator Controller

VRM9.0 and VRM9.1 (VID = 1.1V to 1.85V)

3-Phase, 5-Bit VID, 600kHz Synchronous Buck

Switching Regulator Controller

AMD Opteron^TM(VID = 0.8V to 1.55V)

Single Phase DC/DC Controller for Intel IMVP-4

Compatible Processors

6-Bit IMVP-4 VID: 0.7V ≤ V

≤ 1.708V, 4V ≤ V ≤ 30V, I ≤ 25A,

OUT

IN

Lossless Voltage Positioning

2-Phase DC/DC Controller for Pentium (Centrino)

Processors

40A, 0.7V ≤ V ≤1.708V, 4V ≤ V ≤ 30V

OUT

IN

No R

is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.

SENSE

Opteron is a trademark of AMD Corporation.

3738f

LT/TP 0604 1K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3738CUHF
厂家：	Linear
描述：	3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning 3相降压控制器，用于Intel VRM9 / VRM10与有源电压定位稳压器开关式稳压器或控制器电源电路开关式控制器
文件：	总32页 (文件大小：316K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3738CUHF [Linear]

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