LTC3779HFE#PBF_技术文档

LTC3779

150V V and V Synchronous

IN

OUT

4-Switch Buck-Boost Controller

FeaTures

DescripTion

The LTC^®3779 is a high performance buck-boost switching

regulator controller that operates from input voltages

above, below or equal to the output voltage. The constant

frequency current mode architecture allows a phase-

lockable frequency of up to 600kHz, while an input/output

constant current loop provides support for battery charging.

n

4-Switch Current Mode Single Inductor Architecture

Allows V Above, Below or Equal to V

IN

OUT

n

Wide V Range: 4.5V to 150V

IN

Wide Output Voltage Range: 1.2V ≤ V

≤ 150V

OUT

Synchronous Rectification: Up to 99% Efficiency

1% 1.2V Voltage Reference

Input or Output Average Current Limit

With a wide 4.5V to 150V input and output range and

seamless transfers between operating regions, the

LTC3779 is ideal for automotive, telecom and battery-

powered systems.

On-Board LDO or External NMOS LDO for DRV

CC

36V EXTV LDO Powers Drivers

CC

Programmable 6V to 10V DRV Optimizes Efficiency

CC

No Top FET Refresh Noise in Boost or Buck Mode

The LTC3779 features a precision 1.2V reference and

power good output indicator. The MODE pin can select

between pulse-skipping mode or forced continuous mode

of operation. Pulse-skipping mode offers high efficiency

at light load while forced continuous mode operates at

a constant frequency for noise sensitive applications.

The PLLIN pin allows the IC to be synchronized to an

external clock. The SS pin ramps the output voltage

during start-up. Current foldback limits MOSFET heat

dissipation during short-circuit conditions.

V

Disconnected from V During Shutdown

OUT

IN

Phase-Lockable Fixed Frequency (50kHz to 600kHz)

No Reverse Current During Start-Up

Power Good Output Voltage Monitor

150V Rated RUN Pin with Accurate Turn-On Threshold

Programmable Input Overvoltage Lockout

Thermally Enhanced FE38 TSSOP Package Modified

for High Voltage Operation

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Analog

Devices, Inc. All other trademarks are the property of their respective owners.

applicaTions

n

Industrial, Automotive, Medical, Military, Avionics

Typical applicaTion

V

IN

20V TO 120V

4mΩ

V

48V

10A

OUT

5µF

20µF

Efficiency and Power Loss

vs Input Voltage

30µF

56µF

1k

V

BOOST1

INSNS

5Ω

0.1µF

100

98

96

94

92

90

30

24

18

12

6

V

0.22µF

IN

15µH

SW1

TG1

BG1

10k

RUN

EFFICIENCY

133k

1.21k

V

INOV

475k

100Ω

220pF

100Ω

SENSEP

4mΩ

NDRV

SENSEN

SGND

DRV

CC

LTC3779

PGND

10µF

BG2

V5

BOOST2

2.2µF

SS

V

I

= 48V

= 10A

POWER LOSS

0.22µF

OUT

0.1µF

FREQ

SW2

0

56.2k

TG2

0

12 24 36 48 60 72 84 96 108 120

100Ω

I

AVGSNSP

V

VOLTAGE (V)

IN

4.7µF

3779 TA01b

100Ω

I

TH

I

AVGSNSN

1k

10k

V

OUTSNS

100pF

V

FB

10nF

3779 TA01a

12.1k

3779f

1

For more information www.linear.com/LTC3779

LTC3779

absoluTe MaxiMuM raTings

pin conFiguraTion

(Note 1)

TOP VIEW

Input Supply Voltage (V )....................... 150V to –0.3V

IN

1

2

SW1

38

37

36

BG1

VINOV

Topside Driver Voltage

TG1

BOOST1, BOOST2.....................................161V to –0.3V

Switch Voltage SW1, SW2.......................... 150V to –5V

RUN ......................................................... 150V to –0.3V

3

BOOST1

DRVSET

SGND

4

5

V

IN

34

32

30

28

26

24

EXTV

CC

I

, I

....................................150V to –10V

...................................... 150V to –0.3V

AVGSNSP AVGSNSN

6

NDRV

V

, V

INSNS OUTSNS

7

V

DRV

CC

INSNS

EXTV Voltage ........................................ 36V to –0.3V

CC

8

V5

SS

NDRV Voltage ....................................................(Note 9)

9

V

OUTSNS

39

PGND

DRV Voltage ............................................11V to –0.3V

10

11

12

13

14

15

16

17

18

19

V

FB

CC

BOOST1-SW2, BOOST2-SW2 .....................11V to –0.3V

TG1-SW1, TG2-SW2, BG1, BG2..........................(Note 8)

V5 Voltage.................................................... 6V to –0.3V

MODE, PLLIN, SS, PGOOD .......................... V5 to –0.3V

ITH, FREQ, DRVSET..................................... V5 to –0.3V

SENSEP, SENSEN, VINOV ............................ V5 to –0.3V

I

SENSEP

SENSEN

ITH

AVGSNSN

I

AVGSNSP

SGND

MODE

PLLIN

FREQ

RUN

BOOST2

TG2

22

21

20

V

Voltage ............................................... 2.7V to –0.3V

FB

PGOOD

BG2

Operating Junction Temperature

SW2

Range (Notes 2, 3)................................. –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

FE PACKAGE

VARIATION: FE38(31)

38-LEAD PLASTIC TSSOP

EXTV /DRV Peak Current ..............................100mA

CC

T

= 150°C, θ = 28°C/W

JA

JMAX

EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB

FOR RATED ELECTRICAL AND THERMAL CHARACTERISTICS

http://www.linear.com/product/LTC3779#orderinfo

orDer inForMaTion

LEAD FREE FINISH

LTC3779EFE#PBF

LTC3779IFE#PBF

LTC3779HFE#PBF

TAPE AND REEL

PART MARKING

LTC3779FE

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3779EFE#TRPBF

LTC3779IFE#TRPBF

LTC3779HFE#TRPBF

38-Lead Plastic TSSOP

–40°C to 125°C

–40°C to 150°C

LTC3779FE

Consult LTC Marketing for parts specified with wider operating temperature ranges.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

3779f

2

For more information www.linear.com/LTC3779

LTC3779

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2), V_IN= 15V, V_RUN= 5V, V_EXTVCC= 0V, V_DRVSET= 0V,

V_VINOV= 0V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

4.5

TYP

MAX

150

1.212

-50

UNITS

V

Input Supply Operating Voltage Range

Output Supply Operating Voltage Range

Regulated Feedback Voltage

Feedback Current

(Note 4)

V

IN

1.2

OUT

l

(Note 5); ITH Voltage = 1.4V

(Note 5)

1.188

1.2

–15

0.02

0.01

V

nA

%

Reference Voltage Line Regulation

Output Voltage Load Regulation

(Note 5); V = 7V to 100V

0.2

IN

(Note 5); Measured in Servo Loop; ∆ITH

Voltage = 1.5V to 2V

0.2

Transconductance Amplifier gm

Input DC Supply Current

Shutdown

(Note 5); ITH = 1.4V; Sink/Source 5µA

(Note 6)

1.5

3.6

mmho

mA

µA

V

I

Q

RUN = 0V

40

Undervoltage Lockout

V5 Ramping Up

4.1

3.6

1.1

4.35

3.85

1.2

4.6

4.1

1.3

V5 Ramping Down

V

RUN Pin ON Threshold

RUN Pin Hysteresis

V

Rising

V

RUN

100

2.5

mV

µA

V

RUN Pin Source Current

RUN Pin Hysteresis Current

V

< 1.2V

> 1.2V

RUN

6.5

RUN

V

Overvoltage Lockout Threshold

Rising

1.18

1.28

1.38

IN

VINOV

(Rising)

V

Overvoltage Hysteresis

50

mV

µA

IN

SENSE Pins Current

Pins Current

V

= V

= 0

SENSEN

2

SENSEP

I

= V = 10V

IAVGSNSN

15

AVGSNSP

AVGSNSN

AVGSNS

IAVGSNSP

Soft-Start Charge Current

V

= 0V

= 1V

4

5

6

µA

SS

FB

l

V

Maximum Current Sense Threshold

(Buck Region Valley Current Mode)

70

90

110

mV

SENSE(MAX)

Maximum Current Sense Threshold

(Boost Region Peak Current Mode)

V

= 1V

120

140

50

160

mV

FB

Maximum Input / Output Average

Current Sense Threshold

= V

= 10V, V = 1V

47.5

52.5

IAVGSNSP

IAVGSNSN

FB

DF

Maximum Duty Factor

% Switch C On

90

9

%

MAX, BOOST

Minimum Duty Factor for Main Switch in % Switch C On

Boost Operation

ON(MIN, BOOST)

DF

Minimum Duty Factor for Main Switch in % Switch B On

Buck Operation

9

%

ON(MIN, BUCK)

Gate Driver

TG Pull-Up On Resistance

V

= 9V

3.1

1.3

Ω

DRVCC

TG Pull-Down On Resistance

BG Pull-Up On Resistance

BG Pull-Down On Resistance

= 9V

5.5

3

TG Transition Time:

Rise Time

Fall Time

V

C

= 9V (Note 7)

= 3300pF

60

ns

LOAD

BG Transition Time:

Rise Time

Fall Time

V

C

= 9V (Note 7)

DRVCC

= 3300pF

ns

LOAD

3779f

3

For more information www.linear.com/LTC3779

LTC3779

elecTrical characTerisTics ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C (Note 2), V_IN= 15V, V_RUN= 5V, V_EXTVCC= 0V, V_DRVSET= 0V,

V_VINOV= 0V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

C

= 3300pF Each Driver, V

= V5

60

ns

LOAD

DRVSET

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

C

= 3300pF Each Driver, V

60

ns

LOAD

DRV LDO Regulator

CC

V

DRV Regulation Voltage from NDRV

NDRV Driving External NFET, V

= 0V

DRVCC

CC

EXTVCC

Regulator

7V < V < 150V, V

= 0V

5.8

6.8

6.1

7.1

8.1

9.1

10

6.4

7.4

V

IN

DRVSET

8V < V < 150V, V

= 1/4 V

= Float

V5

9V < V < 150V, V

7.8

8.4

IN

10V < V < 150V, V

= 3/4 V

8.75

9.65

9.45

10.35

IN

V5

11V < V < 150V, V

= V

V5

IN

DRV Regulation Voltage from Internal

IN

V

= V , V

DRVCC EXTVCC

= 0V

CC

NDRV

V

LDO

7V < V < 150V, V

5.5

6.5

5.8

6.8

7.8

8.8

9.5

6.1

7.1

V

IN

DRVSET

8V < V < 150V, V

= 1/4 V

= Float

V5

9V < V < 150V, V

7.5

8.1

10V < V < 150V, V

= 3/4 V

= V

V5

8.45

9.15

9.85

IN

DRVSET

V5

11V < V < 150V, V

DRV Load Regulation from V LDO

I

= 0mA to 50mA, V

EXTVCC

= 0V

0.5

2

%

CC

IN

CC

V

DRV Regulation Voltage from Internal 7V < V

< 30V, V

5.8

6.8

6.1

7.1

8.1

9.1

10

6.4

7.4

8.4

9.45

10.35

V

EXTVCC

CC

EXTVCC

DRVSET

EXTV LDO

8V < V

9V < V

10V < V

11V < V

= 1/4 V

= Float

CC

V5

7.8

< 30V, V

= 3/4 V

8.75

9.65

EXTVCC

DRVSET

V5

= V

V5

DRV Load Regulation from Internal

I

= 0mA to 50mA, V = 12V

EXTVCC

DRVSET

0.5

2

%

CC

EXTV LDO

V

= 0V

CC

EXTV LDO Switchover Voltage

EXTV Ramping Positive

DRV – 0.5

V

CC

EXTV Hysteresis

% of DRV Regulation Voltage

10

%

CC

V5 Linear Regulator

V5 Regulation Voltage

6V < V

< 10V

5.3

5.5

0.5

5.7

1

V

DRVCC

V5 Load Regulation

Oscillator and Phase-Locked Loop

Nominal Frequency

I

V5

= 0mA to 20mA, V

= 7V

%

DRVCC

R

FREQ

R

FREQ

R

FREQ

= 68.5kΩ

≤ 20kΩ

225

30

250

40

275

50

kHz

Low Fixed Frequency

High Fixed Frequency

= 135kΩ

450

2

500

550

PLLIN Input Threshold

V

Rising

Falling

V

PLLIN

1.2

PLLIN Input Resistance

200

20

kΩ

kHz

µA

l

Synchronizable Oscillator Frequency

Frequency Setting Current

PLLIN = External Clock

50

18

600

22

I

FREQ

PGOOD Output

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level

I

= 2mA

= 5.5V

0.1

0.3

1

V

PGOOD

V

µA

PGOOD

with Respect to Set Regulated Voltage

Ramping Negative

FB

–10

10

%

µs

FB

Ramping Positive

FB

PGOOD delay

High to Low

125

PGOOD

3779f

4

For more information www.linear.com/LTC3779

LTC3779

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 3: This IC includes over temperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

Continuous operation above the specified absolute maximum operating

junction temperature may impair device reliability or permanently damage

the device.

Note 2: The LTC3779 is tested under pulsed load conditions such that T

J

≈ T . The LTC3779E is guaranteed to meet performance specifications

A

from 0°C to 85°C junction temperature. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3779I is guaranteed over the full –40°C to 125°C operating junction

temperature range. The LTC3779H is guaranteed over the full –40°C to

150°C operating junction temperature range. High junction temperature

degrades operating lifetimes; operating lifetime is derated for junction

temperatures greater than 125°C. Note that the maximum ambient

temperature consistent with these specifications is determined by

specific operating conditions in conjunction with board layout, the rated

Note 4: When biased from an auxiliary supply through the EXTV pin, the

CC

LTC3779 can operate from a V voltage lower than 4.5V. Otherwise the

IN

minimum V operational voltage is 4.5V after startup.

IN

Note 5: The LTC3779 is tested in a feedback loop that servos V to a

ITH

specified voltage and measures the resultant V

.

FB

Note 6: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications information.

Note 7: Rise and fall times are measured using 10% and 90% levels.

Delay times are measured using 50% levels.

Note 8: Do not apply a voltage or current source to these pins. They must

be connected to capacitive loads only, otherwise permanent damage may

occur. These pins are rated for an absolute maximum voltage of –0.3V to

11V.

package thermal impedance and other environmental factors. The junction

temperature T is calculated from the ambient temperature T and power

J

A

dissipation P according to the formula:

D

T = T + (P • θ ),

J

A

D

JA

Note 9: Do not apply a voltage or current source to the NDRV pin, other

where θ = 28°C/W for the TSSOP package.

JA

than tying NDRV to DRV when not used. If used it must be connected

CC

to capacitive loads only (see DRVCC Regulator in the Applications

Information section), otherwise permanent damage may occur.

3779f

5

For more information www.linear.com/LTC3779

LTC3779

Typical perForMance characTerisTics

Efficiency and Power Loss

vs Load Current and Input Voltage

Continuous Mode

Efficiency and Power Loss

vs Input Voltage

100

96

92

88

84

80

76

72

68

64

60

10

9

8

7

6

5

4

3

2

1

0

100

97

94

91

88

85

10

8

V

OUT

= 12V

OUT

EFFICIENCY

FIGURE 17 CIRCUIT

I

= 5A

V

SW

= 48V

OUT

f

= 250kHz

6

EFFICIENCY

V

IN

V

IN

V

IN

= 72V

= 48V

= 24V

4

POWER LOSS

2

POWER LOSS

0

0.1

1

10

5

10 15 20 25 30 35 40 45 50 55

LOAD CURRENT (A)

VIN VOLTAGE (V)

3779 G01

3779 G02

Load Step Boost Region

Continuous Mode

Load Step Boost Region

Pulse-Skipping Mode

Load Step Buck-Boost Region

Continuous Mode

I

LOAD

I

LOAD

5A/DIV

I

L

I

L

5A/DIV

V

OUT

1V/DIV

AC-COUPLED

3779 G03

3779 G04

3779 G05

200µs/DIV

V

= 36V

V

= 36V

V

= 48V

IN

OUT

IN

OUT

IN

OUT

= 48V

Load Step Buck-Boost Region

Pulse-Skipping Mode

Load Step Buck Region

Continuous Mode

Load Step Buck Region

Pulse-Skipping Mode

I

LOAD

5A/DIV

I

L

5A/DIV

V

OUT

1V/DIV

AC-COUPLED

3779 G07

3779 G08

3779 G06

200µs/DIV

V

= 120V

= 48V

V

= 120V

IN

= 48V

OUT

V

= 48V

IN

OUT

IN

OUT

= 48V

3779f

6

For more information www.linear.com/LTC3779

LTC3779

Typical perForMance characTerisTics

Forced Continuous Mode

Buck-Boost Region

Forced Continuous Mode

Boost Region

Pulse-Skipping Mode

Boost Region

SW1

100V/DIV

SW1

100V/DIV

SW1

100V/DIV

SW2

100V/DIV

SW2

100V/DIV

SW2

100V/DIV

I

L

1A/DIV

5A/DIV

V

OUT

200mV/DIV

AC-COUPLED

3779 G11

3779 G09

3779 G10

5µs/DIV

V

= 48V

V

I

V

I

IN

OUT

IN

OUT

V

I

= 48V

= 0A

OUT

LOAD

Pulse-Skipping Mode

Buck-Boost Region

Forced Continuous Mode

Buck Region

Pulse-Skipping Mode

Buck Region

SW1

100V/DIV

SW1

100V/DIV

SW1

100V/DIV

SW2

100V/DIV

SW2

100V/DIV

SW2

100V/DIV

I

L

5A/DIV

1A/DIV

V

OUT

200mV/DIV

AC-COUPLED

3779 G13

3779 G14

3779 G12

5µs/DIV

V

I

= 120V

= 48V

LOAD

V

I

= 120V

= 48V

OUT

LOAD

V

I

= 48V

IN

OUT

IN

OUT

= 48V

= 0A

LOAD

Start-Up from RUN

Forced Continuous Mode

Pre-Biased Output

Start-Up Forced Continuous Mode

Boost Region

Start-Up Forced Continuous Mode

Buck-Boost Region

SW1

50V/DIV

SW1

100V/DIV

SW2

100V/DIV

SW2

100V/DIV

SW2

50V/DIV

100V/DIV

I

L

I

L

I

L

500mA/DIV

5A/DIV

V

OUT

50V/DIV

3779 G16

3779 G17

3779 G15

5ms/DIV

2.5ms/DIV

V

= 24V

V

= 48V

V

= 24V

IN

OUT

IN

OUT

IN

= 48V

OUT

200mA LOAD

15Ω RESISTIVE LOAD

PRE-BIAS = 12V

3779f

7

For more information www.linear.com/LTC3779

LTC3779

Typical perForMance characTerisTics

Shutdown from RUN

Pulse-Skipping Mode

Boost Region

Start-Up Forced Continuous Mode

Buck Region

Forced Continuous Mode

Boost Region

RUN

5V/DIV

RUN

5V/DIV

SW1

100V/DIV

SW1

100V/DIV

SW2

100V/DIV

SW2

100V/DIV

SW2

100V/DIV

I

L

500mA/DIV

20A/DIV

V

OUT

50V/DIV

V

50V/DIV

OUT

50V/DIV

3779 G20

3779 G19

3779 G18

200µs/DIV

5ms/DIV

V

= 24V

V

= 24V

V

= 120V

= 48V

IN

OUT

IN

OUT

IN

OUT

= 48V

5A LOAD

15Ω RESISTIVE LOAD

Shutdown from RUN

Forced Continuous Mode

Buck-Boost Region

Shutdown from RUN

Forced Continuous Mode

Buck Region

Line Transient Rising Edge

RUN

5V/DIV

V

IN

SW1

100V/DIV

SW1

100V/DIV

12V to 120V

SW2

I

SW2

TH

100V/DIV

2V/DIV

100V/DIV

I

L

I

L

I

L

20A/DIV

1A/DIV

2A/DIV

V

OUT

V

OUT

V

OUT

500mV/DIV

50V/DIV

AC-COUPLED

3779 G22

3779 G21

3779 G23

200µs/DIV

1ms/DIV

V

I

= 120V

= 48V

LOAD

V

= 48V

V

= 48V

IN

OUT

IN

OUT

= 48V

= 5A

NO LOAD

Line Transient Falling Edge

DRV_CCvs Load Current

10.5

10.0

9.5

6.5

6.0

5.5

5.0

V

LDO (No NDRV FET), EXTV = 0V

CC

labelV2435 LDO (No NDRV FET), EXTV = 0V

IN

CC

NDRV LDO (NDRV FET), EXTV = 0V

CC

V

IN

EXTV = 12V (No NDRV FET)

EXTV = 8.5V (No NDRV FET)

CC

100V/DIV

I

TH

2V/DIV

I

L

1A/DIV

V

OUT

500mV/DIV

AC-COUPLED

3779 G24

1ms/DIV

V

= 12V

V = 12V

IN

DRVSET = V5

IN

V

= 48V

OUT

DRVSET = 0V

9.0

0

20

40

60

80

100

0

20

40

60

80

100

LOAD CURRENT (mA)

3779 G25

3779 G26

3779f

8

For more information www.linear.com/LTC3779

LTC3779

Typical perForMance characTerisTics

VINOV Transient Forced

Continuous Mode Buck Region

Peak Current Threshold vs V_ITH

(Boost)

Current Foldback Limit

200

150

100

50

200

150

100

50

SW1

BOOST

100V/DIV

SW2

100A/DIV

I

L

10A/DIV

0

V

OUT

50V/DIV

–50

–100

–150

–50

–100

–150

3779 G27

10ms/DIV

V

= 120V

OUT

IN

BUCK

= 48V

50Ω RESISTIVE LOAD

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

(V)

0

0.4 0.8 1.2 1.6 2.0 2.4 2.8

(V)

V

FB

ITH

3779 G28

3779 G29

Valley Current Threshold vs V_ITH

(Buck)

Regulated Feedback Voltage

vs Temperature

Maximum Current Limit

vs Temperature

100

50

200

150

100

50

1220

1210

1200

1190

1180

BOOST

0

–50

–100

BUCK

–100

–150

–50 –25

0

0.2 0.4 0.6 0.8 1.1 1.3 1.5 1.7 1.9 2.1

(V)

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

V

TEMPERATURE (°C)

ITH

3779 G30

3779 G31

3779 G32

Undervoltage Lockout Threshold

(V5) vs Temperature

V5 Low Dropout Regulation

Voltage vs Temperature

EXTV_CCLDO vs Temperature

4.4

4.3

4.2

4.1

4.0

3.9

3.8

3.7

3.6

5.7

5.6

5.5

5.4

5.3

12

11

10

9

EXTV = 30V

CC

RISING

DRVSET = V5

DRVSET = 3/4 • V5

DRVSET = 1/2 • V5

8

DRVSET = 1/4 • V5

7

DRVSET = GND

FALLING

6

5

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3779 G33

3779 G34

3779 G35

3779f

9

For more information www.linear.com/LTC3779

LTC3779

Typical perForMance characTerisTics

Oscillator Frequency

vs Temperature

NDRV LDO vs Temperature

V_INLDO vs Temperature

800

700

600

500

400

300

200

100

0

12

11

10

9

12

11

10

9

FREQ = V5

DRVSET = V5, V = 11V

IN

DRVSET = V5, V = 11V

IN

DRVSET = 3/4 • V5, V = 10V

R

= 120k

FREQ

IN

DRVSET = 3/4 • V5, V = 10V

IN

DRVSET = 1/2 • V5, V = 9V

IN

DRVSET = 1/2 • V5, V = 9V

8

IN

8

R

FREQ

= 67.5k

DRVSET = 1/4 • V5, V = 8V

IN

DRVSET = 1/4 • V5, V = 8V

IN

7

DRVSET = GND, V = 7V

IN

DRVSET = GND, V = 7V

R

FREQ

= 27.5k

IN

FREQ = GND

6

5

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3779 G38

3779 G36

3779 G37

EXTV = 0V

CC

Frequency Setting Current

vs Temperature

Input Supply Current

vs Temperature

5

4

3

2

1

0

20.5

20.4

20.3

20.2

20.1

20.0

19.9

19.8

19.7

19.6

19.5

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3779 G40

3779 G39

V

= 0.8V

FREQ

Soft-Start Pull-Up Current

vs Temperature

RUN Threshold vs Temperature

5.2

1.4

1.3

1.2

1.1

1.0

0.9

ON

OFF

5.1

5.0

4.9

–50 –25

0

25 50 75 100 125 150

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3779 G42

3779 G41

3779f

10

For more information www.linear.com/LTC3779

LTC3779

pin FuncTions

BG1/BG2 (Pins 1 and 19): Bottom Gate Driver Outputs.

DRV_CC(Pin 7): Output of the Internal or External Low

Dropout Regulator. The gate drivers are powered from

this voltage source. The DRV_CCvoltage is set by the

DRVSET pin. A low ESR 4.7µF (X5R or better) ceramic

bypass capacitor should be connected between DRV_CC

and PGND, as close as possible to the IC. Do not use the

This pin drives the gate(s) of the bottom N-Channel

MOSFET between PGND to DRV .

CC

VINOV (Pin 2): Connect to the input supply through a

resistor divider to set the over-voltage lockout level. A

voltage on this pin above 1.28V disables all switching,

and the top GATE pins are held low, the bottom GATE pins

DRV pin for any other purpose.

CC

are held high, and V

is disconnected from V . DRV

V5 (Pin 8): Output of the Internal 5.5V Low Dropout

Regulator. The control circuits are powered from this

voltage. Bypass this pin to SGND with a minimum of

4.7µF low ESR tantalum or ceramic capacitor, as close

as possible to the IC.

OUT

IN

CC

and V5 regulation is maintained during an over-voltage

event. Normal operation resumes when the voltage on this

pin decreases below 1.23V. Exceeding the VINOV lockout

threshold triggers a soft-start reset, resulting in a graceful

recovery from an input supply transient. Tie this pin to

ground if the overvoltage function is not used.

SS (Pin 9): Soft-Start Input. The voltage ramp rate at this

pin sets the voltage ramp rate of the regulated voltage.

This pin has a 5μA pull-up current. A capacitor to ground

at this pin sets the ramp time to final regulated output

voltage.

DRVSET (Pin 3): Sets the regulated output voltage of the

DRV linear regulator from 6V to 10V in 1V increments.

CC

Tying this pin to SGND sets DRV_CCto 6V, tying it to

1/4•V5 sets DRV_CCto 7V, while floating this pin sets

V

(Pin 10): Error Amplifier Input. The FB pin should be

FB

DRV to 8V, tying it to 3/4•V5 sets DRV to 9V, and

CC

connected through a resistive divider network to V

to

OUT

tying it to V5 sets DRV to 10V.

CC

set the output voltage.

SGND (Pins 4 and 14): Signal ground. All feedback

and soft-start connections should return to SGND. For

optimum load regulation, the SGND pin should be Kelvin

connected to the PCB location between the negative

terminals of the output capacitors.

SENSEP (Pin 11): The positive input to the differential

current comparator. This pin is normally connected to a

sense resistor at the source of the power MOSFET. The ITH

pin voltage and controlled offsets between the SENSEP

and SENSEN pins, in conjunction with R_SENSE, set the

current trip threshold.

EXTV (Pin 5): External Power Input to an Internal LDO

Conn^Ce^Ccted to DRV_CC. When the voltage on this pin is

SENSEN (Pin 12): The negative input to the differential

current sense comparator. This pin is normally connected

to the ground side of the sense resistor.

greater than the DRV LDO setting minus 500mV, this

CC

LDO bypasses the internal LDO powered from V or the

IN

external LDO connected to NDRV. Tie this pin to ground

ITH (Pin 13): Error Amplifier Output. The current

comparator trip threshold increases with the ITH control

voltage. The ITH pin is also used for compensating the

control loop of the converter.

if the EXTV is not used.

CC

NDRV (Pin 6): Drive Output for External Pass Device of

the LDO Regulator connected to DRV . Connect to the

gate of an external NMOS pass devi^Cc^Ce. To disable the

MODE (Pin 15): Mode Selection pin. Tying this pin to

SGND or below 0.8V enables forced continuous mode.

Tying it to V5 enables pulse-skipping mode.

external linear regulator, tie NDRV to DRV . An internal

CC

charge pump can drive NDRV above V for low dropout

IN

performance.

3779f

11

For more information www.linear.com/LTC3779

LTC3779

pin FuncTions

PLLIN (Pin 16): External Synchronization Input to Phase

Detector. For external sync, apply a clock signal to this pin

and the internal PLL will synchronize the internal oscillator

to the clock. The PLL compensation network is integrated

into the IC. When synchronized to an external clock, the

regulator can operate either in forced continuous or pulse-

skipping mode. The mode of operation is controlled by

the setting on the MODE pin.

RUN (Pin 24): Enable Control Input. A voltage above 1.2V

turns on the IC. There is a 2.5µA pull-up current on this

pin. Once the RUN pin rises above the 1.2V threshold the

pull-up current increases to 6.5µA. Forcing this pin below

1.1V shuts down the controller. This pin can be tied to V

for always-on operation. Do not float this pin.

IN

I

(Pin 26): The positive input to the Input / Output

AVGSNSP

Average Current Sense Amplifier.

FREQ (Pin 17): The frequency control pin for the internal

VCO. Frequencies between 50kHz and 600kHz can be

programmed by using a resistor between FREQ and

SGND. The resistor and an internal 20µA source current

create a voltage used by the internal oscillator to set the

frequency.

I_AVGSNSN(Pin 28): The negative input to the Input / Output

Average Current Sense Amplifier. Short I_AVGSNSPand

I

pins together, and tie them to V5, if this average

AVGSNSN

current loop function is not used.

V

(Pin 30): V

Sense Input to the Buck-Boost

OUT

Tr^Oa^Un^Ts^Sit^Nio^Sn comparator. Connect this pin to the drain of

the top N-channel MOSFET on the output side through

a 1kΩ resistor.

PGOOD (Pin 18): Fault indicator Output. Open-drain

output that pulls to ground when the voltage on the V

pin is not within 10ꢀ of its set point.

FB

V_INSNS(Pin 32): V_INSense Input to the Buck-Boost

Transition comparator. Connect this pin to the drain of

the top N-channel MOSFET on the input side.

SW1, SW2 (Pins 20 and 38): Switch Node Connections

to the Inductors.

TG1, TG2 (Pin 21 and 37): High Current Gate Drives

for Top N-Channel MOSFETs. These are the outputs of

floating high side drivers with a voltage swing equal to

V (Pin 34): Main Supply Pin. A bypass capacitor should

IN

be tied between this pin and the PGND pin.

PGND (Exposed Pad Pin 39): Driver Power Ground.

DRV superimposed on the switch node voltage SW.

CC

Connects to the (–) terminal of C_IN, C_OUTand R_SENSE

.

BOOST1. BOOST2 (Pin 22 and 36): Boosted Floating

Driver Supplies. The (+) terminal of the bootstrap

capacitor connects to this pin. This pin swings from a

The exposed pad must be soldered to PCB ground for

electrical contact and rated thermal performance.

diode drop below DRV up to V + DRV .

CC

IN

CC

3779f

12

For more information www.linear.com/LTC3779

LTC3779

block DiagraM

DRV

CC

V

IN

V

/BOOST2

/BOOST1

BOOST1

BOOST2

OUT

CHARGE

D

A

CONTROL

V

IN

BOOST1

TG1

C

A

FCB

CCM/DCM

FET A

V

INOV

I

DREV

+

–

D1

OV

V

SW1

+

–

IN

BUCK

LOGIC

DRV

CC

1.2V

SW1

BG1

PGND

BG2

–

+

SHDN

FET B

2.5µA

I

REV

RUN

+

–

R

SENSE

FCB

DRV

CC

BOOST

LOGIC

SW2

TG2

V

FLD

FET D

FET C

D2

I

V

CMP

INSNS

+

–

BUCK/BOOST

TRANSITION

DETECTOR

C

B

BOOST2

BBT

V

OUTSNS

D

OV/SHDN

B

DRV

CC

I

AVGSNSP

+

–

A1

R

SENSE2

CCM

DCM

MODE

SELECT

I

AVGSNSN

SLOPE

V

OUT

+

200k

I

OS

–

EA

V

FB

–

+

PLLIN

FREQ

1.2V

SS

PHASE DET

20µA

5µA

200k

I

TH

OSCILLATOR

SENSEP

SENSEN

1.32V

+

–

PGOOD

CHARGE

PUMP

V

IN

V

FB

DRV LDO

CC

CONTROL

V

IN

–

+

EN

1.08V

NDRV

DRVSET

+

–

+

–

NDRV

–

NDRV LDO

V

LDO

EXTV LDO

CC

IN

+

–

DRV

CC

4R

1R

V5

LDO

C

DRVCC

V5

UVLO

SGND

EXTV

DRVSET

V5

CC

3779 BD

C

V5

3779f

13

For more information www.linear.com/LTC3779

LTC3779

operaTion

MAIN CONTROL LOOP

If EXTV is taken above its switchover voltage, the V

and ND^CR^CV LDOs are turned off and an EXTV LDO ^Ii^Ns

CC

The LTC3779 is a current mode controller that provides

an output voltage above, equal to or below the input volt-

age. The LTC proprietary topology and control architecture

employs a current-sensing resistor. The inductor current

is controlled by the voltage on the I pin, which is the

output of the error amplifier EA. The V pin receives the

voltage feedback signal, which is compared to the internal

reference voltage by the EA. If the input/output current

regulation loop is implemented, the sensed inductor

current is controlled by either the sensed feedback voltage

or the input/output current.

turned on. Once enabled, the EXTV_CCLDO supplies power

from EXTV to DRV . Using the EXTV pin allows the

CC

DRV power to be derived from a high efficiency external

sour^Cc^Ce such as the LTC3779 switching regulator output.

TH

FB

Most of the internal circuitry is powered from the V5

rail that is generated by an internal linear regulator from

DRV . The V5 pin needs to be bypassed with a 1µF to

CC

10µF external capacitor between V5 and SGND. This pin

provides a 5.5V output that can supply up to 20mA of

current. See the Applications Information section for more

details.

DRV /EXTV /V5 Power

CC

Top MOSFET DRIVER and Internal Charge Path

Power for the top and bottom MOSFET drivers is derived

from the DRV pin. The DRV supply voltage can be

Each of the two top MOSFET drivers is biased from its

floating bootstrap capacitor, which is normally recharged

by DRV_CCthrough an external diode when the top MOSFET

is turned off and when SW goes low. When the LTC3779

operates exclusively in the buck or boost regions, one

of the top MOSFETs is constantly on. An internal charge

programmed ^Cfr^Com 6V to 10V in 1V steps using the

DRVSET pin. Two separate LDOs (low dropout linear

regulators) can provide power from V_INto DRV_CC. The

CC

internal V LDO uses an internal P-channel pass device

IN

between the V_INand DRV_CCpins. To prevent high on-chip

power dissipation in high input voltage applications, the

LTC3779 also includes an NDRV LDO that utilizes the

NDRV pin to supply power to DRV_CCby driving the gate of

an external N-channel MOSFET acting as a linear regulator

path, from V

and BOOST2 to B00ST1 or from V and

OUT

IN

B00ST1 to B00ST2, charges the bootstrap capacitor so

that the top MOSFET can be kept on. However, if a high

leakage external diode is used such that the internal charge

path cannot provide sufficient charge to the external

bootstrap capacitor, an internal UVLO comparator, which

constantly monitors the drop across the capacitor, will

sense the (BOOST – SW) voltage when it is below the

boost capacitor refresh threshold. This will turn off its top

MOSFET for about one-twelfth of the clock period every

four cycles to allow the bootstrap capacitor to recharge.

The boost capacitor refresh threshold varies with the

DRVSET pin setting.

with its source connected to DRV and drain connected

CC

to V . The NDRV LDO includes an internal charge pump

IN

that allows NDRV to be driven above V for low dropout

IN

performance.

When the EXTV_CCpin is tied to a voltage below its

switchover voltage (DRV –500mV), the V and NDRV

CC

IN

LDOs are enabled and one of them supplies power from

V to DRV . The V LDO has a slightly lower regulation

IN

point than^Ct^Che NDRV LDO. If the NDRV LDO is being

used with an external N-channel MOSFET, the gate of the

MOSFET tied to the NDRV pin is driven such that DRV

Shutdown and Start-Up

CC

The LTC3779 can be shut down by pulling the RUN pin

low. Pulling RUN below 1.1V shuts down the main control

loop for the controller and most internal circuits, including

regulates above the V LDO regulation point, causing all

DRV_CCcurrent to flo^Iw^Nthrough the external N-channel

MOSFET, and bypassing the internal V_INLDO pass device.

If the NDRV LDO is not being used, all DRV_CCcurrent

flows through the internal P-channel pass device between

the DRV and V5 regulators. Releasing RUN allows an

CC

internal 2.5µA current to pull-up the pin and enable the

controller. When RUN is above the accurate threshold of

the V and DRV pins.

IN

CC

3779f

14

For more information www.linear.com/LTC3779

LTC3779

operaTion

1.2V, the internal LDO will power up DRV . At the same

Power Switch Control

CC

time, a 6.5µA pull-up current will kick in to provide more

RUN pin hysteresis. The RUN pin may be externally pulled

up or driven directly by logic. The RUN pin can tolerate up

to 150V (absolute maximum), so it can be conveniently

Figure 1 shows a simplified diagram of how the four

power switches are connected to the inductor, V , V

IN

and GND. Figure 2 shows the regions of operation^Of^Uo^Tr

the LTC3779 as a function of V

– V or switch duty

OUT

IN

tied to V in always-on applications where the controller

IN

cycle, DC. The power switches are properly controlled so

the transfer between regions is continuous. Hysteresis is

added to prevent chattering when transitioning between

regions.

is enabled continuously and never shut down. The RUN

pin will have no internal pull-up current when externally

driven to a voltage above 4V.

V

IN

V

OUT

Soft-Start

TG1

BG1

A

D

TG2

BG2

The start-up of the controller’s output voltage V_OUTis

controlled by the voltage on the SS pin. When the voltage

on the SS pin is less than the 1.2V internal reference,

L

SW1

SW2

B

C

the LTC3779 regulates the V voltage to the SS voltage

FB

R

SENSE

instead of the 1.2V reference. This allows the SS pin to

be used to program soft-start by connecting an external

capacitor from the SS pin to SGND. An internal 5µA

pull-up current charges this capacitor, creating a voltage

ramp on the SS pin. As the SS voltage rises linearly from

3779 F01

Figure 1. Simplified Diagram of the Output Switches

0V to 1.2V (and beyond), the output voltage V

rises

OUT

D

MAX

BOOST

smoothly from zero to its final value. When RUN is pulled

low to disable the controller, or during an overvoltage

event on the V_INinput supply or during an overtemperature

shutdown event, or when V5 drops below its undervoltage

lockout threshold of 3.85V, the SS pin is pulled low by

an internal MOSFET. When in undervoltage lockout, the

controller is disabled and the external MOSFETs are held

off.

A ON, B OFF

PWM C, D SWITCHES

BOOST REGION

BUCK/BOOST REGION

BUCK REGION

D

MIN

BOOST

FOUR SWITCH PWM

D

MAX

BUCK

D ON, C OFF

PWM A, B SWITCHES

D

MIN

BUCK

3779 F02

Figure 2. Operating Region vs Duty Cycle

Certain applications can require the start-up of the

converter into a non-zero load voltage, where residual

charge is stored on the V_OUTcapacitor at the onset of

converter switching. In order to prevent the V_OUTfrom

discharging under these conditions, the part will be forced

into discontinuous mode of operation until the SS voltage

crosses V or 1.32V, whichever is lower.

FB

3779f

15

For more information www.linear.com/LTC3779

LTC3779

operaTion

Buck Region (V >> V

)

Buck-Boost Region (V ≈ V

)

IN

OUT

IN

OUT

When V_INis significantly higher than V_OUT, the part will run

in the buck region. In this region switch C is always off. At

the start of every cycle, synchronous switch B is turned on

first. Inductor current is sensed when synchronous switch

B is turned on. After the sensed inductor valley current

falls below a reference voltage, which is proportional to

V_ITH, synchronous switch B is turned off and switch A

is turned on for the remainder of the cycle. Switches A

and B will alternate, behaving like a typical synchronous

buck regulator. The duty cycle of Switch A increases

until the maximum duty cycle of the converter reaches

When V_INis close to V_OUT, the controller enters the buck-

boost region. Figure 4 shows the typical waveforms in this

region. At the beginning of a clock cycle, if the controller

starts with B and D on, the controller first operates as if in

the buck region. When I

trips, switch B is turned off,

CMP

and switch A is turned on. At 120° clock phase, switch C is

turned on. The LTC3779 starts to operate as a boost until

I

trips. Then, switch D is turned on for the remainder

CMP

of the clock period. If the controller starts with switches

A and C on, the controller first operates as a boost, until

I

trips and switch D is turned on. At 120°, switch B is

CMP

DC

, given by:

turned on, making it operate as a buck. Then, I

trips,

(MAX_BUCK)

CMP

turning switch B off and switch A on for the remainder of

the clock period.

⎛

⎞

⎟

⎠

1

12

DC_(MAX,BUCK)= 1−

•100ꢀ = 91.67ꢀ

⎜

⎝

Figure 3 shows the typical buck region waveforms. If V

IN

CLOCK

approaches V , the buck-boost region is reached.

OUT

SWITCH A

SWITCH B

SWITCH C

SWITCH D

CLOCK

SWITCH A

SWITCH B

I

L

3779 F04a

LOW

HIGH

SWITCH C

SWITCH D

(4a) Buck-Boost Region (V_IN≥ V_OUT

)

I

L

CLOCK

3779 F03

SWITCH A

SWITCH B

Figure 3. Buck Region (V_IN>> V_OUT

)

SWITCH C

SWITCH D

I

L

3779 F04b

(4b) Buck-Boost Region (V_IN≤ V_OUT

)

Figure 4. Buck-Boost Region

3779f

16

For more information www.linear.com/LTC3779

LTC3779

operaTion

Boost Region (V << V

)

OUT

Light Load Current Operation (MODE Pin)

IN

Switch A is always on and synchronous switch B is always

off in the boost region. In every cycle, switch C is turned

on first. Inductor current is sensed when synchronous

switch C is turned on. After the sensed inductor peak

current exceeds what the reference voltage demands,

The LTC3779 can be enabled to enter pulse-skipping

mode or forced continuous conduction mode. To select

forced continuous operation, tie the MODE pin to a DC

voltage below 0.8V (e.g., SGND). To select pulse-skipping

mode of operation, tie the MODE pin to V5.

which is proportional to V , switch C is turned off and

ITH

Pulse-Skipping Mode: When the LTC3779 enters pulse-

skipping or discontinuous mode, in the boost region,

synchronous switch D is held off whenever reverse

current through switch A is detected. At very light loads,

the current comparator, I_CMP, may remain tripped for

several cycles and force switch C to stay off for the same

number of cycles (i.e., skipping pulses). In the buck

region, the inductor current is not allowed to reverse.

Synchronous switch B is held off whenever reverse

current on the inductor is detected. At very light loads,

synchronous switch D is turned on for the remainder of

the cycle. Switches C and D will alternate, behaving like a

typical synchronous boost regulator.

The duty cycle of switch C decreases until the minimum

duty cycle of the converter reaches DC

by:

, given

(MIN,BOOST)

⎛

⎜

⎝

⎞

⎟

⎠

1

12

DC_(MIN,BOOST)

=

•100ꢀ = 8.33ꢀ

the current comparator, I

, may remain untripped for

CMP

Figure 5 shows typical boost region waveforms. If V_IN

several cycles, holding switch A off for the same number

of cycles. Synchronous switch B also remains off for the

skipped cycles. In the buck-boost region, the controller

operates alternatively in boost and buck regions in one

clock cycle, as in continuous operation. A small amount

of reverse current is allowed, to minimize ripple. For the

same reason, a narrow band of continuous buck and

boost operation is allowed on the high and low line ends

of the buck-boost region.

approaches V , the buck-boost region is reached.

OUT

CLOCK

HIGH

LOW

SWITCH A

SWITCH B

SWITCH C

SWITCH D

I

Forced Continuous Mode: The forced continuous

mode allows the inductor current to reverse directions

without any switches being forced “off” to prevent this

from happening. At very light load currents the inductor

current will swing positive and negative as the appropriate

average current is delivered to the output. During soft-

L

3779 F05

Figure 5. Boost Region (V_IN<< V_OUT

)

start, if the SS pin is lower than V , the part will be forced

FB

into discontinuous mode to prevent pulling current from

the output to the input. After SS voltage crosses V or

FB

1.32V, whichever is lower, forced continuous mode will

be enabled.

3779f

17

For more information www.linear.com/LTC3779

LTC3779

operaTion

Output Overvoltage

prevents overloading the DC input source, while the

output current limit provides a building block for battery

charger or LED driver applications. It can also serve as

an extra current limit protection for a constant-voltage

regulation application. The input or output current limit

function has an operating voltage range of GND to the

If the output voltage is higher than the value commanded

by the V_FBresistor divider, the LTC3779 will respond

according to the mode and region of operation. In

continuous conduction mode, the LTC3779 will sink

current into the input. If the input supply is capable of

sinking current, the LTC3779 will allow up to about 80mV/

absolute maximum V or V , respectively.

IN

OUT

R

to be sunk into the input. In pulse-skipping mode

SENSE

Frequency Selection and Phase-Locked Loop (FREQ

and PLLIN Pins)

and in the buck or boost regions, switching will stop

and the output will be allowed to remain high. In pulse-

skipping mode, and in the buck-boost region as well as the

narrow band of continuous boost operation that adjoins

it, current sunk into the input through switch A is limited

The selection of switching frequency is a trade-off

between efficiency and component size. Low frequency

operation increases efficiency by reducing MOSFET

switching losses, but requires larger inductance and/or

capacitance to maintain low output ripple voltage. The

switching frequency of the LTC3779’s controllers can be

selected using the FREQ pin. If the SYNC pin is not being

driven by an external clock source, the FREQ pin can be

used to program the controller’s operating frequency

from 50kHz to 600kHz.

to approximately 40mV/ R

of switch A. If this level

DS(ON)

is reached, switching will stop and the output will rise. In

pulse-skipping mode, and in the narrow continuous buck

region that adjoins the buck/ boost region, current sunk

into the input through R

is limited to approximately

SENSE

40mV/R

.

SENSE

Voltage Regulation Loop

Switching frequency is determined by the voltage on

the FREQ pin. Since there is a precision 20µA current

flowing out of the FREQ pin, the user can program the

controller’s switching frequency with a single resistor to

SGND. Figure 9 in the Applications Information section

shows the relationship between the FREQ pin resistor

value and the switching frequency.

The LTC3779 provides a constant-voltage regulation

loop, for regulating the output voltage. A resistor divider

between V , V and GND senses the output voltage.

OUT FB

As with traditional voltage regulators, when V_FBrises near

or above the reference voltage of EA (1.2V typical, see

Block Diagram), the ITH voltage is reduced to command

the amount of current that keeps V

desired voltage.

regulated to the

OUT

A phase-locked loop (PLL) is integrated on the LTC3779

to synchronize the internal oscillator to an external clock

source driving the PLLIN pin. While LTC3779 is being

synchronized to an external clock source, depending on

the voltage of the MODE pin, it can be enabled to enter

pulse-skipping mode or forced continuous conduction

mode. The PLL filter network is integrated inside the

LTC3779.

Constant-Current Regulation (I

and

AVGSNSP

I

Pins)

AVGSNSN

The LTC3779 provides a constant-current regulation

loop for either input or output current. A sensing resistor

close to the input or output capacitor will sense the

input or output current. When the current exceeds the

programmed current limit, the voltage on the ITH pin

will be pulled down to maintain the desired maximum

input or output current. The input current limit function

The PLL is capable of locking to any frequency within the

range of 50kHz to 600kHz. The frequency setting resistor

should always be present to set the controller’s initial

switching frequency before locking to the external clock.

3779f

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LTC3779

operaTion

Power Good (PGOOD) Pins

Thermal Shutdown

The PGOOD pin is connected to the open drain of an

internal N-channel MOSFET. When V_FBis not within 10ꢀ

of the 1.2V reference voltage, the PGOOD pin is pulled

low. The PGOOD pin is also pulled low when RUN is below

1.1V or when the LTC3779 is in the soft-start phase. There

The LTC3779 has a temperature sensor integrated on

the IC, to sense the die temperature near the gate driver

circuits. When the die temperature exceeds 175°C, all

switching actions stop, the top GATE pins are held low,

and the bottom GATE pins are held high, and V_OUTis

is an internal 125µs power good or bad mask when V

disconnected from V . At the same time, the SS pin is

FB

IN

goes in or out of the 10ꢀ window. The PGOOD pin is

allowed to be pulled up by an external resistor to V5 or

an external source of up to 6V.

pulled low by an internal MOSFET. When the temperature

drops 10°C below the trip threshold, the part goes through

a SS reset cycle and normal operation resumes.

Short-Circuit Protection, Current Limit and Current

Limit Foldback

Input Undervoltage and Overvoltage Lockout

The LTC3779 implements a protection feature that

inhibits switching when the input voltage rises above a

programmable operating range. By using a resistor divider

from the input supply to ground, the RUN and VINOV pins

serve as a precise input supply voltage monitor. Switching

is disabled when either the RUN pin falls below 1.1V or the

OVLO pin rises above 1.28V, which can be configured to

limit switching to a specific range of input supply voltage.

The maximum current threshold of the controller is limited

by a voltage clamp on the ITH pin. In every boost cycle,

the sensed maximum peak voltage is limited to 140mV.

In every buck cycle, the sensed maximum valley voltage

is limited to 90mV. In the buck-boost region, only peak

sensed voltage is limited by the same threshold as in the

boost region.

The LTC3779 includes current foldback to help limit load

current when the output is shorted to ground. If the output

falls below 50ꢀ of its nominal output level, then the

maximum sense voltage is progressively lowered from

its maximum value to one-third of the maximum value.

Foldback current limiting is disabled during the soft-start.

Under short-circuit conditions, the LTC3779 will limit the

current by operating as a buck with very low duty cycles,

and by skipping cycles. In this situation, synchronous

switch B will dissipate most of the power (but less than

in normal operation).

When switching is disabled, the LTC3779 can safely

sustain input voltages on the RUN pin up to the absolute

maximum rating of 150V. Input supply undervoltage or

overvoltage events trigger a soft-start reset, which results

in a graceful recovery from an input supply transient.

3779f

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LTC3779

applicaTions inForMaTion

The Typical Application on the first page is a basic LTC3779

application circuit. External component selection is driven

by the load requirement, and begins with the selection of

R

Selection and Maximum Output Current

SENSE

The R

resistance must be chosen properly to achieve

SENSE

the desired amount of output current. Too much resistance

can limit the output current below the application

requirements. Start by determining the maximum allowed

R

and the inductor value. Next, the power MOSFETs

SENSE

are selected. Finally, C_INand C_OUTare selected. This circuit

can be configured for operation up to an input voltage of

150V.

R

resistance in the boost region, R

.

SENSE

Follow this by finding the maximum^SEa^Nll^So^Ew^(Me^Ad^X,R^BO_S^O_EN^ST_S⁾_E

resistance in the buck region, R_{SENSE(MAX,BUCK)}. The

selected R_SENSEresistance must be smaller than both.

Figure 6 shows how I_LOAD(MAX)• R_SENSEvaries with input

and output voltage.

Inductor Current Sensing and Slope Compensation

The LTC3779 operates using inductor current mode

control. The LTC3779 measures the peak of the inductor

current waveform in the boost region and the valley of

the inductor current waveform in the buck region. The

160

150

140

130

120

110

100

90

inductor current is sensed across the R

resistor with

SENSE

pins SENSEP and SENSEN. During any given cycle, the

peak (boost region) or valley (buck region) of the inductor

current is controlled by the ITH pin voltage.

Slope compensation provides stability in constant

frequency architectures by preventing subharmonic

oscillations at high duty cycles in boost operation and at

low duty cycles in buck operation. This is accomplished

internally by adding a compensating ramp to the inductor

current signal at duty cycles in excess of 40ꢀ in the boost

region, or subtracting a ramp from the inductor current

signal at lower than 40ꢀ duty cycles in the buck region.

Normally, this results in a reduction of maximum inductor

peak current for duty cycles >40ꢀ in the boost region,

or an increase of maximum inductor current for duty

cycles <40ꢀ in the buck region. However, the LTC3779

uses a scheme that counteracts this compensating ramp,

which allows the maximum inductor current to remain

unaffected throughout all duty cycles.

0.1

1

10

V

/V

IN OUT

(V)

3779 F06

Figure 6. Load Current vs V_IN/V_OUT

3779f

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LTC3779

applicaTions inForMaTion

Boost Region: In the boost region, the maximum output

Otherwise, if the inductor value is already known then

∆I_L(MAX,BOOST)can be more accurately calculated as

follows:

current capability is the least when V is at its minimum

IN

and V

is at its maximum. Therefore R

must be

chose^On^Ut^To meet the output current requirements under

these conditions.

SENSE

⎛

⎜

⎝

⎞

⎟

⎠

DC_{(MAX,C,BOOST)}

100ꢀ

•V

IN(MIN)

∆I_L(MAX,BOOST)

where:

=

A

Start by finding the boost region duty cycle when V is

IN

f•L

minimum and V

is maximum using:

OUT

⎛

⎞

V

IN(MIN)

⎜

⎟

DC_{(MAX,C,BOOST)}≅ 1–

•100ꢀ

⎜

⎟

DC_{(MAX,C,BOOST)}is the maximum duty cycle percentage

in the boost region as calculated previously.

V_OUT(MAX)

⎝

⎠

For example, an application with a V range of 12V to

f is the switching frequency

IN

48V and V

set to 36V will have:

OUT

L is the inductance of the main inductor

After the maximum ripple current is known, the maximum

⎛

⎞

⎟

⎠

12V

36V

DC_{(MAX,C,BOOST)}≅ 1–

•100ꢀ=67ꢀ

⎜

⎝

allowed R

follows:

in the boost region can be calculated as

SENSE

Next, the inductor ripple current in the boost region must

be determined. If the main inductor L is not known, the

R_{SENSE(MAX,BOOST)}

=

maximum ripple current ∆I

can be estimated

by choosing ∆I_L(MAX,BOOS^L_T⁽₎^Mt^Ao^X,b^BOe^O3^S0^T)ꢀ to 50ꢀ of the

2•V_{RSENSE(MAX,BOOST,MAXDC)}•V

IN(MIN)

Ω

2•I_{OUT(MAX,BOOST)}•V_OUT(MIN)+ ∆I

•V

IN(MIN)

(

) (

)

L(MAX,BOOST)

maximum inductor current in the boost region as follows:

V_OUT(MAX)•I

where V_{RSENSE(MAX,BOOST,MAXDC)}is the maximum

inductor current sense voltage as discussed in the

previous section.

∆I_L(MAX,BOOST)

≅

^{OUT(MAX,BOOST)}A

⎛

⎞

100ꢀ

V

•

–0.5

⎜

⎟

⎠

IN(MIN)

ꢀRipple

⎝

Using values from the previous examples:

where:

2•140mV •12

R_{SENSE(MAX,BOOST)}

=

=18.66mΩ

I

is the maximum output load current

OUT(MAX,BOOST)

required in the boost region

2•2A •36V + 3A •12V

) (

(

)

Buck Region: The duty cycle for buck operation can be

ꢀRipple is 30ꢀ to 50ꢀ

calculated using:

For example, using V_OUT(MAX)= 36V, V_IN(MIN)= 12V,

I_{OUT(MAX,BOOST)}= 2A and ꢀRipple = 40ꢀ we can estimate:

⎛

⎞

⎟

V_OUT(MIN)

⎜

DC_(MAX,B,BUCK)≅ 1−

•100ꢀ

⎜

⎝

⎟

V

36V •2A

⎛

⎜

⎝

IN(MAX)

⎠

∆I_L(MAX,BOOST)

≅

=3A

⎞

⎟

⎠

100ꢀ

40ꢀ

12V •

–0.5

3779f

21

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LTC3779

applicaTions inForMaTion

Before calculating the maximum R_SENSEresistance,

however, the inductor ripple current must be determined.

If the main inductor L is not known, the ripple current

∆I_L(MIN,BUCK)can be estimated by choosing ∆I_L(MIN,BUCK)

to be 10ꢀ of the maximum inductor current in the buck

region as follows:

R

SENSE2

TO

TO DRAIN OF

SWITCH D

SYSTEM

+

R

F

C

F

V

OUT

100Ω

2

1

I

AVGSNSN

AVGSNSP

LTC3779

I

⎛

⎜

⎝

3779 F07

∆I_L(MIN,BUCK)

≅

^{OUT(MAX,BUCK)}A

⎞

⎟

⎠

100ꢀ

10ꢀ

–0.5

Figure 7. Programming Output Current Limit

R

where:

SENSE2

FROM DC

POWER INPUT

TO DRAIN OF

SWITCH A

+

R

F

C

F

I_{OUT(MAX,BUCK)}is the maximum output load current

required in the buck region.

100Ω

2

1

If the inductor value is already known then ∆I

can be calculated as follows:

L(MIN,BUCK)

I

AVGSNSN

AVGSNSP

LTC3779

3779 F08

⎛

⎜

⎝

⎞

⎟

⎠

DC_(MIN,B,BUCK)

100ꢀ

•V

OUT(MIN)

Figure 8. Programming Input Current Limit

∆I_{L MIN,BUCK}

=

A

(

)

f•L

input/output current limit is not desired, the I

and

I

pins should be shorted together to^AV^V5^G.^SNSP

where:

AVGSNSN

With the typical 100Ω resistors shown here, the value

of capacitor C_Fshould be 1µF to 4.7µF. The current

loop’s transfer function should approximate that of the

voltage loop. Crossover frequency should be one-tenth

the switching frequency, and gain should decrease by

20dB/decade. Similar current and voltage loop transfer

functions will ensure overall system stability.

DC

is the minimum duty cycle percentage

(MIN,B,BUCK)

in the buck region as calculated previously.

f is the switching frequency

L is the inductance of the main inductor

After the inductor ripple current is known, the maximum

allowed R

follows:

in the buck region can be calculated as

SENSE

When the I

common mode voltage is above ~4V,

AVGSNS

the I_AVGSNSNpin sources 10µA. The I_AVGSNSPpin, however,

sources 15µA, when a constant current is being regulated.

The error introduced by this mismatch can be offset to a

2•V_{RSENSE(MAX,BUCK,MINDC)}

R_{SENSE(MAX,BUCK)}

=

Ω

2•I

–∆I

L(MIN,BUCK)

(

)

OUT(MAX,BUCK)

first order by scaling the I

and I

resistors

AVGSNSN

accordingly. For example^A,^Vi^Gf^St^Nh^Se^PI

branch has a

Programming Input/Output Current Limit

AVGSNSP

100Ω resistor, the 1.50mV across it can be replicated in

the I branch by using a 150Ω resistor.

As shown in Figure 7 and Figure 8, input/output current

AVGSNSN

sense resistor R

should be placed between the bulk

capacitor for V ^SEo^Nr^SEV²

and the decoupling capacitor.

When the I_AVGSNScommon mode voltage falls below

~4V, the I current decreases linearly; it reaches

IN

OUT

A lowpass filter formed by R and C is recommended to

AVGSNS

F

approximately –300µA at zero volts. The maximum

current sinking can vary by 20ꢀ to 30ꢀ due to process

reduce the switching noise and stabilize the current loop.

The input/output current limit is set internally to 50mV. If

3779f

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For more information www.linear.com/LTC3779

LTC3779

applicaTions inForMaTion

250

200

150

100

50

variation. Ensure that I_AVGSNScommon mode voltage

never exceeds its absolute maximum of –10V below

ground. Pay special attention to short-circuit conditions

in high power applications.

Phase-Locked Loop and Frequency Synchronization

The LTC3779 has a phase-locked loop (PLL) comprised of

an internal voltage-controlled oscillator (VCO) and a phase

detector. This allows the turn-on of the bottom MOSFET of

the controller to be locked to the rising edge of an external

clock signal applied to the PLLIN pin. The phase detector

is an edge sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit false locking

to harmonics of the external clock.

0

100 200 300 400 500 600 700 800

FREQUENCY (kHz)

3779 F09

Figure 9. FREQ Pin Resistor Value vs Frequency

5.5V 5.5V

R

SET

20µA

The output of the phase detector is a pair of complementary

current sources that charge or discharge the internal filter

network. There is a precision 20µA of current flowing out

of the FREQ pin. This allows a single resistor to SGND

to set the switching frequency when no external clock

is applied to the PLLIN pin. The internal switch between

FREQ and the integrated PLL filter network is on, allowing

the filter network to be pre-charged at the same voltage as

the FREQ pin. The relationship between the voltage on the

FREQ pin and operating frequency is shown in Figure 9

and specified in the Electrical Characteristics table. If an

external clock is detected on the PLLIN pin, the internal

switch previously mentioned will turn off and isolate the

influence of the FREQ pin.

FREQ

MODE/

PLLIN

DIGITAL

PHASE/

FREQUENCY

DETECTOR

SYNC

EXTERNAL

OSCILLATOR

VCO

3779 F10

Figure 10. Phase-Locked Loop Block Diagram

are the same but exhibit a phase difference, the current

sources turn on for the amount of time corresponding to

the phase difference. The voltage on the filter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the filter capacitor holds the voltage.

Note that the LTC3779 can only be synchronized to an

external clock whose frequency is within range of the

LTC3779’s internal VCO. This is guaranteed to be between

50kHz and 600kHz. A simplified block diagram is shown

in Figure 10.

Typically, the external clock (on the PLLIN pin) input high

threshold is 2V, while the input low threshold is 1.2V.

If the external clock frequency is greater than the internal

oscillator’s frequency, f_OSC, then current is sourced

continuously from the phase detector output, pulling up

the filter network. When the external clock frequency is

less than f_OSC, current is sunk continuously, pulling down

the filter network. If the external and internal frequencies

The operating frequency of the LTC3779 can be

approximated using the following formula:

2

R

FREQ

= 0.000115(f ) + 0.174 (f ) + 18.5

OSC

where f

is in kHz and R

is in kΩ.

OSC

FREQ

3779f

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LTC3779

applicaTions inForMaTion

Inductor Selection

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can

concentrate on copper loss and preventing saturation.

Ferrite core material saturates “hard,” which means that

inductance collapses abruptly when the peak design

current is exceeded. This results in an abrupt increase

in inductor ripple current and consequent output voltage

ripple. Do not allow the core to saturate!

The operating frequency and inductor selection are

interrelated in that higher operating frequencies allow the

use of smaller inductor and capacitor values. The inductor

value has a direct effect on ripple current. The inductor

current ripple ∆I is typically set to 20ꢀ to 40ꢀ of the

L

maximum inductor current in the boost region at V_IN(MIN)

.

For a given ripple the inductance terms in continuous

mode are as follows:

C and C

Selection

IN

OUT

V

²• V − V

•100

IN(MIN)

(

)

In the boost region, input current is continuous. In the

buck region, input current is discontinuous. In the buck

IN(MIN)

OUT

L_BOOST

>

H,

2

f •I_OUT(MAX)• ꢀRipple • V_OUT

region, the selection of input capacitor C is driven by

IN

V_OUT• V_IN(MAX)− V

•100

the need to filter the input square wave current. Use a low

ESR capacitor sized to handle the maximum RMS current.

For buck operation, the input RMS current is given by:

(

)

OUT

L_BUCK

>

H

f •I_OUT(MAX)• ꢀRipple • V

IN(MAX)

where:

f is operating frequency, Hz

ꢀ Ripple is allowable inductor current ripple

V_OUT

V

IN

V_OUT

I_RMS≈ I_OUT(MAX)

•

−1

V

IN

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT(MAX)/2. This simple worst-case condition

is commonly used for design because even significant

deviations do not offer much relief. Note that ripple

current ratings from capacitor manufacturers are often

based on only 2000 hours of life which makes it advisable

to derate the capacitor.

V

is minimum input voltage, V

is maximum input voltage, V

is output voltage, V

IN(MIN)

IN(MAX)

OUT

I

is maximum output load current, A

OUT(MAX)

For high efficiency, choose an inductor with low core loss,

such as ferrite. Also, the inductor should have low DC

2

In the boost region, the discontinuous current shifts

from the input to the output, so C_OUTmust be capable

of reducing the output voltage ripple. The effects of ESR

(equivalent series resistance) and the bulk capacitance

must be considered when choosing the right capacitor

for a given output ripple voltage. The steady ripple due to

charging and discharging the bulk capacitance is given by:

resistance to reduce the I R losses, and must be able to

handle the peak inductor current without saturating. To

minimize radiated noise, use a toroid, pot core or shielded

bobbin inductor.

Inductor Core Selection

Once the inductance value is determined, the type of

inductor must be selected. Core loss is independent of

core size for a fixed inductor value, but it is very dependent

on inductance selected. As inductance increases, core

losses go down. Unfortunately, increased inductance

requires more turns of wire and therefore copper losses

will increase.

I_OUT(MAX)• V − V

(

)

V

IN(MIN)

OUT

∆V_{RIPPLE(BOOST,CAP)}

=

C_OUT• V_OUT• f

where C

is the output filter capacitor.

OUT

The steady ripple due to the voltage drop across the ESR

is given by:

∆V

= I

• ESR

OUT(MAX,BOOST)

(BOOST,ESR)

3779f

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LTC3779

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In buck mode, V

ripple is given by:

In order to select the power MOSFETs, the power

dissipated by the device must be known. For switch A,

the maximum power dissipation happens in the boost

region, when it remains on all the time. Its maximum

power dissipation at maximum output current is given by:

OUT

⎛

⎞

⎟

⎠

1

∆V_OUT≤ ∆I ESR+

⎜

⎝

L

8 • f •C_OUT

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Aluminum electrolytic and ceramic capacitors are

available in surface mount packages. Ceramic capacitors

have excellent low ESR characteristics but can have a high

voltage coefficient. Bulk capacitors are now available with

low ESR and high ripple current ratings, such as OSCON

and aluminum electrolytics with hybrid conductive

polymers.

2

⎛

⎜

⎝

⎞

V_OUT

P_A,BOOST

=

•I_OUT(MAX)•ρ_t•R

⎟

DS(ON)

V

⎠

IN

where ρ is a normalization factor (unity at 25°C)

t

accounting for the significant variation in on-resistance

with temperature, typically about 0.4ꢀ/°C, as shown in

Figure 11. For a maximum junction temperature of 125°C,

using a value ρ = 1.5 is reasonable.

t

2.0

1.5

1.0

0.5

0

Power MOSFET Selection and Efficiency

Considerations

The LTC3779 requires four external N-channel power

MOSFETs, two for the top switches (switches A and

D, shown in Figure 1) and two for the bottom switches

(switches B and C, shown in Figure 1). Important

parameters for the power MOSFETs are the breakdown

voltage V

DS(ON)

, threshold voltage V

, on-resistance

RSS

BR,DSS

GS,TH

R

, reverse transfer capacitance C

and maximum

current I

.

DS(MAX)

50

100

–50

150

0

JUNCTION TEMPERATURE (°C)

The peak-to-peak drive levels are set by the DRV_CC

voltage. This voltage can range from 6V to 10V depending

on the DRVSET pin setting. Therefore, both logic-level

and standard-level threshold MOSFETs can be used in

most applications, depending on the programmed DRV_CC

voltage. Pay close attention to the BV_DSSspecification for

the MOSFETs as well.

3779 F11

Figure 11. Normalized R_DS(ON)vs Temperature

The LTC3779’s ability to adjust the gate drive level

between 6V to 10V allows an application circuit to be

precisely optimized for efficiency. When adjusting the gate

drive level, the final arbiter is the total input current for

the regulator. If a change is made and the input current

decreases, then the efficiency has improved. If there is

no change in input current, then there is no change in

efficiency.

3779f

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Switch B operates in the buck region as the synchronous

rectifier. Its power dissipation at maximum output current

is given by:

Schottky Diode (D1, D2) Selection

The Schottky diodes, D1 and D2, shown in the Block

Diagram, conduct during the dead time between the

conduction of the power MOSFET switches. They are

intended to prevent the body diode of synchronous

switches B and D from turning on and storing charge

during the dead time. In particular, D2 significantly

reduces reverse recovery current between switch D

turn-off and switch C turn-on, which improves converter

efficiency and reduces switch C voltage stress. In order

for the diode to be effective, the inductance between it

and the synchronous switch must be as small as possible,

mandating that these components be placed adjacently.

V − V

IN

OUT

P_B,BUCK

=

•I_OUT(MAX)²•ρ_t•R_DS(ON)

V

IN

Switch C operates in the boost region as the control

switch. Its power dissipation at maximum current is given

by:

V

− V V

(

)

IN

2

OUT

P_C,BOOST

=

•I_OUT(MAX)²•ρ_t

V

IN

I_OUT(MAX)

3

•R_DS(ON)+k • V_OUT

•

•C_RSS• f

V

IN

Setting Output Voltage

The LTC3779 output voltage is set by two external

feedback resistive dividers carefully placed across the

output, as shown in Figure 12. The regulated output

voltage is determined by:

where C_RSSis usually specified by the MOSFET

manufacturers. The constant k, which accounts for the

loss caused by reverse recovery current, is inversely

proportional to the gate drive current and has an empirical

value of 1.7.

V

OUT

= 1.2V • (1 + R /R )

B A

For switch D, the maximum power dissipation happens

in the boost region, when its duty cycle is higher than

50ꢀ. Its maximum power dissipation at maximum output

current is given by:

To improve the frequency response, a feed forward

capacitor, C , may be used. Great care should be taken

FF

to route the V line away from noise sources, such as

FB

the inductor or the SW line.

2

⎛

⎜

⎝

⎞

V

V_OUT

IN

V

OUT

P_D,BOOST

=

•

•I_OUT(MAX)•ρ_t•R

⎟

DS(ON)

V

⎠

IN

R

B

C

FF

LTC3779

V

For the same output voltage and current, switch A has the

highest power dissipation and switch B has the lowest

power dissipation unless a short occurs at the output.

FB

R

A

3779 F12

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

Figure 12. Setting Output Voltage

T = T + P • R

J

A

TH(JA)

The R

to be used in the equation normally includes

TH(JA)

the R

for the device plus the thermal resistance from

TH(JC)

the case to the ambient temperature (R

). This value

TH(JC)

of T can then be compared to the original, assumed value

J

used in the iterative calculation process.

3779f

26

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LTC3779

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RUN Pin and Overvoltage/Undervoltage Lockout

The RUN and VINOV pins can alternatively be configured

as undervoltage (UVLO) and overvoltage (OVLO) lockouts

on the V_INsupply with a resistor divider from V_INto

ground. A simple resistor divider can be used as shown

The LTC3779 is enabled using the RUN pin. It has a rising

threshold of 1.2V with 100mV of hysteresis. Pulling the

RUN pin below 1.1V shuts down the main control loop

for the controller and most internal circuits, including the

DRV_CCand V5 LDOs. In this state the LTC3779 draws only

40μA of quiescent current. Releasing the RUN pin allows

an internal 2.5µA current to pull-up the pin and enable the

controller. The RUN comparator itself has about 100mV

of hysteresis. When the voltage on the RUN pin exceeds

1.2V, the current sourced into the RUN pin is switched

from 2.5µA to 6.5µA current. The user can therefore

program both the rising threshold and the amount of

hysteresis using an external resistive divider.

in Figure 14 to meet specific V voltage requirements.

IN

One can program additional hysteresis for the RUN

comparator by adjusting the values of the resistive divider.

The current that flows through the R3-R4-R5 divider

will directly add to the shutdown and active current of

the LTC3779, and care should be taken to minimize

the impact of this current on the overall efficiency of

the application circuit. Resistor values in the megohm

range may be required to keep the impact on quiescent

shutdown current low. To pick resistor values, the sum

total of R3 + R4 + R5 (R

) should be chosen first

TOTAL

The RUN pin is high impedance above 3V and must be

externally pulled up/down or driven directly by logic, as

shown in Figure 13. The RUN pin can tolerate up to 150V

(absolute maximum), so it can be conveniently tied to V_IN

in always-on applications where the controller is enabled

continuously and never shut down.

based on the allowable DC current that can be drawn from

V .

IN

The individual values of R3, R4 and R5 can then be

calculated from the following equations:

⎛

⎜

⎝

⎞

⎟

⎠

1.2V

R5 =R_TOTAL

R4 =R_TOTAL

•

Rising V OVLO Threshold

IN

V

IN

SUPPLY

⎛

⎜

⎝

⎞

⎟

⎠

1.2V

4.7M

LTC3779

RUN

LTC3779

RUN

−R5

Rising V UVLO Threshold

IN

R3 =R_TOTAL−R4−R5

3779 F13

For applications that do not need a precise external OVLO,

the VINOV pin should be tied directly to ground. The RUN

pin in this type of application can be used as an external

UVLO using the following equations with R5 = 0Ω.

Figure 13. RUN Pin Interface to Logic

V

IN

R3

⎛

⎞

⎟

⎠

R3

R4

V

= 1.2V 1+

−2.5µ•R3

⎜

IN(ON)

RUN

⎝

⎛

LTC3779

VINOV

R4

R5

⎞

R3

R4

V

= 1.1V 1+

−6.5µ•R3

⎟

⎜

IN(OFF)

3779 F14

⎝

⎠

Figure 14. Adjustable UV and OV Lockout

3779f

27

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LTC3779

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Similarly, for applications that do not require a precise

N-channel MOSFET acting as a linear regulator with its

UVLO, the RUN pin can be tied to V_IN. In this configuration,

drain connected to V .

IN

the UVLO threshold is limited to the internal V UVLO

IN

The NDRV LDO provides an alternative method to

supply power to DRVCC from the input supply without

dissipating the power inside the LTC3779 IC. It has an

internal charge pump that allows NDRV to be driven above

thresholds as shown in the Electrical Characteristics table.

The resistor values for the OVLO can be computed using

the previous equations with R3 = 0Ω.

Be aware that the OVLO pin cannot be allowed to exceed

its absolute maximum rating of 6V. To keep the voltage

on the OVLO pin from exceeding 6V, the following relation

should be satisfied:

the V supply, allowing for low dropout performance.

IN

The V LDO has a slightly lower regulation point than the

IN

NDRV LDO, such that all DRV current flows through the

CC

external N-channel MOSFET (and not through the internal

P-channel pass device) once DRV reaches regulation.

CC

⎛

⎜

⎝

⎞

⎟

⎠

R5

V

•

< 6V

IN(MAX)

When laying out the PC board, care should be taken to

route NDRV away from any switching nodes, especially

SW, TG, and BOOST. Coupling to the NDRV node could

cause its voltage to collapse and the NDRV LDO to lose

regulation. If this occurs, the internal V_INLDO would

R3+R4+R5

Soft-Start

The start-up of V

is controlled by the voltage on the SS

OUT

pin. If its RUN pin voltage is below 1.1V the controller is in

the shutdown state; its SS pin is actively pulled to ground

in this shutdown state. If the RUN pin voltage is above

1.2V, the controller powers up. A soft-start current of

5μA then starts to charge the SS soft-start capacitor. Note

that soft-start is achieved not by limiting the maximum

output current of the controller but by controlling the

output ramp voltage according to the ramp rate on the

SS pin. When the voltage on the SS pin is less than the

take over and maintain DRV voltage at a slightly lower

CC

regulation point. However, internal heating of the IC would

become a concern. High frequency noise on the drain of

the external NFET could also couple into the NDRV node

(through the gate-to-drain capacitance of the NDRV NFET)

and adversely affect NDRV regulation. The following are

methods that could mitigate this potential issue (refer to

Figure 15).

1. Add local decoupling capacitors right next to the drain

of the external NDRV NFET in the PCB layout.

internal 1.2V reference, the LTC3779 regulates the V pin

FB

voltage to the voltage on the SS pin instead of the internal

reference. Current foldback is disabled during this phase.

The soft-start range is defined to be the voltage range

from 0V to 1.2V on the SS pin. The total soft-start time

can be calculated as:

2. Insert a resistor (~100Ω) in series with the gate of the

NDRV NFET.

3. Insert a small capacitor (~1nF) between the gate and

source of the NDRV NFET.

⎛

⎞

1.2V

5µA

When testing the application circuit, be sure the NDRV

voltage does not collapse over the entire input voltage

and output current operating range of the buck-boost

regulator. If the NDRV LDO is not being used, connect

t

_SS= C_SS•

⎜

⎟

⎝

⎠

DRV Regulator

CC

the NDRV pin to DRV (Figure 15b).

CC

The LTC3779 features three separate low dropout linear

regulators (LDO) that can supply power at the DRVCC

pin. The internal V LDO uses an internal P-channel pass

device between the V_INand DRV_CCpins. The internal

EXTV_CCLDO uses an internal P-channel pass device

between the EXTV_CCand DRV_CCpins. The NDRV LDO

utilizes the NDRV pin to drive the gate of an external

The DRV_CCsupply is regulated between 6V to 10V,

depending on the DRVSET pin setting. The internal V_IN

IN

and EXTV LDOs can supply a peak current of at least

CC

50mA. The DRV pin must be bypassed to ground with

CC

a minimum of 4.7μF ceramic capacitor. Good bypassing is

needed to supply the high transient currents required by

3779f

28

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V

IN

LDO, NDRV LDO or the EXTV LDO. When the voltage on

the EXTV pin is less than ^Cit^Cs switchover threshold (as

V

IN

CC

LTC3779

NDRV

R1*

determined by the DRVSET pin), the V and NDRV LDOs

IN

C2*

are enabled. Power dissipation in this case is highest and

C1*

is equal to V • I

. If the NDRV LDO is not being

IN

used, this power ^Dis^RVd^Ci^Cssipated inside the IC. The gate

charge current is dependent on operating frequency as

discussed in the Efficiency Considerations section.

DRV

CC

GND

*R1, C1 AND C2 ARE OPTIONAL

3779 F15a

The junction temperature can be estimated by using the

equations given in Note 2 of the Electrical Characteristics

table. For example, if DRV_CCis set to 6V, the DRV_CC

current is limited to less than 49mA from a 40V supply

Figure 15a. Configuring the NDRV LDO

Figure 15.

V

IN

V

IN

when not using the EXTV or NDRV LDO’s at a 70°C

CC

NDRV

LTC3779

ambient temperature:

T = 70°C + (49mA)(40V)(28°C/W) = 125°C

J

DRV

CC

To prevent the maximum junction temperature from being

GND

exceeded, the V supply current must be checked while

IN

3779 F15b

operating in forced continuous mode (MODE = SGND) at

maximum V .

Figure 15b. Disabling the NDRV LDO

IN

When the voltage applied to EXTV_CCrises above its

the MOSFET gate drivers. The DRVSET pin programs the

switchover threshold, the V and NDRV LDOs are turned

IN

DRV supply voltage and selects the appropriate DRV

CC

off and the EXTV_CCLDO is enabled. The EXTV_CCLDO

remains on as long as the voltage applied to EXTV_CC

remains above the switchover threshold minus the

comparator hysteresis. The EXTV_CCLDO attempts to

regulate the DRV_CCvoltage to the voltage as programmed

by the DRVSET pin, so while EXTV_CCis less than this

UVLO and EXTV_CCswitchover threshold voltages as

shown in the Electrical Characteristics table. The DRVSET

pin has five logic level states. When DRVSET is either

grounded, floated or tied to V5, the typical value for the

DRV voltage will be 6V, 8V and 10V respectively. Use

CC

the 10V setting with careful PCB layout. This is because

any overshoot between BOOST and SW would exceed

the absolute maximum voltage of 11V for the floating

driver. Set DRVSET to one-fourth of V5 and three-fourths

voltage, the LDO is in dropout and the DRV voltage is

CC

approximately equal to EXTV . When EXTV is greater

CC

than the programmed voltage, up to an absolute maximum

of 36V, DRV is regulated to the programmed voltage.

CC

of V5 for 7V and 9V DRV voltages. Please note that the

CC

DRVSET pin has an internal 200k pull-down to SGND and

Using the EXTV_CCLDO allows the MOSFET driver and

control power to be derived from the LTC3779’s switching

regulator output (5.7V ≤ V_OUT≤ 36V) during normal

operation and from the V_INor NDRV LDO when the output

is out of regulation (e.g., start-up, short-circuit).

a 200k pull-up to V5. The EXTV turn on threshold is

CC

the selected DRV_CCregulation voltage minus 500mV. The

turn off threshold is 500mV below the turn on threshold.

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the

maximum junction temperature rating for the LTC3779

Significant efficiency and thermal gains can be realized by

powering DRV from the output, since the V current

resulting from^CCthe driver and control curren^It^Ns will be

scaled by a factor of (Duty Cycle)/(Switcher Efficiency).

to be exceeded. The DRV current, which is dominated

CC

by the gate charge current, may be supplied by the V

IN

3779f

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For 5.5V to 36V regulator outputs, this means connecting

4. EXTV connected to the regulator output through an

CC

the EXTV pin directly to V . Tying the EXTV pin

external Zener diode. If the output voltage is greater

than 36V, a Zener diode can be used to drop the

necessary voltage between V_OUTand EXTV_CCsuch

CC

OUT

CC

to a 12V supply reduces the junction temperature in the

previous example from 125°C to:

that EXTV remains below 36V (Figure 16). In this

CC

T = 70°C+49mA •(12V) 28°C/W = 86°C

(

)

J

configuration, a bypass capacitor on EXTV_CCof at

least 0.1μF is recommended. An optional resistor

While using the EXTV LDO there is an V under voltage

detection circuit that^Cd^Cisables the EXTV ^INLDO if the V

between EXTV and GND can be inserted to ensure

CC

IN

adequate bias current through the Zener diode.

voltage is less that the DRV voltage that is set by the

CC

DRVSET pin.

V

OUT

> 36V

For applications where the minimum V_INvoltage of

LTC3779

EXTV

LTC3779 needs to be less than 4.5V, the EXTV pin can

CC

EXTV < 36V

CC

be used to power the V_INof LTC3779. The V_INunder

0.1µF

voltage detection circuit is disabled when DRVSET is set

GND

to three-fourths of V5, for 9V DRV voltage. Under this

CC

3779 F16

condition the DRV voltage can be higher than the V

CC

IN

of LTC3779 and an external blocking diode should be

Figure 16. Using a Zener Diode Between V_OUTand EXTV_CC

connected from the V pin of LTC3779 to the external

IN

V supply, to avoid back feeding the V supply.

IN

V5 Regulator

The following list summarizes the four possible

An additional P-channel LDO supplies power at the V5

pin from the DRV_CCpin. Whereas DRV_CCpowers the

gate drivers, V5 powers much of the LTC3779’s internal

circuitry. The V5 LDO regulates the voltage at the V5 pin

connections for EXTV :

CC

1. EXTV_CCgrounded. This will cause DRV_CCto be

powered from the internal V or NDRV LDO resulting

IN

in an efficiency penalty of up to 10ꢀ at high input

to 5.5V when DRV is at least 6V. The LDO can supply

CC

voltages.

a peak current of 20mA and must be bypassed to ground

with a minimum of 4.7μF ceramic capacitor or low

ESR electrolytic capacitor. No matter what type of bulk

capacitor is used, an additional 0.1μF ceramic capacitor

placed directly adjacent to the V5 and SGND pins is highly

recommended. V5 is also used as a pull-up to bias other

pins, such as MODE, DRVSET and SS.

2. EXTV_CCconnected directly to the regulator output.

This is the normal connection for a 5.5V to 36V

regulator and provides the highest efficiency.

3. EXTV_CCconnected to an external supply. If an external

supply is available in the 5.5V to 36V range, it may be

used to power EXTV providing it is compatible with

the MOSFET gate dr^Civ^Ce requirements.

3779f

30

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Pre-Biased Output Start-Up

In the buck region, maximum sense voltage and the sense

resistance determine the maximum allowed inductor

valley current, which is:

There may be situations that require the power supply to

start up with a pre-bias on the output capacitors. In this

case, it is desirable to start up without discharging that

output pre-bias. The LTC3779 can safely power up into a

pre-biased output without discharging it.

90mV

I_L(MAX,BUCK)

=

R_SENSE

To further limit current in the event of a short circuit to

ground, the LTC3779 includes foldback current limiting.

If the output falls by more than 50ꢀ, then the maximum

sense voltage is progressively lowered to about one-third

of its full value.

If the voltage on the SS pin is lower than V , to prevent

FB

pulling current from the output to the input, the LTC3779

forces the part into discontinuous mode of operation

irrespective of the status of the MODE pin. If V_FBis

>1.12V, or when the SS voltage crosses V or 1.32V,

FB

whichever event happens first, then the MODE pin setting

determines the mode of operation.

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100ꢀ.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

Topside MOSFET Driver Supply

In the Block Diagram, the external bootstrap capacitors

C and C , connected to the BOOST1 and BOOST2 pins,

A

B

supply the gate drive voltage for the topside MOSFET

switches A and D. When the top switch A turns on, the

switch node SW1 rises to V and the BOOST1 pin rises

ꢀ Efficiency = 100ꢀ – (L1 + L2 + L3 + ...)

IN

to approximately V + DRV . When the bottom switch

IN

CC

where L1, L2, etc. a e the individual losses as a percentage

of input power.

B turns on, the switch node SW1 is low and the boost

capacitor C is charged through D from DRV . When

A

CC

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

the top switch D turns on, the switch node SW2 rises to

V

and the BOOST2 pin rises to approximately V

CC

+

OUT

losses in LTC3779 circuits: 1) IC V current, 2) MOSFET

DRV . When the bottom switch C turns on, switch node

IN

driver current, 3) I²R losses, 4) topside MOSFET transition

losses.

SW2 is low and the boost capacitor C_Bis charged through

D from DRV . The boost capacitors C and C need to

B

CC

A

B

store about 100 times the gate charge required by the top

switches A and D. In most applications, a 0.1µF to 0.47µF,

X5R or X7R dielectric capacitor is adequate.

1. The V current is the DC supply current given in the

IN

Electrical Characteristics table. V_INcurrent typically

results in a small (<0.1ꢀ) loss.

2. The MOSFET driver current results from switching the

gate capacitance of the power MOSFETs. Each time

a MOSFET gate is switched from low to high to low

again, a packet of charge dQ moves from the driver

supply to ground. The resulting dQ/dt is a current

out of the driver supply that is typically much larger

than the control circuit current. In continuous mode,

Fault Conditions: Current Limit and Current Foldback

The maximum inductor current is inherently limited in a

current mode controller by the maximum sense voltage. In

the boost region, maximum sense voltage and the sense

resistance determine the maximum allowed inductor peak

current, which is:

140mV

R_SENSE

I

= f(Q + Q ), where Q and Q are the gate

GATECHG

T B T B

I_L(MAX,BOOST)

=

charges of the topside and bottom side MOSFETs.

3779f

31

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3. I R losses are predicted from the DC resistances of

2

Checking Transient Response

the fuse (if used), MOSFET, inductor and current sense

resistor. In continuous mode, the average output

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

current flows through L and R

, but is chopped

SENSE

between the topside MOSFET and the synchronous

MOSFET. If the two MOSFETs have approximately the

load current. When a load step occurs, V

shifts by an

OUT

amount equal to ∆I

• ESR, where ESR is the effective

LOAD

same R

, then the resistance of one MOSFET

DS(ON)

series resistance of C_OUT. ∆I_LOADalso begins to charge or

discharge C generating the feedback error signal that

can simply be summed with the resistances of L and

OUT

R_SENSEto obtain I²R losses. For example, if each

forces the regulator to adapt to the current change and

R

DS(ON)

= 10mΩ, R = 10mΩ, R

= 5mΩ, then

SENSE

L

return V to its steady-state value. During this recovery

OUT

the total resistance is 25mΩ. This results in losses

ranging from 0.6ꢀ to 2ꢀ as the output current

increases from 3A to 15A for a 12V output.

time V

can be monitored for excessive overshoot or

OUT

ringing, which would indicate a stability problem. The

availability of the ITH pin not only allows optimization of

control loop behavior but also provides a DC-coupled and

AC-filtered closed-loop response test point. The DC step,

rise time and settling at this test point truly reflects the

closed-loop response. Assuming a predominantly second

order system, phase margin and/or damping factor can be

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining

the rise time at the pin.

Efficiency varies as the inverse square of V

for

the same external components and output^Op^Uo^Twer

level. The combined effects of increasingly lower

output voltages and higher currents required by

high performance digital systems is not doubling

but quadrupling the importance of loss terms in the

switching regulator system!

4. Transition losses apply only to the topside MOSFET(s),

and become significant only when operating at high

input voltages (typically 15V or greater). Transition

losses can be estimated from:

The ITH external components shown in the Typical

Application circuit will provide an adequate starting point

for most applications. The ITH series R -C filter sets the

C

dominant pole-zero loop compensatio^Cn. The values can

be modified slightly (from 0.5 to 2 times their suggested

values) to optimize transient response once the final PC

layout is done and the particular output capacitor type

and value have been determined. The output capacitors

need to be selected because the various types and values

determine the loop gain and phase. An output current

pulse of 20ꢀ to 80ꢀ of full-load current having a rise

time of 1μs to 10μs will produce output voltage and ITH

pin waveforms that will give a sense of the overall loop

stability without breaking the feedback loop.

2

Transition Loss = (1.7) V • I

• C

• f

IN

O(MAX)

RSS

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5ꢀ to

10ꢀ efficiency degradation in portable systems. It is very

important to include these system level losses during the

design phase. The internal battery and fuse resistance

losses can be minimized by making sure that C_INhas

adequate charge storage and very low ESR at the switching

frequency. A 25W supply will typically require a minimum of

20μF to 40μF of capacitance having a maximum of 20mΩ to

50mΩ of ESR. Other losses including Schottky conduction

losses during dead time and inductor core losses generally

account for less than 2ꢀ total additional loss.

3779f

32

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Placing a power MOSFET directly across the output

capacitor and driving the gate with an appropriate signal

generator is a practical way to produce a realistic load

step condition. The initial output voltage step resulting

from the step change in output current may not be within

the bandwidth of the feedback loop, so this signal cannot

be used to determine phase margin. This is why it is better

to look at the ITH pin signal which is in the feedback

loop and is the filtered and compensated control loop

response.

(–) terminals. The path formed by the top N-channel

MOSFET, bottom N-channel MOSFET and the C_IN

capacitor should have short leads and PC trace

lengths. The output capacitor (–) terminals should

be connected as close as possible to the (–) terminals

of the input capacitor by placing the capacitors next

to each other.

2. Does the LTC3779 V pin’s resistive divider connect

FB

to the (+) terminal of C_OUT? The resistive divider must

be connected between the (+) terminal of C

and

OUT

The gain of the loop will be increased by increasing

signal ground. The feedback resistor connections

should not be along the high current input feeds from

the input capacitor(s).

R and the bandwidth of the loop will be increased by

C

decreasing C_C. If R_Cis increased by the same factor

that C is decreased, the zero frequency will be kept the

same,^Cthereby keeping the phase shift the same in the

most critical frequency range of the feedback loop. The

output voltage settling behavior is related to the stability

of the closed-loop system and will demonstrate the actual

overall supply performance.

3. Are the SENSEN and SENSEP leads routed together

with minimum PC trace spacing? The filter capacitor

+

–

between SENSE and SENSE should be as close as

possible to the IC. Ensure accurate current sensing

with Kelvin connections at the SENSE resistor.

4. Is the DRV_CCand decoupling capacitor connected

close to the IC, between the DRV and the ground

pin? This capacitor carries the^CM^COSFET drivers’

current peaks.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with C_OUT, causing a rapid drop in V_OUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

5. Keep the SW, TG, and BOOST nodes away from

sensitive small-signal nodes. All of these nodes have

very large and fast moving signals and therefore

should be kept on the output side of the LTC3779

and occupy minimum PC trace area.

C

to C

is greater than 1:50, the switch rise time

LOAD

OUT

should be controlled so that the load rise time is limited

to approximately 25 • C

. Thus a 10μF capacitor would

require a 250μs rise ti^Lm^Oe^A,^Dlimiting the charging current

to about 200mA.

6. The path formed by switch A, switch B, D1 and the

C

capacitor should have short leads and PC trace

IN

lengths. The path formed by switch C, switch D, D2

and the C

and PC trace lengths.

capacitor also should have short leads

OUT

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC.

7. Use a modified star ground technique: a low

impedance, large copper area central grounding

point on the same side of the PC board as the input

and output capacitors with tie-ins for the bottom of

1. Are the signal and power grounds kept separate?

The combined IC signal ground pin and the ground

the DRV decoupling capacitor, the bottom of the

CC

return of C

must return to the combined C

voltage feedback resistive divider and the GND pin of

the IC.

DRVCC

OUT

3779f

33

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Design Example

The R

resistor value can be calculated by using the

SENSE

maximum current sense voltage specification with some

accommodation for tolerances.

V = 6V to 100V

IN

V

OUT

= 12V

2 •140mV • V_IN(MIN)

R_SENSE

=

I

= 5A

OUT(MAX)

2 •I_{OUT(MAX,BOOST)}• V_OUT+∆I_L,BOOST• V_IN(MIN)

= 13.3mΩ

f = 200kHz

Maximum ambient temperature = 60°C

Adding an additional 30ꢀ margin, choose R

13.3mΩ/1.3 = 10mΩ.

to be

SENSE

Set the frequency at 200kHz by applying 1.11V on the

FREQ pin (see Figure 9). The 20µA current flowing out

of the FREQ pin will give 1.11V across a 55.6k resistor

to GND. The inductance value is chosen first based on a

30ꢀ ripple current assumption. In the buck region, the

ripple current is:

Output voltage is 12V. Select R as 12.1k. R is:

A

B

V_OUT•R_A

R_B=

–R_A

1.2

Select R_Bas 110k. Both R_Aand R_Bshould have a tolerance

of no more than 1ꢀ.

⎛

⎞

⎟

⎠

V_OUT

f •L

V_OUT

∆I_L,BUCK

=

• 1–

⎜

V

⎝

IN

Selecting MOSFET Switches

∆I_L,BUCK•100

I_RIPPLE,BUCK

=

ꢀ

The MOSFETs are selected based on voltage rating and

R_DS(ON)value. It is important to ensure that the part is

specified for operation with the available gate voltage

amplitude. In this case, the amplitude is 10V and MOSFETs

with an R_DS(ON)value specified at V_GS= 4.5V can be used.

I_OUT

The highest value of ripple current occurs at the maximum

input voltage. In the boost region, the ripple current is:

⎛

⎞

⎟

⎠

V

IN

V_OUT

IN

f •L

Select QA and QB. With 100V maximum input voltage

MOSFETs with a rating of at least 150V are used. As we do

not yet know the actual thermal resistance (circuit board

design and airflow have a major impact) we assume that

the MOSFET thermal resistance from junction to ambient

is 50°C/W.

∆I_L,BOOST

=

• 1–

⎜

⎝

∆I_L,BOOST• 100

I_RIPPLE,BOOST

=

ꢀ

I_IN

The highest value of ripple current occurs at V = V /2.

IN

OUT

If we design for a maximum junction temperature, T_J(MAX)

= 125°C, the maximum R

value can be calculated.

A 15µH inductor will produce 10ꢀ ripple in the boost

DS(ON)

First, calculate the maximum power dissipation:

region (V = 6V) and 70ꢀ ripple in the buck region (V

IN

= 100V).

⎛

⎞

T

_J(MAX)−T_A(MAX)

⎜

⎟

P_D(MAX)

=

⎜

⎟

R_(j−a)

⎝

⎠

(125−60)

P_D(MAX)

= 1.3W

50

3779f

34

For more information www.linear.com/LTC3779

LTC3779

applicaTions inForMaTion

The maximum dissipation in QA occurs at minimum input

voltage when the circuit operates in the boost region and

QA is on continuously. The input current is then:

The highest dissipation occurs at minimum input voltage

when the inductor current is highest. For switch QC the

dissipation is:

V_OUT•I

(V_OUT− V )V

IN

2

OUT

^OUT(MAX), or 10A

P

=

C,BOOST

V

IN

IN(MIN)

2

• I_OUT(MAX)• ρ_t• R_DS(ON)

We calculate a maximum value for R

:

DS(ON)

I_OUT(MAX)

P

3

D(MAX)

+ k • V_OUT

•

• C_RSS• f

R_DS(ON)(125°C) <

2

V

IN

I

IN(MAX)

where C_RSSis usually specified by the MOSFET

manufacturers. The constant k, which accounts for the

loss caused by reverse recovery current, is inversely

proportional to the gate drive current and has an empirical

value of 1.7.

1.3W

R_DS(ON)(125°C) <

= 0.013Ω

(10A)²

The Infineon BSC360N15NS3G has a typical R_DS(ON)

of 0.036Ω at V = 10V. Two MOSFETs can be used in

GS

parallel to handle the power dissipation.

The dissipation in switch QD is:

The maximum dissipation in QB occurs at maximum input

voltage when the circuit is operating in the buck region.

The dissipation is:

2

⎛

⎜

⎝

⎞

⎟

⎠

V

V_OUT

IN

P_D,BOOST

=

•

• I_OUT(MAX)

V_OUT

• ρ_t• R_DS(ON)

V

IN

V − V

IN

OUT

P_B,BUCK

=

•I_OUT(MAX)²•ρ_t•R_DS(ON)

V

IN

BSC050NE2LS is a possible choice for QC and QD. The

calculated power loss at 6V input voltage is then 0.392W

for QC and 0.375W for QD.

1.3W

R_DS(ON)(125°C)<

= 0.059Ω

⎛

⎜

⎝

⎞

⎟

⎠

100V −12V

• (5A)²

100V

C_INis chosen to filter the square current in the buck

region. In this mode, the maximum input current peak is:

The Infineon BSC190N15NS3G with a typical R

19mΩ can be used.

of

DS(ON)

⎛

⎞

⎟

⎠

70ꢀ

2 •100ꢀ

I_{IN,PEAK(MAX,BUCK)}= 5A • 1+

= 6.75A

⎜

⎝

Select QC and QD. With 12V output voltage we need

MOSFETs with 20V or higher rating.

A low ESR (10mΩ) capacitor is selected. Input voltage

ripple is 67.5mV (assuming ESR dominates the ripple).

C

is chosen to filter the square current in the boost

OUT

region. In this mode, the maximum output current peak is:

⎛

⎞

⎟

⎠

12

6

10ꢀ

2 •100ꢀ

I_{OUT,PEAK(MAX,BOOST)}

=

• 5 • 1+

= 10.5A

⎜

⎝

A low ESR (5mΩ) capacitor is suggested. This capacitor

will limit output voltage ripple to 53mV (assuming ESR

dominates the ripple).

3779f

35

For more information www.linear.com/LTC3779

LTC3779

applicaTions inForMaTion

3779f

36

For more information www.linear.com/LTC3779

LTC3779

package DescripTion

Please refer to http://www.linear.com/product/LTC3779#packaging for the most recent package drawings.

FE Package

Package Variation: FE38 (31)

38-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1865 Rev B)

Exposed Pad Variation AB

4.75 REF

9.60 – 9.80*

(.378 – .386)

4.75

(.187)

REF

38

20

6.60 0.10

4.50 REF

2.74 REF

SEE NOTE 4

6.40

2.74

REF (.252)

(.108)

0.315 0.05

BSC

1.05 0.10

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

PIN NUMBERS 23, 25, 27, 29, 31, 33 AND 35 ARE REMOVED

19

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.50

(.0196)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.17 – 0.27

(.0067 – .0106)

TYP

FE38 (AB) TSSOP REV B 0910

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

3. DRAWING NOT TO SCALE

3779f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation

37

that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC3779

LTC3779

Typical applicaTion

99% Efficient 480W, 48V Output Buck-Boost Converter

V

IN

20V TO 120V

D2

1µF

×5

200V

10µF

×2

125V

4mΩ

V

48V

10A

OUT

D1

10µF

×3

50V

56µF

63V

1k

M

V

BOOST1

TOPA

INSNS

5Ω

M

TOPD

×2

V

0.22µF

IN

15µH

0.1µF

SW1

TG1

BG1

10k

M

BOTC

BOTB

RUN

133k

V

INOV

475k

100Ω

220pF

SENSEP

1.21k

R1

4mΩ

M

NDRV

SENSEN

SGND

100Ω

DRV

CC

LTC3779

EXTV

CC

PGND

10µF

1µF

BG2

BOOST2

PGOOD

0.22µF

100k

SW2

V5

TG2

DRVSET

2.2µF

100Ω

I

AVGSNSP

SS

D1, D2: DFLS1200-7

4.7µF

M

: BSC190N15NS3 G

100Ω

NDRV

FREQ

: BSC110N15NS5

: BSC093N15NS5

: BSC028N06NS

: BSC066N06NS

I

TOPA

BOTB

TOPD

BOTC

AVGSNSN

0.1µF

1k

V

OUTSNS

56.2k

MODE

V

FB

3779 TA02

PLLIN

I

TH

12.1k

10k

10nF

100pF

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

LT^®8705A

LTC7813

LTC3899

LTM^®8056

LTC3895

LTC3639

LTC3638

LTC7138

LTC7103

80V V and V

DC/DC Controller

Synchronous 4-Switch Buck-Boost

2.8V ≤ V ≤ 80V, Input and Output Current Monitor, 5mm × 7mm QFN-38

and TSSOP-38

IN

OUT

IN

60V Low I Synchronous Boost+Buck Controller Low EMI 4.5V (Down to 2.2V After Start-Up) ≤ V ≤ 60V, Boost V

Up to 60V,

Q

IN

OUT

and Low Input/Output Ripple

0.8V ≤ Buck V

≤ 60V, I = 29µA, 5mm × 5mm QFN-32

OUT Q

60V, Triple Output, Buck/Buck/Boost Synchronous

Controller with 29µA Burst Mode I

4.5V (Down to 2.2V After Start-Up) ≤ V ≤ 60V, V

Up to 60V, Buck V

OUT OUT

IN

Range: 0.8V to 60V, Boost V

Up to 60V

Q

OUT

58V Buck-Boost μModule Regulator, Adjustable Input and 5V ≤ V ≤ 58V, 1.2V ≤ V

Output Current Limiting

≤ 48V 15mm × 15mm × 4.92mm BGA Package

IN

OUT

150V Low I , Synchronous Step-Down DC/DC Controller 4V ≤ V ≤ 140V, 150V Absolute Maximum, PLL Fixed Frequency 50kHz to

Q

IN

with 100% Duty Cycle

900kHz, 0.8V ≤ V ≤ 60V, Adjustable 5V to 10V Gate Drive, I = 40µA

OUT Q

150V High Efficiency 100mA Synchronous Step-Down

Regulator

Integrated Power MOSFETs, 4V≤ V ≤ 150V, 0.8V ≤ V

MSOP-16(12)

≤ V , I = 12µA,

IN Q

IN

OUT

140V High Efficiency 250mA Step-Down Regulator

Integrated Power MOSFETs, 4V≤ V ≤ 140V, 0.8V ≤ V

≤ V , I = 12µA,

IN Q

IN

MSOP-16(12)

140V High Efficiency 400mA Step-Down Regulator

Integrated Power MOSFETs, 4V≤ V ≤ 140V, 0.8V ≤ V

≤ V , I = 12µA,

IN Q

IN

MSOP-16(12)

105V, 2.3A Low EMI Synchronous Step-Down Regulator 4.4V ≤ V ≤ 105V, 1V ≤ V

≤ V , I = 2µA Fixed Frequency 200kHz to

IN Q

IN

OUT

2MHz, 5mm × 6mm QFN

3779f

LT 0817 • PRINTED IN USA

www.linear.com/LTC3779

38

 LINEAR TECHNOLOGY CORPORATION 2017

For more information www.linear.com/LTC3779


型号：	LTC3779HFE#PBF
厂家：	Linear
描述：	LTC3779 - 150V VIN and VOUT Synchronous 4-Switch Buck-Boost Controller; Package: TSSOP; Pins: 38; Temperature Range: -40°C to 125°C 开关
文件：	总38页 (文件大小：2113K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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