LTC3786EMSEPBF [Linear]
Low IQ Synchronous Boost Controller; 低智商同步升压控制器
| 型号： | LTC3786EMSEPBF |
| 厂家： | 
Linear |
| 描述： | Low IQ Synchronous Boost Controller |
| 文件： | 总34页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3786
Low I Synchronous
Q
Boost Controller
FeaTures
DescripTion
n
Synchronous Operation For Highest Efficiency and
The LTC®3786 is a high performance synchronous boost
converter controller that drives all N-channel power
MOSFETs. Synchronous rectification increases efficiency,
reduces power losses and eases thermal requirements,
allowing the LTC3786 to be used in high power boost
applications.
Reduced Heat Dissipation
n
Wide V Range: 4.5V to 38V (40V Abs Max) and
IN
Operates Down to 2.5V After Start-Up
Output Voltages Up to 60V
n
n
n
n
n
n
n
n
n
n
n
n
1ꢀ 1.2V Reference Voltage
R
or Inductor DCR Current Sensing
SENSE
A 4.5V to 38V input supply range encompasses a wide
range of system architectures and battery chemistries.
When biased from the output of the boost converter or
another auxiliary supply, the LTC3786 can operate from
an input supply as low as 2.5V after start-up. The 55µA
no-load quiescent current extends operating run time in
battery-powered systems.
100ꢀ DutyCycle Capability forSynchronous MOSFET
Low Quiescent Current: 55µA
Phase-Lockable Frequency (75kHz to 850kHz)
Programmable Fixed Frequency (50kHz to 900kHz)
Adjustable Output Voltage Soft-Start
Power Good Output Voltage Monitor
Low Shutdown Current I : <8µA
Internal 5.4V LDO for Gate Drive Supply
Thermally Enhanced 16-Pin 3mm × 3mm QFN and
MSOP Packages
Q
The operating frequency can be set for a 50kHz to 900kHz
range or synchronized to an external clock using the
internal PLL. The LTC3786 also features a precision 1.2V
reference and a power good output indicator. The SS pin
rampstheoutputvoltageduringstart-up.ThePLLIN/MODE
pin selects among Burst Mode® operation, pulse-skipping
mode or continuous inductor current mode at light loads.
applicaTions
n
Industrial and Automotive Power Supplies
n
Automotive Start-Stop Systems
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are
n
Medical Devices
High Voltage Battery-Powered Systems
registered trademarks and No R
is a trademark of Linear Technology Corporation. All other
SENSE
n
trademarks are the property of their respective owners. Protected by U. S. Patents, including
5408150, 5481178, 5705919, 5929620, 6177787, 6498466, 6580258, 6611131.
Typical applicaTion
12V to 24V/5A Synchronous Boost Converter
Efficiency and Power Loss
vs Load Current
V
4.5V TO 24V
IN
VBIAS
SENSE
100
90
80
70
60
50
40
30
20
10
0
10000
1000
100
10
+
LTC3786
220µF
4mΩ
BURST
–
EFFICIENCY
SENSE
BURST
LOSS
PGOOD
PLLIN/MODE
RUN
3.3µH
FREQ
TG
0.1µF
V
24V
5A
OUT
SS
SW
0.1µF
15nF
220µF
8.66k
12.1k
BOOST
BG
ITH
V
V
= 12V
220pF
IN
OUT
1
= 24V
Burst Mode OPERATION
FIGURE 8 CIRCUIT
INTV
CC
VFB
0.1
4.7µF
0.00001 0.0001 0.001 0.01
0.1
1
10
GND
232k
OUTPUT CURRENT (A)
3786 TA01a
3786 TA01b
3786fa
1
LTC3786
absoluTe MaxiMuM raTings (Notes 1, 3)
+
+
–
VBIAS ........................................................ –0.3V to 40V
BOOST ........................................................–0.3V to 71V
SW............................................................. –0.3V to 65V
RUN ............................................................. –0.3V to 8V
Maximum Current Sourced into Pin
from Source >8V ..............................................100µA
PGOOD, PLLIN/MODE.................................. –0.3V to 6V
INTV , (BOOST – SW) ............................... –0.3V to 6V
SENSE , SENSE ........................................ –0.3V to 40V
SENSE – SENSE ..................................... –0.3V to 0.3V
SS, ITH, FREQ, VFB...............................–0.3V to INTV
–
CC
Operating Junction Temperature Range...–40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
MSE Package Only............................................300°C
CC
pin conFiguraTion
TOP VIEW
TOP VIEW
16 15 14 13
1
2
3
4
5
6
7
8
VFB
16 PGOOD
15 SW
+
SW
PGOOD
VFB
1
2
3
4
12 BG
SENSE
–
SENSE
14 TG
11 GND
17
GND
17
GND
ITH
SS
13 BOOST
12 VBIAS
RUN
10
9
PLLIN/MODE
FREQ
11 INTV
CC
+
SENSE
FREQ
10 BG
RUN
9
GND
5
6
7
8
MSE PACKAGE
16-LEAD PLASTIC MSOP
T
= 125°C, θ = 40°C/W, θ = 10°C/W
JMAX
JA JC
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 68°C/W, θ = 4.2°C/W
JA JC
JMAX
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC3786EMSE#PBF
LTC3786IMSE#PBF
LTC3786EUD#PBF
LTC3786IUD#PBF
TAPE AND REEL
PART MARKING*
3786
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3786EMSE#TRPBF
LTC3786IMSE#TRPBF
LTC3786EUD#TRPBF
LTC3786IUD#TRPBF
16-Lead Plastic MSOP
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
3786
16-Lead Plastic MSOP
LFXW
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
LFXW
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3786fa
2
LTC3786
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, unless otherwise noted (Note 2).
SYMBOL
Main Control Loop
VBIAS Chip Bias Voltage Operating Range
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4.5
38
1.212
50
V
V
l
V
Regulated Feedback Voltage
Feedback Current
I
= 1.2V (Note 4)
TH
1.188
1.200
5
FB
I
(Note 4)
= 6V to 38V
nA
FB
V
V
Reference Line Voltage Regulation
Output Voltage Load Regulation
V
0.002
0.02
%/V
REFLNREG
LOADREG
BIAS
(Note 4)
l
l
Measured in Servo Loop;
0.01
0.1
%
%
∆I Voltage = 1.2V to 0.7V
TH
Measured in Servo Loop;
–0.01
–0.1
∆I Voltage = 1.2V to 2V
TH
g
Error Amplifier Transconductance
I
= 1.2V
TH
2
mmho
m
I
Input DC Supply Current
Pulse-Skipping or Forced Continuous Mode
Sleep Mode
(Note 5)
Q
RUN = 5V; V = 1.25V (No Load)
0.8
55
8
mA
µA
µA
FB
RUN = 5V; V = 1.25V (No Load)
RUN = 0V
80
20
FB
Shutdown
l
l
UVLO
INTV Undervoltage Lockout Thresholds
V
V
Ramping Up
Ramping Down
4.1
3.8
4.3
V
V
CC
INTVCC
INTVCC
3.6
l
V
V
RUN Pin On Threshold
V
Rising
1.18
1.28
100
4.5
0.5
10
1.38
V
mV
µA
µA
µA
mV
V
RUN
RUN
RUN Pin Hysteresis
RUNHYS
RUNHYS
RUN
I
I
I
RUN Pin Hysteresis Current
RUN Pin Current
V
V
V
V
> 1.28V
RUN
RUN
< 1.28V
Soft-Start Charge Current
Maximum Current Sense Threshold
SENSE Pins Common Mode Range (BOOST
= 0V
7
13
82
38
SS
SS
FB
l
V
V
= 1.1V
68
2.5
75
SENSE(MAX)
SENSE(CM)
Converter Input Supply Voltage V )
IN
+
+
I
I
t
t
t
t
SENSE Pin Current
V
V
C
C
C
C
= 1.1V
= 1.1V
200
300
1
µA
µA
ns
ns
ns
ns
Ω
SENSE
FB
FB
–
–
SENSE Pin Current
SENSE
Top Gate Rise Time
= 3300pF (Note 6)
= 3300pF (Note 6)
= 3300pF (Note 6)
= 3300pF (Note 6)
20
20
r(TG)
f(TG)
r(BG)
f(BG)
LOAD
LOAD
LOAD
LOAD
Top Gate Fall Time
Bottom Gate Rise Time
20
Bottom Gate Fall Time
20
R
R
R
R
Top Gate Pull-Up Resistance
Top Gate Pull-Down Resistance
Bottom Gate Pull-Up Resistance
Bottom Gate Pull-Down Resistance
1.2
1.2
1.2
1.2
80
UP(TG)
DN(TG)
UP(BG)
DN(BG)
D(TG/BG)
Ω
Ω
Ω
t
t
Top Gate Off to Bottom Gate On Switch-On
Delay Time
C
C
= 3300pF (Each Driver)
= 3300pF (Each Driver)
ns
LOAD
LOAD
Bottom Gate Off to Top Gate On Switch-On
Delay Time
80
ns
D(BG/TG)
DF
Maximum BG Duty Factor
Minimum BG On-Time
96
%
MAXBG
t
(Note 7)
110
ns
ON(MIN)
3786fa
3
LTC3786
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VBIAS = 12V, unless otherwise noted (Note 2).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INTV Linear Regulator
CC
INTVCC(VIN)
V
V
Internal V Voltage
6V < VBIAS < 38V
5.2
5.4
0.5
5.6
2
V
CC
INT
INTV Load Regulation
I = 0mA to 50mA
CC
%
LDO
CC
Oscillator and Phase-Locked Loop
f
Programmable Frequency
R
R
R
= 25k
= 60k
= 100k
105
400
760
kHz
kHz
kHz
PROG
FREQ
FREQ
FREQ
335
465
f
f
f
Lowest Fixed Frequency
Highest Fixed Frequency
Synchronizable Frequency
V
V
= 0V
320
485
75
350
535
380
585
850
kHz
kHz
kHz
LOW
HIGH
SYNC
FREQ
FREQ
= INTV
CC
l
PLLIN/MODE = External Clock
PGOOD Output
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
PGL
PGOOD
I
V
V
µA
PGOOD
PGOOD
V
with Respect to Set Regulated Voltage
FB
PG
V
Ramping Negative
–12
8
–10
2.5
10
–8
12
%
%
%
%
FB
Hysteresis
Ramping Positive
V
FB
Hysteresis
2.5
t
PGOOD Delay
PGOOD Going High to Low
25
µs
PGOOD(DELAY)
BOOST Charge Pump
I
BOOST Charge Pump Available
Output Current
V
= 12V; V
– V = 4.5V;
85
µA
BOOST
SW
BOOST
SW
FREQ = 0V, Forced Continuous or
Pulse-Skipping Mode
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 2: The LTC3786 is tested under pulsed load conditions such that
T ≈ T . The LTC3786E is guaranteed to meet specifications from
J
A
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3786I is guaranteed over the –40°C to 125°C operating junction
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors. The junction temperature
Note 4: The LTC3786 is tested in a feedback loop that servos V to the
FB
output of the error amplifier while maintaining I at the midpoint of the
TH
current limit range.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: see Minimum On-Time Considerations in the Applications
Information section.
(T in °C) is calculated from the ambient temperature (T in °C) and power
J
A
dissipation (P in Watts) according to the formula:
D
T = T + (P • θ )
JA
J
A
D
where θ = 68°C for the QFN package and θ = 40°C for the MSOP
JA
JA
package.
3786fa
4
LTC3786
Typical perForMance characTerisTics
Efficiency and Power Loss
vs Output Current
Efficiency and Power Loss
vs Output Current
100
90
80
70
60
50
40
30
20
10
0
10000
1000
100
10
100
90
80
70
60
50
40
30
20
10
0
10000
1000
100
10
BURST
EFFICIENCY
BURST
LOSS
V
V
= 12V
IN
OUT
= 24V
FIGURE 8 CIRCUIT
CCM EFFICIENCY
CMM LOSS
BURST EFFICIENCY
BURST LOSS
PULSE-SKIPPING EFFICIENCY
PULSE-SKIPPING LOSS
V
V
= 12V
IN
OUT
1
1
= 24V
Burst Mode OPERATION
FIGURE 8 CIRCUIT
0.1
0.1
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01
0.1
1
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
3786 G01
3786 G02
Load Step
Forced Continuous Mode
Load Step
Burst Mode Operation
Efficiency vs Input Voltage
100
99
I
= 2A
LOAD
LOAD STEP
2A/DIV
LOAD STEP
2A/DIV
FIGURE 8 CIRCUIT
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
98
97
96
95
94
93
V
= 12V
OUT
V
= 24V
OUT
V
OUT
V
OUT
500mV/DIV
500mV/DIV
3786 G04
3786 G05
V
V
= 12V
200µs/DIV
V
V
= 12V
200µs/DIV
IN
OUT
IN
OUT
= 24V
= 24V
LOAD STEP FROM 200mA TO 2.5A
FIGURE 8 CIRCUIT
LOAD STEP FROM 200mA TO 2.5A
FIGURE 8 CIRCUIT
5
10
15
25
0
20
INPUT VOLTAGE (V)
3786 G03
Load Step
Pulse-Skipping Mode
Inductor Current at Light Load
Soft Start-Up
LOAD STEP
2A/DIV
INDUCTOR
CURRENT
5A/DIV
FORCED
CONTINUOUS
MODE
V
OUT
5V/DIV
Burst Mode
OPERATION
5A/DIV
V
OUT
PULSE-
SKIPPING MODE
500mV/DIV
0V
3786 G06
3786 G07
3786 G08
V
V
= 12V
200µs/DIV
V
V
LOAD
= 12V
5µs/DIV
V
V
= 12V
20ms/DIV
IN
OUT
IN
IN
OUT
= 24V
= 24V
= 24V
OUT
LOAD STEP FROM 200mA TO 2.5A
FIGURE 8 CIRCUIT
I
= 200µA
FIGURE 8 CIRCUIT
FIGURE 8 CIRCUIT
3786fa
5
LTC3786
Typical perForMance characTerisTics
Regulated Feedback Voltage
vs Temperature
Soft-Start Pull-Up Current
vs Temperature
Shutdown Current vs Temperature
1.212
11.0
10.5
10.0
9.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
V
= 12V
IN
1.209
1.206
1.203
1.200
1.197
1.194
1.191
1.188
9.0
–20
5
55
80 105 130
–45
30
–20
5
55
80 105 130
–45 –20
5
30
55
80 105 130
–45
30
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3786 G11
3786 G09
3786 G10
Shutdown Current
vs Input Voltage
Shutdown (RUN) Threshold
vs Temperature
Quiescent Current vs Temperature
20
15
10
5
1.40
1.35
1.30
1.25
1.20
1.15
1.10
80
70
60
50
V
V
= 12V
= 1.25V
IN
FB
RUN RISING
40
30
20
RUN FALLING
0
–20
5
55
80 105 130
55
TEMPERATURE (°C)
105 130
–45
30
5
10
20 25 30 35 40
15
INPUT VOLTAGE (V)
–45 –20
5
30
80
0
TEMPERATURE (°C)
3786 G12
3786 G14
3786 G13
Undervoltage Lockout Threshold
vs Temperature
INTVCC Line Regulation
INTVCC Line Regulation
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
NO LOAD
NO LOAD
INTV RISING
CC
INTV FALLING
CC
0
20
INPUT VOLTAGE (V)
30 35
–20
5
55
80 105 130
5
10 15
25
40
6.0
–45
30
4.5
4.75
5.25
5.5
5.75
5.0
TEMPERATURE (°C)
INPUT VOLTAGE (V)
3786 G15
3786 G16
3786 G17
3786fa
6
LTC3786
Typical perForMance characTerisTics
Oscillator Frequency
vs Temperature
INTVCC vs Load Current
INTVCC vs Load Current
600
550
500
450
400
350
300
5.50
5.45
5.40
5.35
5.30
5.25
5.20
5.15
5.2
5.0
4.8
4.6
4.4
4.2
4.0
V = 5V
IN
V
= 12V
IN
FREQ = INTV
CC
FREQ = GND
55
80 105 130
0
20
30
40
50
60
–45
5
30
10
–20
0
20
60 80
180
40
100 120 140 160
LOAD CURRENT (mA)
TEMPERATURE (°C)
LOAD CURRENT (mA)
3786 G20
3786 G19
3786 G18
Oscillator Frequency
vs Input Voltage
Maximum Current Sense
Threshold vs ITH Voltage
SENSE Pin Input Current
vs Temperature
360
358
356
354
352
350
348
346
344
342
340
260
240
220
200
180
160
140
120
100
80
120
100
80
FREQ = GND
V
= 12V
SENSE
PULSE-SKIPPING MODE
FORCED CONTINUOUS MODE
Burst Mode OPERATION
+
SENSE PIN
60
40
20
0
60
40
20
0
–20
–40
–60
–
SENSE PIN
5
10
20
INPUT VOLTAGE (V)
25
30
35
40
0
0.6
0.8
VOLTAGE (V)
1.0
1.2 1.4
–45 –20
5
30
55
80 105 130
15
0.2 0.4
TEMPERATURE (°C)
I
TH
3786 G21
3786 G23
3786 G22
SENSE Pin Input Current
vs ITH Voltage
SENSE Pin Input Current
vs VSENSE Voltage
Maximum Current Sense
Threshold vs Duty Cycle
260
240
220
200
180
160
140
120
100
80
260
240
220
200
180
160
140
120
100
80
120
100
80
60
40
20
0
V
= 12V
SENSE
+
+
SENSE PIN
SENSE PIN
60
40
20
0
60
40
20
0
–
–
SENSE PIN
SENSE PIN
20 30 40 50 60
100
70 80 90
0
1
I
1.5
2
2.5
3
2.5
17.5 22.5 27.5 32.5 37.5
7.5 12.5
V COMMON MODE VOLTAGE (V)
SENSE
0
10
0.5
VOLTAGE (V)
DUTY CYCLE (%)
TH
3786 G24
3786 G25
3786 G26
3786fa
7
LTC3786
Typical perForMance characTerisTics
Charge Pump Charging Current
vs Operating Frequency
Charge Pump Charging Current
vs Switch Voltage
110
100
90
80
70
60
50
40
30
20
10
0
120
100
80
V
V
= 16.5V
BOOST
SW
FREQ = 0V
= 12V
–45°C
25°C
FREQ = INTV
CC
130°C
60
40
20
0
50 150 250 350 450 550 650 750
OPERATING FREQUENCY (kHz)
5
20
25
30
35
40
10
15
SWITCH VOLTAGE (V)
3786 G27
3786 G28
pin FuncTions (MSOP/QFN)
VFB (Pin 1/Pin 3): Error Amplifier Feedback Input. This
pin receives the remotely sensed feedback voltage from
an external resistive divider connected across the output.
SS (Pin 5/Pin 7): Output Soft-Start Input. A capacitor to
ground at this pin sets the ramp rate of the output voltage
during start-up.
+
SENSE (Pin2/Pin4):PositiveCurrentSenseComparator
PLLIN/MODE(Pin6/Pin9):ExternalSynchronizationInput
to Phase Detector and Forced Continuous Mode Input.
When an external clock is applied to this pin, it will force
the controller into forced continuous mode of operation
and the phase-locked loop will force the rising BG signal
to be synchronized with the rising edge of the external
clock. When not synchronizing to an external clock, this
input determines how the LTC3786 operates at light loads.
Pulling this pin to ground selects Burst Mode operation.
An internal 100k resistor to ground also invokes Burst
Mode operation when the pin is floated. Tying this pin
Input. The (+) input to the current comparator is normally
connectedtothepositiveterminalofacurrentsenseresis-
tor. The current sense resistor is normally placed at the
input of the boost controller in series with the inductor.
This pin also supplies power to the current comparator.
–
SENSE (Pin3/Pin5):NegativeCurrentSenseComparator
Input. The (–) input to the current comparator is normally
connected to the negative terminal of a current sense re-
sistor connected in series with the inductor. The common
+
–
mode voltage range on the SENSE and SENSE pins is
2.5V to 38V (40V abs max).
to INTV forces continuous inductor current operation.
CC
Tying this pin to a voltage greater than 1.2V and less than
ITH (Pin 4/Pin 6): Current Control Threshold and Error
Amplifier Compensation Point. The voltage on this pin
sets the current trip threshold.
INTV – 1.3V selects pulse-skipping operation. This can
CC
be done by adding a 100k resistor between the PLLIN/
MODE pin and INTV .
CC
3786fa
8
LTC3786
pin FuncTions (MSOP/QFN)
FREQ (Pin 7/Pin 9): The Frequency Control Pin for the
Internal VCO. Connecting the pin to GND forces the VCO
to a fixed low frequency of 350kHz. Connecting the pin
BG (Pin 10/Pin 12): Bottom Gate. Connect to the gate of
the main N-channel MOSFET.
INTV (Pin 11/Pin 13): Output of Internal 5.4V LDO.
CC
to INTV forces the VCO to a fixed high frequency of
CC
Power supply for control circuits and gate drivers. De-
couple this pin to GND with a minimum 4.7µF low ESR
ceramic capacitor.
535kHz. The frequency can be programmed from 50kHz
to 900kHz by connecting a resistor from the FREQ pin to
GND. The resistor and an internal 20µA source current
create a voltage used by the internal oscillator to set the
frequency. Alternatively, this pin can be driven with a DC
voltage to vary the frequency of the internal oscillator.
VBIAS (Pin 12/Pin 14): Main Supply Pin. It is normally
tied to the input supply V or to the output of the boost
IN
converter. A bypass capacitor should be tied between this
pin and the GND pin. The operating voltage range on this
pin is 4.5V to 38V (40V abs max).
RUN (Pin 8/Pin 10): Run Control Input. Forcing this pin
below 1.28V shuts down the controller. Forcing this pin
below 0.7V shuts down the entire LTC3786, reducing
quiescent current to approximately 8µA. An external
BOOST (Pin 13/Pin 15): Floating Power Supply for the
Synchronous MOSFET. Bypass to SW with a capacitor
and supply with a Schottky diode connected to INTV .
resistor divider connected to V can set the threshold
CC
IN
for converter operation. Once running, a 4.5µA current is
sourced from the RUN pin allowing the user to program
hysteresis using the resistor values.
TG (Pin 14/Pin 16): Top Gate. Connect to the gate of the
synchronous NMOS.
SW (Pin 15/Pin 1): Switch Node. Connect to the source
of the synchronous top MOSFET, the drain of the main
bottom MOSFET, and the inductor.
GND (Pin 9, Exposed Pad Pin 17/ Pin 11, Exposed Pad
Pin 17): Ground. Connects to the source of the bottom
(main) N-channel MOSFET and the (–) terminal(s) of C
IN
PGOOD (Pin 16/Pin 2): Power Good Indicator. Open-drain
logic output that is pulled to ground when the output volt-
age is more than 10 % away from the regulated output
voltage. To avoid false trips the output voltage must be
outsideoftherangefor25µsbeforethisoutputisactivated.
and C . All small-signal components and compensa-
OUT
tion components should also connect to this ground.
The exposed pad must be soldered to the PCB for rated
thermal performance.
3786fa
9
LTC3786
block DiagraM
INTV
CC
D
B
PGOOD
BOOST
1.32V
+
–
S
R
Q
C
TG
B
V
FB
SHDN
+
–
SWITCHING
LOGIC
V
OUT
1.08V
20µA
SW
AND
CHARGE
PUMP
C
OUT
INTV
CC
FREQ
BG
CLK
VCO
PFD
+
0.425V
SLEEP
–
–
+
ICMP
IREV
L
+
+
+
– –
–
–
+
2mV
SENSE
SENSE
VFB
2.8V
0.7V
PLLIN/
MODE
R
SENSE
SLOPE COMP
SENS LO
SYNC
DET
V
IN
C
IN
+
–
100k
2.5V
+
–
–
1.2V
SS
EA
VBIAS
+
–
OV
1.32V
C
C
ITH
SHDN
0.5µA/
4.5µA
R
C
C
C2
5.4V
LDO
+
–
11V
10µA
3786 BD
3.8V
SENS
LO
SHDN
RUN
INTV
GND
SS
CC
C
SS
3786fa
10
LTC3786
operaTion (Refer to the Block Diagram)
Main Control Loop
ance source, do not exceed the absolute maximum rating
of 8V. The RUN pin has an internal 11V voltage clamp
that allows the RUN pin to be connected through a resis-
The LTC3786 uses a constant-frequency, current mode
step-up control architecture. During normal operation,
the external bottom MOSFET is turned on when the clock
sets the RS latch, and is turned off when the main current
comparator, ICMP, resets the RS latch. The peak inductor
current at which ICMP trips and resets the latch is con-
trolled by the voltage on the ITH pin, which is the output
of the error amplifier, EA. The error amplifier compares
the output voltage feedback signal at the VFB pin, (which
is generated with an external resistor divider connected
tor to a higher voltage (for example, V ), as long as the
IN
maximumcurrentintotheRUNpindoesnotexceed100µA.
An external resistor divider connected to V can set the
IN
threshold for converter operation. Once running, a 4.5µA
current is sourced from the RUN pin allowing the user to
program hysteresis using the resistor values.
The start-up of the controller’s output voltage, V , is
OUT
controlled by the voltage on the SS pin. When the voltage
on the SS pin is less than the 1.2V internal reference, the
LTC3786 regulates the VFB voltage to the SS pin voltage
instead of the 1.2V reference. This allows the SS pin to
be used to program a soft-start by connecting an external
capacitor from the SS pin to GND. An internal 10µA pull-
up current charges this capacitor creating a voltage ramp
on the SS pin. As the SS voltage rises linearly from 0V to
1.2V, the output voltage rises smoothly to its final value.
across the output voltage, V , to ground) to the internal
OUT
1.200Vreferencevoltage.Inaboostconverter,therequired
inductorcurrentisdeterminedbytheloadcurrent, V and
IN
V
OUT
. When the load current increases, it causes a slight
decreaseinVFBrelativetothereference, whichcausesthe
EA to increase the ITH voltage until the average inductor
current in each channel matches the new requirement
based on the new load current.
After the bottom MOSFET is turned off each cycle, the
top MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current comparator
IR, or the beginning of the next clock cycle.
Light Load Current Operation—Burst Mode Operation,
Pulse-Skipping or Continuous Conduction
(PLLIN/MODE Pin)
The LTC3786 can be enabled to enter high efficiency Burst
Modeoperation,constant-frequencypulse-skippingmode
or forced continuous conduction mode at low load cur-
rents.ToselectBurstModeoperation,tiethePLLIN/MODE
pin to ground. To select forced continuous operation, tie
INTV Power
CC
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV pin. The
CC
VBIAS LDO (low dropout linear regulator) supplies 5.4V
the PLLIN/MODE pin to INTV . To select pulse-skipping
CC
from VBIAS to INTV .
CC
mode, tie the PLLIN/MODE pin to a DC voltage greater
than 1.2V and less than INTV – 1.3V.
CC
Shutdown and Start-Up (RUN and SS Pins)
When the controller is enabled for Burst Mode opera-
tion, the minimum peak current in the inductor is set to
approximately 30% of the maximum sense voltage even
though the voltage on the ITH pin indicates a lower value.
If the average inductor current is higher than the required
current, the error amplifier, EA, will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.450V.
The LTC3786 can be shut down using the RUN pin. Pulling
this pin below 1.28V shuts down the main control loop.
Pulling this pin below 0.7V disables the controller and
most internal circuits, including the INTV LDOs. In this
CC
state, the LTC3786 draws only 8µA of quiescent current.
Note: Do not apply load while the chip is in shutdown. The
output MOSFET will be turned off during shutdown and
the output load may cause excessive power dissipation
in the body diode.
The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low imped-
3786fa
11
LTC3786
operaTion (Refer to the Block Diagram)
In sleep mode, much of the internal circuitry is turned off
and the LTC3786 draws only 55µA of quiescent current.
In sleep mode, the load current is supplied by the output
capacitor. Astheoutputvoltagedecreases, theEA’s output
begins to rise. When the output voltage drops enough,
the ITH pin is reconnected to the output of the EA, the
sleep signal goes low, and the controller resumes normal
operation by turning on the bottom external MOSFET on
the next cycle of the internal oscillator.
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
When the controller is enabled for Burst Mode operation,
theinductorcurrentisnotallowedtoreverse. Thereverse-
currentcomparator(IR)turnsoffthetopexternalMOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous current operation.
The switching frequency of the LTC3786’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to GND, tied to
In forced continuous operation or when clocked by an
external clock source to use the phase-locked loop (see
theFrequencySelectionandPhase-LockedLoopsection),
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
rent is determined by the voltage on the ITH pin, just as
in normal operation. In this mode, the efficiency at light
loads is lower than in Burst Mode operation. However,
continuous operation has the advantages of lower output
voltage ripple and less interference to audio circuitry, as
it maintains constant-frequency operation independent
of load current.
,orprogrammedthroughanexternalresistor.Tying
INTV
CC
FREQ to GND selects 350kHz while tying FREQ to INTV
CC
selects535kHz. PlacingaresistorbetweenFREQandGND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 5.
A phase-locked loop (PLL) is available on the LTC3786
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3786’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of the external bottom MOSFET to the rising edge
of the synchronizing signal.
WhenthePLLIN/MODEpinisconnectedforpulse-skipping
mode,theLTC3786operatesinPWMpulse-skippingmode
at light loads. In this mode, constant-frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
comparator ICMP may remain tripped for several cycles
and force the external bottom MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of BG. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
3786fa
12
LTC3786
operaTion (Refer to the Block Diagram)
The typical capture range of the LTC3786’s PLL is from
approximately 55kHz to 1MHz, and is guaranteed to lock
to an external clock source whose frequency is between
75kHz and 850kHz.
Power Good
The PGOOD pin is connected to an open-drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the VFB pin voltage is not
within 10% of the 1.2V reference voltage. The PGOOD
pin is also pulled low when the corresponding RUN pin
is low (shut down). When the VFB pin voltage is within
the 10% requirement, the MOSFET is turned off and the
pin is allowed to be pulled up by an external resistor to a
source of up to 6V (abs max).
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
Operation When V > Regulated V
IN
OUT
WhenV risesabovetheregulatedV voltage,theboost
IN
OUT
controller can behave differently depending on the mode,
inductor current and V voltage. In forced continuous
IN
Operation at Low SENSE Pin Common Mode Voltage
mode,theloopkeepsthetopMOSFEToncontinuouslyonce
V rises above V . The internal charge pump delivers
ThecurrentcomparatorintheLTC3786ispowereddirectly
IN
OUT
+
current to the boost capacitor to maintain a sufficiently
high TG voltage. (The amount of current the charge pump
can deliver is characterized by two curves in the Typical
Performance Characteristics section.)
from the SENSE pin. This enables the common mode
+
–
voltage of SENSE and SENSE pins to operate as low
as 2.5V, which is below the INTV UVLO threshold. The
CC
figure on the first page shows a typical application when
the controller’s VBIAS is powered from V
while V
OUT
IN
Inpulse-skippingmode, ifV isbetween100%and110%
IN
+
supply can go as low as 2.5V. If the voltage on SENSE
drops below 2.5V, the SS pin will be held low. When the
of the regulated V
voltage, TG turns on if the inductor
OUT
current rises above a certain threshold and turns off if the
inductor current falls below this threshold. This threshold
current is set to approximately 4% of the maximum ILIM
current. If the controller is programmed to Burst Mode
+
SENSE voltagereturnstothenormaloperatingrange, the
SS pin will be released, initiating a new soft-start cycle.
BOOST Supply Refresh and Internal Charge Pump
operation under this same V window, then TG remains
IN
The top MOSFET driver is biased from the floating boot-
strap capacitor, C , which normally recharges during each
off regardless of the inductor current.
B
If V rises above 110% of the regulated V
voltage in
IN
OUT
cycle through an external diode when the bottom MOSFET
turns on. There are two considerations to keep the BOOST
supply at the required bias level. During start-up, if the
bottom MOSFET is not turned on within 100µs after UVLO
goes low, the bottom MOSFET will be forced to turn on
for~400ns. This forced refresh generates enough BOOST-
SW voltage to allow the top MOSFET to be fully enhanced
instead of waiting for the initial few cycles to charge the
any mode, the controller turns on TG regardless of the
inductor current. In Burst Mode operation, however, the
internal charge pump turns off if the chip is asleep. With
the charge pump off, there would be nothing to prevent
the boost capacitor from discharging, resulting in an
insufficient TG voltage needed to keep the top MOSFET
completely on. To prevent excessive power dissipation
across the body diode of the top MOSFET in this situa-
tion, the chip can be switched over to forced continuous
or pulse-skipping mode to enable the charge pump, or a
Schottky diode can also be placed in parallel to the top
MOSFET.
bootstrap capacitor, C . There is also an internal charge
B
pump that keeps the required bias on BOOST. The charge
pump always operates in both forced continuous mode
and pulse-skipping mode. In Burst Mode operation, the
charge pump is turned off during sleep and enabled when
the chip wakes up. The internal charge pump can normally
supply a charging current of 85µA.
3786fa
13
LTC3786
applicaTions inForMaTion
TheTypicalApplicationonthefirstpageisabasicLTC3786
applicationcircuit.LTC3786canbeconfiguredtouseeither
inductor DCR (DC resistance) sensing or a discrete sense
Filter components mutual to the sense lines should be
placed close to the LTC3786, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), sense resistor R1 should be placed
closetotheswitchingnode,topreventnoisefromcoupling
into sensitive small-signal nodes.
resistor (R
) for current sensing. The choice between
SENSE
the two current sensing schemes is largely a design trade-
off between cost, power consumption and accuracy. DCR
sensing is becoming popular because it does not require
current sensing resistors and is more power efficient,
especially in high current applications. However, current
sensing resistors provide the most accurate current limits
for the controller. Other external component selection is
driven by the load requirement, and begins with the se-
Sense Resistor Current Sensing
lection of R
(if R
is used) and inductor value.
SENSE
SENSE
Next, the power MOSFETs are selected. Finally, input and
output capacitors are selected.
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. R
output current.
is chosen based on the required
SENSE
+
–
SENSE and SENSE Pins
The current comparator has a maximum threshold
of 75mV. The current comparator threshold
+
–
The SENSE and SENSE pins are the inputs to the cur-
rent comparators. The common mode input voltage range
of the current comparators is 2.5V to 38V. The current
sense resistor is normally placed at the input of the boost
controller in series with the inductor.
V
SENSE(MAX)
sets the peak of the inductor current, yielding a maximum
average inductor current, I , equal to the peak value
MAX
TO SENSE FILTER,
NEXT TO THE CONTROLLER
+
The SENSE pin also provides power to the current com-
parator. It draws ~200µA during normal operation. There
is a small base current of less than 1µA that flows into
the SENSE pin. The high impedance SENSE input to the
current comparators allows accurate DCR sensing.
V
IN
–
–
INDUCTOR OR R
3786 F01
SENSE
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
V
VBIAS
V
VBIAS
IN
IN
+
+
SENSE
SENSE
C1 R2
(OPTIONAL)
DCR
L
–
–
SENSE
SENSE
INTV
INTV
CC
CC
INDUCTOR
R1
LTC3786
LTC3786
BOOST
BOOST
TG
TG
V
V
SW
BG
SW
BG
OUT
OUT
SGND
SGND
3786 F02a
3786 F02b
L
DCR
R2
R1 + R2
||
PLACE C1 NEAR SENSE PINS (R1 R2) • C1 =
R
= DCR •
SENSE(EQ)
(2a) Using a Resistor to Sense Current
(2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
3786fa
14
LTC3786
applicaTions inForMaTion
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the maximum current sense threshold
less half the peak-to-peak ripple current, ∆I . To calculate
L
the sense resistor value, use the equation:
V
SENSE(MAX)
(V
).
R
=
SENSE(MAX)
SENSE
∆I
L
I
+
MAX
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficientofresistance,whichisapproximately0.4%/°C.A
conservativevalueforthemaximuminductortemperature
2
WhenusingthecontrollerinlowV andveryhighvoltage
IN
output applications, the maximum inductor current and
correspondingly the maximum output current level will
be reduced due to the internal compensation required to
meet stability criterion for boost regulators operating at
greater than 50% duty factor. A curve is provided in the
Typical Performance Characteristics section to estimate
this reduction in peak inductor current level depending
upon the operating duty factor.
(T ) is 100°C.
L(MAX)
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
RSENSE(EQUIV)
RD =
DCRMAX at T
L(MAX)
Inductor DCR Sensing
C1 is usually selected to be in the range of 0.1µF to 0.47µF.
ThisforcesR1||R2toaround2k, reducingerrorthatmight
For applications requiring the highest possible efficiency
at high load currents, the LTC3786 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor can be less than 1mΩ
for high current inductors. In a high current application
requiring such an inductor, conduction loss through a
sense resistor could reduce the efficiency by a few percent
compared to DCR sensing.
–
have been caused by the SENSE pin’s 1µA current.
The equivalent resistance R1|| R2 is scaled to the room
temperature inductance and maximum DCR:
L
R1||R2 =
DCR at 20°C • C1
(
)
The sense resistor values are:
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature. Consult
the manufacturer’s data sheets for detailed information.
R1||R2
RD
R1•RD
1– RD
R1=
; R2 =
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at V = 1/2 V
:
OUT
IN
V
• V • V
IN IN
(
=
)
OUT
PLOSS_R1
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
totheextraswitchinglossesincurredthroughR1.However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Using the inductor ripple current value from the inductor
valuecalculationsection,thetargetsenseresistorvalueis:
VSENSE(MAX)
RSENSE(EQUIV)
=
∆IL
IMAX
+
2
Peak efficiency is about the same with either method.
3786fa
15
LTC3786
applicaTions inForMaTion
Inductor Value Calculation
The peak-to-peak gate drive levels are set by the INTV
CC
voltage. Thisvoltageistypically5.4V. Consequently, logic-
level threshold MOSFETs must be used in most applica-
The operating frequency and inductor selection are in-
terrelated in that higher operating frequencies allow the
use of smaller inductor and capacitor values. Why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge and switching losses. Also, at
higher frequency, the duty cycle of body diode conduction
is higher, which results in lower efficiency. In addition to
this basic trade-off, the effect of inductor value on ripple
currentandlowcurrentoperationmustalsobeconsidered.
tions. Pay close attention to the BV
specification for
DSS
the MOSFETs as well; many of the logic level MOSFETs
are limited to 30V or less.
Selection criteria for the power MOSFETs include the on-
resistance, R
, Miller capacitance, C , input
DS(ON) MILLER
voltage and maximum output current. Miller capacitance,
, can be approximated from the gate charge curve
C
MILLER
usually provided on the MOSFET manufacturer’s data
sheet. C is equal to the increase in gate charge
MILLER
along the horizontal axis while the curve is approximately
The inductor value has a direct effect on ripple current.
flat divided by the specified change in V . This result is
DS
The inductor ripple current ∆I decreases with higher
L
then multiplied by the ratio of the application applied V
DS
inductance or frequency and increases with higher V :
IN
to the gate charge curve specified V . When the IC is
DS
operating in continuous mode, the duty cycles for the top
and bottom MOSFETs are given by:
V
f •L
V
IN
VOUT
IN
∆IL =
1–
VOUT – V
IN
Main Switch Duty Cycle =
VOUT
Accepting larger values of ∆I allows the use of low
L
inductances, but results in higher output voltage ripple
V
VOUT
IN
and greater core losses. A reasonable starting point for
Synchronous Switch Duty Cycle =
setting ripple current is ∆I = 0.3(I
). The maximum
MAX
L
∆I occurs at V = 1/2 V .
L
IN
OUT
IfthemaximumoutputcurrentisI
andeachchan-
OUT(MAX)
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
nel takes one-half of the total output current, the MOSFET
power dissipations in each channel at maximum output
current are given by:
25% of the current limit determined by R
. Lower
SENSE
V
– V
V
IN
OUT
(
)
inductor values (higher ∆I ) will cause this to occur at
OUT
L
2
PMAIN
=
•IOUT(MAX) • 1+ δ
(
)
2
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease. Once the value of L is known, an
inductor with low DCR and low core losses should be
selected.
V
IN
IOUT(MAX)
3
•RDS(ON) + k • VOUT
•
•RDR
V
IN
• CMILLER • f
V
VOUT
IN
2
P
=
•IOUT(MAX) • 1+ δ •R
(
)
SYNC
DS(ON)
Power MOSFET Selection
Two external power MOSFETs must be selected for the
LTC3786: one N-channel MOSFET for the bottom (main)
switch, and one N-channel MOSFET for the top (synchro-
nous) switch.
where δ is the temperature dependency of R
DS(ON)
(approximately 1Ω) is the effective driver resistance at the
MOSFET’s Miller threshold voltage. The constant k, which
3786fa
16
LTC3786
applicaTions inForMaTion
accounts for the loss caused by reverse recovery current,
is inversely proportional to the gate drive current and has
an empirical value of 1.7.
The steady ripple voltage due to charging and discharging
the bulk capacitance in a single phase boost converter is
given by:
2
BothMOSFETshaveI RlosseswhilethebottomN-channel
IOUT(MAX) • V
– VIN(MIN)
(
)
OUT
VRIPPLE
=
V
equation includes an additional term for transition losses,
COUT • VOUT • f
which are highest at low input voltages. For high V the
IN
high current efficiency generally improves with larger
where C
is the output filter capacitor.
OUT
MOSFETs, while for low V the transition losses rapidly
IN
The steady ripple due to the voltage drop across the ESR
is given by:
increasetothepointthattheuseofahigherR
device
DS(ON)
withlowerC
actuallyprovideshigherefficiency.The
MILLER
synchronous MOSFET losses are greatest at high input
voltage when the bottom switch duty factor is low or dur-
ing overvoltage when the synchronous switch is on close
to 100% of the period.
∆V
= I
• ESR
L(MAX)
ESR
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings (i.e., OS-CON and POSCAP).
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
vs Temperature curve, but
DS(ON)
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
C and C
IN
Selection
OUT
Setting Output Voltage
The input ripple current in a boost converter is relatively
low (compared with the output ripple current), because
The LTC3786 output voltage is set by an external feedback
resistordividercarefullyplacedacrosstheoutput,asshown
in Figure 3. The regulated output voltage is determined by:
this current is continuous. The input capacitor, C , volt-
IN
age rating should comfortably exceed the maximum input
voltage. Although ceramic capacitors can be relatively
tolerant of overvoltage conditions, aluminum electrolytic
capacitorsarenot.Besuretocharacterizetheinputvoltage
for any possible overvoltage transients that could apply
excess stress to the input capacitors.
RB
RA
VOUT = 1.2V 1+
Great care should be taken to route the VFB line away
from noise sources, such as the inductor or the SW line.
Also, keep the VFB node as small as possible to avoid
noise pickup.
The value of the C is a function of the source impedance,
IN
andingeneral,thehigherthesourceimpedance,thehigher
the required input capacitance. The required amount of
inputcapacitanceisalsogreatlyaffectedbythedutycycle.
High output current applications that also experience high
duty cycles can place great demands on the input supply,
both in terms of DC current and ripple current.
V
OUT
R
B
LTC3786
VFB
Inaboostconverter,theoutputhasadiscontinuouscurrent,
R
A
so C
must be capable of reducing the output voltage
OUT
3786 F03
ripple. The effects of ESR (equivalent series resistance)
andthebulkcapacitancemustbeconsideredwhenchoos-
ing the right capacitor for a given output ripple voltage.
Figure 3. Setting Output Voltage
3786fa
17
LTC3786
applicaTions inForMaTion
Soft-Start (SS Pin)
temperature, the LTC3786 INTV current is limited to
CC
less than 20mA in the QFN package from a 40V supply:
The start-up of the V
is controlled by the voltage on
OUT
the SS pin. When the voltage on the SS pin is less than
theinternal1.2Vreference, theLTC3786regulatestheVFB
pin voltage to the voltage on the SS pin instead of 1.2V.
T = 70°C + (20mA)(40V)(68°C/W) = 125°C
J
In an MSOP package, the INTV current is limited to less
CC
than 34mA from a 40V supply:
Soft-startisenabledbysimplyconnectingacapacitorfrom
the SS pin to ground, as shown in Figure 4. An internal
10µA current source charges the capacitor, providing a
linear ramping voltage at the SS pin. The LTC3786 will
T = 70°C + (34mA)(40V)(40°C/W) = 125°C
J
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (PLLIN/MODE
regulate the V pin (and hence, V ) according to the
FB
OUT
OUT
= INTV ) at maximum VBIAS.
voltage on the SS pin, allowing V
from V to its final regulated value. The total soft-start
to rise smoothly
CC
IN
Topside MOSFET Driver Supply (C , D )
B
B
time will be approximately:
External bootstrap capacitors, C , connected to the
B
1.2V
10µA
tSS = CSS
•
BOOST pin supplies the gate drive voltage for the topside
MOSFET. Capacitor C in the Block Diagram is charged
B
though external diode, D , from INTV when the SW pin
B
CC
LTC3786
SS
is low. When the topside MOSFET is to be turned on, the
driver places the C voltage across the gate-source of the
B
C
SS
desired MOSFET. This enhances the MOSFET and turns on
SGND
3786 F04
the topside switch. The switch node voltage, SW, rises to
V
andtheBOOSTpinfollows.WiththetopsideMOSFET
OUT
Figure 4. Using the SS Pin to Program Soft-Start
on, the boost voltage is above the output voltage: V
BOOST
= V
+ V
. The value of the boost capacitor, C ,
INTVCC B
OUT
INTV Regulator
CC
needs to be 100 times that of the total input capacitance
of the topside MOSFET(s). The reverse breakdown of the
The LTC3786 features an internal P-channel low dropout
linear regulator (LDO) that supplies power at the INTV
external Schottky diode must be greater than V
.
CC
IN(MAX)
pin from the VBIAS supply pin. INTV powers the gate
CC
The external diode D can be a Schottky diode or silicon
B
drivers and much of the LTC3786’s internal circuitry. The
diode,butineithercaseitshouldhavelowleakageandfast
recovery. Paycloseattentiontothereverseleakageathigh
temperatures where it generally increases substantially.
VBIAS LDO regulates INTV to 5.4V. It can supply at least
CC
50mA and must be bypassed to ground with a minimum
of 4.7µF ceramic capacitor. Good bypassing is needed to
supplythehightransientcurrentsrequiredbytheMOSFET
gate drivers.
The topside MOSFET driver includes an internal charge
pumpthatdeliverscurrenttothebootstrapcapacitorfrom
the BOOST pin. This charge current maintains the bias
voltage required to keep the top MOSFET on continuously
during dropout/overvoltage conditions. The Schottky/
silicon diode selected for the topside driver should have a
reverse leakage less than the available output current the
charge pump can supply. Curves displaying the available
charge pump current under different operating conditions
can be found in the Typical Performance Characteristics
section.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the
maximum junction temperature rating for the LTC3786
to be exceeded. The power dissipation for the IC is equal
to VBIAS • I
. The gate charge current is dependent
INTVCC
on operating frequency, as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 2 of the
Electrical Characteristics. For example, at 70°C ambient
3786fa
18
LTC3786
applicaTions inForMaTion
A leaky diode D in the boost converter can not only
ously from the phase detector output, pulling up the VCO
B
prevent the top MOSFET from fully turning on but it can
input. When the external clock frequency is less than f
,
OSC
also completely discharge the bootstrap capacitor C and
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
B
create a current path from the input voltage to the BOOST
pin to INTV . This can cause INTV to rise if the diode
CC
CC
leakage exceeds the current consumption on INTV .
CC
This is particularly a concern in Burst Mode operation
where the load on INTV can be very small. The external
CC
Schottky or silicon diode should be carefully chosen such
that INTV never gets charged up much higher than its
CC
normal regulation voltage.
C , holds the voltage at the VCO input.
LP
Typically, the external clock (on PLLIN/MODE pin) input
highthresholdis1.6V,whiletheinputlowthresholdis1.2V.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on-chip
Note that the LTC3786 can only be synchronized to an
external clock whose frequency is within range of the
LTC3786’s internal VCO, which is nominally 55kHz to
1MHz.Thisisguaranteedtobebetween75kHzand850kHz.
(such as an INTV short to ground), the overtemperature
CC
shutdown circuitry will shut down the LTC3786. When the
junction temperature exceeds approximately 170°C, the
overtemperaturecircuitrydisablestheINTV LDO,causing
RapidphaselockingcanbeachievedbyusingtheFREQpin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
CC
the INTV supply to collapse and effectively shut down
CC
the entire LTC3786 chip. Once the junction temperature
dropsbacktoapproximately155°C, theINTV LDOturns
CC
back on. Long-term overstress (T > 125°C) should be
J
avoided as it can degrade the performance or shorten
the life of the part.
Since the shutdown may occur at full load, beware that
the load current won’t result in high power dissipation in
the body diodes of the top MOSFET. In this case, PGOOD
output may be used to turn the system load off.
1000
900
800
700
600
500
400
300
200
100
Phase-Locked Loop and Frequency Synchronization
The LTC3786 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the bottom MOSFET to be locked to the rising
edgeofanexternalclocksignalappliedtothePLLIN/MODE
pin. The phase detector is an edge-sensitive digital type
thatprovideszerodegreesphaseshiftbetweentheexternal
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
3786 F05
If the external clock frequency is greater than the internal
Figure 5. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
oscillator’sfrequency,f ,thencurrentissourcedcontinu-
OSC
3786fa
19
LTC3786
applicaTions inForMaTion
Table 2 summarizes the different states in which the FREQ
pin can be used.
losses in LTC3786 circuits: 1) IC VBIAS current, 2) INTV
CC
2
regulatorcurrent,3)I Rlosses,4)BottomMOSFETtransi-
tion losses and 5) Body diode conduction losses.
Table 2
1. The VBIAS current is the DC supply current given in the
ElectricalCharacteristicstable,whichexcludesMOSFET
driver and control currents. VBIAS current typically
results in a small (<0.1%) loss.
FREQ PIN
PLLIN/MODE PIN
DC Voltage
FREQUENCY
350kHz
0V
INTV
DC Voltage
535kHz
CC
Resistor
DC Voltage
50kHz to 900kHz
Phase Locked to External Clock
Any of the Above
External Clock
2. INTV current is the sum of the MOSFET driver and
CC
control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOS-
FETs. Each time a MOSFET gate is switched from low to
high to low again, a packet of charge, dQ, moves from
Minimum On-Time Considerations
Minimum on-time, t , is the smallest time duration
that the LTC3786 is capable of turning on the bottom
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum
on-time limit.
ON(MIN)
INTV to ground. The resulting dQ/dt is a current out
CC
of INTV that is typically much larger than the control
CC
circuit current. In continuous mode, I
= f(Q +
GATECHG
T
Q ),whereQ andQ arethegatechargesofthetopside
B
T
B
and bottom side MOSFETs.
In forced continuous mode, if the duty cycle falls below
what can be accommodated by the minimum on-time,
the controller will begin to skip cycles but the output will
continuetoberegulated.Morecycleswillbeskippedwhen
V increases. Once V rises above V , the loop keeps
2
3. DC I R losses. These arise from the resistances of the
MOSFETs, sensing resistor, inductor and PC board
traces and cause the efficiency to drop at high output
currents.
IN
IN
OUT
the top MOSFET continuously on. The minimum on-time
for the LTC3786 is approximately 110ns.
4. Transition losses apply only to the bottom MOSFET(s),
andbecomesignificantonlywhenoperatingatlowinput
voltages. Transition losses can be estimated from:
Efficiency Considerations
3 IMAX • CRSS • f
VOUT
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the greatest improvement. Percent efficiency
can be expressed as:
Transition Loss = 1.7
(
)
V
IN
5. Body diode conduction losses are more significant at
higherswitchingfrequency.Duringthedeadtime,theloss
inthetopMOSFETsisI • V ,whereV isaround0.7V.
L
DS
DS
At higher switching frequency, the dead time becomes
a good percentage of switching cycle and causes the
efficiency to drop.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Other hidden losses, such as copper trace and internal
batteryresistances,canaccountforanadditionalefficiency
degradation in portable systems. It is very important to
includethesesystem-levellossesduringthedesignphase.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
3786fa
20
LTC3786
applicaTions inForMaTion
Checking Transient Response
This is why it is better to look at the ITH pin signal which
is in the feedbackloopandisthe filtered and compensated
control loop response.
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in load current.
The gain of the loop will be increased by increasing
When a load step occurs, V
shifts by an amount equal
R and the bandwidth of the loop will be increased by
OUT
C
to∆I
,whereESRistheeffectiveseriesresistance
decreasing C . If R is increased by the same factor that
C C
LOAD(ESR)
of C . ∆I
also begins to charge or discharge C
C is decreased, the zero frequency will be kept the same,
OUT
LOAD
OUT
C
generatingthefeedbackerrorsignalthatforcestheregula-
tor to adapt to the current change and return V to its
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loopsystemandwilldemonstratetheactualoverall
supply performance.
OUT
OUT
steady-state value. During this recovery time V
can
be monitored for excessive overshoot or ringing, which
would indicate a stability problem. OPTI-LOOP® compen-
sation allows the transient response to be optimized over
a wide range of output capacitance and ESR values. The
availability of the ITH pin not only allows optimization of
control loop behavior, but it also provides a DC-coupled
and AC-filtered closed-loop response test point. The DC
step,risetimeandsettlingatthistestpointtrulyreflectsthe
closed-loopresponse. Assuming a predominantly second
order system, phasemarginand/or dampingfactor canbe
estimated using the percentage of overshoot seen at this
pin.Thebandwidthcanalsobeestimatedbyexaminingthe
rise time at the pin. The ITH external components shown
in the Figure 8 circuit will provide an adequate starting
point for most applications.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
is greater than 1:50, the switch rise time
OUT
should be controlled so that the load rise time is limited to
approximately 25 • C . Thus, a 10µF capacitor would
LOAD
require a 250µs rise time, limiting the charging current
to about 200mA.
Design Example
The ITH series R -C filter sets the dominant pole-zero
C
C
loop compensation. The values can be modified slightly
to optimize transient response once the final PCB layout
is complete and the particular output capacitor type and
value have been determined. The output capacitors must
beselectedbecausethevarioustypesandvaluesdetermine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1µs to
10µs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
As a design example, assume V = 12V(nominal),
IN
V =22V(max), V
=24V, I
=4A, V
IN
OUT
OUT(MAX) SENSE(MAX)
= 75mV and f = 350kHz.
Theinductancevalueischosenfirstbasedona30%ripple
current assumption. Tie the MODE/PLLIN pin to GND,
generating 350kHz operation. The minimum inductance
for 30% ripple current is:
V
f •L
V
IN
VOUT
IN
∆IL =
1–
Placing a power MOSFET and load resistor directly
across the output capacitor and driving the gate with an
appropriate pulse generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current
may not be within the bandwidth of the feedback loop,
so this signal cannot be used to determine phase margin.
The largest ripple happens when V = 1/2V
= 12V,
OUT
IN
where the average maximum inductor is I
= I
MAX OUT(MAX)
• (V /V ) = 8A. A 6.8µH inductor will produce a 31%
OUT IN
ripple current. The peak inductor current will be the maxi-
mum DC value plus one-half the ripple current, or 9.25A.
3786fa
21
LTC3786
applicaTions inForMaTion
The R
resistor value can be calculated by using the
1. Put the bottom N-channel MOSFET MBOT and the top
N-channel MOSFET MTOP in one compact area with
SENSE
maximum current sense voltage specification with some
accommodation for tolerances:
C
.
OUT
75mV
9.25A
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
RSENSE
≤
= 0.008Ω
of C
must return to the combined C
(–)
INTVCC
OUT
Choosing 1% resistors: R = 5k and R = 95.3k yields an
output voltage of 24.072V.
terminals. The path formed by the bottom N-channel
MOSFET and the capacitor should have short leads and
PC trace lengths. The output capacitor (–) terminals
should be connected as close as possible to the (–)
source terminal of the bottom MOSFET.
A
B
ThepowerdissipationonthetopsideMOSFETineachchan-
nelcanbeeasilyestimated.ChoosingaVishaySi7848BDP
MOSFET results in: R
maximum input voltage with T(estimated) = 50°C:
= 0.012Ω, C
= 150pF. At
DS(ON)
MILLER
3. Does the LTC3786 VFB pin’s resistive divider connect
to the (+) terminal of C ? The resistive divider must
OUT
24V – 12V 24V
(
)
2
P
=
• 4A
be connected between the (+) terminal of C
and
(
)
MAIN
OUT
2
12V
(
)
signal ground and placed close to the VFB pin. The
feedback resistor connections should not be along the
high current input feeds from the input capacitor(s).
• 1+ 0.005 50°C – 25°C • 0.008Ω
(
)
(
)
4A
3
–
+
+ 1.7 24V
) (
150pF 350kHz = 0.7W
) (
(
)
(
)
4. Are the SENSE and SENSE leads routed together with
minimumPCtracespacing?Thefiltercapacitorbetween
12V
+
–
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
C
is chosen to filter the square current in the output.
The maximum output current peak is:
OUT
RIPPLE%
2
IOUT(PEAK) = IOUT(MAX) • 1+
5. Is the INTV decoupling capacitor connected close
CC
to the IC, between the INTV and the power ground
CC
31%
2
pin? This capacitor carries the MOSFET drivers’ cur-
= 4 • 1+
= 4.62A
rent peaks. An additional 1µF ceramic capacitor placed
immediately next to the INTV and GND pins can help
CC
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 23.1mV (assuming ESR
dominate ripple).
improve noise performance substantially.
6. Keep the switching node (SW), top gate node (TG) and
boost node (BOOST) away from sensitive small-signal
nodes. All of these nodes have very large and fast
moving signals and, therefore, should be kept on the
output side of the LTC3786 and occupy a minimal PC
trace area.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 6. Figure 7 illustrates the current
waveforms present in the various branches the synchro-
nous regulator operating in the continuous mode. Check
the following in your layout:
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
CC
decouplingcapacitor,thebottomofthevoltagefeedback
resistive divider and the GND pin of the IC.
3786fa
22
LTC3786
applicaTions inForMaTion
PC Board Layout Debugging
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling.
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Moni-
tor the output switching node (SW pin) to synchronize
the oscilloscope to the internal oscillator and probe the
actual output voltage. Check for proper performance over
the operating voltage and current range expected in the
application. The frequency of operation should be main-
tained over the input voltage range down to dropout and
until the output load drops below the low current opera-
tion threshold— typically 10% of the maximum designed
current level in Burst Mode operation.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hook-up will still
bemaintained,buttheadvantagesofcurrentmodecontrol
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawelldesigned, lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pick-up at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
Reduce V from its nominal level to verify operation with
IN
high duty cycle. Check the operation of the undervoltage
lockout circuit by further lowering V while monitoring
IN
the outputs to verify operation.
3786fa
23
LTC3786
applicaTions inForMaTion
+
SENSE
SENSE
PGOOD
V
PULLUP
–
R
SENSE
L1
SW
TG
LTC3786
C
B
BOOST
BG
FREQ
+
M1
M2
f
IN
PLLIN/MODE
RUN
VBIAS
GND
VFB
+
V
IN
ITH
SS
GND
INTV
CC
V
OUT
3786 F06
Figure 6. Recommended Printed Circuit Layout Diagram
L1
V
SW
R
OUT
V
SENSE
IN
R
IN
C
R
L
OUT
C
IN
3786 F07
BOLD LINES INDICATE HIGH SWITCHING CURRENT.
KEEP LINES TO A MINIMUM LENGTH
Figure 7. Branch Current Waveforms
3786fa
24
LTC3786
applicaTions inForMaTion
VBIAS
+
SENSE
LTC3786
SENSE
V
IN
5V TO 24V
R
C
SENSE
IN
4mΩ
22µF
–
L
3.3µH
PLLIN/MODE
RUN
TG
FREQ
V
24V
5A*
OUT
C
0.1µF
SS
SW
C
0.1µF
D
+
C
B
MTOP
MBOT
OUTA
C
SS
OUTB
22µF
220µF
BOOST
BG
×4
C
ITH
15nF
R
8.66k
ITH
ITH
C
ITHA
220pF
INTV
CC
C
INT
4.7µF
GND
R
12.1k
A
100k
VFB
PGOOD
R
S
232k
3786 F08
C
C
, C
OUTB
D: BAS140W
: TDK C4532X5R1E226M
IN OUTA
: SANYO 50CE220LX
L: PULSE PA1494.362NL
MBOT, MTOP: RENESAS HAT2169H
*WHEN V < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
IN
Figure 8. High Efficiency 24V Boost Converter
VBIAS
+
SENSE
V
IN
5V TO 28V
R
SENSE
C
IN
LTC3786
SENSE
4mΩ
6.8µF
–
×4
L
3.3µH
PLLIN/MODE
RUN
TG
FREQ
V
28V
4A*
OUT
C
0.1µF
SS
SW
C
0.1µF
D
+
C
B
OUTA
MTOP
MBOT
C
SS
OUTB
6.8µF
220µF
BOOST
BG
×4
C
ITH
15nF
R
8.66k
ITH
ITH
C
ITHA
220pF
INTV
CC
C
INT
4.7µF
GND
R
12.1k
A
100k
VFB
PGOOD
R
S
261k
3786 F09
C
C
, C
OUTB
D: BAS140W
: TDK C4532X7R1H685K
IN OUTA
: SANYO 63CE220KX
L: PULSE PA1494.362NL
MBOT, MTOP: RENESAS HAT2169H
*WHEN V < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
IN
Figure 9. High Efficiency 28V Boost Converter
3786fa
25
LTC3786
applicaTions inForMaTion
VBIAS
+
SENSE
LTC3786
SENSE
V
IN
5V TO 36V
R
C
SENSE
IN
5mΩ
6.8µF
–
×4
L
10.2µH
PLLIN/MODE
RUN
TG
FREQ
V
36V
3A*
OUT
C
0.1µF
SS
SW
C
0.1µF
D
+
C
B
OUTA
MTOP
MBOT
C
SS
OUTB
6.8µF
220µF
BOOST
BG
×4
C
ITH
15nF
R
8.66k
ITH
ITH
C
ITHA
220pF
INTV
CC
C
INT
4.7µF
GND
R
12.1k
A
100k
VFB
PGOOD
R
S
357k
3786 F10
C
, C
: TDK C4532X7R1H685K
IN OUTA
C
: SANYO 63CE220KX
OUTB
D: BAS170W
L: PULSE PA2050.103NL
MBOT, MTOP: RENESAS RJIC0652DPB
*WHEN V < 9V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
IN
Figure 10. High Efficiency 36V Boost Converter
VBIAS
+
SENSE
V
IN
5.8V TO 34V
R
SENSE
C
LTC3786
SENSE
IN
9mΩ
22µF
–
L
10µH
•
•
C
10µF
PLLIN/MODE
RUN
TG
D
FREQ
V
OUT
C
SS
0.1µF
10.5V
1.2A
SW
BOOST
BG
C
OUT
SS
270µF
MBOT
C
ITH
100nF
R
13k
ITH
ITH
INTV
CC
C
10pF
ITHA
C
INT
4.7µF
GND
R
115k
A
100k
PGOOD
VFB
R
S
887k
3786 F11
C
C
: SANYO 50CE220LX
IN
: SANYO SVPC270M
OUT
D: DIODES, INC. B360A-13-F
L: COOPER BUSSMANN DRQ125-100
MBOT: BSZ097NO4L
Figure 11. 10.5V Nonsynchronous SEPIC Converter
3786fa
26
LTC3786
applicaTions inForMaTion
VBIAS
V
IN
4.5V TO 24V START-UP
VOLTAGE OPERATES THROUGH
TRANSIENTS DOWN TO 2.5V
+
C
SENSE
IN
22µF
R
SENSE
5mΩ
LTC3786
–
SENSE
L
60.4k
= 400kHz
3.2µH
RUN
f
SW
FREQ
TG
V
10V
5A
*
OUT
C
SS
SW
0.1µF
C
+
C
B
MTOP
OUTA
C
OUTB
0.1µF
22µF
SS
150µF
×3
C
ITH
BOOST
BG
R
ITH
10nF
4.64k
MBOT
ITH
C
ITHA
100pF
D
INTV
CC
C
INT
4.7µF
R
A
GND
12.1k
100k
100k
VFB
PLLIN/MODE
R
88.7k
B
PGOOD
3786 F12a
C
OUTB
, C
: TDK C4532X5R1E226M
IN OUTA
C
: SANYO 35HVH150M
L: SUMIDA CDEP106-3R2-88
MBOT, MTOP: RENESAS HAT2170
D: INFINEON BAS140W
*WHEN V > 10V, V
FOLLOWS V .
IN
IN
OUT
100
98
96
94
92
90
88
86
V
= 12V
= 9V
IN
V
IN
IN
V
= 6V
1
2
3
4
5
6
OUTPUT CURRENT (A)
3786 F12b
Figure 12. High Efficiency 10V Boost Converter
3786fa
27
LTC3786
applicaTions inForMaTion
V
IN
2.7V TO 4.2V
+
C
IN
SENSE
47µF
R
SENSE
×2
LTC3786
6mΩ
–
SENSE
L
PLLIN/MODE
0.67µH
RUN
TG
V
5V
4A
OUT
FREQ
SW
C
C
C
B
SS
OUT
MTOP
0.1µF
0.1µF
47µF
×4
BOOST
BG
SS
C
ITH
MBOT
R
ITH
6.8nF
D2
5.11k
D1
ITH
Q
VBIAS
C
ITHA
INTV
100pF
CC
C
INT
4.7µF
100k
GND
R
A
V
V
IN
1M
OUT
C1
10µF
150k
C2
10µF
VFB
PGOOD
LTC1754-5
+
R
B
C
C
SHDN
C
FLY
475k
–
1µF
GND
3786 F13a
C
, C : TDK C3225X5R1A476M
IN OUT
L: TOKO FDV0840-R67M
MBOT, MTOP: INFINEON BSC046N02KS
Q: VISHAY SILICONIX Si1499DH
D1: INFINEON BAS140W
D2: NXP PMEG2005EJ
C
: MURATA GRM39X5R105K6.3AJ
FLY
C1, C2: MURATA GRM40X5R106K6.3AJ
98
96
94
92
90
88
V
V
V
= 4.2V
= 3.3V
= 2.7V
IN
IN
IN
86
0
1
2
3
4
OUTPUT CURRENT (A)
3786 F13b
Figure 13. Low IQ Lithium-Ion to 5V/4A Boost Converter
3786fa
28
LTC3786
applicaTions inForMaTion
VBIAS
SENSE
V
IN
+
5V TO 24V
C
IN
R
26.1k
1%
22µF
LTC3786
S2
C1
0.1µF
L
R
53.6k
1%
S1
10.2µH
RUN
–
SENSE
FREQ
TG
C
SS
V
24V
4A
0.1µF
OUT
SW
C
SS
+
B
MTOP
MBOT
C
OUTA
C
0.1µF
OUTB
C
ITH
22µF
220µF
R
ITH
15nF
BOOST
BG
×4
8.87k
ITH
C
D
ITHA
220pF
INTV
CC
C
INT
4.7µF
GND
PLLIN/MODE
R
A
12.1k
100k
VFB
PGOOD
R
B
232k
3786 F14a
C1: TDK C1005X7R1C104K
C
, C
: TDK C4532X5R1E226M
IN OUTA
OUTB
C
: SANYO, 50CE220AX
L: PULSE PA2050.103NL
MBOT, MTOP: RENESAS RJK0305
D: INFINEON BAS140W
100
98
96
94
92
90
88
86
V
= 12V
IN
0
1
2
3
4
OUTPUT CURRENT (A)
3786 F14b
Figure 14. High Efficiency 24V Boost Converter with Inductor DCR Current Sensing
3786fa
29
LTC3786
applicaTions inForMaTion
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
VBIAS
+
SENSE
V
IN
5V TO 12V
R
C
SENSE
IN
10nF
LTC3786
15mΩ
T
22µF
–
×2
SENSE
D
V
OUT
1:10
PLLIN/MODE
350V
25k
= 105kHz
•
C
OUT
10mA
RUN
FREQ
f
SW
68nF
TG
×2
22Ω
220pF
•
C
SS
0.1µF
SS
C
ITH
SW
BOOST
BG
R
ITH
22nF
8.66k
ITH
MBOT
C
ITHA
100pF
INTV
CC
C
INT
4.7µF
16.2k
1%
GND
100k
VFB
PGOOD
1M
1%
1M
1%
1.5M
1%
3786 F15
C
C
: TDK C3225X7R1C226M
OUT
IN
: TDK C3225X7R2J683K
D: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES
MBOT: VISHAY SILICONIX Si7850DP
T: TDK DCT15EFD-U44S003
Figure 15. Low IQ High Voltage Flyback Power Supply
VBIAS
+
SENSE
V
IN
5V TO 24V
R
C
SENSE
IN
LTC3786
SENSE
6mΩ
10µF
–
×2
L
10µH
PLLIN/MODE
RUN
TG
D
FREQ
V
24V
2A
OUT
C
0.1µF
SS
SW
+
C
OUTB
C
SS
OUTA
47µF
10µF
BOOST
BG
×4
C
ITH
22nF
C
R
8.66k
ITH
MBOT
ITH
100pF
ITHA
INTV
CC
C
INT
4.7µF
12.1k
1%
GND
100k
VFB
PGOOD
232k
1%
3786 F15
C
OUTB
, C
: MURATA GRM31CR61E106KA12
IN OUTA
C
: KEMET T495X476K035AS
D: ON SEMI MBRS340T3G
L: VISAY SILICONIX IHLP-5050FD-01 10µH
MBOT: VISHAY SILICONIX Si4840BDP
Figure 16. Low IQ Nonsynchronous 24V/2A Boost Converter
3786fa
30
LTC3786
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSE Package
16-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1667 Rev C)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ± 0.102
(.112 ± .004)
2.845 ± 0.102
(.112 ± .004)
0.889 ± 0.127
(.035 ± .005)
1
8
0.35
REF
5.23
(.206)
MIN
1.651 ± 0.102
(.065 ± .004)
1.651 ± 0.102
(.065 ± .004)
3.20 – 3.45
(.126 – .136)
0.12 REF
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
16
9
0.305 ± 0.038
0.50
(.0197)
BSC
NO MEASUREMENT PURPOSE
4.039 ± 0.102
(.159 ± .004)
(NOTE 3)
(.0120 ± .0015)
TYP
0.280 ± 0.076
(.011 ± .003)
RECOMMENDED SOLDER PAD LAYOUT
16151413121110
9
REF
DETAIL “A”
0.254
(.010)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0° – 6° TYP
4.90 ± 0.152
(.193 ± .006)
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
1 2 3 4 5 6 7 8
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MSE16) 0910 REV C
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3786fa
31
LTC3786
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
1.45 ± 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ± 0.05
3.00 ± 0.10
(4 SIDES)
15 16
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
2
1.45 ± 0.10
(4-SIDES)
(UD16) QFN 0904
0.200 REF
0.25 ± 0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3786fa
32
LTC3786
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
9/11
Updated the Topside MOSFET Driver Supply (C , D ) section.
18
27
B
B
Updated Figure 12.
3786fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC3786
Typical applicaTion
High Efficiency 48V Boost Converter
VBIAS
+
SENSE
V
IN
5V TO 38V
R
C
SENSE
IN
LTC3786
8mΩ
6.8µF
–
×4
SENSE
L
16µH
PLLIN/MODE
RUN
TG
FREQ
V
48V
2A*
OUT
C
0.1µF
SS
SW
C
0.1µF
D
+
C
B
OUTA
MTOP
MBOT
C
SS
OUTB
6.8µF
220µF
BOOST
BG
×4
C
ITH
15nF
R
8.66k
ITH
ITH
C
ITHA
220pF
INTV
CC
C
INT
4.7µF
GND
R
12.1k
A
100k
VFB
PGOOD
R
S
475k
3786 TA02
C
C
, C
OUTB
D: BAS170W
: TDK C4532X7R1H685K
IN OUTA
: SANYO 63CE220KX
L: PULSE PA2050.163NL
MBOT, MTOP: RENESAS RJK0652DPB
*WHEN V < 13V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
IN
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTC3788/LTC3788-1 2-Phase Dual Output Synchronous Step-Up Controllers
4.5V ≤ V ≤ 38V, V
Up to 60V, 50kHz to 900kHz, 5mm × 5mm
OUT
IN
QFN-32 and SSOP-28 Packages
LTC3787
LTC3859
2-Phase Single Output Synchronous Boost Controller
4.5V ≤ V ≤ 38V, V Up to 60V, 50kHz to 900kHz, 5mm × 5mm
IN
OUT
QFN-28 and SSOP-28 Packages
Low I , Triple Output, Buck/Buck/Boost Synchronous
4.5V ≤ V ≤ 38V, Boost Output Voltage Up to 60V, 50kHz to 900kHz,
Q
IN
Controller
5mm × 7mm QFN-38 and TSSOP-38 Packages
LTC3862/LTC3862-1 Multiphase Current Mode Step-Up DC/DC Controllers
4V ≤ V ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz, SSOP-24,
IN
TSSOP-24, 5mm × 5mm QFN-24
LTC3813/LTC3814-5 100V/60V Maximum V Current Mode Synchronous
No R
, Large 1Ω Gate Driver, Adjustable Off-Time, SSOP-28,
SENSE
OUT
Step-Up DC/DC Controllers
TSSOP-16
LTC1871, LTC1871-1, Wide Input Range, No R
™ Low Quiescent Current
Adjustable Switching Frequency, 2.5V ≤ V ≤ 36V, Burst Mode
SENSE
IN
LTC1871-7
Flyback, Boost and SEPIC Controllers
Operation at Light Load, MSOP-10
LT®3757/LT3758
Boost, Flyback, SEPIC and Inverting Controllers
V Up to 40V/100V, 100kHz to 1MHz Programmable Operation
IN
Frequency, 3mm × 3mm DFN-10 and MSOP-10E
LTC3780
High Efficiency Synchronous 4-Switch Buck-Boost DC/
DC Controller
4V ≤ V ≤ 36V, 0.8V ≤ V ≤ 30V, SSOP-24, 5mm × 5mm QFN-32
IN
OUT
3786fa
LT 0911 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
34
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●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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