LTC3819EG#PBF [Linear]
LTC3819 - 2-Phase, High Efficiency, Step-Down Controller for Sun Server CPUs; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C;型号: | LTC3819EG#PBF |
厂家: | Linear |
描述: | LTC3819 - 2-Phase, High Efficiency, Step-Down Controller for Sun Server CPUs; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C 开关 光电二极管 |
文件: | 总32页 (文件大小:365K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3819
2-Phase, High Efficiency,
Step-Down Controller for
Sun Server CPUs
U
DESCRIPTIO
FEATURES
■
Output Stages Operate Antiphase Reducing Input
The LTC®3819 is a 2-phase, VID programmable, synchro-
nous step-down switching regulator controller that drives
twoN-channelexternalpowerMOSFETstagesinafixedfre-
quency architecture. The 2-phase controller drives its two
output stages out of phase at frequencies up to 300kHz to
minimize the RMS ripple currents in both input and output
capacitors.The2-phasetechniqueeffectivelymultipliesthe
fundamental frequency by two, improving transient re-
sponse while operating each channel at an optimum fre-
quency for efficiency. Thermal design is also simplified.
and Output Capacitance Requirements and Power
Supply Induced Noise
■
Dual Input Supply Capability for Load Sharing
■
5-Bit SUN CPU VID Code:
VOUT = 1.025V to 1.4125V
■
±1% Output Voltage Accuracy
■
True Remote Sensing Differential Amplifier
■
Power Good Output Voltage Monitor
■
Supports Active Voltage Positioning
■
Current Mode Control Ensures Current Sharing
An operating mode select pin (FCB) can be used to select
among three modes including Burst Mode® operation for
highestefficiency.Aninternaldifferentialamplifierprovides
true remote sensing of the regulated supply’s positive and
negative output terminals as required in high current ap-
plications.
OPTI-LOOP® Compensation Minimizes COUT
■
■
Three Operational Modes: PWM, Burst and Cycle Skip
Programmable Fixed Frequency: 150kHz to 300kHz
Wide VIN Range: 4V to 36V Operation
Adjustable Soft-Start Current Ramping
Internal Current Foldback and Short-Circuit Shutdown
Overvoltage Soft Latch Eliminates Nuisance Trips
■
■
■
■
■
■
The RUN/SS pin provides soft-start and optional timed,
short-circuit shutdown. Current foldback limits MOSFET
dissipation during short-circuit conditions when the
overcurrentlatchoffisdisabled.OPTI-LOOPcompensation
allows the transient response to be optimized for a wide
range of output capacitors and ESR values.
Available in 36-LUead Narrow (0.209) SSOP Package
APPLICATIO S
■
Sun™ Server CPU Supply
, LTC and LT are registered trademarks of Linear Technology Corporation. OPTI-LOOP
and Burst Mode are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6304066, 5705919.
U
TYPICAL APPLICATIO
V
IN
5V TO 28V
10µF
35V
×6
0.1µF
V
IN
FCB
TG1
BOOST1
SW1
S
0.002Ω
RUN/SS
0.47µF
220pF
1µH
3.3k
S
LTC3819
D1
I
BG1
TH
SGND
PGND
+
SENSE1
SENSE1
PGOOD
–
5 VID BITS VID0–VID4
TG2
BOOST2
SW2
V
_
0.002Ω
DD CORE
EAIN
0.47µF
1.025V TO 1.4125V
45A
1µH
ATTENOUT
ATTENIN
D2
BG2
+
V
V
V
INTV
DIFFOUT
CC
+
C
OUT
+
–
SENSE2
SENSE2
OS
270µF
2V
10µF
+
–
OS
×4
3716 F01
Figure 1. High Current Dual Phase Step-Down Converter
3819f
1
LTC3819
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
(Note 1)
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
Input Supply Voltage (VIN).........................36V to –0.3V
Topside Driver Voltages (BOOST1,2).........42V to –0.3V
Switch Voltage (SW1, 2) .............................36V to –5 V
SENSE1+, SENSE2+, SENSE1–,
1
2
PGOOD
TG1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
RUN/SS
+
SENSE1
–
LTC3819EG
3
SW1
SENSE1
4
BOOST1
EAIN
PLLFLTR
PLLIN
SENSE2– Voltages ................... (1.1)INTVCC to –0.3V
5
V
IN
EAIN, VOS+, VOS–, EXTVCC, INTVCC, RUN/SS,
6
BG1
V
BIAS, ATTENIN, ATTENOUT, PGOOD, NO_CPU,
7
EXTV
CC
FCB
VID0–VID4, Voltages ...............................7V to –0.3V
Boosted Driver Voltage (BOOST-SW) ..........7V to –0.3V
8
INTV
CC
I
TH
9
PGND
BG2
SGND
PLLFLTR, PLLIN, VDIFFOUT
,
10
11
12
13
14
15
16
17
18
V
DIFFOUT
–
FCB Voltages ................................... INTVCC to –0.3V
TH Voltage................................................2.7V to –0.3V
BOOST2
SW2
V
V
OS
+
–
+
I
OS
TG2
SENSE2
SENSE2
Peak Output Current <1µs(TG1, 2, BG1, 2)................ 3A
INTVCC RMS Output Current................................ 50mA
Operating Ambient Temperature Range
(Note 2) .............................................. –40°C to 85°C
Junction Temperature (Note 3)............................. 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ATTENIN
V
BIAS
ATTENOUT
NO_CPU
VID0
VID4
VID3
VID2
VID1
G PACKAGE
36-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 85°C/W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 15V, V
= 5V, V
= 5V unless otherwise noted.
RUN/SS
A
IN
BIAS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
V
V
Regulated Feedback Voltage
Maximum Current Sense Threshold
Feedback Current
I
Voltage = 1.2V; Measured at V (Note 4)
EAIN
●
●
0.594
62
0.600
75
0.606
88
V
mV
nA
EAIN
TH
SENSEMAX
INEAIN
I
(Note 4)
(Note 4)
–5
–50
V
Output Voltage Load Regulation
LOADREG
Measured in Servo Loop, ∆I Voltage: 1.2V to 0.7V
●
●
0.1
–0.1
0.5
–0.5
%
%
TH
Measured in Servo Loop, ∆I Voltage: 1.2V to 2V
TH
V
V
Reference Voltage Line Regulation
Forced Continuous Threshold
Forced Continuous Current
V
= 3.6V to 30V (Note 4)
IN
0.002
0.6
0.02
0.63
–1
%/V
V
REFLNREG
FCB
●
0.57
I
– 0.17
4.3
µA
V
FCB
V
Burst Inhibit (Constant Frequency)
Threshold
Measured at FCB pin
Measured at V
4.8
BINHIBIT
V
Output Overvoltage Threshold
Undervoltage Lockout
●
0.64
3
0.66
3.33
0.68
4
V
V
OVL
EAIN
UVLO
V Ramping Down
IN
3819f
2
LTC3819
The
●
denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T = 25°C. V = 15V, V
= 5V, V
= 5V unless otherwise noted.
RUN/SS
A
IN
BIAS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
3
MAX
UNITS
mmho
V/mV
g
g
Transconductance Amplifier g
I
I
= 1.2V, Sink/Source 5µA (Note 4)
m
m
TH
TH
Transconductance Amplifier Gain
= 1.2V, (g • Z ; No Ext Load) (Note 4)
1.5
mOL
m
L
I
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
Q
1.2
20
mA
µA
V
V
V
V
= 0V
40
RUN/SS
RUN/SS
RUN/SS
RUN/SS
I
Soft-Start Charge Current
RUN/SS Pin ON Threshold
RUN/SS Pin Latchoff Arming
RUN/SS Discharge Current
Shutdown Latch Disable Current
Total Sense Pins Source Current
Maximum Duty Factor
= 1.9V
Rising
–0.5
1.0
–1.2
1.5
4.1
2
µA
V
RUN/SS
V
V
1.9
4.5
4
RUN/SS
RUN/SSLO
SCL
Rising from 3V
V
I
I
I
Soft Short Condition V
= 0.5V, V
= 4.5V
RUN/SS
0.5
µA
µA
µA
%
EAIN
V
= 0.5V
EAIN
1.6
–60
99.5
5
SDLHO
SENSE
Each Channel: V
In Dropout
(Note 6)
–
– = V
+ + = 0V
–85
98
SENSE1 , 2
SENSE1 , 2
DF
MAX
Top Gate Transition Time:
Rise Time
Fall Time
TG1, 2 t
TG1, 2 t
C
C
= 3300pF
= 3300pF
30
40
90
90
ns
ns
r
f
LOAD
LOAD
Bottom Gate Transition Time:
Rise Time
Fall Time
(Note 6)
BG1, 2 t
BG1, 2 t
C
C
= 3300pF
= 3300pF
30
20
90
90
ns
ns
r
f
LOAD
LOAD
TG/BG t
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
C
= 3300pF Each Driver (Note 6)
90
ns
ns
ns
1D
LOAD
BG/TG t
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
C
= 3300pF Each Driver (Note 6)
90
2D
LOAD
t
Minimum On-Time
Tested with a Square Wave (Note 7)
180
ON(MIN)
Internal V Regulator
CC
V
V
V
V
V
Internal V Voltage
6V < V < 30V, V = 4V
EXTVCC
4.8
4.5
5.0
0.2
80
5.2
1.0
V
%
INTVCC
CC
IN
INT
INTV Load Regulation
I
I
I
I
= 0 to 20mA, V
= 4V
EXTVCC
LDO
LDO
CC
CC
CC
CC
CC
EXT
EXTV Voltage Drop
= 20mA, V
= 5V
160
mV
V
CC
EXTVCC
EXTV Switchover Voltage
= 20mA, EXTV Ramping Positive
●
4.7
0.2
EXTVCC
LDOHYS
CC
CC
EXTV Switchover Hysteresis
= 20mA, EXTV Ramping Negative
V
CC
CC
VID Parameters
V
Operating Supply Voltage Range
2.7
5.5
V
BIAS
R
ATTEN
Resistance Between ATTENIN
and ATTENOUT Pins
5
kΩ
ATTEN
Resistive Divider Error
●
–0.35
0.25
0.4
%
kΩ
V
ERR
R
VID0 to VID4 Pull-Up Resistance
VID0 to VID4 Logic Threshold Low
VID0 to VID4 Logic Threshold High
VID0 to VID4 Leakage
(Note 8)
40
PULLUP
VID
VID
VID
THLOW
THHIGH
LEAK
1.6
V
V
< VID0–VID4 < 7V
±1
µA
V
BIAS
V
NO_CPU Maximum Output Voltage
I
= 2mA
0.4
NO_CPU
NO_CPU
3819f
3
LTC3819
The
●
denotes the specifications which apply over the full operating
= 5V, V = 5V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at T = 25°C. V = 15V, V
A
IN
BIAS
RUN/SS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator and Phase-Locked Loop
f
f
f
Nominal Frequency
Lowest Frequency
Highest Frequency
PLLIN Input Resistance
V
V
V
= 1.2V
= 0V
190
120
280
220
140
310
50
250
160
360
kHz
kHz
kHz
kΩ
NOM
LOW
HIGH
PLLFLTR
PLLFLTR
PLLFLTR
≥ 2.4V
R
PLLIN
I
Phase Detector Output Current
Sinking Capability
Sourcing Capability
PLLFLTR
f
f
< f
> f
–15
15
µA
µA
PLLIN
PLLIN
OSC
OSC
R
Controller 2-Controller 1 Phase
180
Deg
RELPHS
PGOOD Output
V
PGOOD Voltage Low
I
= 2mA
= 5V
0.1
0.3
V
PGL
PGOOD
I
PGOOD Leakage Current
PGOOD Trip Level, Either Controller
V
V
±1
µA
PGOOD
PGOOD
V
with Respect to Set Output Voltage
EAIN
PG
V
V
Ramping Negative
Ramping Positive
–8
8
–10
10
–12
12
%
%
EAIN
EAIN
Differential Amplifier/Op Amp Gain Block
A
Differential Amplifier Gain
Common Mode Rejection Ratio
Input Resistance
V
= 0V
AMPMD
0.995
46
1
1.005
V/V
dB
DA
CMRR
0V < V < 5V; V = 0V
AMPMD
55
80
DA
CM
R
Measured at V + Input; V = 0V
AMPMD
kΩ
IN
OS
Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 2: The LTC3819EG is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current ≥40% I
(see Minimum On-Time
Considerations in the Applications Information section).
MAX
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
Note 8: Each built-in pull-up resistor attached to the VID inputs also has a
LTC3819EG: T = T + (P • 85°C/W)
Note 4: The LTC3819 is tested in a feedback loop that servos V to a
series diode to allow input voltages higher than the VIDV supply without
damage or clamping (see the Applications Information section).
J
A
D
CC
ITH
specified voltage and measures the resultant V
.
EAIN
3819f
4
LTC3819
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage
(Figure 12)
Efficiency vs Load Current
Efficiency vs Load Current
(Figure 12)
(3 Operating Modes) (Figure 12)
100
80
60
40
20
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
I
= 20A
OUT
OUT
Burst Mode
OPERATION
V
= 1.4125V
V
V
V
V
= 5V
IN
IN
IN
IN
FORCED
CONTINUOUS
MODE
= 8V
= 12V
= 20V
CONSTANT
FREQUENCY
(BURST DISABLED)
V
V
= 1.4125V
OUT
EXTVCC
FREQ = 200kHz
= 0V
V
V
= 5V
IN
OUT
= 1.4125V
V
= 0V
FCB
FREQ = 200kHz
0.1
1
10
100
0.01
0.1
1
10 100
15
5
10
20
LOAD CURRENT (A)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
3819 G02
3819 G01
3819 G03
INTV and EXTV Switch
Supply Current vs Input Voltage
and Mode
CC
CC
Voltage vs Temperature
EXTV Voltage Drop
CC
250
200
150
100
50
1000
800
600
400
200
0
5.05
5.00
4.95
4.90
4.85
4.80
4.75
4.70
INTV VOLTAGE
CC
ON
EXTV SWITCHOVER THRESHOLD
CC
SHUTDOWN
0
0
10
20
30
40
50
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
0
5
10
15
20
25
30
35
CURRENT (mA)
INPUT VOLTAGE (V)
3819 G05
3819 G06
3819 G04
Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)
Maximum Current Sense Threshold
vs Duty Factor
Internal 5V LDO Line Reg
75
50
25
0
5.1
5.0
80
70
60
50
40
30
20
10
0
I
= 1mA
LOAD
4.9
4.8
4.7
4.6
4.5
4.4
0
20
40
60
80
100
20
INPUT VOLTAGE (V)
30
35
0
5
10
15
25
50
0
25
75
100
DUTY FACTOR (%)
PERCENT OF NOMINAL OUTPUT VOLTAGE (%)
3819 G08
3819 G07
3819 G09
3819f
5
LTC3819
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Current Sense Threshold
Maximum Current Sense Threshold
vs V (Soft-Start)
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
vs I Voltage
TH
RUN/SS
80
60
40
20
90
80
80
76
72
68
64
60
70
60
50
40
30
20
10
0
–10
–20
–30
V
= 1.4125V
2
SENSE(CM)
0
0
1
3
4
5
6
0
1
2
0
0.5
1
1.5
(V)
2
2.5
V
(V)
RUN/SS
COMMON MODE VOLTAGE (V)
V
ITH
3819 G10
3819 G11
3819 G12
SENSE Pins Total Source Current
Load Regulation
V
ITH
vs V
(Soft-Start)
RUN/SS
0.0
–0.1
–0.2
–0.3
–0.4
2.5
100
50
FCB = 0V
= 15V
V
IN
FIGURE 1
2.0
1.5
1.0
0
–50
–100
0.5
0
0
5
10
15
20
25
0
2
3
4
5
6
1
1
0
2
V
(V)
LOAD CURRENT (A)
V
COMMON MODE VOLTAGE (V)
RUN/SS
SENSE
3819 G13
3819 G14
3819 G15
Maximum Current Sense
Threshold vs Temperature
RUN/SS Current vs Temperature
Soft-Start Up (Figure 12)
80
78
76
74
72
70
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
VITH
1V/DIV
VOUT
1V/DIV
VRUN/SS
2V/DIV
100ms/DIV
3718 G18
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
125
50
75 100
TEMPERATURE (°C)
TEMPERATURE (°C)
3819 G16
3819 G17
3819f
6
LTC3819
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Constant Frequency Mode
(Figure 12)
Load Step (Figure 12)
Burst Mode Operation (Figure 12)
VIN = 12V, VOUT = 1.4125V, ILOAD = 3A
VIN = 12V, VOUT = 1.4125V, ILOAD = 3A
VIN = 12V, VOUT = 1.25V
VOUT(AC)
50mV/DIV
VOUT(AC)
50mV/DIV
VOUT(AC)
50mV/DIV
IL1
5A/DIV
IL1
5A/DIV
IL2
5A/DIV
ILOAD
10A/DIV
IL2
5A/DIV
R5, R7 = 2mΩ
R5, R7 = 2mΩ
FCB = OPEN
FCB = INTVCC
200µs/DIV
3819 G19
10µs/DIV
3819 G25
10µs/DIV
3819 G26
Oscillator Frequency
vs Temperature
Current Sense Pin Input Current
vs Temperature
EXTV Switch Resistance
CC
vs Temperature
–12
–11
–10
–9
10
8
350
300
V
= 1.4125V
OUT
V
= 2.4V
PLLFLTR
250
200
150
100
50
6
V
= 0V
PLLFLTR
4
–8
2
0
–7
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75
125
–50 –25
0
25
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
3819 G20
3819 G21
3819 G22
Undervoltage Lockout
vs Temperature
V
Shutdown Latch
RUN/SS
Thresholds vs Temperature
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
3.50
3.45
3.40
3.35
LATCH ARMING
LATCHOFF
THRESHOLD
3.30
3.25
3.20
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
125
50
75 100
TEMPERATURE (°C)
3819 G23
3819 G24
3819f
7
LTC3819
U
U
U
PI FU CTIO S
RUN/SS (Pin 1): Combination of Soft-Start, Run Control
Input and Short-Circuit Detection Timer. A capacitor to
groundatthispinsetstheramptimetofullcurrentoutput.
Forcing this pin below 0.8V causes the IC to shut down all
internal circuitry. All functions are disabled in shutdown.
SENSE1+, SENSE2+ (Pins 2,14): The (+) Input to Each
Differential Current Comparator. The ITH pin voltage and
built-in offsets between SENSE– and SENSE+ pins in
conjunction with RSENSE set the current trip threshold.
ITH (Pin 8): Error Amplifier Output and Switching Regula-
torCompensationPoint.Bothcurrentcomparator’sthresh-
oldsincreasewiththiscontrolvoltage. Thenormalvoltage
range of this pin is from 0V to 2.4V
SGND (Pin 9): Signal Ground. This pin is common to both
controllers. Route separately to the PGND pin.
V
DIFFOUT (Pin 10): Output of a Differential Amplifier. This
pin provides true remote output voltage sensing. VDIFFOUT
normally drives an external resistive divider that sets the
output voltage.
SENSE1–, SENSE2– (Pins 3,13): The (–) Input to the
Differential Current Comparators.
VOS–, VOS+ (Pins 11, 12): Inputs to an Operational Ampli-
EAIN(Pin4):Inputtotheerroramplifierthatcomparesthe
feedback voltage to the internal 0.6V reference voltage.
This pin is normally connected to a resistive divider from
the output of the differential amplifier (DIFFOUT).
fier. Internal precision resistors configure it as a differen-
tial amplifier whose output is VDIFFOUT
.
ATTENOUT (Pin 15): Voltage Feedback Signal Resistively
Divided According to the VID Programming Code.
PLLFLTR (Pin 5): The phase-locked loop’s lowpass filter
is tied to this pin. Alternatively, this pin can be driven with
an AC or DC voltage source to vary the frequency of the
internal oscillator. Do not apply voltage to this pin prior to
application of VIN.
NO_CPU (Pin 16): Open-Drain Logic Output. NO_CPU is
pulled to ground if VID0 to VID3 are all high.
VID0–VID4 (Pins 17,18, 19, 20, 21): VID Control Logic
Input Pins.
V
BIAS (Pin 22): Supply Pin for the VID Control Circuit.
PLLIN (Pin 6): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with
50kΩ. The phase-locked loop will force the rising top gate
signal of controller 1 to be synchronized with the rising
edge of the PLLIN signal.
ATTENIN (Pin 23): The Input to the VID Controlled Resis-
tive Divider.
TG2, TG1 (Pins 24, 35): High Current Gate Drives for Top
N-Channel MOSFETS. These are the outputs of floating
drivers with a voltage swing equal to INTVCC superim-
posed on the switch node voltage SW.
FCB(Pin7):ForcedContinuousControl Input. Thisinput
acts on both output stages. Pulling this pin below 0.6V
will force continuous synchronous operation. Do not
leave this pin floating without a decoupling capacitor.
3819f
8
LTC3819
U
U
U
PI FU CTIO S
SW2, SW1 (Pins 25, 34): Switch Node Connections to
Inductors. Voltage swing at these pins is from a Schottky
diode (external) voltage drop below ground to VIN.
control circuits are powered from this voltage source.
Decouple to power ground with a 1µF ceramic capacitor
placed directly adjacent to the IC and minimum of 4.7µF
additional tantalum or other low ESR capacitor.
BOOST2, BOOST1 (Pins 26, 33): Bootstrapped Supplies
totheTopsideFloatingDrivers.Externalcapacitorsarecon-
nected between the BOOST and SW pins, and Schottky
diodesareconnectedbetweentheBOOSTandINTVCC pins.
EXTVCC (Pin 30): External Power Input to an Internal
Switch. This switch closes and supplies INTVCC, bypass-
ing the internallow dropout regulator whenever EXTVCC is
higher than 4.7V. See EXTVCC Connection in the Applica-
tions Information section. Do not exceed 7V on this pin
BG2, BG1 (Pins 27, 31): High Current Gate Drives for
Bottom N-Channel MOSFETS. Voltage swing at these pins
is from ground to INTVCC.
and ensure VEXTVCC ≤ VINTVCC
.
VIN (Pin 32): Main Supply Pin. Should be closely de-
coupled to the IC’s signal ground pin.
PGND (Pin 28): Driver Power Ground. Connect to sources
ofbottomN-channelMOSFETSandthe(–)terminalsofCIN.
PGOOD (Pin 36): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on the EAIN pin is not
within ±10% of its set point.
INTVCC (Pin 29): Output of the Internal 5V Linear Low
Dropout Regulator and the EXTVCC Switch. The driver and
3819f
9
LTC3819
U
U W
FU CTIO AL DIAGRA
PLLIN
PHASE DET
f
IN
50k
PLLFLTR
INTV
V
IN
CC
R
LP
D
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
B
BOOST
TG
CLK1
C
LP
OSCILLATOR
CLK2
TO SECOND
CHANNEL
C
B
DROP
OUT
+
TOP
BOT
C
IN
D1
DET
BOT FCB
TOP ON
SW
PGOOD
S
Q
Q
–
+
0.66V
SWITCH
LOGIC
INTV
CC
R
BG
EAIN
–
+
B
C
OUT
+
–
0.54V
PGND
0.55V
–
V
OUT
V
V
OS
40k
40k
40k
SHDN
–
R
SENSE
L
1
2
–
A1
3
4
INTV
+
CC
+
I
I
2
1
OS
–
40k
–
+
+
–
+
+
+
SENSE
SENSE
30k
30k
DIFFOUT
0.86V
5V
FB
–
3V
–
+
4.5V
0.18µA
SLOPE
COMP
45k
45k
FCB
2.4V
+
–
FCB
V
FB
–
+
EA
V
EAIN
0.60V
REF
V
0.60V
0.66V
IN
OV
+
–
+
–
4.8V
5V
LDO
REG
C
C
EXTV
CC
1.2µA
I
SHDN
RST
5V
FB
TH
RUN
SOFT-
START
C
R
C2
C
INTV
CC
5V
+
6V
INTERNAL
SUPPLY
SGND
C
RUN/SS
SS
ATTENIN
5k
5-BIT VID DECODER
ATTENOUT
TYPICAL ALL
VID PINS
40k
R1
NO_CPU
VID0 VID1 VID2 VID3 VID4
V
BIAS
3819 FBD
3819f
10
LTC3819
U
(Refer to Functional Diagram)
OPERATIO
Main Control Loop
controller forces continuous PWM current mode opera-
tion. In this mode, the top and bottom MOSFETs are
alternately turned on to maintain the output voltage inde-
pendentofdirectionofinductorcurrent. WhentheFCBpin
is below VINTVCC – 2V but greater than 0.6V, the controller
enters Burst Mode operation. Burst Mode operation sets
a minimum output current level before inhibiting the top
switch and turns off the synchronous MOSFET(s) when
the inductor current goes negative. This combination of
requirements will, at low currents, force the ITH pin below
a voltage threshold that will temporarily inhibit turn-on of
both output MOSFETs until the output voltage drops.
There is 60mV of hysteresis in the burst comparator B tied
to the ITH pin. This hysteresis produces output signals to
the MOSFETs that turn them on for several cycles, fol-
lowed by a variable “sleep” interval depending upon the
load current. The resultant output voltage ripple is held to
a very small value by having the hysteretic comparator
after the error amplifier gain block.
The LTC3819 uses a constant frequency, current mode
step-down architecture with the two output stages oper-
ating 180 degrees out of phase. During normal operation,
each top MOSFET is turned on when the clock for that
channel sets the RS latch, and turned off when the main
current comparator, I1, resets the RS latch. The peak
inductor current at which I1 resets the RS latch is con-
trolled by the voltage on the ITH pin, which is the output of
error amplifier EA. The EAIN pin receives the voltage
feedback signal, which is compared to the internal refer-
ence voltage by the EA. When the load current increases,
it causes a slight decrease in VEAIN relative to the 0.6V
reference, which in turn causes the ITH voltage to increase
until the average inductor current matches the new load
current. After the top MOSFET has turned off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by current comparator I2, or
the beginning of the next cycle.
The top MOSFET drivers are biased from floating boot-
strap capacitor CB, which normally is recharged during
each off cycle through an external diode when the top
MOSFET turns off. As VIN decreases to a voltage close to
VOUT, the loop may enter dropout and attempt to turn on
the top MOSFET continuously. The dropout detector de-
tects this and forces the top MOSFET off for about 500ns
every tenth cycle to allow CB to recharge.
Constant Frequency Operation
When the FCB pin is tied to INTVCC, Burst Mode operation
is disabled and a forced minimum peak output current
requirementisremoved.Thisprovidesconstantfrequency,
discontinuous (preventing reverse inductor current) cur-
rent operation over the widest possible output current
range.Thisconstantfrequencyoperationisnotasefficient
as Burst Mode operation, but does provide a lower noise,
constant frequency operating mode down to approxi-
mately 1% of designed maximum output current.
The main control loop is shut down by pulling the RUN/
SS pin low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1.5V, the main control loop is enabled with
the ITH voltage clamped at approximately 30% of its
maximum value. As CSS continues to charge, the ITH pin
voltageisgraduallyreleasedallowingnormal,full-current
operation.
Continuous Current (PWM) Operation
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be
forced back into the main power supply potentially boost-
ing the input supply to dangerous voltage levels—
BEWARE!
Low Current Operation
T
he FCB pin selects between two modes of low current
operation. When the FCB pin voltage is below 0.6V, the
3819f
11
LTC3819
U
(Refer to Functional Diagram)
OPERATIO
Frequency Synchronization
output RMS current typically up to 25mA. The amplifier
is not capable of sinking current and therefore must be
resistively loaded to do so.
The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
DC frequency control input of the oscillator that operates
over a 140kHz to 310kHz range corresponding to a DC
voltageinputfrom0Vto2.4V.Whenlocked,thePLLaligns
the turn on of the top MOSFET to the rising edge of the
synchronizingsignal.WhenPLLINisleftopen,thePLLFLTR
pingoeslow,forcingtheoscillatortominimumfrequency.
Output Overvoltage Protection
An overvoltage comparator, 0V, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFETisturnedoffandthebottomMOSFETisturnedon
until the overvoltage condition is cleared.
InputcapacitanceESRrequirementsandefficiencylosses
are substantially reduced because the peak current drawn
from the input capacitor is effectively divided by two and
power loss is proportional to the RMS current squared. A
two stage, single output voltage implementation can
reduce input path power loss by 75% and radically reduce
the required RMS current rating of the input capacitor(s).
Power Good (PGOOD)
The PGOOD pin is connected to the drain of an internal
MOSFET. The MOSFET turns on when the output voltage
is not within ±10% of its nominal output level as deter-
mined by the feedback divider. When the output is within
±10%ofitsnominalvalue,theMOSFETisturnedoffwithin
10µs and the PGOOD pin should be pulled up by an
external resistor to a source of up to 7V.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
of the IC circuitry is derived from INTVCC. When the
EXTVCC pin is left open, an internal 5V low dropout
regulator supplies INTVCC power. If the EXTVCC pin is
taken above 4.8V, the 5V regulator is turned off and an
internalswitchisturnedonconnectingEXTVCC toINTVCC.
This allows the INTVCC power to be derived from a high
efficiency external source such as the output of the regu-
lator itself or a secondary winding, as described in the
Applications Information section. An external Schottky
diode can be used to minimize the voltage drop from
EXTVCC to INTVCC in applications requiring greater than
the specified INTVCC current. Voltages up to 7V can be
applied to EXTVCC for additional gate drive capability.
Short-Circuit Detection
The RUN/SS capacitor is used initially to limit the inrush
current from the input power source. Once the control-
lershavebeengiventime, asdeterminedbythecapacitor
on the RUN/SS pin, to charge up the output capacitors
and provide full-load current, the RUN/SS capacitor is
then used as a short-circuit timeout circuit. If the output
voltage falls to less than 70% of its nominal output
voltage the RUN/SS capacitor begins discharging as-
suming that the output is in a severe overcurrent and/or
short-circuit condition. If the condition lasts for a long
enough period as determined by the size of the RUN/SS
capacitor, the controller will be shut down until the
RUN/SS pin voltage is recycled. This built-in latchoff can
be overidden by providing a current >5µA at a compli-
ance of 5V to the RUN/SS pin. This current shortens the
soft-start period but also prevents net discharge of the
RUN/SS capacitor during a severe overcurrent and/or
short-circuit condition. Foldback current limiting is acti-
vated when the output voltage falls below 70% of its
nominal level whether or not the short-circuit latchoff
circuit is enabled.
Differential Amplifier
This controller includes a true unity-gain differential am-
+
–
plifier. Sensing both VOUT and VOUT benefits regu-
lation in high current applications and/or applications
having electrical interconnection losses. The amplifier is
aunity-gainstable,2MHzgain-bandwidth,>120dBopen-
loop gain design. The amplifier has an output slew rate of
5V/µs and is capable of driving capacitive loads with an
3819f
12
LTC3819
U
W U U
APPLICATIO S I FOR ATIO
The basic LTC3819 application circuit is shown in
Figure 1 on the first page. External component selection
begins with the selection of the inductors based on ripple
current requirements and continues with the current
sensing resistors using the calculated peak inductor
current and/or maximum current limit. Next, the power
MOSFETs, D1 and D2 are selected. The operating fre-
quency and the inductor are chosen based mainly on the
amount of ripple current. Finally, CIN is selected for its
ability to handle the input ripple current (that PolyPhaseTM
operationminimizes)andCOUT ischosenwithlowenough
ESR to meet the output ripple voltage and load step
specifications (also minimized with PolyPhase). Current
mode architecture provides inherent current sharing be-
tween output stages. The circuit shown in Figure 1 can be
configured for operation up to an input voltage of 28V
(limited by the external MOSFETs). Current mode control
allows the ability to connect the two output stages to two
differentinputpowersupplyrails.Aheavyoutputloadcan
take some power from each input supply according to the
selection of the RSENSE resistors.
plus an additional current which is proportional to the
voltage applied to the PLLFLTR pin. Refer to Phase-
Locked Loop and Frequency Synchronization for addi-
tional information.
A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 2. As the operating frequency
isincreasedthegatechargelosseswillbehigher,reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 310kHz.
2.5
2.0
1.5
1.0
0.5
0
120
170
220
270
320
OPERATING FREQUENCY (kHz)
3819 F02
RSENSE Selection For Output Current
Figure 2. Operating Frequency vs V
PLLFLTR
RSENSE1,2 are chosen based on the required peak output
current. The LTC3819 current comparator has a maxi-
mum threshold of 75mV/RSENSE and an input common
mode range of SGND to 1.1(INTVCC). The current com-
parator threshold sets the peak inductor current, yielding
a maximum average output current IMAX equal to the peak
value less half the peak-to-peak ripple current, ∆IL.
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
MOSFET gate charge and transition losses increase
directly with frequency. In addition to this basic tradeoff,
the effect of inductor value on ripple current and low
currentoperationmustalsobeconsidered.ThePolyPhase
approach reduces both input and output ripple currents
while optimizing individual output stages to run at a lower
fundamental frequency, enhancing efficiency.
Assuming a common input power source for each output
stage and allowing a margin for variations in the
LTC3819 and external component values yields:
50mV
RSENSE = N
IMAX
where N = 2 for 2 phase. For more than 2 phase use the
LTC1629-6 plus the LTC3819.
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆IL per individual section, N,
decreases with higher inductance or frequency and
Operating Frequency
The LTC3819 uses a constant frequency, phase-lockable
architecturewiththefrequencydeterminedbyaninternal
capacitor. This capacitor is charged by a fixed current
increases with higher VIN or VOUT
:
PolyPhase is a registered trademark of Linear Technology Corporation.
3819f
13
LTC3819
APPLICATIO S I FOR ATIO
U
W U U
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ® cores. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductor type selected. As
inductance increases, core losses go down. Unfortu-
nately, increased inductance requires more turns of wire
and therefore copper losses will increase.
⎛
⎞
VOUT
f •L
VOUT
V
IN
∆IL =
1−
⎜
⎟
⎝
⎠
where f is the individual output stage operating frequency.
In a 2-phase converter, the net ripple current seen by the
output capacitor is much smaller than the individual
inductor ripple currents due to ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Figure 3 shows the net ripple current seen by the output
capacitors for 1- and 2-phase configurations. The output
ripple current is plotted for a fixed output voltage as the
duty factor is varied between 10% and 90% on the x-axis.
The output ripple current is normalized against the induc-
tor ripple current at zero duty factor. The graph can be
used in place of tedious calculations, simplifying the
design process.
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space effi-
cient, especially when you can use several layers of wire.
Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
1.0
1-PHASE
2-PHASE
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Power MOSFET, D1 and D2 Selection
Two external power MOSFETs must be selected for each
output stage with the LTC3819: one N-channel MOSFET
for the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY FACTOR (V /V
)
OUT IN
3819 F03
Figure 3. Normalized Output Ripple Current
vs Duty Factor [I ≈ 0.3 (∆I )]
The peak-to-peak drive levels are set by the INTVCC
voltage. This voltage is typically 5V during start-up
(see EXTVCC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(VIN < 5V); then, sublogic-level threshold MOSFETs
(VGS(TH) < 1V) should be used. Pay close attention to the
BVDSS specification for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less.
RMS
O(P–P)
Accepting larger values of ∆IL allows the use of low
inductances, butcanresultinhigheroutputvoltageripple.
A reasonable starting point for setting ripple current is
∆IL = 0.4(IOUT)/2, where IOUT is the total load current.
Remember, the maximum ∆IL occurs at the maximum
input voltage. The individual inductor ripple currents are
determined by the inductor, input and output voltages.
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
Inductor Core Selection
resistance RDS(ON), reverse transfer capacitance CRSS
,
Once the values for L1 and L2 are known, the type of
inductor must be selected. High efficiency converters
input voltage and maximum output current. When the
3819f
14
LTC3819
U
W U U
APPLICATIO S I FOR ATIO
LTC3819isoperatingincontinuousmodethedutyfactors
for the top and bottom MOSFETs of each output stage are
given by:
The Schottky diodes, D1 and D2 shown in Figure 1
conduct during the dead-time between the conduction of
the two large power MOSFETs. This helps prevent the
body diode of the bottom MOSFET from turning on,
storing charge during the dead-time, and requiring a
reverse recovery period which would reduce efficiency. A
1A to 3A Schottky (depending on output current) diode is
generally a good compromise for both regions of opera-
tion due to the relatively small average current. Larger
diodes result in additional transition losses due to their
larger junction capacitance.
VOUT
V
IN
Main SwitchDuty Cycle =
⎛
⎞
V – VOUT
IN
Synchronous SwitchDuty Cycle =
⎜
⎟
V
IN
⎝
⎠
The MOSFET power dissipations at maximum output
current are given by:
CIN and COUT Selection
2
In continuous mode, the source current of each top
⎛
⎞
VOUT IMAX
N-channel MOSFET is a square wave of duty cycle VOUT
/
PMAIN
=
1+ δ RDS(ON)
+
(
)
⎜
⎟
V
IN
2
⎝
⎠
VIN. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a closed form
equation can be found in Application Note 77. Figure 4
shows the input capacitor ripple current for a 2-phase
configuration with the output voltage fixed and input
voltage varied. The input ripple current is normalized
against the DC output current. The graph can be used in
place of tedious calculations. The minimum input ripple
currentcanbeachievedwhentheinputvoltageistwicethe
output voltage.
2⎛
⎞
IMAX
2
k V
CRSS
f
(
IN
)
(
)( )
⎜
⎟
⎝
⎠
2
⎛
⎞
V – VOUT IMAX
IN
P
SYNC
=
1+ δ RDS(ON)
(
)
⎜
⎟
V
2
⎝
⎠
IN
where δ is the temperature dependency of RDS(ON) and k
is a constant inversely related to the gate drive current.
In the graph of Figure 4, the 2-phase local maximum input
RMS capacitor currents are reached when:
Both MOSFETs have I2R losses but the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 20V the
high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increasetothepointthattheuseofahigherRDS(ON)device
with lower CRSS actual provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.
VOUT 2k − 1
=
V
IN
4
where k = 1, 2
These worst-case conditions are commonly used for
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
currentratingsareoftenbasedononly2000hoursoflife.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the capacitor manufacturer if there is any
question.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. CRSS is usually specified in the
MOSFET characteristics. The constant k = 1.7 can be
used to estimate the contributions of the two terms in the
main switch dissipation equation.
3819f
15
LTC3819
U
W U U
APPLICATIO S I FOR ATIO
0.6
COUT required ESR < 4(RSENSE) and
COUT > 1/(16f)(RSENSE
0.5
)
0.4
The emergence of very low ESR capacitors in small,
surface mount packages makes very physically small
implementations possible. The ability to externally com-
pensate the switching regulator loop using the ITH
pin(OPTI-LOOP compensation) allows a much wider se-
lection of output capacitor types. OPTI-LOOP compensa-
tion effectively removes constraints on output capacitor
ESR. The impedance characteristics of each capacitor
type are significantly different than an ideal capacitor and
therefore require accurate modeling or bench evaluation
during design.
1-PHASE
2-PHASE
0.3
0.2
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
DUTY FACTOR (V /V
)
OUT IN
3819 F04
Figure 4. Normalized RMS Input Ripple Current
vs Duty Factor for 1 and 2 Output Stages
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
dielectriccapacitoravailablefromSanyoandthePanasonic
SP surface mount types have the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON type capacitors is recommended to reduce
the inductance effects.
It is important to note that the efficiency loss is propor-
tional to the input RMS current squared and therefore a
2-phase implementation results in 75% less power loss
when compared to a single phase design. Battery/input
protection fuse resistance (if used), PC board trace and
connector resistance losses are also reduced by the
reduction of the input ripple current in a 2-phase system.
The required amount of input capacitance is further
reduced by the factor, 2, due to the effective increase in
the frequency of the current pulses.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum elec-
trolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer sur-
face mount capacitors offer very low ESR also but have
muchlowercapacitivedensityperunitvolume. Inthecase
oftantalum,itiscriticalthatthecapacitorsaresurgetested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV or the KEMET T510
seriesofsurfacemounttantalums,availableincaseheights
ranging from 2mm to 4mm. Other capacitor types include
Sanyo OS-CON, POSCAPs, Panasonic SP caps, Nichicon
PL series and Sprague 595D series. Consult the manufac-
turer for other specific recommendations. A combination
of capacitors will often result in maximizing performance
and minimizing overall cost and size.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment has been met, the RMS current rating generally far
exceeds the IRIPPLE(P-P) requirements. The steady state
output ripple (∆VOUT) is determined by:
⎛
⎞
1
∆VOUT ≈ ∆IRIPPLE ESR +
⎜
⎟
16fCOUT
⎝
⎠
Where f = operating frequency of each stage, COUT
=
output capacitance and ∆IRIPPLE = combined inductor
ripple currents.
The output ripple varies with input voltage since ∆IL is a
functionofinputvoltage.Theoutputripplewillbelessthan
50mV at max VIN with ∆IL = 0.4IOUT(MAX)/2 assuming:
3819f
16
LTC3819
U
W U U
APPLICATIO S I FOR ATIO
INTVCC Regulator
When the voltage applied to EXTVCC rises above 4.7V, the
internal regulator is turned off and an internal switch
closes, connecting the EXTVCC pin to the INTVCC pin
therebysupplyinginternalandMOSFETgatedrivingpower
to the IC. The switch remains closed as long as the voltage
applied to EXTVCC remains above 4.5V. This allows the
MOSFET driver and control power to be derived from a
separate 5V supply during normal operation (4.7V <
An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. The INTVCC
regulator powers the drivers and internal circuitry of the
LTC3819.TheINTVCC pinregulatorcansupplyupto50mA
peak and must be bypassed to power ground with a
minimum of 4.7µF tantalum or electrolytic capacitor. An
additional 1µF ceramic capacitor placed very close to the
IC is recommended due to the extremely high instanta-
neous currents required by the MOSFET gate drivers.
V
EXTVCC < 7V) and from the internal regulator when the
external 5V supply is not available. Do not apply greater
than 7V to the EXTVCC pin and ensure that EXTVCC < VIN +
0.3V when using the application circuits shown. If an
external voltage source is applied to the EXTVCC pin when
the VIN supply is not present, a diode can be placed in
series with the LTC3819’s VIN pin and a Schottky diode
between the EXTVCC and the VIN pin, to prevent current
from backfeeding VIN.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3819 to be
exceeded. The supply current is dominated by the gate
charge supply current, in addition to the current drawn
from the differential amplifier output. The gate charge is
dependent on operating frequency as discussed in the
Efficiency Considerations section. The supply current can
either be supplied by the internal 5V regulator or via the
EXTVCC pin. When the voltage applied to the EXTVCC pin
is less than 4.7V, all of the INTVCC load current is supplied
by the internal 5V linear regulator. Power dissipation for
the IC is higher in this case by (IIN)(VIN – INTVCC) and
efficiency is lowered. The junction temperature can be
estimated by using the equations given in Note 1 of the
Electrical Characteristics. For example, the LTC3819 VIN
current is limited to less than 24mA from a 24V supply:
Topside MOSFET Driver Supply (CB,DB) (Refer to
Functional Diagram)
External bootstrap capacitors CB1 and CB2 connected to
the BOOST1 and BOOST2 pins supply the gate drive
voltages for the topside MOSFETs. Capacitor CB in the
Functional Diagram is charged though diode DB from
INTVCC whentheSWpinislow.WhenthetopsideMOSFET
turns on, the driver places the CB voltage across the gate-
sourceofthedesiredMOSFET.ThisenhancestheMOSFET
and turns on the topside switch. The switch node voltage,
TJ = 70°C + (24mA)(24V)(85°C/W) = 119°C
UseoftheEXTVCCpinreducesthejunctiontemperature to:
TJ = 70°C + (24mA)(5V)(85°C/W) = 80.2°C
SW, rises to VIN and the BOOST pin rises to VIN + VINTVCC.
The value of the boost capacitor CB needs to be 30 to 100
times that of the total input capacitance of the topside
MOSFET(s). ThereversebreakdownofDB mustbegreater
than VIN(MAX).
The input supply current should be measured while the
controller is operating in continuous mode at maximum
VIN and the power dissipation calculated in order to
prevent the maximum junction temperature from being
exceeded.
The final arbiter when defining the best gate drive ampli-
tude level will be the input supply current. If a change is
made that decreases input current, the efficiency has
improved. If the input current does not change then the
efficiency has not changed either.
EXTVCC Connection
The LTC3819 contains an internal P-channel MOSFET
switch connected between the EXTVCC and INTVCC pins.
3819f
17
LTC3819
U
W U U
APPLICATIO S I FOR ATIO
Output Voltage
Table 1. VID Output Voltage Programming
CODE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
VID4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
VID3
GND
GND
GND
GND
GND
GND
GND
GND
Float
Float
Float
Float
Float
Float
Float
Float
GND
GND
GND
GND
GND
GND
GND
GND
Float
Float
Float
Float
Float
Float
Float
Float
VID2
GND
GND
GND
GND
Float
Float
Float
Float
GND
GND
GND
GND
Float
Float
Float
Float
GND
GND
GND
GND
Float
Float
Float
Float
GND
GND
GND
GND
Float
Float
Float
Float
VID1
GND
GND
Float
Float
GND
GND
Float
Float
GND
GND
Float
Float
GND
GND
Float
Float
GND
GND
Float
Float
GND
GND
Float
Float
GND
GND
Float
Float
GND
GND
Float
Float
VID0
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
GND
Float
OUTPUT
1.4125V
1.4000V
1.3875V
1.3750V
1.3625V
1.3500V
1.3375V
1.3250V
1.3125V
1.3000V
1.2875V
1.2750V
1.2625V
1.2500V
1.2375V
1.2250V
1.2125V
1.2000V
1.1875V
1.1750V
1.1625V
1.1500V
1.1375V
1.1250V
1.1125V
1.1000V
1.0875V
1.0750V
1.0625V
1.0500V
1.0375V
1.0250V
The LTC3819 has a true remote voltage sense capablity.
The sensing connections should be returned from the load
back to the differential amplifier’s inputs through a com-
mon, tightly coupled pair of PC traces. The differential
amplifier corrects for DC drops in both the power and
ground paths. The differential amplifier output signal is
divided down and compared with the internal precision
0.6V voltage reference by the error amplifier.
Output Voltage Programming
The output voltage is digitally programmed as defined in
Table 1 using the VID0 to VID4 logic input pins. The VID
logic inputs program a precision, 0.25% internal feedback
resistivedivider.TheLTC3819hasanoutputvoltagerange
of 1.025V to 1.4125V in 12.5mV steps.
Between the ATTENOUT pin and ground is a variable
resistor,R1,whosevalueiscontrolledbythefiveVIDinput
pins (VID0 to VID4). Another resistor, R2, between the
ATTENIN and the ATTENOUT pins completes the resistive
divider. The output voltage is thus set by the ratio of
(R1 + R2) to R1.
EachVIDdigitalinputispulledupbya40kresistorinseries
with a diode from VBIAS. Therefore, it must be grounded to
get a digital low input, and can be either floated or con-
nected to VBIAS to get a digital high input. The series diode
is used to prevent the digital inputs from being damaged
or clamped if they are driven higher than VBIAS. The digital
inputs accept CMOS voltage levels.
VBIAS is the supply voltage for the VID section. It is
normally connected to INTVCC but can be driven from
other sources. If it is driven from another source, that
source must be in the range of 2.7V to 5.5V and must be
alive prior to enabling the LTC3819.
3819f
18
LTC3819
U
W U U
APPLICATIO S I FOR ATIO
Soft-Start/Run Function
V
INTV
CC
IN
3.3V OR 5V
RUN/SS
R
*
R *
SS
SS
The RUN/SS pin provides three functions: 1) Run/Shut-
down,2)soft-startand3)adefeatableshort-circuitlatchoff
timer. Soft-start reduces the input power sources’ surge
currents by gradually increasing the controller’s current
limit ITH(MAX). The latchoff timer prevents very short,
extreme load transients from tripping the overcurrent
latch. A small pull-up current (>5µA) supplied to the RUN/
SS pin will prevent the overcurrent latch from operating.
The following explanation describes how the functions
operate.
D1
RUN/SS
D1*
C
SS
C
SS
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
3719 F05
Figure 5. RUN/SS Pin Interfacing
Fault Conditions: Overcurrent Latchoff
An internal 1.2µA current source charges up the soft-start
capacitor, CSS. When the voltage on RUN/SS reaches
1.5V, the controller is permitted to start operating. As the
voltage on RUN/SS increases from 1.5V to 3.0V, the
internal current limit is increased from 25mV/RSENSE to
75mV/RSENSE. The output current limit ramps up slowly,
taking an additional 1.4s/µF to reach full current. The
outputcurrentthusrampsupslowly,reducingthestarting
surge current required from the input power supply. If
RUN/SS has been pulled all the way to ground there is a
delay before starting of approximately:
The RUN/SS pin also provides the ability to latch off the
controllerswhenanovercurrentconditionisdetected.The
RUN/SS capacitor, CSS, is used initially to limit the inrush
current of both controllers. After the controllers have been
started and been given adequate time to charge up the
output capacitors and provide full load current, the RUN/
SS capacitor is used for a short-circuit timer. If the output
voltagefallstolessthan70%ofitsnominalvalueafterCSS
reaches 4.1V, CSS begins discharging on the assumption
that the output is in an overcurrent condition. If the
condition lasts for a long enough period as determined by
thesizeoftheCSS,thecontrollerwillbeshutdownuntilthe
RUN/SS pin voltage is recycled. If the overload occurs
during start-up, the time can be approximated by:
1.5V
1.2µA
tDELAY
=
CSS = 1.25s/µF CSS
(
)
tLO1 ≈ (CSS • 0.6V)/(1.2µA) = 5 • 105 (CSS)
The time for the output current to ramp up is then:
Iftheoverloadoccursafterstart-up,thevoltageonCSS will
continue charging and will provide additional time before
latching off:
3V − 1.5V
1.2µA
t
=
CSS = 1.25s/µF CSS
IRAMP
(
)
tLO2 ≈ (CSS • 3V)/(1.2µA) = 2.5 • 106 (CSS)
BypullingtheRUN/SSpinbelow0.8VtheLTC3819isput
into low current shutdown (IQ < 40µA). The RUN/SS pins
can be driven directly from logic as shown in Figure 5.
Diode D1 in Figure 5 reduces the start delay but allows
SS to ramp up slowly providing the soft-start function.
The RUN/SS pin has an internal 6V zener clamp (see
Functional Diagram).
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, RSS, to the RUN/SS pin as
showninFigure5. Thisresistanceshortensthesoft-start
period and prevents the discharge of the RUN/SS capaci-
tor during a severe overcurrent and/or short-circuit
C
3819f
19
LTC3819
U
W U U
APPLICATIO S I FOR ATIO
condition. When deriving the 5µA current from VIN as in
the figure, current latchoff is always defeated. The diode
connecting this pull-up resistor to INTVCC, as in Figure 5,
eliminates any extra supply current during shutdown
while eliminating the INTVCC loading from preventing
controller start-up.
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆fH, is equal to the capture range, ∆fC:
∆fH = ∆fC = ±0.5 fO (150kHz-300kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 6.
Why should you defeat current latchoff? During the
prototypingstageofadesign,theremaybeaproblemwith
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is com-
plete whether to rely solely on foldback current limiting or
to enable the latchoff feature by removing the pull-up
resistor.
2.4V
R
LP
10k
PHASE
DETECTOR
C
LP
EXTERNAL
OSC
PLLFLTR
PLLIN
DIGITAL
PHASE/
OSC
FREQUENCY
DETECTOR
50k
The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
3719 F06
CSS > (COUT )(VOUT)(10-4)(RSENSE
)
Figure 6. Phase-Locked Loop Block Diagram
The minimum recommended soft-start capacitor of CSS
0.1µF will be sufficient for most applications.
=
If the external frequency (fPLLIN) is greater than the oscil-
lator frequency f0SC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f0SC, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre-
quencies are the same but exhibit a phase difference, the
currentsourcesturnonforanamountoftimecorrespond-
ing to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor CLP holds the voltage. The
LTC3819 PLLIN pin must be driven from a low impedance
source such as a logic gate located close to the pin.
Phase-Locked Loop and Frequency Synchronization
The LTC3819 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the
center frequency fO. A voltage applied to the PLLFLTR pin
of 1.2V corresponds to a frequency of approximately
220kHz. The nominal operating frequency range of the
LTC3819 is 140kHz to 310kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
3819f
20
LTC3819
U
W U U
APPLICATIO S I FOR ATIO
The loop filter components (CLP, RLP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP =10k and CLP is 0.01µF to
0.1µF.
FCB Pin Operation
The following table summarizes the possible states avail-
able on the FCB pin:
Table 2
FCB Pin
Condition
0V to 0.55V
Forced Continuous (Current Reversal
Allowed—Burst Inhibited)
Minimum On-Time Considerations
0.65V < V < 4.3V (typ)
Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
FCB
Minimum on-time, tON(MIN), is the smallest time duration
thattheLTC3819iscapableofturningonthetopMOSFET.
It is determined by internal timing delays and the gate
chargerequiredtoturnonthetopMOSFET.Lowdutycycle
applications may approach this minimum on-time limit
and care should be taken to ensure that:
>4.8V
Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
Active Voltage Positioning
VOUT
tON MIN
<
Active voltage positioning can be used to minimize peak-
to-peak output voltage excursion under worst-case tran-
sient loading conditions. The open-loop DC gain of the
control loop is reduced depending upon the maximum
load step specifications. Active voltage positioning can
easily be added to the LTC3819 by loading the ITH pin with
a resistive divider having a Thevenin equivalent voltage
sourceequaltothemidpointoperatingvoltageoftheerror
amplifier, or 1.2V (see Figure 7).
(
)
V f
IN( )
Ifthedutycyclefallsbelowwhatcanbeaccommodatedby
the minimum on-time, the LTC3819 will begin to skip
cycles resulting in variable frequency operation. The out-
put voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the LTC3819 is generally less
than 200ns. However, as the peak sense voltage de-
creases,theminimumon-timegraduallyincreases.Thisis
of particular concern in forced continuous applications
withlowripplecurrentatlightloads.Ifthedutycycledrops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger ripple current and voltage ripple.
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
worst-case peak-to-peak output voltage deviation due to
transient loading can theoretically be reduced to half or
alternatively the amount of output capacitance can
be reduced for a particular application. A complete
explanation is included in Design Solutions 10 or the
LTC1736 data sheet. (See www.linear-tech.com)
If an application can operate close to the minimum
on-time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement. As a general
rule, keep the inductor ripple current of each phase equal
INTV
CC
R
R
T2
T1
I
TH
LTC3819
R
C
to or greater than 15% of IOUT(MAX) at VIN(MAX)
.
C
C
3719 F07
Figure 7. Active Voltage Positioning Applied to the LTC3819
3819f
21
LTC3819
U
W U U
APPLICATIO S I FOR ATIO
quadrupling the importance of loss terms in the switching
regulator system!
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
2) Transition losses apply only to the topside MOSFET(s),
and are significant only when operating at high input
voltages (typically 12V or greater). Transition losses can
be estimated from:
⎛
⎞
IO(MAX)
2
%Efficiency = 100% – (L1 + L2 + L3 + ...)
Transition Loss = (1.7)VIN
CRSS f
⎜
⎟
2
⎝
⎠
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
3) INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTVCC to
ground. The resulting dQ/dt is a current out of INTVCC that
is typically much larger than the control circuit current. In
continuous mode, IGATECHG = (QT + QB), where QT and QB
are the gate charges of the topside and bottom side
MOSFETs.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3819 circuits: 1) I2R losses, 2) Topside
MOSFET transition losses, 3) INTVCC regulator current
and 4) LTC3819 VIN current (including loading on the
differential amplifier output).
1) I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
SupplyingINTVCC powerthroughtheEXTVCC switchinput
from an output-derived source will scale the VIN current
required for the driver and control circuits by the ratio
(Duty Factor)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTVCC current results in approxi-
mately 3mA of VIN current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from VIN) to only a few percent.
the average output current flows through L and RSENSE
,
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same RDS(ON), then the resistance of one
MOSFET can simply be summed with the resistances of L,
RSENSE and ESR to obtain I2R losses. For example, if each
RDS(ON)=10mΩ, RL=10mΩ, andRSENSE =5mΩ, thenthe
total resistance is 25mΩ. This results in losses ranging
from 2% to 8% as the output current increases from 3A to
15A per output stage for a 5V output, or a 3% to 12% loss
per output stage for a 3.3V output. Efficiency varies as the
inverse square of VOUT for the same external components
and output power level. The combined effects of increas-
ingly lower output voltages and higher currents required
by high performance digital systems is not doubling but
4) The VIN current has two components: the first is the
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control cur-
rents; the second is the current drawn from the differential
amplifier output. VIN current typically results in a small
(<0.1%) loss.
3819f
22
LTC3819
U
W U U
APPLICATIO S I FOR ATIO
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10%efficiencydegradationinportablesystems.Itisvery
important to include these “system” level losses in the
design of a system. The internal battery and input fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and a very low ESR at
the switching frequency. A 50W supply will typically
require a minimum of 200µF to 300µF of output capaci-
tance having a maximum of 10mΩ to 20mΩ of ESR. The
LTC3819 2-phase architecture typically halves the input
and output capacitance requirements over competing
solutions. Other losses including Schottky conduction
losses during dead-time and inductor core losses gener-
ally account for less than 2% total additional loss.
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin. The ITH external components
shown in the Figure 1 circuit will provide an adequate
starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be decided
upon first because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of <2µs will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. The initial output voltage step resulting
from the step change in output current may not be within
the bandwidth of the feedback loop, so this signal cannot
be used to determine phase margin. This is why it is
better to look at the Ith pin signal which is in the feedback
loop and is the filtered and compensated control loop
response. The gain of the loop will be increased by
increasing RC and the bandwidth of the loop will be
increased by decreasing CC. If RC is increased by the
same factor that CC is decreased, the zero frequency will
be kept the same, thereby keeping the phase the same in
the most critical frequency range of the feedback loop.
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD(ESR), where ESR is the effective
seriesresistanceofCOUT(∆ILOAD)alsobeginstochargeor
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time, and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
3819f
23
LTC3819
W U U
U
APPLICATIO S I FOR ATIO
Design Example
1.2V
5.5V
Asadesignexample,assumeVIN=5V(nominal),VIN = 5.5V
(max), VOUT =1.2V, IMAX =20A, TA =70°Candf = 300kHz.
PMAIN
=
10 2 1+ 0.005 110°C − 25°C
( )
(
)(
)
]
[
2
0.013Ω + 1.7 5.5V 10A 300pF
Theinductancevalueischosenfirstbasedona30%ripple
current assumption. The highest value of ripple current
occursatthemaximuminputvoltage.TietheFREQSETpin
to the INTVCC pin for 300kHz operation. The minimum
inductance for 30% ripple current is:
(
) (
)(
)
300kHz = 0.45W
(
)
The worst-case power disipated by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem-
perature rise is:
⎛
⎞
VOUT
VOUT
V
IN
L ≥
1−
⎜
⎟
⎝
⎠
f ∆L
2
5.5V − 1.2V
5.5V
= 1.5W
(
)
P
SYNC
=
2 10A 1.48 0.013Ω
(
) (
)(
)
⎛
⎞
1.2V
1.2V
5.5V
≥
1−
⎜
⎟
⎝
⎠
300kHz 30% 10A
(
)(
)(
)
Ashort-circuittogroundwillresultinafoldedbackcurrent
of about:
≥ 1.04µH
A 1µH inductor will produce 31% ripple current. The peak
inductor current will be the maximum DC value plus one
half the ripple current, or 11.5A. The minimum on-time
occurs at maximum VIN:
⎡
⎢
⎤
⎥
200ns 5.5V
(
)
25mV
0.004Ω
1
2
ISC
=
+
= 6.8A
⎢
⎣
⎥
⎦
1µH
The worst-case power disipated by the synchronous
MOSFET under short-circuit conditions at elevated ambi-
ent temperature and estimated 50°C junction temperature
rise is:
VOUT
V f
IN
1.2V
tON MIN
=
=
= 0.73µs
(
)
5.5V 300kHz
(
)(
)
The RSENSE resistors value can be calculated by using the
maximum current sense voltage specification with some
accomodation for tolerances:
2
5.5V − 1.2V
5.5V
= 696mW
P
SYNC
=
6.8A 1.48 0.013Ω
(
) (
)(
)
50mV
11.5A
RSENSE
=
≈ 0.004Ω
which is less than normal, full-load conditions. Inciden-
tally, since the load no longer dissipates power in the
shorted condition, total system power dissipation is de-
creased by over 99%.
The power dissipation on the topside MOSFET can be
easily estimated. Using a Siliconix Si4420DY for example;
RDS(ON) = 0.013Ω, CRSS = 300pF. At maximum input
voltagewithTJ(estimated)=110°Catanelevatedambient
temperature:
The duty factor for this application is:
VO 1.2V
DF =
=
= 0.24
V
5V
IN
3819f
24
LTC3819
U
W U U
APPLICATIO S I FOR ATIO
Using Figure 4, the RMS ripple current will be:
ground joins the power ground plane beside Pin 28. It is
recommendedthatthePin28returntothe(–)platesofCIN.
IINRMS = (20A)(0.25) = 5ARMS
+
2) Does the LTC3819 VOS pin connect to the point of
An input capacitor(s) with a 5ARMS ripple current rating is
required.
–
load? Does the LTC3819 VOS pin connect to the load
return?
The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
and multiplying by the factor obtained from Figure 3
along with the calculated duty factor. The output ripple in
continuous mode will be highest at the maximum input
voltage since the duty factor is <50%. The maximum
output current ripple is:
3)AretheSENSE– andSENSE+ leadsroutedtogetherwith
minimum PC trace spacing? The filter capacitors between
SENSE+ and SENSE– pin pairs should be as close as
possible to the LTC3819. Ensure accurate current sensing
with Kelvin connections at the current sense resistor. See
Figure 8.
4) Does the (+) plate of CIN connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the AC current to the MOSFETs. Keep the input
currentpathformedbytheinputcapacitor,topandbottom
MOSFETs, and the Schottky diode on the same side of the
PC board in a tight loop to minimize conducted and
radiated EMI.
VOUT
fL
∆ICOUT
=
0.5 at 24%D F
(
)
1.2V
∆ICOUTMAX
=
0.5
300kHz 1.0µH
(
)(
)
= 2AP-P
5) Is the INTVCC 1µF ceramic decoupling capacitor con-
nected closely between INTVCC and the PGND pin? This
capacitor carries the MOSFET driver peak currents. A
small value is recommended to allow placement immedi-
ately adjacent to the IC.
VOUTRIPPLE = 20mΩ 2AP-P = 40mVP-P
(
)
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3819. Check the following in your layout:
6) Keep the switching nodes, SW1 (SW2), away from
sensitive small-signal nodes. Ideally the switch nodes
should be placed at the furthest point from the
LTC3819.
1) Are the signal and power grounds separate? The signal
ground traces should return to Pin 9 first. Connect Pin 9
toPin28throughawideandstraighttrace. Thenthesignal
7)Usealowimpedancesourcesuchasalogicgatetodrive
the PLLIN pin and keep the lead as short as possible.
PADS OF SENSE RESISTOR
TRACE TO OUTPUT CAP (+)
TRACE TO INDUCTOR
3819 F09
+
–
SENSE
SENSE
Figure 8. Proper Current Sense Connections
3819f
25
LTC3819
APPLICATIO S I FOR ATIO
U
W
U U
of the input capacitor(s) with a short isolated PC trace
since very high switched currents are present. A separate
isolated path from the negative plate(s) of the input
capacitor(s) should be used to tie in the IC power ground
pin (PGND) and the signal ground pin (SGND). This
technique keeps inherent signals generated by high cur-
rent pulses from taking alternate current paths that have
finite impedances during the total period of the switching
regulator.ExternalOPTI-LOOPcompensationallowsover-
compensation for PC layouts which are not optimized but
this is not the recommended design procedure.
The diagram in Figure 9 illustrates all branch currents in a
2-phase switching regulator. It becomes very clear after
studying the current waveforms why it is critical to keep
the high-switching-current paths to a small physical size.
High electric and magnetic fields will radiate from these
“loops” just as radio stations transmit signals. The output
capacitor ground should return to the negative terminal of
the input capacitor and not share a common ground path
with any switched current paths. The left half of the circuit
gives rise to the “noise” generated by a switching regula-
tor. The ground terminations of the sychronous MOSFETs
and Schottky diodes should return to the negative plate(s)
SW1
D1
L1
R
SENSE1
V
V
OUT
IN
R
IN
C
OUT
+
+
C
R
L
IN
SW2
L2
R
SENSE2
D2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
3819 F09
Figure 9. Instantaneous Current Path Flow in a Multiple Phase Switching Regulator
3819f
26
LTC3819
U
W
U U
APPLICATIO S I FOR ATIO
Simplified Visual Explanation of How a 2-Phase
Controller Reduces Both Input and Output RMS Ripple
Current
The worst-case RMS ripple current for a single stage
design peaks at an input voltage of twice the output
voltage.Theworst-caseRMSripplecurrentforatwostage
design results in peak outputs of 1/4 and 3/4 of input
voltage. When the RMS current is calculated, higher
effective duty factor results and the peak current levels are
divided as long as the currents in each stage are balanced.
Refer to Application Note 19 for a detailed description of
how to calculate RMS current for the single stage switch-
ing regulator. Figures 3 and 4 illustrate how the input and
output currents are reduced by using an additional phase.
The input current peaks drop in half and the frequency is
doubled for this 2-phase converter. The input capacity
requirement is thus reduced theoretically by a factor of
four! Ceramic input capacitors with their unbeatably low
ESR characteristics can be used.
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors.TheRMSinputripplecurrentisdividedby,and
the effective ripple frequency is multiplied up by the
number of phases used (assuming that the input voltage
isgreaterthanthenumberofphasesusedtimestheoutput
voltage). The output ripple amplitude is also reduced by,
and the effective ripple frequency is increased by the
number of phases used. Figure 10 graphically illustrates
the principle.
SINGLE PHASE
DUAL PHASE
SW V
SW1 V
SW2 V
I
CIN
I
L1
L2
I
COUT
I
I
CIN
I
COUT
3819 F10
RIPPLE
Figure 10. Single and 2-Phase Current Waveforms
3819f
27
LTC3819
APPLICATIO S I FOR ATIO
U
W
U U
Figure 4 illustrates the RMS input current drawn from the
input capacitance vs the duty cycle as determined by the
ratio of input and output voltage. The peak input RMS
currentlevelofthesinglephasesystemisreducedby50%
in a 2-phase solution due to the current splitting between
the two stages.
⎡
⎢
⎤
⎥
1− 2D 1− D
(
)
2VOUT
fL
∆IRIPPLE
=
⎢
⎣
⎥
⎦
1− 2D + 1
where D is duty factor.
The input and output ripple frequency is increased by the
number of stages used, reducing the output capacity
requirements.WhenVIN isapproximatelyequalto2(VOUT
as illustrated in Figures 3 and 4, very low input and output
ripple currents result.
An interesting result of the 2-phase solution is that the VIN
which produces worst-case ripple current for the input
capacitor, VOUT = VIN/2, in the single phase design pro-
duces zero input current ripple in the 2-phase design.
)
The output ripple current is reduced significantly when
compared to the single phase solution using the same
inductance value because the VOUT/L discharge current
term from the stage that has its bottom MOSFET on
subtractscurrentfromthe(VIN –VOUT)/Lchargingcurrent
resultingfromthestagewhichhasitstopMOSFETon. The
output ripple current is:
Figure 12 shows a typical application using LTC3819 to
power the SUN CPU core. The input can vary from 7V to
24V, the output voltage can be programmed from 1.025V
to 1.4125V with a maximum current of 42A. This power
supply receives three input signals to generate different
output voltage offsets based on the operation conditions.
3819f
28
LTC3819
U
TYPICAL APPLICATIO
3819f
29
LTC3819
U
TYPICAL APPLICATIO
3819f
30
LTC3819
U
PACKAGE DESCRIPTIO
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.50 – 13.10*
(.492 – .516)
1.25 ±0.12
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
5
7
8
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
TYP
(.002)
NOTE:
MIN
1. CONTROLLING DIMENSION: MILLIMETERS
G36 SSOP 0204
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3819f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
31
LTC3819
RELATED PARTS
PART NUMBER
LTC1702A/LTC1703
LTC1706-63
DESCRIPTION
COMMENTS
500kHz, 25MHz GBW, 3.3V ≤ V ≤ 7V
Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators
5-Bit VID Programmer for SUN Server CPU
IN
1.25V ≤ V
≤ 1.4125V, 125mV Steps
OUT
LTC1708-PG
Dual High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator
with 5-Bit VID and Power Good Indication
1.3V ≤ V
≤ 3.5V, Current Mode Ensures
OUT
Accurate Current Sharing, 3.5V ≤ V ≤ 36V
IN
LTC1709-7
LTC1735
LTC1736
LTC1778
2-Phase High Efficiency Controller with 5-Bit Mobile VID and Power Good
Burst Mode Operation and Cycle Skip Low
Indication (0.9V ≤ V
≤ 2V)
Current Modes, 3.5V ≤ V ≤ 36V
OUT
IN
High Efficiency Synchronous Step-Down Controller
Burst Mode Operation, 16-Pin Narrow SSOP,
Fault Protection, 3.5V ≤ V ≤ 36V
IN
High Efficiency Synchronous Step-Down Controller with 5-Bit VID
Output Fault Protection, Power Good, GN-24,
3.5V ≤ V ≤ 36V, 0.925V ≤ V
≤ 2V
IN
OUT
No R
TM Synchronous Current Mode Step-Down Controller
No Sense Resistor Required, 4V ≤ V ≤ 36V,
IN
SENSE
0.8V ≤ V
0.6V ≤ V
≤ V , SSOP-16
IN
OUT
LTC3716
2-Phase High Efficiency Controller with 5-Bit VID and Power Good Indication
≤ 1.75V, I
≤ 40A
OUT
OUT
LTC3717/LTC3831
LTC3719
DDR Memory Termination Regulators (V Supply)
Precision Regulation, Up to 20A, Small PCB Area
0.8V ≤ V ≤ 1.55V, I ≤ 40A
TT
2-Phase High Efficiency Controller for AMD Hammer CPUs
Dual 2-Phase 550kHz Step-Down Synchronous Controller
550kHz PolyPhase Step-Down Synchronous Controller
OUT
OUT
LTC3728
Up to 550kHz per Phase, Dual Output, I
≤ 20A
OUT
LTC3729
Up to 550kHz per Phase, Up to 12-Phase
Operation, IOUT = 20A per Phase
LTC3732
3-Phase Step-Down Synchronous Controller (VRM 9.0/9.1)
600kHz per Phase, 5-Bit VID, ±5% Accurate
Current Sharing, IOUT ≤ 60A
Adaptive Power and No R
are a trademarks of Linear Technology Corporation.
SENSE
3819f
LT 1005 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005
相关型号:
LTC3819EG#TRPBF
LTC3819 - 2-Phase, High Efficiency, Step-Down Controller for Sun Server CPUs; Package: SSOP; Pins: 36; Temperature Range: -40°C to 85°C
Linear
LTC3822EDD#PBF
LTC3822 - No RSENSE, Low Input Voltage, Synchronous Step-Down DC/DC Controller; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LTC3822EDD#TRPBF
LTC3822 - No RSENSE, Low Input Voltage, Synchronous Step-Down DC/DC Controller; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C
Linear
LTC3822EDD-1#TR
LTC3822-1 - No RSENSE, Low Input Voltage, Synchronous Step-Down DC/DC Controller; Package: DFN; Pins: 12; Temperature Range: -40°C to 85°C
Linear
LTC3822EGN-1#PBF
LTC3822-1 - No RSENSE, Low Input Voltage, Synchronous Step-Down DC/DC Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LTC3822EGN-1#TRPBF
LTC3822-1 - No RSENSE, Low Input Voltage, Synchronous Step-Down DC/DC Controller; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明