LTC3833IFE#TRPBF [Linear]
LTC3833 - Fast Accurate Step-Down DC/DC Controller with Differential Output Sensing; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C;
| 型号： | LTC3833IFE#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3833 - Fast Accurate Step-Down DC/DC Controller with Differential Output Sensing; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总36页 (文件大小：512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3833
Fast Accurate Step-Down
DC/DC Controller with
Differential Output Sensing
DESCRIPTION
FEATURES
The LTC®3833 is a synchronous step-down DC/DC
switching regulator controller targeted for high power
applications. It drives all N-channel power MOSFETs. The
controlledon-timevalleycurrentmodearchitectureallows
for both fast transient response and constant frequency
n
Wide V Range: 4.5V to 38V
OUT
Output Accuracy: 0.ꢀ5ꢁ at ꢀ5ꢂ° and 0.6ꢃꢁ
over Temperature
Differential Output Sensing Allowing Up to 500mV
Line Loss
Fast Load Transient Response
IN
n
V
Range: 0.6V to 5.5V
n
n
switching in steady-state operation, independent of V ,
IN
n
n
n
V
OUT
and load current.
t
= ꢀ0ns, t
= 90ns
ON(MIN)
OFF(MIN)
Differential output voltage sensing along with a precision
internal reference combine to offer ±±.ꢀ67 output regula-
tion and the ability to correct for up to ±ꢁ±±mV variations
in the output terminals due to line losses. The operating
frequency can be programmed from 2±±kHz to 2MHz with
anexternalresistorandcanbesynchronizedtoanexternal
clock for noise and EMI sensitive applications.
°ontrolled On-Time Valley °urrent Mode
Architecture
n
Frequency Programmable from ꢀ00kHz to ꢀMHz
and Synchronizable to External °lock
n
n
n
n
n
n
R
or Inductor DCR Current Sensing
SENSE
Overvoltage Protection and Current Limit Foldback
Power Good Output Voltage Monitor
Very low t and t times allow for near ±7 and near
Output Tracking or Adjustable Soft-Start
ON
OFF
1±±7dutycycles,respectively.Programmablesoft-startor
outputvoltagetrackingisavailable.Safetyfeaturesinclude
outputovervoltageprotection,programmablecurrentlimit
with foldback, and a power good output signal.
External V Input for Bypassing Internal LDO
CC
2±-Pin QFN (3mm × 4mm) and TSSOP Packages
APPLICATIONS
n
L, LT, LTC, LTM, OPTI-LOOP, PolyPhase, µModule, Linear Technology and the Linear logo
Distributed Power Systems
are registered trademarks and Hot Swap, No R
and UltraFast are trademarks of Linear
SENSE
n
Point-of-Load Converters
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including ꢁ481168, ꢁ486ꢁꢁ4, ꢀꢁ8±2ꢁ8, ꢀ3±4±ꢀꢀ, ꢀ46ꢀꢁ89,
ꢀ664ꢀ11.
n
Computing Systems
Datacomm Systems
n
TYPICAL APPLICATION
1.5V, ꢀ0A, 300kHz High °urrent Step-Down °onverter
INTV
CC
Efficiency
V
IN
4.5V TO 14V
V
V
IN
RNG
100
90
80
70
60
50
40
180µF
V
PULSE-SKIPPING
MODE
OUT
–
SENSE
SENSE
100k
+
PGOOD
RUN
0.1µF
3.24k
TG
SW
FORCED
CONTINUOUS
MODE
LTC3833
0.1µF
0.47µH
V
1.5V
20A
OUT
TRACK/SS
BOOST
470pF
15k
0.1µF
INTV
CC
4.7µF
10k
I
INTV
CC
330µF
TH
137k
×2
RT
10k
EXTV
CC
BG
V
V
= 12V
IN
OUT
= 1.5V
SGND
PGND
300kHz
0.1
1
10
100
MODE/PLLIN
+
V
V
OSNS
OSNS
LOAD CURRENT (A)
3833 TA01a
–
3833 TA01b
3833f
1
LTC3833
(Note 1)
ABSOLUTE MAXIMUM RATINGS
V Voltage ................................................ –±.3V to 4±V
Operating Junction Temperature Range
IN
BOOST Voltage .......................................... –±.3V to 4ꢀV
SW Voltage ................................................... –ꢁV to 4±V
(Notes 2, 3, 4)........................................ –4±°C to 12ꢁ°C
Storage Temperature Range .................. –ꢀꢁ°C to 1ꢁ±°C
Lead Temperature (Soldering, 1± sec)
INTV , EXTV , (BOOST-SW), PGOOD, RUN,
CC
CC
RNG
MODE/PLLIN, V
Voltages....................... –±.3V to ꢀV
FE Package .......................................................3±±°C
+
–
V
OUT
V
, SENSE , SENSE Voltages.................. –±.ꢀV to ꢀV
+
–
, V
Voltages ........ –±.ꢀV to (INTV + ±.3V)
OSNS
OSNS
CC
CC
RT, ITH Voltages .....................–±.3V to (INTV + ±.3V)
TRACK/SS Voltages..................................... –±.3V to ꢁV
PIN CONFIGURATION
TOP VIEW
TOP VIEW
PGOOD
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
BOOST
TG
20 19 18 17
–
+
SENSE
V
V
1
2
3
4
5
6
16 BOOST
15 TG
OSNS
–
SENSE
SW
+
OSNS
V
BG
OUT
TRACK/SS
ITH
14 SW
21
SGND
–
V
PGND
OSNS
21
SGND
13 BG
+
V
INTV
CC
OSNS
V
12 PGND
RNG
TRACK/SS
ITH
V
IN
RT
11 INTV
CC
MODE/PLLIN
7
8
9 10
V
RNG
EXTV
CC
RT 10
RUN
FE PACKAGE
20-LEAD PLASTIC TSSOP
UDC PACKAGE
20-LEAD (3mm × 4mm) PLASTIC QFN
T
JMAX
= 12ꢁ°C, θ = 38°C/W
JA
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
T
= 12ꢁ°C, θ = 43°C/W
JA
JMAX
EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3833EUDC#PBF
LTC3833IUDC#PBF
LTC3833EFE#PBF
LTC3833IFE#PBF
TAPE AND REEL
PART MARKING*
LFGT
PA°KAGE DES°RIPTION
TEMPERATURE RANGE
LTC3833EUDC#TRPBF
LTC3833IUDC#TRPBF
LTC3833EFE#TRPBF
LTC3833IFE#TRPBF
–4±°C to 12ꢁ°C
–4±°C to 12ꢁ°C
–4±°C to 12ꢁ°C
–4±°C to 12ꢁ°C
2±-Lead (3mm × 4mm) Plastic QFN
2±-Lead (3mm × 4mm) Plastic QFN
2±-Lead Plastic TSSOP
LFGT
LTC3833FE
LTC3833FE
2±-Lead Plastic TSSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3833f
2
LTC3833
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = ꢀ5ꢂ°. VIN = 15V, VFB = VOSNS+ – VOSNS–, unless otherwise noted. (Note 4)
SYMBOL
General
PARAMETER
°ONDITIONS
MIN
TYP
MAX
UNITS
V
V
Input Voltage Operating Range
Output Voltage Operating Range
4.ꢁ
±.ꢀ
38
V
V
IN
ꢁ.ꢁ
OUT
I
Input DC Supply Current
Normal
Shutdown Supply Current
Q
MODE/PLLIN = INTV
RUN = ±V
2
1ꢁ
4
2ꢁ
mA
µA
CC
t
t
Minimum On-Time
Minimum Off-Time
V
IN
= 38V, V = ±.ꢀV
OUT
2±
9±
ns
ns
ON(MIN)
OFF(MIN)
Output Sensing
V
Regulated Differential Feedback Voltage
ITH = 1.2V (Note ꢁ)
T = 2ꢁ°C
REG
+
–
(V
– V
)
±.ꢁ98ꢁ
±.ꢁ9ꢀ
±.ꢁ94
±.ꢀ
±.ꢀ
±.ꢀ
±.ꢀ±1ꢁ
±.ꢀ±4
±.ꢀ±ꢀ
V
V
V
OSNS
OSNS
A
l
l
T = ±°C to 8ꢁ°C
A
T = –4±°C to 12ꢁ°C
A
Regulated Differential Feedback Voltage
Over Line, Load and Common Mode
V
V
= 4.ꢁV to 38V, ITH = ±.ꢁV to 1.9V,
IN
–
= ±ꢁ±±mV (Note ꢁ)
OSNS
+
–
l
l
(V
– V
)
T = ±°C to 8ꢁ°C
±.ꢁ94
±.ꢁ91
±.ꢀ
±.ꢀ
±.ꢀ±ꢀ
±.ꢀ±9
V
V
OSNS
OSNS
A
T = –4±°C to 12ꢁ°C
A
l
g
Error Amplifier Transconductance
ITH = 1.2V (Note ꢁ)
1.4
1.6
±ꢁ
2
mS
nA
µA
m(EA)
VOSNS
VOSNS
+
–
+
I
I
V
V
Input Bias Current
Input Bias Current
V
V
= ±.ꢀV
= ±.ꢀV
±2ꢁ
–ꢁ±
OSNS
OSNS
FB
FB
–
–3ꢁ
°urrent Sensing
l
l
l
V
V
V
Valley Current Sense Threshold,
V
V
V
= 2V, V = ±.ꢁ6V
8±
22
39
1±±
3±
12±
38
mV
mV
mV
SENSE(MAX)
SENSE(MIN)
RNG
RNG
RNG
FB
+
–
V
– V
= ±V, V = ±.ꢁ6V
SENSE
SENSE ,
FB
Peak Current = Valley + Ripple
= INTV , V = ±.ꢁ6V
ꢁ±
ꢀ1
CC FB
Minimum Current Sense Threshold,
V
RNG
V
RNG
V
RNG
= 2V, V = ±.ꢀ3V
–ꢁ±
–1ꢁ
–2ꢁ
mV
mV
mV
FB
+
–
V
– V
, Forced Continuous
= ±V, V = ±.ꢀ3V
FB
SENSE
SENSE
Mode
= INTV , V = ±.ꢀ3V
CC FB
+
–
l
SENSE , SENSE Voltage Range
(Common Mode)
Referenced to Signal Ground (SGND)
–±.ꢁ
ꢁ.ꢁ
V
SENSE(CM)
SENSE
+
–
I
SENSE , SENSE Input Bias Current
V
V
= ±.ꢀV
= ꢁV
±ꢁ
1
±ꢁ±
4
nA
µA
SENSE(CM)
SENSE(CM)
Start-Up and Shutdown
l
V
V
RUN Pin On Threshold
RUN Pin Hysteresis
V
Rising
RUN
1.1
3.4
1.2
6±
1.3
V
mV
µA
V
RUN(TH)
RUN(HYS)
I
Soft-Start Charging Current
V = ±V
TRACK/SS
1.±
3.ꢀꢁ
4.2
SS
l
l
UVLO
UVLO
INTV Undervoltage Lockout
INTV Falling
4.±
4.ꢁ
LOCK
CC
CC
INTV Undervoltage Lockout Release
INTV Rising
V
RELEASE
CC
CC
Switching Frequency and °lock Synchronization
f
Free Running Switching Frequency
R = 2±ꢁk
16ꢁ
4ꢁ±
18±±
2±±
ꢁ±±
2±±±
22ꢁ
ꢁꢁ±
22±±
kHz
kHz
kHz
T
R = 8±.ꢀk
T
R = 18.2k
T
V
V
Clock Input High Level into MODE/PLLIN
Clock Input Low Level into MODE/PLLIN
2
V
V
CLK(IH)
CLK(IL)
±.ꢁ
3833f
3
LTC3833
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TA = ꢀ5ꢂ°. VIN = 15V, VFB = VOSNS+ – VOSNS–, unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
°ONDITIONS
MIN
TYP
MAX
UNITS
Gate Drivers
R
R
R
R
TG Driver Pull-Up On-Resistance
TG Driver Pull-Down On-Resistance
BG Driver Pull-Up On-Resistance
BG Driver Pull-Down On-Resistance
TG High
TG Low
BG High
BG Low
(Note ꢀ)
2.ꢁ
1.2
2.ꢁ
±.8
2±
Ω
Ω
Ω
Ω
ns
TG(HI)
TG(LO)
BG(HI)
BG(LO)
DLY(OFF)
t
Top Gate Off to Bottom Gate On
Delay Time
t
Bottom Gate Off to Top Gate On
Delay Time
(Note ꢀ)
1ꢁ
ns
DLY(ON)
Internal V Regulator and External V
°°
°°
INTV
Internal V Voltage
ꢀV < V < 38V
ꢁ.1
4.4
ꢁ.3
–1
ꢁ.ꢁꢁ
–2
V
7
CC
CC
IN
INTV (7)
Internal V Load Regulation
I
CC
= ±mA to ꢁ±mA
CC
CC
EXTV
EXTV
EXTV Switchover Voltage
EXTV Rising
4.ꢀ
2±±
2±±
4.6ꢁ
V
CC(TH)
CC
CC
EXTV Switchover Hysteresis
mV
mV
CC(HYS)
CC
EXTV Voltage Drop
V = ꢁV, I = ꢁ±mA
EXTVCC CC
∆EXTV
CC
CC
PGOOD Output
PGD
PGD
PGD
PGOOD Upper Threshold
PGOOD Lower Threshold
V
Rising (with Respect to Regulated
FB
ꢁ
6.ꢁ
1±
–ꢁ
7
7
OV
Feedback Voltage V
)
REG
V
FB
Falling (with Respect to Regulated
–1±
–6.ꢁ
UV
Feedback Voltage V
)
REG
PGOOD Hysteresis
V
FB
Returning
2
±.1ꢁ
2±
7
V
HYS
V
PGOOD Low Voltage
I
= ꢁmA
±.4
PGD(LO)
PGOOD
t
t
Delay from OV/UV Fault to PGOOD Falling
µs
µs
PGD(FALL)
PGD(RISE)
Delay from OV/UV Recovery to PGOOD
Rising
1±
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LTC3833 is tested under pulsed loading conditions such
that T ≈ T . The LTC3833E is guaranteed to meet specifications from
J
A
±°C to 8ꢁ°C junction temperature; specifications over the –4±°C to
12ꢁ°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3833I is guaranteed to meet specifications over the full –4±°C to 12ꢁ°C
operating junction temperature range. Note that the maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal impedance and other environmental factors.
Note ꢀ: The junction temperature (T in °C) is calculated from the ambient
J
temperature (T in °C) and power dissipation (P in Watts) as follows:
A
D
T = T + (P • θ )
JA
J
A
D
where θ (in °C/W) is the package thermal impedance provided in the Pin
JA
Configuration section for the corresponding package.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 5: The LTC3833 is tested in a feedback loop that adjusts
+
–
V
= V
– V
to achieve a specified error amplifier output voltage
FB
OSNS
OSNS
(on ITH pin). The specification at 8ꢁ°C is not tested in production. This
specification is assured by design, characterization and correlation to
production testing at 12ꢁ°C.
Note 6: Delay times are measured using ꢁ±7 levels.
3833f
4
LTC3833
TYPICAL PERFORMANCE CHARACTERISTICS TA = ꢀ5ꢂ° unless otherwise noted
Transient Response: Forced
°ontinuous Mode
Load Step: Forced °ontinuous
Mode
Load Release: Forced °ontinuous
Mode
I
I
LOAD
20A/DIV
I
LOAD
LOAD
20A/DIV
20A/DIV
V
OUT
V
50mV/DIV
OUT
50mV/DIV
V
OUT
50mV/DIV
I
I
L
L
I
L
20A/DIV
20A/DIV
20A/DIV
3833 G01
3833 G02
3833 G03
50µs/DIV
5µs/DIV
5µs/DIV
LOAD TRANSIENT = 0A TO 20A
LOAD STEP = 0A TO 20A
LOAD RELEASE = 20A TO 0A
V
= 12V, V
= 1.5V
V
= 12V, V
= 1.5V
V
= 12V, V
= 1.5V
IN
OUT
IN
OUT
IN
OUT
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
Transient Response: Pulse-
Skipping Mode
Load Release: Pulse-Skipping
Mode
Load Step: Pulse-Skipping Mode
I
I
I
LOAD
20A/DIV
LOAD
LOAD
20A/DIV
20A/DIV
V
OUT
V
50mV/DIV
OUT
50mV/DIV
V
OUT
50mV/DIV
I
I
I
L
L
L
20A/DIV
20A/DIV
20A/DIV
3833 G04
3833 G05
3833 G06
50µs/DIV
5µs/DIV
5µs/DIV
LOAD TRANSIENT = 500mA TO 20A
LOAD STEP = 500mA TO 20A
LOAD RELEASE = 20A TO 500mA
V
= 12V, V
= 1.5V
V
= 12V, V
= 1.5V
V
= 12V, V
= 1.5V
IN
OUT
IN
OUT
IN
OUT
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
Soft Start-Up into
a Pre-Biased Output
Normal Soft Start-Up
Output Tracking
V
RUN
2V/DIV
IN
5V/DIV
V
OUT
500mV/DIV
TRACK/SS
200mV/DIV
TRACK/SS
200mV/DIV
TRACK/SS
200mV/DIV
V
PRE-BIASED TO 0.75V
OUT
V
OUT
V
OUT
500mV/DIV
500mV/DIV
3833 G07
3833 G08
3833 G09
10ms/DIV
V
V
= 12V
OUT
FIGURE 10 CIRCUIT
10ms/DIV
V
V
= 12V
10ms/DIV
V
V
= 12V
IN
IN
OUT
IN
OUT
= 1.5V
= 1.5V
= 1.5V
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
3833f
5
LTC3833
TYPICAL PERFORMANCE CHARACTERISTICS TA = ꢀ5ꢂ° unless otherwise noted
Overcurrent Protection
Short-°ircuit Protection
Overvoltage Protection
OVERVOLTAGE REGION
CURRENT LIMIT (25A)
SHORT-
CIRCUIT
TRIGGER
OVERVOLTAGE
TRIGGER
SHORT-CIRCUIT
REGION
V
OUT
I
LOAD
200mV/DIV
V
OUT
10A/DIV
1V/DIV
I
L
I
I
I
LOAD
NOTE 7
LOAD
12A
L
10A/DIV
12A
20A/DIV
I
V
DROOPS DUE TO
L
OUT
10A/DIV
REACHING CURRENT LIMIT
V
BG
5V/DIV
OUT
200mV/DIV
INDUCTOR CURRENT FOLDBACK
DURING SHORT-CIRCUIT
NOTE 8
3833 G10
3833 G11
3833 G12
V
V
= 12V
10ms/DIV
V
V
= 12V
1ms/DIV
V
V
= 12V
20µs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.5V
= 1.5V
= 1.5V
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
NOTE 8: BG IS FORCED HIGH FOR EXTENDED
PERIODS TO REMOVE OVERVOLTAGE
NOTE 7: INDUCTOR CURRENT REACHES
CURRENT LIMIT BEFORE FOLDBACK
AND DURING SHORT-CIRCUIT RECOVERY
Output Regulation
vs Input Voltage
Output Regulation
vs Load °urrent
Output Regulation
vs Temperature
0.2
0.2
0.1
0
0.2
0.1
0
V
I
= 0.6V
= 5A
V
V
I
= 15V
= 0.6V
= 0A
V
V
V
= 15V
OUT
IN
OUT
IN
= 0.6V
LOAD
OUT
OUT
V
NORMALIZED AT V = 15V
NORMALIZED AT I
= 4A
OUT
IN
LOAD
LOAD
V
NORMALIZED AT T = 25°C
0.1
0
OUT
A
–0.1
–0.1
–0.1
–0.2
–0.2
–0.2
0
5
10 15 20 25 30 35 40
(V)
0
2
4
I
6
8
10
–50 –25
0
25 50 55 100 125 150
TEMPERATURE (°C)
V
(A)
IN
LOAD
3833 G13
3833 G14
3833 G15
Non-Synchronized Switching
Frequency vs Input Voltage
Non-Synchronized Switching
Frequency vs Load °urrent
Non-Synchronized Switching
Frequency vs Temperature
0.2
2.0
1.5
1.0
0.5
0
1.0
0.5
V
I
= 15V, V
LOAD
FREQUENCY NORMALIZED AT T = 25°C
= 0.6V
OUT
V
V
= 15V
IN
IN
OUT
= 0A, f = 500kHz
= 0.6A
f = 500kHz
0.1 FREQUENCY NORMALIZED AT I
A
= 4A
LOAD
0
–0.5
–1.0
–1.5
–2.0
0
–0.1
V
I
= 0.6V
= 5A
OUT
LOAD
–0.5
–1.0
f = 500kHz
FREQUENCY NORMALIZED AT V = 15V
IN
–0.2
25 30
75 100
125 150
0
5
10 15 20
(V)
35 40
–50 –25
0
25 50
0
2
4
6
8
10
V
TEMPERATURE (°C)
IN
I
(A)
LOAD
3833 G16
3833 G18
3833 G17
3833f
6
LTC3833
TYPICAL PERFORMANCE CHARACTERISTICS TA = ꢀ5ꢂ° unless otherwise noted
tON(MIN) and tOFF(MIN)
vs Voltage on VOUT Pin
tON(MIN) and tOFF(MIN)
vs Voltage on VIN Pin
tON(MIN) and tOFF(MIN)
vs Switching Frequency
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
t
t
OFF(MIN)
OFF(MIN)
t
OFF(MIN)
t
ON(MIN)
t
ON(MIN)
t
ON(MIN)
V
= 38V
V
V
= 38V
IN
OUT
V
= 0.6V
IN
OUT
f ≈ 2000kHz
= 0.6V
f ≈ 2000kHz
0
1
3
4
5
6
0
20
(V)
30 35
200
500
1100 1400 1700 2000
2
5
10 15
25
40
800
V
(V)
V
FREQUENCY (kHz)
OUT
IN
3833 G19
3833 G20
3833 G21
Error Amplifier Transconductance
vs Temperature
°urrent Sense Voltage
vs ITH Voltage
Maximum °urrent Sense Voltage
vs Temperature
120
100
80
1.80
1.75
1.70
1.65
1.60
1.55
1.50
120
100
80
60
40
20
0
V
= 2V
RNG
60
40
V
= 1V
20
RNG
0
V
= 0.6V
RNG
RNG
RNG
RNG
RNG
V
= 0.6V
RNG
V
V
V
V
= 0.9V
= 1.3V
= 1.6V
= 2.0V
–20
–40
–60
75 100
75 100
125 150
–50 –25
0
25 50
125 150
0
2
2.5
–50 –25
0
25 50
0.5
1
1.5
TEMPERATURE (°C)
TEMPERATURE (°C)
ITH VOLTAGE (V)
3833 G22
3833 G23
3833 G24
Input Undervoltage Lockout
Thresholds vs Temperature
RUN and TRA°K/SS Pull-Up
°urrents vs Temperature
RUN Thresholds vs Temperature
1.8
1.6
1.4
1.2
1.0
0.8
0.6
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
4.5
4.3
4.1
3.9
3.7
3.5
3.3
SWITCHING REGION
UVLO RELEASE
(INTV RISING)
CC
RUN
STANDBY REGION
TRACK/SS
UVLO LOCK
(INTV FALLING)
CC
SHUTDOWN REGION
75 100
25 50
TEMPERATURE (°C)
75 100
–50 –25
0
125 150
3833 G27
50 75
TEMPERATURE (°C)
–50 –25
0
25 50
125 150
–50 –25
0
25
100 125 150
TEMPERATURE (°C)
3833 G26
3833 G25
3833f
7
LTC3833
(FE/UD°)
PIN FUNCTIONS
PGOOD (Pin 1/Pin 1ꢃ): Power Good Indicator Output.
This open-drain logic output is pulled to ground when
the output voltage is outside of a ±6.ꢁ7 window around
the regulation point.
ITH (Pin 8/Pin 4): Current Control Voltage and Switch-
ing Regulator Compensation Point. The current sense
thresholdincreaseswiththiscontrolvoltagewhichranges
from ±V to 2.4V.
+
SENSE (Pin ꢀ/Pin 18): Differential Current Sensing (+)
V
(Pin 9/Pin 5): Current Sense Voltage Range Input.
RNG
+
Input.ForR
currentsensing,Kelvin(4-wire)connect
ThemaximumallowedsensevoltagebetweenSENSE and
SENSE
+
–
–
SENSE and SENSE pins across the sense resistor. For
SENSE is equal to 0.05 • V . If V
is tied to SGND,
RNG
RNG
+
–
DCR sensing, Kelvin connect SENSE and SENSE pins
across the sense filter capacitor.
the device operates with a maximum sense voltage of
3±mV. If V
a maximum sense voltage of ꢁ±mV.
is tied to INTV , the device operates with
RNG
CC
–
SENSE (Pin 3/Pin 19): Differential Current Sensing (–)
Input.ForR
currentsensing,Kelvin(4-wire)connect
RT(Pin10/Pin6):SwitchingFrequencyProgrammingPin.
Connect an external resistor from RT to signal ground to
program the switching frequency between 2±±kHz and
2MHz. An external clock applied to MODE/PLLIN must
be within ±3±7 of this free-running frequency to ensure
frequency lock.
SENSE
+
–
SENSE and SENSE pins across the sense resistor. For
+
–
DCR sensing, Kelvin connect SENSE and SENSE pins
across the sense filter capacitor.
V
OUT
(Pin 4/Pin ꢀ0): Output voltage sense for adjusting
the TG on-time for constant frequency operation. Tying
this pin to the local output (instead of remote output)
is recommended for most applications. This pin can be
programmed as needed for achieving the steady-state
on-time required for constant frequency operation.
RUN (Pin 11/Pin ꢃ): Digital Run Control Input. RUN self
biases high with an internal 1.3µA pull-up. Forcing RUN
below 1.2V turns off TG and BG. Taking RUN below ±.6ꢁV
shutsdownallbiasandplacestheLTC3833intomicropower
shutdown mode of approximately 1ꢁμA.
–
V
(Pin 5/Pin 1): Differential Output Sensing (–)
OSNS
Input. Connect this pin to the negative terminal of the
output capacitor. There is a bias current of 3ꢁµA (typical)
flowing out of this pin.
EXTV (Pin 1ꢀ/Pin 8): External V Input. When EXT-
°° CC
V
exceeds 4.ꢀV, an internal switch connects this pin to
CC
INTV and shuts down the internal regulator so that the
CC
controller and gate drive power is drawn from EXTV .
+
CC
V
OSNS
(Pin6/Pinꢀ):DifferentialOutputSensing(+)Input.
EXTV should not exceed V .
CC
IN
Connect this pin to the feedback resistor divider between
the positive and negative output capacitor terminals. In
nominal operation the LTC3833 will regulate the differen-
tial output voltage which is divided down to ±.ꢀV by the
feedback resistor divider.
MODE/PLLIN (Pin 13/Pin 9): External Clock Synchroniza-
tionInputand/orForcedContinuousModeInput.Whenan
externalclockisappliedtothispin, therisingTGsignalwill
be synchronized with the rising edge of the external clock.
Additionally,thispindeterminesoperationunderlightload
conditions.WheneitheraclockinputisdetectedorMODE/
TRA°K/SS (Pin ꢃ/Pin 3): External Tracking and Soft-Start
Input.TheLTC3833regulatesthedifferentialfeedbackvolt-
PLLINistiedtoINTV ,forcedcontinuousmodeoperation
+
–
CC
age(V
−V
)tothesmallerof±.ꢀVorthevoltage
OSNS
OSNS
is selected. Tying this pin to SGND allows discontinuous
on the TRACK/SS pin. An internal 1.±μA pull-up current
source is connected to this pin. A capacitor to ground at
this pin sets the ramp time to the final regulated output
voltage. Alternatively, another voltage supply connected
through a resistor divider to this pin allows the output to
track the other supply during start-up.
pulse-skipping mode operation at light loads.
3833f
8
LTC3833
PIN FUNCTIONS
V (Pin14/Pin10):MainSupplyInput.Thesupplyvoltage
SW (Pin 18/Pin 14): Switch Node Connection. The (–)
IN
can range from 4.ꢁV to 38V. For increased noise immunity
decouple this pin to signal ground with an RC filter. The
voltage on this pin is also used to adjust the TG on-time
in order to maintain constant frequency operation.
terminal of the bootstrap capacitor, C , connects to this
B
node. This pin swings from a diode voltage below ground
up to V .
IN
TG (Pin 19/Pin 15): Top Gate Drive Output. This pin drives
INTV (Pin 15/Pin 11): Internal ꢁ.3V Regulator Output.
the gate of the top N-Channel power MOSFET between
°°
The driver and control circuits are powered from this volt-
V
SW
and V
.
BOOST
age. Decouplethispintopowergroundwithaminimumof
BOOST (Pin ꢀ0/Pin 16): Boosted Driver Supply Connec-
tion. The (+) terminal of the bootstrap capacitor, C , as
4.6μFceramiccapacitor(C ).TheanodeoftheSchottky
VCC
B
diode, D , connects to this pin.
B
well as the cathode of the Schottky diode, D , connects
B
PGND(Pin16/Pin1ꢀ):PowerGroundConnection.Connect
to this node. This node swings from INTV – V
CC SCHOTTKY
this pin as close as practical to the source of the bottom
to V + INTV – V
.
IN
CC
SCHOTTKY
N-channel power MOSFET, the (–) terminal of C
and
VCC
SGND (Exposed Pad Pin ꢀ1/Exposed Pad Pin ꢀ1): Signal
Ground Connection. The SGND exposed pad must be
soldered to the circuit board for electrical contact and
rated thermal performance. All small-signal components
should be connected to the signal ground. Connect signal
ground to power ground only at one point using a single
PCB trace.
the (–) terminal of C .
IN
BG (Pin 1ꢃ/Pin 13): Bottom Gate Drive Output. This pin
drives the gate of the bottom N-channel power MOSFET
between INTV and power ground.
CC
3833f
9
LTC3833
FUNCTIONAL DIAGRAM
V
IN
C
IN
V
IN
IN
LDO
OUT EN
BO0ST
TG
UVLO
C
B
D
B
+
–
–
3.65V
4.2V
TG DRV
MT
R
L
SENSE
SW
V
OUT
EXTV
CC
CC
1.3µA
+
–
RUN
+
4.6V
0.75V
1.2V
–
C
OUT
START
STOP
–
LOGIC
CONTROL
INTV
CC
INTV
V
OUT
ONE-SHOT
TIMER
R
R
FB2
FB1
C
VCC
BG
MB
BG DRV
TIME
ADJUST
PGND
I
I
REV
CMP
–
+
–
+
CLOCK
MODE/PLLIN
RT
CLOCK
DETECT
PLL
SYSTEM
+
SENSE
–
SENSE
OSCILLATOR
1µA
R
T
TRACK/SS
+
+
+
–
C
SS
0.6V
INTV
CC
V
OSNS
+
–
0.645V
+
OV
–
R
PGD
DA
(A = 1)
PGOOD
EA
m(EA)
–
(g
= 1.7mS)
V
OSNS
3833 FD
+
UV
–
0.555V
V
I
TH
SGND
RNG
INTV
CC
R1
R
ITH
C
ITH1
R2
OPERATION (Refer to Functional Diagram)
Main °ontrol Loop
one-shot timer. The PLL system adjusts the delay in the
one-shot timer until the top MOSFET turn-on is synchro-
nized either to the internal oscillator or the external clock
input if provided. As the top MOSFET turns off, the bottom
MOSFET turns on with a small time delay (dead time) to
avoid shoot-through current. The next switching cycle is
The LTC3833 uses valley current mode control to regulate
theoutputvoltageinanallN-channelMOSFETDC/DCstep-
down converter. Current control is achieved by sensing
+
–
the inductor current across SENSE and SENSE , either
by using an explicit resistor connected in series with the
inductor or by implicitly sensing the inductor’s resistive
(DCR) voltage drop through an RC filter connected across
the inductor.
initiated when the current comparator, I
, senses that
CMP
inductor current has reached the valley threshold point
and turns the bottom MOSFET off immediately and the
top MOSFET on. Again in order to avoid shoot-through
current there is a small dead-time delay before the top
MOSFET turns on.
Innormalsteady-stateoperation,thetopMOSFETisturned
on for a fixed time interval proportional to the delay in the
3833f
10
LTC3833
(Refer to Functional Diagram)
OPERATION
The voltage on the ITH pin sets the I
valley threshold
the top MOSFET turns off. If the V voltage is low and
IN
CMP
point. The error amplifier, EA, adjusts this ITH voltage
INTV drops below 3.ꢀꢁV, undervoltage lockout circuitry
CC
+
by comparing the differential feedback signal, V
−
disables the external MOSFET driver and prevents the
power switches from turning on.
OSNS
–
V
OSNS
,toa±.ꢀVinternalreferencevoltage.Consequently,
the LTC3833 regulates the output voltage by forcing the
differentialfeedbackvoltagetobeequaltothe±.ꢀVinternal
reference. The difference amplifier, DA, converts the dif-
ferential feedback signal to a single-ended input for the
EA. If the load current increases, it causes a drop in the
differential feedback voltage relative to the reference. The
EA forces ITH voltage to rise until the average inductor
current again matches the load current.
Shutdown and Start-Up
The LTC3833 can be shut down using the RUN pin. Pulling
this pin below 1.2V prevents the controller from switch-
ing, and less than ±.6ꢁV disables most of the internal bias
circuitry,includingtheINTV regulator.WhenRUNisless
CC
than±.6ꢁV,theshutdownI isabout1ꢁμA.PullingtheRUN
Q
pin between ±.6ꢁV and 1.2V enables the controller into a
standby mode where all internal circuitry is powered-up
Differential Output Sensing
buttheexternalMOSFETdriverisdisabled. ThestandbyI
Q
Theoutputvoltageisresistivelydividedexternallytocreate
afeedbackvoltageforthecontroller.Theinternaldifference
amplifier, DA, senses this feedback voltage along with the
output’s remote ground reference to create a differential
feedback voltage. This scheme overcomes any ground
offsets between local ground and remote output ground,
resulting in a more accurate output voltage. The LTC3833
allows for remote output ground deviations as much as
±ꢁ±±mV with respect to local ground.
is about 2mA. Releasing the RUN pin from ground allows
an internal 1.3μA current to pull the pin above 1.2V and
fully enable the controller including the external MOSFET
driver. Alternatively, the RUN pin may be externally pulled
up or driven directly by logic. Be careful not to exceed the
absolutemaximumratingofꢀVonthispin.Whenpulledup
by a resistor to an external voltage, the RUN pin will sink
up to 3ꢁµA of current before reaching ꢀV. If the external
voltage is above ꢀV (e.g., V ), select a large enough resis-
IN
tor value so that the voltage on RUN will not exceed ꢀV.
INTV /EXTV Power
°°
°°
The start-up of the controller’s output voltage, V , is
OUT
Power for the top and bottom MOSFET drivers and most
controlled by the voltage on the TRACK/SS pin. When
the voltage on the TRACK/SS pin is less than the ±.ꢀV
internal reference, the LTC3833 regulates the differential
feedback voltage to the TRACK/SS voltage instead of the
±.ꢀV reference. This allows the TRACK/SS pin to be used
otherinternalcircuitryisderivedfromtheINTV pin.Power
CC
on the INTV pin is derived in two ways: if the EXTV
CC
CC
pin is below 4.ꢀV, then an internal ꢁ.3V low dropout linear
regulator, LDO, supplies INTV power from V ; if the
CC
IN
EXTV pin is tied to an external source larger than 4.ꢀV,
for programming a ramp-up time for V
by connecting
CC
OUT
then the LDO is shut down and an internal switch shorts
the EXTV pin to the INTV pin, thereby powering the
an external capacitor from the TRACK/SS pin to SGND. An
internal1μApull-upcurrentchargesthiscapacitor,creating
a voltage ramp on the TRACK/SS pin. As the TRACK/SS
voltage rises from ±V to ±.ꢀV (and beyond), the LTC3833
CC
CC
INTV pinwiththeexternalsourceandhelpingtoincrease
CC
overallefficiencyanddecreaseinternalselfheatingthrough
power dissipated in the LDO. This external power source
could be the output of the step-down switching regulator
itself if the output is programmed to higher than 4.ꢀV.
forces the output voltage, V , to ramp up smoothly to
OUT
itsfinalvalue. Alternatively, theTRACK/SSpincanbeused
to track the start-up of V
to another external supply
OUT
as in a master slave configuration. Typically, this requires
connecting a resistor divider from the master supply to
the TRACK/SS pin (see Soft-Start and Tracking).
The top MOSFET driver is biased from the floating boot-
strap capacitor, C , which normally recharges during
B
each off cycle through an external Schottky diode when
3833f
11
LTC3833
OPERATION (Refer to Functional Diagram)
When the RUN pin is pulled low to disable the controller or
turn-ontotherisingedgeoftheclock. TheLTC3833oper-
atesinforcedcontinuousmodewhenitissynchronizedto
the external clock. The external clock frequency has to be
within ±3±7 of the internal oscillator frequency for suc-
cessful synchronizationand theclockinput levels should
be greater than 2V for HI and less than ±.ꢁV for LO. The
MODE/PLLINpinhasaninternalꢀ±±kpull-downresistor.
whenINTV dropsbelowitsundervoltagelockoutthresh-
CC
old of 3.ꢀꢁV, the TRACK/SS pin is pulled low internally.
Light Load °urrent Operation
When the DC load current is less than 1/2 of the peak-
to-peak inductor current ripple, the inductor current can
drop to zero or become negative. If the MODE/PLLIN pin
is connected to SGND, the LTC3833 will transition into
discontinuousmodeoperation(alsocalledpulse-skipping
mode),whereacurrentreversalcomparator,IREV,detects
and prevents negative inductor current by shutting off the
bottom MOSFET, MB. In this mode, both switches remain
off with the output capacitor supplying the load current.
As the output capacitor discharges and the output volt-
age droops lower, the EA will eventually move the ITH
voltage above the zero current level to initiate another
switching cycle.
Power Good and Fault Protection
The power good pin, PGOOD, is connected internally to
an open-drain N-channel MOSFET. An external pull-up
resistor to a voltage supply of up to ꢀV (or INTV ) com-
CC
pletes the power good detection scheme. Overvoltage
and undervoltage comparators OV and UV turn on the
MOSFET and pull the PGOOD pin low when the differen-
tial feedback voltage is outside a ±6.ꢁ7 window of the
±.ꢀV reference voltage. The PGOOD pin is also pulled low
when the LTC3833 is in the soft-start or tracking phase,
when in undervoltage lockout, or when the RUN pin is
low (shut down).
If the MODE/PLLIN pin is tied to INTV or an external
CC
clockisappliedtoMODE/PLLIN,theLTC3833willbeforced
to operate in continuous mode (called forced continuous
mode) and not transition into discontinuous mode. In this
When the differential feedback voltage is within the ±6.ꢁ7
requirement, the open-drain NMOS is turned off and the
pin is pulled up by an external resistor. There is an internal
delay of 1±µs before the PGOOD pin will indicate power
good once the differential feedback voltage is within the
±6.ꢁ7 window. When the feedback voltage goes out of
the ±6.ꢁ7 window, there is an internal 2±μs delay before
PGOOD is pulled low. In an overvoltage condition, MT is
turned off and MB is turned on immediately without any
delay and held on until the overvoltage condition clears.
case the current reversal comparator, I , is disabled, al-
REV
lowing the inductor current to become negative and thus
maintain constant frequency operation.
Frequency Selection and External °lock
Synchronization
The steady-state switching frequency of the LTC3833 is
set by an internal oscillator. The frequency of this internal
oscillator can be programmed from 2±±kHz to 2MHz by
connecting a resistor from the RT pin to SGND. The RT
pin is forced to 1.2V internally. A phase-locked loop (PLL)
system synchronizes the TG turn-on to this internal oscil-
lator when no external clock is provided.
Foldbackcurrentlimitingisprovidediftheoutputisshorted
to ground. As the differential feedback voltage drops, the
current threshold voltage on the ITH pin is pulled down
and clamped to 1.2V. This reduces the inductor valley
current level to 1/4th of its maximum value as the differ-
ential feedback approaches ±V. Foldback current limiting
is disabled at start-up.
For applications with stringent frequency or interference
requirements, an external clock source connected to
the MODE/PLLIN pin can be used to synchronize the TG
3833f
12
LTC3833
APPLICATIONS INFORMATION
The Typical Application on the first page of this data sheet
is a basic LTC3833 application circuit. The LTC3833 can be
configured to sense the inductor current either through a
Moreprecisely,theV valueprogrammedintheprevious
OUT
equation is with respect to the output’s ground reference,
and thus is a differential quantity. For example, if V
is
OUT
seriessenseresistor,R
,orthroughanRCfilteracross
SENSE
programmed to ꢁV and the output ground reference is at
–±.ꢁV, then the output will be 4.ꢁV with respect to signal
ground.Theminimumdifferentialoutputvoltageislimited
totheinternalreference,±.ꢀV,andthemaximumdifferential
output voltage is ꢁ.ꢁV.
the inductor (DCR). The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Once the required output voltage and operat-
ing frequency have been determined, external component
selection is driven by load requirements, and begins with
theselectionofinductorandcurrentsensingcomponents.
Next, the power MOSFETs are selected. Finally, input and
output capacitors are selected.
+
The V
pin is high impedance with no input bias cur-
OSNS
–
rent. The V
pin has about 3ꢁμA of current flowing
OSNS
out of the pin.
Differentialoutputsensingallowsformoreaccurateoutput
regulation in high power distributed systems having large
line losses. Figure 2 illustrates the potential variations in
the power and ground lines due to parasitic elements.
These variations are exacerbated in multi-application
systems with shared ground planes. Without differential
outputsensing, these variationsdirectly reflect as anerror
in the regulated output voltage. The LTC3833’s differential
output sensing can correct for up to ±ꢁ±±mV of variation
in the output’s power and ground lines.
Output Voltage Programming and
Differential Output Sensing
The LTC3833 integrates differential output sensing with
output voltage programming, allowing for simple and
seamless design. As shown in Figure 1, the output voltage
is programmed by an external resistor divider from the
The LTC3833’s differential output sensing scheme is
distinct from conventional schemes where the regulated
output and its ground reference are directly sensed with
a difference amplifier whose output is then divided down
with an external resistive divider and fed into the error
amplifier input. This conventional scheme is limited by
the common mode input range of the difference amplifier
and typically limits differential sensing to the lower range
of output voltages.
regulated output point to its ground reference. The resis-
+
tive divider is tapped by the V
pin, and the ground
OSNS
–
reference is sensed by V
. An optional feed-forward
capacitor, C , can be used to improve the transient
OSNS
FF
performance of the regulator system as discussed under
OPTI-LOOP® Compensation. The resulting output voltage
is given according to the following equation:
The LTC3833 allows for seamless differential output
sensing by sensing the resistively divided feedback volt-
age differentially. This allows for differential sensing in
the full output range from ±.ꢀV to ꢁ.ꢁV. The difference
amplifier of the LTC3833 has a –3dB bandwidth of 8MHz,
high enough to not affect main loop compensation and
transient behavior.
RFB2
R
VOUT = 0.6V • 1+
FB1
V
OUT
LTC3833
+
+
C
To avoid noise coupling into V
should be placed near the V
, the resistor divider
FF
OSNS
+
R
R
FB2
(OPT)
–
and V
pins and
C
OSNS
OSNS
V
OUT
OSNS
physically close to the LTC3833. The remote output and
ground traces should be routed together as a differential
pair to the remote output. These traces should be termi-
FB1
–
3833 F01
V
OSNS
nated as close as physically possible to the remote output
Figure 1. Setting Output Voltage
3833f
13
LTC3833
APPLICATIONS INFORMATION
+
C
IN
V
C
IN
–
POWER TRACE
PARASITICS
MT
L
LTC3833
+
V
DROP(PWR)
MB
–
V
OSNS
V
OSNS
I
LOAD
C
OUT1
OUT2
I
R
R
FB1
LOAD
FB2
GROUND TRACE
PARASITICS
V
DROP(GND)
OTHER CURRENTS
FLOWING IN
SHARED GROUND
PLANE
3833 F02
Figure ꢀ: Differential Output Sensing Used to °orrect Line Loss Variations in a
High Power Distributed System with a Shared Ground Plane
point that is to be accurately regulated through remote
differential sensing.
for maximum synchronization margin. Refer to Phase and
Frequency Synchronization for further details.
Switching Frequency Programming
Inductor Selection
The choice of operating frequency is a trade-off between
efficiencyandcomponentsize.Loweringtheoperatingfre-
quencyimprovesefficiencybyreducingMOSFETswitching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades efficiency but reduces
component size.
The operating frequency and inductor selection are inter-
relatedinthathigheroperatingfrequenciesallowtheuseof
smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET
gate charge losses and top MOSFET transition losses.
In addition to this basic trade-off, the effect of inductor
value on ripple current and low current operation must
also be considered.
The switching frequency of the LTC3833 can be pro-
grammed from 2±±kHz to 2MHz by connecting a resistor
from the RT pin to signal ground. The value of this resistor
is given by the following empirical formula:
The inductor value has a direct effect on ripple current.
The inductor ripple current, ∆I , decreases with higher
L
inductance or frequency and increases with higher V :
IN
41550
VOUT
f •L
VOUT
R kΩ =
–2.2
[
]
∆IL =
• 1–
T
f kHz
V
IN
Not counting resistor tolerances, the switching fre-
quency could still have a ±1±7 deviation from the ideal
programmed value. The internal PLL has a synchroniza-
tion range of ±3±7 around this programmed frequency.
Therefore, during external clock synchronization be sure
thattheexternalclockfrequencyiswithinthis±3±7range
of the RT programmed frequency. It is advisable that the
RT programmed frequency be equal to the external clock
Accepting larger values of ∆I allows the use of low induc-
L
tances, but results in higher output voltage ripple, higher
ESRlossesintheoutputcapacitor,andgreatercorelosses.
A reasonable starting point for setting ripple current is
∆I = 0.4 • I
where I
is the maximum
L
OUT(MAX)
OUT(MAX)
output current for the application. The maximum ∆I
L
occurs at the maximum input voltage. To guarantee that
3833f
14
LTC3833
APPLICATIONS INFORMATION
ripple current does not exceed a specified maximum, the
inductance should be chosen according to:
in the LTC3833 and external component values. Note that
ITH is close to 2.4V when in current limit.
An external resistive divider from INTV can be used
CC
VOUT
f • ∆IL(MAX)
VOUT
L =
• 1−
to set the voltage on the V
pin between ±.ꢀV and 2V,
RNG
V
IN(MAX)
resulting in maximum sense voltages between 3±mV and
1±±mV. The wide voltage sense range allows for a variety
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
tolerate the core loss of low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy
or Kool Mμ cores. Ferrite core material saturates hard,
meaning that inductance collapses abruptly when the
peak design current is exceeded. This results in an abrupt
increase in inductor ripple current and consequent output
voltage ripple. Do not allow the core to saturate!
of applications. The V
pin can also be tied to either
RNG
SGND or INTV to force internal defaults. When V
is
CC
RNG
tied to SGND, the device operates with a maximum sense
voltage of 3±mV. When the V pin is tied to INTV , the
RNG
CC
device operates with a maximum sense voltage of ꢁ±mV.
R
Inductor °urrent Sensing
SENSE
A typical R
inductor current sensing scheme is
SENSE
SENSE
showninFigure3. R
ischosenbasedontherequired
A variety of inductors designed for high current, low volt-
ageapplicationsareavailablefrommanufacturerssuchas
Sumida, Panasonic, Coiltronics, Coilcraft, Toko, Vishay,
Pulse and Wurth.
maximum output current. Given the maximum current,
,maximumsensevoltage,V ,setbythe
I
OUT(MAX)
SENSE(MAX)
V
pin, and maximum inductor ripple current, ∆I
,
RNG
L(MAX)
the value of R
can be chosen as:
SENSE
VSENSE(MAX)
°urrent Sense Pins and °urrent Limit Programming
RSENSE
=
∆IL(MAX)
+
Inductor current is sensed through the SENSE and
IOUT(MAX)
–
–
SENSE pins and fed into the internal current compara-
2
tors. The common mode input voltage range of the cur-
rent comparators is –±.ꢁV to ꢁ.ꢁV. Both SENSE pins are
high impedance inputs. When the common mode range
is between –±.ꢁV to 1.1V, there is no input bias current,
and when between 1.4V and ꢁ.ꢁV, there is less than 1μA
of current flowing into the pins. Between 1.1V and 1.4V,
the input bias current will be zero if the common mode
voltage is ramped up from 1.1V and less than 1μA if the
common mode voltage is ramped down from 1.4V. The
high impedance inputs to the current comparator allow
accurate DCR sensing. However, care must be taken not
to float these pins during normal operation.
Conversely, given R
and I
, V
OUT(MAX) SENSE(MAX)
SENSE
and thus the V
voltage could be determined from the
RNG
above equation. To assure that the maximum rated output
current can be supplied for different operating conditions
andcomponentvariations,sufficientdesignmarginshould
be built into these calculations.
R
RESISTOR
SENSE
AND
PARASITIC INDUCTANCE
R
ESL
V
OUT
LTC3833
ThemaximumallowedsensevoltageV
between
SENSE(MAX)
R
R
+
–
F
SENSE and SENSE is set by the voltage applied to the
pin and is given by:
+
–
SENSE
V
C
RNG
F
F
3833 F03
SENSE
V
= 0.05 • V
RNG
SENSE(MAX)
FILTER COMPONENTS
PLACED NEAR SENSE PINS
The current mode control loop does not allow the induc-
tor current valleys to exceed 0.05 • V . In practice, one
RNG
Figure 3. RSENSE °urrent Sensing
should allow sufficient margin to account for variations
3833f
15
LTC3833
APPLICATIONS INFORMATION
BecauseofpossiblePCBnoiseinthecurrentsensingloop,
loss through a sense resistor would cost several points
of efficiency compared to DCR sensing.
the current ripple of ∆V
= ∆I • R
also needs
SENSE
L
SENSE
to be checked in the design to get a good signal-to-noise
The inductor DCR is sensed by connecting an RC filter
across the inductor. This filter typically consists of one
or two resistors (R1 and R2) and one capacitor (C1) as
showninFigure4.IftheexternalR1||R2•C1timeconstant
is chosen to be exactly equal to the L/DCR time constant,
the voltage drop across the external capacitor is equal
to the voltage drop across the inductor DCR multiplied
by R2/(R1 + R2). Therefore, R2 may be used to scale
the voltage across the sense terminals when the DCR is
greater than the target sense resistance. With the ability
ratio. In general, for a reasonably good PCB layout, a
1±mV∆V
voltageisrecommendedasaconservative
number to start with, either for R
applications.
SENSE
or DCR sensing
SENSE
For today’s highest current density solutions the value of
the sense resistor can be less than 1mΩ and the maxi-
mum sense voltage can be as low as 3±mV. In addition,
inductor ripple currents greater than ꢁ±7 with operation
up to 2MHz are becoming more common. Under these
conditions, the voltage drop across the sense resistor’s
parasitic inductance becomes more relevant. A small RC
filter placed near the IC has been traditionally used to re-
duce the effects of capacitive and inductive noise coupled
in the sense traces on the PCB. A typical filter consists of
two series 1±Ω resistors connected to a parallel 1±±±pF
capacitor, resulting in a time constant of 2±ns.
to program current limit through the V
pin, R2 may
RNG
be optional. C1 is usually selected to be in the range of
±.±1μF to ±.46μF. This forces R1|| R2 to around 2k to 4k,
reducing error that might have been caused by the SENSE
pins’ input bias currents.
The first step in designing DCR current sensing is to
determine the DCR of the inductor. Where provided, use
themanufacturer’smaximumvalue, usuallygivenat2ꢁ°C.
Increase this value to account for the temperature coef-
ficient of resistance, which is approximately ±.47/°C. A
The filter components need to be placed close to the IC.
The positive and negative sense traces need to be routed
as a differential pair and Kelvin (4-wire) connected to the
sense resistor.
conservative value for inductor temperature T is 1±±°C.
L
TheDCRoftheinductorcanalsobemeasuredusingagood
RLC meter, but the DCR tolerance is not always the same
and varies with temperature; consult the manufacturers’
datasheets for detailed information.
D°R Inductor °urrent Sensing
For applications requiring higher efficiency at high load
currents, the LTC3833 is capable of sensing the voltage
drop across the inductor DCR, as shown in Figure 4.
The DCR of the inductor represents the small amount of
DC winding resistance, which can be less than 1mΩ for
today’s low value, high current inductors. In a high cur-
rent application requiring such an inductor, conduction
From the DCR value, V
is calculated as:
SENSE(MAX)
VSENSE(MAX) = DCRMAX at 25°C• 1+ 0.4% T
–25°C
(
)
L(MAX)
• IOUT(MAX) – ∆IL/2
If V
is within the maximum sense voltage of
SENSE(MAX)
the LTC3833 as programmed by the V
pin (3±mV to
RNG
INDUCTOR
1±±mV), thentheRCfilteronlyneedsR1. IfV
is
L
DCR
SENSE(MAX)
V
OUT
higher, then R2 may be used to scale down the maximum
C
OUT
L/DCR = (R1||R2) C1
R1
LTC3833
sense voltage so that it falls within range.
+
–
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
SENSE
R2
(OPT)
C1
3833 F04
SENSE
C1 NEAR SENSE PINS
V
IN(MAX) – VOUT • V
(
)
OUT
P
R1 =
LOSS ( )
Figure 4. D°R °urrent Sensing
R1
3833f
16
LTC3833
APPLICATIONS INFORMATION
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
The MOSFET power dissipations at maximum output
current are given by:
2
PTOP = DTOP •IOUT(MAX)2 •RDS(ON)(MAX) 1+ δ + V
(
)
IN
R
sensing. Light load power loss can be modestly
SENSE
I
RTG(HI)
RTG(LO)
OUT(MAX)
higher with a DCR network than with a sense resistor due
totheextraswitchinglossesincurredthroughR1.However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
•
•CMILLER
+
• f
2
V
INTVCC – VMILLER
V
MILLER
2
P
= D
• I
• R
(1 + δ)
BOT
BOT OUT(MAX)
DS(ON)(MAX)
whereD andD arethedutycyclesofthetopMOSFET
TOP
BOT
andbottomMOSFETrespectively, δ isthetemperaturede-
To maintain a good signal-to-noise ratio for the current
pendency of R , R is the TG pull-up resistance,
DS(ON) TG(HI)
is the TG pull-down resistance. V
sense signal, use a minimum ∆V
of 1±mV. For a
DCR sensing application, the actual ripple voltage will be
determined by:
SENSE
and R
is the
TG(LO)
MILLER
Miller effect V voltage and is taken graphically from the
GS
MOSFET’s data sheet.
V – VOUT VOUT
IN
2
∆VSENSE
=
•
BothMOSFETshaveI RlosseswhilethetopsideN-channel
R1•C1 V • f
IN
equation includes an additional term for transition losses,
which are highest at high input voltages. For V < 2±V,
IN
Power MOSFET Selection
the high current efficiency generally improves with larger
MOSFETs, while for V > 2±V, the transition losses rapidly
IN
Two external power MOSFETs must be selected for the
LTC3833 controller: one N-channel MOSFET for the top
(main) switch and one N-channel MOSFET for the bottom
(synchronous) switch. The peak-to-peak drive levels are
increasetothepointthattheuseofahigherR
device
DS(ON)
withlowerC
actuallyprovideshigherefficiency.The
MILLER
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
short-circuit when the synchronous switch is on close to
1±±7 of the period.
set by the INTV voltage. This voltage is typically ꢁ.3V.
CC
Consequently, logic-level threshold MOSFETs must be
used in most applications. Pay close attention to the
BV
specification for the MOSFETs as well; most of the
The term (1 + δ) is generally given for a MOSFET in the
DSS
logic-level MOSFETs are limited to 3±V or less. Selection
form of a normalized R
vs temperature curve, but
DS(ON)
criteria for the power MOSFETs include the on-resistance,
δ = 0.005/°C • (T – T ) can be used as an approximation
J
A
R
DS(ON)
, Miller capacitance, C , input voltage and
MILLER
for low voltage MOSFETs (T is estimated junction tem-
perature of the MOSFET and T is ambient temperature).
J
maximum output current. Miller capacitance, C
,
MILLER
A
can be approximated from the gate charge curve usu-
° and °
Selection
ally provided on the MOSFET manufacturers’ data sheet.
IN
OUT
C
is equal to the increase in gate charge along the
MILLER
Incontinuousmode, thesourcecurrentofthetopN-chan-
horizontal axis where the curve is approximately flat, di-
vided by the specified change in V . This result is then
nel MOSFET is a square wave of duty cycle V /V . To
OUT IN
DS
preventlargevoltagetransients, alowESRinputcapacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
multiplied by the ratio of the application V to the gate
DS
charge curve specified V . When the IC is operating in
DS
continuous mode, the duty cycles for the top and bottom
MOSFETs are given by:
VOUT
V
VOUT
IN
IRMS ≅ IOUT(MAX)
•
•
–1
V
VOUT
IN
Main Switch Duty Cycle D
=
(
)
TOP
V
IN
This formula has a maximum at V = 2V , where I
IN OUT RMS
= I
/2. This simple worst-case condition is com-
VOUT
OUT(MAX)
Synchronous Switch Duty Cycle D
= 1–
(
)
BOT
monlyusedfordesignbecauseevensignificantdeviations
V
IN
3833f
17
LTC3833
APPLICATIONS INFORMATION
do not offer much relief. Note that capacitor manufactur-
ers’ ripple current ratings for electrolytic and conductive
polymer capacitors are often based on only 2±±± hours of
life. This makes it advisable to further derate the capacitor
or to choose a capacitor rated at a higher temperature
than required.
have low ESL (and correspondingly higher self resonant
frequencies) to be placed in parallel with larger value
capacitors that have higher ESL. This will ensure good
noise and EMI filtering in the entire frequency spectrum
of interest. Even though ceramic capacitors generally
have good high frequency performance, small ceramic
capacitors may still have to be parallel connected with
large ones to optimize performance.
The selection of C
is primarily determined by the effec-
OUT
tiveseriesresistance, ESR, tominimizevoltageripple. The
outputripple,∆V ,incontinuousmodeisdeterminedby:
OUT
Top MOSFET Driver Supply (° , D )
B
B
1
Anexternalbootstrapcapacitor,C ,connectedtotheBOOST
B
∆VOUT ≤ ∆IL RESR
+
pinsuppliesthegatedrivevoltageforthetopsideMOSFET.
8• f •COUT
This capacitor is charged through diode D from INTV
B
CC
The output ripple is highest at maximum input voltage
when the switch node is low. When the top MOSFET turns
since ∆I increases with input voltage. Typically, once the
on, the switch node rises to V and the BOOST pin rises to
L
IN
ESR requirement for C
has been met, the RMS current
approximately V + INTV . The boost capacitor needs to
OUT
IN
CC
ratinggenerallyfarexceedsthepeak-to-peakcurrentripple
requirement. The choice of using smaller output capaci-
tance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage.
storeapproximately1±±timesthegatechargerequiredby
thetopMOSFET.Inmostapplicationsa±.1μFto±.46μF,XꢁR
orX6Rdielectriccapacitorisadequate.Itisrecommended
that the BOOST capacitor be no larger than 1±7 of the
INTV capacitor, C , to ensure that the C can supply
CC
VCC
VCC
theupperMOSFETgatechargeandBOOSTcapacitorunder
all operating conditions. Variable frequency in response
to load steps offers superior transient performance but
requires higher instantaneous gate drive. Gate charge
demands are greatest in high frequency low duty factor
applications under high dI/dt load steps and at start-up.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramiccapacitorsareallavailableinsurfacemountpack-
ages. Special polymer capacitors offer very low ESR but
havelowercapacitancedensitythanothertypes.Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
foruseinswitchingpowersupplies.Aluminumelectrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
Ceramic capacitors have excellent low ESR characteris-
tics but can have a high voltage coefficient and audible
piezoelectriceffects.ThehighQofceramiccapacitorswith
traceinductancecanalsoleadtosignificantringing. When
used as input capacitors, care must be taken to ensure
that ringing from inrush currents and switching does not
pose an overvoltage hazard to the power switches and
controller.
In order to minimize SW node ringing and EMI, connect a
ꢁΩ to 1±Ω resistor in series with the BOOST pin. Make the
C andD connectionsontheothersideoftheresistor.This
B
B
seriesresistorhelpstoslowdowntheTGrisetime,limiting
thehighdI/dtcurrentthroughthetopMOSFETthatcauses
SW node ringing.
INTV Regulator and EXTV Power
°°
°°
The LTC3833 features a PMOS low dropout linear regu-
lator (LDO) that supplies power to INTV from the V
CC
IN
supply. INTV powers the gate drivers and much of the
CC
LTC3833’sinternalcircuitry.TheLDOregulatesthevoltage
at the INTV pin to ꢁ.3V.
CC
The LDO can supply a maximum current of ꢁ±mA
and
RMS
Forhighswitchingfrequencies,reducingoutputrippleand
betterEMIfilteringmayrequiresmall-valuecapacitorsthat
must be bypassed to ground with a minimum of 4.6μF
ceramic capacitor. Good bypassing is needed to supply
3833f
18
LTC3833
APPLICATIONS INFORMATION
the high transient currents required by the MOSFET gate
drivers.
However, for 3.3V and other low voltage outputs, addi-
tional circuitry is required to derive EXTV power from
CC
the regulator output.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3833 to be
exceeded, especially if the LDO is active and provides
The following list summarizes the four possible connec-
tions for EXTV :
CC
1. EXTV leftopen(orgrounded).ThiswillcauseINTV
CC
CC
INTV . Power dissipation for the IC in this case is high-
CC
to be powered from the internal ꢁ.3V LDO resulting
in an efficiency penalty of up to 1±7 at high input
voltages.
est and is approximately equal to V • I
. The gate
IN INTVCC
charge current is dependent on operating frequency as
discussed in the Efficiency Considerations section. The
junction temperature can be estimated by using the equa-
tions given in Note 2 of the Electrical Characteristics. For
2. EXTV connecteddirectlytoswitchingregulatoroutput
CC
V
> 4.ꢀV. This provides the highest efficiency.
OUT
example, when using the LDO, LTC3833’s INTV current
CC
3. EXTV connected to an external supply. If a 4.ꢀV or
CC
islimitedtolessthan38mAfroma38VsupplyatT =6±°C
A
greater external supply is available, it may be used to
in the FE package:
power EXTV providing that the external supply is
CC
sufficient enough for MOSFET gate drive requirements.
T = 6±°C + (38mA)(38V)(38°C/W) ≈ 12ꢁ°C
J
4. EXTV connected to an output-derived boostnetwork.
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode at maximum
CC
For 3.3V and other low voltage converters, efficiency
gains can still be realized by connecting EXTV to an
CC
output-derivedvoltagethathasbeenboostedtogreater
V .
IN
than 4.ꢀV.
When the voltage applied to EXTV pin rises above 4.ꢀV,
CC
For applications where the main input power is less than
ꢁ.3V, tie the V and INTV pins together and tie the com-
the INTV LDO is turned off and the EXTV is connected
CC
CC
to INTV with an internal switch. This switch remains on
IN
CC
CC
bined pins to the V input with an optional 1Ω or 2.2Ω
as long as the voltage applied to EXTV remains above
IN
CC
resistor as shown in Figure ꢁ to minimize the voltage drop
caused by the gate charge current. This will override the
INTV LDOandwillpreventINTV fromdroppingtoolow
4.4V. Using the EXTV allows the MOSFET driver and
CC
control power to be derived from the LTC3833’s switching
regulator output during normal operation and from the
LDO when the output is out of regulation (e.g., start-up,
CC
CC
due to the dropout voltage. Make sure the INTV voltage
CC
exceeds the R
test voltage for the external MOSFET
which is typically at 4.ꢁV for logic-level devices.
short circuit). If more than ꢁ±mA
current is required
DS(ON)
RMS
through EXTV , then an external Schottky diode can be
CC
added between the EXTV and INTV pins. Do not apply
CC
CC
more than ꢀV to the EXTV pin and make sure that this
CC
LTC3833
external voltage source is less than V .
IN
INTV
CC
Significant efficiency and thermal gains can be realized
R
VIN
V
V
IN
IN
by powering INTV from the switching regulator output,
CC
C
C
VCC
IN
since the V current resulting from the driver and control
IN
currentswillbescaledbyafactorof(DutyCycle)/(Switcher
Efficiency).
Tying the EXTV pin to a ꢁV supply reduces the junction
3833 F05
CC
temperature in the previous example from 12ꢁ°C to:
Figure 5. Setup for VIN ≤ 5V
T = 6±°C + (38mA)(ꢁV)(38°C/W) ≈ 66°C
J
3833f
19
LTC3833
APPLICATIONS INFORMATION
V Undervoltage Lockout (UVLO)
IN
When the LTC3833 is configured to track another supply,
a voltage divider can be used from the tracking supply to
the TRACK/SS pin to scale the ramp rate appropriately.
Two common implementations of tracking as shown in
Figure ꢀa are coincident and ratiometric. For coincident
tracking, make the divider ratio from the external supply
the same as the divider ratio for the differential feedback
voltage. Ratiometric tracking could be achieved by using
a different ratio than the differential feedback (Figure ꢀb).
Note that the small soft-start capacitor charging current is
alwaysflowing,producingasmalloffseterror.Tominimize
this error, select the tracking resistive divider values to be
small enough to make this offset error negligible.
The LTC3833 has two functions that help protect the con-
trollerincaseofinputundervoltageconditions.Aprecision
UVLOcomparatorconstantlymonitorstheINTV voltage
CC
to ensure that an adequate gate-drive voltage is present.
The comparator enables UVLO and locks out the switch-
ing action until INTV rises above 4.2V. Once UVLO is
CC
released, the comparator does not retrigger UVLO until
INTV falls below 3.ꢀꢁV. This hysteresis prevents oscil-
CC
lations when there are disturbances on INTV .
CC
Another way to detect an undervoltage condition is to
monitortheV supply.BecausetheRUNpinhasaprecision
IN
turn-onvoltageof1.2V, onecanusearesistordividerfrom
V toturnontheICwhenV ishighenough. TheRUNpin
Phase and Frequency Synchronization
IN
IN
has bias currents that depend on the RUN voltage as well
For applications that require better control of EMI and
switchingnoiseorhavespecialsynchronizationneeds,the
LTC3833canphaseandfrequencysynchronizetheturn-on
of the top MOSFET to an external clock signal applied to
the MODE/PLLIN pin. The applied clock signal needs to
be within ±3±7 of the RT pin programmed free-running
frequency to assure proper frequency and phase lock.
asV voltage.Thesebiascurrentsshouldbetakenintoac-
IN
countwhendesigningthevoltagedividerandUVLOcircuit
to prevent faulty conditions. Generally for RUN < 3V a bias
current of 1.3μA flows out of the RUN pin, and for RUN >
3V, correspondingly increasing current flows into the pin,
reachingamaximumofabout3ꢁμAforRUN=ꢀV.
The clock signal levels should generally comply to V >
IH
Soft-Start and Tracking
2V and V < ±.ꢁV. The MODE/PLLIN pin has an internal
IL
The LTC3833 has the ability to either soft-start by itself
with a capacitor or track the output of an external supply.
Soft-start or tracking features are achieved not by limiting
the maximum output current of the switching regulator
but by controlling the regulator’s output voltage according
to the ramp rate on the TRACK/SS pin.
ꢀ±±k pull-down resistor to ensure pulse-skipping mode
if the pin is left floating.
The LTC3833 uses the voltages on V and V
pins as
OUT
IN
well as the RT programmed frequency to determine the
steady-state on-time as follows:
VOUT
When configured to soft-start by itself, a capacitor should
be connected to the TRACK/SS pin. TRACK/SS is pulled
low until the RUN pin voltage exceeds 1.2V and UVLO is
released, atwhichpointaninternalcurrentof1μA charges
tON
≈
V • f
IN
An internal PLL system adjusts this on-time dynamically
in order to maintain phase and frequency lock with the
external clock. The LTC3833 will maintain phase and fre-
the soft-start capacitor, C , connected to TRACK/SS.
SS
Current foldback is disabled during this phase to ensure
smooth soft-start or tracking. The soft-start or tracking
range is defined to be the voltage range from ±V to ±.ꢀV
on the TRACK/SS pin. The total soft-start time can be
calculated as:
quency lock under steady-state conditions for V , V
IN OUT
and load current.
As shown in the previous equation, the top MOSFET on-
time is a function of the switching regulator’s output. This
outputismeasuredbytheV
pinandisusedtocalculate
OUT
CSS
tSOFTSTART = 0.6V •
1µA
the required on-time. Therefore, simply connecting V
OUT
to the regulator’s local output point is preferable for most
applications. However, there could be applications where
3833f
20
LTC3833
APPLICATIONS INFORMATION
EXTERNAL
SUPPLY
EXTERNAL
SUPPLY
V
V
OUT
OUT
3833 F06
TIME
TIME
Ratiometric Tracking
Coincident Tracking
Figure 6a. Two Different Modes of Output Tracking
EXT. V
V
EXT. V
V
OUT
OUT
R
R
R
R
R1
R
R
FB2
FB1
FB2
FB2
R2
R1+ R2 EXT. V
R2
0.6V
TO
TRACK/SS
TO
TRACK/SS
+
–
+
–
≥
TO V
TO V
OSNS
OSNS
OSNS
OSNS
FB1
FB1
TO V
TO V
3833 F06b
Coincident Tracking Setup
Ratiometric Tracking Setup
Figure 6b. Setup for °oincident and Ratiometric Tracking
the internally calculated on-time differs significantly from
the real on-time required by the application. For example,
if there are differences between the local output point and
theremotelyregulatedoutputpointduetolinelosses,then
the internally calculated on-time will be inaccurate. Lower
efficiencies in the switching regulator can also cause the
realon-timetobesignificantlydifferentfromtheinternally
calculated on-time (see Efficiency Considerations). For
application and therefore maintain constant frequency
operation.
If the application requires very low on-times approaching
minimum on-time, the PLL system may not be able to
maintain a ±3±7 synchronization range. In fact, there is
a possibility of losing phase/frequency lock at minimum
on-time, and definitely losing phase/frequency lock for
applications requiring less than minimum on-time. This
is discussed further under Minimum On-Time, Minimum
Off-Time and Dropout Operation.
these circumstances, the voltage on the V
pin can
OUT
be programmed with a resistive divider from INTV or
CC
from the regulator’s output itself. Note that there is a ꢁ±±k
During dynamic transient conditions either in the line or
load (e.g., load step or release), the LTC3833 may lose
phaseandfrequencylockintheprocessofachievingfaster
transient response. For large slew rates (e.g., 1±A/µs),
phase and frequency lock will be lost (see Figure 6) until
the system returns back to a steady-state condition at
which point the device will resume frequency lock and
eventually achieve phase lock to the external clock. For
relatively small slew rates (1±A/s), phase and frequency
lock can still be maintained.
nominal resistance looking into the V
pin.
OUT
The PLL adjusted on-time achieved after phase locking is
the steady-state on-time required by the switching regula-
tor, and if the V
programmed on-time is substantially
OUT
equal to this steady-state on-time, then the PLL system
does not have to use its ±3±7 frequency lock range for
systematiccorrections.Insteadthelockrangecanbeused
tocorrectforcomponentvariationsorotheroperatingpoint
conditions. If needed, the V
pin can be programmed
OUT
to achieve the steady-state on-time as required by the
3833f
21
LTC3833
APPLICATIONS INFORMATION
I
LOAD
CLOCK
INPUT
PHASE LOCKED
ESTABLISHES
FREQUENCY
LOCK SOON
ESTABLISHES
PHASE LOCK
AFTER ~600µs
LOSES PHASE
LOCK DUE TO
FAST LOAD
RELEASE
ESTABLISHES
FREQUENCY
LOCK SOON
LOSES PHASE
LOCK DUE
TO FAST
LOAD STEP
SW
V
OUT
3833 F07
Figure ꢃ. Phase and Frequency Locking Behavior During Transient Load °onditions
For light loading conditions, the phase and frequency
synchronization will be active if there is a clock input ap-
plied. If there is no clock input during light loading, then
theswitchingfrequencyisbasedonwhattheMODE/PLLIN
wellasoperatingconditionsoftheswitchingregulator.The
effective on-time is defined as the time period that the SW
node stays high and this period can be different from the
time period that the top MOSFET’s gate stays high. One
of the factors that contributes to this discrepancy is the
on/offswitchingcharacteristicsofthepowerMOSFETs. If,
for example, the power MOSFET’s turn-on delay is much
smaller than the turn-off delay, then the effective on-time
willbelongerthantheMOSFET’sgateturn-on-time,thereby
limiting the minimum on-time to a longer value than that
forced by the LTC3833.
pin is tied to. When MODE/PLLIN is tied to INTV , the
CC
LTC3833 will operate in forced continuous mode at the RT
programmedfree-runningfrequency.WhenMODE/PLLIN
pin is tied to signal ground, the LTC3833 will operate in
pulse-skipping discontinuous conduction mode for light
loading and will switch to continuous conduction (at the
free-running frequency) for normal and heavy loads.
Light loading operation in forced continuous mode will
also elongate the effective minimum on-time, as shown
in Figure 8. At light loading, the dead times between the
top MOSFET switching on/off and the bottom MOSFET
switching on/off add to the intrinsic on-time of the top
MOSFET. In forced continuous light loading, when the
inductor current flows in the reverse direction, the SW
node is pre-biased high during the dead time from the
bottom FET turning off to the top FET turning on. On the
other edge, when the top MOSFET turns off and before
the bottom MOSFET turns on, the SW node lingers high
for a longer duration of time due to a smaller magnitude
of inductor current available in light loading to pull the
SW node low.
Minimum On-Time, Minimum Off-Time
and Dropout Operation
The minimum on-time is the smallest duration of time
in which the LTC3833 can keep the top power MOSFET’s
gate (TG) in its on state. This minimum on-time is 2±ns
for the LTC3833 and is achieved when the V
pin is
OUT
IN
tied to its minimum value of ±.ꢀV while the V is tied to
its maximum value of 38V. For larger values of V
or
OUT
smaller values of V , the minimum on-time achievable
IN
will be longer than 2±ns. The minimum on-time will have
adependencyontheoperatingconditionsoftheswitching
regulator, but is intended to be smaller for high step-down
ratio applications that will require low on-times.
The effective minimum on-time of the switching regula-
tor, however, will depend also on external components
(especially the characteristics of the power MOSFETs) as
Incontinuousmodeoperation, theminimumon-timelimit
imposes a minimum duty cycle of:
D
MIN
= f • t
ON(MIN)
3833f
22
LTC3833
APPLICATIONS INFORMATION
TG-SW
then immediately turned back on. This minimum off-time
includes the time to turn on the bottom power MOSFET’s
gate and turn it back off along with the dead time delays
from top MOSFET off to bottom MOSFET on and bottom
MOSFET off to top MOSFET on. The minimum off-time
that the LTC3833 can achieve is 9±ns.
(V OF
GS
TOP MOSFET)
DEAD-TIME
DELAYS
BG
(V OF
GS
BOTTOM MOSFET)
I
L
0
The effective minimum off-time of the switching regulator
is defined as the shortest period of time that the SW node
can stay low. This effective minimum off-time can vary
from the LTC3833’s 9±ns of minimum off-time. The main
factor impacting the effective minimum off-time is the top
andbottompowerMOSFETs’gatechargingcharacteristics,
NEGATIVE
INDUCTOR
CURRENT
IN FCM
V
IN
SW
3833 F08
DURING BG-TG DEAD TIME,
DURING TG-BG DEAD TIME,
THE RATE OF SW NODE DISCHARGE
WILL DEPEND ON THE CAPACITANCE
ON THE SW NODE AND INDUCTOR
CURRENT MAGNITUDE
NEGATIVE INDUCTOR CURRENT
WILL FLOW THROUGH TOP MOSFET’S
BODY DIODE TO PRECHARGE SW NODE
including Q and turn-on/off delays. These characteristics
g
can either extend or shorten the SW node’s minimum
off-timeascomparedtotheLTC3833’sminimumoff-time.
+
V
I
L
IN
–
Large size (high Q ) power MOSFETs generally tend to
g
increase the effective minimum off-time due to longer
gate charging and discharging times. On the other hand,
imbalances in turn-on and turn-off delays could reduce
the effective minimum off-time.
L
L
SW
I
L
TOTAL CAPACITANCE
ON THE SW NODE
The minimum off-time limit imposes a maximum duty
cycle of:
Figure 8. Light Loading On-Time Extension with Forced
°ontinuous Mode Operation
D
MAX
= 1 – f • t
OFF(MIN)
where t
is the effective minimum on-time for the
where t
is the effective minimum off-time of the
ON(MIN)
OFF(MIN)
switching regulator. As the equation shows, reducing the
operating frequency will alleviate the minimum duty cycle
constraint.
switching regulator. Reducing the operating frequency al-
leviatesthemaximumdutycycleconstraint.Ifthemaximum
duty cycle is reached, due to a drooping input voltage for
example, then the output will drop out of regulation. The
minimum input voltage to avoid dropout is:
If the application requires a smaller than minimum duty
cycle, the output voltage will still remain in regulation, but
theswitchingfrequencywilldecreasefromitsprogrammed
valueorlosefrequencysynchronizationifusinganexternal
clock. Depending on the application, this may not be of
critical importance.
VOUT
DMAX
V
=
IN(MIN)
At the onset of dropout, there is a region of V about
IN
ꢁ±±mV that generates two discrete off-times, one being
the minimum off-time and the other being an off-time that
is about 4±ns to ꢀ±ns larger than the minimum off-time.
This secondary off-time is due to the longer delay in trip-
ping the internal current comparator. The two off-times
average out to the required duty cycle to keep the output
in regulation with the output ripple remaining the same.
However, there is higher SW node jitter, especially appar-
ent when synchronized to an external clock. Depending
For applications that require relatively low on-times,
proper caution has to be taken when choosing the top
power MOSFET. If a high Q MOSFET is chosen such that
g
the on-time is not sufficient to fully turn the MOSFET on,
there will be significant losses in efficiency as a result
of larger R
resistance and possibly failure of the
DS(ON)
MOSFET due to significant heat dissipation.
The minimum off-time is the smallest duration of time
that the top power MOSFET’s gate can be turned off and
on the application, this may not be of critical importance.
3833f
23
LTC3833
APPLICATIONS INFORMATION
Fault °onditions: °urrent Limiting and Overvoltage
step,risetimeandsettlingatthistestpointtrulyreflectsthe
closed-loop response. Assuming a predominantly second
ordersystem, phasemarginand/ordampingfactorcanbe
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at this pin.
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3833, the maximum sense voltage is controlled
by the voltage on the V
pin. With valley current mode
RNG
control, the maximum sense voltage and the sense re-
sistance determine the maximum allowed inductor valley
current. The corresponding output current limit is:
TheITHseriesR -C
filtersetsthedominantpole-zero
ITH ITH1
loop compensation. Additionally, a small capacitor placed
from the ITH pin to SGND, C , may be required to at-
ITH2
VSENSE(MAX)
1
2
tenuate high frequency noise. The values can be modified
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selectedbecausetheirvarioustypesandvaluesdetermine
theloopfeedbackfactorgainandphase. Anoutputcurrent
pulse of 2±7 to 1±±7 of full load current having a rise
time of 1μs to 1±μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The general
goal of OPTI-LOOP compensation is to realize a fast but
stable ITH response with minimal output droop due to
the load step. For a detailed explanation of OPTI-LOOP
compensation, refer to Application Note 6ꢀ.
ILIMIT
=
+ • ∆IL
RSENSE
The current limit value should be checked to ensure that
> I . The current limit value should
I
LIMIT(MIN)
OUT(MAX)
be greater than the inductor current required to produce
maximum output power at the worst-case efficiency.
Worst-case efficiency typically occurs at the highest V
IN
and highest ambient temperature. It is important to check
for consistency between the assumed MOSFET junction
temperatures and the resulting value of I
the MOSFET switches.
which heats
LIMIT
To further limit current in the event of a short circuit to
ground, the LTC3833 includes foldback current limiting.
If the output fails by more than ꢁ±7, then the maximum
sensevoltageisprogressivelyloweredtoaboutone-fourth
of its full value.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
im-
OUT
•ESR,where
mediatelyshiftsbyanamountequalto∆I
LOAD
ESR is the effective series resistance of C . ∆I
also
OUT
LOAD
If the output exceeds 6.ꢁ7 of the programmed value,
then it is considered as an overvoltage (OV) condition.
In such a case, the top MOSFET is immediately turned
off and the bottom MOSFET is turned on indefinitely until
the OV condition is removed. Current limiting is not active
during an OV. If the output returns to a nominal level, then
normal operation resumes. If the OV persists a long time,
the current through the bottom MOSFET and inductor
could exceed their maximum ratings.
beginstochargeordischargeC ,generatingafeedback
OUT
error signal used by the regulator to return V
to its
can
OUT
steady-state value. During this recovery time, V
OUT
be monitored for overshoot or ringing that would indicate
a stability problem.
ConnectingaresistiveloadinserieswithapowerMOSFET,
then placing the two directly across the output capacitor
anddrivingthegatewithanappropriatesignalgeneratoris
a practical way to produce a realistic load-step condition.
Theinitialoutputvoltagestepresultingfromthestepchange
in output current may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
phase margin. This is why it is better to look at the ITH
pin signal which is in the feedback loop and is the filtered
and compensated feedback loop response.
OPTI-LOOP °ompensation
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for
a wide range of loads and output capacitors. The ITH pin
not only allows optimization of the control loop behavior
butalsoprovidesatestpointforthestep-downregulator’s
DC-coupledandAC-filteredclosed-loopresponse.TheDC
3833f
24
LTC3833
APPLICATIONS INFORMATION
ThegainoftheloopincreaseswithR andthebandwidth
of one MOSFET can simply by summed with the re-
ITH
of the loop increases with decreasing C
. If R is
sistances of L and the board traces to obtain the DC
ITH1
ITH
2
increased by the same factor that C
is decreased, the
I R loss. For example, if R
= ±.±1Ω and R =
DS(ON) L
ITH1
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
±.±±ꢁΩ, the loss will range from 1ꢁmW to 1.ꢁW as
the output current varies from 1A to 1±A.
feedbackloop.Inaddition,afeedforwardcapacitor,C ,can
FF
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the
inputvoltage,loadcurrent,driverstrengthandMOSFET
capacitance,amongotherfactors.Thelossissignificant
at input voltages above 2±V.
beaddedtoimprovethehighfrequencyresponse,asshown
in Figure 1. Capacitor C provides phase lead by creating
FF
a high frequency zero with R which improves the phase
FB2
margin. The output voltage settling behavior is related to
thestabilityoftheclosed-loopsystemandwilldemonstrate
overall performance of the step-down regulator.
3. INTV current. This is the sum of the MOSFET driver
CC
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>1±μF) input capacitors.
If the switch connecting the load has low resistance and
is driven quickly, then the discharged input capacitors are
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
effectivelyputinparallelwithC , causingarapiddropin
OUT
from INTV to ground. The resulting dQ/dt is a current
CC
V
OUT
. No regulator can deliver enough current to prevent
out of INTV that is typically much larger than the
CC
this problem. The solution is to limit the turn-on speed of
the load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates cur-
rent limiting, short-circuit protection and soft starting.
controller I current. In continuous mode, I
=
Q
GATECHG
f•(Q
+Q
),whereQ
andQ
arethe
g(TOP)
g(BOT)
g(TOP)
g(BOT)
gate charges of the topside and bottom side MOSFETs,
respectively.
Efficiency °onsiderations
Supplying INTV power through EXTV could save
CC CC
severalpointsofefficiency,especiallyforhighV appli-
IN
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 1±±7.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
cations.ConnectingEXTV toanoutput-derivedsource
CC
will scale the V current required for the driver and
IN
controller circuits by a factor of Duty Cycle/Efficiency.
Forexample,ina2±VtoꢁVapplication,1±mAofINTV
CC
current results in approximately 2.ꢁmA of V current.
IN
This reduces the mid-current loss from 1±7 or more
7Efficiency = 1±±7 – (L1 + L2 + L3 + ...)
(if the driver was powered directly from V ) to only a
IN
few percent.
where L1, L2, etc. are the individual losses as a percent-
age of input power. Although all dissipative elements in
the circuit produce losses, four main sources account for
most of the losses:
4. C loss. The input capacitor has the difficult job of
IN
filtering the large RMS input current to the regulator. It
2
must have a very low ESR to minimize the AC I R loss
2
and sufficient capacitance to prevent the RMS current
from causing additional upstream losses in cabling,
fuses or batteries.
1. I R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause
the efficiency to drop at high output currents. In
continuous mode the average output current flows
though the inductor L, but is chopped between the
top and bottom MOSFETs. If the two MOSFETs have
Other losses, which include the C
ESR loss, bottom
OUT
MOSFET reverse-recovery loss and inductor core loss
generally account for less than 27 additional loss.
approximately the same R
, then the resistance
DS(ON)
3833f
25
LTC3833
APPLICATIONS INFORMATION
Whenmakingadjustmentstoimproveefficiency, theinput
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current there is no change in efficiency.
The frequency is programmed by:
41550
f kHz
41550
350
R kΩ =
–2.2=
–2.2≈ 116.5k
[
]
T
[
]
Select the nearest standard value of 11ꢁk.
Power losses in the switching regulator will reflect as a
longer than ideal on-time. This efficiency accounted on-
time in continuous mode can be calculated as:
Theminimumon-timeoccursformaximumV andshould
IN
be greater than 2±ns which is the best that the LTC3833
can achieve. The minimum on-time for this application is:
tON(IDEAL)
VOUT
IN(MAX) • f 24V •350kHz
1.2V
tON(REAL)
≈
tON(MIN)
=
=
≈ 143ns
Efficiency
V
Design Example
Set the inductor value to give 4±7 ripple current at maxi-
mum V :
Considerastep-downconverterwithV =ꢀVto24V, V
IN
IN
OUT
= 1.2V, I
= 1ꢁA, and f = 3ꢁ±kHz (see Figure 9).
OUT(MAX)
1.2V
1.2V
24V
L =
• 1–
≈ 0.54µH
The regulated output voltage is determined by:
350kHz •40%•15A
RFB2
R
Select ±.ꢁꢀμH which is the nearest standard value.
VOUT = 0.6V • 1+
FB1
+
–
Using a 2±k resistor from V
feedback resistor is also 2±k.
to V
, the top
OSNS
OSNS
INTV
CC
R
V
PGD
100k
IN
6V TO 24V
V
IN
+
C
82µF
25V
IN1
V
C
IN2
10µF
PGOOD
LTC3833
OUT
R
DIV1
Efficiency
52.3k
–
SENSE
100
90
80
70
60
50
40
30
20
V
RNG
C
R
DCR
DCR
PULSE-SKIPPING
MODE
0.1µF
R
3.09k
DIV2
+
10k
SENSE
RUN
350kHz
MT
TG
MODE/PLLIN
EXTV
CC
SW
L1
0.56µH
FORCED
CONTINUOUS
MODE
C
0.1µF
C
B
SS
V
1.2V
15A
OUT
0.1µF
BOOST
TRACK/SS
ITH
R
FB2
20k
D
C
B
C
ITH1
470pF
C
OUT1
C
+
OUT2
INTV
CC
INTV
VCC
4.7µF
R
CC
ITH
330µF
2.5V
×2
100µF
47.5k
×2
R
FB1
20k
MB
BG
C
47pF
ITH2
V
V
= 12V
IN
OUT
= 1.2V
PGND
+
R
115k
T
0.1
1
10
100
LOAD CURRENT (A)
V
V
RT
SGND
OSNS
–
3833 F09b
OSNS
3833 F09
C
: SANYO 25SVPD82M
OUT1
L1: VISHAY IHLP4040DZ-056µH
MB: RENESAS RJK0330DPB
MT: RENESAS RJK0305DPB
IN1
C
: SANYO 2R5TPE330M9
D : CENTRAL CMDSH-3
B
Figure 9. 1.ꢀV, 15A, 350kHz Step-Down °onverter
3833f
26
LTC3833
APPLICATIONS INFORMATION
The resulting maximum ripple current is:
top MOSFET (main switch), and RJK±33±DBP (R
DS(ON)
= 3.9mΩ max, V = 4.ꢁV, θ = 4±°C/W, T =
GS
JA
J(MAX)
1.2V
350kHz •0.56µH
1.2V
24V
1ꢁ±°C) is chosen for the bottom MOSFET (synchronous
switch). The power dissipation and the resulting junction
∆IL =
• 1–
≈ 5.8A
temperature for each MOSFET can be calculated for V
IN
Often in high power applications, DCR current sensing is
preferred over R in order to maximize efficiency. In
= 24V and T = 6ꢁ°C:
A
SENSE
1.2V
24V
2
2
order to determine the DCR filter values, first the induc-
tor manufacturer has to be chosen. For this design, the
Vishay IHLP-4±4±DZ-±1 model is chosen with a value of
PTOP
=
• 15A 13mΩ 1+ 0.4 + 24V
(
) (
)(
) (
)
15A
2
2.5Ω
5.3V –3V 3V
1.2Ω
•
150pF
+
350kHz
(
)
±.ꢁꢀμH and DCR
=1.8mΩ. This implies that:
MAX
≈ 0.54W
V
= DRC
at 25°C • [1 + 0.4% (T
SENSE(MAX)
MAX L(MAX)
– 25°C)] • [I
– ∆I /2]
L
40°C
W
OUT(MAX)
TJ(TOP) = 75°C+ 0.54W
≈ 97°C
(
)
= 1.8mΩ • [1 + 0.4% (100°C – 25°C)] •
[15A – 5.8A/2]
24V –1.2V
24V
2
P
=
15A 3.9mΩ 1+ 0.4 ≈ 1.2W
(
) (
)(
)
BOT
≈ 28.3mV
40°C
W
TJ(BOT) = 75°C+ 1.2W
= 123°C
(
)
The maximum sense voltage is within the range that
LTC3833canhandlewithoutanyadditionalscaling.There-
fore, the DCR filter consists of a simple RC filter across
the inductor. If the C is chosen to be ±.1µF, then the R can
be calculated as:
These numbers show that careful attention should be paid
to proper heat sinking when operating at higher ambient
temperatures.
L
0.56µH
Select C to give an RMS current rating greater than 6A
IN
RDCR
=
=
≈ 3.11k
DCRMAX •CDCR 1.8mΩ •0.1µF
at 6ꢁ°C. The output capacitor C
is chosen for a low
OUT
ESR of 4.ꢁmΩ to minimize output voltage changes due to
inductor ripple current and load steps. The output voltage
ripple is given as:
The closest standard value is 3.±9k.
The resulting value of V
factor is:
with a ꢁ±7 design margin
RNG
∆V
= ∆I
• ESR = (5.8A)(4.5mΩ)
OUT(RIPPLE)
L(MAX)
≈ 2ꢀmV
V
RNG
= V /0.05 • MF
SENSE(MAX)
However, a ±A to 1±A load step will cause an output
change of up to:
= 28.3mV/0.05 • 1.5 ≈ 850mV
To generate the V
voltage, connect a resistive divider
RNG
∆V
= ∆I
• ESR = (10A)(4.5mΩ) = 45mV
OUT(STEP)
LOAD
from INTV to SGND with R
= ꢁ2.3k and R
=
DIV2
CC
DIV1
1±k.
Optional 1±±μF ceramic output capacitors are included to
minimize the effect of ESR and ESL in the output ripple
and to improve load step response.
For the external N-channel MOSFETs, Renesas RJK-
±3±ꢁDBP (R = 13mΩ max, C = 1ꢁ±pF, V
GS
DS(ON)
= 4.ꢁV, θ = 4±°C/W, T
MILLER
= 1ꢁ±°C) is chosen for the
JA
J(MAX)
3833f
27
LTC3833
APPLICATIONS INFORMATION
P° Board Layout °hecklist
• Place BOOST, TG, SW, BG and PGND pins facing the
power train components. Keep high dV/dt signals on
BOOST,TG,SWandBGawayfromsensitivesmall-signal
traces and components.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3833.
•
For RSENSE current sensing, place the sense resistor
close to the inductor on the output side. Use a Kelvin
(4-wire) connection across the sense resistor and
route the traces together as a differential pair. RC filter
the differential sense signal close to SENSE+/SENSE–
pins, placing the filter capacitor as close as possible
to the pins. For DCR sensing, Kelvin connect across
the inductor and place the DCR sensing resistor closer
to the SW node and further away from the SENSE+/
SENSE– pins. Place the DCR capacitor close to the
SENSE+/SENSE– pins.
• Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking
purposes. Use wide rails and/or entire planes for V ,
IN
V
and PGND nodes for good filtering and minimal
OUT
copper loss. If a ground layer is used, then it should
be immediately below (and/or above) the routing layer
for the power train components which consist of C ,
IN
power MOSFETs, inductor, sense resistor (if used) and
C
. Flood unused areas of all layers with copper for
OUT
better heat sinking.
• Keep signal and power grounds separate except at the
point where they are shorted together. Short signal and
power ground together only at a single point with a nar-
row PCB trace (or single via in a multilayer board). All
powertraincomponentsshouldbereferencedtopower
• Place the resistive feedback divider R
as close as
FB1/2
+
–
possible to V
/V
pins and route the remote
OSNS
OSNS
output and ground traces together as a differential
pair and terminate as close to the regulation point as
possible(preferablyKelvinconnectacrossthecapacitor
at the remote output point).
ground and all small-signal components (e.g., C
,
ITH1
R , C etc.) should be referenced to signal ground.
T
SS
• Place the ceramic C
capacitor as close as possible
VCC
• Place C , power MOSFETs, inductor, sense resistor (if
IN
to INTV and PGND pins. Likewise, the C capacitor
CC
B
used), and primary C
capacitors close together in
OUT
should be as close as possible to BOOST and SW pins.
Thesecapacitorsprovidethegatechargingcurrentsfor
the power MOSFETs.
one compact area. The SW node should be compact
but be large enough to handle the inductor currents
without large copper losses. Connect the drain of the
topside MOSFET as close as possible to the (+) plate of
• Placesmall-signalcomponentsasclosetotheirrespec-
tive pins as possible. This minimizes the possibility of
PCB noise coupling into these pins. Give priority to
C capacitor(s)thatprovidesthe bulkoftheAC current
IN
(these are normally the ceramic capacitors), and con-
SENSE+/SENSE–, ITH, RT and V
+
–
nect the source of the bottom side MOSFET as close as
V
/V
,
OSNS
OSNS RNG
possibletothe(–)terminalofthesameC capacitor(s).
pins.Usesufficientisolationwhenroutingaclocksignal
into MODE/PLLIN pin so that the clock does not couple
into sensitive small-signal pins.
IN
The high dI/dt loop formed by C , the top MOSFET,
IN
and the bottom MOSFET should have short leads and
PCB trace lengths to minimize high frequency EMI and
voltage stress from inductive ringing. The (–) terminal
• Filter the V input to the LTC3833 with a simple RC
IN
filter close to the pin. The RC filter should be referenced
to signal ground.
of the primary C
capacitor(s) which filter the bulk
OUT
of the inductor ripple current (these are normally the
ceramic capacitors) should also be connected close to
the (–) terminal of C .
IN
3833f
28
LTC3833
APPLICATIONS INFORMATION
INTV
R
VIN
2.2Ω
CC
V
IN
V
IN
4.5V TO 14V
+
C
C
IN1
180µF
16V
IN2
C
VIN
22µF
R
LTC3833
0.1µF
PGD
×2
100k
V
PGOOD
OUT
R
F2
10Ω
–
SENSE
SENSE
C
F
R
F1
1000pF
10Ω
+
RUN
MT
L1
0.47µH
V
TG
SW
RNG
R
SENSE
MODE/PLLIN
1.5mΩ
V
1.5V
20A
OUT
EXTV
CC
BOOST
C
OUT2
R
FB2
D
B
C
B
0.1µF
100µF
C
SS
0.1µF
15k
×2
INTV
CC
INTV
CC
TRACK/SS
ITH
C
OUT1
+
R
FB1
C
47pF
330µF
ITH2
C
VCC
10k
2.5V
×2
4.7µF
C
220pF
MB
ITH1
BG
PGND
+
R
ITH
84.5k
R 137k
T
RT
SGND
V
V
OSNS
OSNS
–
3833 F10a
C
C
: SANYO 16SVP180M
L1: PULSE PA0515.471NLT
MB: RENESAS RJK0330DPB
MT: RENESAS RJK0305DPB
IN1
: SANYO 2R5TPE330M9
OUT1
D : CENTRAL CMDSH-3
B
Efficiency
100
PULSE-SKIPPING
MODE
90
80
70
60
50
40
FORCED
CONTINUOUS
MODE
V
V
= 12V
IN
OUT
= 1.5V
0.1
1
10
100
LOAD CURRENT (A)
3833 F10b
Figure 10. 1.5V, ꢀ0A, 300kHz High °urrent Step-Down °onverter
3833f
29
LTC3833
TYPICAL APPLICATIONS
5V, 8A, ꢀ00kHz High Efficient Step-Down °onverter
R
VIN
2.2Ω
V
IN
V
IN
7V TO 38V
C
+
C
IN2
C
VIN
IN1
INTV
CC
R
10µF
0.1µF
PGD
EXTV
100µF
50V
CC
100k
×3
PGOOD
RUN
V
OUT
–
SENSE
SENSE
C
R
DCR
DCR
0.22µF
5.9k
+
V
RNG
C
SS
LTC3833
MT
TG
0.1µF
L1
6µH
TRACK/SS
SW
V
5V
8A
OUT
C
ITH1
BOOST
R
220pF
ITH
R
B
D
R
FB2
B
86.6k
C
B
10Ω
C
OUT1
147k
C
ITH
+
OUT2
0.1µF
INTV
INTV
CC
CC
330µF
6.3V
×2
100µF
C
VCC
R
205k
T
×2
4.7µF
R
FB1
RT
20k
MB
BG
MODE/PLLIN
PGND
+
OSNS
–
V
V
SGND
OSNS
3833 TA02
C
C
: NICHICON UCJ1H101MCL1GS
L1: COOPER HC2LP-6R0
MB: INFINEON BSC035N04LS
MT: INFINEON BSC035N04LS
IN1
: SANYO 6TPE330MIL
OUT1
D : DIODES INC. SDM10K45
B
Efficiency
100
PULSE-SKIPPING
MODE
95
90
85
80
75
70
FORCED
CONTINUOUS
MODE
V
V
= 12V
OUT
IN
= 5V
0.1
1
10
LOAD CURRENT (A)
3833 TA02b
3833f
30
LTC3833
TYPICAL APPLICATIONS
0.6V, 10A, ꢀ00kHz Low Output Step-Down °onverter
R
VIN
2.2Ω
V
IN
INTV
CC
R
V
IN
4.5V TO 14V
+
C
C
C
IN1
100µF
50V
VIN
IN2
PGD
LTC3833
PGOOD
0.1µF
10µF
100k
×3
V
OUT
–
R
F2
MODE/PLLIN
10Ω
V
SENSE
SENSE
RNG
R
10Ω
C
F1
F
1000pF
+
RUN
C
SS
MT
2200pF
TG
SW
TRACK/SS
R
SENSE
3mΩ
L1
1µH
C
ITH1
V
0.6V
10A
OUT
C
0.1µF
B
R
220pF
ITH
BOOST
51k
C
OUT1
+
D
B
ITH
330µF
2.5V
×2
INTV
CC
INTV
CC
VCC
4.7µF
C
R
T
205k
C
OUT2
RT
100µF
MB
BG
PGND
+
×2
EXTV
CC
V
V
SGND
OSNS
–
OSNS
3833 TA03
C
C
: NICHICON UCJ1H101MCL1GS
L1: WURTH 7443320100
MT: INFINEON BSC093N04LS
MB: INFINEON BSC035N04LS
IN1
: SANYO 2R5TPE330M9
OUT
D : DIODES INC. SDM10K45
B
Efficiency
90
80
70
60
50
40
30
20
PULSE-SKIPPING
MODE
FORCED
CONTINUOUS
MODE
V
V
= 12V
OUT
IN
= 0.6V
0.1
10
1
LOAD CURRENT (A)
3833 TA03b
3833f
31
LTC3833
TYPICAL APPLICATIONS
Area °ompact ꢀ.5V, 5A, 1.ꢀMHz Step-Down °onverter
R
VIN
INTV
CC
2.2Ω
V
IN
V
V
IN
RNG
6V TO 28V
+
C
47µF
35V
C
IN1
C
VIN
IN2
0.1µF
10µF
LTC3833
R
100k
PGD
V
PGOOD
RUN
EXTV
OUT
–
SENSE
SENSE
+
C
DCR
CC
R
DCR
0.1µF
1.1k
MT
TG
MODE/PLLIN
TRACK/SS
ITH
C
SS
SW
L1
1µH
0.01µF
C
0.1µF
B
V
2.5V
5A
OUT
BOOST
C
ITH1
R
D
FB2
B
R
220pF
ITH
31.6k
INTV
CC
INTV
CC
VCC
20k
C
4.7µF
C
R
OUT1
FB1
100µF
10k
R
T
MB
BG
PGND
+
33.2k
RT
SGND
V
V
OSNS
OSNS
–
3833 TA04
C
: KEMET T521X476M035ATE070
IN1
D : DIODES INC. SDM10K45
B
L1: VISHAY IHLP2525CZ-1µH
MT, MB: VISHAY/SILICONIX Si4816BDY
Efficiency
90
80
70
60
50
40
30
20
PULSE-
SKIPPING
MODE
FORCED
CONTINUOUS
MODE
V
V
= 12V
IN
OUT
= 2.5V
0.1
10
1
LOAD CURRENT (A)
3833 TA04b
3833f
32
LTC3833
TYPICAL APPLICATIONS
3.3V, 15A, ꢀ00kHz High Power Step-Down °onverter
V
IN
V
IN
4.5V TO 24V
R
+
C
IN1
100µF
35V
C
C
VIN
IN2
VIN
INTV
CC
2.2Ω
10µF
0.1µF
×5
RUN
V
OUT
–
LTC3833
R
PGD
100k
SENSE
PGOOD
C
R
R
DCR2
DCR
DCR1
0.22µF
17.4k
3.92k
+
SENSE
V
RNG
MODE/PLLIN
EXTV
MT
TG
SW
CC
L1
2µH
C
SS
V
3.3V
15A
OUT
0.1µF
BOOST
TRACK/SS
ITH
R
D
B
FB2
C
B
C
ITH1
C
90.9k
OUT1
220µF
4V
C
+
OUT2
0.1µF
INTV
CC
INTV
CC
R
680pF
ITH
100µF
18.2k
C
VCC
×2
R
FB1
4.7µF
×2
20k
MB
BG
C
47pF
ITH2
PGND
+
R
T
205k
V
V
RT
SGND
OSNS
–
OSNS
3833 TA06
C
C
: SUNCON 35HVP100M
L1: WURTH 7443551200
MB: RENESAS RJK0330DPB
MT: RENESAS RJK0305DPB
IN1
: SANYO 4TPE220MFC2
OUT1
D : CENTRAL CMDSH-3
B
Efficiency
100
90
80
70
60
50
40
PULSE-SKIPPING
MODE
FORCED
CONTINUOUS
MODE
V
V
= 12V
IN
OUT
= 3.3V
0.1
1
10
100
LOAD CURRENT (A)
3833 F10b
3833f
33
LTC3833
PACKAGE DESCRIPTION
UD° Package
ꢀ0-Lead Plastic QFN (3mm × 4mm)
(Reference LTC DWG # ±ꢁ-±8-1642 Rev Ø)
0.70 ±0.05
3.50 ± 0.05
2.10 ± 0.05
2.65 ± 0.05
1.50 REF
1.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
3.10 ± 0.05
4.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
0.75 ± 0.05
1.50 REF
19 20
R = 0.05 TYP
3.00 ± 0.10
0.40 ± 0.10
1
2
PIN 1
TOP MARK
(NOTE 6)
2.65 ± 0.10
1.65 ± 0.10
4.00 ± 0.10
2.50 REF
(UDC20) QFN 1106 REV Ø
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3833f
34
LTC3833
PACKAGE DESCRIPTION
FE Package
ꢀ0-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # ±ꢁ-±8-1ꢀꢀ3 Rev H)
Exposed Pad Variation °B
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV H 0910
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3833f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3833
TYPICAL APPLICATION
High Frequency 5.5V, 4A, ꢀMHz Step-Down °onverter
R
R
PGD
VIN
INTV
CC
100k
2.2Ω
V
IN
V
PGOOD
MODE/PLLIN
IN
7V TO 14V
Efficiency
C
C
+
IN2
C
47µF
35V
VIN
IN1
R
4.7µF
0.1µF
DIV1
LTC3833
100k
×2
90
80
70
60
50
40
30
20
V
PULSE-
SKIPPING
MODE
RNG
EXTV
CC
R
R
F2
DIV2
RUN
V
OUT
–
26.1k
10Ω
SENSE
C
SS
0.1µF
C
R
F1
F
1000pF 10Ω
+
SENSE
TRACK/SS
ITH
FORCED
CONTINUOUS
MODE
MT
TG
C
ITH1
R
220pF
ITH
20k
L1
1.2µH
R
SENSE
SW
10mΩ
V
5.5V
4A
OUT
C
0.1µF
B
BOOST
D
C
R
T
18.2k
B
C
R
FB2
FF
22pF
V
IN
V
OUT
= 12V
INTV
CC
INTV
CC
165k
C
OUT1
RT
= 5.5V
VCC
4.7µF
22µF
R
×2
SGND
MB
FB1
0.1
10
BG
1
20k
LOAD CURRENT (A)
PGND
+
3833 TA05b
V
V
OSNS
OSNS
–
3833 TA05
C
: KEMET T521X476M035ATE070
L1: WURTH 744313120
MT, MB: INFINEON BSC093N04LS
IN1
D : DIODES, INC. SDM10K45
B
RELATED PARTS
PART NUMBER
DES°RIPTION
°OMMENTS
LTC3868/LTC3869
No R
™ Constant On-Time Synchronous Step-Down
Very Fast Transient Response, t
= 43ns, 4V ≤ V ≤ 38V,
SENSE
ON(MIN) IN
DC/DC Controller
±.ꢀV ≤ V
≤ ±.9V , SSOP-1ꢀ, MSOP-1ꢀE, 3mm × 3mm QFN-1ꢀ
OUT IN
LTC366ꢁ
High Frequency Synchronous Voltage Mode Step-Down
DC/DC Controller
Very Fast Transient Response, t
= 3±ns, 4V ≤ V ≤ 38V,
ON(MIN) IN
±.ꢀV ≤ V
≤ ±.8V , MSOP-1ꢀE, 3mm × 3mm QFN-1ꢀ
IN
OUT
LTC38ꢁ4
Small Footprint Synchronous Step-Down DC/DC Controller Fixed 4±±kHz Operating Frequency 4.ꢁV ≤ V ≤ 38V,
IN
±.8V ≤ V
≤ ꢁ.2ꢁV, 2mm × 3mm QFN-12
OUT
LTC38ꢁ1A/LTC38ꢁ1A-1 No R
Wide V Range Synchronous Step-Down
Phase-Lockable Fixed Frequency 2ꢁ±kHz to 6ꢁ±kHz, 4V ≤ V ≤ 38V,
IN
SENSE
IN
DC/DC Controller
±.8V ≤ V
≤ ꢁ.2ꢁV, MSOP-1ꢀE, 3mm × 3mm QFN-1ꢀ, SSOP-1ꢀ
OUT
LTC3891
LTC38ꢁꢀ
ꢀ±V, Low I Synchronous Step-Down DC/DC Controller
PLL Capable Fixed Frequency ꢁ±kHz to 9±±kHz, 4V ≤ V ≤ ꢀ±V,
IN
Q
±.8V ≤ V
≤ 24V, I = ꢁ±µA
Q
OUT
2-Phase, Single Output Synchronous Step-Down
DC/DC Controller with Diff Amp and DCR Temperature
Compensation
Phase-Lockable Fixed 2ꢁ±kHz to 66±kHz Frequency,
4.ꢁV ≤ V ≤ 38V, ±.ꢀV ≤ V ≤ ꢁ.2ꢁV
IN
OUT
LTC3829
3-Phase, Single Output Synchronous Step-Down
DC/DC Controller with Diff Amp and DCR Temperature
Compensation
Phase-Lockable Fixed 2ꢁ±kHz to 66±kHz Frequency,
4.ꢁV ≤ V ≤ 38V, ±.ꢀV ≤ V ≤ ꢁ.2ꢁV
IN
OUT
LTC38ꢁꢁ
2-Phase, Dual Output Synchronous Step-Down DC/DC
Controller with Differential Remote Sense
Phase-Lockable Fixed Frequency 2ꢁ±kHz to 66±kHz,
4.ꢁV ≤ V ≤ 38V, ±.ꢀV ≤ V ≤ 12.ꢁV
IN
OUT
LTC38ꢁ±/LTC38ꢁ±-1
2-Phase, Dual Output Synchronous Step-Down DC/DC
Phase-Lockable Fixed Frequency 2ꢁ±kHz to 68±kHz, 4V ≤ V ≤ 3±V,
IN
Controllers, R
or DCR Current Sensing
±.8V ≤ V
≤ ꢁ.2ꢁV, 4mm × 4mm QFN-28, 4mm × ꢁmm QFN-28,
OUT
SENSE
SSOP-28
LTC38ꢁ3
Triple Output, Multiphase Synchronous Step-Down DC/DC Phase-Lockable Fixed Frequency 2ꢁ±kHz to 6ꢁ±kHz, 4V ≤ V ≤ 24V,
IN
Controller, R
or DCR Current Sensing
V
Up to 13.ꢁV
OUT
SENSE
3833f
LT 1010 • PRINTED IN USA
36 LinearTechnology Corporation
1ꢀ3± McCarthy Blvd., Milpitas, CA 9ꢁ±3ꢁ-6416
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(4±8) 432-19±± FAX: (4±8) 434-±ꢁ±6 www.linear.com
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