LTC3834EUFD-PBF_技术文档

LTC3834

30µA I Synchronous

Q

Step-Down Controller

FEATURES

DESCRIPTION

TheLTC^®3834isahighperformancestep-downswitching

regulator controller that drives an all N-channel synchro-

nous power MOSFET stage. A constant-frequency current

mode architecture allows a phase-lockable frequency of

up to 650kHz.

n

Wide Output Voltage Range: 0.8V ≤ V

≤ 10V

OUT

n

Low Operating Quiescent Current: 30μA

OPTI-LOOP^®Compensation Minimizes C

1% Output Voltage Accuracy

n

OUT

Wide V Range: 4V to 36V

IN

Phase-Lockable Fixed Frequency 140kHz to 650kHz

Dual N-Channel MOSFET Synchronous Drive

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Output Voltage Soft-Start or Tracking

Output Current Foldback Limiting

The 30μA no-load quiescent current extends operating

life in battery powered systems. OPTI-LOOP compensa-

tion allows the transient response to be optimized over

a wide range of output capacitance and ESR values. The

LTC3834 features a precision 0.8V reference and a power

good output indicator. The 4V to 36V input supply range

encompasses a wide range of battery chemistries.

Power Good Output Voltage Monitor

Clock Output for PolyPhase^®Applications

Output Overvoltage Protection

The TRACK/SS pin ramps the output voltage during

start-up. Current foldback limits MOSFET heat dissipa-

tion during short-circuit conditions. A reduced feature set

version of the part (LTC3834-1) is available in a smaller,

lower pin count package.

Low Shutdown I : 4μA

Q

Internal LDO Powers Gate Drive from V or V

IN

OUT

Selectable Continuous, Pulse Skipping or

Burst Mode^®Operation at Light Loads

n

Small 20-Lead TSSOP or 4mm × 5mm QFN Package

Comparison of LTC3834 and LTC3834-1

CLKOUT/

APPLICATIONS

PART #

PHASMD EXTV

PGOOD

Yes

PACKAGES

CC

LTC3834

LTC3834-1

Yes

No

Yes

No

FE20/4mm × 5mm QFN

GN16/3mm × 5mm DFN

n

Automotive Systems

No

n

Telecom Systems

L, LT, LTC, LTM, Burst Mode, PolyPhase and OPTI-LOOP are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5408150, 5481178, 5705919, 5929620, 6304066,

6498466, 6580258, 6611131.

n

Battery-Operated Digital Devices

n

Distributed DC Power Systems

TYPICAL APPLICATION

High Efﬁciency Synchronous Step-Down Converter

V

IN

4V TO 36V

CLKOUT

PLLLPF

RUN

V

IN

10000

1000

100

10

100

90

10μF

TG

0.01μF

0.22μF

PGOOD

TRACK/SS

80

BOOST

SW

70

3.3μH

V

OUT

3.3V

5A

0.012Ω

I

TH

560pF

54.2k

60

50

LTC3834

150pF

150μF

40

30

20

10

SGND

PLLIN/MODE

INTV

EXTV

CC

4.7μF

68.1k

1

V

BG

FB

–

+

SENSE

0

0.1

215k

0.000001

0.0001

OUTPUT CURRENT (A)

0.01

1

PGND

3834 TA01b

3834 TA01

3834fb

1

LTC3834

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

Input Supply Voltage (V )......................... 36V to –0.3V

I , V Voltages ...................................... 2.7V to –0.3V

IN

TH FB

Topside Driver Voltage (BOOST) ................ 42V to –0.3V

Peak Output Current <10μs (TG, BG)..........................3A

Switch Voltage (SW)..................................... 36V to –5V

INTV Peak Output Current ................................. 50mA

CC

INTV , (BOOST-SW), CLKOUT, PGOOD .. 8.5V to –0.3V

Operating Temperature Range (Note 2).... –40°C to 85°C

Junction Temperature (Note 3) ............................. 125°C

Storage Temperature Range................... –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

CC

RUN, TRACK/SS ......................................... 7V to –0.3V

+

–

SENSE , SENSE Voltages ........................ 11V to –0.3V

PLLIN/MODE, PHASMD, PLLLPF ......... INTV to –0.3V

CC

EXTV ...................................................... 10V to –0.3V

FE Package ....................................................... 300°C

CC

PIN CONFIGURATION

TOP VIEW

CLKOUT

PLLLPF

1

2

20

19

18

17

16

15

14

13

12

11

PHASMD

PLLIN/MODE

PGOOD

20 19 18 17

I

TH

3

I

1

2

3

4

5

6

16 PGOOD

+

TH

TRACKS/SS

4

SENSE

+

TRACK/SS

15 SENSE

14 SENSE

13 RUN

–

V

FB

5

21

SENSE

–

V

FB

SGND

PGND

BG

6

RUN

BOOST

TG

21

SGND

PGND

BG

7

12 BOOST

11 TG

8

INTV

CC

9

SW

7

8

9 10

EXTV

CC

10

V

IN

FE PACKAGE

20-LEAD PLASTIC TSSOP

UFD PACKAGE

20-PIN (4mm s 5mm) PLASTIC QFN

T

JMAX

= 125°C, θ = 35°C/W

JA

EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB

T

JMAX

= 125°C, θ = 37°C/W

JA

EXPOSED PAD (PIN 21) IS SGND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC3834EFE#PBF

LTC3834IFE#PBF

LTC3834EUFD#PBF

LTC3834IUFD#PBF

TAPE AND REEL

PART MARKING*

LTC3834FE

3834

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC3834EFE#TRPBF

LTC3834IFE#TRPBF

LTC3834EUFD#TRPBF

LTC3834IUFD#TRPBF

20-Lead Plastic TSSOP

–40°C to 85°C (Note 2)

–40°C to 85°C

20-Lead Plastic TSSOP

–40°C to 85°C (Note 2)

–40°C to 85°C

20-Lead (4mm × 5mm) Plastic QFN

3834

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

3834fb

2

LTC3834

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 12V, V_RUN= 5V unless otherwise noted.

SYMBOL

Main Control Loops

V_FBRegulated Feedback Voltage

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

(Note 4); I Voltage = 1.2V

0.792

0.800

–5

0.808

–50

V

nA

TH

I

Feedback Current

(Note 4)

VFB

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 4V to 30V (Note 4)

0.002

0.02

%/V

REFLNREG

IN

(Note 4)

Measured in Servo Loop; ΔI Voltage = 1.2V to 0.7V

Measured in Servo Loop; ΔI Voltage = 1.2V to 2V

LOADREG

l

0.1

–0.1

0.5

–0.5

%

TH

g

Transconductance Ampliﬁer g

I = 1.2V; Sink/Source 5μA (Note 4)

TH

0.5

mmho

m

I

Q

Input DC Supply Current

Sleep Mode

Shutdown

(Note 5)

RUN = 5V, V = 0.83V (No Load)

30

4

50

10

μA

FB

V

= 0V

RUN

l

UVLO

Undervoltage Lockout

V

Ramping Down

3.7

10

4

V

%

IN

V

OVL

Feedback Overvoltage Lockout

Sense Pins Total Source Current

Maximum Duty Factor

Measured at V Relative to Regulated V

8

12

FB

–

+

I

V

SENSE

= V

= 0V

–220

99.4

1.1

μA

%

SENSE

DF

In Dropout

98

0.85

0.5

85

MAX

I

Soft-Start Charge Current

V

TRACK

= 0V

1.45

0.9

μA

V

TRACK/SS

V

ON

RUN Pin ON Threshold

V Rising

RUN

0.7

RUN

–

l

Maximum Current Sense Threshold

V

FB

= 0.7V, V

= 3.3V

100

115

mV

SENSE(MAX)

SENSE

TG Transition Time:

Rise Time

Fall Time

(Note 6)

TG t

C

= 3300pF

50

90

ns

r

f

LOAD

= 3300pF

BG Transition Time:

Rise Time

Fall Time

(Note 6)

LOAD

BG t

C

= 3300pF

40

90

80

r

f

ns

TG/BG t

BG/TG t

Top Gate Off to Bottom Gate On Delay C

Synchronous Switch-On Delay Time

= 3300pF

70

ns

1D

LOAD

Bottom Gate Off to Top Gate On Delay C

Top Switch-On Delay Time

2D

LOAD

t

Minimum On-Time

(Note 7)

200

ON(MIN)

INTV Linear Regulator

CC

V

Internal V Voltage

8.5V < V < 30V, V = 0V

EXTVCC

5

5.25

0.2

7.5

0.2

4.7

0.2

5.5

1.0

7.8

1.0

V

%

V

INTVCCVIN

CC

IN

INTV Load Regulation

I

CC

= 0mA to 20mA, V

= 0V

LDOVIN

CC

EXTVCC

Internal V Voltage

V = 8.5V

EXTVCC

7.2

4.5

INTVCCEXT

LDOEXT

CC

INTV Load Regulation

I

CC

= 0mA to 20mA, V

= 8.5V

%

V

CC

EXTVCC

EXTV Switchover Voltage

EXTV Ramping Positive

CC

EXTVCC

CC

EXTV Hysteresis

V

LDOHYS

CC

Oscillator and Phase-Locked Loop

f

I

Nominal Frequency

Lowest Frequency

Highest Frequency

V

= No Connect

= 0V

360

220

475

400

250

530

115

800

440

280

580

140

kHz

NOM

PLLLPF

LOW

= INTV

HIGH

CC

Minimum Synchronizable Frequency PLLIN/MODE = External Clock; V

Maximum Synchronizable Frequency PLLIN/MODE = External Clock; V

Phase Detector Output Current

Sinking Capability

Sourcing Capability

= 0V

= 2V

SYNCMIN

SYNCMAX

PLLLPF

650

PLLLPF

f

< f

> f

–5

5

μA

PLLIN/MODE

OSC

3834fb

3

LTC3834

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. V_IN= 12V, V_RUN= 5V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PGOOD Output

V

I

PGOOD Voltage Low

PGOOD Leakage Current

PGOOD Trip Level

I

= 2mA

= 5V

0.1

0.3

1

V

PGL

PGOOD

V

μA

PGOOD

V

with Respect to Set Regulated Voltage

Ramping Negative

Ramping Positive

PG

FB

V

FB

V

FB

–12

8

–10

10

–8

12

%

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: The LTC3834 is tested in a feedback loop that servos V to a

ITH

speciﬁed voltage and measures the resultant V

.

FB

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 2: The LTC3834E is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls. The LTC3834I is guaranteed to meet

performance speciﬁcations over the –40°C to 85°C operating temperature

range.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: The minimum on-time condition is speciﬁed for an inductor

peak-to-peak ripple current ≥40% of I

(see Minimum On-Time

MAX

Considerations in the Applications Information section).

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formulas:

D

LTC3834FE: T = T + (P • 35°C/W)

J

A

D

LTC3834UFD: T = T + (P • 37°C/W)

J

A

D

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

Efﬁciency and Power Loss

vs Output Current

Efﬁciency vs Load Current

Efﬁciency vs Input Voltage

98

96

94

92

90

88

10000

1000

100

10

100

90

100

90

Burst Mode OPERATION

FORCED CONTINUOUS MODE

PULSE SKIPPING MODE

= 12V

= 3.3V

V

= 12V

= 5V

V

= 3.3V

IN

OUT

FIGURE 11 CIRCUIT

V

OUT

= 3.3V

80

V

IN

OUT

70

80

60

50

70

40

30

20

10

0

86

84

82

80

60

50

40

1

FIGURE 11 CIRCUIT

0.01

FIGURE 11 CIRCUIT

0.1

10

20 25 30 35 40

15

INPUT VOLTAGE (V)

0

5

0.000001

0.0001

OUTPUT CURRENT (A)

1

0.000001

0.0001

0.01

1

OUTPUT CURRENT (A)

3834 G02

3834 G01

3834 G03

3834fb

4

LTC3834

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

Load Step

(Forced Continuous Mode)

Load Step (Burst Mode Operation)

Load Step (Pulse Skipping Mode)

V

OUT

100mV/DIV

AC

100mV/DIV

AC

100mV/DIV

AC

COUPLED

I

L

I

L

2A/DIV

3834 G06

3834 G05

3834 G04

20μs/DIV

FIGURE 11 CIRCUIT

20μs/DIV

FIGURE 11 CIRCUIT

V

= 3.3V

20μs/DIV

FIGURE 11 CIRCUIT

V

= 3.3V

V

= 3.3V

OUT

Inductor Current at Light Load

Soft Start-Up

Tracking Start-Up

FORCED

CONTINUOUS

MODE

MASTER

2V/DIV

2A/DIV

Burst Mode

OPERATION

V

OUT

V

OUT

1V/DIV

2V/DIV

PULSE

SKIPPING

MODE

3834 G08

3834 G09

3834 G07

20ms/DIV

FIGURE 11 CIRCUIT

20ms/DIV

FIGURE 11 CIRCUIT

V

LOAD

FIGURE 11 CIRCUIT

= 3.3V

2μs/DIV

OUT

I

= 100μA

Total Input Supply Current vs

Input Voltage

EXTV_CCSwitchover and INTV_CC

Voltages vs Temperature

INTV_CCLine Regulation

350

300

250

200

150

5.5

5.4

5.3

5.2

5.1

5.0

6.0

5.8

5.6

5.4

5.2

5.0

4.8

4.6

FIGURE 11 CIRCUIT

INTV

CC

EXTV RISING

CC

300μA LOAD

NO LOAD

100

50

0

EXTV FALLING

CC

4.4

4.2

4.0

20

INPUT VOLTAGE (V)

30

35

5

10

15

25

25 30 35 40

INPUT VOLTAGE (V)

0

5

10 15 20

35

TEMPERATURE (°C)

75

95

–45 –25 –5

15

55

3834 G10

3834 G12

3834 G11

3834fb

5

LTC3834

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

Maximum Current Sense Voltage

vs I_THVoltage Cycle

SENSE Pins Total Input

Bias Current

Maximum Current Sense

Threshold vs Duty

100

80

60

30

120

100

80

FORCED CONTINUOUS

Burst Mode OPERATION

(RISING)

Burst Mode OPERATION

(FALLING)

PULSE SKIPPING

0

–30

–60

–90

6O

40

20

0

–120

–150

–180

–210

–240

–270

–300

60

40

20

0

–20

10% DUTY CYCLE

–40

0.6

1.0 1.2

1.4

40

60 70 80 90 100

0

0.2 0.4

I

0.8

5

6

7

8

9

10

0

10 20 30

50

0

1

2

3

4

PIN VOLTAGE (V)

DUTY CYCLE (%)

V

COMMON MODE VOLTAGE (V)

TH

SENSE

3834 G13

3834 G15

3834 G14

SENSE Pins Total Input

Bias Current vs I_TH

Foldback Current Limit

Quiescent Current vs Temperature

120

100

80

4

40

38

36

34

32

3

2

1

0

60

40

20

0

30

28

26

24

22

0.4

0.6 0.7 0.8 0.9

0

0.1 0.2 0.3

0.5

1.0

1.4

0

0.2 0.4 0.6 0.8

VOLTAGE (V)

1.2

30

TEMPERATURE (°C)

60 75 90

–45 –30 –15

0

15

45

FEEDBACK VOLTAGE (V)

I

TH

3834 G16

3834 G18

3834 G17

TRACK/SS Pull-Up Current

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

1.00

1.30

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

1.25

1.20

1.15

1.10

1.05

1.00

0.95

0.90

30

TEMPERATURE (°C)

30

TEMPERATURE (°C)

60 75 90

–45 –30 –15

0

15

45 60 75 90

–45 –30 –15

0

15

45

3834 G20

3834 G19

3834fb

6

LTC3834

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, unless otherwise noted.}

Regulated Feedback Voltage

vs Temperature

SENSE Pins Total Input Bias

Current vs Temperature

Shutdown Current

vs Input Voltage

808

806

804

60

30

12

10

8

V

= 10V

OUT

0

V

= 3.3V

OUT

–30

–60

–90

802

800

798

796

794

792

6

–120

–150

–180

–210

–240

–270

–300

4

V

= 0V

15

OUT

2

0

30

TEMPERATURE (°C)

–45 –30 –15

0

15

45 60 75 90

30

–45 –30 –15

0

45 60 75 90

5

10

15

20

25

35

30

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3834 G21

3834 G22

3834 G23

Oscillator Frequency

vs Temperature

Undervoltage Lockout Threshold

vs Temperature

4.2

4.1

800

700

600

500

400

300

200

100

0

4.0

3.9

3.8

3.7

3.6

3.5

3.4

3.3

3.2

RISING

V

= INTV

CC

PLLLPF

V

= FLOAT

= GND

PLLLPF

FALLING

V

PLLLPF

30

TEMPERATURE (°C)

–45 –30 –15

0

15

45 60 75 90

35

75

95

–45 –25 –5

15

55

TEMPERATURE (°C)

3834 G25

3834 G24

INTV_CCvs Load Current

Shutdown Current vs Temperature

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

7

6

5

4

3

2

1

0

V

IN

= 12V

EXTV = 5V

CC

40

LOAD CURRENT (mA)

60

0

10

20

30

50

30

TEMPERATURE (°C)

60 75 90

–45 –30 –15

0

15

45

3834 G26

3834 G27

3834fb

7

LTC3834

PIN FUNCTIONS ^(FE/UFD)

CLKOUT (Pin 1/Pin 19): Open-Drain Output Clock Signal

available to daisy-chain other controller ICs for additional

MOSFET driver stages/phases.

the Applications Information section. Do not exceed 10V

on this pin.

V (Pin 11/Pin 9): Main Supply Pin. A bypass capacitor

IN

should be tied between this pin and the signal ground

PLLLPF (Pin 2/Pin 20): The phase-locked loop’s lowpass

pin.

ﬁlter is tied to this pin when synchronizing to an external

clock. Alternatively, tie this pin to GND, V or leave

IN

SW(Pin12/Pin10):SwitchNodeConnectionstoInductor.

ﬂoating to select 250kHz, 530kHz or 400kHz switching

VoltageswingatthispinisfromaSchottkydiode(external)

frequency.

voltage drop below ground to V .

IN

I

(Pin 3/Pin 1): Error Ampliﬁer Outputs and Switching

TH

TG (Pin 13/Pin 11): High Current Gate Drive for Top

Regulator Compensation Points. The current comparator

N-ChannelMOSFET.Thesearetheoutputsofﬂoatingdrivers

trip point increases with this control voltage.

withavoltageswingequaltoINTV –0.5Vsuperimposed

CC

on the switch node voltage SW.

TRACK/SS (Pin 4/Pin 2): External Tracking and Soft-Start

Input.TheLTC3834regulatestheV voltagetothesmaller

FB

BOOST (Pin 14/Pin 12): Bootstrapped Supply to the

Topside Floating Driver. A capacitor is connected between

the BOOST and SW pins and a Schottky diode is tied

of 0.8V or the voltage on the TRACK/SS pin. A internal 1μA

pull-upcurrentsourceisconnectedtothispin. Acapacitor

to ground at this pin sets the ramp time to ﬁnal regulated

output voltage. Alternatively, a resistor divider on another

voltage supply connected to this pin allows the LTC3834

output to track the other supply during start-up.

between the BOOST and INTV pins. Voltage swing at the

CC

BOOST pin is from INTV to (V + INTV ).

CC

IN

CC

RUN (Pin 15/Pin 13): Digital Run Control Input for

Controller. Forcing this pin below 0.7V shuts down all

controller functions, reducing the quiescent current that

the LTC3834 draws to approximately 4μA.

V

(Pin 5/Pin 3): Receives the remotely sensed feed-

FB

back voltage from an external resistive divider across

the output.

–

SENSE (Pin 16/Pin 14): The (–) Input to the Differential

SGND(Pin6/Pin4):Small-SignalGround. Mustberouted

separately from high current grounds to the common (–)

terminals of the input capacitor.

Current Comparator.

+

SENSE (Pin 17/Pin 15): The (+) Input to the Differential

Current Comparator. The I pin voltage and controlled

TH

PGND(Pin7/Pin5):DriverPowerGround.Connectstothe

–

+

offsets between the SENSE and SENSE pins in conjunc-

tion with R set the current trip threshold.

sourceofbottom(synchronous)N-channelMOSFET,anode

SENSE

of the Schottky rectiﬁer and the (–) terminal of C .

IN

PGOOD(Pin18/Pin16):Open-DrainLogicOutput.PGOOD

BG (Pin 8/Pin 6): High Current Gate Drive for Bottom

is pulled to ground when the voltage on the V pin is not

FB

(Synchronous) N-Channel MOSFET. Voltage swing at this

within 10% of its set point.

pin is from ground to INTV .

CC

PLLIN/MODE (Pin 19/Pin 17): External Synchronization

Input to Phase Detector and Forced Continuous Control

Input. When an external clock is applied to this pin, the

phase-locked loop will force the rising TG signal to be

synchronized with the rising edge of the external clock. In

this case, an R-C ﬁlter must be connected to the PLLLPF

pin. When not synchronizing to an external clock, this

input determines how the LTC3834 operates at light loads.

Pulling this pin below 0.7V selects Burst Mode operation.

INTV (Pin 9/Pin 7): Output of the Internal Linear Low

CC

Dropout Regulator. The driver and control circuit are

powered from this voltage source. Must be decoupled

to power ground with a minimum of 4.7μF tantalum or

ceramic capacitor.

EXTV (Pin10/Pin8):ExternalPowerInputtoanInternal

CC

LDO Connected to INTV . This LDO supplies V power,

CC

bypassing the internal LDO powered from V whenever

IN

TyingthispintoINTV forcescontinuousinductorcurrent

EXTV is higher than 4.7V. See EXTV Connection in

CC

3834fb

8

LTC3834

PIN FUNCTIONS ^(FE/UFD)

operation. Tying this pin to a voltage greater than 0.9V and

Exposed Pad (Pin 21/Pin 21): SGND. Must be soldered

to the PCB.

less than INTV selects pulse-skipping operation.

CC

PHASMD (Pin 20/Pin 18): Control Input to Phase Selector

whichdeterminesthephaserelationshipsbetweenTGand

the CLKOUT signal.

FUNCTIONAL DIAGRAM

PLLIN/

MODE

F

IN

PHASE DET

INTV

CC

V

IN

PHASMD

PLLLPF

D

C

B

BOOST

TG

R

LP

C

LP

B

DROP

OUT

DET

CLK

TOP

BOT

C

IN

D

OSCILLATOR

INTV

BOT

TOP ON

FC

CC

SW

S

R

Q

10k

CLKOUT

PGOOD

–

+

SWITCH

LOGIC

0.88V

INTV

CC

BG

V

FB1

–

+

BURSTEN

SLEEP

C

OUT

PGND

B

0.72V

+

–

0.4V

V

OUT

SHDN

R

SENSE

L

–

+

INTV – 0.5V

CC

FC

ICMP

IR

+

–

+ +

–

+

PLLIN/MODE

–

+

BURSTEN

0.8V

+

6mV

SENSE

0.45V

2(V

)

FB

–

SENSE

SLOPE

COMP

V

FB

R

B

V

FB

–

+

TRACK/SS

0.80V

EA

OV

V

IN

R

A

V

IN

+

–

+

–

4.7V

5.25V/

7.5V

LDO

0.88V

C

I

TH

EXTV

INTV

CC

0.5μA

R

C

C2

6V

1μA

TRACK/SS

CC

+

RUN

INTERNAL

SUPPLY

SGND

SHDN

SS

3834 FD

3834fb

9

LTC3834

(Refer to Functional Diagram)

OPERATION

ThetopMOSFETdriverisbiasedfromtheﬂoatingbootstrap

Main Control Loop

capacitor, C , which normally recharges during each off

B

The LTC3834 uses a constant-frequency, current mode

step-down architecture. During normal operation, the

external top MOSFET is turned on when the clock sets the

RSlatch,andisturnedoffwhenthemaincurrentcompara-

tor, ICMP, resets the RS latch. The peak inductor current

at which ICMP trips and resets the latch is controlled by

cycle through an external diode when the top MOSFET

turns off. If the input voltage V decreases to a voltage

IN

close to V , the loop may enter dropout and attempt

OUT

to turn on the top MOSFET continuously. The dropout

detector detects this and forces the top MOSFET off for

about one twelfth of the clock period every tenth cycle to

the voltage on the I pin, which is the output of the error

TH

allow C to recharge.

B

ampliﬁer EA. The error ampliﬁer compares the output volt-

agefeedbacksignalattheV pin,(whichisgeneratedwith

FB

Shutdown and Start-Up (RUN and TRACK/SS Pins)

an external resistor divider connected across the output

The LTC3834 can be shut down using the RUN pin. Pulling

thispinbelow0.7Vshutsdownthemaincontrolloopofthe

controller. A low disables the controller and most internal

voltage, V , to ground) to the internal 0.800V reference

OUT

voltage. When the load current increases, it causes a slight

decrease in V relative to the reference, which cause the

FB

circuits, including the INTV regulator, at which time the

CC

EA to increase the I voltage until the average inductor

TH

LTC3834 draws only 4μA of quiescent current.

current matches the new load current.

Releasing the RUN pin allows an internal 0.5μA current

to pull up the pin and enable that controller. Alternatively,

the RUN pin may be externally pulled up or driven directly

by logic. Be careful not to exceed the Absolute Maximum

rating of 7V on this pin.

After the top MOSFET is turned off each cycle, the bottom

MOSFETisturnedonuntileithertheinductorcurrentstarts

to reverse, as indicated by the current comparator IR, or

the beginning of the next clock cycle.

INTV /EXTV Power

CC

The start-up of the output voltage V

is controlled by

OUT

the voltage on the TRACK/SS pin. When the voltage on

the TRACK/SS pin is less than the 0.8V internal reference,

Power for the top and bottom MOSFET drivers and most

other internal circuitry is derived from the INTV pin.

CC

the LTC3834 regulates the V voltage to the TRACK/SS

When the EXTV pin is left open or tied to a voltage less

FB

CC

pin voltage instead of the 0.8V reference. This allows

the TRACK/SS pin to be used to program a soft-start by

connecting an external capacitor from the TRACK/SS pin

to SGND. An internal 1μA pull-up current charges this

capacitor creating a voltage ramp on the TRACK/SS pin.

As the TRACK/SS voltage rises linearly from 0V to 0.8V

than 4.7V, an internal 5.25V low dropout linear regulator

supplies INTV power from V . If EXTV is taken above

CC

IN

CC

4.7V, the 5.25V regulator is turned off and a 7.5V low

dropout linear regulator is enabled that supplies INTV

CC

power from EXTV . If EXTV is less than 7.5V (but

CC

greater than 4.7V), the 7.5V regulator is in dropout and

INTV is approximately equal to EXTV . When EXTV

CC

(and beyond), the output voltage V

from zero to its ﬁnal value.

rises smoothly

OUT

CC

is greater than 7.5V (up to an absolute maximum rating

of 10V), INTV is regulated to 7.5V. Using the EXTV

CC

Alternatively the TRACK/SS pin can be used to cause the

start-up of V to “track” that of another supply. Typi-

pin allows the INTV power to be derived from a high

CC

OUT

efﬁciency external source such as one of the LTC3834

switching regulator outputs.

cally, this requires connecting to the TRACK/SS pin an

external resistor divider from the other supply to ground

(see Applications Information section).

3834fb

10

LTC3834

(Refer to Functional Diagram)

OPERATION

When the RUN pin is pulled low to disable the LTC3834, or

normal operation by turning on the top external MOSFET

on the next cycle of the internal oscillator.

when V drops below its undervoltage lockout threshold

IN

of 3.7V, the TRACK/SS pin is pulled low by an internal

MOSFET. When in undervoltage lockout, the controller is

disabled and the external MOSFETs are held off.

When the LTC3834 is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse

current comparator (RI

) turns off the bottom external

CMP

MOSFET just before the inductor current reaches zero,

preventing it from reversing and going negative, thus

operating in discontinuous operation.

Light Load Current Operation (Burst Mode Operation,

Pulse-Skipping or Continuous Conduction)

(PLLIN/MODE Pin)

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions.Thepeakinductorcurrentisdeterminedbythe

The LTC3834 can be enabled to enter high efﬁciency

BurstModeoperation,constant-frequencypulse-skipping

mode, or forced continuous conduction mode at low load

currents. To select Burst Mode operation, tie the PLLIN/

MODE pin to a DC voltage below 0.8V (e.g., SGND). To

select forced continuous operation, tie the PLLIN/MODE

pin to INTV_CC. To select pulse skipping mode, tie the

PLLIN/MODE pin to a DC voltage greater than 0.8V and

less than INTV_CC– 0.5V.

voltage on the I pin, just as in normal operation. In this

TH

mode, the efﬁciency at light loads is lower than in Burst

Mode operation. However, continuous operation has the

advantages of lower output ripple and less interference

to audio circuitry. In forced continuous mode, the output

ripple is independent of load current.

When the PLLIN/MODE pin is connected for pulse skip-

ping mode or clocked by an external clock source to

use the phase-locked loop (see Frequency Selection and

Phase-Locked Loop section), the LTC3834 operates in

PWM pulse skipping mode at light loads. In this mode,

constant-frequency operation is maintained down to ap-

proximately 1% of designed maximum output current.

At very light loads, the current comparator ICMP may

remaintrippedforseveralcyclesandforcetheexternaltop

MOSFET to stay off for the same number of cycles (i.e.,

skipping pulses). The inductor current is not allowed to

reverse (discontinuous operation). This mode, like forced

continuousoperation, exhibitslowoutputrippleaswellas

low audio noise and reduced RF interference as compared

to Burst Mode operation. It provides higher low current

efﬁciency than forced continuous mode, but not nearly as

high as Burst Mode operation.

When the LTC3834 is enabled for Burst Mode operation,

the peak current in the inductor is set to approximately

one-tenth of the maximum sense voltage even though the

voltage on the I pin indicates a lower value. If the aver-

TH

age inductor current is lower than the load current, the

error ampliﬁer EA will decrease the voltage on the I pin.

TH

When the I voltage drops below 0.4V, the internal sleep

TH

signalgoeshigh(enabling“sleep”mode)andbothexternal

MOSFETs are turned off. The I pin is then disconnected

TH

from the output of the EA and “parked” at 0.425V.

In sleep mode, much of the internal circuitry is turned off,

reducing the quiescent current that the LTC3834 draws to

only 30μA. In sleep mode, the load current is supplied by

the output capacitor. As the output voltage decreases, the

EA’s output begins to rise. When the output voltage drops

enough, the I pin is reconnected to the output of the

TH

EA, the sleep signal goes low, and the controller resumes

3834fb

11

LTC3834

OPERATION

Frequency Selection and Phase-Locked Loop

(PLLLPF and PLLIN/MODE Pins)

signal on the CLKOUT pin can be used to synchronize

additional power stages in a multiphase power supply

solution feeding a single, high current output or multiple

separate outputs. The PHASMD pin is used to adjust the

phase of the CLKOUT signal, as summarized in Table 1.

The phases are calculated relative to the zero degrees

phase being deﬁned as the rising edge of the top gate

driver output (TG).

Theselectionofswitchingfrequencyisatrade-offbetween

efﬁciency and component size. Low frequency opera-

tion increases efﬁciency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

The switching frequency of the LTC3834’s controllers can

be selected using the PLLLPF pin.

TheCLKOUTpinhasanopen-drainoutputdevice.Normally,

a 10k to 100k resistor can be connected from this pin to a

voltage supply that is less than or equal to 8.5V.

If the PLLIN/MODE pin is not being driven by an exter-

nal clock source, the PLLLPF pin can be ﬂoated, tied to

INTVCC, or tied to SGND to select 400kHz, 530kHz or

250kHz, respectively.

Table 1

V

CLKOUT PHASE

PHASMD

GND

90°

A phase-locked loop (PLL) is available on the LTC3834

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. In this

case,aseriesR-CshouldbeconnectedbetweenthePLLLPF

pinandSGNDtoserveasthePLL’sloopﬁlter. TheLTC3834

phase detector adjusts the voltage on the PLLLPF pin to

align the turn-on of the external top MOSFET to the rising

edge of the synchronizing signal.

Floating

INTV

120°

180°

CC

Output Overvoltage Protection

An overvoltage comparator guards against transient over-

shoots as well as other more serious conditions that may

overvoltage the output. When the V pin rises to more

than10%higherthanitsregulationpointof0.800V,thetop

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

FB

The typical capture range of the LTC3834’s phase-locked

loop is from approximately 115kHz to 800kHz, with a

guarantee to be between 140kHz and 650kHz. In other

words, the LTC3834’s PLL is guaranteed to lock to an

externalclocksourcewhosefrequencyisbetween140kHz

and 650kHz.

Power Good (PGOOD) Pin

ThePGOODpinisconnectedtoanopen-drainofaninternal

N-channel MOSFET. The MOSFET turns on and pulls the

PGOOD pin low when the V pin voltage is not within

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.2V (falling).

FB

10%ofthe0.8Vreferencevoltage.ThePGOODpinisalso

pulled low when the RUN pin is low (shut down). When

PolyPhase Applications (CLKOUT and PHASMD Pins)

the V pin voltage is within the 10% requirement, the

FB

MOSFET is turned off and the pin is allowed to be pulled

The LTC3834 features two pins (CLKOUT and PHASMD)

that allow other controller ICs to be daisy-chained with

the LTC3834 in PolyPhase applications. The clock output

up by an external resistor to a source of up to 8.5V.

3834fb

12

LTC3834

APPLICATIONS INFORMATION

R

Selection For Output Current

anyone ever choose to operate at lower frequencies with

larger components? The answer is efﬁciency. A higher

frequency generally results in lower efﬁciency because

of MOSFET gate charge losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

SENSE

R

is chosen based on the required output current.

SENSE

The current comparator has a maximum threshold of

100mV/R

and an input common mode range of

SENSE

SGND to 10V. The current comparator threshold sets the

peak of the inductor current, yielding a maximum average

output current I

peak-to-peak ripple current, ΔI .

equal to the peak value less half the

The inductor value has a direct effect on ripple current.

MAX

The inductor ripple current ΔI decreases with higher

L

inductance or frequency and increases with higher V :

IN

Allowing a margin for variations in the IC and external

component values yields:

⎛

⎞

V_OUT

V_IN

1

ΔI_L=

V_OUT1–

⎜

⎝

⎟

80mV

I_MAX

(f)(L)

⎠

R_SENSE

=

Accepting larger values of ΔI allows the use of low

L

When using the controller in very low dropout conditions,

themaximumoutputcurrentlevelwillbereducedduetothe

internal compensation required to meet stability criterion

for buck regulators operating at greater than 50% duty

factor. A curve is provided to estimate this reduction in

peak output current level depending upon the operating

duty factor.

inductances, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

setting ripple current is ΔI = 0.3(I

). The maximum

MAX

L

ΔI occurs at the maximum input voltage.

L

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

10% of the current limit determined by R

. Lower

SENSE

Operating Frequency and Synchronization

inductor values (higher ΔI ) will cause this to occur at

L

The choice of operating frequency, is a trade-off between

efﬁciency and component size. Low frequency operation

improvesefﬁciencybyreducingMOSFETswitchinglosses,

both gate charge loss and transition loss. However, lower

frequency operation requires more inductance for a given

amount of ripple current.

lower load currents, which can cause a dip in efﬁciency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

Inductor Core Selection

The internal oscillator of the LTC3834 runs at a nominal

400kHz frequency when the PLLLPF pin is left ﬂoating

and the PLLIN/MODE pin is a DC low or high. Pulling the

PLLLPF to INTVCC selects 530kHz operation; pulling the

PLLLPF to SGND selects 250kHz operation.

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores. Actual core loss is independent of core size for a

ﬁxedinductorvalue,butitisverydependentoninductance

selected. As inductance increases, core losses go down.

Unfortunately, increased inductance requires more turns

of wire and therefore copper losses will increase.

Alternatively, the LTC3834 will phase-lock to a clock

signal applied to the PLLIN/MODE pin with a frequency

between 140kHz and 650kHz (see Phase-Locked Loop

and Frequency Synchronization).

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

3834fb

Inductor Value Calculation

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

13

LTC3834

APPLICATIONS INFORMATION

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

The MOSFET power dissipations at maximum output

current are given by:

V_OUT

V_IN

2

P_MAIN

=

I

(

1+δΔT R

+

(

)

MAX

DS(ON)

Power MOSFET and Schottky Diode (Optional)

Selection

I

⎛

⎝

⎞

⎠

2

MAX

2

V

R

C

MILLER

•

(

)

(

_DR)(

)

IN ⎜

⎟

Two external power MOSFETs must be selected for the

LTC3834: one N-channel MOSFET for the top (main)

switch, and one N-channel MOSFET for the bottom (syn-

chronous) switch.

⎡

⎤

⎥

⎦

1

+

f

( )

⎢

⎣

V

_INTVCC– V_THMINV_THMIN

Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.

CC

V_IN– V_OUT

V_IN

2

P_SYNC

=

I

(

1+δΔT R

DS(ON)

(

)

Thisvoltageistypically5Vduringstart-up(seeEXTV Pin

MAX

CC

Connection).Consequently,logic-level thresholdMOSFETs

must be used in most applications. The only exception is

where δ is the temperature dependency of R

and

DS(ON)

if low input voltage is expected (V < 5V); then, sub-logic

IN

R

(approximately 2Ω) is the effective driver resistance

DR

level threshold MOSFETs (V

< 3V) should be used.

GS(TH)

at the MOSFET’s Miller threshold voltage. V

typical MOSFET minimum threshold voltage.

is the

THMIN

Pay close attention to the BV

speciﬁcation for the

DSS

MOSFETs as well; most of the logic-level MOSFETs are

limited to 30V or less.

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

which are highest at high input voltages. For V < 20V

IN

resistance R

, Miller capacitance C

, input

DS(ON)

MILLER

the high current efﬁciency generally improves with larger

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

MOSFETs, while for V > 20V the transition losses rapidly

IN

C

MILLER

increasetothepointthattheuseofahigherR

device

DS(ON)

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

withlowerC

actuallyprovideshigherefﬁciency.The

MILLER

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

along the horizontal axis while the curve is approximately

ﬂat divided by the speciﬁed change in V . This result is

DS

then multiplied by the ratio of the application applied V

DS

to the Gate charge curve speciﬁed V . When the IC is

DS

The term (1 + δΔT) is generally given for a MOSFET in

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

the form of a normalized R

vs Temperature curve,

DS(ON)

but δ = 0.005/°C can be used as an approximation for low

V_OUT

Main Switch Duty Cycle =

V_IN

voltage MOSFETs.

TheoptionalSchottkydiodeD1showninFigure6conducts

during the dead-time between the conduction of the two

power MOSFETs. This prevents the body diode of the

bottom MOSFET from turning on, storing charge during

the dead-time and requiring a reverse recovery period that

V_IN– V_OUT

Synchronous SwitchDuty Cycle=

V_IN

could cost as much as 3% in efﬁciency at high V . A 1A

IN

to 3A Schottky is generally a good compromise for both

regions of operation due to the relatively small average

current.Largerdiodesresultinadditionaltransitionlosses

due to their larger junction capacitance.

3834fb

14

LTC3834

APPLICATIONS INFORMATION

V

OUT

C and C

Selection

IN

OUT

Incontinuousmode,thesourcecurrentofthetopMOSFET

is a square wave of duty cycle (V )/(V ). To prevent

large voltage transients, a low ESR capacitor sized for the

maximumRMScurrentmustbeused.ThemaximumRMS

capacitor current is given by:

R

C

LTC3834

B

A

FF

V

OUT

IN

FB

R

3834 F01

Figure 1. Setting Output Voltage

1/2

I_MAX

V_IN

⎡

⎤

C_INRequired I_RMS

≈

V

_OUT)(

V – V

IN OUT

(

)

200

100

⎣

⎦

0

This formula has a maximum at V = 2V , where I

RMS

IN

OUT

–100

–200

–300

–400

–500

–600

–700

= I /2. This simple worst-case condition is commonly

OUT

usedfordesignbecauseevensigniﬁcantdeviationsdonot

offermuchrelief.Notethatcapacitormanufacturers’ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet

size or height requirements in the design. Due to the high

operating frequency of the LTC3834, ceramic capacitors

0

1

2

3

4

5

10

6

7

8

9

V

COMMON MODE VOLTAGE (V)

SENSE

3835 F02

can also be used for C . Always consult the manufacturer

IN

Figure 2. SENSE Pins Input Bias Current

vs Common Mode Voltage

if there is any question.

The selection of C

is driven by the effective series

OUT

To improve the frequency response, a feed-forward ca-

resistance (ESR). Typically, once the ESR requirement

pacitor, C , may be used. Great care should be taken to

FF

is satisﬁed, the capacitance is adequate for ﬁltering. The

route the V line away from noise sources, such as the

FB

output ripple (ΔV ) is approximated by:

OUT

inductor and the SW line.

⎛

⎜

⎝

⎞

1

+

–

ΔV_OUT≈I_RIPPLEESR+

SENSE and SENSE Pins

⎟

8fC_OUT

⎠

The common mode input range of the current comparator

is from 0V to 10V. Continuous linear operation is provided

throughout this range allowing output voltages from 0.8V

to 10V. The input stage of the current comparator requires

thatcurrenteitherbesourcedorsunkfromtheSENSEpins

depending on the output voltage, as shown in the curve in

Figure 2. If the output voltage is below 1.5V, current will

ﬂow out of both SENSE pins to the main output. In these

where f is the operating frequency, C

is the output

OUT

capacitance and I

is the ripple current in the induc-

RIPPLE

tor. The output ripple is highest at maximum input voltage

since I increases with input voltage.

RIPPLE

Setting Output Voltage

The LTC3834 output voltage is set by an external feed-

back resistor divider carefully placed across the output,

as shown in Figure 1. The regulated output voltage is

determined by:

cases, the output can be easily pre-loaded by the V

OUT

resistordividertocompensateforthecurrentcomparator’s

negative input bias current. Since V is servoed to the

FB

0.8V reference voltage, R in Figure 1 should be chosen

A

⎛

⎞

R_B

R_A

to be less than 0.8V/I

, with I

determined from

SENSE

V_OUT= 0.8V • 1+

⎜

⎝

⎟

Figure 2 at the speciﬁed output voltage.

⎠

3834fb

15

LTC3834

APPLICATIONS INFORMATION

Tracking and Soft-Start (TRACK/SS Pin)

according to the voltage on the TRACK/SS pin, allowing

OUT

The total soft-start time will be approximately:

V

to rise smoothly from 0V to its ﬁnal regulated value.

The start-up of V

is controlled by the voltage on the

OUT

TRACK/SS pin. When the voltage on the TRACK/SS pin is

0.8V

t_SS=C_SS•

1μA

lessthantheinternal0.8Vreference,theLTC3834regulates

the V pin voltage to the voltage on the TRACK/SS pin

FB

insteadof0.8V. TheTRACK/SSpincanbeusedtoprogram

an external soft-start function or to allow V

another supply during start-up.

to “track”

Alternatively, the TRACK/SS pin can be used to track two

(or more) supplies during start-up, as shown qualitatively

in Figures 4a and 4b. To do this, a resistor divider should

OUT

Soft-start is enabled by simply connecting a capacitor

from the TRACK/SS pin to ground, as shown in Figure 3.

An internal 1μA current source charges up the capacitor,

providing a linear ramping voltage at the TRACK/SS pin.

be connected from the master supply (V ) to the TRACK/

X

SS pin of the slave supply (V ), as shown in Figure 5.

OUT

During start-up V

will track V according to the ratio

OUT

X

set by the resistor divider:

The LTC3834 will regulate the V pin (and hence V

)

FB

OUT

R_TRACKA+R_TRACKB

R_A+R_B

V_X

R_A

=

•

LTC3834

TRACK/SS

V_OUTR_TRACKA

C

SS

For coincident tracking (V

= V during start-up),

OUT

X

SGND

3834 F03

R = R

A

TRACKA

TRACKB

Figure 3. Using the TRACK/SS Pin to Program Soft-Start

R = R

B

V (MASTER)

X

V (MASTER)

X

V

OUT

(SLAVE)

V

OUT

(SLAVE)

3834 F04B

TIME

3834 F04A

(4a) Coincident Tracking

(4b) Ratiometric Tracking

Figure 4. Two Different Modes of Output Voltage Tracking

V

OUT

x

LTC3834

RB

V

FB

RA

R

TRACKB

TRACK/SS

3834 F05

TRACKA

Figure 5. Using the TRACK/SS Pin for Tracking

3834fb

16

LTC3834

APPLICATIONS INFORMATION

INTV Regulators

is greater than 7.5V up to an absolute maximum of 10V,

CC

INTV is regulated to 7.5V.

CC

TheLTC3834featurestwoseparateinternalP-channellow

dropout linear regulators (LDO) that supply power at the

Using the EXTV_CCLDO allows the MOSFET driver and

control power to be derived from the LTC3834 switch-

ing regulator output (4.7V ≤ V_OUT≤ 10V) during normal

operation and from the V_INLDO when the output is out

of regulation (e.g., start-up, short circuit). If more current

is required through the EXTV_CCLDO than is speciﬁed,

an external Schottky diode can be added between the

EXTV_CCand INTV_CCpins. Do not apply more than 10V to

the EXTV_CCpin and make sure that EXTV_CC≤ V_IN.

INTV pin from either the V supply pin or the EXTV

CC

IN

CC

pin, respectively, depending on the connection of the

EXTV pin. INTV powers the gate drivers and much of

CC

the LTC3834’s internal circuitry. The V LDO regulates

IN

the voltage at the INTV pin to 5.25V and the EXTV

CC

LDO regulates it to 7.5V. Each of these can supply a peak

current of 50mA and must be bypassed to ground with a

minimumof4.7μFceramiccapacitor.Theceramiccapacitor

placed directly adjacent to the INTV and PGND IC pins is

CC

Signiﬁcant efﬁciency and thermal gains can be realized

highlyrecommended.Goodbypassingisneededtosupply

the high transient currents required by the MOSFET gate

drivers and to prevent interaction between the channels.

by powering INTV from the output, since the V cur-

CC

IN

rent resulting from the driver and control currents will be

scaledbyafactorof(DutyCycle)/(SwitcherEfﬁciency).For

4.7V to 10V regulator outputs, this means connecting the

EXTV pin directly to V . Tying the EXTV pin to a 5V

HighinputvoltageapplicationsinwhichlargeMOSFETsare

being driven at high frequencies may cause the maximum

junctiontemperatureratingfortheLTC3834tobeexceeded.

CC

OUT

CC

supply reduces the junction temperature in the previous

example from 125°C to:

TheINTV current,whichisdominatedbythegatecharge

CC

current, may be supplied by either the 5V V LDO or the

IN

T = 70°C + (24mA)(5V)(95°C/W) = 81°C

J

7.5V EXTV LDO. When the voltage on the EXTV pin

CC

However, for 3.3V and other low voltage outputs, addi-

is less than 4.7V, the V LDO is enabled. Power dissipa-

IN

tional circuitry is required to derive INTV power from

CC

tion for the IC in this case is highest and is equal to V •

IN

the output.

I

.Thegatechargecurrentisdependentonoperating

INTVCC

The following list summarizes the four possible connec-

frequency as discussed in the Efﬁciency Considerations

section. The junction temperature can be estimated by

using the equations given in Note 3 of the Electrical Char-

tions for EXTV :

CC

1. EXTV Left Open (or Grounded). This will cause

CC

acteristics. For example, the LTC3834 INTV current is

CC

INTV to be powered from the internal 5.25V regulator

CC

limited to less than 41mA from a 24V supply when in the

resulting in an efﬁciency penalty of up to 10% at high

G package and not using the EXTV supply:

CC

input voltages.

T = 70°C + (41mA)(36V)(95°C/W) = 125°C

2. EXTV Connected Directly to V . This is the normal

J

CC

OUT

connection for a 5V regulator and provides the highest

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

operating in continuous conduction mode (PLLIN/MODE

efﬁciency.

3. EXTV Connected to an External supply. If an external

CC

supply is available in the 5V to 7V range, it may be used

= INTV ) at maximum V .

CC

IN

to power EXTV providing it is compatible with the

CC

When the voltage applied to EXTV rises above 4.7V, the

CC

MOSFET gate drive requirements.

V LDO is turned off and the EXTV LDO is enabled. The

IN

CC

4. EXTV ConnectedtoanOutput-DerivedBoostNetwork.

EXTV LDO remains on as long as the voltage applied to

CC

For 3.3V and other low voltage regulators, efﬁciency

EXTV remains above 4.5V. The EXTV LDO attempts

CC

gains can still be realized by connecting EXTV to an

to regulate the INTV voltage to 7.5V, so while EXTV

CC

output-derivedvoltagethathasbeenboostedtogreater

is less than 7.5V, the LDO is in dropout and the INTV

than 4.7V. This can be done with the capacitive charge

voltage is approximately equal to EXTV . When EXTV

CC

pump shown in Figure 6.

3834fb

17

LTC3834

APPLICATIONS INFORMATION

Fault Conditions: Current Limit and Current Foldback

Topside MOSFET Driver Supply (C , D )

B

The LTC3834 includes current foldback to help limit load

current when the output is shorted to ground. If the out-

put falls below 70% of its nominal output level, then the

maximum sense voltage is progressively lowered from

100mV to 30mV. Under short-circuit conditions with very

low duty cycles, the LTC3834 will begin cycle skipping in

order to limit the short-circuit current. In this situation

the bottom MOSFET will be dissipating most of the power

but less than in normal operation. The short-circuit ripple

Externalbootstrapcapacitors,C_B,connectedtotheBOOST

pinssupplythegatedrivevoltagesforthetopsideMOSFET.

Capacitor C_Bin the Functional Diagram is charged though

external diode D_Bfrom INTV_CCwhen the SW pin is low.

When the topside MOSFET is to be turned on, the driver

places the C_Bvoltage across the gate-source of the de-

sired MOSFET. This enhances the MOSFET and turns on

the topside switch. The switch node voltage, SW, rises to

V_INand the BOOST pin follows. With the topside MOSFET

on, the boost voltage is above the input supply: V_BOOST

= V_IN+ V_INTVCC. The value of the boost capacitor, C_B,

needs to be 100 times that of the total input capacitance

of the topside MOSFET. The reverse breakdown of the

current is determined by the minimum on-time, t

,

ON(MIN)

of the LTC3834 (≈200ns), the input voltage and inductor

value:

ΔI

= t (V /L)

ON(MIN) IN

L(SC)

external Schottky diode must be greater than V_IN(MAX)

.

The resulting short-circuit current is:

When adjusting the gate drive level, the ﬁnal arbiter is the

total input current for the regulator. If a change is made

and the input current decreases, then the efﬁciency has

improved. If there is no change in input current, then

there is no change in efﬁciency.

30mV

R_SENSE

1

2

I_SC=

– ΔI_L(SC)

Fault Conditions: Overvoltage Protection (Crowbar)

V

IN

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

muchhigherthannominallevels.Thecrowbarcauseshuge

currents to ﬂow, that blow the fuse to protect against a

shorted top MOSFET if the short occurs while the control-

ler is operating.

1μF

+

C

IN

0.22μF

BAT85

V

IN

LTC3834

VN2222LL

TG1

SW

R

N-CH

SENSE

A comparator monitors the output for overvoltage con-

ditions. The comparator (OV) detects overvoltage faults

greaterthan10%abovethenominaloutputvoltage. When

this condition is sensed, the top MOSFET is turned off and

the bottom MOSFET is turned on until the overvoltage

condition is cleared. The bottom MOSFET remains on

continuously for as long as the overvoltage condition

V

OUT

EXTV

CC

L1

+

C

OUT

BG1

PGND

3834 F06

Figure 6. Capacitive Charge Pump for EXTV_CC

persists; if V

returns to a safe level, normal operation

OUT

automatically resumes. A shorted top MOSFET will result

in a high current condition which will open the system

fuse. The switching regulator will regulate properly with

a leaky top MOSFET by altering the duty cycle to accom-

modate the leakage.

3834fb

18

LTC3834

APPLICATIONS INFORMATION

Phase-Locked Loop and Frequency Synchronization

If the external clock frequency is greater than the internal

oscillator’s frequency, f , then current is sourced con-

OSC

The LTC3834 has a phase-locked loop (PLL) comprised of

aninternalvoltage-controlledoscillator(VCO)andaphase

detector. This allows the turn-on of the top MOSFET (TG)

to be locked to the rising edge of an external clock signal

applied to the PLLIN/MODE pin. The phase detector is

an edge sensitive digital type that provides zero degrees

phase shift between the external and internal oscillators.

This type of phase detector does not exhibit false lock to

harmonics of the external clock.

tinuously from the phase detector output, pulling up the

PLLLPF pin. When the external clock frequency is less

than f , current is sunk continuously, pulling down

OSC

the PLLLPF pin. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

the phase difference. The voltage on the PLLLPF pin is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

The output of the phase detector is a pair of comple-

mentary current sources that charge or discharge the

external ﬁlter network connected to the PLLLPF pin. The

relationship between the voltage on the PLLLPF pin and

operating frequency, when there is a clock signal applied

to PLLIN/MODE, is shown in Figure 7 and speciﬁed in the

Electrical Characteristics table. Note that the LTC3834 can

onlybesynchronizedtoanexternalclockwhosefrequency

is within range of the LTC3834’s internal VCO, which is

nominally 115kHz to 800kHz. This is guaranteed to be

between 140kHz and 650kHz. A simpliﬁed block diagram

is shown in Figure 8.

the ﬁlter capacitor C holds the voltage.

LP

The loop ﬁlter components, C and R , smooth out

LP

the current pulses from the phase detector and provide a

stable input to the voltage-controlled oscillator. The ﬁlter

components C and R determine how fast the loop

LP

acquires lock. Typically R = 10k and C is 2200pF to

LP

0.01μF.

Typically,theexternalclock(onPLLIN/MODEpin)inputhigh

threshold is 1.6V, while the input low threshold is 1.2V.

900

800

700

600

500

400

300

200

100

0

2.4V

R

LP

C

LP

PLLLPF

PLLIN/

MODE

DIGITAL

PHASE/

FREQUENCY

DETECTOR

EXTERNAL

OSCILLATOR

0

0.5

1

1.5

2

2.5

3834 F08

PLLLPF PIN VOLTAGE (V)

3835 F07

Figure 8. Phase-Locked Loop Block Diagram

Figure 7. Relationship Between Oscillator Frequency and Voltage

at the PLLLPF Pin When Synchronizing to an External Clock

3834fb

19

LTC3834

APPLICATIONS INFORMATION

Table 2 summarizes the different states in which the

PLLLPF pin can be used.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3834 circuits: 1) IC V current, 2) INTV

IN

CC

Table 2

2

regulator current, 3) I R losses, 4) Topside MOSFET

PLLLPF PIN

0V

PLLIN/MODE PIN

DC Voltage

FREQUENCY

transition losses.

250kHz

400kHz

1. The V current has two components: the ﬁrst is the

IN

Floating

DC Voltage

DCsupplycurrentgivenintheElectricalCharacteristics

table, which excludes MOSFET driver and control cur-

rents; the second is the current drawn from the 3.3V

INTV

DC Voltage

530kHz

CC

RC Loop Filter

Clock Signal

Phase-Locked to External Clock

Minimum On-Time Considerations

Minimum on-time, t , is the smallest time duration

linear regulator output. V current typically results in

IN

a small (< 0.1%) loss.

ON(MIN)

that the LTC3834 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that

2. INTV current is the sum of the MOSFET driver and

CC

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge dQ moves

from INTV to ground. The resulting dQ/dt is a cur-

CC

V_OUT

V_IN(f)

t_ON(MIN)

<

rent out of INTV that is typically much larger than the

CC

control circuit current. In continuous mode, I

GATECHG

= f(Q + Q ), where Q and Q are the gate charges of

T

B

T

B

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

the topside and bottom side MOSFETs.

Supplying INTV power through the EXTV switch

CC

input from an output-derived source will scale the V

IN

current required for the driver and control circuits by

The minimum on-time for the LTC3834 is approximately

200ns. However, as the peak sense voltage decreases

the minimum on-time gradually increases up to about

250ns. This is of particular concern in forced continuous

applications with low ripple current at light loads. If the

duty cycle drops below the minimum on-time limit in this

situation, a signiﬁcant amount of cycle skipping can occur

with correspondingly larger current and voltage ripple.

a factor of (Duty Cycle)/(Efﬁciency). For example, in a

20V to 5V application, 10mA of INTV current results

CC

in approximately 2.5mA of V current. This reduces

IN

the mid-current loss from 10% or more (if the driver

was powered directly from V ) to only a few percent.

IN

2

3. I R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resis-

tor, and input and output capacitor ESR. In continuous

mode the average output current ﬂows through L and

Efﬁciency Considerations

R

, but is “chopped” between the topside MOSFET

SENSE

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

andthesynchronousMOSFET.IfthetwoMOSFETshave

approximately the same R

, then the resistance

DS(ON)

of one MOSFET can simply be summed with the resis-

2

tances of L, R

and ESR to obtain I R losses. For

DS(ON)

SENSE

example, if each R

= 30mΩ, R = 50mΩ, R

L SENSE

= 10mΩ and R

= 40mΩ (sum of both input and

ESR

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

output capacitance losses), then the total resistance

is 130mΩ. This results in losses ranging from 3% to

where L1, L2, etc. are the individual losses as a percent-

age of input power.

13% as the output current increases from 1A to 5A for

3834fb

20

LTC3834

APPLICATIONS INFORMATION

a 5V output, or a 4% to 20% loss for a 3.3V output.

test point. The DC step, rise time and settling at this test

point truly reﬂects the closed-loop response. Assuming a

predominantlysecondordersystem,phasemarginand/or

damping factor can be estimated using the percentage of

overshoot seen at this pin. The bandwidth can also be

Efﬁciency varies as the inverse square of V

for the

OUT

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

estimated by examining the rise time at the pin. The I

TH

external components shown in the Typical Application

circuit will provide an adequate starting point for most

applications.

4. TransitionlossesapplyonlytothetopsideMOSFET, and

become signiﬁcant only when operating at high input

voltages (typically 15V or greater). Transition losses

can be estimated from:

The I series R -C ﬁlter sets the dominant pole-zero

TH

C

loop compensation. The values can be modiﬁed slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the ﬁnal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1μs to 10μs will

2

Transition Loss = (1.7) V

I

C

f

IN O(MAX) RSS

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efﬁciency degradation in portable systems. It is

very important to include these “system” level losses

during the design phase. The internal battery and fuse

resistance losses can be minimized by making sure that

produce output voltage and I pin waveforms that will

TH

C

has adequate charge storage and very low ESR at

give a sense of the overall loop stability without break-

ing the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This

IN

the switching frequency. A 25W supply will typically

require a minimum of 20μF to 40μF of capacitance hav-

ing a maximum of 20mΩ to 50mΩ of ESR. Other losses

including Schottky conduction losses during dead-time

and inductor core losses generally account for less than

2% total additional loss.

Checking Transient Response

is why it is better to look at the I pin signal which is in

TH

the feedback loop and is the ﬁltered and compensated

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

control loop response. The gain of the loop will be in-

creased by increasing R and the bandwidth of the loop

C

will be increased by decreasing C . If R is increased by

load current. When a load step occurs, V

shifts by an

C

OUT

the same factor that C is decreased, the zero frequency

amount equal to ΔI

(ESR), where ESR is the effective

C

LOAD

will be kept the same, thereby keeping the phase shift the

same in the most critical frequency range of the feedback

loop. The output voltage settling behavior is related to the

stability of the closed-loop system and will demonstrate

the actual overall supply performance.

series resistance of C . ΔI

also begins to charge or

generating the feedback error signal that

OUT

LOAD

discharge C

OUT

forces the regulator to adapt to the current change and

return V to its steady-state value. During this recov-

OUT

ery time V

can be monitored for excessive overshoot

OUT

or ringing, which would indicate a stability problem.

OPTI-LOOP compensation allows the transient response

to be optimized over a wide range of output capacitance

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

and ESR values. The availability of the I pin not only

TH

with C , causing a rapid drop in V . No regulator can

OUT

allows optimization of control loop behavior but also pro-

vides a DC coupled and AC ﬁltered closed-loop response

alter its delivery of current quickly enough to prevent this

3834fb

21

LTC3834

APPLICATIONS INFORMATION

sudden step change in output voltage if the load switch

ThepowerdissipationonthetopsideMOSFETcanbeeasily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

resistance is low and it is driven quickly. If the ratio of

C

to C

is greater than 1:50, the switch rise time

results in: R

= 0.035Ω/0.022Ω, C

= 215pF. At

LOAD

OUT

DS(ON)

MILLER

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10μF capacitor would

maximum input voltage with T(estimated) = 50°C:

LOAD

1.8V

22V

2

require a 250μs rise time, limiting the charging current

to about 200mA.

P_MAIN

=

5

( )

1+(0.005)(50°C–25°C) •

[

]

5A

2

⎛

⎞

2

0.035Ω + 22V

) (

4Ω 215pF •

)(

(

)

(

)

⎜

⎝

⎟

⎠

Design Example

1

As a design example, assume V = 12V(nominal), V =

⎡

⎤

IN

+

300kHz = 332mW

(

)

⎢

⎣

⎥

⎦

22V(max), V

= 1.8V, I

= 5A, and f = 250kHz.

OUT

MAX

5–2.3 2.3

Theinductancevalueischosenﬁrstbasedona30%ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. Tie the PLLLPF

pin to GND, generating 250kHz operation. The minimum

inductance for 30% ripple current is:

A short-circuit to ground will result in a folded back cur-

rent of:

25mV 1⎛ 120ns(22V)⎞

I_SC=

–

= 2.1A

⎜

⎟

⎝

⎠

0.01Ω 2

3.3μH

⎛

⎞

V_OUT

(f)(L)

V_OUT

V_IN

with a typical value of R

and δ = (0.005/°C)(20) =

ΔI_L=

1–

DS(ON)

⎜

⎟

⎝

⎠

0.1. TheresultingpowerdissipatedinthebottomMOSFET

is:

A 4.7μH inductor will produce 23% ripple current and a

3.3μH will result in 33%. The peak inductor current will

be the maximum DC value plus one half the ripple cur-

rent, or 5.84A, for the 3.3μH value. Increasing the ripple

current will also help ensure that the minimum on-time

of 180ns is not violated. The minimum on-time occurs at

22V –1.8V

2

P_SYNC

=

2.1A 1.125 0.022Ω

(

) (

)(

)

22V

=100mW

which is less than under full-load conditions.

C is chosen for an RMS current rating of at least 3A at

maximum V :

IN

temperature assuming only this channel is on. C

is

OUT

V_OUT

V_IN(MAX)f 22V(250kHz)

1.8V

t_ON(MIN)

=

= 327ns

chosen with an ESR of 0.02Ω for low output ripple. The

output ripple in continuous mode will be highest at the

maximum input voltage. The output voltage ripple due to

ESR is approximately:

The R

resistor value can be calculated by using the

maximum current sense voltage speciﬁcation with some

accommodation for tolerances:

SENSE

V

= R (ΔI ) = 0.02Ω(1.67A) = 33mV

ESR L P-P

ORIPPLE

80mV

5.84A

R_SENSE

≤

≈0.012Ω

Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields

an output voltage of 1.816V.

3834fb

22

LTC3834

APPLICATIONS INFORMATION

PC Board Layout Checklist

side” of the LTC3834 and occupy minimum PC trace

area.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 9. The Figure 10 illustrates the

current waveforms present in the various branches of the

synchronous regulator operating in the continuous mode.

Check the following in your layout:

7. Use a modiﬁed “star ground” technique: a low imped-

ance, large copper area central grounding point on

the same side of the PC board as the input and output

capacitors with tie-ins for the bottom of the INTV

CC

decouplingcapacitor,thebottomofthevoltagefeedback

resistive divider and the SGND pin of the IC.

1. Is the top N-channel MOSFET M1 located within 1cm

PC Board Layout Debugging

of C ?

IN

It is helpful to use a DC-50MHz current probe to monitor

thecurrentintheinductorwhiletestingthecircuit.Monitor

the output switching node (SW pin) to synchronize the

oscilloscope to the internal oscillator and probe the actual

outputvoltageaswell. Checkforproperperformanceover

the operating voltage and current range expected in the

application. The frequency of operation should be main-

tained over the input voltage range down to dropout and

until the output load drops below the low current opera-

tion threshold—typically 10% of the maximum designed

current level in Burst Mode operation.

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

of C

must return to the combined C

(–) ter-

INTVCC

OUT

minals. The path formed by the top N-channel MOSFET,

Schottky diode and the C capacitor should have short

IN

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible

to the (–) terminals of the input capacitor by placing

the capacitors next to each other and away from the

Schottky loop described above.

3. Does the LTC3834 V pin resistive divider connect to

FB

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawell-designed,lownoisePCBimplementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required.

the (+) terminals of C ? The resistive divider must be

OUT

connected between the (+) terminal of C

and signal

OUT

ground. The feedback resistor connections should not

be along the high current input feeds from the input

capacitor(s).

–

+

4. Are the SENSE and SENSE leads routed together with

minimumPCtracespacing?Theﬁltercapacitorbetween

Reduce V from its nominal level to verify operation

+

–

IN

SENSE and SENSE should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the SENSE resistor.

of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

5. Is the INTV decoupling capacitor connected close to

CC

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

theIC, betweentheINTV andthepowergroundpins?

CC

ThiscapacitorcarriestheMOSFETdriverscurrentpeaks.

Anadditional1μFceramiccapacitorplacedimmediately

next to the INTV and PGND pins can help improve

CC

noise performance substantially.

6. Keep the switching node (SW), top gate node (TG), and

boost node (BOOST) away from sensitive small-signal

nodes. All of these nodes have very large and fast mov-

ing signals and therefore should be kept on the “output

3834fb

23

LTC3834

APPLICATIONS INFORMATION

high current output loading at lower input voltages, look

for inductive coupling between CIN, Schottky and the top

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

when the current sensing leads are hooked up backwards.

The output voltage under this improper hookup will still

be maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

V

IN

C1

1nF

C

B

C

IN

M1

M2

L1

OUT

D1

OPTIONAL

C

OUT

D

B

3834 F09

Figure 9. LTC3834 Recommended Printed Circuit Layout Diagram

L1

R

SENSE

SW

V

OUT

IN

R

IN

C

IN

D1

C

OUT

R

L1

3834 F10

BOLD LINES INDICATE HIGH SWITCHING

CURRENT. KEEP LINES TO A MINIMUM LENGTH.

Figure 10. Branch Current Waveforms

3834fb

24

LTC3834

TYPICAL APPLICATIONS

High Efﬁciency 9.5V, 3A Step-Down Converter

INTV

CC

100k

V

IN

CLKOUT

PLLLPF

RUN

V

IN

10V TO 36V

C

10μF

IN

M1

TG

C

B

0.01μF

0.22μF

PGOOD

TRACK/SS

L1

BOOST

SW

7.2μH

0.015Ω

V

9.5V

3A

OUT

I

TH

560pF

LTC3834

D

B

100pF

105k

C

OUT

150μF

CMDSH-3

SGND

PLLIN/MODE

INTV

EXTV

CC

4.7μF

39.2k

M2

V

FB

BG

–

+

SENSE

432k

22pF

PGND

3834 TA02

M1, M2: Si4840DY

L1: CDEP105-7R2M

C

OUT

: SANYO 10TPD150M

High Efﬁciency 12V to 1.8V, 2A Step-Down Converter

V

12V

IN

CLKOUT

PLLLPF

RUN

V

IN

C

10μF

IN

M1

TG

C

B

0.01μF

0.22μF

PGOOD

TRACK/SS

L1

BOOST

SW

3.3μH

20mΩ

V

1.8V

2A

I

TH

OUT

1000pF

48.7k

D

B

LTC3834

100pF

C

OUT

CMDSH-3

100μF

SGND

PLLIN/MODE

INTV

CC

CERAMIC

4.7μF

68.1k

84.5k

EXTV

CC

M2

V

BG

FB

–

+

SENSE

PGND

100pF

3834 TA03

M1, M2: Si4840DY

L1: TOKO DS3LC A915AY-3R3M

3834fb

25

LTC3834

TYPICAL APPLICATIONS

High Efﬁciency 5V, 5A Step-Down Converter

V

IN

CLKOUT

PLLLPF

RUN

V

IN

5.5V TO 36V

C

10μF

IN

M1

TG

C

B

0.01μF

0.22μF

PGOOD

TRACK/SS

L1

BOOST

SW

3.3μH

0.012Ω

V

5V

5A

I

TH

OUT

560pF

D

B

LTC3834

150pF

54k

C

OUT

CMDSH-3

150μF

SGND

PLLIN/MODE

INTV

EXTV

CC

4.7μF

69.8k

M2

V

FB

BG

–

+

SENSE

365k

PGND

39pF

3834 TA04

M1, M2: Si4840DY

L1: CDEP105-3R2M

C

OUT

: SANYO 10TPD150M

High Efﬁciency 1.2V, 5A Step-Down Converter

V

IN

CLKOUT

PLLLPF

RUN

V

IN

INTV

CC

4V TO 36V

C

10μF

IN

GND

M1

TG

10k

C

B

0.01μF

0.22μF

PGOOD

TRACK/SS

L1

BOOST

SW

2.2μH

V

1.2V

5A

0.012Ω

OUT

I

TH

2.2nF

26.1k

LTC3834

D

B

100pF

C

OUT

CMDSH-3

150μF

s2

SGND

PLLIN/MODE

INTV

EXTV

CC

4.7μF

68.1k

34k

M2

V

FB

BG

–

+

SENSE

390pF

PGND

3834 TA05

M1, M2: Si4840DY

L1: CDEP105-2R2M

C

OUT

: SANYO 10TPD150M

3834fb

26

LTC3834

PACKAGE DESCRIPTION

FE Package

20-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1663)

Exposed Pad Variation CB

6.40 – 6.60*

3.86

(.152)

(.252 – .260)

3.86

(.152)

20 1918 17 16 15 14 1312 11

6.60 p 0.10

2.74

(.108)

4.50 p 0.10

6.40

(.252)

BSC

2.74

(.108)

SEE NOTE 4

0.45 p 0.05

1.05 p0.10

0.65 BSC

5

7

8

1

2

3

4

6

9 10

RECOMMENDED SOLDER PAD LAYOUT

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0o – 8o

0.65

(.0256)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

FE20 (CB) TSSOP 0204

0.195 – 0.30

(.0077 – .0118)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

MILLIMETERS

(INCHES)

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

UFD Package

20-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1711 Rev B)

PIN 1 NOTCH

R = 0.20 OR

C = 0.35

0.75 p 0.05

1.50 REF

19

4.00 p 0.10

(2 SIDES)

R = 0.05 TYP

20

0.70 p 0.05

0.40 p 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2.65 p 0.05

3.65 p 0.05

2

4.50 p 0.05

3.10 p 0.05

1.50 REF

5.00 p 0.10

(2 SIDES)

2.50 REF

3.65 p 0.10

2.65 p 0.10

PACKAGE

OUTLINE

0.25 p 0.05

0.50 BSC

2.50 REF

(UFD20) QFN 0506 REV

B

0.25 p 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

R = 0.115

TYP

4.10 p 0.05

5.50 p 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

3834fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC3834

TYPICAL APPLICATION

V

IN

CLKOUT

PLLLPF

RUN

PGOOD

TRACK/SS

V

IN

4V TO 36V

C

IN

10μF

M1

TG

C

B

0.01μF

0.22μF

L1

3.2μH

BOOST

SW

0.012Ω

V

3.3V

5A

I

OUT

TH

560pF

D

B

LTC3834

150pF

C

54k

OUT

CMDSH-3

150μF

SGND

INTV

EXTV

CC

4.7μF

68.1k

PLLIN/MODE

M2

V

BG

FB

–

+

SENSE

215k

PGND

39pF

3834 F11

M1, M2: Si4840DY

L1: CDEP105-2R2M

C

OUT

: SANYO 10TPD150M

Figure 11. High Efﬁciency Step-Down Converter

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

LTC1735

High Efﬁciency Synchronous Step-Down Switching Regulator Output Fault Protection, 16-Pin SSOP

LTC1778/

LTC1778-1

Up to 97% Efﬁciency, 4V ≤ V ≤ 36V, 0.8V ≤ V

≤ (0.9)(V ),

IN

No R

™ Current Mode Synchronous Step-Down

IN

OUT

SENSE

I

Up to 20A

OUT

Controllers

LTC3708

Dual, 2-Phase, DC/DC Controller with Output Tracking

Current Mode, No R , Up/Down Tracking, Synchronizable

SENSE

LTC3727/

LTC3727-1

High Efﬁciency, 2-Phase, Synchronous Step-Down Switching

Regulators

2-Phase Operation; 4V ≤ V ≤ 36V, 0.8V ≤ V

≤ 14V,

OUT

IN

99% Duty Cycle, 5mm × 5mm QFN, SSOP-28

LTC3728

LTC3729

Dual, 550kHz, 2-Phase Synchronous Step-Down Controller

Dual 180° Phased Controllers, V 3.5V to 35V, 99% Duty Cycle,

IN

5mm × 5mm QFN, SSOP-28

20A to 200A, 550kHz PolyPhase Synchronous Controller

Expandable from 2-Phase to 12-Phase, Uses All Surface Mount

Components, V Up to 36V

IN

LTC3731

LT3800

3- to 12-Phase Step-Down Synchronous Controller

High Voltage Synchronous Regulator Controller

60A to 240A Output Current, 0.6V ≤ V

≤ 6V, 4.5V ≤ V ≤ 32V

OUT IN

V

IN

up to 60V, I

≤ 20A, Current Mode, Onboard Bias Regulator,

OUT

Burst Mode Operation, 16-Lead TSSOP Package

LTC3826/

LTC3826-1

30μA I , Dual, 2-Phase Synchronous Step-Down Controller

Q

2-Phase Operation; 30μA One Channel No-Load I (50μA Total),

Q

4V ≤ V ≤ 36V, 0.8V ≤ V

≤ 10V

IN

OUT

LTC3827/

LTC3827-1

Low I Dual Synchronous Controller

2-Phase Operation; 115μA Total No Load I , 4V ≤ V ≤ 36V 80μA

Q

IN

No-Load I with One Channel On

Q

LTC3835/

LTC3835-1

Low IQ Synchronous Step-Down Controller

80μA No Load IQ, 4V ≤ V ≤ 36V, 0.8V ≤ V

≤ 10V

OUT

IN

LT3844

High Voltage Current Mode Controller with Programmable

Operating Frequency

V

up to 60V, I

≤ 5A Onboard Bias Regulator, Burst Mode

OUT

IN

Operation, Sync Capability, 16-Lead TSSOP Package

LTC3845

LTC3850

Low I Synchronous Step-Down Controller

4V ≤ V ≤ 60V, 1.23V ≤ V ≤ 36V, 120μA Quiescent Current

Q

IN

OUT

Dual, 2-Phase Synchronous Step-Down DC/DC Controller

2-Phase Operation; 4V ≤ V ≤ 24V, 95% Efﬁciency, No R

IN SENSE

Option, I

up to 20A, 4mm × 4mm QFN

OUT

No R

is a trademark of Linear Technology Corporation.

SENSE

3834fb

LT 0608 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

28

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3834EUFD-PBF
厂家：	Linear
描述：	30μA IQ Synchronous Step-Down Controller 30μA IQ同步降压型控制器控制器
文件：	总28页 (文件大小：427K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3834EUFD-PBF [Linear]

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