LTC3836EGN-PBF [Linear]
Dual 2-Phase, No RSENSETM Low VIN Synchronous Controller; 双2相，无RSENSETM低VIN同步控制器
| 型号： | LTC3836EGN-PBF |
| 厂家： | 
Linear |
| 描述： | Dual 2-Phase, No RSENSETM Low VIN Synchronous Controller |
| 文件： | 总28页 (文件大小：445K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3836
Dual 2-Phase,
No R
TM Low V
SENSE
IN
Synchronous Controller
FEATURES
DESCRIPTION
The LTC®3836 is a 2-phase dual output synchronous
step-down switching regulator controller with tracking
that drives external N-channel power MOSFETs using few
external components. The constant-frequency current
n
No Current Sense Resistors Required
n
Out-of-Phase Controllers Reduce Required Input
Capacitance
n
All N-Channel Synchronous Drive
n
V Range: 2.75V to 4.5V
mode architecture with MOSFET V sensing eliminates
IN
DS
n
Constant-Frequency Current Mode Operation
the need for sense resistors and improves efficiency.
The power loss and noise due to the ESR of the input
capacitance are minimized by operating the two control-
lersout-of-phase. Pulse-skippingoperationprovideshigh
efficiency at light loads. The 97% duty cycle capability
provides low dropout operation, extending operating time
in battery-powered systems.
n
0.6V 1.5% Voltage Reference
n
Low Dropout Operation: 97% Duty Cycle
n
True PLL for Frequency Locking or Adjustment
n
Selectable Pulse-Skipping/Continuous Operation
n
Tracking Function
Internal Soft-Start Circuitry
n
n
Power Good Output Voltage Monitor
The operating frequency is selectable from 300kHz to
750kHz, allowing the use of small surface mount induc-
tors and capacitors. For noise sensitive applications, the
LTC3836 operating frequency can be externally synchro-
nized from 250kHz to 850kHz.
n
Output Overvoltage Protection
n
Micropower Shutdown: I = 6.5μA
Q
n
Tiny Low Profile (4mm × 5mm) QFN and Narrow
SSOP Packages
The LTC3836 features an internal 1ms soft-start that can
be extended with an external capacitor. A tracking input al-
lows the second output to track the first during start-up.
APPLICATIONS
n
General Purpose 3.3V to 1.X Supplies
n
Single Lithium-Ion Powered Devices
Distributed DC Power Systems
The LTC3836 is available in the tiny thermally enhanced
(4mm × 5mm) QFN and 28-lead narrow SSOP packages.
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. No R
SENSE
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 5481178, 5929620, 6144194, 6304066,
6498466, 6580258, 6611131.
TYPICAL APPLICATION
High Efficiency, 2-Phase, Dual Synchronous DC/DC Step-Down Converter
Efficiency/Power Loss vs Load Current
100
90
80
70
60
50
40
30
20
10
0
10000
V
IN
3.3V
3.3V-1.8V
EFFICIENCY
22μF
× 3
V
IN
BOOST1 BOOST2
3.3V-1.2V
EFFICIENCY
+
+
SENSE1 SENSE2
1000
100
10
TG1
TG2
0.47μH
0.47μH
SW1
SW2
LTC3836
3.3V-1.2V
POWER LOSS
BG1
BG2
PGND
3.3V-1.8V
POWER LOSS
59k
118k
V
V
OUT2
OUT1
V
V
FB1
FB2
1.8V AT
15A
1.2V AT
I
I
TH1
TH2
15A
820pF
15k
820pF
15k
SGND
CIRCUIT OF FIGURE 15
1000 10000
LOAD CURRENT (mA)
59k
100μF
× 2
100μF
× 2
1
59k
10
100
100000
3836 TA01b
3836 TA01
3836fa
1
LTC3836
ABSOLUTE MAXIMUM RATINGS
(Note 1)
BOOST1, BOOST2 Voltages ....................... –0.3V to 10V
SW1, SW2 Voltages............................... –2V to V + 1V
IN
Input Supply Voltage (V )........................ –0.3V to 4.5V
PGOOD....................................................... –0.3V to 10V
Operating Temperature Range (Note 2).... –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
Junction Temperature (Note 3) ............................. 125°C
IN
PLLLPF, RUN/SS, SYNC/FCB,
+
+
SENSE1 , SENSE2 ,
IPRG1, IPRG2 Voltages..................–0.3V to (V + 0.3V)
IN
V
, V , I , I
,
FB1 FB2 TH1 TH2
TRACK/SS2 Voltages ................................ –0.3V to 2.4V
PIN CONFIGURATION
TOP VIEW
TOP VIEW
+
1
2
SENSE1
BOOST1
PGND
BG1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SW1
N/C
28 27 26 25 24 23
3
IPRG1
VFB1
ITH1
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
BG1
4
V
FB1
TH1
SYNC/FCB
TG1
5
SYNC/FCB
TG1
I
IPRG2
PLLLPF
SGND
6
IPRG2
PLLLPF
SGND
PGND
TG2
29
7
PGND
TG2
8
V
IN
RUN/SS
N/C
9
RUN/SS
BG2
V
IN
TRACK/SS2
VFB2
10
11
12
13
14
TRACK/SS2
BG2
N/C
V
FB2
TH2
9
10 11 12 13 14
UFD PACKAGE
PGND
I
BOOST2
PGOOD
SW2
+
SENSE2
28-LEAD (4mm × 5mm) PLASTIC QFN
GN PACKAGE
28-LEAD PLASTIC SSOP
T
= 125°C, θ = 43°C/W
JMAX
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 90°C/W
JA
JMAX
ORDER INFORMATION
LEAD FREE FINISH
LTC3836EGN#PBF
LTC3836EUFD#PBF
TAPE AND REEL
PART MARKING
LTC3836EGN
3836
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3836EGN#TRPBF
LTC3836EUFD#TRPBF
28-Lead Plastic SSOP
–40°C to 85°C
–40°C to 85°C
28-Lead (4mm × 5mm) Plastic QFN
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
Input DC Supply Current
Normal Mode
Shutdown
(Note 4)
450
6.5
4
700
15
μA
μA
μA
RUN/SS = V
IN
RUN/SS = 0V
= UVLO Threshold –200mV
UVLO
10
V
IN
3836fa
2
LTC3836
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Undervoltage Lockout Threshold
V
V
Falling
Rising
1.95
2.15
2.25
2.45
2.55
2.75
V
V
IN
IN
Shutdown Threshold at RUN/SS
Start-Up Current Source
0.45
0.4
0.65
0.65
0.6
0.85
1
V
μA
RUN/SS = 0V
l
Regulated Feedback Voltage
Output Voltage Line Regulation
Output Voltage Load Regulation
–40°C to 85°C (Note 5)
0.591
0.609
0.2
V
2.75V < V < 4.5V (Note 5)
0.05
mV/V
IN
I
TH
I
TH
= 0.9V (Note 5)
= 1.7V
0.12
0.5
%
%
–0.12
–0.5
V
Input Current
(Note 5)
10
1.5
0.68
20
50
2.2
0.7
nA
μA
V
FB1,2
TRACK/SS2 Input Current
TRACK/SS2 = 0V
1
Overvoltage Protect Threshold
Overvoltage Protect Hysteresis
Auxiliary Feedback Threshold
Measured at V
0.66
FB
mV
V
SYNC/FCB Ramping Positive
C = 3000pF
0.525
0.6
40
0.675
Top Gate (TG) Drive 1, 2 Rise Time
Top Gate (TG) Drive 1, 2 Fall Time
Bottom Gate (BG) Drive 1, 2 Rise Time
Bottom Gate (BG) Drive 1, 2 Fall Time
ns
ns
ns
ns
L
C = 3000pF
L
40
C = 3000pF
L
50
C = 3000pF
L
40
l
l
l
Maximum Current Sense Voltage (ΔV
)
IPRG = Floating
IPRG = 0V
110
70
122
82
135
95
mV
mV
mV
SENSE(MAX)
+
(SENSE – SW)
IPRG = V
185
202
220
IN
Maximum Duty Cycle
Soft-Start Time
In Dropout
97
%
Time for V to Ramp from 0.05V to 0.55V
0.6
0.8
1
ms
FB1
Oscillator and Phase-Locked Loop
Oscillator Frequency
Unsynchronized (SYNC/FCB Not Clocked)
PLLLPF = Floating
480
260
650
550
300
750
600
340
825
kHz
kHz
kHz
PLLLPF = 0V
PLLLPF = V
IN
Phase-Locked Loop Lock Range
SYNC/FCB Clocked
l
l
Minimum Synchronizable Frequency
Maximum Synchronizable Frequency
200
250
kHz
kHz
850
1150
Phase Detector Output Current
Sinking
f
f
> f
> f
–4
4
μA
μA
OSC
OSC
SYNC/FCB
SYNC/FCB
Sourcing
PGOOD Output
PGOOD Voltage Low
PGOOD Trip Level
I
Sinking 1mA
140
mV
PGOOD
V
with Respect to Set Output Voltage
FB
–13
–16
7
–10.0
–13.3
10.0
–7
–10
13
%
%
%
%
V
V
V
V
< 0.6V, Ramping Positive
< 0.6V, Ramping Negative
> 0.6V, Ramping Negative
> 0.6V, Ramping Positive
FB
FB
FB
FB
10
13.3
16
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: T is calculated from the ambient temperature T and power dissi-
J A
pation P according to the following formula: T = T + (P • θ °C/W)
D
J
A
D
JA
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5: The LTC3836 is tested in a feedback loop that servos I to a
Note 2: The LTC3836 is guaranteed to meet specified performance from
0°C to 85°C. Specifications over the –40°C to 85°C operating range are
assured by design, characterization and correlation with statistical process
controls.
TH
specified voltage and measures the resultant V voltage.
FB
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as shown in Figure 1.
3836fa
3
LTC3836
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
Load Step
(Forced Continuous Mode)
Load Step
(Pulse-Skipping Mode)
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
V
V
OUT
OUT
AC COUPLED
100mV/DIV
AC COUPLED
100mV/DIV
PULSE-SKIPPING
MODE
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
FORCED
CONTINUOUS
MODE
3836 G03
3836 G02
V
V
= 3.6V
100μs/DIV
V
V
= 3.6V
100μs/DIV
IN
OUT
IN
OUT
SYNC/FCB = V
IN
= 1.8V
= 1.8V
SYNC/FCB = 0V
1000 10000
LOAD CURRENT (mA)
PULSE-SKIPPING MODE: 400MA TO 4A
CIRCUIT OF FIGURE 15
CONTINUOUS MODE: 400mA TO 4A
CIRCUIT OF FIGURE 15
1
10
100
V
= 3.3V
OUT
3836 G01
IN
V
= 1.5V
CIRCUIT OF FIGURE 15
Light Load
(Pulse-Skipping Mode)
Light Load
(Forced Continuous Mode)
Tracking Start-Up with Internal
Soft-Start (CRUN/SS = 0μF)
V
OUT1
V
1.8V
V
SW
SW
2V/DIV
2V/DIV
V
V
OUT
OUT
20mV/DIV
V
OUT2
1.2V
20mV/DIV
AC COUPLED
AC COUPLED
500mV/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
3836 G04
3836 G05
3836 G06
V
V
LOAD
= 3.6V
2μs/DIV
V
V
LOAD
= 3.6V
2μs/DIV
V = 3.6V
IN
250μs/DIV
= 1Ω
IN
IN
= 1.8V
= 1.8V
R
= R
LOAD1 LOAD2
OUT
OUT
I
= 300mA
I
= 300mA
CIRCUIT OF FIGURE 15
CIRCUIT OF FIGURE 15
CIRCUIT OF FIGURE 15
Tracking Start-Up with External
Soft-Start (CRUN/SS = 0.01μF)
Oscillator Frequency
vs Input Voltage
Sequential Start-Up
5
4
V
V
OUT1
OUT1
1.8V
1.8V
3
2
V
1
OUT2
V
OUT2
1.2V
1.2V
0
500mV/DIV
500mV/DIV
–1
–2
–3
–4
–5
3836 G07
3836 G10
V
= 3.6V
LOAD1
2.50ms/DIV
LOAD2
V
= 3.3V
IN
LOAD1
4ms/DIV
IN
R
= R
= 1Ω
R
= R = 1Ω
LOAD2
CIRCUIT OF FIGURE 15
V
V
: INTERNAL SOFT-START
OUT1
: C
= 0.047μF
OUT2 TRACK/SS
2.5
3.0
3.5
4.0
4.5
CIRCUIT OF FIGURE 15
INPUT VOLTAGE (V)
3836 G08
3836fa
4
LTC3836
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C unless otherwise noted.
Regulated Feedback Voltage
vs Temperature
Maximum Current Sense Voltage
vs ITH Pin Voltage
Shutdown (RUN/SS) Threshold
vs Temperature
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
100
80
60
40
20
0
0.606
0.605
0.604
0.603
0.602
0.601
0.600
0.599
0.598
0.597
0.596
0.595
0.594
FORCED CONTINUOUS
MODE
PULSE-SKIPPING
MODE
–20
0.5
1
I
1.5
VOLTAGE (V)
2
–60
60 80
–40 –20
0
20 40
100
20 40
–60 –40 –20
TEMPERATURE (°C)
0
60 80 100
TEMPERATURE (°C)
TH
3836 G09
3836 G12
3836 G11
RUN/SS Pull-Up Current
vs Temperature
Maximum Current Sense
Threshold vs Temperature
Oscillator Frequency
vs Temperature
10
8
1.0
0.9
0.8
0.7
0.6
0.5
0.4
135
130
125
120
I
= FLOAT
PRG
6
4
2
0
–2
–4
–6
–8
–10
115
40 60
–60 –40 –20
TEMPERATURE (°C)
0
20
80 100
–60 –40 –20
0
20 40 60 80 100
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
TEMPERATURE (°C)
3836 G13
3836 G14
3836 G15
Shutdown Quiescent Current
vs Input Voltage
RUN/SS Start-Up Current
vs Input Voltage
Undervoltage Lockout Threshold
vs Temperature
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
18
16
14
12
10
8
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
RUN/SS = 0V
V
RISING
IN
V
FALLING
IN
6
4
2
0
2.5
3.0
3.5
4.0
4.5
20 40
2.5
3.0
3.5
4.0
4.5
–60 –40 –20
0
60 80 100
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3836 G18
3836 G17
3836 G16
3836fa
5
LTC3836
PIN FUNCTIONS
(GN Package)/(UFD Package)
SW1/SW2 (Pins 1, 14)/(Pins 26, 11): Switch Node
Connection to Inductor and External MOSFETs. Also the
negative input to differential peak current comparator
and an input to the reverse current comparator. Normally
connected to the source of the main MOSFET, the drain of
the synchronous MOSFET, and the inductor.
smaller of 0.6V or the voltage on the TRACK/SS2 pin. An
internal 1.5μA pull-up current source is connected to this
pin. A capacitor to ground at this pin sets the ramp time
to final regulated output voltage. Alternatively, a resistor
divider on another voltage supply connected to this pin
allows the LTC3836 output to track the other supply dur-
ing start-up.
NC (Pins 2, 18)/(Pins 16, 28): No Connection.
PGOOD (Pin 13)/(Pin 10): Power-Good Output Voltage
Monitor Open-Drain Logic Output. This pin is pulled to
IPRG1/IPRG2 (Pins 3, 6)/(Pins 27, 3): Three-State Pins
to Select Maximum Peak Sense Voltage Threshold. These
pins select the maximum allowed voltage drop between
ground when the voltage on either feedback pin (V
FB2
,
FB1
V
) is not within 13.3% of its nominal set point.
+
the SENSE and SW pins (i.e., the maximum allowed drop
PGND(Pins17,22,26)/(Pins14,19,23):PowerGround.
These pins serve as the ground connection for the gate
drivers and the negative input to the reverse current
comparators. The Exposed Pad must be soldered to PCB
ground.
across the external main MOSFET) for each channel. Tie
to V , GND or float to select 202mV, 82mV, or 122mV
IN
respectively.
V
/V
(Pins 4, 11)/(Pins 1, 8): Feedback Pins.
FB1 FB2
Receives the remotely sensed feedback voltage for its con-
troller from an external resistor divider across the output.
RUN/SS (Pin 20)/(Pin 17): Run Control Input and Op-
tional External Soft-Start Input. Forcing this pin below
0.65V shuts down the chip (both channels). Driving this
I
/I
(Pins 5, 12)/(Pins 2, 9): Current Threshold
TH1 TH2
and Error Amplifier Compensation Point. Nominal operat-
ing range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
pin to V or releasing this pin enables the chip, using
IN
the chip’s internal soft-start. An external soft-start can
be programmed by connecting a capacitor between this
pin and ground.
PLLLPF (Pin 7)/(Pin 4): Frequency Set/PLL Lowpass
Filter. When synchronizing to an external clock, this pin
serves as the lowpass filter point for the phase-locked
loop. Normally a series RC is connected between this pin
and ground.
TG1/TG2 (Pins 23, 21)/(Pins 20, 18): Top Gate Drive
Output. These pins drive the gates of the external topside
MOSFETs. These pins have an output swing from PGND
to BOOST.
SYNC/FCB (Pin 24)/(Pin 21): This pin performs two
functions: 1) external clock synchronization input for
phase-locked loop, and 2) pulse-skipping operation or
forced continuous mode select. To synchronize with an
external clock using the PLL, apply a CMOS compatible
clock with a frequency between 250kHz and 850kHz. To
select pulse-skipping operation at light loads, tie this
Whennotsynchronizingtoanexternalclock,thispinserves
asthefrequencyselectinput. TyingthispintoGNDselects
300kHz operation; tying this pin to V selects 750kHz
IN
operation. Floating this pin selects 550kHz operation.
SGND(Pin8)/(Pin5):Small-SignalGround.Thispinserves
as the ground connection for most internal circuits.
pin to V . Grounding this pin selects forced continuous
IN
V
IN
(Pin 9)/(Pin 6): Small-Signal Power Supply. This
operation, which allows the inductor current to reverse.
When synchronized to an external clock, pulse-skipping
operation is enabled at light loads.
pin powers the entire chip except for the gate drivers.
Externally filtering this pin with a lowpass RC network
(e.g., R = 10Ω, C = 1μF) is suggested to minimize noise
pickup, especially in high load current applications.
BG1/BG2 (Pins 25, 19)/(Pins 22, 15): Bottom Gate
Drive Output. These pins drive the gates of the external
synchronous MOSFETs. These pins have an output swing
from PGND to BOOST.
TRACK/SS2(Pin10)/(Pin7):Channel2TrackingandSoft-
Start Input. The LTC3836 regulates the V voltage to the
FB2
3836fa
6
LTC3836
PIN FUNCTIONS (GN/UFD Package)
+
+
BOOST1/BOOST2 (Pins 27, 16)/(Pins 24, 13): Positive
Supply Pin for the Gate Driver Circuitry. A bootstrapped
capacitor, charged with an external Schottky diode and a
boost voltage source, is connected between the BOOST
and SW pins. Voltage swing at the BOOST pins is from
SENSE1 /SENSE2 (Pins 28, 5)/(Pins 25, 12): Positive
Input to Differential Current Comparator. Also powers the
gate drivers. Normally connected to the drain of the main
external MOSFET.
Exposed Pad (Pin 29) UFD Package Only: Must be sol-
dered to PCB ground.
boost source voltage (typically V ) to this boost source
IN
voltage + V .
IN
FUNCTIONAL DIAGRAM (Common Circuitry)
R
VIN
V
IN
(TO CONTROLLER 1, 2)
V
IN
C
VIN
UNDERVOLTAGE
LOCKOUT
VOLTAGE
REFERENCE
0.6V
REF
V
0.65μA
SHDN
RUN/SS
t
= 1ms
+
–
SEC
EXTSS
INTSS
SYNC/FCB
PLLLPF
PHASE
DETECTOR
SYNC DETECT
CLK1
CLK2
VOLTAGE
CONTROLLED
OSCILLATOR
SLOPE1
SLOPE2
SLOPE
COMP
–
–
+
V
FB1
UV1
PGOOD
FCB
FCB
OV1
SHDN
+
0.6V
0.54V
37362 FD
+
–
OV2
UV2
V
FB2
3836fa
7
LTC3836
FUNCTIONAL DIAGRAM (Controller 1)
BOOST1
V
IN
+
SENSE1
TG1
C
CB
IN
RS1
CLK1
S
R
Q
SWITCHING
LOGIC
PGND
SW1
BG1
ANTISHOOT
THROUGH
L1
AND
OV1
SC1
FCB
BLANKING
CIRCUIT
V
OUT1
BOOST1
C
OUT1
PGND
IREV1
SLOPE1
–
+
SW1
ICMP
+
IPRG1
SENSE1
SHDN
–
R1B
R1A
V
FB1
+
EAMP
+
–
EXTSS
INTSS
0.6V
I
TH1
R
ITH1
0.12V
+
–
C
ITH1
SC1
SCP
V
FB1
V
PGND
SW1
+
–
–
+
FB1
OV1
OVP
IREV1
RICMP
0.68V
3836 FD2
IPROG1 FCB
3836fa
8
LTC3836
FUNCTIONAL DIAGRAM (Controller 2)
BOOST2
V
IN
+
SENSE2
TG2
C
CB
IN
RS2
CLK2
S
R
Q
SWITCHING
LOGIC
PGND
SW2
BG2
ANTISHOOT
THROUGH
L2
AND
OV2
SC2
FCB
BLANKING
CIRCUIT
V
OUT2
BOOST2
C
OUT2
PGND
IREV2
SLOPE2
SW2
–
ICMP
+
+
IPRG2
SENSE2
SHDN
–
+
R2B
R2A
V
FB2
+
–
0.60V
EAMP
V
OUT1
R
1μA
TRACK/SS2
TRACKB
TRACKA
R
SHDN
I
TH2
R
ITH2
0.12V
+
C
ITH2
SC2
SCP
V
–
FB2
TRACK
V
PGND
SW2
+
–
+
FB2
OV2
OVP
IREV2
–
0.68V
3836 FD3
FCB
3836fa
9
LTC3836
OPERATION (Refer to Functional Diagram)
Main Control Loop
source), the EAMP regulates the V
from 0V to 0.6V.
proportionally
FB1
The LTC3836 uses a constant-frequency, current mode
architecturewiththetwocontrollersoperating180degrees
out-of-phase. During normal operation, the top external
power MOSFET is turned on when the clock for its chan-
nel sets the RS latch, and turned off when the current
The start-up of V
is controlled by the voltage on the
OUT2
TRACK/SS2 pin. When the voltage on the TRACK/SS2
pin is less than the 0.6V internal reference, the LTC3836
regulates the V voltage to the TRACK/SS2 pin voltage
FB2
comparator (I
) resets the latch. The peak inductor
CMP
instead of the 0.6V reference. This allows the TRACK/SS2
pin to be used to program a soft-start by connecting an
external capacitor from the TRACK/SS2 pin to SGND.
An internal 1μA pull-up current charges this capacitor,
creating a voltage ramp on the TRACK/SS2 pin. As the
TRACK/SS2 voltage rises linearly from 0V to 0.6V (and
CMP
current at which I
resets the RS latch is determined
by the voltage on the I pin, which is driven by the output
of the error amplifier (EAMP). The V pin receives the
TH
FB
output voltage feedback signal from an external resistor
divider. This feedback signal is compared to the internal
0.6VreferencevoltagebytheEAMP.Whentheloadcurrent
beyond), the output voltage V
zero to its final value.
rises smoothly from
OUT2
increases, it causes a slight decrease in V relative to the
FB
0.6V reference, which in turn causes the I voltage to
TH
Alternatively, the TRACK/SS2 pin can be used to cause the
start-up of V to “track” that of another supply. Typi-
increase until the average inductor current matches the
new load current. While the top N-channel MOSFET is off,
the bottom N-channel MOSFET is turned on until either
the inductor current starts to reverse, as indicated by the
OUT2
cally, this requires connecting to the TRACK/SS2 pin an
external resistor divider from the other supply to ground
(see Applications Information section).
current reversal comparator, I , or the beginning of
RCMP
the next cycle.
When the RUN/SS pin is pulled low to disable the
LTC3836, or when V drops below its undervoltage
IN
Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK/SS2 Pins)
lockout threshold, the TRACK/SS2 pin is pulled low by
an internal MOSFET. When in undervoltage lockout, both
controllers are disabled and the external MOSFETs are
held off.
The LTC3836 is shut down by pulling the RUN/SS pin
low. In shutdown, all controller functions are disabled and
the chip draws only 6.5μA. The TG and BG outputs are
held low (off) in shutdown. Releasing RUN/SS allows an
internal 0.65μA current source to charge up the RUN/SS
pin. When the RUN/SS pin reaches 0.65V, the LTC3836’s
two controllers are enabled.
Light Load Operation (Pulse-Skipping or Continuous
Conduction) (SYNC/FCB Pin)
TheLTC3836canbeenabledtoenterhighefficiencypulse-
skippingoperationorforcedcontinuousconductionmode
atlowloadcurrents.Toselectpulse-skippingoperation,tie
The start-up of V
is controlled by the LTC3836’s
the SYNC/FCB pin to a DC voltage above 0.6V (e.g., V ).
OUT1
IN
internal soft-start. During soft-start, the error amplifier
To select forced continuous operation, tie the SYNC/FCB
EAMP compares the feedback signal V to the internal
to a DC voltage below 0.6V (e.g., SGND).
FB1
soft-startramp(insteadofthe0.6Vreference),whichrises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the I pin. The main N-channel MOSFET
TH
The 1ms soft-start time can be increased by con-
is turned on every cycle (constant-frequency) regardless
of the I pin voltage. In this mode, the efficiency at light
necting the optional external soft-start capacitor C
TH
SS
loads is lower than in pulse-skipping operation. However,
continuousmodehastheadvantagesofloweroutputripple
and less interference with audio circuitry.
3836fa
between the RUN/SS and SGND pins. As the RUN/SS
pin continues to rise linearly from approximately 0.65V
to 1.3V (being charged by the internal 0.65μA current
10
LTC3836
OPERATION (Refer to Functional Diagram)
When the SYNC/FCB pin is tied to a DC voltage above
0.6V or when it is clocked by an external clock source
to use the phase-locked loop (see Frequency Selection
and Phase-Locked Loop), the LTC3836 operates in PWM
pulse-skipping mode at light loads. In this mode, the
Frequency Selection and Phase-Locked Loop (PLLLPF
and SYNC/FCB Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
current comparator I
may remain tripped for several
CMP
cycles and force the main N-channel MOSFET to stay off
for the same number of cycles. The inductor current is
not allowed to reverse, though (discontinuous operation).
This mode, like forced continuous operation, exhibits low
output ripple as well as low audio noise and reduced RF
interference. However, it provides low current efficiency
higher than forced continuous mode. During start-up or
The switching frequency of the LTC3836’s controllers can
be selected using the PLLLPF pin.
If the SYNC/FCB is not being driven by an external clock
source, the PLLLPF can be floated, tied to V or tied to
IN
SGND to select 550kHz, 750kHz or 300kHz respectively.
a short-circuit condition (V
or V
≤ 0.54V), the
FB1
FB2
A phase-locked loop (PLL) is available on the LTC3836
to synchronize the internal oscillator to an external clock
sourcethatisconnectedtotheSYNC/FCBpin. Inthiscase,
a series RC should be connected between the PLLLPF pin
and SGND to serve as the PLL’s loop filter. The LTC3836
phase detector adjusts the voltage on the PLLLPF pin to
align the turn-on of controller 1’s top MOSFET to the ris-
ing edge of the synchronizing signal. Thus, the turn-on
of controller 2’s top MOSFET is 180 degrees out-of-phase
with the rising edge of the external clock source.
LTC3836 operates in pulse-skipping mode (no cur-
rent reversal allowed), regardless of the state of the
SYNC/FCB pin.
Short-Circuit Protection
When an output is shorted to ground (V < 0.12V), the
FB
switching frequency of that controller is reduced to one-
fifthofthenormaloperatingfrequency.Theothercontroller
maintains regulation in pulse-skipping mode.
Theshort-circuitthresholdonV isbasedonthesmaller
FB2
The typical capture range of the LTC3836’s phase-locked
loop is from approximately 200kHz to 1MHz, and is guar-
anteed over temperature between 250kHz and 850kHz.
In other words, the LTC3836’s PLL is guaranteed to lock
to an external clock source whose frequency is between
250kHz and 850kHz.
of 0.12V and a fraction of the voltage on the TRACK/SS2
pin. This also allows V
to start up and track V
OUT1
OUT2
OUT1
more easily. Note that if V
is truly short-circuited
(V
= V = 0V), then the LTC3836 will try to regulate
OUT1
FB1
V
to 0V if a resistor divider on V
is connected to
OUT2
OUT1
the TRACK/SS pin.
Dropout Operation
Output Overvoltage Protection
Each top MOSFET driver is biased from the floating boot-
As a further protection, the overvoltage comparator (OV)
guardsagainsttransientovershoots,aswellasothermore
seriousconditionsthatmayovervoltagetheoutput. When
strap capacitor C , which normally recharges during each
B
off cycle through an external diode when the top MOSFET
turns off. If the input voltage V decreases to a voltage
thefeedbackvoltageontheV pinhasrisen13.33%above
IN
FB
close to V , the loop may enter dropout and attempt to
thereferencevoltageof0.6V, themainN-channelMOSFET
is turned off and the synchronous N-channel MOSFET is
turned on until the overvoltage is cleared.
OUT
turn on the top MOSFET continuously. The dropout detec-
tor detects this and forces the top MOSFET off for about
200ns every fourth cycle to allow C to recharge.
B
3836fa
11
LTC3836
OPERATION (Refer to Functional Diagram)
Undervoltage Lockout
110
100
90
80
70
60
50
40
30
20
10
0
To prevent operation of the external MOSFETs below safe
input voltage levels, an undervoltage lockout is incorpo-
rated in the LTC3836. When the input supply voltage (V )
drops below 2.25V, the external MOSFETs and all internal
circuitry are turned off except for the undervoltage block,
which draws only a few microamperes.
IN
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG1 and IPRG2 Pins)
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
When a controller is operating below 20% duty cycle,
37362 F01
+
the peak current sense voltage (between the SENSE and
SW pins) allowed across the main N-channel MOSFET is
determined by:
Figure 1. Maximum Peak Current vs Duty Cycle
A V – 0.7V
(
=
)
ITH
Power-Good (PGOOD) Pin
ꢀVSENSE(MAX)
10
A window comparator monitors both feedback voltages
and the open-drain PGOOD output pin is pulled low when
eitherorbothfeedbackvoltagesarenotwithin 10%ofthe
0.6V reference voltage. PGOOD is low when the LTC3836
is shut down or in undervoltage lockout.
where A is a constant determined by the state of the
IPRG pins. Floating the IPRG pin selects A = 1;
tying IPRG to V selects A = 5/3; tying IPRG to SGND
IN
selects A = 2/3. The maximum value of V is typically
ITH
about1.98V,sothemaximumsensevoltageallowedacross
the main N-channel MOSFET is 122mV, 202mV, or 82mV
for the three respective states of the IPRG pin. The peak
sensevoltagesforthetwocontrollerscanbeindependently
selected by the IPRG1 and IPRG2 pins.
2-Phase Operation
Why the need for 2-phase operation? Many constant-fre-
quencydualswitchingregulatorsoperatebothcontrollers
in phase (i.e., single phase operation). This means that
both topside MOSFETs are turned on at the same time,
causing current pulses of up to twice the amplitude of
those from a single regulator to be drawn from the input
capacitor. These large amplitude pulses increase the total
RMS current flowing in the input capacitor, requiring the
use of larger and more expensive input capacitors, and
increase both EMI and power losses in the input capacitor
and input power supply.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor given by the curve
in Figure 1.
The peak inductor current is determined by the peak
sense voltage and the on-resistance of the main N-chan-
nel MOSFET:
With2-phaseoperation,thetwocontrollersoftheLTC3836
are operated 180 degrees out-of-phase. This effectively
interleaves the current pulses coming from the topside
MOSFET switches, greatly reducing the time where they
overlap and add together. The result is a significant reduc-
tion in the total RMS current, which in turn allows the
use of smaller, less expensive input capacitors, reduces
shielding requirements for EMI and improves real world
ꢀVSENSE(MAX)
IPK
=
RDS(ON)
operating efficiency.
3836fa
12
LTC3836
OPERATION (Refer to Functional Diagram)
Figure2showsexamplewaveformsforasinglephasedual
controller versus a 2-phase LTC3836 system. In this case,
two outputs of different voltage, each drawing the same
load current are derived from a single input supply. In this
example, 2-phase operation could halve the RMS input
capacitor current. While this is an impressive reduction
Thereducedinputripplecurrentalsomeansthatlesspower
is lost in the input power path, which could include batter-
ies, switches, trace/connector resistances, and protection
circuitry.ImprovementsinbothconductedandradiatedEMI
also directly accrue as a result of the reduced RMS input
current and voltage. Significant cost and board footprint
savings are also realized by being able to use smaller, less
expensive, lower RMS current-rated input capacitors.
by itself, remember that power losses are proportional
2
to I
, meaning that just one-fourth the actual power
RMS
is wasted.
Ofcourse,theimprovementaffordedby2-phaseoperation
is a function of the relative duty cycles of the two control-
lers, which in turn are dependent upon the input supply
voltage. Figure3depictshowtheRMSinputcurrentvaries
forsinglephaseand2-phasedualcontrollerswith2.5Vand
1.8V outputs. A good rule of thumb for most applications
is that 2-phase operation will reduce the input capacitor
requirement to that for just one channel operating at
maximum current and 50% duty cycle.
Single Phase
Dual Controller
2-Phase
Dual Controller
SW1 (V)
SW2 (V)
2.0
SINGLE PHASE
DUAL CONTROLLER
1.6
1.8
I
I
L1
L2
1.4
1.2
1.0
0.8
2-PHASE
DUAL CONTROLLER
0.6
0.4
V
V
= 2.5V/2A
= 1.8V/2A
OUT1
OUT2
0.2
0
I
IN
3.0
3.5
4.0
4.5
INPUT VOLTAGE (V)
3836 F02
3836 F03
Figure 2. Example Waveforms for a Single Phase
Dual Controller vs the 2-Phase LTC3836
Figure 3. RMS Input Current Comparison
3836fa
13
LTC3836
APPLICATIONS INFORMATION
The typical LTC3836 application circuit is shown in
Figure 13. External component selection for each of the
LTC3836’s controllers is driven by the load requirement
and begins with the selection of the inductor (L) and the
power MOSFETs (M1 to M4).
A reasonable starting point is setting ripple current I
RIPPLE
to be 40% of I
yields:
. Rearranging the above equation
OUT(MAX)
ꢀVSENSE(MAX)
5
RDS(ON)(MAX) = •
6
IOUT(MAX)
Power MOSFET Selection
for Duty Cycle < 20%.
Each of the LTC3836’s two controllers requires two ex-
ternal N-channel power MOSFETs for the topside (main)
switch and the bottom (synchronous) switch. Important
parameters for the power MOSFETs are the breakdown
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of R
amount of load current:
to provide the required
DS(ON)
voltageV
,thresholdvoltageV
,on-resistance
BR(DSS)
GS(TH)
ꢀVSENSE(MAX)
5
6
R
t
, reverse transfer capacitance C , turn-off delay
and the total gate charge Q .
DS(ON)
RSS
R
DS(ON)(MAX) = •SF •
IOUT(MAX)
D(OFF)
G
The gate drive voltage is the input supply voltage. Since
the LTC3836 is designed for operation down to low input
where SF is a scale factor whose value is obtained from
the curve in Figure 1.
voltages, a sublogic level MOSFET (R
guaranteed
DS(ON)
These must be further derated to take into account the
significant variation in on-resistance with temperature.
Thefollowingequationisagoodguidefordeterminingthe
at V = 2.5V) is required for applications that work close
GS
to this voltage.
The main MOSFET’s on-resistance is chosen based on the
required load current. The maximum average output load
required R
at 25°C (manufacturer’s specifica-
DS(ON)MAX
tion), allowing some margin for variations in the LTC3836
current I
is equal to the peak inductor current
OUT(MAX)
and external component values:
minus half the peak-to-peak ripple current I
. The
RIPPLE
ꢀVSENSE(MAX)
5
6
LTC3836’s current comparator monitors the drain-to-
R
DS(ON)(MAX) = •0.9 •SF •
IOUT(MAX) •ꢁT
source voltage V of the main MOSFET, which is sensed
DS
+
between the SENSE and SW pins. The peak inductor cur-
ρ
The isanormalizingtermaccountingforthetemperature
T
rent is limited by the current threshold, set by the voltage
variationinon-resistance,whichistypicallyabout0.4%/°C,
ontheI pinofthecurrentcomparator.Thevoltageonthe
TH
as shown in Figure 4. Junction to case temperature T is
JC
I
pin is internally clamped, which limits the maximum
current sense threshold ΔV
TH
about 10°C in most applications. For a maximum ambi-
to approximately
SENSE(MAX)
ρ
ent temperature of 70°C, using
equation is a reasonable choice.
≈ 1.3 in the above
80°C
122mV when IPRG is floating (82mV when IPRG is tied
low; 202mV when IPRG is tied high).
The power dissipated in the top and bottom MOSFETs
strongly depends on their respective duty cycles and load
current. When the LTC3836 is operating in continuous
mode, the duty cycles for the MOSFETs are:
The output current that the LTC3836 can provide is
given by:
ꢀVSENSE(MAX)
IRIPPLE
IOUT(MAX)
=
–
RDS(ON)
2
VOUT
TopMOSFET Duty Cycle=
V
IN
V – VOUT
IN
Bottom MOSFET Duty Cycle=
V
IN
3836fa
14
LTC3836
APPLICATIONS INFORMATION
The MOSFET power dissipations at maximum output
current are:
Operating Frequency and Synchronization
The choice of operating frequency, f , is a trade-off
OSC
between efficiency and component size. Low frequency
operation improves efficiency by reducing MOSFET
switching losses, both gate charge loss and transition
loss. However, lower frequency operation requires more
inductance for a given amount of ripple current.
VOUT
2
PTOP
=
=
•IOUT(MAX)2 •ꢀT •RDS(ON) + 2• V
IN
V
IN
• IOUT(MAX) •CRSS • fOSC
V – VOUT
PBOT
•IOUT(MAX)2 •ꢀT •RDS(ON)
IN
V
TheinternaloscillatorforeachoftheLTC3836’scontrollers
runs at a nominal 550kHz frequency when the PLLLPF
pin is left floating and the SYNC/FCB pin is a DC low or
IN
2
Both MOSFETs have I R losses and the P
equation
TOP
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The bottom MOSFET losses
are greatest at high input voltage or during a short-circuit
when the bottom duty cycle is nearly 100%.
high. Pulling the PLLLPF to V selects 750kHz operation;
IN
pulling the PLLLPF to GND selects 300kHz operation.
Alternatively, the LTC3836 will phase-lock to a clock signal
applied to the SYNC/FCB pin with a frequency between
250kHz and 850kHz (see Phase-Locked Loop and Fre-
quency Synchronization).
2.0
1.5
1.0
0.5
0
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency f
directly determine the
OSC
inductor’s peak-to-peak ripple current:
ꢀ
OUT ꢃ
fOSC •L
ꢄ
VOUT V – V
IN
IRIPPLE
=
ꢂ
ꢅ
V
ꢁ
IN
50
100
–50
150
0
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
JUNCTION TEMPERATURE (°C)
3836 F04
Figure 4. RDS(ON) vs Temperature
TheLTC3836utilizesanonoverlapping,antishoot-through
gate drive control scheme to ensure that the MOSFETs
are not turned on at the same time. To function properly,
the control scheme requires that the MOSFETs used are
intended for DC/DC switching applications. Many power
MOSFETs are intended to be used as static switches and
therefore are slow to turn on or off.
A reasonable starting point is to choose a ripple current
that is about 40% of I . Note that the largest ripple
OUT(MAX)
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
VIN – VOUT VOUT
fOSC •IRIPPLE VIN
L ꢀ
•
3836fa
15
LTC3836
APPLICATIONS INFORMATION
Inductor Core Selection
phasetechniquetypicallyreducestheinputcapacitor’sRMS
ripple current by a factor of 30% to 70% when compared
to a single phase power supply solution.
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Incontinuousmode,thesourcecurrentofthemainN-chan-
nelMOSFETisasquarewaveofdutycycle(V )/(V ).To
OUT
IN
preventlargevoltagetransients, alowESRcapacitorsized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
ꢃ1/2
IMAX
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
ꢁ
CIN Required IRMS ꢀ
V
V – V
IN OUT
(
OUT )(
)
ꢂ
ꢄ
V
IN
This formula has a maximum at V = 2V , where I
RMS
= I /2. This simple worst-case condition is commonly
IN
OUT
OUT
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3836, ceramic capacitors
Schottky Diode Selection (Optional)
The Schottky diodes D1 and D2 in Figure 16 conduct
current during the dead time between the conduction of
the power MOSFETs . This prevents the body diode of
the bottom MOSFET from turning on and storing charge
during the dead time, which could cost as much as 1% in
efficiency. A 1A Schottky diode is generally a good size for
most LTC3836 applications, since it conducts a relatively
small average current. Larger diodes result in additional
transition losses due to their larger junction capacitance.
This diode may be omitted if the efficiency loss can be
tolerated.
can also be used for C . Always consult the manufacturer
IN
if there is any question.
The benefit of the LTC3836 2-phase operation can be cal-
culated by using the equation above for the higher power
controller and then calculating the loss that would have
resultedifbothcontrollerchannelsswitchedonatthesame
time. The total RMS power lost is lower when both control-
lers are operating due to the reduced overlap of current
pulses required through the input capacitor’s ESR. This is
why the input capacitor’s requirement calculated above for
theworst-casecontrollerisadequateforthedualcontroller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benefit of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The drains of the main MOSFETs should be placed within
C and C
Selection
IN
OUT
The selection of C is simplified by the 2-phase architec-
IN
ture and its impact on the worst-case RMS current drawn
throughtheinputnetwork(battery/fuse/capacitor).Itcanbe
shown that the worst-case capacitor RMS current occurs
when only one controller is operating. The controller with
the highest (V )(I ) product needs to be used in the
OUT OUT
formula below to determine the maximum RMS capacitor
current requirement. Increasing the output current drawn
from the other controller will actually decrease the input
RMS ripple current from its maximum value. The out-of-
1cm of each other and share a common C (s). Separating
IN
the drains and C may produce undesirable voltage and
IN
current resonances at V .
IN
3836fa
16
LTC3836
APPLICATIONS INFORMATION
A small (0.1μF to 1μF) bypass capacitor between the chip
To improve the frequency response, a feedforward ca-
V pin and ground, placed close to the LTC3836, is also
pacitor, C , may be used. Great care should be taken to
IN
FF
suggested. A 10Ω resistor placed between C (C1) and
route the V line away from noise sources, such as the
IN
FB
the V pin provides further isolation between the two
inductor or the SW line.
IN
channels.
Run/Soft-Start Function
The selection of C
is driven by the effective series
OUT
The RUN/SS pin is a dual purpose pin that provides the
optional external soft-start function and a means to shut
down the LTC3836.
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔV ) is approximated by:
OUT
PullingtheRUN/SSpinbelow0.65VputstheLTC3836into
ꢂ
ꢅ
ꢇ
1
ꢀVOUT ꢁIRIPPLE ESR+
a low quiescent current shutdown mode (I = 6.5μA). If
ꢄ
Q
8fC
ꢃ
OUT ꢆ
RUN/SS has been pulled all the way to ground, there will
be a delay before the LTC3836 comes out of shutdown
and is given by:
where f is the operating frequency, C
is the output
OUT
capacitance and I
is the ripple current in the induc-
RIPPLE
tor. The output ripple is highest at maximum input voltage
since I increases with input voltage.
CSS
0.65μA
t
DELAY = 0.65V •
=1s/μF •CSS
RIPPLE
Setting Output Voltage
This pin can be driven directly from logic as shown in
The LTC3836 output voltages are each set by an external
feedback resistor divider carefully placed across the out-
put, as shown in Figure 5. The regulated output voltage
is determined by:
Figure 6. Diode D in Figure 6 reduces the start delay
SS
but allows C to ramp up slowly providing the soft-start
SS
function. This diode (and capacitor) can be deleted if the
external soft-start is not needed.
ꢀ
ꢂ
ꢁ
B ꢃ
A ꢄ
R
R
3.3V OR 5V
RUN/SS
RUN/SS
V
OUT = 0.6V • 1+
ꢅ
D
SS
C
SS
V
OUT
C
SS
R
C
FF
B
A
1/2 LTC3836
V
≤ V
RUN/SS
(INTERNAL SOFT-START)
DD
IN
V
FB
R
3836 F05
3836 F06
Figure 6. RUN/SS Pin Interfacing
Figure 5. Setting Output Voltage
3836fa
17
LTC3836
APPLICATIONS INFORMATION
During soft-start, the start-up of V
is controlled by
regulates the V voltage to the TRACK/SS2 pin voltage
FB2
OUT1
slowlyrampingthepositivereferencetotheerroramplifier
from 0V to 0.6V, allowing V to rise smoothly from 0V
instead of 0.6V. The start-up of V
may ratiometrically
OUT2
track that of V
, according to a ratio set by a resistor
OUT1
OUT1
toitsfinalvalue. Thedefaultinternalsoft-starttimeis1ms.
This can be increased by placing a capacitor between the
RUN/SS pin and SGND. In this case, the soft-start time
will be approximately:
divider (Figure 7c):
VOUT1
VOUT2 RTRACKA
R
TRACKA +RTRACKB
R2B+R2A
R2A
=
•
600mV
0.65μA
t
SS1 =CSS •
For coincident tracking (V
= V
during start-up),
OUT2
OUT1
R2A = R
R2B = R
TRACKA
TRACKB
Tracking
The start-up of V
is controlled by the voltage on the
OUT2
The ramp time for V
value is:
to rise from 0V to its final
TRACK/SS2pin.Normallythispinisusedtoallowthestart-
up of V to track that of V as shown qualitatively
OUT2
OUT2
OUT1
in Figures 7a and 7b. When the voltage on the TRACK/SS2
pin is less than the internal 0.6V reference, the LTC3836
R
TRACKA +RTRACKB
0.6
t
SS2 = tSS1
•
•
VOUT1F
RTRACKA
V
OUT1
V
OUT2
LTC3836
R1B
R2B
V
V
FB2
FB1
R1A
R2A
R
R
TRACKB
TRACKA
TRACK/SS2
3836 F07a
Figure 7a. Using the TRACK/SS Pin
V
V
V
V
OUT1
OUT2
OUT1
OUT2
3836 F07b_c
TIME
TIME
(7b) Coincident Tracking
(7c) Ratiometric Tracking
Figures 7b and 7c. Two Different Modes of Output Voltage Tracking
3836fa
18
LTC3836
APPLICATIONS INFORMATION
For coincident tracking,
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
VOUT2F
VOUT1F
t
SS2 = tSS1 •
Theoutputofthephasedetectorisapairofcomplementary
current sources that charge or discharge the external filter
network connected to the PLLLPF pin. The relationship
between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
FCB, is shown in Figure 8 and specified in the Electrical
Characteristics table. Note that the LTC3836 can only be
synchronizedtoanexternalclockwhosefrequencyiswithin
range of the LTC3836’s internal VCO, which is nominally
200kHz to 1MHz. This is guaranteed, over temperature
and variations, to be between 300kHz and 750kHz. A
simplified block diagram is shown in Figure 9.
where V
and V
OUT2 OUT1
are the final, regulated values
should always be greater than
OUT1F
and V
OUT2F
. V
of V
OUT1
V
when using the TRACK/SS2 pin for tracking. If no
OUT2
tracking function is desired, then the TRACK/SS2 pin may
be tied to a capacitor to ground, which sets the ramp time
to final regulated output voltage.
Phase-Locked Loop and Frequency Synchronization
The LTC3836 has a phase-locked loop (PLL) comprised of
aninternalvoltage-controlledoscillator(VCO)andaphase
detector. This allows the turn-on of the main N-channel
MOSFET of controller 1 to be locked to the rising edge
of an external clock signal applied to the SYNC/FCB pin.
The turn-on of controller 2’s main N-channel MOSFET is
thus 180 degrees out-of-phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
If the external clock frequency is greater than the internal
oscillator’s frequency, f , then current is sourced con-
OSC
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f , current is sunk continuously, pulling down
OSC
the PLLLPF pin. If the external and internal frequencies
1400
1200
1000
800
600
400
200
0
2.4V
R
LP
C
LP
PLLLPF
SYNC/
FCB
DIGITAL
PHASE/
FREQUENCY
DETECTOR
EXTERNAL
OSCILLATOR
OSCILLATOR
0
0.5
1
1.5
2
2.4
PLLLPF PIN VOLTAGE (V)
3836 F09
3836 F08
Figure 8. Relationship Between Oscillator Frequency
and Voltage at the PLLLPF Pin When Synchronizing to
an External Clock
Figure 9. Phase-Locked Loop Block Diagram
3836fa
19
LTC3836
APPLICATIONS INFORMATION
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
5V supply is available. Note that in applications where the
supply voltage to C exceeds V , the BOOST pin will draw
B
IN
approximately 500μA in shutdown mode.
Table 2 summarizes the different states in which the
SYNC/FCB pin can be used
the filter capacitor C holds the voltage.
Table 2.
LP
SYNC/FCB PIN
CONDITION
The loop filter components, C and R , smooth out the
LP
LP
0V to 0.5V
Forced Continuous Mode
Current Reversal Allowed
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components C and R determine how fast the loop
0.7V to V
Pulse-Skipping Operation Enabled
No Current Reversal Allowed
IN
LP
LP
acquires lock. Typically R = 10k and C is 2200pF to
LP
LP
External Clock Signal
Enable Phase-Locked Loop
(Synchronize to External CLK)
Pulse-Skipping at Light Loads
No Current Reversal Allowed
0.01μF.
Typically, the external clock (on SYNC/FCB pin) input high
level is 1.6V, while the input low level is 1.2V.
Fault Condition: Short-Circuit and Current Limit
Table 1 summarizes the different states in which the
PLLLPF pin can be used.
To prevent excessive heating of the bottom MOSFET,
foldback current limiting can be added to reduce the cur-
rent in proportion to the severity of the fault.
Table 1.
PLLLPF PIN
0V
SYNC/FCB PIN
DC Voltage
DC Voltage
DC Voltage
Clock Signal
FREQUENCY
Foldback current limiting is implemented by adding
300kHz
550kHz
diodes D
and D
between the output and the I
FB1
FB2
TH
= 0V),
Floating
pin as shown in Figure 11. In a hard short (V
OUT
V
750kHz
IN
the current will be reduced to approximately 50% of the
maximum output current.
RC Loop Filter
Phase-Locked to External Clock
Topside MOSFET Drive Supply (C , D )
B
B
V
OUT
1/2 LTC3836
R2
R1
D
D
+
FB1
In the Functional Diagram, external bootstrap capaci-
tor C is charged from a boost power source (usually
I
V
FB
TH
B
FB2
V ) through diode D when the SW node is low. When
IN
B
a MOSFET is to be turned on, the C voltage is applied
B
3836 F11
across the gate-source of the desired device. When the
topside MOSFET is on, the BOOST pin voltage is above
Figure 11. Foldback Current Limiting
the input supply. V
= 2V . C must be 100 times the
IN B
BOOST
totalinputcapacitanceofthetopsideMOSFET.Thereverse
breakdown of D must be greater than V
. Figure 6
B
IN(MAX)
shows how a 5V gate drive can be achieved if a secondary
3836fa
20
LTC3836
APPLICATIONS INFORMATION
Using a Sense Resistor
V decreases below 3V. Figure 12 shows the amount of
IN
change as the supply is reduced down to 2.4V. Also
A sense resistor R
can be connected between V
IN
SENSE
shown is the effect on V
.
REF
and SW to sense the output load current. In this case, the
drain of the topside N-channel MOSFET is connected to
Minimum On-Time Considerations
Minimumon-time,t ,isthesmallestamountoftime
–
SENSE pin and the source is connected to the SW pin of
the LTC3836. Therefore, the current comparator monitors
ON(MIN)
that the LTC3836 is capable of turning the main N-chan-
nel MOSFET on and then off. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. Low duty cycle and high frequency applica-
tions may approach the minimum on-time limit and care
should be taken to ensure that:
the voltage developed across R
, not the V of the
SENSE
DS
top MOSFET. The output current that the LTC3836 can
provide in this case is given by:
ꢀVSENSE(MAX)
IRIPPLE
IOUT(MAX)
=
–
RDS(ON)
2
Setting ripple current as 40% of I
Figure 1 to choose SF, the value of R
and using
VOUT
fOSC • VIN
OUT(MAX)
tON(MIN)
<
is:
SENSE
ꢀVSENSE(MAX)
5
6
R
SENSE = •SF •
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3836 will begin to skip
cycles (unless forced continuous mode is selected). The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase. The minimum on-
time for the LTC3836 is typically about 200ns. However,
IOUT(MAX)
Variation in the resistance of a sense resistor is much
smaller than the variation in on-resistance of an external
MOSFET. Therefore the load current is well controlled with
a sense resistor. However the sense resistor causes extra
2
I R losses in addition to those of the MOSFET. Therefore,
as the peak sense voltage (I
• R
) decreases,
L(PEAK)
DS(ON)
using a sense resistor lowers the efficiency of LTC3836,
especially at high load currents.
the minimum on-time gradually increases up to about
250ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If forced
continuousmodeisselectedandthedutycyclefallsbelow
the minimum on-time requirement, the output will be
regulated by overvoltage protection.
Low Supply Operation
Although the LTC3836 can function down to below 2.4V,
the maximum allowable output current is reduced as
105
V
REF
100
95
90
MAXIMUM
SENSE VOLTAGE
85
80
75
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
3836 F12
Figure 12. Line Regulation of VREF and
Maximum Sense Voltage for Low Input Supply
3836fa
21
LTC3836
APPLICATIONS INFORMATION
Efficiency Considerations
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
a load step occurs, V
immediately shifts by an amount
OUT
equal to (ΔI
)(ESR), where ESR is the effective series
LOAD
resistance of C . ΔI
also begins to charge or dis-
OUT
LOAD
Efficiency = 100% – (L1 + L2 + L3 + …)
charge C , which generates a feedback error signal. The
OUT
where L1, L2, etc. are the individual losses as a percent-
age of input power.
regulator loop then returns V
to its steady-state value.
can be monitored for
OUT
During this recovery time, V
OUT
overshoot or ringing. OPTI-LOOP® compensation allows
the transient response to be optimized over a wide range
of output capacitance and ESR values.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of
the losses in LTC3836 circuits: 1) LTC3836 DC bias cur-
2
The I series R -C filter (see Functional Diagram) sets
rent, 2) MOSFET gate charge current, 3) I R losses, and
TH
C
C
thedominantpole-zeroloopcompensation.TheI external
4) transition losses.
TH
components shown in the Typical Application on the front
pageofthisdatasheetwillprovideanadequatestartingpoint
for most applications. The values can be modified slightly
(from 0.2 to 5 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. Theoutputcapacitorsneedtobedecidedupon
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full load current having a rise time of 1μs to
1) The V (pin) current is the DC supply current, given
IN
in the electrical characteristics, excluding MOSFET
driver currents. V current results in a small loss that
IN
increases with V .
IN
2) MOSFETgatechargecurrentresultsfromswitchingthe
gate capacitance of the power MOSFETs. Each time a
MOSFETgateisswitchedfromlowtohightolowagain,
+
a packet of charge dQ moves from SENSE to ground.
+
The resulting dQ/dt is a current out of SENSE , which
10μswillproduceoutputvoltageandI pinwaveformsthat
is typically much larger than the DC supply current. In
TH
will give a sense of the overall loop stability. The gain of the
continuous mode, I
= f • Q .
GATECHG
P
loop will be increased by increasing R , and the bandwidth
C
2
3) I RlossesarecalculatedfromtheDCresistancesofthe
MOSFETsandinductor.Incontinuousmode,theaverage
outputcurrentflowsthroughLbutis“chopped”between
thetopMOSFETand the bottomMOSFET. TheMOSFET
of the loop will be increased by decreasing C . The output
C
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance. For a detailed explanation of optimiz-
ing the compensation components, including a review of
control loop theory, refer to Application Note 76.
R
s multiplied by duty cycle can be summed with
DS(ON)
2
the resistance of L to obtain I R losses.
4) Transitionlossesapplytothetop MOSFETandincrease
with higher operating frequencies and input voltages.
Transition losses can be estimated from:
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C , causing a rapid drop in V . No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
2
Transition Loss = 2 (V ) I
C
(f)
OUT
OUT
IN O(MAX) RSS
Otherlosses,includingC andC ESRdissipativelosses
IN
OUT
and inductor core losses, generally account for less than
2% total additional loss.
the load rise time is limited to approximately (25)(C
).
LOAD
Thus a 10μF capacitor would require a 250μs rise time,
OPTI-LOOP is a trademark of Linear Technology Corporation.
limiting the charging current to about 200mA.
3836fa
22
LTC3836
APPLICATIONS INFORMATION
PC Board Layout Checklist
scribed above in item 1). The power grounds for the
two channels should connect together at a common
point. It is most important to keep the ground paths
with high switching currents away from each other.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3836.Theseitemsareillustratedinthelayoutdiagramof
Figure13.Figure14depictsthecurrentwaveformspresent
in the various branches of the 2-phase dual regulator.
The PGND pins on the LTC3836 should be shorted
together and connected to the common power ground
connection (away from the switching currents).
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small
as possible and isolated as much as possible from the
power loop of the other channel. Ideally, the main and
synchronous FETs should be connected close to one
another with an input capacitor placed right at the FETs.
It is better to have two separate, smaller valued input
capacitors(e.g.,two10μF—oneforeachchannel)than
it is to have a single larger valued capacitor (e.g., 22μF)
that the channels share with a common connection.
3) Put the feedback resistors close to the V pins. The
FB
trace connecting the top feedback resistor (R ) to
B
the output capacitor should be a Kelvin trace. The I
TH
compensation components should also be very close
to the LTC3836.
+
4) The current sense traces (SENSE and SW) should be
KelvinconnectionsrightatthemainN-channelMOSFET
drains and sources.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-
signal components, especially the opposite channel’s
2) Thesignalandpowergroundsshouldbekeptseparate.
Thesignalgroundconsistsofthefeedbackresistordivid-
ers, I compensation networks and the SGND pin.
feedbackresistors,I compensationcomponents,and
TH
TH
+
the current sense pins (SENSE and SW).
The power grounds consist of the (–) terminal of the
input and output capacitors and the source of the
synchronous N-channel MOSFET. Each channel should
have its own power ground for its power loop (as de-
6) Connecttheboostcapacitorstotheswitchnodes,notto
the small signal nodes SWn. Connect the boost diodes
to the positive terminal of the input capacitor.
+
C
OUT1
V
OUT1
L1
LTC3836EGN
28
27
+
1
2
3
SENSE1
SW1
N/C
C
B1
BOOST1
26
IPRG1
PGND
4
5
D
B1
25
24
23
M1
VIN1
M2
V
FB1
TH1
BG1
SYNC/FCB
TG1
C
I
6
IPRG2
PLLLPF
SGND
C
22
VIN
7
PGND
V
IN
8
21
20
19
TG2
RUN/SS
BG2
9
C
VIN2
M3
D
V
B2
IN
10
11
12
13
M4
TRACK/SS2
C
18
17
16
15
14
B2
N/C
PGND
V
FB2
TH2
I
BOOST2
PGOOD
+
SENSE2
L2
SW2
+
V
OUT2
C
OUT2
3836 F13
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 13. LTC3836 Layout Diagram
3836fa
23
LTC3836
APPLICATIONS INFORMATION
L1
V
OUT1
+
C
R
L1
OUT1
V
IN
R
IN
+
C
IN
L2
V
OUT2
+
C
R
L2
OUT2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH
3836 F14
Figure 14. Branch Current Waveforms
C
, 33pF
, 118k
FFW1
R
FB1B
R
, 12.4k
TRACKB
D
B1
C
B1
, 0.22μF
LTC3836EUFD
FB1 BOOST1
R
, 59k
FB1A
1
7
24
26
25
V
R
, 11.8k
TRACKA
SW1
+
TRACK/SS2
L1
V
OUT1
1.8V
15A
C
, 82pF
M1
ITH1A
SENSE1
C
, 820pF
C
ITH1
R
, 15.8k
ITH1
20
22
23
29
19
14
2
TG1
BG1
C
OUT1
X2
I
TH1
27
4
D1
M2
PLLLPF
IPRG1
R
PLLLPF
PGND
PGND
PGND
PGND
BG2
TG2
PLLLPF
SYNC/FCB
RUN/SS
SGND
21
17
5
C
, 10nF
SS
V
IN
2.75V TO 4.5V
15
18
C
IN
X2
C
M3
OUT2
X2
D2
C
VIN
, 1μF
6
V
IN
R
VIN
, 10Ω
10
3
PGOOD
IPRG2
V
OUT2
L2
12
11
+
C
, 82pF
ITH2A
SENSE2
1.2V
15A
M4
9
I
TH2
SW2
C
, 820pF
C , 0.22μF
B2
ITH2
R
ITH2
, 15.8k
13
BOOST2
R
FB2A
, 59k
8
V
N/C N/C
16 28
D
FB2
B2
R
, 59k
FB2B
3836 F15
L1, L2: VISHAY IHLP2525CZERR 47M01
C
C
: 22μF X2, 6.3V, X5R
IN
, C
OUT1 OUT2
: TAIYO YUDEN JMK235BJ107MM X2
M1-M4: VISHAY Si7882DP
Figure 15. 2-Phase, 550kHz, Dual Output Synchronous DC/DC Converter
with Ceramic Output Capacitors
3836fa
24
LTC3836
APPLICATIONS INFORMATION
C
, 82pF
FFW1
R
, 88.7k, 1%
FB1B
D
LTC3836EUFD
BOOST1
C , 0.22μF
B1
B1
R
C
, 59k, 1%
FB1A
1
7
24
26
25
V
FB1
C
, 10nF
SS2
SW1
L1
V
OUT1
TRACK/SS2
+
SENSE1
, 47pF
1.5V
5A
ITH1A
M1
C
, 470pF
ITH1
R
, 64.9k
ITH1
20
22
23
29
19
14
2
+
I
TG1
BG1
TH1
D1
C
OUT1
27
4
21
IPRG1
PLLLPF
SYNC/FCB
PGND
PGND
PGND
PGND
BG2
TG2
C
, 10nF
SS
V
IN
3.3V
17
5
RUN/SS
SGND
15
18
M2
C
IN
D2
C
C
, 1μF
6
OUT2
VIN
+
X2
V
IN
R
, 10Ω
VIN
10
3
PGOOD
IPRG2
V
OUT2
1.1V
5A
L2
12
11
+
SENSE2
C
, 47pF
ITH2A
9
I
TH2
SW2
C
, 470pF
C , 0.22μF
B2
ITH2
R
, 64.9k
ITH2
13
BOOST2
R
, 59k, 1%
FB2A
8
D
V
N/C N/C
16 28
B2
FB2
R
FB2B
49.9k, 1%
L1, L2: VISHAY IHLP2525CZERR 47M01
3836 F16
C
C
: 22μF X2, 6.3V, X5R
IN
OUT1 OUT2
C
, 82pF
FFW2
, C
: SANYO POSCAP, 2R5TPE330M
M1, M2: FAIRCHILD FDS6898A
Figure 16a. 2-Phase, 750kHz, Dual Output Synchronous DC/DC Converter
100
90
80
70
60
50
40
30
20
10
0
CHANNEL 1
1.5V
V
OUT
200mV/DIV
AC COUPLED
I
L1
5A/DIV
CHANNEL 2
1.1V
I
L2
5A/DIV
I
LOAD
5A/DIV
3836 F17c
40μs/DIV
V
V
LOAD
= 3.3V
OUT
IN
= 1.25V
I
= 10A TO 15A
10
100
1000
10000
LOAD CURRENT (mA)
3836 F16b
Figure 16b. Efficiency vs Load Current
Figure 16c. Load Step
3836fa
25
LTC3836
TYPICAL APPLICATIONS
C
, 120pF
FFW1
R
, 66.5k
FB1B
R
, 68.1k
TRACKB
D
LTC3836EUFD
BOOST1
C
, 0.22μF
B1
B1
R
, 61.9k
FB1A
1
7
24
26
25
V
FB1
R
, 61.9k
TRACKA
SW1
TRACK/SS2
L1
C
ITH1A
, 100pF
M1
+
SENSE1
C
, 2700pF
C
ITH1
R
, 1.37k
ITH1
20
22
23
29
19
14
2
TG1
BG1
I
D1
B320A
TH1
27
4
M2
, 0.015μF
PLLLPF
IPRG1
R
, 15k
PLLLPF
PGND
PGND
PGND
PGND
BG2
TG2
C
PLLLPF
SYNC/FCB
RUN/SS
SGND
OUT
V
OUT
500kHz
21
17
5
1.25V
20A
C
, 10nF
SS
15
18
D2
M3
C
, 10μF
VIN
6
V
IN
B320A
V
IN
2.75V TO
R
, 10Ω
VIN
10
3
4.2V
PGOOD
IPRG2
L2
C
12
11
IN
+
C
, 100pF
ITH2A
SENSE2
3836 F17
X3
M4
9
I
TH2
SW2
C
, 0.22μF
B2
13
8
BOOST2
V
FB2
D
N/C N/C
16 28
B2
L1, L2: TOKO 0.47μF FDV0630-R47M=P3
C
C
: 22μF X3, 6.3V, X5R
IN
: AVX CORECAP 560μF, 2.5V
OUT
NPV V567M002 R003
M1, M2, M3, M4: SILICONIX Si7882DP
Figure 17a. Single Output, High Current Application with External Frequency Synchronization
100
V
OUT
V
= 2.7V
IN
200mV/DIV
90
80
70
60
50
40
30
20
AC COUPLED
I
L1
5A/DIV
I
L2
V
IN
= 3.6V
5A/DIV
V
= 4.2V
IN
I
LOAD
5A/DIV
3836 F17c
40μs/DIV
V
V
LOAD
= 3.3V
OUT
IN
= 1.25V
I
= 10A TO 15A
10
100
1000
10000
100000
LOAD CURRENT (mA)
3836 F17b
Figure 17b. Efficiency vs Load Current
Figure 17c. Load Step
3836fa
26
LTC3836
PACKAGE DESCRIPTION
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.386 – .393*
(9.804 – 9.982)
.045 ±.005
.033
(0.838)
REF
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
1
2
3
4
5
6
7
8
9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
(0.38 ± 0.10)
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
× 45°
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN28 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712)
2.65 ± 0.10
(2 SIDES)
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
R = 0.05
TYP
R = 0.115
TYP
0.75 ± 0.05
4.00 ± 0.10
(2 SIDES)
27
28
0.40
± 0.10
0.70 ±0.05
PIN 1
TOP MARK
(NOTE 6)
1
2
4.50
2.65
± 0.05
± 0.05
(2 SIDES)
5.00
3.65
3.10
± 0.05
± 0.10
± 0.10
(2 SIDES)
(2 SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
3.65 ± 0.05
0.200
REF
0.00
– 0.05
(2 SIDES)
4.10 ± 0.05
5.50 ± 0.05
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE
MO-220 VARIATION (WXXX-X).
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND
BOTTOM OF PACKAGE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
(UFD28) QFN 0405
3836fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3836
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Burst Mode® Operation, 16-Pin Narrow SSOP, 3.5V ≤ V ≤ 36V
LTC1735
High Efficiency Synchronous Step-Down Controller
IN
LTC1778
No R
TM Synchronous Step-Down Controller
Current Mode Operation Without Sense Resistor,
SENSE
Fast Transient Response, 4V ≤ V ≤ 36V
IN
LTC2923
LTC3411
Power Supply Tracking Controller
Controls Up to Three Supplies, 10-Lead MSOP
1.25A (I ), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, V : 2.5V to 5.5V, I = 60μA, I = <1μA,
OUT
IN
Q
SD
MS Package
LTC3412A
LTC3415
LTC3416
3A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.25V to 5.5V, V
SD
= 0.8V, I = 60mA,
OUT Q
OUT
IN
I
= <1mA, TSSOP-16E and 4mm × 4mm QFN Packages
7A, PolyPhase Synchronous Step-Down Regulator with
Output Tracking and Margining
V : 2.5V to 5.5V, Spread Spectrum Operation, 5mm × 7mm
IN
QFN Package
4A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.25V to 5.5V, I = <1μA,
OUT
IN
SD
with Output Tracking
TSSOP-20E Package
LTC3418
LTC3701
LTC3708
8A, 4MHz Synchronous Step-Down Regulator
V : 2.25V to 5.5V, 5mm × 7mm QFN Package
IN
2-Phase, Low Input Voltage Dual Step-Down DC/DC Controller 2.5V ≤ V ≤ 9.8V, 550kHz, PGOOD, PLL, 16-Lead SSOP
IN
Fast 2-Phase, No R
Buck Controller with Output Tracking Constant On-Time Dual Controller, V Up to 36V, Very Low
SENSE
IN
Duty Cycle Operation, 5mm × 5mm QFN Package
LTC3728/LTC3728L Dual, 550kHz, 2-Phase Synchronous Step-Down
Switching Regulator
Constant-Frequency, V to 36V, 5V and 3.3V LDOs,
IN
5mm × 5mm QFN or 28-Lead SSOP
LTC3736
Dual, 2-Phase, No R
Synchronous Controller
2.75V ≤ V ≤ 9.8V, Output Tracking, Burst Mode Operation
IN
SENSE
SENSE
LTC3736-1
Dual, 2-Phase, No R
Spread Spectrum
Synchronous Controller with
V : 2.75V to 9.8V, 4mm × 4mm QFN Package
IN
Spread Spectrum Operation; Output Tracking
LTC3736-2
LTC3737
2-Phase, No R
, Dual Synchronous Controller with
2.75V ≤ V ≤ 9.8V, 0.6V ≤ V
≤ V , 0.6V 1% Reference,
SENSE
IN
OUT IN
Output Tracking
High Current Limit, 4mm × 4mm QFN Package
Dual, 2-Phase, No R
Controller with Output Tracking
Non-Synchronous Constant-Frequency with PLL, 4mm × 4mm
QFN and 24-Lead SSOP Packages
SENSE
LTC3772
LTC3776
No R
Step-Down DC/DC Controller
2.75V ≤ V ≤ 9.8V, SOT-23 or 3mm × 2mm DFN Packages
IN
SENSE
Dual, 2-Phase, No R
QDR Memory Termination
Synchronous Controller for DDR/
Provides V and V with One IC, 2.75V ≤ V ≤ 9.8V,
DDQ TT IN
SENSE
4mm × 4mm QFN and 24-Lead SSOP Packages
LTC3808
No R
, Low EMI, Synchronous Step-Down Controller with 2.75V ≤ V ≤ 9.8V; Spread Spectrum Operation; 3mm × 4mm
IN
SENSE
Output Tracking
DFN and 16-Lead SSOP Packages
LTC3809/LTC3809-1 No R
Synchronous Step-Down Controllers
2.75V to 9.8V, 3mm × 3mm DFN and 10-Lead MSOPE Packages
SENSE
LTC3822
No R
, Low V , All N-Channel MOSFET, Synchronous
2.75V ≤ V ≤ 4.5V; 0.6V ≤ V
≤ V , 10-Lead MS and
IN
SENSE
IN
IN
OUT
Step-Down DC/DC Controller
3mm x 3mm DFN Packages
LTC3822-1
No R , Low V , All N-Channel MOSFET, Synchronous
2.75V ≤ V ≤ 4.5V; 0.6V ≤ V
≤ V , 16-Lead SSOP and
IN
SENSE
IN
IN
OUT
Step-Down DC/DC Controller with External Soft-Start
3mm x 3mm DFN Packages
Burst Mode is a registered trademark of Linear Technology Corporation.
3836fa
LT 0807 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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