LTC3850EUF#PBF [Linear]
LTC3850 - Dual, 2-Phase Synchronous Step-Down Switching Controller; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C;
| 型号： | LTC3850EUF#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3850 - Dual, 2-Phase Synchronous Step-Down Switching Controller; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总38页 (文件大小：586K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3850/LTC3850-1
Dual, 2-Phase
Synchronous Step-Down
Switching Controller
DESCRIPTION
The LTC®3850 is a high performance dual synchronous
step-down switching regulator controller that drives all
N-channel power MOSFET stages. A constant-frequency
current mode architecture allows a phase-lockable fre-
quency of up to 780kHz. Power loss and supply noise are
minimized by operating the two controller output stages
out of phase.
OPTI-LOOP® compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The LTC3850 features a precision 0.8V
reference and a power good output indicator. A wide 4V to
24V(28Vmaximum/30VforLTC3850I)inputsupplyrange
encompasses most battery chemistries and intermediate
bus voltages.
FEATURES
n
Dual, 180° Phased Controllers Reduce Required
Input Capacitance and Power Supply Induced Noise
n
High Efficiency: Up to 95%
n
R
or DCR Current Sensing
SENSE
n
n
n
n
n
1% 0.8V ꢀutput Voltage Accuracy
Phase-Lockable Fixed Frequency 250kHz to 780kHz
Supports Pre-Biased Output
Dual N-Channel MOSFET Synchronous Drive
Wide V Range: 4V to 24V (30V for LTC3850I)
IN
Operation
n
n
n
n
n
Adjustable Soft-Start Current Ramping or Tracking
Foldback Output Current Limiting
Output Overvoltage Protection
Power Good Output Voltage Monitor
28-Pin 4mm × 4mm, 4mm × 5mm QFN and Narrow
SSOP Packages
Independent TK/SS pins for each controller ramp the
output voltages during start-up. Current foldback limits
MOSFET heat dissipation during short-circuit condi-
tions. The MODE/PLLIN pin selects among Burst Mode®
operation, pulse-skipping mode, or continuous inductor
current mode and allows the IC to be synchronized to an
external clock.
APPLICATIONS
n
Notebook and Palmtop Computers
n
Portable Instruments
n
Battery-Operated Digital Devices
DC Power Distribution Systems
n
TheLTC3850isavailableinlowprofile28-pin4mm× 4mm,
4mm × 5mm QFN and narrow SSOP packages.
L, LT, LTC, LTM, OPTI-LOOP and Burst Mode are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by U.S.
Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258.
TYPICAL APPLICATION
High Efficiency Dual 3.3V/2.5V Step-Down Converter
Efficiency
V
IN
100
95
10000
1000
100
7V TO
24V
22µF
50V
V
V
= 12V
IN
OUT
4.7µF
= 3.3V
EFFICIENCY
V
PGOOD INTV
IN
CC
90
TG1
TG2
0.1µF
0.1µF
85
BOOST1
SW1
BOOST2
SW2
2.2µH
2.2µH
80
75
LTC3850
2.2k
BG2
PGND
BG1
70
65
60
55
50
2.2k
500kHz
MODE/PLLIN
I
FREQ/PLLFLTR
POWER LOSS
1000
LIM
+
–
+
SENSE1
RUN1
SENSE1
SENSE2
0.1µF
0.1µF
RUN2
–
V
SENSE2
OUT1
3.3V
5A
V
OUT2
10
10000
V
V
FB2
2.5V
FB1
10
100
5A
63.4k
43.2k
I
I
LOAD CURRENT (mA)
TH1
TH2
10nF
10k
220pF
15k
220pF
15k
38501 TA01b
TK/SS1 SGND TK/SS2
100µF
6V
100µF
6V
20k
20k
0.1µF
0.1µF
38501 TA01
38501fc
1
LTC3850/LTC3850-1
ABSOLUTE MAXIMUM RATINGS
(Note 1)
+
–
+
–
Input Supply Voltage (V ).........................28V to –0.3V
SENSE1 , SENSE2 , SENSE1 ,
IN
Input Supply Voltage (V ),
SENSE2 Voltages.....................................5.5V to –0.3V
IN
LTC3850I Only .......................................30V to –0.3V
MODE/PLLIN, I ,TK/SS1,TK/SS2, FREQ/PLLFLTR
LIM
Input Supply Transient Voltage (V ) < 500ms, with
Voltages................................................INTV to –0.3V
IN
CC
INTV ≥ 5V, LTC3850I Only...................34V to –0.3V
I
, I , V , V Voltages..................2.7V to –0.3V
CC
TH1 TH2 FB1 FB2
Top Side Driver Voltages
INTV Peak Output Current ................................100mA
CC
BOOST1, BOOST2..................................34V to –0.3V
Switch Voltage (SW1, SW2) .........................28V to –5V
Switch Voltage (SW1, SW2),
Operating Temperature Range (Note 2)....–40°C to 85°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range...................–65°C to 125°C
Lead Temperature (Soldering, 10 sec)
LTC3850I Only ..........................................30V to –5V
INTV , RUN1, RUN2, PGOOD, EXTV ,
(GN Package).................................................... 300°C
CC
CC
(BOOST1-SW1), (BOOST2-SW2).................6V to –0.3V
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
28 FREQ/PLLFLTR
27 MODE/PLLIN
26 SW1
RUN1
+
SENSE1
–
3
SENSE1
4
25 TG1
TK/SS1
28 27 26 25 24 23 22
5
24 BOOST1
23 BG1
I
TH1
TK/SS1
1
2
3
4
5
6
7
21 BOOST1
6
V
FB1
I
BG1
20
19
18
17
16
15
TH1
7
22
V
IN
SGND
V
V
FB1
IN
8
21 INTV
20 BG2
V
CC
FB2
V
INTV
BG2
29
FB2
CC
9
I
TH2
I
TH2
10
11
12
13
14
19 PGND
18 BOOST2
17 TG2
TK/SS2
TK/SS2
PGND
–
–
SENSE2
BOOST2
SENSE2
+
SENSE2
8
9
10 11 12 13 14
UF PACKAGE
16 SW2
RUN2
15 PGOOD
I
(EXTV )*
CC
LIM
GN PACKAGE
28-LEAD NARROW PLASTIC SSOP
28-LEAD (4mm × 4mm) PLASTIC QFN
T
= 125°C, θ = 95°C/W
T
= 125°C, θ = 37°C/W, θ = 2.6°C/W
JMAX
JA
JMAX JA JC
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
*PIN 14 = I FOR LTC3850GN, EXTV FOR LTC3850GN-1
LIM
CC
TOP VIEW
28 27 26 25 24 23
–
SENSE1
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
BOOST1
TK/SS1
ITH1
BG1
VIN
VFB1
INTV
BG2
CC
29
VFB2
ITH2
PGND
BOOST2
TG2
TK/SS2
–
SENSE2
9
10 11 12 13 14
UFD PACKAGE
28-LEAD (4mm × 5mm) PLASTIC QFN
T
= 125°C, θ = 34°C/W, EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
JA
JMAX
38501fc
2
LTC3850/LTC3850-1
ORDER INFORMATION
LEAD FREE FINISH
LTC3850EGN#PBF
LTC3850EGN-1#PBF
LTC3850IGN#PBF
LTC3850IGN-1#PBF
LTC3850EUF#PBF
LTC3850EUFD#PBF
LTC3850IUF#PBF
LTC3850IUFD#PBF
TAPE AND REEL
PART MARKING
LTC3850GN
LTC3850GN-1
LTC3850GN
LTC3850GN-1
3850
PACKAGE DESCRIPTIꢀN
TEMPERATURE RANGE
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
LTC3850EGN#TRPBF
LTC3850EGN-1#TRPBF
LTC3850IGN#TRPBF
LTC3850IGN-1#TRPBF
LTC3850EUF#TRPBF
LTC3850EUFD#TRPBF
LTC3850IUF#TRPBF
LTC3850IUFD#TRPBF
28-Lead Narrow Plastic SSOP
28-Lead Narrow Plastic SSOP
28-Lead Narrow Plastic SSOP
28-Lead Narrow Plastic SSOP
28-Lead (4mm × 4mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 4mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
3850
3850
3850
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
38501fc
3
LTC3850/LTC3850-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2 = 5V, unless otherwise noted.
SYMBꢀL
PARAMETER
CꢀNDITIꢀNS
MIN
TYP
MAX
UNITS
Main Control Loops
l
V
Regulated Feedback Voltage
Feedback Current
I
Voltage = 1.2V; (Note 4)
0.792
0.800
–10
0.808
–50
V
nA
FB1,2
TH1,2
I
(Note 4)
= 6V to 24V (Note 4)
FB1,2
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
0.002
0.02
%/V
REFLNREG
IN
(Note 4)
Measured in Servo Loop; DI Voltage = 1.2V to 0.7V
Measured in Servo Loop; DI Voltage = 1.2V to 1.6V
LOADREG
l
l
0.01
–0.01
0.1
–0.1
%
%
TH
TH
g
m1,2
Transconductance Amplifier g
I = 1.2V; Sink/Source 5µA; (Note 4)
TH1,2
2.2
mmho
m
I
Input DC Supply Current
Normal Mode
Shutdown
(Note 5)
IN
RUN1,2
Q
V
V
= 15V; EXTV Tied to V ; V = 5V
850
30
µA
µA
CC
OUT1 OUT1
= 0V
50
UVLO
UVLO
Undervoltage Lockout on INTV
V
Ramping Down
3
V
V
CC
INTVCC
UVLO Hysteresis
0.5
97.2
0.86
1
HYS
DF
Maximum Duty Factor
In Dropout
96
%
V
MAX
l
l
V
Feedback Overvoltage Lockout
Sense Pin Bias Current
Soft-Start Charge Current
RUN Pin ON Threshold
RUN Pin ON Hysteresis
Measured at V
0.84
0.88
2
OVL
FB1,2
I
I
(Each Channel) V
= 3.3V
µA
µA
V
SENSE
SENSE1,2
V
= 0V
TK/SS1,2
0.9
1.1
1.3
1.22
80
1.7
1.35
TK/SS1,2
V
V
V
V
, V
Rising
RUN1,2
RUN1 RUN2
mV
RUN1,2HYS
SENSE(MAX)
l
l
l
Maximum Current Sense Threshold
(Note 8)
V
V
V
= 0.7V, V
= 0.7V, V
= 0.7V, V
= 3.3V, I = 0V
20
40
60
30
50
75
40
60
90
mV
mV
mV
FB1,2
FB1,2
FB1,2
SENSE1,2
SENSE1,2
SENSE1,2
LIM
= 3.3V, I = Float
LIM
= 3.3V, I = INTV
LIM
CC
TG R
TG R
BG R
BG R
TG Driver Pull-Up On-Resistance
TG Driver Pulldown On-Resistance
BG Driver Pull-Up On-Resistance
BG Driver Pulldown On-Resistance
TG High
TG Low
BG High
BG Low
(Note 6)
2.6
1.5
2.4
1.1
Ω
Ω
Ω
Ω
UP
DOWN
UP
DOWN
TG Transition Time:
Rise Time
Fall Time
TG1,2 t
TG1,2 t
C
C
= 3300pF
25
25
ns
ns
r
f
LOAD
LOAD
= 3300pF
BG Transition Time:
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
BG1,2 t
BG1,2 t
C
C
= 3300pF
= 3300pF
25
25
ns
ns
r
f
TG/BG t
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
1D
C
C
= 3300pF Each Driver
= 3300pF Each Driver
30
ns
LOAD
BG/TG t
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
2D
30
90
ns
ns
LOAD
t
Minimum On-Time
(Note 7)
ON(MIN)
INTV Linear Regulator
CC
V
V
V
V
V
Internal V Voltage
7V < V < 24V
4.8
4.5
5
5.2
2
V
%
INTVCC
CC
IN
INT
INTV Load Regulation
I = 0mA to 50mA
CC
0.5
4.7
50
LDO
CC
l
EXTV Switchover Voltage
EXTV Ramping Positive
V
EXTVCC
CC
CC
EXT
EXTV Voltage Drop
I
= 20mA, V = 5V
EXTVCC
100
mV
mV
LDO
CC
CC
EXTV Hysteresis
200
LDOHYS
CC
38501fc
4
LTC3850/LTC3850-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 15V, VRUN1,2 = 5V, unless otherwise noted.
SYMBꢀL
PARAMETER
CꢀNDITIꢀNS
MIN
TYP
MAX
UNITS
ꢀscillator and Phase-Locked Loop
f
f
f
Nominal Frequency
V
V
V
= 1.2V
= 0V
450
210
700
500
250
780
250
550
290
860
kHz
kHz
kHz
kΩ
NOM
LOW
HIGH
FREQ
FREQ
FREQ
Lowest Frequency
Highest Frequency
≥ 2.4V
R
MODE/PLLIN Input Resistance
MODE/PLLIN
FREQ
I
Phase Detector Output Current
Sinking Capability
Sourcing Capability
f
f
< f
> f
–13
13
µA
µA
MODE
MODE
OSC
OSC
PGꢀꢀD ꢀutput
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.1
0.3
2
V
PGL
PGOOD
I
V
V
µA
PGOOD
PGOOD
V
with Respect to Set Regulated Voltage
FB
PG
V
Ramping Negative
Ramping Positive
–5
5
–7.5
7.5
–10
10
%
%
FB
FB
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3850E/LTC3850E-1 are guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3850I/LTC3850I-1 are
guaranteed to meet performance specifications over the –40°C to 85°C
operating temperature range.
LTC3850GN: T = T + (P • 95°C/W)
J A D
LTC3850UF: T = T + (P • 37°C/W)
J
A
D
LTC3850UFD: T = T + (P • 43°C/W)
J
A
D
Note 4: The LTC3850 is tested in a feedback loop that servos V
specified voltage and measures the resultant V
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
to a
ITH1,2
.
FB1,2
Note 3: T is calculated from the ambient temperature T and power
peak-to-peak ripple current ≥40% of I
(see Minimum On-Time
J
A
MAX
dissipation P according to the following formulas:
Considerations in the Applications Information section).
D
Note 8: V
defaults to 50mV typical for the LTC3850-1.
SENSE(MAX)
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs ꢀutput Current
and Mode
Efficiency vs ꢀutput Current
and Mode
Efficiency and Power Loss
vs Input Voltage
100
90
100
90
2000
1500
1000
500
0
100
V
V
= 12V
V
I
= 3.3V
= 2A
IN
OUT
OUT
OUT
BURST
DCM
= 1.8V
BURST
80
80
95
90
85
80
70
70
EFFICIENCY
DCM
60
50
60
50
40
30
20
10
0
40
30
20
10
0
POWER LOSS
CCM
CCM
V
V
= 12V
OUT
IN
= 3.3V
10
100
LOAD CURRENT (mA)
CIRCUIT OF FIGURE 14
1000
10000
10
100
LOAD CURRENT (mA)
CIRCUIT OF FIGURE 14
1000
10000
15
5
10
20
25
INPUT VOLTAGE (V)
38501 G03
38501 G01
38501 G02
CIRCUIT OF FIGURE 14
38501fc
5
LTC3850/LTC3850-1
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
(Burst Mode ꢀperation)
Load Step
(Forced Continuous Mode)
I
LOAD
I
LOAD
2A/DIV
2A/DIV
200mA TO 2.5A
200mA TO 2.5A
I
I
L
L
2A/DIV
2A/DIV
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC COUPLED
AC COUPLED
38501 G04
38501 G05
40µs/DIV
CIRCUIT OF FIGURE 14
= 12V, V = 1.8V
40µs/DIV
CIRCUIT OF FIGURE 14
V
V
= 12V, V
= 1.8V
IN
OUT
IN
OUT
Load Step
(Pulse-Skipping Mode)
Inductor Current at Light Load
FORCED
CONTINUOUS
MODE
I
LOAD
2A/DIV
200mA TO 2.5A
2A/DIV
I
L
2A/DIV
Burst Mode
OPERATION
2A/DIV
V
OUT
100mV/DIV
AC COUPLED
PULSE-SKIPPING
MODE
2A/DIV
38501 G07
38501 G06
1µs/DIV
CIRCUIT OF FIGURE 14
= 12V, V = 1.8V
40µs/DIV
CIRCUIT OF FIGURE 14
V
I
V
= 12V, V
= 1.8V
IN
OUT
IN
OUT
= 100µA
LOAD
Prebiased ꢀutput at 2V
Coincident Tracking
RUN1
2V/DIV
V
, 3.3V
OUT1
V
OUT
V
TK/SS
3Ω LOAD, 1V/DIV
2V/DIV
500mV/DIV
V
, 1.8V
OUT2
V
FB
1.5Ω LOAD
500mV/DIV
1V/DIV
38501 G09
38501 G08
1ms/DIV
2.5ms/DIV
38501fc
6
LTC3850/LTC3850-1
TYPICAL PERFORMANCE CHARACTERISTICS
Tracking Up and Down
with External Ramp
Quiescent Current
vs Input Voltage without EXTVCC
INTVCC Line Regulation
5.25
5
4
3
2
1
0
TK/SS1
TK/SS2
2V/DIV
5.00
4.75
4.50
4.25
4.00
3.75
3.50
V
OUT1
3.3V
3Ω LOAD
1V/DIV
V
OUT2
1.8V
1.5Ω LOAD
1V/DIV
38501 G10
10ms/DIV
5
10
15
20
5
10
15
25
25
0
20
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
38501 G11
38501 G12
Current Sense Threshold
vs ITH Voltage
Maximum Current Sense Threshold
vs Common Mode Voltage
Maximum Current Sense
Threshold vs Duty Cycle
80
60
80
70
60
50
100
90
80
70
60
50
40
30
20
10
0
I
= INTV
CC
I
= INTV
CC
LIM
LIM
I
= INTV
CC
LIM
I
= FLOAT
LIM
I
= FLOAT
LIM
40
20
I
= FLOAT
LIM
40
30
I
= GND
LIM
I
= GND
LIM
I
= GND
LIM
0
–20
–40
20
10
0
0
0.5
1
1.5
2
1
2
4
0
5
3
20
40
80
0
100
60
V
(V)
V
COMMON MODE VOLTAGE (V)
ITH
DUTY CYCLE (%)
SENSE
38501 G13
38501 G14
38501 G15
TK/SS Pull-Up Current
vs Temperature
Maximum Current Sense Voltage vs
Feedback Voltage (Current Foldback)
2.00
1.75
1.50
1.25
1.00
80
70
60
50
40
30
20
10
0
I
= INTV
CC
LIM
I
I
= FLOAT
= GND
LIM
LIM
50
TEMPERATURE (°C)
100
–50 –25
0
25
75
0.4 0.5
0.6 0.7 0.8 0.9
0
0.1 0.2 0.3
FEEDBACK VOLTAGE (V)
38501 G17
38501 G16
38501fc
7
LTC3850/LTC3850-1
TYPICAL PERFORMANCE CHARACTERISTICS
Regulated Feedback Voltage
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
ꢀscillator Frequency
vs Temperature
900
800
700
600
500
400
300
200
1.5
1.4
1.3
1.2
1.1
1.0
806
804
802
800
798
796
794
V
= INTV
CC
FREQ
ON
V
= 1.2V
FREQ
OFF
V
= 0V
FREQ
50
TEMPERATURE (°C)
100
50
TEMPERATURE (°C)
100
50
TEMPERATURE (°C)
100
–50 –25
0
25
75
–50 –25
0
25
75
–50 –25
0
25
75
38501 G20
38501 G18
38501 G19
ꢀscillator Frequency
vs Input Voltage
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
Shutdown Current
vs Input Voltage
420
410
400
390
380
5
4
3
2
1
0
50
40
30
20
10
0
RISING
FALLING
10
15
20
25
5
10
15
20
25
50
TEMPERATURE (°C)
100
5
–50 –25
0
25
75
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
38501 G22
38501 G21
38501 G23
Quiescent Current
vs Temperature without EXTVCC
Shutdown Current
vs Temperature
50
40
30
20
10
0
5
4
3
2
1
0
V
= 15V
IN
50
TEMPERATURE (°C)
100
–50 –25
0
25
75
50
TEMPERATURE (°C)
100
–50 –25
0
25
75
38501 G24
38501 G25
38501fc
8
LTC3850/LTC3850-1
PIN FUNCTIONS (GN/UF/UFD)
RUN1, RUN2 (Pins 1, 13/Pins 26, 9/Pins 27, 10): Run
Control Inputs. A voltage above 1.2V on either pin turns
on the IC. However, forcing either of these pins below 1.2V
causes the IC to shut down that particular channel. There
are 0.5µA pull-up currents for these pins. Once the RUN
pin rises above 1.2V, an additional 4.5µA pull-up current
is added to the pin.
V > V
at all times. On the GN package, EXTV
IN
EXTVCC CC
is the optional bonding in place of I for LTC3850-1. In
the LTC3850-1, I will default to 50mV.
LIM
LIM
I
(Pin 14, LTC3850 ꢀnly/Pin 10/Pin 11): Current
LIM
Comparator Sense Voltage Range Inputs. Tying this pin to
SGND, FLOAT or INTV sets the maximum current sense
threshold to three different levels for each comparator.
CC
+
+
SENSE1 , SENSE2 (Pins 2, 12/Pins 27, 8/Pins 28, 9):
Current Sense Comparator Inputs. The (+) inputs to the
currentcomparatorsarenormallyconnectedtoDCRsens-
ing networks or current sensing resistors.
PGꢀꢀD (Pin 15/Pin 12/Pin 13): Power Good Indicator
Output. Open-drain logic out that is pulled to ground when
eitherchanneloutputexceedsthe 7.5%regulationwindow,
after the internal 17µs power bad mask timer expires.
–
–
SENSE1 , SENSE2 (Pins 3, 11/Pins 28, 7/Pins 1, 8):
Current Sense Comparator Inputs. The (–) inputs to the
current comparators are connected to the outputs.
PGND(Pin19/Pin16/Pin17):PowerGroundPin.Connect
this pin closely to the sources of the bottom N-channel
MOSFETs, the (–) terminal of CV and the (–) terminal
CC
TK/SS1, TK/SS2 (Pins 4, 10/Pins 1, 6/Pins 2, 7): Output
Voltage Tracking and Soft-Start Inputs. When one channel
is configured to be master of the two channels, a capaci-
tor to ground at this pin sets the ramp rate for the master
channel’s output voltage. When the channel is configured
of C .
IN
INTV (Pin21/Pin18/Pin19):Internal5VRegulatorOutput.
CC
The control circuits are powered from this voltage.
Decouple this pin to PGND with a 4.7µF low ESR tantalum
or ceramic capacitor.
to be the slave of two channels, the V voltage of the
FB
V (Pin 22/Pin 19/Pin 20): Main Input Supply. Decouple
master channel is reproduced by a resistor divider and
applied to this pin. Internal soft-start currents of 1.3µA
charge the soft-start capacitors.
IN
this pin to PGND with a capacitor (0.1µF to 1µF). For ap-
plications where the main input power is 5V, tie the V
IN
and INTV pins together.
CC
I
, I (Pins 5, 9/Pins 2, 5/Pins 3, 6): Current Control
TH1 TH2
BG1, BG2 (Pins 23, 20/Pins 20, 17/Pins 21, 18): Bottom
Gate Driver Outputs. These pins drive the gates of the
bottom N-Channel MOSFETs and swings between PGND
Thresholds and Error Amplifier Compensation Points.
Each associated channels’ current comparator tripping
threshold increases with its I control voltage.
TH
and INTV .
CC
V
, V (Pins 6, 8/Pins 3, 4/Pins 4, 5): Error Amplifier
FB1 FB2
BꢀꢀST1, BꢀꢀST2 (Pins 24, 18/Pins 21, 15/Pins 22, 16):
Boosted Floating Driver Supplies. The (+) terminal of the
boost-strap capacitors connect to these pins. These pins
Feedback Inputs. These pins receive the remotely sensed
feedback voltages for each channel from external resistive
dividers across the outputs.
swing from a diode voltage drop below INTV up to V
CC
IN
SGND (Pin 7/Pin 29/Pin 29): Signal Ground. All small-
signalcomponentsandcompensationcomponentsshould
connect to this ground, which in turn connects to PGND
at one point. Pin 29 is the Exposed Pad, only available on
the UF package.
+ INTV .
CC
TG1, TG2 (Pins 25, 17/Pins 22, 14/Pins 23, 15): Top Gate
Driver Outputs. These are the outputs of floating drivers
with a voltage swing equal to INTV superimposed on
CC
the switch nodes voltages.
EXTV (Pin14, LTC3850-1 ꢀnly/Pin11/Pin12):External
CC
SW1, SW2 (Pins 26, 16/Pins 23, 13/Pins 24, 14): Switch
Node Connections to Inductors. Voltage swing at these
pins are from a body diode voltage drop below ground
Power Input to an Internal Switch Connected to INTV .
This switch closes and supplies the IC power, bypassing
the internal low dropout regulator, whenever EXTV is
higher than 4.7V. Do not exceed 6V on this pin and ensure
CC
CC
to V .
IN
38501fc
9
LTC3850/LTC3850-1
PIN FUNCTIONS
MꢀDE/PLLIN (Pin 27/Pin 24/Pin 25): Force Continuous
Mode, Burst Mode, or Pulse-Skipping Mode Selection
Pin and External Synchronization Input to Phase Detector
Pin. Connect this pin to SGND to force both channels into
FREQ/PLLFLTR(Pin28/Pin25/Pin26):ThePhase-Locked
Loop’sLow-PassFilterisTiedtoThisPin.Alternatively,this
pin can be driven with a DC voltage to vary the frequency
of the internal oscillator.
the continuous mode of operation. Connect to INTV to
CC
Exposed Pad (Pin 29, UF/UFD Packages ꢀnly): Signal
Ground.MustbesolderedtoPCB,providingalocalground
for the control components of the IC, and be tied to the
PGND pin under the IC.
enable pulse-skipping mode of operation. Leaving the
pin floating will enable Burst Mode operation. A clock on
the pin will force the controller into continuous mode of
operation and synchronize the internal oscillator.
FUNCTIONAL DIAGRAM
FREQ/PLLFLTR
MODE/PLLIN
EXTV
V
IN
CC
V
IN
4.7V
+
C
IN
–
+
F
0.8V
5V
REG
MODE/SYNC
DETECT
INTV
CC
PLL-SYNC
–
+
INTV
CC
F
BOOST
BURSTEN
OSC
S
R
C
B
TG
FCNT
ON
Q
I
M1
SW
L1
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
V
OUT
3k
+
–
–
+
+
D
SENSE
SENSE
B
I
CMP
REV
–
+
C
OUT
RUN
OV
BG
M2
C
VCC
SLOPE COMPENSATION
I
LIM
PGND
PGOOD
INTV
CC
UVLO
+
–
0.74V
R2
SLOPE RECOVERY
ACTIVE CLAMP
1
UV
OV
V
FB
51k
I
THB
+
–
V
IN
SLEEP
R1
0.86V
SGND
SS
RUN
–
–
+
+
0.8V
REF
1.3µA
EA
+ –
–
+
+
0.64V
1.2V
0.5µA
0.55V
38501 FD
C
C1
C
SS
I
RUN
TK/SS
TH
R
C
38501fc
10
LTC3850/LTC3850-1
OPERATION
Main Control Loop
Shutdown and Start-Up (RUN1, RUN2 and TK/SS1,
TK/SS2 Pins)
The LTC3850 is a constant-frequency, current mode step-
down controller with two channels operating 180 degrees
out-of-phase. Duringnormaloperation, eachtopMOSFET
is turned on when the clock for that channel sets the RS
latch, and turned off when the main current comparator,
The two channels of the LTC3850 can be independently
shut down using the RUN1 and RUN2 pins. Pulling either
of these pins below 1.2V shuts down the main control
loopforthatcontroller. Pullingbothpinslowdisablesboth
I
, resets the RS latch. The peak inductor current at
controllersandmostinternalcircuits,includingtheINTV
CMP
which I
CC
resets the RS latch is controlled by the voltage
regulator. Releasing either RUN pin allows an internal
0.5µA current to pull up the pin and enable that control-
ler. Alternatively, the RUN pin may be externally pulled up
or driven directly by logic. Be careful not to exceed the
Absolute Maximum Rating of 6V on this pin.
CMP
TH
on the I pin, which is the output of each error ampli-
fier EA. The V pin receives the voltage feedback signal,
FB
which is compared to the internal reference voltage by the
EA. When the load current increases, it causes a slight
decrease in V relative to the 0.8V reference, which in
FB
The start-up of each controller’s output voltage V
is
OUT
turn causes the I voltage to increase until the average
TH
controlled by the voltage on the TK/SS1 and TK/SS2 pins.
When the voltage on the TK/SS pin is less than the 0.8V
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on until either the inductor current starts to reverse, as
indicated by the reverse current comparator I , or the
beginning of the next cycle.
internal reference, the LTC3850 regulates the V voltage
FB
to the TK/SS pin voltage instead of the 0.8V reference. This
allows the TK/SS pin to be used to program a soft-start
by connecting an external capacitor from the TK/SS pin
to SGND. An internal 1.3µA pull-up current charges this
capacitor, creating a voltage ramp on the TK/SS pin. As the
TK/SS voltage rises linearly from 0V to 0.8V (and beyond),
REV
INTV /EXTV Power
CC
CC
Power for the top and bottom MOSFET drivers and most
otherinternalcircuitryisderivedfromtheINTV pin.When
theoutputvoltageV risessmoothlyfromzerotoitsfinal
CC
OUT
the EXTV pin is left open or tied to a voltage less than
value. Alternatively the TK/SS pin can be used to cause the
CC
4.7V,aninternal5VlinearregulatorsuppliesINTV power
start-up of V
to “track” that of another supply. Typically,
CC
OUT
from V . If EXTV is taken above 4.7V, the 5V regulator is
thisrequiresconnectingtotheTK/SSpinanexternalresistor
divider from the other supply to ground (see the Applica-
tions Information section). When the corresponding RUN
IN
CC
turned off and an internal switch is turned on connecting
EXTV . Using the EXTV pin allows the INTV power
CC
CC
CC
to be derived from a high efficiency external source such
as one of the LTC3850 switching regulator outputs.
pin is pulled low to disable a controller, or when INTV
CC
drops below its undervoltage lockout threshold of 3V, the
TK/SS pin is pulled low by an internal MOSFET. When in
undervoltage lockout, both controllers are disabled and
the external MOSFETs are held off.
Each top MOSFET driver is biased from the floating boot-
strap capacitor C , which normally recharges during each
B
off cycle through an external diode when the top MOSFET
turns off. If the input voltage V decreases to a voltage
IN
Light Load Current ꢀperation (Burst Mode ꢀperation,
Pulse-Skipping, or Continuous Conduction)
close to V , the loop may enter dropout and attempt
OUT
to turn on the top MOSFET continuously. The dropout
detector detects this and forces the top MOSFET off for
about one-twelfth of the clock period every third cycle to
The LTC3850 can be enabled to enter high efficiency Burst
Modeoperation,constant-frequencypulse-skippingmode,
or forced continuous conduction mode. To select forced
continuous operation, tie the MODE/PLLIN pin to a DC
voltage below 0.8V (e.g., SGND). To select pulse-skipping
allow C to recharge. However, it is recommended that a
B
load be present during the drop-out transition to ensure
C is recharged.
B
mode of operation, tie the MODE/PLLIN pin to INTV . To
CC
select Burst Mode operation, float the MODE/PLLIN pin.
38501fc
11
LTC3850/LTC3850-1
OPERATION
When a controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-third of the maximum sense voltage even though
Frequency Selection and Phase-Locked Loop
(FREQ/PLLFLTR and MꢀDE/PLLIN Pins)
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage. The switching frequency
of the LTC3850’s controllers can be selected using the
FREQ/PLLFLTR pin. If the MODE/PLLIN pin is not being
driven by an external clock source, the FREQ/PLLFLTR
pin can be used to program the controller’s operating
frequency from 250kHz to 780kHz.
the voltage on the I pin indicates a lower value. If the
TH
average inductor current is higher than the load current,
the error amplifier EA will decrease the voltage on the I
TH
pin. When the I voltage drops below 0.5V, the internal
TH
sleep signal goes high (enabling “sleep” mode) and both
external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When a controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator
A phase-locked loop (PLL) is available on the LTC3850
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller is operating in forced continuous mode when
it is synchronized. A series R-C should be connected
between the FREQ/PLLFLTR pin and SGND to serve as
the PLL’s loop filter.
(I )turnsoffthebottomexternalMOSFETjustbeforethe
REV
inductor current reaches zero, preventing it from revers-
ing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads or
underlargetransientconditions.Thepeakinductorcurrent
Power Good (PGꢀꢀD Pin)
ThePGOODpinisconnectedtoanopendrainofaninternal
N-channel MOSFET. The MOSFET turns on and pulls the
is determined by the voltage on the I pin, just as in nor-
TH
PGOOD pin low when either V pin voltage is not within
FB
mal operation. In this mode, the efficiency at light loads is
lower than in Burst Mode operation. However, continuous
mode has the advantages of lower output ripple and less
interference with audio circuitry.
7.5% of the 0.8V reference voltage. The PGOOD pin is
alsopulledlowwheneitherRUNpinisbelow1.2Vorwhen
the LTC3850 is in the soft-start or tracking phase. When
the V pin voltage is within the 7.5% requirement, the
FB
When the MODE/PLLIN pin is connected to INTV ,
CC
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source of up to 6V. The
PGOOD pin will flag power good immediately when both
the LTC3850 operates in PWM pulse-skipping mode at
light loads. At very light loads, the current comparator
I
may remain tripped for several cycles and force the
CMP
V pins are within the 7.5% window. However, there is
FB
external top MOSFET to stay off for the same number of
cycles (i.e., skipping pulses). The inductor current is not
allowed to reverse (discontinuous operation). This mode,
likeforcedcontinuousoperation,exhibitslowoutputripple
as well as low audio noise and reduced RF interference
as compared to Burst Mode operation. It provides higher
low current efficiency than forced continuous mode, but
not nearly as high as Burst Mode operation.
an internal 17µs power bad mask when either V goes
FB
out of the 7.5% window.
ꢀutput ꢀvervoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (> 7.5%) as well as other more serious con-
ditions that may overvoltage the output. In such cases,
the top MOSFET is turned off and the bottom MOSFET is
turned on until the overvoltage condition is cleared.
38501fc
12
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
+
–
TheTypicalApplicationonthefirstpageisabasicLTC3850
applicationcircuit.LTC3850canbeconfiguredtouseeither
DCR (inductor resistance) sensing or low value resistor
sensing. The choice between the two current sensing
schemes is largely a design trade-off between cost, power
consumption, and accuracy. DCR sensing is becoming
popular because it saves expensive current sensing resis-
tors and is more power efficient, especially in high current
applications. However, current sensing resistors provide
the most accurate current limits for the controller. Other
externalcomponentselectionisdrivenbytheloadrequire-
SENSE and SENSE Pins
+
–
The SENSE and SENSE pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 5V. Both SENSE pins are
high impedance inputs with small base currents of less
than 1µA. When the SENSE pins ramp up from 0V to 1.4V,
the small base currents flow out of the SENSE pins. When
theSENSEpinsrampdownfrom5Vto1.1V, thesmallbase
currents flow into the SENSE pins. The high impedance
inputs to the current comparators allow accurate DCR
sensing. However, care must be taken not to float these
pins during normal operation.
ment, and begins with the selection of R
(if R
is
SENSE
SENSE
used)andinductorvalue.Next,thepowerMOSFETsarese-
lected. Finally, input and output capacitors are selected.
Filter components mutual to the sense lines should be
placed close to the LTC3850, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), sense resistor R1 should be placed
Current Limit Programming
The I pin is a tri-level logic input which sets the maxi-
LIM
mum current limit of the controller. When I
is either
LIM
grounded, floated or tied to INTV , the typical value for
CC
themaximumcurrentsensethresholdwillbe30mV,50mV
or 75mV, respectively.
Which setting should be used? For the best current limit
accuracy,usethe75mVsetting.The30mVsettingwillallow
for the use of very low DCR inductors or sense resistors,
but at the expense of current limit accuracy. The 50mV
settingisagoodbalancebetweenthetwo.Forsingleoutput
dual phase applications (see Figure 21), use the 50mV or
75mV setting for optimal current sharing.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
C
OUT
INDUCTOR OR R
38501 F01
SENSE
Figure 1. Sense Lines Placement
with Inductor or Sense Resistor
V
V
IN
V
V
IN
IN
IN
INTV
INTV
CC
CC
BOOST
TG
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
INDUCTOR
BOOST
TG
V
OUT
L
DCR
SW
R
S
ESL
V
OUT
LTC3850
SW
LTC3850
BG
BG
C
• 2 ≤ ESL/R
F
RF
S
PGND
POLE-ZERO
PGND
R1
CANCELLATION
+
R
R
F
F
SENSE
+
SENSE
C1*
R2
C
F
–
–
SENSE
SENSE
SGND
SGND
38501 F02b
38501 F02a
L
DCR
R2
R1 + R2
+
FILTER COMPONENTS
PLACED NEAR SENSE PINS
||
R1 R2 × C1 =
R
= DCR
*PLACE C1 NEAR SENSE ,
SENSE(EQ)
–
SENSE PINS
(2a) Using a Resistor to Sense Current
(2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
38501fc
13
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
closetotheswitchingnode,topreventnoisefromcoupling
intosensitivesmall-signalnodes. ThecapacitorC1should
be placed close to the IC pins.
reducetheeffectsofcapacitiveandinductivenoisecoupled
inthe sense traces on the PCB. A typical filter consists of
two series 10Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 20ns.
Low Value Resistors Current Sensing
ThissameRCfilter,withminormodifications,canbeusedto
extracttheresistivecomponentofthecurrentsensesignal
inthepresenceofparasiticinductance.Forexample,Figure
3 illustrates the voltage waveform across a 2mΩ sense
resistor with a 2010 footprint for the 1.2V/15A converter
showninFigure18operatingat100%load. Thewaveform
is the superposition of a purely resistive component and a
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
inductor ripple current and the on-time and off-time of
the top switch, the value of the parasitic inductance was
determined to be 0.5nH using the equation:
A typical sensing circuit using a discrete resistor is
shown in Figure 2a. R
required output current.
is chosen based on the
SENSE
The current comparator has a maximum threshold
determined by the I setting. The input
V
SENSE(MAX)
LIM
common mode range of the current comparator is 0V
to 5V. The current comparator threshold sets the peak of
the inductor current, yielding a maximum average output
current I
equal to the peak value less half the peak-to-
MAX
peak ripple current, ∆I . To calculate the sense resistor
L
value, use the equation:
VSENSE(MAX)
VESL(STEP)
RSENSE
=
tON • tOFF
∆IL
ESL =
I(MAX)
+
∆IL
tON + tOFF
2
IftheRCtimeconstantischosentobeclosetotheparasitic
inductance divided by the sense resistor (L/R), the result-
ing waveform looks resistive again, as shown in Figure
4. For applications using low maximum sense voltages,
check the sense resistor manufacturer’s data sheet for
information about parasitic inductance. In the absence of
data, measure the voltage drop directly across the sense
resistor to extract the magnitude of the ESL step and use
the equation above to determine the ESL. However, do not
over-filter. Keep the RC time constant less than or equal
to the inductor time constant to maintain a high enough
BecauseofpossiblePCBnoiseinthecurrentsensingloop,
the AC current sensing ripple of ∆V = ∆I • R
SENSE
L
SENSE
also needs to be checked in the design to get a good
signal-to-noise ratio. In general, for a reasonably good
PCB layout, a 15mV ∆V
a conservative number to start with, either for R
DCR sensing applications.
voltage is recommended as
SENSE
or
SENSE
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV for
theLTC1628/LTC3728family)thatthevoltagedropacross
the parasitic inductance of the sense resistor represented
a relatively small error. For today’s highest current density
solutions, however, the value of the sense resistor can
be less than 1mΩ and the peak sense voltage can be as
low as 20mV. In addition, inductor ripple currents greater
than 50% with operation up to 1MHz are becoming more
common. Under these conditions the voltage drop across
the sense resistor’s parasitic inductance is no longer neg-
ligible. A typical sensing circuit using a discrete resistor is
showninFigure2a. Inpreviousgenerationsofcontrollers,
a small RC filter placed near the IC was commonly used to
ripple voltage on V
.
RSENSE
The above generally applies to high density / high cur-
rent applications where I > 10A and low values of
(MAX)
inductors are used. For applications where I
< 10A,
(MAX)
set R to 10 Ohms and C to 1000pF. This will provide a
F
F
good starting point.
The filter components need to be placed close to the IC.
The positive and negative sense traces need to be routed
as a differential pair and Kelvin connected to the sense
resistor.
38501fc
14
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value
is:
VSENSE(MAX)
RSENSE(EQUIV)
=
∆IL
V
ESL(STEP)
I(MAX)
+
2
V
SENSE
20mV/DIV
To ensure that the application will deliver full load cur-
rent over the full operating temperature range, choose
the minimum value for the Maximum Current Sense
38501 F03
500ns/DIV
Figure 3. Voltage Waveform Measured
Directly Across the Sense Resistor.
Threshold (V ) in the Electrical Characteristics
SENSE(MAX)
table (20mV, 40mV, or 60mV, depending on the state of
the I pin).
LIM
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given
at 20°C. Increase this value to account for the tempera-
ture coefficient of resistance, which is approximately
V
SENSE
20mV/DIV
0.4%/°C. A conservative value for T
is 100°C.
L(MAX)
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
38501 F04
500ns/DIV
RSENSE(EQUIV)
Figure 4. Voltage Waveform Measured After the
Sense Resistor Filter. CF = 1000pF, RF = 100Ω.
RD =
DCR(MAX) at TL(MAX)
Inductor DCR Sensing
C1 is usually selected to be in the range of 0.047µF to
0.47µF. This forces R1||R2 to around 2kΩ, reducing error
that might have been caused by the SENSE pins’ 1µA
current.
For applications requiring the highest possible efficiency
at high load currents, the LTC3850 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amountofDCwindingresistanceofthecopper,whichcanbe
lessthan1mΩfortoday’slowvalue,highcurrentinductors.
In a high current application requiring such an inductor,
conduction loss through a sense resistor would cost sev-
eral points of efficiency compared to DCR sensing.
The equivalent resistance R1||R2 is scaled to the room
temperature inductance and maximum DCR:
L
R1||R2=
(DCR at 20°C) • C1
The sense resistor values are:
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult the
manufacturers’ datasheets for detailed information.
R1||R2
RD
R1• RD
1−RD
R1=
; R2=
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
V
IN(MAX) − VOUT • V
(
)
OUT
PLOSS R1=
R1
38501fc
15
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, re-
duces conduction losses and provides higher efficiency
at heavy loads. Peak efficiency is about the same with
either method.
A reasonable starting point is to choose a ripple current
that is about 40% of I . Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
OUT(MAX)
VIN – VOUT VOUT
fOSC •IRIPPLE VIN
L ≥
•
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
To maintain a good signal to noise ratio for the current
sense signal, use a minimum ∆V
of 10mV to 15mV.
SENSE
For a DCR sensing application, the actual ripple voltage
will be determined by the equation:
V − VOUT VOUT
IN
∆VSENSE
=
R1•C1 V • fOSC
IN
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant-
frequency architectures by preventing subharmonic
oscillations at high duty cycles. It is accomplished inter-
nally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
this results in a reduction of maximum inductor peak cur-
rent for duty cycles >40%. However, the LTC3850 uses
a patented scheme that counteracts this compensating
ramp, which allows the maximum inductor peak current
to remain unaffected throughout all duty cycles.
Power MꢀSFET and Schottky Diode
(ꢀptional) Selection
Two external power MOSFETs must be selected for each
controller in the LTC3850: one N-channel MOSFET for the
top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency f
directly determine the
The peak-to-peak drive levels are set by the INTV
OSC
CC
inductor’s peak-to-peak ripple current:
voltage. This voltage is typically 5V during start-up
(see EXTV Pin Connection). Consequently, logic-level
CC
VOUT V – VOUT
IN
threshold MOSFETs must be used in most applications.
IRIPPLE
=
V
fOSC •L
IN
The only exception is if low input voltage is expected (V
IN
< 5V); then, sub-logic level threshold MOSFETs (V
GS(TH)
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
< 3V) should be used. Pay close attention to the BV
DSS
specification for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance R
, Miller capacitance C
, input
MILLER
38501fc
DS(ON)
16
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
voltage and maximum output current. Miller capacitance,
a short-circuit when the synchronous switch is on close
to 100% of the period.
C
, can be approximated from the gate charge curve
MILLER
usually provided on the MOSFET manufacturers’ data
sheet. C is equal to the increase in gate charge
The term (1 + d) is generally given for a MOSFET in the
MILLER
form of a normalized R
vs Temperature curve, but
DS(ON)
along the horizontal axis while the curve is approximately
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
flat divided by the specified change in V . This result is
DS
then multiplied by the ratio of the application applied V
DS
to the gate charge curve specified V . When the IC is
The optional Schottky diodes conduct during the dead
time between the conduction of the two power MOSFETs.
These prevent the body diodes of the bottom MOSFETs
from turning on, storing charge during the dead time and
requiringareverserecoveryperiodthatcouldcostasmuch
DS
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
VOUT
Main SwitchDuty Cycle=
V
IN
as 3% in efficiency at high V . A 1A to 3A Schottky is
IN
V – VOUT
generally a good compromise for both regions of opera-
tion due to the relatively small average current. Larger
diodes result in additional transition losses due to their
larger junction capacitance.
IN
Synchronous SwitchDuty Cycle=
V
IN
The MOSFET power dissipations at maximum output cur-
rent are given by:
Soft-Start and Tracking
V
2
OUT
The LTC3850 has the ability to either soft-start by itself
with a capacitor or track the output of another channel or
externalsupply.Whenoneparticularchannelisconfigured
to soft-start by itself, a capacitor should be connected to
its TK/SS pin. This channel is in the shutdown state if its
RUN pin voltage is below 1.2V. Its TK/SS pin is actively
pulled to ground in this shutdown state.
P
=
(
I
1+ δ R
+
)
(
)
)
(
MAIN
MAX
DS(ON)
V
IN
I
2
MAX
2
V
R
C
•
)
(
)(
+
IN
DR
MILLER
1
1
• f
OSC
V
– V
V
INTVCC
TH(MIN)
TH(MIN)
Once the RUN pin voltage is above 1.2V, the channel pow-
ers up. A soft-start current of 1.3µA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined to be the voltage range from 0V to 0.8V on the TK/
SS pin. The total soft-start time can be calculated as:
V – V
2
IN
OUT
P
=
I
1+ δ R
DS(ON)
(
)
)
(
SYNC
MAX
V
IN
where d is the temperature dependency of R
and
DS(ON)
R
(approximately 2Ω) is the effective driver resistance
DR
at the MOSFET’s Miller threshold voltage. V
typical MOSFET minimum threshold voltage.
is the
TH(MIN)
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V < 20V
CSS
tSOFTSTART = 0.8 •
1.3µA
IN
the high current efficiency generally improves with larger
MOSFETs, while for V > 20V the transition losses rapidly
IN
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse-skipping mode up
to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.74V, it
will operate in forced continuous mode and revert to the
increasetothepointthattheuseofahigherR
device
DS(ON)
withlowerC
actuallyprovideshigherefficiency. The
MILLER
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
38501fc
17
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
selected mode once TK/SS > 0.74V. The output ripple is
minimized during the 100mV forced continuous mode
window ensuring a clean PGOOD signal.
some tradeoffs exist. The ratiometric mode saves a pair
of resistors, but the coincident mode offers better output
regulation. This can be better understood with the help
of Figure 7. At the input stage of the slave channel’s error
amplifier, two common anode diodes are used to clamp
the equivalent reference voltage and an additional diode
is used to match the shifted common mode voltage. The
top two current sources are of the same amplitude. In the
coincidentmode, theTK/SSvoltageissubstantiallyhigher
than 0.8V at steady state and effectively turns off D1. D2
and D3 will therefore conduct the same current and offer
When the channel is configured to track another supply,
the feedback voltage of the other supply is duplicated by
a resistor divider and applied to the TK/SS pin. Therefore,
the voltage ramp rate on this pin is determined by the
ramp rate of the other supply’s voltage. Note that the
small soft-start capacitor charging current is always
flowing, producing a small offset error. To minimize this
error, select the tracking resistive divider value to be small
enough to make this error negligible.
tight matching between V
and the internal precision
FB2
0.8V reference. In the ratiometric mode, however, TK/SS
equals 0.8V at steady state. D1 will divert part of the bias
In order to track down another channel or supply after
the soft-start phase expires, the LTC3850 is forced into
current to make V slightly lower than 0.8V.
FB2
continuous mode of operation as soon as V is below the
FB
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a finite amount
ofoutputvoltagedeviation.Furthermore,whenthemaster
channel’s output experiences dynamic excursion (under
load transient, for example), the slave channel output will
be affected as well. For better output regulation, use the
coincident tracking mode instead of ratiometric.
undervoltage threshold of 0.74V regardless of the setting
on the MODE/PLLIN pin. However, the LTC3850 should
always be set in force continuous mode tracking down
when there is no load. After TK/SS drops below 0.1V, its
channel will operate in discontinuous mode.
ꢀutput Voltage Tracking
The LTC3850 allows the user to program how its out-
put ramps up and down by means of the TK/SS pins.
Through these pins, the output can be set up to ei-
ther coincidentally or ratiometrically track another
supply’s output, as shown in Figure 5. In the following
INTV Regulators and EXTV
CC
CC
TheLTC3850featuresanNPNlinearregulatorthatsupplies
power to INTV from the V supply. INTV powers the
CC
IN
CC
gate drivers and much of the LTC3850’s internal circuitry.
ThelinearregulatorregulatesthevoltageattheINTV pin
CC
discussions, V
refers to the LTC3850’s output 1 as a
OUT1
to 5V when V is greater than 6.5V. EXTV connects to
IN
CC
master channel and V
refers to the LTC3850’s output
OUT2
INTV through a P-channel MOSFET and can supply the
CC
2 as a slave channel. In practice, though, either phase can
be used as the master. To implement the coincident track-
ing in Figure 5a, connect an additional resistive divider to
needed power when its voltage is higher than 4.7V. Each
of these can supply a peak current of 100mA and must
be bypassed to ground with a minimum of 1µF ceramic
capacitor or low ESR electrolytic capacitor. No matter
what type of bulk capacitor is used, an additional 0.1µF
V
OUT1
and connect its midpoint to the TK/SS pin of the
slave channel. The ratio of this divider should be the same
as that of the slave channel’s feedback divider shown in
ceramic capacitor placed directly adjacent to the INTV
CC
Figure 6a. In this tracking mode, V
must be set higher
OUT1
and PGND pins is highly recommended. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
thanV
.Toimplementtheratiometrictracking,theratio
OUT2
of the V
divider should be exactly the same as the
OUT2
master channel’s feedback divider. By selecting different
resistors, the LTC3850 can achieve different modes of
tracking including the two in Figure 5.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3850 to be
So which mode should be programmed? While either
mode in Figure 5 satisfies most practical applications,
38501fc
18
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
V
V
OUT1
OUT1
V
V
OUT2
OUT2
TIME
38501 F03a
38501 F03b
TIME
(5a) Coincident Tracking
(5b) Ratiometric Tracking
Figure 5. Two Different Modes of ꢀutput Voltage Tracking
V
OUT1
V
OUT1
V
OUT2
V
OUT2
R3
R4
R1
R2
R3
R4
R1
R2
R3
TO
TK/SS2
PIN
TO
TK/SS2
PIN
TO
FB1
PIN
TO
FB2
PIN
TO
TO
V
V
V
FB2
V
FB1
PIN
PIN
R4
38501 F06
(6a) Coincident Tracking Setup
(6b) Ratiometric Tracking Setup
Figure 6. Setup for Coincident and Ratiometric Tracking
I
I
+
–
D1
D2
EA2
TK/SS2
0.8V
D3
V
FB2
38501 F07
Figure 7. Equivalent Input Circuit of Error Amplifier
38501fc
19
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
exceeded. The INTV current, which is dominated by the
1. EXTV left open (or grounded). This will cause
CC
CC
gatechargecurrent,maybesuppliedbyeitherthe5Vlinear
INTV to be powered from the internal 5V regulator
CC
resulting in an efficiency penalty of up to 10% at high
input voltages.
regulator or EXTV . When the voltage on the EXTV pin
CC
CC
is less than 4.7V, the linear regulator is enabled. Power
dissipation for the IC in this case is highest and is equal
2. EXTV connected directly to V . This is the
CC
OUT
to V • I
. The gate charge current is dependent
IN
INTVCC
normal connection for a 5V regulator and provides
the highest efficiency.
on operating frequency as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 3 of the
3. EXTV connected to an external supply. If a 5V
CC
external supply is available, it may be used to power
ElectricalCharacteristics.Forexample,theLTC3850INTV
CC
EXTV providing it is compatible with the MOSFET
CC
current is limited to less than 24mA from a 24V supply in
the GN package and not using the EXTV supply:
gate drive requirements.
CC
4. EXTV connected to an output-derived boost net-
T = 70°C + (24mA)(24V)(95°C/W) = 125°C
CC
J
work. For 3.3V and other low voltage regulators,
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operatingincontinuousconductionmode(MODE/PLLIN=
efficiency gains can still be realized by connecting
EXTV to an output-derived voltage that has been
CC
boosted to greater than 4.7V.
SGND)atmaximumV .WhenthevoltageappliedtoEXTV
IN
CC
For applications where the main input power is 5V, tie
the V and INTV pins together and tie the combined
rises above 4.7V, the INTV linear regulator is turned off
CC
and the EXTV is connected to the INTV . The EXTV
IN
CC
CC
CC
CC
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
remainsonaslongasthevoltageappliedtoEXTV remains
CC
in Figure 8 to minimize the voltage drop caused by the
above 4.5V. Using the EXTV allows the MOSFET driver
CC
gate charge current. This will override the INTV linear
and control power to be derivedfromone oftheLTC3850’s
CC
regulator and will prevent INTV from dropping too low
switching regulator outputs during normal operation and
CC
due to the dropout voltage. Make sure the INTV voltage
from the INTV when the output is out of regulation
CC
CC
is at or exceeds the R
test voltage for the MOSFET
(e.g., start-up, short-circuit). If more current is required
DS(ON)
which is typically 4.5V for logic level devices.
through the EXTV than is specified, an external Schottky
CC
diode can be added between the EXTV and INTV pins.
CC
CC
Do not apply more than 6V to the EXTV pin and make
CC
V
sure that EXTV < V .
IN
CC
IN
LTC3850
R
VIN
INTV
5V
CC
Significant efficiency and thermal gains can be realized by
powering INTV from the output, since the V current
1Ω
CINTV
4.7µF
CC
+
CC
IN
C
IN
resultingfromthedriverandcontrolcurrentswillbescaled
by a factor of (Duty Cycle)/(Switcher Efficiency).
38501 F08
Figure 8. Setup for a 5V Input
Tying the EXTV pin to a 5V supply reduces the junction
CC
temperature in the previous example from 125°C to:
Topside MꢀSFET Driver Supply (C , DB)
B
T = 70°C + (24mA)(5V)(95°C/W) = 81°C
J
External bootstrap capacitors C connected to the BOOST
B
However, for 3.3V and other low voltage outputs, addi-
pinssupplythegatedrivevoltagesforthetopsideMOSFETs.
tional circuitry is required to derive INTV power from
CC
Capacitor C in the Functional Diagram is charged though
B
the output.
external diode DB from INTV when the SW pin is low.
CC
When one of the topside MOSFETs is to be turned on,
The following list summarizes the four possible connec-
the driver places the C voltage across the gate source
tions for EXTV :
B
CC
of the desired MOSFET. This enhances the MOSFET and
38501fc
20
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
turns on the topside switch. The switch node voltage, SW,
ripple current by a factor of 30% to 70% when compared
to a single phase power supply solution.
rises to V and the BOOST pin follows. With the topside
IN
MOSFET on, the boost voltage is above the input supply:
Incontinuousmode,thesourcecurrentofthetopMOSFET
V
B
= V + V
. The value of the boost capacitor
BOOST
IN
INTVCC
is a square wave of duty cycle (V )/(V ). To prevent
OUT
IN
C needs to be 100 times that of the total input capa-
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
citance of the topside MOSFET(s). The reverse break-
down of the external Schottky diode must be greater
than V
. When adjusting the gate drive level, the
IN(MAX)
IMAX
final arbiter is the total input current for the regulator. If
a change is made and the input current decreases, then
the efficiency has improved. If there is no change in input
current, then there is no change in efficiency.
1/2
CIN Required IRMS
≈
V
OUT )(
V – V
IN OUT
(
)
V
IN
This formula has a maximum at V = 2V , where I
RMS
IN
OUT
= I /2. This simple worst-case condition is commonly
OUT
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3850, ceramic capacitors
Undervoltage Lockout
The LTC3850 has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLOcomparatorconstantlymonitorstheINTV voltage
CC
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTV is below
CC
3V. To prevent oscillation when there is a disturbance on
the INTV , the UVLO comparator has 500mV of preci-
CC
can also be used for C . Always consult the manufacturer
IN
sion hysteresis.
if there is any question.
Another way to detect an undervoltage condition is to
The benefit of the LTC3850 2-phase operation can be cal-
culated by using the equation above for the higher power
controller and then calculating the loss that would have
resultedifbothcontrollerchannelsswitchedonatthesame
time.ThetotalRMSpowerlostislowerwhenbothcontrol-
lers are operating due to the reduced overlap of current
pulses required through the input capacitor’s ESR. This is
whytheinputcapacitor’srequirementcalculatedabovefor
theworst-casecontrollerisadequateforthedualcontroller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benefit of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The sources of the top MOSFETs should be placed within
monitor the V supply. Because the RUN pins have a
IN
precision turn-on reference of 1.2V, one can use a resistor
divider to V to turn on the IC when V is high enough.
IN
IN
An extra 4.5µA of current flows out of the RUN pin once
the RUN pin voltage passes 1.2V. One can program the
hysteresis of the run comparator by adjusting the values
of the resistive divider. For accurate V undervoltage
IN
detection, V needs to be higher than 4V.
IN
C and C
Selection
IN
ꢀUT
The selection of C is simplified by the 2-phase architec-
IN
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
beshownthattheworst-casecapacitorRMScurrentoccurs
when only one controller is operating. The controller with
the highest (V )(I ) product needs to be used in the
1cmofeachotherandshareacommonC (s). Separating
OUT OUT
IN
formula below to determine the maximum RMS capacitor
current requirement. Increasing the output current drawn
from the other controller will actually decrease the input
RMS ripple current from its maximum value. The out-of-
phasetechniquetypicallyreducestheinputcapacitor’sRMS
the sources and C may produce undesirable voltage and
IN
current resonances at V .
IN
A small (0.1µF to 1µF) bypass capacitor between the chip
V pin and ground, placed close to the LTC3850, is also
IN
38501fc
21
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
suggested. A 2.2Ω – 10Ω resistor placed between C
soft-start or tracking up. Under short-circuit conditions
with very low duty cycles, the LTC3850 will begin cycle
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The short-
circuit ripple current is determined by the minimum on-
IN
(C1) and the V pin provides further isolation between
IN
the two channels.
The selection of C
is driven by the effective series
OUT
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
time t
of the LTC3850 (≈ 90ns), the input voltage
ON(MIN)
and inductor value:
output ripple (∆V ) is approximated by:
OUT
1
∆VOUT ≈IRIPPLE ESR+
V
IN
L
∆IL(SC) = tON(MIN)
•
8fC
OUT
where f is the operating frequency, C
is the output
OUT
The resulting short-circuit current is:
capacitance and I
is the ripple current in the induc-
RIPPLE
1/3 VSENSE(MAX)
tor. The output ripple is highest at maximum input voltage
since I increases with input voltage.
1
ISC
=
– ∆IL(SC)
RIPPLE
RSENSE
2
Setting ꢀutput Voltage
Phase-Locked Loop and Frequency Synchronization
The LTC3850 output voltages are each set by an external
feedback resistive divider carefully placed across the out-
put, as shown in Figure 9. The regulated output voltage
is determined by:
The LTC3850 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (V ) and a phase
CO
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
of controller 2’s top MOSFET is thus 180 degrees out-
of-phase with the external clock. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
RB
R
VOUT = 0.8V • 1+
A
To improve the frequency response, a feed-forward ca-
pacitor, C , may be used. Great care should be taken to
FF
route the V line away from noise sources, such as the
FB
inductor or the SW line.
V
OUT
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the FREQ/PLLFLTR pin. The
relationship between the voltage on the FREQ/PLLFLTR
pin and operating frequency is shown in Figure 10 and
specified in the Electrical Characteristics table. Note that
the LTC3850 can only besynchronized to an externalclock
whose frequency is within range of the LTC3850’s internal
R
C
FF
B
1/2 LTC3850
V
FB
R
A
38501 F09
Figure 9. Setting ꢀutput Voltage
Fault Conditions: Current Limit and Current Foldback
V .Thisisguaranteedtobebetween250kHzand780kHz.
CO
A simplified block diagram is shown in Figure 11.
The LTC3850 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximumprogrammedvaluetoone-thirdofthemaximum
value. Foldback current limiting is disabled during the
If no clock is applied to MODE/PLLIN pin, the FREQ/
PLLFLTR pin will be high impedance.
If the external clock frequency is greater than the internal
oscillator’s frequency, f , then current is sourced con-
OSC
38501fc
22
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
900
800
700
600
500
400
300
200
100
0
Typically, the external clock (on MODE/PLLIN pin)
input high threshold is 1.6V, while the input low thres-
hold is 1V.
Minimum ꢀn-Time Considerations
Minimum on-time t
is the smallest time duration
ON(MIN)
that the LTC3850 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
0
0.5
1
1.5
2
2.5
FREQ/PLLFLTR PIN VOLTAGE (V)
38501 F10
VOUT
Figure 10. Relationship Between ꢀscillator
Frequency and Voltage at the FREQ/PLLFLTR Pin
tON(MIN)
<
V (f)
IN
2.4V
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
R
LP
C
LP
FREQ/
PLLFLTR
MODE/
PLLIN
DIGITAL
PHASE/
FREQUENCY
DETECTOR
EXTERNAL
OSCILLATOR
The minimum on-time for the LTC3850 is approximately
90ns, with reasonably good PCB layout, minimum 30%
inductor current ripple and at least 10mV – 15mV ripple
on the current sense signal. The minimum on-time can be
affected by PCB switching noise in the voltage and current
loop. As the peak sense voltage decreases the minimum
on-time gradually increases to 130ns. This is of particular
concern in forced continuous applications with low ripple
current at light loads. If the duty cycle drops below the
minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
VCO
38501 F11
Figure 11. Phase-Locked Loop Block Diagram
tinuously from the phase detector output, pulling up the
FREQ/PLLFLTR pin. When the external clock frequency
is less than f , current is sunk continuously, pulling
OSC
down the FREQ/PLLFLTR pin. If the external and internal
frequencies are the same but exhibit a phase difference,
the current sources turn on for an amount of time corre-
spondingtothephasedifference.ThevoltageontheFREQ/
PLLFLTR pin is adjusted until the phase and frequency of
the internal and external oscillators are identical. At the
stable operating point, the phase detector output is high
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
impedance and the filter capacitor C holds the voltage.
LP
The loop filter components, C and R , smooth out the
LP
LP
current pulses from the phase detector and provide a
%Efficiency = 100% – (L1 + L2 + L3 + ...)
stable input to the voltage-controlled oscillator. The filter
where L1, L2, etc. are the individual losses as a percent-
age of input power.
components C and R determine how fast the loop
LP
LP
LP
acquires lock. Typically R = 10k and C is 2200pF to
LP
0.01µF.
38501fc
23
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
Although all dissipative elements in the circuit produce
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
losses, four main sources usually account for most of the
losses in LTC3850 circuits: 1) IC V current, 2) INTV
IN
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
transition losses.
1. The V current is the DC supply current given in
IN
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. V current typi-
2
IN
Transition Loss = (1.7) V
I
C
f
IN O(MAX) RSS
cally results in a small (<0.1%) loss.
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
2. INTV current is the sum of the MOSFET driver and
CC
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
losses can be minimized by making sure that C has
IN
from INTV to ground. The resulting dQ/dt is a cur-
CC
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having
a maximum of 20mΩ to 50mΩ of ESR. The LTC3850
2-phasearchitecturetypicallyhalvesthisinputcapacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead time
and inductor core losses generally account for less than
2% total additional loss.
rent out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
= f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
the topside and bottom side MOSFETs.
Supplying INTV power through EXTV from an out-
CC
CC
put-derived source will scale the V current required
IN
for the driver and control circuits by a factor of (Duty
Cycle)/(Efficiency). For example, in a 20V to 5V applica-
tion, 10mA of INTV current results in approximately
CC
Checking Transient Response
2.5mAofV current. Thisreducesthemid-currentloss
IN
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
from 10% or more (if the driver was powered directly
from V ) to only a few percent.
IN
2
3. I R losses are predicted from the DC resistances of the
load current. When a load step occurs, V
shifts by an
OUT
fuse (if used), MOSFET, inductor, current sense resistor.
In continuous mode, the average output current flows
amount equal to ∆I
(ESR), where ESR is the effective
LOAD
series resistance of C . ∆I
also begins to charge or
generating the feedback error signal that
OUT
LOAD
through L and R
, but is “chopped” between the
SENSE
discharge C
OUT
topside MOSFET and the synchronous MOSFET. If the
two MOSFETs have approximately the same R
forces the regulator to adapt to the current change and
return V to its steady-state value. During this recovery
,
DS(ON)
OUT
then the resistance of one MOSFET can simply be
time V
can be monitored for excessive overshoot or
OUT
summed with the resistances of L and R
to obtain
SENSE
= 10mΩ, R
ringing, which would indicate a stability problem. The
2
I R losses. For example, if each R
DS(ON)
L
availability of the I pin not only allows optimization of
TH
= 10mΩ, R
= 5mΩ, then the total resistance is
SENSE
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
ordersystem, phasemarginand/ordampingfactorcanbe
estimated using the percentage of overshoot seen at this
25mΩ. This results in losses ranging from 2% to 8%
as the output current increases from 3A to 15A for
a 5V output, or a 3% to 12% loss for a 3.3V output.
Efficiency varies as the inverse square of V
for the
OUT
same external components and output power level. The
combined effects of increasingly lower output voltages
38501fc
24
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
pin.Thebandwidthcanalsobeestimatedbyexaminingthe
to approximately 25 • C
require a 250µs rise time, limiting the charging current
to about 200mA.
. Thus a 10µF capacitor would
LOAD
rise time at the pin. The I external components shown
TH
in the Typical Application circuit will provide an adequate
starting point for most applications.
PC Board Layout Checklist
The I series R -C filter sets the dominant pole-zero
TH
C
C
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 12. Figure 13 illustrates the
current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1µs to 10µs will
1. Are the top N-channel MOSFETs M1 and M3 located
within 1 cm of each other with a common drain con-
produce output voltage and I pin waveforms that will
TH
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
nection at C ? Do not attempt to split the input
IN
decoupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C
must return to the combined C
(–) ter-
INTVCC
OUT
minals. The V and I traces should be as short as
FB
TH
possible.ThepathformedbythetopN-channelMOSFET,
Schottky diode and the C capacitor should have short
is why it is better to look at the I pin signal which is in
TH
IN
the feedback loop and is the filtered and compensated
control loop response. The gain of the loop will be in-
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
creased by increasing R and the bandwidth of the loop
C
will be increased by decreasing C . If R is increased by
C
C
the same factor that C is decreased, the zero frequency
C
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
3. Do the LTC3850 V pins’ resistive dividers connect to
FB
the (+) terminals of C ? The resistive divider must be
OUT
connected between the (+) terminal of C
and signal
OUT
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with C , causing a rapid drop in V . No regulator can
+
–
4. Are the SENSE and SENSE leads routed together with
minimumPCtracespacing?Thefiltercapacitorbetween
OUT
OUT
+
–
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connectionsatthesenseresistororinductor,whichever
is used for current sensing.
C
to C
is greater than 1:50, the switch rise time
LOAD
OUT
should be controlled so that the load rise time is limited
38501fc
25
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
TK/SS1
R
PU2
V
PULL-UP
PGOOD
I
PGOOD
TH1
V
FB1
L1
R
SENSE
D1
+
–
V
OUT1
SENSE1
SENSE1
PLLLPF
TG1
SW1
C
B1
M1
M2
BOOST1
BG1
I
LIM
1µF
CERAMIC
f
IN
MODE/PLLIN
RUN1
C
OUT1
V
IN
R
IN
C
VIN
PGND
RUN2
V
GND
IN
EXTV
CC
C
IN
SGND
C
INTVCC
–
INTV
SENSE2
CC
C
OUT2
D2
1µF
CERAMIC
+
BG2
SENSE2
M4
M3
BOOST2
V
FB2
TH2
C
B2
SW2
TG2
I
R
SENSE
V
OUT2
TK/SS2
L2
38501 F12
Figure 12. Recommended Printed Circuit Layout Diagram
SW1
L1
R
SENSE1
V
OUT1
D1
C
R
L1
OUT1
V
IN
R
IN
C
IN
SW2
L2
R
SENSE2
V
OUT2
D2
C
R
L2
OUT2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
38501 F13
Figure 13. Branch Current Waveforms
38501fc
26
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
5. Is the INTV decoupling capacitor connected close
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current com-
parator trip point when the other channel is turning on its
top MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.
CC
to the IC, between the INTV and the power ground
CC
pins?ThiscapacitorcarriestheMOSFETdriverscurrent
peaks. An additional 1µF ceramic capacitor placed im-
mediately next to the INTV and PGND pins can help
CC
improve noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1,TG2),andboostnodes(BOOST1,BOOST2)away
from sensitive small-signal nodes, especially from the
opposite channel’s voltage and current sensing feed-
back pins. All of these nodes have very large and fast
moving signals and therefore should be kept on the
“output side” of the LTC3850 and occupy minimum
PC trace area. If DCR sensing is used, place the top
resistor (Figure 2b, R1) close to the switching node.
Reduce V from its nominal level to verify operation
IN
of the regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V while
IN
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
CC
decouplingcapacitor,thebottomofthevoltagefeedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
for inductive coupling between C , Schottky and the top
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switchingnode(SWpin)tosynchronizetheoscilloscopeto
the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range down to dropout and until the
output load drops below the low current operation
threshold—typically 10% of the maximum designed cur-
rent level in Burst Mode operation.
Design Example
Asadesignexampleforatwochannelmediumcurrentregu-
lator, assume V = 12V(nominal), V = 20V(maximum),
IN
IN
V
= 3.3V, V
= 1.8V, I = 5A, and f = 500kHz
OUT1
OUT2
MAX1,2
(see Figure 14).
The regulated output voltages are determined by:
RB
R
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Over-
compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for its individual
VOUT = 0.8V • 1+
A
Using 20k 1% resistors from both V nodes to ground,
FB
the top feedback resistors are (to the nearest 1% standard
value) 63.4k and 25.5k.
The frequency is set by biasing the FREQ/PLLFLTR pin to
1.2V (see Figure 10), using a divider from INTV . This
CC
38501fc
27
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
V
IN
7V TO
20V
22µF
50V
1µF
2.2Ω
4.7µF
D3
D4
V
PGOOD EXTV INTV
CC CC
IN
M2
M1
TG1
TG2
0.1µF
0.1µF
L1
L2
BOOST1
SW1
BOOST2
SW2
3.3µH
2.2µH
LTC3850
BG2
4.12k
1%
BG1
10k, 1%
6.19k
1%
MODE/PLLIN
PGND
I
LIM
FREQ/PLLFLTR
+
+
SENSE1
SENSE2
1.5k
1%
1.33k
1%
0.1µF
0.1µF
–
–
SENSE1
RUN1
SENSE2
33pF
33pF
RUN2
V
OUT1
3.3V
5A
V
OUT2
V
TH1
V
TH2
1.8V
FB1
FB2
I
I
5A
63.4k
1%
25.5k
1%
2200pF
5.49k
1%
1800pF
TK/SS1
TK/SS2
0.1µF
SGND
100pF
100pF
0.1µF
C
C
OUT1
100µF
X2
20k
1%
4.75k
1%
3.16k
1%
20k
1%
OUT2
100µF
X2
38501 F14
L1, L2: COILTRONICS HCP0703
M1, M2: VISHAY SILICONIX Si4816BDY
C
, C
: TAIYO YUDEN JMK325BJ107MM
OUT1 OUT2
Figure 14. High Efficiency Dual 500kHz 3.3V/1.8V Step-Down Converter
voltage will decrease as V approaches 5V, lowering the
the maximum DC value plus one-half the ripple current,
or 5.725A for Channel 1 and 5.7A for Channel 2.
IN
switchingfrequency.Ifaseparate5Vsupplyisconnectedto
EXTV , INTV will remain at 5V even if V decreases.
CC
CC
IN
Theminimumon-timeoccursonChannel1atthemaximum
The inductance values are based on a 35% maximum
ripple current assumption (1.75A for each channel). The
highest value of ripple current occurs at the maximum
input voltage:
V , and should not be less than 90ns:
IN
VOUT
IN(MAX) f 20V(500kHz)
1.8V
tON(MIN)
With I
=
=
=180ns
resistor value
SENSE
V
VOUT
f • ∆IL(MAX)
VOUT
V
IN(MAX)
floating, the equivalent R
LIM
L =
1−
can be calculated by using the minimum value for the
maximum current sense threshold (40mV).
Channel 1 will require 3.2µH, and Channel 2 will require
1.9µH. The next highest standard values are 3.3µH
and 2.2µH. At the nominal input voltage (12V), the ripple
will be:
V
SENSE(MIN)
R
=
=
SENSE(EQUIV)
∆I
L(NOM)
I
+
LOAD(MAX)
2
40mV
VOUT
VOUT
≅ 7mΩ
∆IL(NOM)
=
1−
1.5A
2
5A +
f • L
V
IN(NOM)
Channel 1 will have 1.45A (29%) ripple, and Channel 2 will
have 1.4A (28%) ripple. The peak inductor current will be
The equivalent R
is the same for Channel 2.
SENSE
38501fc
28
LTC3850/LTC3850-1
APPLICATIONS INFORMATION
The Coiltronics (Cooper) HCP0703-2R2 (20mΩ DCR
The respective values for Channel 2 are R1 = 4.12k, R2 =
MAX
at 20°C) and HCP0703-3R3 (30mΩ DCR
at 20°C) are
1.5k; and P
R1 = 8mW.
MAX
LOSS
chosen.At100°C,theestimatedmaximumDCRvaluesare
26.4mΩ and 39.6mΩ. The divider ratios are:
BurstModeoperationischosenforhighlightloadefficiency
(Figure 15) by floating the MODE/PLLIN pin. Power loss
due to the DCR sensing network is slightly higher at light
loads than would have been the case with a suitable sense
resistor (7mΩ). At heavier loads, DCR sensing provides
higher efficiency.
RSENSE(EQUIV)
7mΩ
RD =
=
= 0.26;
DCRMAX at TL(MAX) 26.4mΩ
7mΩ
≅ 0.18
and
39.6mΩ
ThepowerdissipationonthetopsideMOSFETcanbeeasily
estimated. Choosing a Siliconix Si4816BDY dual MOSFET
For each channel, 0.1µF is selected for C1.
results in: R
= 0.023Ω/0.016Ω, C
@ 100pF.
DS(ON)
MILLER
L
2.2µH
At maximum input voltage with T(estimated) = 50°C:
R1||R2=
=
(DCRMAX at 20°C)•C1 20mΩ •0.1µF
3.3V
2
3.3µH
30mΩ •0.1µF
PMAIN
=
5
1+(0.005)(50°C – 25°C) •
( )
[
]
=1.1k ; and
= 1.1k
20V
0.023Ω + 20V
5A
2
2
2Ω 100pF •
)(
(
) (
)
(
)
For channel 1, the DCR
filter/divider values are:
SENSE
1
1
1.1k
0.18
R1||R2
RD
+
500kHz =186mW
(
)
R1=
R2=
=
≅ 6.19k;
5– 2.3 2.3
R1• RD 6.19k • 0.18
A short-circuit to ground will result in a folded back cur-
rent of:
=
≅1.33k
1−RD
1− 0.18
1/ 3 50mV
0.007Ω
90ns(20V)
3.3µH
(
)
1
2
The power loss in R1 at the maximum input voltage is:
ISC
=
–
= 2.1A
(VIN(MAX) − VOUT )• VOUT
PLOSSR1=
=
with a typical value of R
and d = (0.005/°C)(20)
R1
DS(ON)
= 0.1. The resulting power dissipated in the bottom
MOSFET is:
(20V − 3.3V)•3.3V
= 9mW
6.19k
20V – 3.3V
20V
100
90
80
70
60
50
40
10
2
PSYNC
=
2.1A 1.125 0.016Ω
DCR
(
) (
)(
)
= 66mW
which is less than under full-load conditions.
C is chosen for an RMS current rating of at least 2A at
7mΩ
1
DCR
IN
0.1
0.01
temperature assuming only channel 1 or 2 is on. C
is
OUT
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
EFFICIENCY
POWER LOSS
0.01
0.1
1
10
LOAD CURRENT (mA)
38501 F15
V
= R (∆I ) = 0.02Ω(1.5A) = 30mV
ESR L P–P
ORIPPLE
Figure 15. Design Example Efficiency vs Load
38501fc
29
LTC3850/LTC3850-1
TYPICAL APPLICATIONS
V
IN
7V TO
24V
22µF
50V
2.2Ω
1µF
4.7µF
D3
D4
V
PGOOD INTV
IN
CC
M1
M2
TG1
TG2
0.1µF
0.1µF
L2
2.2µH
L2
3.3µH
BOOST1
SW1
BOOST2
SW2
LTC3850
BG2
BG1
10k
1%
MODE/PLLIN
PGND
I
LIM
FREQ/PLLFLTR
10Ω
1000pF
10Ω
10Ω
+
–
+
SENSE1
SENSE2
1000pF
8mΩ
15pF
8mΩ
10pF
–
SENSE1
RUN1
SENSE2
10Ω
RUN2
V
EXTV
V
OUT1
3.3V
5A
CC
V
OUT2
V
5V
FB1
FB2
TH2
105k
1%
5A
63.4k
1%
I
I
TH1
1000pF
1000pF
TK/SS1
TK/SS2
SGND
+
+
20k
1%
100pF
C
10k
1%
20k
1%
C
OUT2
150µF
15k
1%
3.16k
1%
OUT1
220µF
100pF
0.1µF
0.1µF
38501 F16
L1: TDK RLF 7030T-2R2M5R4
L2: TDK ULF10045T-3R3N6R9
C
C
: SANYO 4TPE220MF
OUT1
: SANYO 6TPE150MI
OUT2
Figure 16. 3.3V/5A, 5V/5A Converter Using Sense Resistors
38501fc
30
LTC3850/LTC3850-1
TYPICAL APPLICATIONS
38501fc
31
LTC3850/LTC3850-1
TYPICAL APPLICATIONS
38501fc
32
LTC3850/LTC3850-1
TYPICAL APPLICATIONS
5V 0.5V
4.7µF
6.3V
2x
1Ω
4.7µF
D3
D4
V
PGOOD EXTV INTV
CC
IN
CC
M2
M1
TG1
TG2
0.1µF
0.1µF
L1
L2
BOOST1
SW1
BOOST2
SW2
0.75µH
0.75µH
LTC3850
BG2
1.2k
1%
BG1
1.2k
1%
PLLIN
750kHz
MODE/PLLIN
PGND
I
LIM
FREQ/PLLFLTR
+
+
SENSE1
SENSE2
4.99k
1%
2.94k
1%
0.047µF
0.047µF
–
–
SENSE1
RUN1
SENSE2
47pF
100pF
RUN2
V
OUT1
1.8V
5A
V
1.2V
5A
OUT2
V
TH1
V
TH2
FB1
FB2
I
I
25.5k
1%
10k
1%
2200pF
14k
1%
100pF
1nF
2200pF
TK/SS1
TK/SS2
0.1µF
10nF
10k
1%
SGND
100pF
0.1µF
C
C
OUT1
100µF
X2
OUT2
100µF
X2
20k
1%
20k
1%
14k
1%
38501 F19
L1, L2: TOKO FDV0630 0.75µH
M1, M2: VISHAY SILICONIX Si4816BDY
, C : TAIYO YUDEN JMK325BJ107MM
C
OUT1 OUT2
Figure 19. 1.8V/5A, 1.2V/5A Core-I/ꢀ Converter with a 5V Input Synchronized at 750kHz
2.2Ω
1µF
V
V
IN2
3.3V
IN1
12V
13.0k
10k
4.7µF
2x
4.7µF
M1
4.7µF
D3
D4
V
PGOOD EXTV INTV
CC CC
IN
M2
TG1
TG2
0.1µF
0.1µF
L1
L2
0.75µH
BOOST1
SW1
BOOST2
SW2
2.2µH
LTC3850
BG2
1.2k
1%
BG1
10k
1%
3.74k
1%
MODE/PLLIN
PGND
I
LIM
FREQ/PLLFLTR
+
+
SENSE1
SENSE2
4.32k
1%
1.40k
1%
0.1µF
0.1µF
–
–
SENSE1
RUN1
SENSE2
47pF
100pF
RUN2
V
OUT1
2.5V
5A
V
1.2V
5A
OUT2
V
TH1
V
TH2
FB1
FB2
I
I
43.2k
1%
10k
1%
2200pF
10k
1%
100pF
2200pF
6.04k
1%
TK/SS1
TK/SS2
0.1µF
SGND
100pF
0.1µF
C
C
OUT1
100µF
X2
OUT2
100µF
X2
20k
1%
20k
1%
3.16k
1%
38501 F20
L1: TOKO FDV0630 2.2µH
L2: TOKO FDV0630 0.75µH
M1, M2: VISHAY SILICONIX Si4816BDY
, C : TAIYO YUDEN JMK325BJ107MM
C
OUT1 OUT2
Figure 20. 2.5V/5A, 1.2V/5A Core-I/ꢀ Converter with Dual Inputs
38501fc
33
LTC3850/LTC3850-1
PACKAGE DESCRIPTION
GN Package
28-Lead Plastic SSꢀP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.386 – .393*
(9.804 – 9.982)
.045 .005
.033
(0.838)
REF
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
1
2
3
4
5
6
7
8
9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
.015 .004
(0.38 0.10)
.0532 – .0688
(1.35 – 1.75)
× 45°
.004 – .0098
(0.102 – 0.249)
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN28 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
38501fc
34
LTC3850/LTC3850-1
UF Package
28-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1721 Rev A)
0.70 0.05
4.50 0.05
3.10 0.05
2.64 0.05
(4 SIDES)
PACKAGE
OUTLINE
0.20 0.05
0.40 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
BOTTOM VIEW—EXPOSED PAD
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
0.75 0.05
R = 0.115
TYP
4.00 0.10
(4 SIDES)
R = 0.05
TYP
27 28
0.40 0.05
PIN 1
TOP MARK
(NOTE 6)
1
2
2.64 0.10
(4-SIDES)
(UF28) QFN 0106 REVA
0.200 REF
0.20 0.05
0.40 BSC
0.00 – 0.05
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
38501fc
35
LTC3850/LTC3850-1
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 0.05
4.50 0.05
3.10 0.05
2.50 REF
2.65 0.05
3.65 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
3.50 REF
4.10 0.05
5.50 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 0.05
4.00 0.10
(2 SIDES)
27
28
0.40 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 0.10
(2 SIDES)
3.50 REF
3.65 0.10
2.65 0.10
(UFD28) QFN 0506 REV B
0.25 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
38501fc
36
LTC3850/LTC3850-1
REVISION HISTORY (Revision history begins at Rev C)
REV
DATE
DESCRIPTIꢀN
PAGE NUMBER
C
3/11
Updated Switch Voltage (SW1, SW2) LTC3850I only from 30V to –0.3V to 30V to –5V
2
38501fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
37
LTC3850/LTC3850-1
TYPICAL APPLICATION
V
IN
7V TO 14V
20k
2.55k
10k
+
2.21k
10µF
2x
RUN
180µF
L1
RJK0305DPB
RJK0301DPB
1nF
0.1µF
–
0.56µH
7.5k
0.1µF
0.1µF
+
SENSE1 SENSE1 RUN1 FREQ MODE SW1 TG1
CMDSH-3
220pF
TK/SS1
BOOST1
BG1
2.2nF
I
TH1
2.74k
20k
2.2Ω
1µF
V
V
V
IN
FB1
FB2
TH2
LTC3850
INTV
CC
V
OUT
1.1V/30A
4.7µF
I
BG2
+
PGND
C
OUT1
100µF
2x
TK/SS2
SENSE2
330µF
2.5V
4x
CMDSH-3
0.1µF
–
BOOST2
L2
0.56µH
RJK0305DPB
RJK0301DPB
+
SENSE2 SGND RUN2
I
EXTV
PGOOD SW2 TG2
CC
LIM
0.1µF
2.21k
PGOOD
20k
100k
RUN
38501 TA04
L1, L2: VISHAY IHLP4040DZ-01 0.56µH
OUT
C
: SANYO 2R5TPE330M9
FOR SINGLE OUTPUT, DUAL PHASE OPERATION, TIE THE FOLLOWING PINS TOGETHER:
V
TO V
TK/SS1 TO TK/SS2
RUN1 TO RUN2
FB1
FB1
ITH1 TO ITH2
Figure 21. 1.1V/30A Dual Phase Core Converter, FSW = 400kHz
RELATED PARTS
PART NUMBER DESCRIPTIꢀN
CꢀMMENTS
97% Efficiency, No Sense Resistor, 16-Pin SSOP
LTC1625/
LTC1775
No R ™ Current Mode Synchronous Step-Down Controllers
SENSE
LTC1735
LTC1778
High Efficiency Synchronous Step-Down Switching Regulator
Programmable Fixed Frequency from 200kHz to 550kHz
≤ (0.9)(V ),
No R Wide Input Range Synchronous Step-Down Controller Up to 97% Efficiency, 4V ≤ V ≤ 36V, 0.8V ≤ V
SENSE
IN
OUT
IN
I
Up to 20A
OUT
LTC3727A-1
LTC3728
Dual, 2-Phase Synchronous Controller
Very Low Dropout; V
≤ 14V, 4V ≤ V ≤ 36V
OUT IN
2-Phase 550kHz, Dual Synchronous Step-Down Controller
20A to 200A PolyPhase® Synchronous Controllers
QFN and SSOP Packages, High Frequency for Smaller L and C
LTC3729
Expandable from 2-Phase to 12-Phase, Uses All Surface Mount
Components
LTC3731
LTC3773
3-Phase, Single Output From 250kHz to 600kHz Synchronous
Step-Down Controller
0.6V ≤ V
≤ 6V, 4.5V ≤ V ≤ 32V, I
≤ 60A,
OUT
OUT
IN
Integrated MOSFET Drivers
3-Phase Step-Down DC/DC Controller,
3.3V ≤ V ≤ 36V, Fixed Frequency 160kHz to 700kHz
Triple Output DC/DC Synchronous Controller
IN
LTC3810
LTC3826
LTC3828
100V Current Mode Synchronous Step-Down Switching Controller 0.8V ≤ V
≤ 0.93V , 6.2V ≤ V ≤ 100V, No R
OUT IN IN SENSE
Low I , Dual, 2-Phase Synchronous Step-Down Controller
30µA I , 0.8V ≤ V
≤ 10V, 4V ≤ V ≤ 36V
OUT IN
Q
Q
Dual, 2-Phase Synchronous Step-Down Controller with Tracking
Up to Six Phases, 0.8V ≤ V
≤ 7V, 4.5V ≤ V ≤ 28V
OUT IN
LTC3834/
LTC3834-1
Low I , Synchronous Step-Down Controller
30µA I , 0.8V ≤ V
≤ 10V, 4V ≤ V ≤ 36V
OUT IN
Q
Q
LT3845
Low I , High Voltage Single Output Synchronous Step-Down
1.23V ≤ V
≤ 36V, 4V ≤ V ≤ 60V, 120µA I
OUT IN Q
Q
DC/DC Controller
PolyPhase is a registered trademark of Linear Technology Corporation. No R
is a trademark of Linear Technology Corporation.
SENSE
38501fc
LT 0311 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
38
l
l
LINEAR TECHNOLOGY CORPORATION 2007
(408)432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC3850EUFD#PBF
LTC3850 - Dual, 2-Phase Synchronous Step-Down Switching Controller; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C
Linear
LTC3850IGN#PBF
LTC3850 - Dual, 2-Phase Synchronous Step-Down Switching Controller; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明