LTC3859IUHF-TRPBF [Linear]
Low IQ, Triple Output, Buck/Buck/Boost Synchronous Controller; 低IQ ,三路输出,降压/降压/升压同步控制器型号: | LTC3859IUHF-TRPBF |
厂家: | Linear |
描述: | Low IQ, Triple Output, Buck/Buck/Boost Synchronous Controller |
文件: | 总40页 (文件大小:592K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3859
Low I , Triple Output,
Q
Buck/Buck/Boost
Synchronous Controller
FEATURES
DESCRIPTION
The LTC®3859 is a high performance triple output (buck/
buck/boost) synchronous DC/DC switching regulator
controllerthatdrivesallN-channelpowerMOSFETstages.
Constant frequency current mode architecture allows a
phase-lockable switching frequency of up to 850kHz. The
LTC3859 operates from a wide 4.5V to 38V input supply
range.Whenbiasedfromtheoutputoftheboostconverter
or another auxiliary supply, the LTC3859 can operate from
an input supply as low as 2.5V after start-up.
n
Dual Buck Plus Single Boost Synchronous Controllers
n
Outputs Remain in Regulation Through Cold Crank
Down to 2.5V
n
Low Operating I : 55μA (One Channel On)
Wide Bias Input Voltage Range: 4.5V to 38V
Buck Output Voltage Range: 0.8V ≤ V
Boost Output Voltage Up to 60V
Q
n
n
n
n
n
n
n
n
≤ 24V
OUT
R
or DCR Current Sensing
SENSE
100% Duty Cycle for Boost Synchronous MOSFET
Phase-Lockable Frequency (75kHz to 850kHz)
Programmable Fixed Frequency (50kHz to 900kHz)
Selectable Continuous, Pulse-Skipping or Low Ripple
Burst Mode® Operation at Light Loads
The 55μA no-load quiescent current extends operating
runtime in battery powered systems. OPTI-LOOP com-
pensation allows the transient response to be optimized
over a wide range of output capacitance and ESR values.
The LTC3859 features a precision 0.8V reference for the
bucks, 1.2V reference for the boost and a power good
output indicator.
n
n
n
n
Very Low Buck Dropout Operation: 99% Duty Cycle
Adjustable Output Voltage Soft-Start or Tracking
Low Shutdown I : 14μA
Small 38-Pin 5mm × 7mm QFN and TSSOP Packages
Q
Independent TRACK/SS pins for each controller ramp the
output voltages during start-up. Current foldback limits
MOSFET heat dissipation during short-circuit conditions.
The PLLIN/MODE pin selects among Burst Mode opera-
tion,pulse-skippingmode,orcontinuousinductorcurrent
mode at light loads.
APPLICATIONS
n
Automotive Always-On and Start-Stop Systems
n
Battery Operated Digital Devices
n
Distributed DC Power Systems
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP and ꢀModule are registered trademarks and
No R
is a trademark of Linear Technology Corporation. All other trademarks are the
SENSE
property of their respective owners. Protected by U.S. Patents including 5481178, 5705919,
5929620, 6144194, 6177787, 6580258.
TYPICAL APPLICATION
V
OUT3
REGULATED AT 10V WHEN V < 10V
IN
220ꢀF
1ꢀF
FOLLOWS V WHEN V > 10V
IN
IN
499k
V
BIAS
Efficiency vs Input Voltage
V
TG1
FB3
68.1k
100
4.9ꢀH
V
5V
5A
6mΩ
OUT1
V
OUT2
= 8.5V
95
90
85
80
75
70
65
60
55
50
TG3
SW3
SW1
BG1
1.2ꢀH
2mΩ
V
IN
V
= 5V
OUT1
2.5V TO 38V
LTC3859
(START-UP ABOVE 5V)
220ꢀF
BG3
+
SENSE1
SENSE1
–
+
–
SENSE3
SENSE3
INTV
V
FB1
357k
CC
68.1k
220ꢀF
RUN1, 2, 3
EXTV
4.7ꢀF
BOOST1, 2, 3
CC
0.1ꢀF
FIGURE 12 CIRCUIT
SW1, 2, 3
I
= 2A
TG2
SW2
BG2
LOAD
V
8.5V
3A
6.5ꢀH
OUT2
8mΩ
I
TH1, 2, 3
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
3859 TA01b
SENSE2+
SENSE2–
TRACK/SS1, 2
SS3
0.1ꢀF
V
FB2
649k
PGND SGND
68.1k
68ꢀF
3859 TA01
3859f
1
LTC3859
ABSOLUTE MAXIMUM RATINGS (Note 1)
+
–
+
+
–
SENSE1 , SENSE2 , SENSE1
Bias Input Supply Voltage (V
).............. –0.3V to 40V
BIAS
SENSE2 Voltages ..................................... –0.3V to 28V
Buck Top Side Driver Voltages
–
SENSE3 , SENSE3 Voltages..................... –0.3V to 40V
(BOOST1, BOOST2) ............................. –0.3V to 46V
Boost Top Side Driver Voltages
PLLIN/MODE, FREQ Voltages ............... –0.3V to INTV
CC
EXTV ....................................................... –0.3V to 14V
(BOOST3) ............................................ –0.3V to 76V
Buck Switch Voltage (SW1, SW2) ................ –5V to 40V
Boost Switch Voltage (SW3) ........................ –5V to 70V
CC
I
, I , I , V , V , V Voltages .... –0.3V to 6V
TH1 TH2 TH3 FB1 FB2 FB3
PGOOD1, OV3 Voltages .............................. –0.3V to 6V
TRACK/SS1, TRACK/SS2, SS3 Voltages ..... –0.3V to 6V
Operating Junction Temperature Range
INTV , (BOOST1–SW1),
CC
(BOOST2–SW2), (BOOST3–SW3),.......... –0.3V to 6V
RUN1, RUN2, RUN3 .................................... –0.3V to 8V
Maximum Current Sourced Into Pin
(Notes 2, 3)........................................–40°C to 125°C
Maximum Junction Temperature........................... 125°C
Storage Temperature Range...................–65°C to 150°C
from Source >8V...............................................100ꢀA
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
TRACK/SS1
PGOOD1
TG1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
I
TH1
V
FB1
+
3
SENSE1
SENSE1
–
38 37 36 35 34 33 32
4
SW1
FREQ
PLLIN/MODE
SS3
1
2
3
4
5
6
7
8
9
31 SW1
5
BOOST1
BG1
FREQ
PLLIN/MODE
SS3
30 BOOST1
6
BG1
29
28
7
SW3
+
SENSE3
SW3
+
8
TG3
SENSE3
–
SENSE3
27 TG3
–
9
BOOST3
BG3
SENSE3
V
BOOST3
26
FB3
39
PGND
39
PGND
10
11
12
13
14
15
16
17
18
19
V
I
FB3
I
25 BG3
TH3
V
BIAS
TH3
SGND
RUN1
24
V
BIAS
EXTV
CC
SGND
23 EXTV
CC
CC
INTV
CC
RUN1
RUN2
RUN3
RUN2 10
22 INTV
21 BG2
BG2
RUN3 11
–
BOOST2
SW2
20
SENSE2 12
BOOST2
–
SENSE2
13 14 15 16 17 18 19
+
TG2
SENSE2
OV3
V
FB2
TH2
TRACK/SS2
I
UHF PACKAGE
38-LEAD (5mm s 7mm) PLASTIC QFN
FE PACKAGE
38-LEAD PLASTIC TSSOP
T
= 125°C, θ = 34°C/W
JA
JMAX
T
= 125°C, θ = 25°C/W
JA
EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB
JMAX
3859f
2
LTC3859
ORDER INFORMATION
LEAD FREE FINISH
LTC3859EFE#PBF
LTC3859IFE#PBF
LTC3859EUHF#PBF
LTC3859IUHF#PBF
TAPE AND REEL
PART MARKING*
LTC3859FE
LTC3859FE
3859
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
LTC3859EFE#TRPBF
LTC3859IFE#TRPBF
LTC3859EUHF#TRPBF
LTC3859IUHF#TRPBF
38-Lead Plastic TSSOP
38-Lead Plastic TSSOP
38-Lead (5mm × 7mm) Plastic QFN
38-Lead (5mm × 7mm) Plastic QFN
3859
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating junction
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TJ ≈ TA = 25°C. VBIAS = 12V, VRUN1,2,3 = 5V, EXTVCC = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Bias Input Supply Operating Voltage
Range
4.5
38
V
BIAS
V
Buck Regulated Feedback Voltage
(Note 4); I
Voltage = 1.2V
FB1,2
TH1,2
–40°C to 125°C
–40°C to 85°C
l
l
0.788 0.800 0.812
0.792 0.800 0.808
V
V
V
Boost Regulated Feedback Voltage
(Note 4); I
Voltage = 1.2V
FB3
TH3
–40°C to 125°C
–40°C to 85°C
1.182 1.200 1.218
1.188 1.200 1.212
V
V
I
Feedback Current
(Note 4)
5
50
nA
FB1,2,3
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
(Note 4); V = 4V to 38V
0.002
0.02
%/V
REFLNREG
IN
(Note 4)
LOADREG
l
l
Measured in Servo Loop;
TH
0.01
0.1
%
%
ΔI Voltage = 1.2V to 0.7V
Measured in Servo Loop;
–0.01 –0.1
2
ΔI Voltage = 1.2V to 2V
TH
g
Transconductance Amplifier g
Input DC Supply Current
(Note 4); I = 1.2V;
mmho
m1,2,3
m
TH1,2,3
Sink/Source 5ꢀA
(Note 5)
I
Q
Pulse-Skipping or
RUN1 = 5V and RUN2,3 = 0V or
RUN2 = 5V and RUN1,3 = 0V or
RUN3 = 5V and RUN1,2 = 0V
2
3
mA
Forced Continuous Mode
(One Channel On)
V
V
ON = 0.83V (No Load)
FB1, 2
= 1.25V
FB3
Pulse-Skipping or
Forced Continuous Mode
(All Channels On)
Sleep Mode
(One Channel On, Buck)
RUN1,2,3 = 5V,
mA
ꢀA
V
V
= 0.83V (No Load)
FB1,2
FB3
= 1.25V
RUN1 = 5V and RUN2,3 = 0V or
RUN2 = 5V and RUN1,3 = 0V
55
80
V
= 0.83V (No Load)
FB,ON
Sleep Mode
RUN3 = 5V and RUN1,2 = 0V
V = 1.25V
FB3
55
65
80
ꢀA
ꢀA
(One Channel On, Boost)
Sleep Mode
(Buck and Boost Channel On)
RUN1 = 5V and RUN2 = 0V or
RUN2 = 5V and RUN1 = 0V
RUN3 = 5V
100
V
V
= 0.83V (No Load)
FB1,2
FB3
= 1.25V
Sleep Mode
RUN1,2,3 = 5V,
80
14
120
30
ꢀA
(All Three Channels On)
V
V
= 0.83V (No Load)
FB1,2
= 1.25V
FB3
Shutdown
RUN1,2,3 = 0V
ꢀA
3859f
3
LTC3859
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TJ ≈ TA = 25°C. VBIAS = 12V, VRUN1,2,3 = 5V, EXTVCC = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
INTV Ramping Up
MIN
TYP
4.15
3.8
MAX
4.5
4.0
13
UNITS
l
l
UVLO
Undervoltage Lockout
V
V
%
CC
INTV Ramping Down
3.5
7
CC
V
Buck Feedback Overvoltage Protection
Measured at V
Relative to
10
OVL1,2
FB1,2
FB1,2
Regulated V
+
I
I
I
+
–
SENSE Pin Current
Bucks (Channels 1 and 2)
1
ꢀA
ꢀA
SENSE1,2
+
+
SENSE Pin Current
Boost (Channel 3)
170
700
SENSE3
SENSE1,2
–
SENSE Pin Current
Bucks (Channels 1 and 2)
V
V
< V
> V
– 0.5V
+ 0.5V
2
1
ꢀA
ꢀA
ꢀA
OUT1,2
OUT1,2
INTVCC
INTVCC
–
I
–
SENSE Pin Current
Boost (Channel 3)
+, V
SENSE3
V
– = 12V
SENSE3
SENSE3
DF
DF
Maximum Duty Factor for TG
Maximum Duty Factor for BG
Bucks (Channels 1,2) in Dropout, FREQ = 0V
Boost (Channel 3) in Overvoltage
Bucks (Channels 1,2) in Overvoltage
Boost (Channel 3)
98
99
%
%
%
%
MAX,TG
100
100
96
MAX,BG
I
I
Soft-Start Charge Current
Soft-Start Charge Current
V
= 0V
0.7
0.7
1.0
1.4
1.4
ꢀA
TRACK/SS1,2
TRACK/SS1,2
V
SS3
= 0V
1.0
ꢀA
SS3
l
l
V
V
ON
RUN2,3
RUN1 Pin Threshold
RUN2,3 Pin Threshold
V
V
Rising
RUN1
Rising
RUN2,3
1.19
1.23
1.25
1.28
1.31
1.33
V
V
RUN1
ON
V
Hyst RUN Pin Hysteresis
80
mV
RUN1,2,3
l
V
Maximum Current Sense Threshold
V
V
= 0.7V, V
FB1,2,3
– = 3.3V
+ = 12V
SENSE3
43
50
57
38
mV
SENSE1,2,3(MAX)
FB1,2
SENSE1,2
= 1.1V, V
V
SENSE3 Pins Common Mode Range
(BOOST Converter Input Supply Voltage)
2.5
V
SENSE3(CM)
Gate Driver
TG1,2
Pull-Up On-Resistance
Pull-Down On-Resistance
2.5
1.5
Ω
Ω
BG1,2
TG3
Pull-Up On-Resistance
2.4
1.1
1.2
1.0
Ω
Ω
Ω
Ω
Pull-Down On-Resistance
Pull-Up On-Resistance
Pull-Down On-Resistance
BG3
Pull-Up On-Resistance
Pull-Down On-Resistance
1.2
1.0
Ω
Ω
TG Transition Time:
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
TG1,2,3 t
TG1,2,3 t
C
C
= 3300pF
= 3300pF
25
16
ns
ns
r
f
BG Transition Time:
Rise Time
Fall Time
(Note 6)
LOAD
LOAD
BG1,2,3 t
BG1,2,3 t
C
C
= 3300pF
= 3300pF
28
13
ns
ns
r
f
TG/BG t
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
C
= 3300pF Each Driver Bucks (Channels 1, 2)
Boost (Channel 3)
30
70
ns
ns
1D
LOAD
BG/TG t
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
C
= 3300pF Each Driver Bucks (Channels 1, 2)
Boost (Channel 3)
30
70
ns
ns
1D
LOAD
t
t
Buck Minimum On-Time
(Note 7)
95
ns
ON(MIN)1,2
Boost Minimum On-Time
(Note 7)
120
ns
ON(MIN)3
INTV Linear Regulator
CC
V
V
Internal V Voltage
6V < V
< 38V, V
= 0V, I = 0mA
INTVCC
5.0
5.4
0.7
5.6
2
V
INTVCCVBIAS
LDOVBIAS
CC
BIAS
EXTVCC
INTV Load Regulation
I
CC
= 0mA to 50mA, V = 0V
EXTVCC
%
CC
3859f
4
LTC3859
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction
temperature range, otherwise specifications are at TJ ≈ TA = 25°C. VBIAS = 12V, VRUN1,2,3 = 5V, EXTVCC = 0V unless otherwise noted.
SYMBOL
PARAMETER
Internal V Voltage
CONDITIONS
6V < V
MIN
TYP
5.4
0.7
4.7
200
MAX
5.6
2
UNITS
V
V
V
V
V
< 13V, I = 0mA
INTVCC
5.0
INTVCCEXT
CC
EXTVCC
INTV Load Regulation
I
CC
= 0mA to 50mA, V = 8.5V
EXTVCC
%
LDOEXT
CC
EXTV Switchover Voltage
EXTV Ramping Positive
4.5
V
EXTVCC
CC
CC
EXTV Hysteresis
mV
LDOHYS
CC
Oscillator and Phase-Locked Loop
f
f
f
f
f
f
Programmable Frequency
Programmable Frequency
Programmable Frequency
Low Fixed Frequency
R
R
R
= 25k; PLLIN/MODE = DC Voltage
= 65k; PLLIN/MODE = DC Voltage
= 105k; PLLIN/MODE = DC Voltage
= 0V PLLIN/MODE = DC Voltage
115
440
835
350
535
kHz
kHz
kHz
kHz
kHz
kHz
25k
FREQ
FREQ
FREQ
FREQ
FREQ
375
505
65k
105k
LOW
HIGH
SYNC
V
V
320
485
75
380
585
850
High Fixed Frequency
= INTV ; PLLIN/MODE = DC Voltage
CC
l
Synchronizable Frequency
PLLIN/MODE = External Clock
PGOOD1 Output
V
PGOOD1 Voltage Low
PGOOD1 Leakage Current
PGOOD1 Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
PGL1
PGOOD1
I
V
ꢀA
PGOOD1
PGOOD1
V
V
V
with Respect to Set Regulated Voltage
Ramping Negative
PG1
FB1
FB1
–13
7
–10
2.5
10
2.5
20
–7
13
%
%
%
%
ꢀs
Hysteresis
Ramping Positive
V
FB1
Hysteresis
T
PG1
Delay For Reporting a Fault
OV3 Boost Overvoltage Indicator Output
V
OV3 Voltage Low
OV3 Leakage Current
OV3 Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
OV3L
OV3
OV3
I
V
ꢀA
OV3
V
OV
V
With Respect to Set Regulated Voltage
FB
6
10
1.5
13
%
%
Hysteresis
= 16V; V = 12V;
SW3
BOOST3 Charge Pump
I
BOOST3 Charge Pump Available Output
Current
V
65
ꢀA
BST3
BOOST3
Forced Continuous Mode
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The LTC3859 is tested in a feedback loop that servos V
to a
ITH1,2,3
specified voltage and measures the resultant V
. The specification at
FB1,2,3
85°C is not tested in production. This specification is assured by design,
characterization and correlation to production testing at 125°C.
Note 2: The LTC3859 is tested under pulsed conditions such that T ≈ T .
The LTC3859E is guaranteed to meet performance specifications from
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications information.
J
A
0°C to 125°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3859I is guaranteed over the full
–40°C to 125°C operating junction temperature range.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: See Minimum On-Time Considerations in the Applications
Information section.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
T = T + (P • θ )
JA
J
A
D
where θ = 34°C/W for the QFN package and θ = 25°C/W for the TSSOP
JA
JA
package.
3859f
5
LTC3859
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current (Buck)
Efficiency
vs Output Current (Buck)
Efficiency vs Input Voltage (Buck)
100
90
80
70
60
50
40
30
20
10
0
100
99
98
97
96
95
94
93
92
100
90
80
70
60
50
40
30
20
10
0
10000
1000
100
10
FIGURE 12 CIRCUIT
V
= 10V
IN
V
LOAD
= 5V
= 4A
OUT
I
V
= 20V
IN
CCM EFFICIENCY
PULSE-SKIPPING
EFFICIENCY
BURST LOSS
BURST EFFICIENCY
CCM LOSS
1
PULSE-SKIPPING
LOSS
FIGURE 12 CIRCUIT
0.01
OUTPUT CURRENT (A)
0.1
0.0001 0.001
0.1
1
10
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
0.0001 0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
3859 G02
3859 G03
3859 G01
FIGURE 12 CIRCUIT
= 10V, V = 5V
V
IN
OUT
Load Step (Buck)
Burst Mode Operation
Load Step (Buck)
Pulse-Skipping Mode
Load Step (Buck)
Forced Continuous Mode
V
OUT
V
V
OUT
OUT
100mV/DIV
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
AC-COUPLED
I
I
I
L
L
L
2A//DIV
2A//DIV
2A//DIV
3859 G04
3859 G06
3859 G05
50ꢀs/DIV
50ꢀs/DIV
50ꢀs/DIV
V
V
= 12V
= 5V
V
V
= 12V
= 5V
V
V
= 12V
= 5V
IN
OUT
IN
OUT
IN
OUT
FIGURE 12 CIRCUIT
FIGURE 12 CIRCUIT
FIGURE 12 CIRCUIT
Inductor Current at Light Load
(Buck)
Buck Regulated Feedback Voltage
vs Temperature
Soft Start-Up
808
806
804
802
800
798
796
794
792
FORCED
CONTINUOUS
MODE
V
OUT2
2V/DIV
Burst Mode
OPERATION
1A/DIV
V
OUT1
2V/DIV
PULSE-
SKIPPING
MODE
3859 G08
3859 G07
2ms/DIV
FIGURE 12 CIRCUIT
2ꢀs/DIV
V
V
= 10V
IN
= 5V
OUT
LOAD
I
= 1mA
–45 –20
5
30
55
80 105 130
FIGURE 12 CIRCUIT
TEMPERATURE (°C)
3859 G09
3859f
6
LTC3859
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current (Boost)
Efficiency
vs Output Current (Boost)
Efficiency vs Input Voltage (Boost)
100
90
80
70
60
50
40
30
20
10
0
10000
1000
100
100
90
80
70
60
50
40
30
20
10
0
100
99
98
97
96
95
94
93
92
91
90
FIGURE 12 CIRCUIT
V
= 8V
IN
V
V
LOAD
= V
= 10V
= 2A
V
= 5V
BIAS
OUT
IN
IN
I
CCM EFFICIENCY
PULSE-SKIPPING 10
EFFICIENCY
BURST LOSS
BURST
1
EFFICIENCY
FIGURE 12 CIRCUIT
CCM LOSS
V
BIAS
V
OUT
= V
IN
PULSE-SKIPPING
= 10V
LOSS
0.1
0.0001 0.001
OUTPUT CURRENT (A)
FIGURE 12 CIRCUIT
= 5V, V = 10V, V
0.01
0.1
1
10
0.0001 0.001
0.01
0.1
1
10
2
3
4
5
6
7
8
9
10
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
3859 G10
3859 G11
3859 G12
V
IN
= V
IN
OUT
BIAS
Load Step (Boost)
Burst Mode Operation
Load Step (Boost)
Pulse-Skipping Mode
Load Step (Boost)
Forced Continuous Mode
V
OUT
V
V
OUT
OUT
100mV/
DIV
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
AC-
COUPLED
I
I
I
L
L
L
5A/DIV
5A/DIV
5A/DIV
3859 G14
3859 G13
3859 G15
200ꢀs/DIV
200ꢀs/DIV
200ꢀs/DIV
V
V
= 10V
V
V
= 10V
V
V
= 10V
OUT
OUT
IN
OUT
IN
= 5V
= 5V
= 5V
IN
FIGURE 12 CIRCUIT
FIGURE 12 CIRCUIT
FIGURE 12 CIRCUIT
Inductor Current at Light Load
(Boost)
Boost Regulated Feedback
Voltage vs Temperature
Soft Start-Up (Boost)
1.212
1.209
1.206
1.203
1.200
1.197
1.194
1.191
1.188
FORCED
CONTINUOUS
MODE
Burst Mode
OPERATION
5A/DIV
V
OUT3
2V/DIV
PULSE-
SKIPPING
MODE
GND
3859 G17
3859 G16
2ms/DIV
2ꢀs/DIV
V
= 5V
V
V
I
= 10V
IN
OUT
IN
FIGURE 12 CIRCUIT
= 7V
= 1mA
LOAD
–45 –20
5
30
55
80 105 130
FIGURE 12 CIRCUIT
TEMPERATURE (°C)
3859 G18
3859f
7
LTC3859
TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC and EXTVCC
vs Load Current
EXTVCC Switchover and INTVCC
Voltages vs Temperature
INTVCC Line Regulation
5.5
5.4
5.3
5.2
5.1
5.0
5.50
5.45
5.40
5.35
5.30
5.25
5.20
5.15
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
V
= 12V
BIAS
INTV
CC
EXTV = 0V
CC
EXTV = 8.5V
CC
EXTV RISING
CC
EXTV FALLING
CC
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
0
20 40 60 80 100 120 140 160 180 200
–45 –20
5
30
55
80 105 130
LOAD CURRENT (mA)
TEMPERATURE (°C)
3859 G19
3859 G20
3859 G21
SENSE Pins Total Input Current
vs VSENSE Voltage
Buck SENSE Pins Total Input
Current vs Temperature
Boost SENSE Pin Total Input
Current vs Temperature
900
800
700
600
500
400
300
200
100
0
200
180
160
140
120
100
80
800
700
600
500
400
300
200
100
0
+
V
OUT
= 28V
SENSE3 PIN
SENSE1, 2 PINS
60
SENSE3 PIN
40
20
–
V
OUT
= 3.3V
SENSE3 PIN
0
–45 –20
5
30 35 55 80 105 130
–45 –20
5
30 35 55 80 105 130
0
5
10 15 20 25 30 35 40
COMMON MODE VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
V
SENSE
3859 G23
3859 G24
3859 G22
Maximum Current Sense
Threshold vs Duty Cycle
Maximum Current Sense
Threshold vs ITH Voltage
Soft-Start Pull-Up Current
vs Temperature
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
80
70
60
50
40
30
20
10
0
60
50
40
30
BOOST
BUCK
20
10
0
–10
–20
–30
PULSE-SKIPPING
FORCED CONTINUOUS
Burst Mode OPERATION
–45 –20
5
30
55
80 105 130
0
10 20 30 40 50 60 70 80 90 100
0
0.2 0.4 0.6 0.8
(V)
1
1.2 1.4
TEMPERATURE (°C)
DUTY CYCLE (%)
I
TH
3859 G27
3859 G25
3859 G26
3859f
8
LTC3859
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Current
vs Input Voltage
Shutdown Current vs Temperature
Quiescent Current vs Temperature
25
20
15
10
5
22
20
18
16
14
12
10
8
100
90
80
70
60
50
40
ALL CHANNELS ON
ONE CHANNEL ON
0
5
10
15
20
25
30
35
40
–45 –20
5
30
55
80 105 130
–45 –20
5
30
55
80 105 130
INPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
3859 G29
3859 G28
3859 G30
Oscillator Frequency
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
Buck Foldback Current Limit
70
65
60
55
50
45
40
35
30
25
20
15
10
5
600
550
500
450
400
350
300
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
FREQ = INTV
CC
RISING
FALLING
FREQ = GND
0
0
100 200 300 400 500 600 700 800
–45 –20
5
30
55
80 105 130
–45 –20
5
30
55
80 105 130
FEEDBACK VOLTAGE (mV)
TEMPERATURE (°C)
TEMPERATURE (°C)
3859 G31
3859 G32
3859 G33
Shutdown (RUN) Threshold
vs Temperature
Charge Pump Charging Current
vs Operating Frequency
Charge Pump Charging Current
vs Switch Voltage
100
90
80
70
60
50
40
30
20
10
0
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
100
90
80
70
60
50
40
30
20
10
0
V
– V
= 4V
SW3
V
V
= 16V
BOOST3
BOOST3
SW3
= 12V
FREQ = 0V
–45°C
RUN2,3 RISING
25°C
RUN1 RISING
FREQ = INTV
CC
RUN2,3 FALLING
RUN1 FALLING
130°C
5
10
15
20
25
30
35
40
–45 –20
5
30
55
80 105 130
100 200 300 400 500 600 700 800
SWITCH VOLTAGE (V)
TEMPERATURE (°C)
OPERATING FREQUENCY (kHz)
3859 G36
3859 G34
3859 G35
3859f
9
LTC3859
PIN FUNCTIONS (QFN/TSSOP)
FREQ (Pin 1/Pin 5): The Frequency Control Pin for the
Internal VCO. Connecting the pin to GND forces the VCO
to a fixed low frequency of 350kHz. Connecting the pin
INTV (Pin 22/Pin 26): Output of the Internal Linear Low
CC
DropoutRegulator.Thedriverandcontrolcircuitsarepow-
eredfromthisvoltagesource.MustbedecoupledtoPGND
with a minimum of 4.7ꢀF ceramic or tantalum capacitor.
to INTV forces the VCO to a fixed high frequency of
CC
535kHz. Other frequencies between 50kHz and 900kHz
can be programmed using a resistor between FREQ and
GND. The resistor and an internal 20ꢀA source current
create a voltage used by the internal oscillator to set the
frequency.
The INTV pin should also be connected to the DRV
CC
CC
pin, and should not be used for any other purpose.
EXTV (Pin 23/Pin 27): External Power Input to an
CC
Internal LDO Connected to INTV . This LDO supplies
CC
INTV power, bypassing the internal LDO powered from
CC
PLLIN/MODE (Pin 2/Pin 6): External Synchronization
Input to Phase Detector and Forced Continuous Mode
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG1 signal to be
synchronized with the rising edge of the external clock,
and the regulators operate in forced continuous mode.
When not synchronizing to an external clock, this input,
which acts on all three controllers, determines how the
LTC3859 operates at light loads. Pulling this pin to ground
selects Burst Mode operation. An internal 100k resistor to
ground also invokes Burst Mode operation when the pin is
V
whenever EXTV is higher than 4.7V. See EXTV
IN CC CC
Connection in the Applications Information section. Do
not exceed 14V on this pin.
V
(Pin 24/Pin 28): Main Bias Input Supply Pin. A
BIAS
bypass capacitor should be tied between this pin and the
SGND pin.
BG1, BG2, BG3 (Pins 29, 21, 25/Pins 33, 25, 29): High
CurrentGateDrivesforBottom(Synchronous)N-Channel
MOSFETs. Voltage swing at these pins is from ground to
INTV .
CC
floated.TyingthispintoINTV forcescontinuousinductor
CC
BOOST1, BOOST2, BOOST3 (Pins 30, 20, 26/Pins 34,
24, 30): Bootstrapped Supplies to the Top Side Floating
Drivers.CapacitorsareconnectedbetweentheBOOSTand
SW pins and Schottky diodes are tied between the BOOST
current operation. Tying this pin to a voltage greater than
1.2V and less than INTV – 1.3V selects pulse-skipping
CC
operation. This can be done by connecting a 100k resistor
from this pin to INTV .
CC
and INTV pins. Voltage swing at the BOOST pins is from
CC
INTV to (V + INTV ).
SGND (Pin 8/Pin 12): Small Signal Ground common to
both controllers, must be routed separately from high
current grounds to the common (–) terminals of the C
capacitors.
CC
IN
CC
SW1, SW2, SW3 (Pins 31, 19, 28/Pins 35, 23, 32):
Switch Node Connections to Inductors.
IN
TG1, TG2, TG3 (Pins 32, 18, 27/Pins 36, 22, 31): High
Current Gate Drives for Top N-Channel MOSFETs. These
are the outputs of floating drivers with a voltage swing
RUN1, RUN2, RUN3 (Pins 9, 10, 11/Pins 13, 14, 15):
DigitalRunControlInputsforEachController.Forcingeither
ofthesepinsbelow1.2Vshutsdownthatcontroller.Forcing
allofthesepinsbelow0.7VshutsdowntheentireLTC3859,
reducing quiescent current to approximately 14ꢀA.
equal to INTV superimposed on the switch node volt-
CC
age SW.
PGOOD1 (Pin 33/Pin 37): Open-Drain Logic Output.
OV3 (Pin 17/Pin 21): Overvoltage Open-Drain Logic
PGOOD1 is pulled to ground when the voltage on the V
pin is not within 10% of its set point.
FB1
Output for the Boost Regulator. OV3 is pulled to ground
when the voltage on the V pin is under 110% of its set
FB3
point, and becomes high impedance when V goes over
FB3
110% of its set point.
3859f
10
LTC3859
PIN FUNCTIONS (QFN/TSSOP)
TRACK/SS1, TRACK/SS2, SS3 (Pins 34, 16, 3/Pins 38,
V
, V , V (Pins36, 14, 6/Pins2, 18, 10):Receives
FB1 FB2 FB3
20, 7):ExternalTrackingandSoft-StartInput. Forthebuck
the remotely sensed feedback voltage for each controller
from an external resistive divider across the output.
channels, the LTC3859 regulates the V
voltage to the
FB1,2
smallerof0.8V,orthevoltageontheTRACK/SS1,2pin.For
+
+
+
SENSE1 ,SENSE2 ,SENSE3 (Pins37,13,4/Pins3,17,
the boost channel, the LTC3859 regulates the V voltage
FB3
8): The (+) Input to the Differential Current Comparators.
to the smaller of 1.2V, or the voltage on the SS3 pin. An
internal1ꢀApull-upcurrentsourceisconnectedtothispin.
A capacitor to ground at this pin sets the ramp time to final
regulatedoutputvoltage.Alternatively,aresistordivideron
another voltage supply connected to the TRACK/SS pins
of the buck channels allow the LTC3859 buck outputs to
track the other supply during start-up.
The I pin voltage and controlled offsets between the
TH
–
+
SENSE andSENSE pinsinconjunctionwithR
setthe
SENSE
+
currenttripthreshold. Fortheboostchannel,theSENSE3
pin supplies current to the current comparator.
–
–
–
SENSE1 , SENSE2 , SENSE3 (Pins 38, 12, 5/Pins 4,
16, 9): The (–) Input to the Differential Current Compara-
–
tors. When SENSE1,2 for the buck channels is greater
I , I , I
TH1 TH2 TH3
(Pins 35, 15, 7/Pins 1, 19, 11): Error
–
than INTV , then SENSE1,2 pin supplies current to the
CC
AmplifierOutputsandSwitchingRegulatorCompensation
Points. Each associated channel’s current comparator trip
point increases.
current comparator.
PGND (Exposed Pad Pin 39): Driver Power Ground. Con-
nects to the sources of bottom (synchronous) N-channel
MOSFETs and the (–) terminal(s) of C . The exposed
IN
pad must be soldered to the PCB for rated electrical and
thermal performance.
3859f
11
LTC3859
FUNCTIONAL DIAGRAM
3859f
12
LTC3859
FUNCTIONAL DIAGRAM
3859f
13
LTC3859
OPERATION (Refer to Functional Diagram)
Main Control Loop
Each top MOSFET driver is biased from the floating boot-
strap capacitor C , which normally recharges during each
B
The LTC3859 uses a constant frequency, current mode
step-down architecture. The two buck controllers, chan-
nels 1 and 2, operate 180 degrees out of phase with each
other. The boost controller, channel 3, operates in phase
with channel 1. During normal operation, the external
top MOSFET for the buck channels (the external bottom
MOSFET for the boost channel) is turned on when the
clock for that channel sets the RS latch, and is turned off
when the main current comparator, ICMP, resets the RS
latch. The peak inductor current at which ICMP trips and
cycle through an external diode when the switch voltage
goes low.
For buck channels 1 and 2, if the buck’s input voltage
decreases to a voltage close to its output, the loop may
enter dropout and attempt to turn on the top MOSFET
continuously.Thedropoutdetectordetectsthisandforces
the top MOSFET off for about one twelfth of the clock
period every tenth cycle to allow C to recharge.
B
Shutdown and Start-Up (RUN1, RUN2, RUN3 and
TRACK/SS1, TRACK/SS2, SS3 Pins)
resets the latch is controlled by the voltage on the I pin,
TH
which is the output of the error amplifier EA. The error
amplifier compares the output voltage feedback signal at
The three channels of the LTC3859 can be independently
shut down using the RUN1, RUN2 and RUN3 pins. Pull-
ing any of these pins below 1.2V shuts down the main
control loop for that channel. Pulling all three pins below
0.7V disables all controllers and most internal circuits,
the V pin, (which is generated with an external resistor
FB
divider connected across the output voltage, V , to
OUT
ground) to the internal 0.800V reference voltage for the
bucks (1.2V reference voltage for the boost). When the
load current increases, it causes a slight decrease in V
FB
including the INTV LDOs. In this state, the LTC3859
CC
relative to the reference, which causes the EA to increase
draws only 14ꢀA of quiescent current.
the I voltage until the average inductor current matches
TH
Releasing a RUN pin allows a small internal current to pull
up the pin to enable that controller. The RUN1 pin has a
6ꢀA pull-up current while the RUN2 and RUN3 pins have
a smaller 0.5ꢀA. The 6ꢀA current on RUN1 is designed
to be large enough so that the RUN1 pin can be safely
floated (to always enable the controller) without worry
of condensation or other small board leakage pulling the
pin down. This is ideal for always-on applications where
one or more controllers are enabled continuously and
never shut down.
the new load current.
After the top MOSFET for the bucks (the bottom MOSFET
fortheboost)isturnedoffeachcycle, thebottomMOSFET
is turned on (the top MOSFET for the boost) until either
the inductor current starts to reverse, as indicated by the
current comparator IR, or the beginning of the next clock
cycle.
INTV /EXTV Power
CC
CC
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV pin.
Each RUN pin may also be externally pulled up or driven
directly by logic. When driving a RUN pin with a low im-
pedance source, do not exceed the absolute maximum
rating of 8V. Each RUN pin has an internal 11V voltage
clamp that allows the RUN pin to be connected through
CC
When the EXTV pin is left open or tied to a voltage less
CC
than 4.7V, the V
LDO (low dropout linear regulator)
BIAS
supplies 5.4V from V
to INTV . If EXTV is taken
BIAS
CC CC
above 4.7V, the V
LDO is turned off and an EXTV
BIAS
CC
a resistor to a higher voltage (for example, V
), so
BIAS
LDO is turned on. Once enabled, the EXTV LDO supplies
CC
long as the maximum current in the RUN pin does not
exceed 100ꢀA.
5.4V from EXTV to INTV . Using the EXTV pin allows
CC
CC
CC
the INTV power to be derived from a high efficiency
CC
The start-up of each channel’s output voltage V
is con-
external source such as one of the LTC3859 switching
OUT
trolledbythevoltageontheTRACK/SSpin(TRACK/SS1for
channel 1, TRACK/SS2 for channel 2, SS3 for channel 3).
When the voltage on the TRACK/SS pin is less than the
regulator outputs.
3859f
14
LTC3859
OPERATION
0.8V internal reference for the bucks and the 1.2V internal
reference for the boost, the LTC3859 regulates the V
two channels are in sleep mode and the other shut down, it
drawsonly65ꢀAofquiescentcurrent.Ifallthreecontrollers
are enabled in sleep mode, the LTC3859 draws only 80ꢀA
ofquiescent. Insleepmode, theloadcurrentissuppliedby
the output capacitor. As the output voltage decreases, the
EA’s output begins to rise. When the output voltage drops
FB
voltage to the TRACK/SS pin voltage instead of the cor-
responding reference voltage. This allows the TRACK/SS
pin to be used to program a soft-start by connecting an
external capacitor from the TRACK/SS pin to SGND. An
internal1ꢀApull-upcurrentchargesthiscapacitorcreating
a voltage ramp on the TRACK/SS pin. As the TRACK/SS
voltage rises linearly from 0V to 0.8V/1.2V (and beyond
enough, the I pin is reconnected to the output of the
TH
EA, the sleep signal goes low, and the controller resumes
normal operation by turning on the top external MOSFET
on the next cycle of the internal oscillator.
up to INTV ), the output voltage V
rises smoothly
CC
OUT
from zero to its final value.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET (the top external MOSFET for the boost) just
before the inductor current reaches zero, preventing it
from reversing and going negative. Thus, the controller
operates in discontinuous operation.
Alternatively the TRACK/SS pins for buck channels 1 and 2
can be used to cause the start-up of V to track that of
another supply. Typically, this requires connecting to the
TRACK/SSpinanexternalresistordividerfromtheothersup-
ply to ground (see the Applications Information section).
OUT
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping, or Continuous Conduction)
(PLLIN/MODE Pin)
In forced continuous operation or clocked by an external
clock source to use the phase-locked loop (see the Fre-
quency Selection and Phase-Locked Loop section), the
inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
The LTC3859 can be enabled to enter high efficiency Burst
Modeoperation,constantfrequencypulse-skippingmode
or forced continuous conduction mode at low load cur-
rents.ToselectBurstModeoperation,tiethePLLIN/MODE
pin to ground. To select forced continuous operation, tie
rent is determined by the voltage on the I pin, just as
TH
in normal operation. In this mode, the efficiency at light
loads is lower than in Burst Mode operation. However,
continuous operation has the advantage of lower output
voltage ripple and less interference to audio circuitry. In
forced continuous mode, the output ripple is independent
of load current.
the PLLIN/MODE pin to INTV . To select pulse-skipping
CC
mode, tie the PLLIN/MODE pin to a DC voltage greater
than 1.2V and less than INTV – 1.3V.
CC
WhenacontrollerisenabledforBurstModeoperation, the
minimum peak current in the inductor is set to approxi-
mately 25% of the maximum sense voltage (30% for the
When the PLLIN/MODE pin is connected for pulse-skip-
ping mode, the LTC3859 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designedmaximumoutputcurrent. Atverylightloads, the
current comparator ICMP may remain tripped for several
cycles and force the external top MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
boost) even though the voltage on the I pin indicates a
TH
lower value. If the average inductor current is higher than
the load current, the error amplifier EA will decrease the
voltage on the I pin. When the I voltage drops below
TH
TH
0.425V, the internal sleep signal goes high (enabling sleep
mode) and both external MOSFETs are turned off. The I
TH
pin is then disconnected from the output of the EA and
parked at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3859 draws. If
one channel is in sleep mode and the other two are shut
down,theLTC3859drawsonly55ꢀAofquiescentcurrent.If
Mode operation.
3859f
15
LTC3859
OPERATION
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
Boost Controller Operation When V > V
IN OUT
When the input voltage to the boost channel rises above
its regulated V voltage, the controller can behave
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
OUT
differently depending on the mode, inductor current and
V
voltage. In forced continuous mode, the loop works
IN
to keep the top MOSFET on continuously once V rises
IN
above V . An internal charge pump delivers current
OUT
to the boost capacitor from the BST3 pin to maintain a
sufficiently high TG voltage. (The amount of current the
charge pump can deliver is characterized by two curves
in the Typical Performance Characteristics section.)
The switching frequency of the LTC3859’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
Inpulse-skippingmode, ifV isbetween100%and110%
IN
INTV ,orprogrammedthroughanexternalresistor.Tying
CC
of the regulated V
voltage, TG turns on if the inductor
OUT
FREQ to SGND selects 350kHz while tying FREQ to INTV
CC
current rises above a certain threshold and turns off if the
inductor current falls below this threshold. This threshold
current is set approximately to 3% of the programmed
selects 535kHz. Placing a resistor between FREQ and
SGND allows the frequency to be programmed between
50kHz and 900kHz.
maximum I current. If the controller is programmed to
LIM
Burst Mode operation under this same V window, then
A phase-locked loop (PLL) is available on the LTC3859
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3859’s phase detector adjusts the voltage (through an
internallowpassfilter)oftheVCOinputtoaligntheturn-on
of controller 1’s external top MOSFET to the rising edge of
the synchronizing signal. Thus, the turn-on of controller
2’s external top MOSFET is 180 degrees out of phase to
the rising edge of the external clock source.
IN
TG remains off regardless of the inductor current.
If V rises above 110% of the regulated V
voltage in
IN
OUT
any mode, the controller turns on TG regardless of the
inductor current. In Burst Mode operation, however, the
internal charge pump turns off if the entire chip is asleep
(the two buck channels are asleep or shut down). With
the charge pump off, there would be nothing to prevent
the boost capacitor from discharging, resulting in an
insufficient TG voltage needed to keep the top MOSFET
completely on. To prevent excessive power dissipation
across the body diode of the top MOSFET in this situation,
the chip can be switched over to forced continuous mode
to enable the charge pump, or a Schottky diode can also
be placed in parallel with the top MOSFET.
The VCO input voltage is pre-biased to the operating
frequency set by the FREQ pin before the external clock
is applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
pre-bias the loop filter allows the PLL to lock in rapidly
without deviating far from the desired frequency.
Boost Controller at Low SENSE Pin Common Voltage
The current comparator of the boost controller is powered
The typical capture range of the LTC3859’s phase-locked
loop is from approximately 55kHz to 1MHz, with a guar-
antee over all manufacturing variations to be between
75kHz and 850kHz. In other words, the LTC3859’s PLL
is guaranteed to lock to an external clock source whose
frequency is between 75kHz and 850kHz.
+
directly from the SENSE3 pin and can operate to voltages
as low as 2.5V. Since this is lower than the V
UVLO of
BIAS
the chip, V
can be connected to the output of the boost
BIAS
controller, as illustrated in the typical application circuit
in Figure 12. This allows the boost controller to handle
input voltage transients down to 2.5V while maintaining
+
output voltage regulation. If the SENSE3 rises back
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
above 2.5V, the SS3 pin will be released initiating a new
soft-start sequence.
3859f
16
LTC3859
OPERATION
Buck Controller Output Overvoltage Protection
Buck Foldback Current
The two buck channels have an overvoltage comparator
that guards against transient overshoots as well as other
moreseriousconditionsthatmayovervoltagetheiroutputs.
When the buck output voltage falls to less than 70% of
its nominal level, foldback current limiting is activated,
progressivelyloweringthepeakcurrentlimitinproportion
totheseverityoftheovercurrentorshort-circuitcondition.
Foldback current limiting is disabled during the soft-start
When the V
pin rises by more than 10% above its
FB1,2
regulation point of 0.800V, the top MOSFET is turned off
and the bottom MOSFET is turned on until the overvoltage
condition is cleared.
interval (as long as the V voltage is keeping up with
FB
the TRACK/SS1,2 voltage). There is no foldback current
limiting for the boost channel.
Channel 1 Power Good (PGOOD1)
Channel 1 has a PGOOD1 pin that is connected to an open
drain of an internal N-channel MOSFET. The MOSFET
THEORY AND BENEFITS OF 2-PHASE OPERATION
Why the need for 2-phase operation? Up until the 2-phase
family, constant-frequency dual switching regulators
operated both channels in phase (i.e., single-phase
operation). This means that both switches turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current flowing from the
input capacitor, requiring the use of more expensive input
capacitorsandincreasingbothEMIandlossesintheinput
capacitor and battery.
turns on and pulls the PGOOD1 pin low when the V pin
FB1
voltage is not within 10% of the 0.8V reference voltage
for the buck channel. The PGOOD1 pin is also pulled low
when the RUN1 pin is low (shut down). When the V
FB1
pin voltage is within the 10% requirement, the MOSFET
is turned off and the pin is allowed to be pulled up by an
external resistor to a source no greater than 6V.
Boost Overvoltage Indicator (OV3)
The OV3 pin is an overvoltage indicator that signals
whether the output voltage of the channel 3 boost control-
ler goes over its programmed regulated voltage. The pin
is connected to an open drain of an internal N-channel
MOSFET. The MOSFET turns on and pulls the OV3 pin low
With 2-phase operation, the two buck controllers of the
LTC3859 are operated 180 degrees out of phase. This
effectively interleaves the current pulses drawn by the
switches,greatlyreducingtheoverlaptimewheretheyadd
together. The result is a significant reduction in total RMS
input current, which in turn allows less expensive input
capacitors to be used, reduces shielding requirements for
EMI and improves real world operating efficiency.
when the V pin voltage is less than 110% of the 1.2V
FB3
reference voltage for the boost channel. The OV3 pin is
also pulled low when the RUN3 pin is low (shut down).
When the V pin voltage goes higher than 110% of the
FB3
1.2V reference, the MOSFET is turned off and the pin is
allowed to be pulled up by an external resistor to a source
no greater than 6V.
3859f
17
LTC3859
OPERATION
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
I
= 2.53A
I
= 1.55A
IN(MEAS) RMS
IN(MEAS)
RMS
3859 F01a
3859 F01b
(a)
(b)
Figure 1. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching
Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator
Allows Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency
Figure 1 compares the input waveforms for a representa-
tive single-phase dual switching regulator to the 2-phase
dual buck controllers of the LTC3859. An actual measure-
ment of the RMS input current under these conditions
shows that 2-phase operation dropped the input current
It can readily be seen that the advantages of 2-phase op-
eration are not just limited to a narrow operating range,
for most applications is that 2-phase operation will reduce
theinputcapacitorrequirementtothatforjustonechannel
operating at maximum current and 50% duty cycle.
from 2.53A
to 1.55A
. While this is an impressive
RMS
RMS
The schematic on the first page is a basic LTC3859 ap-
plication circuit. External component selection is driven
by the load requirement, and begins with the selection of
reduction in itself, remember that the power losses are
proportionaltoI ,meaningthattheactualpowerwasted
RMS2
is reduced by a factor of 2.66. The reduced input ripple
voltage also means less power is lost in the input power
path, which could include batteries, switches, trace/con-
nectorresistancesandprotectioncircuitry.Improvements
inbothconductedandradiatedEMIalsodirectlyaccrueas
a result of the reduced RMS input current and voltage.
R
and the inductor value. Next, the power MOSFETs
SENSE
are selected. Finally, C and C
are selected.
IN
OUT
3.0
SINGLE PHASE
DUAL CONTROLLER
2.5
2.0
1.5
1.0
0.5
0
Of course, the improvement afforded by 2-phase opera-
tion is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
2-PHASE
DUAL CONTROLLER
voltage V (Duty Cycle = V /V ). Figure 2 shows how
IN
OUT IN
theRMSinputcurrentvariesforsingle-phaseand2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
V
V
= 5V/3A
O1
O2
= 3.3V/3A
0
10
20
30
40
INPUT VOLTAGE (V)
3859 F02
Figure 2. RMS Input Current Comparison
3859f
18
LTC3859
APPLICATIONS INFORMATION
–
TheTypicalApplicationonthefirstpageisabasicLTC3859
application circuit. LTC3859 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption, and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
on the SENSE3 pin allows the current comparator to be
used in inductor DCR sensing.
Filter components mutual to the sense lines should be
placed close to the LTC3859, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 3). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 4b), sense resistor R1 should be placed
closetotheswitchingnode,topreventnoisefromcoupling
into sensitive small-signal nodes.
R
SENSE
(if R
is used) and inductor value. Next, the
SENSE
powerMOSFETsandSchottkydiodesareselected. Finally,
input and output capacitors are selected.
TO SENSE FILTER
NEXT TO THE CONTROLLER
+
–
SENSE and SENSE Pins
+
–
The SENSE and SENSE pins are the inputs to the current
comparators.
CURRENT FLOW
3859 F03
INDUCTOR OR R
SENSE
+
–
+
–
BuckControllers(SENSE1 /SENSE1 ,SENSE2 /SENSE2 ):
The common mode voltage range on these pins is 0V to
28V (absolute maximum), enabling the LTC3859 to regu-
late buck output voltages up to a nominal 24V (allowing
Figure 3. Sense Lines Placement with Inductor or Sense Resistor
Low Value Resistor Current Sensing
+
A typical sensing circuit using a discrete resistor is shown
margin for tolerances and transients). The SENSE pin
in Figure 4a. R
output current.
is chosen based on the required
is high impedance over the full common mode range,
drawing at most 1ꢀA. This high impedance allows the
current comparators to be used in inductor DCR sensing.
SENSE
The current comparators have a maximum threshold
of 50mV. The current comparator threshold
–
The impedance of the SENSE pin changes depending on
V
SENSE(MAX)
–
the common mode voltage. When SENSE is less than
sets the peak of the inductor current, yielding a maximum
INTV –0.5V, a small current of less than 1ꢀA flows out
CC
average output current, I
, equal to the peak value less
MAX
–
of the pin. When SENSE is above INTV +0.5V, a higher
CC
half the peak-to-peak ripple current, ΔI . To calculate the
L
current(≈700ꢀA)flowsintothepin.BetweenINTV –0.5V
CC
sense resistor value, use the equation:
andINTV +0.5V, thecurrenttransitionsfromthesmaller
CC
VSENSE(MAX)
current to the higher current.
RSENSE
=
ΔIL
+
–
IMAX
+
Boost Controller (SENSE3 /SENSE3 ): The common
mode input range for these pins is 2.5V to 38V, allowing
the boost converter to operate from inputs over this full
2
When using the buck controllers in very low dropout
conditions, the maximum output current level will be
reduced due to the internal compensation required to
meet stability criterion for buck regulators operating at
greater than 50% duty factor. A curve is provided in the
Typical Performance Characteristics section to estimate
thisreductioninpeakoutputcurrentleveldependingupon
the operating duty factor.
+
range. The SENSE3 pin also provides power to the cur-
rent comparator and draws about 170ꢀA during normal
operation (when not shut down or asleep in Burst Mode
operation). There is a small bias current of less than 1ꢀA
–
that flows out of the SENSE3 pin. This high impedance
3859f
19
LTC3859
APPLICATIONS INFORMATION
V
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult the
manufacturers’ data sheets for detailed information.
IN1,2
OUT3
(V
)
INTV
CC
BOOST
TG
LTC3859
R
SENSE
V
OUT1,2
IN3
SW
BG
(V
)
+
SENSE1,2
–
(SENSE3 )
CAP
PLACED NEAR SENSE PINS
–
SENSE1, 2
+
(SENSE3 )
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value
SGND
3859 F04a
is:
VSENSE(MAX)
4a. Using a Resistor to Sense Current
RSENSE(EQUIV)
=
ΔIL
V
IN1,2
OUT3
IMAX
+
(V
)
INTV
2
CC
To ensure that the application will deliver full load cur-
BOOST
TG
rent over the full operating temperature range, determine
INDUCTOR
DCR
R
, keeping in mind that the maximum current
SENSE(EQUIV)
LTC3859
L
V
OUT1,2
IN3
SW
BG
sense threshold (V
at 50mV.
) for the LTC3859 is fixed
(V
)
SENSE(MAX)
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of resistance, which is approximately 0.4%/°C.
R1
R2
+
SENSE1, 2
–
(SENSE3 )
C1*
–
SENSE1, 2
+
(SENSE3 )
A conservative value for T
is 100°C.
SGND
L(MAX)
3859 F04b
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
(R1||R2) • C1 = L/DCR
R = DCR(R2/(R1+R2))
SENSE(EQ)
*PLACE C1 NEAR SENSE PINS
RSENSE(EQUIV)
4b. Using the Inductor DCR to Sense Current
Figure 4. Current Sensing Methods
RD =
DCRMAX atTL(MAX)
C1 is usually selected to be in the range of 0.1ꢀF to 0.47ꢀF.
This forces R1||R2 to around 2k, reducing error that might
Inductor DCR Sensing
+
have been caused by the SENSE pin’s 1ꢀA current.
Forapplicationsrequiringthehighestpossibleefficiencyat
high load currents, the LTC3859 is capable of sensing the
voltagedropacrosstheinductorDCR,asshowninFigure4b.
The DCR of the inductor represents the small amount of
DC winding resistance of the copper, which can be less
than 1mꢁ for today’s low value, high current inductors.
In a high current application requiring such an inductor,
conductionlossthroughasenseresistorwouldcostseveral
points of efficiency compared to DCR sensing.
The equivalent resistance R1||R2 is scaled to the room
temperature inductance and maximum DCR:
L
R1PR2=
(DCR at 20°C)•C1
The sense resistor values are:
R1•RD
1−RD
R1PR2
RD
R1=
; R2=
3859f
20
LTC3859
APPLICATIONS INFORMATION
ThemaximumpowerlossinR1isrelatedtodutycycle.For
the buck controllers, the maximum power loss will occur
in continuous mode at the maximum input voltage:
Accepting larger values of ΔI allows the use of low
L
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ΔI = 0.3(I
). The maximum
L
MAX
(VIN(MAX) − VOUT )• VOUT
ΔI occurs at the maximum input voltage for the bucks
PLOSS R1=
L
R1
and V = 1/2•V
for the boost.
OUT
IN
For the boost controller, the maximum power loss in R1
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit (30% for the boost) determined
will occur in continuous mode at V = 1/2•V
:
IN
OUT
(VOUT(MAX) − V )• V
IN
IN
PLOSS R1=
R1
by R
. Lower inductor values (higher ΔI ) will cause
SENSE
L
this to occur at lower load currents, which can cause a dip
inefficiencyintheupperrangeoflowcurrentoperation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to decrease.
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
totheextraswitchinglossesincurredthroughR1.However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcingtheuseofmoreexpensiveferriteormolypermalloy
cores. Actual core loss is independent of core size for a
fixedinductorvalue,butitisverydependentoninductance
selected. As inductance increases, core losses go down.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔI decreases with higher
L
inductance or frequency. For the buck controllers, ΔI
L
increases with higher V :
IN
Power MOSFET and Schottky Diode
(Optional) Selection
⎛
⎞
VOUT
1
ΔIL =
VOUT 1−
⎜
⎝
⎟
(f)(L)
V
⎠
IN
Two external power MOSFETs must be selected for each
controller in the LTC3859: one N-channel MOSFET for the
top switch (main switch for the buck, synchronous for the
boost), and one N-channel MOSFET for the bottom switch
(main switch for the boost, synchronous for the buck).
For the boost controller, the inductor ripple current ΔI
L
increases with higher V
:
OUT
⎛
⎞
V
VOUT
1
IN
ΔIL =
V
1−
IN
⎜
⎟
(f)(L)
⎝
⎠
3859f
21
LTC3859
APPLICATIONS INFORMATION
V
− V V
2
(
)
Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.
OUT
IN OUT
2
CC
PMAIN_BOOST
=
I
•
(
)
OUT(MAX)
This voltage is typically 5.4V during start-up (see EXTV
CC
V
IN
Pin Connection). Consequently, logic-level threshold
2
⎛
⎞
I
⎛
⎞
V
MOSFETs must be used in most applications. Pay close
OUT(MAX)
OUT
1+ δ R
+
)
•
(
(
)
⎜
⎟
DS(ON)
⎜
⎟
attention to the BV
specification for the MOSFETs as
V
2
DSS
⎝
⎠
⎝
⎠
IN
well; many of the logic level MOSFETs are limited to 30V
⎡
⎤
1
1
or less.
R
C
•
+
(f)
(
)
⎢
⎥
⎦
DR
MILLER
V
INTVCC − VTHMIN VTHMIN
⎣
Selection criteria for the power MOSFETs include the
2
V
on-resistance R
, Miller capacitance C
, input
DS(ON)
MILLER
IN
PSYNC_BOOST
=
I
1+ δ R
DS(ON)
(
)
(
)
OUT(MAX)
voltage and maximum output current. Miller capacitance,
, can be approximated from the gate charge curve
VOUT
C
MILLER
usually provided on the MOSFET manufacturers’ data
sheet. C is equal to the increase in gate charge
where ζ is the temperature dependency of R
and
DS(ON)
RDR (approximately 2ꢁ) is the effective driver resistance
MILLER
along the horizontal axis while the curve is approximately
at the MOSFET’s Miller threshold voltage. V
typical MOSFET minimum threshold voltage.
is the
THMIN
flat divided by the specified change in V . This result is
DS
then multiplied by the ratio of the application applied V
2
DS
Both MOSFETs have I R losses while the main N-channel
equations for the buck and boost controllers include an
additional term for transition losses, which are highest at
highinputvoltagesforthebucksandlowinputvoltagesfor
to the gate charge curve specified V . When the IC is
DS
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
VOUT
the boost. For V < 20V (high V for the boost) the high
IN
IN
Buck Main Switch Duty Cycle =
currentefficiencygenerallyimproveswithlargerMOSFETs,
V
IN
while for V > 20V (low V for the boost) the transition
IN
IN
V − VOUT
IN
Buck Sync Switch Duty Cycle =
Boost Main Switch Duty Cycle=
Boost Sync Switch Duty Cycle=
losses rapidly increase to the point that the use of a higher
V
IN
R
devicewithlowerC actuallyprovideshigher
DS(ON)
MILLER
VOUT − V
efficiency. The synchronous MOSFET losses for the buck
controllers are greatest at high input voltage when the top
switch duty factor is low or during a short-circuit when the
synchronous switch is on close to 100% of the period. The
synchronous MOSFET losses for the boost controller are
greatestwhentheinputvoltageapproachestheoutputvolt-
age or during an overvoltage event when the synchronous
switch is on 100% of the period.
IN
VOUT
V
IN
VOUT
The MOSFET power dissipations at maximum output
current are given by:
2
VOUT
PMAIN_BUCK
=
I
(
1+ δ R
+
(
)
)
The term (1+ ζ) is generally given for a MOSFET in the
OUT(MAX)
DS(ON)
V
IN
form of a normalized R
vs Temperature curve, but
DS(ON)
I
⎛
⎜
⎞
ζ = 0.005/°C can be used as an approximation for low
OUT(MAX)
(V )2
(RDR)(CMILLER)•
IN
⎟
voltage MOSFETs.
2
⎝
⎠
The optional Schottky diodes D4, D5, and D6 shown in
Figure 13 conduct during the dead-time between the
conduction of the two power MOSFETs. This prevents
the body diode of the synchronous MOSFET from turning
on, storing charge during the dead-time and requiring a
reverse recovery period that could cost as much as 3%
⎡
⎢
⎤
⎥
⎦
1
1
+
(f)
V
INTVCC − VTHMIN VTHMIN
⎣
2
V − VOUT
IN
PSYNC_BUCK
=
I
1+ δ R
(
)
(
)
OUT(MAX)
DS(ON)
V
IN
in efficiency at high V . A 1A to 3A Schottky is generally
IN
3859f
22
LTC3859
APPLICATIONS INFORMATION
a good compromise for both regions of operation due to
the relatively small average current. Larger diodes result
in additional transition losses due to their larger junction
capacitance.
Capacitors are now available with low ESR and high ripple
current ratings such as OS-CON and POSCAP.
Buck C , C
Selection
IN OUT
TheselectionofC forthetwobuckcontrollersissimplified
IN
Boost C , C
Selection
IN OUT
by the 2-phase architecture and its impact on the worst-
case RMS current drawn through the input network (bat-
tery/fuse/capacitor). It can be shown that the worst-case
capacitor RMS current occurs when only one controller
The input ripple current in a boost converter is relatively
low (compared with the output ripple current), because
this current is continuous. The boost input capacitor C
voltage rating should comfortably exceed the maximum
inputvoltage.Althoughceramiccapacitorscanberelatively
tolerant of overvoltage conditions, aluminum electrolytic
capacitorsarenot.Besuretocharacterizetheinputvoltage
for any possible overvoltage transients that could apply
excess stress to the input capacitors.
IN
is operating. The controller with the highest (V )(I
)
OUT OUT
product needs to be used in the formula shown in Equa-
tion(1)todeterminethemaximumRMScapacitorcurrent
requirement. Increasing the output current drawn from
the other controller will actually decrease the input RMS
ripple current from its maximum value. The out-of-phase
technique typically reduces the input capacitor’s RMS
ripple current by a factor of 30% to 70% when compared
to a single phase power supply solution.
ThevalueofC isafunctionofthesourceimpedance, and
IN
ingeneral,thehigherthesourceimpedance,thehigherthe
required input capacitance. The required amount of input
capacitance is also greatly affected by the duty cycle. High
output current applications that also experience high duty
cycles can place great demands on the input supply, both
in terms of DC current and ripple current.
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle (V )/(V ). To prevent
OUT
IN
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
Inaboostconverter,theoutputhasadiscontinuouscurrent,
1/2
IMAX
so C
must be capable of reducing the output voltage
OUT
⎡
⎤
CIN Required IRMS
≈
V
OUT )(
V − V
IN OUT
(
)
⎣
⎦
ripple.TheeffectsofESR(equivalentseriesresistance)and
the bulk capacitance must be considered when choosing
the right capacitor for a given output ripple voltage. The
steady ripple due to charging and discharging the bulk
capacitance is given by:
(1)
V
IN
This formula has a maximum at V = 2V , where I
IN
OUT
RMS
= I /2. This simple worst-case condition is commonly
OUT
usedfordesignbecauseevensignificantdeviationsdonot
offermuchrelief.Notethatcapacitormanufacturers’ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3859, ceramic capacitors
IOUT(MAX) • VOUT − V
(
)
IN(MIN)
Ripple=
where C
V
COUT • VOUT • f
is the output filter capacitor.
OUT
The steady ripple due to the voltage drop across the ESR
is given by:
can also be used for C . Always consult the manufacturer
IN
ΔV
= I
• ESR
ESR
L(MAX)
if there is any question.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
ThebenefitoftheLTC38592-phaseoperationcanbecalcu-
lated by using Equation (1) for the higher power controller
and then calculating the loss that would have resulted if
both controller channels switched on at the same time.
3859f
23
LTC3859
APPLICATIONS INFORMATION
V
OUT
The total RMS power lost is lower when both controllers
are operating due to the reduced overlap of current pulses
required through the input capacitor’s ESR. This is why
the input capacitor’s requirement calculated above for the
worst-case controller is adequate for the dual controller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benefit of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The drains of the top MOSFETs should be placed within
R
R
C
FF
B
A
1/3 LTC3859
V
FB
3859 F05
Figure 5. Setting Output Voltage
To improve the frequency response, a feedforward ca-
pacitor, C , may be used. Great care should be taken to
FF
route the V line away from noise sources, such as the
FB
inductor or the SW line.
1cm of each other and share a common C (s). Separat-
IN
ing the drains and C may produce undesirable voltage
IN
Tracking and Soft-Start
and current resonances at V .
IN
(TRACK/SS1, TRACK/SS2, SS3 Pins)
A small (0.1ꢀF to 1ꢀF) bypass capacitor between the chip
The start-up of each V
is controlled by the voltage on
OUT
V pin and ground, placed close to the LTC3859, is also
IN
the respective TRACK/SS pin (TRACK/SS1 for channel 1,
TRACK/SS2 for channel 2, SS3 for channel 3). When the
voltage on the TRACK/SS pin is less than the internal
0.8V reference (1.2V reference for the boost channel), the
suggested. A small (1ꢁ to 10ꢁ) resistor placed between
C (C1)andtheV pinprovidesfurtherisolationbetween
IN
IN
the two channels.
The selection of C
is driven by the effective series
LTC3859regulatestheV pinvoltagetothevoltageonthe
OUT
FB
resistance (ESR). Typically, once the ESR requirement
TRACK/SS pin instead of the internal reference. Likewise,
is satisfied, the capacitance is adequate for filtering. The
the TRACK/SS pin for the buck channels can be used to
output ripple (ΔV ) is approximated by:
program an external soft-start function or to allow V
OUT
OUT
to track another supply during start-up.
⎛
⎞
1
ΔVOUT ≈ ΔIL ESR+
⎜
⎝
⎟
1/3 LTC3859
TRACK/SS
8fCOUT
⎠
C
where f is the operating frequency, C
is the output
SS
OUT
SGND
capacitance and ΔI is the ripple current in the inductor.
L
3859 F06
The output ripple is highest at maximum input voltage
since ΔI increases with input voltage.
Figure 6. Using the TRACK/SS Pin to Program Soft-Start
L
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 6.
An internal 1ꢀA current source charges the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
Setting Output Voltage
The LTC3859 output voltages are each set by an external
feedbackresistordividercarefullyplacedacrosstheoutput,
as shown in Figure 5. The regulated output voltages are
determined by:
The LTC3859 will regulate the V pin (and hence V
)
FB
OUT
according to the voltage on the TRACK/SS pin, allowing
⎛
⎜
⎝
⎞
V
to rise smoothly from 0V to its final regulated value.
RB
RA
OUT
VOUT, BUCK = 0.8V 1+
⎟
The total soft-start time will be approximately:
⎠
0.8V
1µ A
tSS_BUCK =CSS
•
⎛
⎜
⎝
⎞
RB
RA
VOUT, BOOST =1.2V 1+
⎟
⎠
1.2V
1µ A
tSS_BOOST =CSS
•
3859f
24
LTC3859
APPLICATIONS INFORMATION
V
V
V
X(MASTER)
X(MASTER)
V
OUT(SLAVE)
OUT(SLAVE)
3859 F07a
TIME
3859 F07b
TIME
7a. Coincident Tracking
7b. Radiometric Tracking
Figure 7. Two Different Modes of Output Voltage Tracking
V
OUT
LTC3859
R
at the INTV pin from either the V
supply pin or the
B
A
CC
BIAS
EXTV pin depending on the connection of the EXTV
V
FB1,2
CC
CC
pin. INTV powers the gate drivers and much of the
R
CC
V
X
LTC3859’sinternalcircuitry.TheV
LDOandtheEXTV
BIAS
CC
LDO regulate INTV to 5.4V. Each of these can supply a
CC
R
R
TRACKB
TRACKA
peak current of 50mA and must be bypassed to ground
with a minimum of 4.7ꢀF ceramic capacitor. No matter
what type of bulk capacitor is used, an additional 1ꢀF
TRACK/SS1,2
ceramic capacitor placed directly adjacent to the INTV
CC
3859 F08
andPGNDICpinsishighlyrecommended.Goodbypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
Figure 8. Using the TRACK/SS Pin for Tracking
Alternatively, the TRACK/SS1 and TRACK/SS2 pins for the
twobuckcontrollerscanbeusedtotracktwo(ormore)sup-
plies during start-up, as shown qualitatively in Figures 7a
and 7b. To do this, a resistor divider should be connected
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3859 to be
from the master supply (V ) to the TRACK/SS pin of the
X
slave supply (V ), as shown in Figure 8. During start-up
exceeded. The INTV current, which is dominated by the
OUT
CC
V
will track V according to the ratio set by the resis-
gate charge current, may be supplied by either the V
OUT
X
BIAS
tor divider:
LDO or the EXTV LDO. When the voltage on the EXTV
CC
CC
pin is less than 4.7V, the V
LDO is enabled. Power
RTRACKA +RTRACKB
RA +RB
VX
RA
BIAS
=
•
dissipation for the IC in this case is highest and is equal
to V • I . The gate charge current is dependent
VOUT RTRACKA
BIAS INTVCC
on operating frequency as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 3 of the
For coincident tracking (V
= V during start-up),
X
OUT
R = R
A
TRACKA
TRACKB
ElectricalCharacteristics.Forexample,theLTC3859INTV
R = R
B
CC
current is limited to less than 40mA from a 40V supply
INTV Regulators
when not using the EXTV supply at a 70°C ambient
CC
CC
temperature in the QFN package:
The LTC3859 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power
T = 70°C + (40mA)(40V)(34°C/W) = 125°C
J
3859f
25
LTC3859
APPLICATIONS INFORMATION
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (PLLIN/MODE
2. EXTV connected directly to the output voltage of one
CC
of the buck regulators. This is the normal connection
for a 5V to 14V regulator and provides the highest ef-
ficiency.
= INTV ) at maximum V .
CC
IN
When the voltage applied to EXTV rises above 4.7V, the
3. EXTV connected to an external supply. If an external
CC
CC
V
LDO is turned off and the EXTV LDO is enabled.
supply is available in the 5V to 14V range, it may be
BIAS
CC
TheEXTV LDOremainsonaslongasthevoltageapplied
usedtopowerEXTV providingitiscompatiblewiththe
CC
CC
to EXTV remains above 4.5V. The EXTV LDO attempts
MOSFET gate drive requirements. Ensure that EXTV
CC
CC
CC
to regulate the INTV voltage to 5.4V, so while EXTV
< V .
CC
CC
CC
CC
IN
is less than 5.4V, the LDO is in dropout and the INTV
4. EXTV connected to an output-derived boost network
CC
voltage is approximately equal to EXTV . When EXTV
CC
off one of the buck regulators. For 3.3V and other low
is greater than 5.4V, up to an absolute maximum of 14V,
INTV is regulated to 5.4V.
voltage buck regulators, efficiency gains can still be
CC
realized by connecting EXTV to an output-derived
CC
Using the EXTV LDO allows the MOSFET driver and
voltage that has been boosted to greater than 4.7V. This
CC
control power to be derived from one of the LTC3859’s
can be done with the capacitive charge pump shown in
switching regulator outputs (4.7V ≤ V
≤ 14V) dur-
Figure 9. Ensure that EXTV < V .
OUT
CC
IN
ing normal operation and from the V
LDO when the
BIAS
output is out of regulation (e.g., startup, short-circuit). If
more current is required through the EXTV LDO than
CC
V
IN1,2
C1
is specified, an external Schottky diode can be added
BAT85
BAT85
BAT85
LTC3859
between the EXTV and INTV pins. In this case, do
CC
CC
not apply more than 6V to the EXTV pin and make sure
CC
MTOP
MBOT
than EXTV ≤ V
.
CC
BIAS
TG
SW
BG
EXTV
CC
Significant efficiency and thermal gains can be realized
by powering INTV from the buck output, since the V
R
L
SENSE
V
OUT1,2
CC
IN
current resulting from the driver and control currents will
bescaledbyafactorof(DutyCycle)/(SwitcherEfficiency).
For 5V to 14V regulator outputs, this means connecting
PGND
the EXTV pin directly to V . Tying the EXTV pin to
CC
OUT
CC
3859 F09
a 8.5V supply reduces the junction temperature in the
Figure 9. Capacitive Charge Pump for EXTVCC
previous example from 125°C to:
Topside MOSFET Driver Supply (C , D )
T = 70°C + (40mA)(8.5V)(34°C/W) = 82°C
J
B
B
External bootstrap capacitors C connected to the BOOST
However, for 3.3V and other low voltage outputs, addi-
B
pinssupplythegatedrivevoltagesforthetopsideMOSFETs.
tional circuitry is required to derive INTV power from
CC
Capacitor C in the Functional Diagram is charged though
the output.
B
external diode D from INTV when the SW pin is low.
B
CC
The following list summarizes the four possible connec-
When one of the topside MOSFETs is to be turned on, the
tions for EXTV :
CC
driver places the C voltage across the gate-source of the
B
1. EXTV left open (or grounded). This will cause INTV
desired MOSFET. This enhances the MOSFET and turns
CC
CC
to be powered from the internal 5.4V regulator result-
ing in an efficiency penalty of up to 10% at high input
voltages.
on the topside switch. The switch node voltage, SW, rises
to V for the buck channels (V
for the boost channel)
IN
OUT
and the BOOST pin follows. With the topside MOSFET
3859f
26
LTC3859
APPLICATIONS INFORMATION
on, the boost voltage is above the input supply: V
Fault Conditions: Buck Overvoltage Protection
BOOST
(Crowbar)
= V + V
(V
= V
+ V
for the boost
IN
INTVCC BOOST
OUT
INTVCC
controller). The value of the boost capacitor C needs to
B
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the one of the buck
regulators rises much higher than nominal levels. The
crowbar causes huge currents to flow, that blow the fuse
to protect against a shorted top MOSFET if the short oc-
curs while the controller is operating.
be 100 times that of the total input capacitance of the
topsideMOSFET(s).Thereversebreakdownoftheexternal
Schottky diode must be greater than V
channels and V
for the buck
IN(MAX)
for the boost channel.
OUT(MAX)
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
improved. If there is no change in input current, then there
is no change in efficiency.
A comparator monitors the buck output for overvoltage
conditions. The comparator detects faults greater than
10% above the nominal output voltage. When this condi-
tion is sensed, the top MOSFET of the buck controller is
turned off and the bottom MOSFET is turned on until the
overvoltage condition is cleared. The bottom MOSFET
remains on continuously for as long as the overvoltage
The topside MOSFET driver for the boost channel includes
an internal charge pump that delivers current to the boot-
strap capacitor from the BOOST3 pin. This charge current
maintainsthebiasvoltagerequiredtokeepthetopMOSFET
on continuously during dropout/overvoltage conditions.
The Schottky diode selected for the boost topside driver
shouldhaveareverseleakagelessthantheavailableoutput
current the charge pump can supply under all operating
conditions. Curves displaying the available charge pump
current under different operating conditions can be found
in the Typical Performance Characteristics section.
condition persists; if V
returns to a safe level, normal
OUT
operation automatically resumes.
A shorted top MOSFET for the buck channel will result in
a high current condition which will open the system fuse.
The switching regulator will regulate properly with a leaky
top MOSFET by altering the duty cycle to accommodate
the leakage.
Fault Conditions: Over Temperature Protection
Fault Conditions: Buck Current Limit and Current
Foldback
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on chip
The LTC3859 includes current foldback for the buck
channels to help limit load current when the output is
shorted to ground. If the buck output falls below 70% of
its nominal output level, then the maximum sense volt-
age is progressively lowered from 100% to 40% of its
maximum selected value. Under short-circuit conditions
with very low duty cycles, the buck channel will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
(such as INTV short to ground), the over temperature
CC
shutdown circuitry will shut down the LTC3859. When the
junction temperature exceeds approximately 170°C, the
overtemperaturecircuitrydisablestheINTV LDO, caus-
CC
ing the INTV supply to collapse and effectively shutting
CC
down the entire LTC3859 chip. Once the junction tempera-
ture drops back to approximately 155°C, the INTV LDO
CC
turns back on. Long term overstress (T > 125°C) should
J
be avoided as it can degrade the performance or shorten
the life of the part.
on-timet
oftheLTC3859(≈95ns),theinputvoltage
ON(MIN)
and inductor value:
Phase-Locked Loop and Frequency Synchronization
The LTC3859 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked to
ΔI = t
(V /L)
ON(MIN) IN
L(SC)
The resulting average short-circuit current is:
1
2
ISC = 40%•ILIM(MAX) − ΔIL(SC)
the rising edge of an external clock signal applied to the
3859f
27
LTC3859
APPLICATIONS INFORMATION
1000
900
800
700
600
500
400
300
200
100
at a frequency correspond to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase-lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
Table 1 summarizes the different states in which the FREQ
pin can be used.
0
15 25 35 45 55 65 75 85 95 105 115 125
Table 1
FREQ PIN RESISTOR (kꢁ)
FREQ PIN
PLLIN/MODE PIN
DC Voltage
FREQUENCY
350kHz
3859 F10
0V
Figure 10. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
INTV
DC Voltage
535kHz
CC
Resistor to SGND
Any of the Above
DC Voltage
50kHz to 900kHz
PLLIN/MODEpin.Theturn-onofcontroller2’stopMOSFET
is thus 180 degrees out of phase with the external clock.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
External Clock
Phase-Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time t is the smallest time duration
ON(MIN)
that the LTC3859 is capable of turning on the top MOSFET
(bottomMOSFETfortheboostcontroller).Itisdetermined
by internal timing delays and the gate charge required to
turn on the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
If the external clock frequency is greater than the internal
oscillator’sfrequency,f ,thencurrentissourcedcontinu-
OSC
ously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than f
,
OSC
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
taken to ensure that
VOUT
V (f)
tON(MIN)_BUCK
<
IN
VOUT − V
IN
tON(MIN)_BOOST
<
VOUT(f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
Note that the LTC3859 can only be synchronized to an
external clock whose frequency is within range of the
LTC3859’sinternalVCO,whichisnominally55kHzto1MHz.
This is guaranteed to be between 75kHz and 850kHz.
The minimum on-time for the LTC3859 is approximately
95ns for the bucks and 120ns for the boost. However, as
the peak sense voltage decreases the minimum on-time
gradually increases up to about 130ns. This is of particu-
lar concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
Typically,theexternalclock(onPLLIN/MODEpin)inputhigh
threshold is 1.6V, while the input low threshold is 1.2V.
Rapidphase-lockingcanbeachievedbyusingtheFREQpin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
3859f
28
LTC3859
APPLICATIONS INFORMATION
Efficiency Considerations
R
, but is “chopped” between the topside MOSFET
SENSE
andthesynchronousMOSFET.IfthetwoMOSFETshave
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
approximately the same R
, then the resistance
DS(ON)
of one MOSFET can simply be summed with the resis-
2
tances of L, R
and ESR to obtain I R losses. For
DS(ON)
SENSE
example, if each R
= 30mꢁ, R = 50mꢁ, R
L SENSE
= 10mꢁ and R
= 40mꢁ (sum of both input and
ESR
output capacitance losses), then the total resistance
is 130mꢁ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Efficiency varies as the inverse square of V
for the
OUT
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
losses in LTC3859 circuits: 1) IC V current, 2) INTV
IN
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET
transition losses.
1. The V current is the DC supply current given in the
IN
4. Transition losses apply only to the top MOSFET(s) (bot-
tomMOSFETfortheboost),andbecomesignificantonly
when operating at high input voltages (typically 15V or
greater). Transition losses can be estimated from:
ElectricalCharacteristicstable,whichexcludesMOSFET
driverandcontrolcurrents. V currenttypicallyresults
IN
in a small (<0.1%) loss.
2. INTV current is the sum of the MOSFET driver and
2
CC
Transition Loss = (1.7)V • I
• C
• f
IN
O(MAX)
RSS
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% efficiency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistancelossescanbeminimizedbymakingsurethat
from INTV to ground. The resulting dQ/dt is a current
CC
out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
C has adequate charge storage and very low ESR at
IN
= f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
the switching frequency. A 25W supply will typically
require a minimum of 20ꢀF to 40ꢀF of capacitance
having a maximum of 20mꢁ to 50mꢁ of ESR. The
LTC38592-phasearchitecturetypicallyhalvesthisinput
capacitance requirement over competing solutions.
Other losses including Schottky conduction losses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.
the topside and bottom side MOSFETs.
SupplyingINTV fromanoutput-derivedsourcepower
CC
through EXTV will scale the V current required
CC
IN
for the driver and control circuits by a factor of (Duty
Cycle)/(Efficiency). Forexample, ina20Vto5Vapplica-
tion, 10mA of INTV current results in approximately
CC
2.5mAofV current.Thisreducesthemid-currentloss
IN
from 10% or more (if the driver was powered directly
from V ) to only a few percent.
Checking Transient Response
IN
2
3. I R losses are predicted from the DC resistances of the
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
fuse (if used), MOSFET, inductor, current sense resis-
tor, and input and output capacitor ESR. In continuous
mode the average output current flows through L and
load current. When a load step occurs, V
shifts by an
OUT
3859f
29
LTC3859
APPLICATIONS INFORMATION
The gain of the loop will be increased by increasing RC
and the bandwidth of the loop will be increased by de-
creasing CC. If RC is increased by the same factor that
CC is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loopsystemandwilldemonstratetheactualoverall
supply performance.
amount equal to ΔI
, where ESR is the effective
LOAD
LOAD(ESR)
series resistance of C . ΔI
also begins to charge or
OUT
discharge C
generating the feedback error signal that
OUT
forces the regulator to adapt to the current change and
return V to its steady-state value. During this recovery
OUT
time V
can be monitored for excessive overshoot or
OUT
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the I pin not only allows
TH
A second, more severe transient is caused by switching
in loads with large (>1ꢀF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
optimization of control loop behavior, but it also provides
a DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
to C
is greater than 1:50, the switch rise time
LOAD
OUT
estimated by examining the rise time at the pin. The I
TH
should be controlled so that the load rise time is limited
to approximately 25 • C . Thus a 10ꢀF capacitor would
external components shown in Figure 16 will provide an
LOAD
adequate starting point for most applications.
require a 250ꢀs rise time, limiting the charging current
to about 200mA.
The I series RC-CC filter sets the dominant pole-zero
TH
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1ꢀs to 10ꢀs will
Buck Design Example
As a design example for one of the buck channels channel,
assume V = 12V
, V = 22V
, V
= 3.3V,
IN
(NOMINAL) IN
(MAX) OUT
= 50mV, and f = 350kHz.
I
= 6A, V
MAX
SENSE(MAX)
Theinductancevalueischosenfirstbasedona30%ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the FREQ pin
to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
produce output voltage and I pin waveforms that will
TH
give a sense of the overall loop stability without breaking
the feedback loop.
⎛
⎞
VOUT
(f)(L)
VOUT
V
IN(NOMINAL)
Placing a power MOSFET directly across the output
capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better to
ΔIL =
1−
⎜
⎟
⎝
⎠
A 3.9ꢀH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 6.88A. Increasing the ripple
current will also help ensure that the minimum on-time
of 95ns is not violated. The minimum on-time occurs at
look at the I pin signal which is in the feedback loop and
TH
maximum V :
IN
is the filtered and compensated control loop response.
VOUT
IN(MAX)(f) 22V(350kHz)
3.3V
tON(MIN)
=
=
= 429ns
V
3859f
30
LTC3859
APPLICATIONS INFORMATION
The R
resistor value can be calculated by using the
PC Board Layout Checklist
SENSE
minimum value for the maximum current sense threshold
(43mV):
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layoutdiagramofFigure11.Figure12illustratesthecurrent
waveforms present in the various branches of the 2-phase
synchronous buck regulators operating in the continuous
mode. Check the following in your layout:
43mV
6.88A
RSENSE
≤
= 0.006Ω
Choosing 1% resistors: R = 25k and R = 80.6k yields
A
B
an output voltage of 3.33V.
ThepowerdissipationonthetopsideMOSFETcanbeeasily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
results in: R
= 0.035ꢁ/0.022ꢁ, C
= 215pF. At
connection at C ? Do not attempt to split the input
DS(ON)
MILLER
IN
maximum input voltage with T(estimated) = 50°C:
decoupling for the two channels as it can cause a large
resonant loop.
3.3V
22V
PMAIN
=
(6A)2 1+(0.005)(50° C − 25° C)
{
}
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
5A
(0.035Ω)+(22V)26 (2.5Ω)(215pF)•
of C
must return to the combined C
(–) ter-
2
INTVCC
OUT
minals. The path formed by the top N-channel MOSFET,
1
1
⎧
⎨
⎩
⎫
⎬
⎭
+
(350kHz)= 433mW
Schottky diode and the C capacitor should have short
IN
5V − 2.3V 2.3V
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
A short-circuit to ground will result in a folded back cur-
rent of:
20mV 1 95ns(22V)
⎧
⎫
⎬
⎭
ISC =
−
= 3.07A
⎨
⎩
0.006Ω 2
3.9µH
3. Do the LTC3859 V pins’ resistive dividers connect to
FB
with a typical value of R
and ζ = (0.005/°C)(25°C)
the (+) terminals of C ? The resistive divider must be
DS(ON)
OUT
= 0.125. The resulting power dissipated in the bottom
connected between the (+) terminal of C
and signal
OUT
MOSFET is:
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
PSYNC =(2.23A)2(1.125)(0.022Ω)= 233mW
which is less than under full-load conditions.
–
+
4.Are the SENSE and SENSE leads routed together with
minimumPCtracespacing?Thefiltercapacitorbetween
The input capacitor to the buck regulator C is chosen
IN
for an RMS current rating of at least 3A at temperature
+
–
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
assuming only this channel is on. C
is chosen with an
OUT
ESR of 0.02ꢁ for low output ripple. The output ripple in
continuous mode will be highest at the maximum input
voltage. The output voltage ripple due to ESR is approxi-
mately:
5. Is the INTV decoupling capacitor connected close
CC
to the IC, between the INTV and the power ground
CC
pins? This capacitor carries the MOSFET drivers’ cur-
V
= R (ΔI ) = 0.02ꢁ(1.75A) = 35mV
ESR L P-P
ORIPPLE
rent peaks. An additional 1ꢀF ceramic capacitor placed
immediatelynexttotheINTV andPGNDpinscanhelp
CC
improve noise performance substantially.
3859f
31
LTC3859
APPLICATIONS INFORMATION
6. Keep the switching nodes (SW1, SW2, SW3), top gate
nodes (TG1, TG2, TG3), and boost nodes (BOOST1,
BOOST2, BOOST3) away from sensitive small-signal
nodes, especially from the opposites channel’s voltage
and current sensing feedback pins. All of these nodes
have very large and fast moving signals and therefore
should be kept on the output side of the LTC3859 and
occupy minimum PC trace area.
A particularly difficult region of operation is when one
controller channel is nearing its current comparator trip
pointwhentheotherchannelisturningonitstopMOSFET.
This occurs around 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
Reduce V from its nominal level to verify operation
IN
of the regulator in dropout. Check the operation of the
7. Useamodifiedstargroundtechnique:alowimpedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
undervoltage lockout circuit by further lowering V while
IN
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
with tie-ins for the bottom of the INTV decoupling
CC
capacitor, the bottom of the voltage feedback resistive
divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
totheinternaloscillatorandprobetheactualoutputvoltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequencyofoperationshouldbemaintainedovertheinput
voltage range down to dropout and until the output load
drops below the low current operation threshold—typi-
cally 25% of the maximum designed current level in Burst
Mode operation.
for inductive coupling between C , Schottky and the top
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawell-designed,lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regula-
tor bandwidth optimization is not required. Only after
each controller is checked for its individual performance
should both controllers be turned on at the same time.
3859f
32
LTC3859
APPLICATIONS INFORMATION
SW1
L1
R
SENSE1
V
OUT1
D1
C
R
L1
OUT1
V
IN
R
IN
C
IN
SW2
L2
R
SENSE2
V
OUT2
D2
C
R
L2
OUT2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
3859 F11
Figure 11. Branch Current Waveforms for Bucks
3859f
33
LTC3859
TYPICAL APPLICATIONS
V
OUT1
R
B1
OPT
R
A1
LTC3859
SENSE1
357k
68.1k
–
+
V
FB1
C1
C
ITH1A
1nF
100pF
R
SENSE1
C
ITH1
ITH1
15k
100k
1500pF
C1
I
PGOOD1
TG1
TH1
10ꢀF
C
SS1
L1
4.9ꢀH
R
SENSE1
6mΩ
MTOP1
MBOT1
0.1ꢀF
V
OUT1
5V
5A
TRACK/SS1
FREQ
SW1
C
B1
0.1ꢀF
BOOST1
BG1
C
OUT1
220ꢀF
PLLIN/MODE
SGND
D1
RUN1
V
BIAS
C
BIAS
RUN2
V
OUT2
10ꢀF
R
B2
10pF
ITH2A
RUN3
PGND
R
A2
649k
68.1k
V
EXTV
FB2
CC
C
2.2nF
ITH2
C
C
INT2
4.7ꢀF
R
ITH2
15k
INT1
C2
10ꢀF
1ꢀF
I
INTV
TH2
CC
C
D2
68pF
MTOP2
MBOT2
L2
6.5ꢀH
TG2
R
C
SENSE2
8mΩ
SS2
C
B2
V
8.5V
3A
OUT2
0.1ꢀF
0.1ꢀF
TRACK/SS2 BOOST2
SW2
BG2
V
OUT3
C
OUT2
R
68ꢀF
B3
OPT
R
68.1k
A3
499k
V
FB3
C
ITH3
+
–
R
ITH3
3.6k
SENSE2
SENSE2
0.01ꢀF
C2
1nF
I
TH3
C
ITH3A
820pF
V
OUT3
10V*
C
SS3
D3
0.1ꢀF
C
OUT3
L3
1.2ꢀH
MTOP3
MBOT3
SS3
TG3
SW3
R
SENSE2
2mΩ
220ꢀF
V
IN
C
B3
2.5V TO 38V
0.1ꢀF
(START-UP ABOVE 5V)
BOOST3
BG3
MTOP1, MTOP2: BSZ097NO4LS
MBOT1, MBOT2: BSZ097NO4LS
MTOP3: BSC027NO4LS
MBOT3: BSCO1BN04LS
L1: WÜRTH 744314490
L2: WÜRTH 744314650
L3: WÜRTH 744325120
C
IN
220ꢀF
–
SENSE3
C3
1nF
+
C
C
C
: SANYO 6TPB220ML
: SANYO 10TPC68M
IN OUT3
SENSE3
OUT1
OUT2
* V
IS 10V WHEN V < 10V,
IN
OUT3
FOLLOWS V WHEN V > 10V
IN
IN
3859 F12
, C
: SANYO 50CE220LX
D1, D2: CMDH-4E
D3: BAS140W
Figure 12. High Efficiency Wide Input Range Dual 5V/8.5V Converter
3859f
34
LTC3859
TYPICAL APPLICATIONS
V
OUT1
R
B1
33pF
R
A1
LTC3859
SENSE1
475k
34k
–
+
V
FB1
C1
C
ITH1A
1nF
100pF
R
SENSE1
ITH1
C
ITH1
100k
10k
680pF
C1
I
PGOOD1
TG1
TH1
C
10ꢀF
SS1
L1
8.8ꢀH
R
SENSE1
9mΩ
MTOP1
MBOT1
0.1ꢀF
V
OUT1
12V
TRACK/SS1
FREQ
SW1
C
B1
3A
0.1ꢀF
BOOST1
BG1
C
OUT1
47ꢀF
PLLIN/MODE
SGND
D1
RUN1
V
BIAS
C
BIAS
RUN2
V
OUT2
10ꢀF
R
B2
15pF
RUN3
PGND
R
A2
215k
68.1k
V
EXTV
FB2
CC
C
ITH2
C
C
INT2
4.7ꢀF
R
ITH2
15k
INT1
820pF
C2
10ꢀF
1ꢀF
I
INTV
TH2
CC
C
ITH2A
150pF
D2
MTOP2
MBOT2
L2
3.2ꢀH
TG2
R
C
SENSE2
6mΩ
C
SS2
B2
V
3.3V
5A
OUT2
0.1ꢀF
0.1ꢀF
TRACK/SS2 BOOST2
SW2
BG2
V
OUT3
C
OUT2
R
150ꢀF
B3
OPT
R
A3
787k
68.1k
V
FB3
C
ITH3
+
–
R
ITH3
3.6k
SENSE2
SENSE2
0.01ꢀF
C2
1nF
I
TH3
C
ITH3A
820pF
V
OUT3
15V*
C
SS3
D3
0.1ꢀF
C
OUT3
L3
1.2ꢀH
MTOP3
MBOT3
SS3
TG3
SW3
R
SENSE2
2mΩ
220ꢀF
V
IN
C
B3
2.5V TO 38V
0.1ꢀF
(START-UP ABOVE 5V)
BOOST3
BG3
MTOP1, MTOP2: VISHAY Si7848DP
MBOT1, MBOT2: VISHAY Si7848DP
MTOP3: BSC027NO4LS
C
IN
220ꢀF
–
MBOT3: BSCO1BN04LS
SENSE3
L1: SUMIDA CDEP105-8R8M
L2: SUMIDA CDEP105-3R2M
L3: WÜRTH 744325120
C3
1nF
+
C
C
C
: KEMET T525D476MO16E035
: SANYO 4TPE150M
SENSE3
OUT1
OUT2
* V
IS 15V WHEN V < 15V,
IN
FOLLOWS V WHEN V > 15V
OUT3
IN
IN
3859 F13
, C
: SANYO 50CE220LX
IN OUT3
D1, D2: CMDH-4E
D3: BAS140W
Figure 13. High Efficiency Wide Input Range Dual 12V/3.3V Converter
3859f
35
LTC3859
TYPICAL APPLICATIONS
V
OUT1
R
B1
56pF
R
A1
LTC3859
SENSE1
28.7k
115k
–
+
V
FB1
C
ITH1A
200pF
C1
1nF
R
SENSE1
ITH1
C
ITH1
100k
3.93k
1000pF
C1
I
PGOOD1
TG1
TH1
10ꢀF
C
SS1
L1
0.47ꢀH
R
SENSE1
MTOP1
MBOT1
0.01ꢀF
V
1V
8A
3.5mΩ
OUT1
TRACK/SS1
FREQ
SW1
C
B1
0.1ꢀF
BOOST1
BG1
C
OUT1
220ꢀF
PLLIN/MODE
SGND
s2
D1
RUN1
V
BIAS
C
BIAS
RUN2
V
OUT2
10ꢀF
R
B2
56pF
RUN3
PGND
R
A2
57.6k
115k
V
EXTV
FB2
CC
C
ITH2
C
C
INT2
4.7ꢀF
R
INT1
ITH2
1000pF
C2
10ꢀF
1ꢀF
3.93k
I
INTV
TH2
CC
C
ITH2A
200pF
D2
MTOP2
MBOT2
L2
0.47ꢀH
TG2
R
SENSE2
3.5mΩ
C
C
SS2
B2
V
1.2V
8A
OUT2
0.01ꢀF
0.1ꢀF
TRACK/SS2 BOOST2
SW2
BG2
V
OUT3
C
OUT2
220ꢀF
R
B3
R
OPT
A3
232k
s2
12.1k
V
FB3
C
ITH3
+
–
R
ITH3
SENSE2
SENSE2
15nF
8.66k
C2
1nF
I
TH3
C
ITH3A
220pF
V
OUT3
24V
5A
C
D3
SS3
C
OUT3
220ꢀF
0.01ꢀF
L3
3.3ꢀH
MTOP3
MBOT3
SS3
TG3
SW3
R
SENSE2
4mΩ
V
IN
C
12V
B3
0.1ꢀF
BOOST3
BG3
C
MTOP1, MTOP2: RENESAS RJK0305
MBOT1, MBOT2: RENESAS RJK0328
MTOP3, MBOT3: RENESAS HAT2169H
L1, L2: SUMIDA CDEP105-0R4
L3: PULSE PA1494.362NL
IN
220ꢀF
–
SENSE3
C3
1nF
C
C
, C
: SANYO 2R5TPE220M
OUT1 OUT2
, C
: SANYO 50CE220AX
IN OUT3
+
D1, D2: CMDH-4E
D3: BAS140W
SENSE3
3859 F14
Figure 14. High Efficiency Triple 24V/1V/1.2V Converter from 12V VIN
3859f
36
LTC3859
TYPICAL APPLICATIONS
V
OUT1
R
B1
R
A1
LTC3859
SENSE1
57.6k
115k
–
+
V
FB1
C
ITH1A
C1
100pF
1nF
R
SENSE1
ITH1
C
ITH1
100k
5.6k
2.2nF
C1
I
PGOOD1
TG1
TH1
10ꢀF
C
SS1
L1
2.2ꢀH
R
SENSE1
9mΩ
MTOP1
MBOT1
0.1ꢀF
V
1.2V
3A
OUT1
TRACK/SS1
FREQ
SW1
C
B1
0.1ꢀF
BOOST1
BG1
C
OUT1
220ꢀF
PLLIN/MODE
SGND
D1
RUN1
V
BIAS
C
BIAS
RUN2
V
OUT2
10ꢀF
R
B2
RUN3
PGND
R
A2
357k
115k
V
EXTV
FB2
CC
C
ITH2
C
C
INT2
4.7ꢀF
R
ITH2
9.1k
INT1
C2
10ꢀF
3.3nF
1ꢀF
I
INTV
TH2
CC
C
ITH2A
D2
100pF
L2
6.5ꢀH
MTOP2
MBOT2
TG2
R
C
SENSE2
9mΩ
SS2
C
B2
0.1ꢀF
V
3.3V
3A
OUT2
0.1ꢀF
TRACK/SS2 BOOST2
SW2
BG2
V
OUT3
C
OUT2
220ꢀF
R
B3
R
A3
887k
115k
V
FB3
C
ITH3
+
–
R
ITH3
13k
SENSE2
SENSE2
100nF
C2
1nF
I
TH3
C
ITH3A
10pF
D3
V
OUT3
10.5V
1.2A
C
SS3
0.1ꢀF
C
OUT3
SS3
TG3
SW3
270ꢀF
C3
10ꢀF
50V
R
SENSE2
9mΩ
V
IN
BOOST3
BG3
MTOP1, MTOP2: BSZ097NO4LS
MBOT1, MBOT2: BSZ097NO4LS
MBOT3: BSZ097NO4L
5.8V TO 34V
L3
10ꢀH
C
IN
MBOT3
220ꢀF
–
L1: WURTH 744311220
SENSE3
L2: WURTH 744314650
L3: COOPER BUSSMANN DRQ125-100
C3
1nF
C
C
C
C
: SANYO 2R5TPE220MAFB
: SANYO 4TPE220MAZB
: SANYO SVPC270M
OUT1
OUT2
OUT3
+
SENSE3
3859 F15
: SANYO 50CE220LX
IN
D1, D2: CMDH-4E
D3: DIODES INC B360A-13-F
Figure 15. High Efficiency 1.2V/3.3V Step-Down Converter with 10.5V SEPIC Converter
3859f
37
LTC3859
PACKAGE DESCRIPTION
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev A)
Exposed Pad Variation AA
4.75 REF
9.60 – 9.80*
(.378 – .386)
4.75
(.187)
REF
38
20
6.60 0.10
2.74 REF
4.50 REF
SEE NOTE 4
6.40
REF (.252)
BSC
2.74
(.108)
0.315 0.05
1.05 0.10
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
19
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0o – 8o
0.50
(.0196)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.17 – 0.27
FE38 (AA) TSSOP 0608 REV A
(.0067 – .0106)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN
FOR EXPOSED PAD ATTACHMENT
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3. DRAWING NOT TO SCALE
3859f
38
LTC3859
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
0.70 p 0.05
5.50 p 0.05
4.10 p 0.05
3.00 REF
5.15 0.05
3.15 0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
5.5 REF
6.10 p 0.05
7.50 p 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER
0.75 p 0.05
3.00 REF
5.00 p 0.10
37
38
0.00 – 0.05
0.40 p0.10
PIN 1
TOP MARK
1
2
(SEE NOTE 6)
5.15 0.10
5.50 REF
7.00 p 0.10
3.15 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 p 0.05
R = 0.125
TYP
R = 0.10
TYP
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
3859f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
39
LTC3859
TYPICAL APPLICATION
High Efficiency Wide Input Range Dual 3.3V/8.5V Converter
V
OUT1
R
B1
215k
15pF
R
A1
LTC3859
SENSE1
68.1k
–
V
FB1
C1
1nF
C
ITH1A
150pF
+
R
SENSE1
C
ITH1
15k
ITH1
100k
820pF
C1
I
PGOOD1
TG1
TH1
C
10ꢀF
SS1
L1
3.2ꢀH
R
SENSE1
6mΩ
MTOP1
MBOT1
0.1ꢀF
V
3.3V
5A
OUT1
TRACK/SS1
FREQ
SW1
C
B1
0.1ꢀF
BOOST1
BG1
C
OUT1
150ꢀF
PLLIN/MODE
SGND
D1
RUN1
V
BIAS
C
BIAS
RUN2
V
OUT2
10ꢀF
R
10pF
B2
RUN3
PGND
R
A2
68.1k
649k
V
EXTV
FB2
CC
C
ITH2
2.2nF
C
C
INT2
4.7ꢀF
R
ITH2
15k
INT1
C2
10ꢀF
1ꢀF
I
INTV
TH2
CC
C
ITH2A
68pF
D2
MTOP2
MBOT2
L2
6.5ꢀH
TG2
R
SENSE2
8mΩ
C
C
SS2
0.1ꢀF
B2
V
8.5V
3A
OUT2
0.1ꢀF
TRACK/SS2 BOOST2
SW2
BG2
V
OUT3
C
OUT2
R
68ꢀF
OPT
B3
R
A3
499k
68.1k
V
FB3
C
ITH3
0.01ꢀF
+
–
R
ITH3
3.6k
SENSE2
SENSE2
C2
1nF
I
TH3
C
ITH3A
820pF
V
OUT3
10V*
C
SS3
0.1ꢀF
D3
C
OUT3
220ꢀF
L3
1.2ꢀH
MTOP3
MBOT3
R
SS3
TG3
SW3
SENSE2
2mΩ
V
IN
MTOP1, MTOP2: VISHAY Si7848DP
MBOT1, MBOT2: BSZ097NO4LS
MTOP3: BSC027NO4LS
C
B3
0.1ꢀF
2.5V TO 38V
(START-UP ABOVE 5V)
BOOST3
BG3
MBOT3: BSCO1BN04LS
C
IN
220ꢀF
L1: SUMIDA CDEP105-3R2M
L2: WÜRTH 744314650
–
SENSE3
L3: WÜRTH 744325120
C3
1nF
C
C
C
: SANYO 6TPB220ML
: SANYO 4TPE150M
OUT1
OUT2
+
, C
: SANYO 50CE220LX
IN OUT3
SENSE3
* V
IS 10V WHEN V < 10V,
IN
FOLLOWS V WHEN V > 10V
IN IN
OUT3
D1, D2: CMDH-4E
D3: BAS140W
3859 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Phase-Lockable Fixed Frequency 50kHz to 900kHz,
4V ≤ V ≤ 38V, 0.8V ≤ V ≤ 24V, I = 50ꢀA/170ꢀA,
LTC3857/LTC3857-1 Low I , Dual Output 2-Phase Synchronous Step-Down
Q
LTC3858/LTC3858-1 DC/DC Controllers with 99% Duty Cycle
IN
OUT
Q
LTC3890
60V, Low I , Dual 2-Phase Synchronous Step-Down
Phase-Lockable Fixed Frequency 50kHz to 900kHz,
Q
DC/DC Controller
4V ≤ V ≤ 60V, 0.8V ≤ V
≤ 24V, I = 50ꢀA
Q
IN
OUT
LTC3780
4-Switch High Efficiency Buck-Boost Controller
4V ≤ V ≤ 36V, 0.8V ≤ V
≤ 30V, SSOP-24, 5mm × 5mm QFN-32
IN
OUT
LTC3834/LTC3834-1/ Low I , Synchronous Step-Down DC/DC Controller with
Phase-Lockable Fixed Frequency 140kHz to 650kHz,
4V ≤ V ≤ 36V, 0.8V ≤ V ≤ 10V, I = 30ꢀA/80ꢀA
Q
LTC3835/LTC3835-1 99% Duty Cycle
IN
OUT
Q
LT3845
Low I , High Voltage Synchronous Step-Down DC/DC
Adjustable Fixed Frequency 100kHz to 500kHz, 4V ≤ V ≤ 60V,
IN
Q
Controller
1.23V ≤ V
≤ 36V, I = 120ꢀA, TSSOP-16
OUT Q
LTC3824
Low I , High Voltage DC/DC Controller, 100% Duty Cycle
Selectable Fixed 200kHz to 600kHz Operating Frequency,
4V ≤ V ≤ 60V, 0.8V ≤ V ≤ V , I = 40ꢀA, MSOP-10E
Q
IN
OUT
IN
Q
3859f
LT 0310 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
40
●
●
© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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