LTC3872ETS8#TRM [Linear]
LTC3872 - No RSENSE Current Mode Boost DC/DC Controller; Package: SOT; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LTC3872ETS8#TRM |
| 厂家： | 
Linear |
| 描述： | LTC3872 - No RSENSE Current Mode Boost DC/DC Controller; Package: SOT; Pins: 8; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总20页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3872
No R
SENSE
Current Mode Boost
DC/DC Controller
U
DESCRIPTIO
FEATURES
The LTC®3872 is a constant frequency current mode
boost DC/DC controller that drives an N-channel power
MOSFET and requires very few external components. The
■
No Current Sense Resistor Required
OUT
■
V
up to 60V
■
■
■
■
■
■
■
Constant Frequency 550kHz Operation
Internal Soft-Start and Optional External Soft-Start
Adjustable Current Limit
No R
TM architecture eliminates the need for a sense
SENSE
resistor, improves efficiency and saves board space.
Pulse Skipping at Light Load
The LTC3872 provides excellent AC and DC load and line
regulation with ±±.ꢀ5 output voltage accuracy. It incor-
porates an undervoltage lockout feature that shuts down
the device when the input voltage falls below 2.3V.
V Range: 2.7ꢀV to 9.8V
IN
±±.ꢀ5 Voltage Reference Accuracy
Current Mode Operation for Excellent Line and Load
Transient Response
■
High switching frequency of ꢀꢀ0kHz allows the use of a
small inductor. The LTC3872 is available in an 8-lead low
profile (±mm) ThinSOTTM package and 8-pin 3mm × 2mm
DFN package.
Low Profile (±mm) SOT-23 and 3mm × 2mm DFN
Packages
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APPLICATIO S
■
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Telecom Power Supplies
No R
and ThinSOT are trademarks of Linear Technology Corporation.
SENSE
■
42V Automotive Systems
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6498466, 6611131, 5731694.
■
24V Industrial Controls
IP Phone Power Supplies
■
U
TYPICAL APPLICATIO
High Efficiency 3.3V Input, 5V Output Boost Converter
Efficiency and Power Loss vs Load Current
100
90
80
70
60
50
40
30
20
10
0
10
1.8nF
17.4k
V
IN
I
V
IN
TH
3.3V
47pF
V
IN
10μF
IPRG
1
1μH
D1
LTC3872
GND
SW
0.1
0.01
0.001
M1
V
RUN/SS NGATE
FB
11k
1%
V
5V
2A
OUT
1nF
34.8k
1%
100μF
×2
3872 TA01
1
10
100
1000
10000
LOAD CURRENT (mA)
3872 TA01b
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LTC3872
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
Operating Temperature Range (Note 2) ... –40°C to 8ꢀ°C
Junction Temperature (Note 3) ............................. ±2ꢀ°C
Storage Temperature Range................... –6ꢀ°C to ±2ꢀ°C
Lead Temperature (Soldering, ±0 sec)
Input Supply Voltage (V ), RUN/SS.......... –0.3V to ±0V
IN
IPRG Voltage..................................–0.3V to (V + 0.3V)
IN
V , I Voltages....................................... –0.3V to 2.4V
FB TH
SW Voltage ................................................ –0.3V to 60V
TS8 Package ......................................................... 300°C
U
W
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
GND
1
2
3
4
8
7
6
5
NGATE
IPRG 1
8 SW
7 RUN/SS
6 V
IN
5 NGATE
V
I
V
IN
FB
I
V
2
3
9
TH
RUN/SS
SW
TH
FB
IPRG
GND 4
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
= ±2ꢀ°C, θ = 230°C/W
DDB PACKAGE
8-LEAD (3mm × 2mm) PLASTIC DFN
= ±2ꢀ°C, θ = 76°C/W
T
JMAX
JA
T
JMAX
JA
EXPOSED PAD (PIN 9) IS GND MUST BE SOLDERED TO PCB
ORDER PART NUMBER
LTC3872ETS8
TS8 PART MARKING
LCGB
ORDER PART NUMBER
LTC3872EDDB
DDB PART MARKING
LCHT
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
Input Voltage Range
2.7ꢀ
9.8
V
Input DC Supply Current
Normal Operation
Shutdown
Typicals at V = 4.2V (Note 4)
IN
2.7ꢀV ≤ V ≤ 9.8V, V = ±.3V
2ꢀ0
8
20
400
20
3ꢀ
μA
μA
μA
IN
ITH
V
V
= 0V
RUN/SS
IN
UVLO
< UVLO Threshold, V
= 0V
RUN
●
●
Undervoltage Lockout Threshold
V
IN
V
IN
Rising
Falling
2.3
2.0ꢀ
2.4ꢀ
2.3
2.7ꢀ
2.ꢀꢀ
V
V
●
Shutdown Threshold (at RUN/SS)
V
V
Falling
Rising
0.6
0.7
0.8ꢀ
0.9ꢀ
±.0ꢀ
±.±ꢀ
RUN/SS
RUN/SS
V
V
●
Regulated Feedback Voltage
(Note ꢀ)
2.7ꢀV < V < 9V (Note ꢀ)
±.±82
±.2
±.2±8
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
0.±4
mV/V
IN
V
ITH
V
ITH
= ±.6V (Note ꢀ)
= ±V (Note ꢀ)
0.0ꢀ
–0.0ꢀ
5
5
V
Input Current
(Note ꢀ)
2ꢀ
ꢀ0
nA
μA
FB
RUN/SS Pull Up Current
V
= 0
0.3ꢀ
0.7
±.2ꢀ
RUN/SS
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LTC3872
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator Frequency
Normal Operation
V
C
C
= ±.2V
ꢀ00
ꢀꢀ0
40
6ꢀ0
kHz
ns
FB
Gate Drive Rise Time
Gate Drive Fall Time
= 3000pF
= 3000pF
LOAD
LOAD
40
ns
●
●
●
Peak Current Sense Voltage
IPRG = GND (Note 6)
IPRG = Float
80
±4ꢀ
240
±00
±70
270
±20
±9ꢀ
290
mV
mV
mV
IPRG = V
IN
Default Internal Soft-Start Time
±
ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3872E is guaranteed to meet performance specifications
from 0°C to 8ꢀ°C junction temperature. Specifications over the –40°C
to 8ꢀ°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls.
Note 3: T is calculated from the ambient temperature T and power
J A
dissipation P according to the following formula:
D
T = T + (P • ±±0°C/W)
J
A
D
Note 4: The dynamic input supply current is higher due to power MOSFET
gate charging (Q • f ). See Applications Information.
G
OSC
Note 5: The LTC3872 is tested in a feedback loop which servos V to
FB
the reference voltage with the I pin forced to the midpoint of its voltage
TH
range (0.7V ≤ V ≤ ±.9V, midpoint = ±.3V).
ITH
Note 6: Rise and fall times are measured at ±05 and 905 levels.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
TA = 25°C unless otherwise noted.
FB Voltage vs Temperature
FB Voltage Line Regulation
ITH Voltage vs RUN/SS Voltage
2.5
2.0
1.5
1.25
1.24
1.2025
1.2020
1.2015
1.23
1.2010
1.2005
1.2000
1.1995
1.22
1.21
1.20
1.19
1.0
0.5
0
V
V
V
= 2.5V
= 3.3V
= 5V
IN
IN
IN
1.1990
1.18
0
3
5
6
7
8
9
10
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
1
2
4
–40 –20
0
20
80 100
–60
40 60
V
(V)
RUN VOLTAGE (V)
TEMPERATURE (˚C)
IN
3872 G03
3872 G02
3872 G01
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LTC3872
U W
TYPICAL PERFOR A CE CHARACTERISTICS
TA = 25°C unless otherwise noted.
Shutdown IQ vs VIN
Shutdown IQ vs Temperature
Frequency vs Duty Cycle
600
14
12
20
15
10
5
500
10
400
300
8
6
4
2
200
100
0
0
0
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
4
5
6
9
10
2
3
7
8
V
(V)
IN
3872 G05
3278 G06
3872 G04
Gate Drive Rise and Fall Time
vs CLOAD
RUN/SS Threshold vs
Temperature
RUN/SS Threshold vs VIN
100
90
80
70
60
50
40
30
20
10
0
1.0
1.00
0.98
0.96
0.94
RISING
RISING
0.9
0.8
RISE TIME
FALL TIME
FALLING
0.92
0.90
0.7
0.6
0.5
0.88
0.86
0.84
FALLING
8
2
4
50
TEMPERATURE (°C)
0
2000
4000
6000
(pF)
8000 10000
0
10
12
–50
25
75
6
–25
0
100 125
150
C
V
(V)
IN
LOAD
3872 G07
3872 G08
3872 G09
Maximum Sense Threshold
vs Temperature
Frequency vs Temperature
300
250
600
IPRG = V
IN
575
550
525
200
150
IPRG = FLOAT
IPRG = GND
100
50
0
500
–50 –30 –10 10 30 50 70 90 110 130 150
–50 –5
0
25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
3872 G11
3872 G10
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LTC3872
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PI FU CTIO S
(TS8/DD8)
IPRG (Pin 1/Pin 4): Current Sense Limit Select Pin.
RUN/SS (Pin 7/Pin 6): Shutdown and external soft-start
pin. Inshutdown, allfunctionsaredisabledandtheNGATE
pin is held low.
I
(Pin 2/Pin 3): It serves as the error amplifier com-
TH
pensation point. Nominal voltage range for this pin is
0.7V to ±.9V.
SW (Pin 8/Pin 5): Switch node connection to inductor and
current sense input pin through external slope compensa-
tion resistor. Normally, the external N-channel MOSFET’s
drain is connected to this pin.
V
(Pin 3/Pin 2): Receives the feedback voltage from an
FB
external resistor divider across the output.
GND (Pin 4/Pin 1): Ground Pin.
ExposedPad(NA/Pin9):Ground.MustbesolderedtoPCB
for electrical contact and rated thermal performance.
NGATE(Pin5/Pin8):GateDrivefortheExternalN-Channel
MOSFET. This pin swings from 0V to V .
IN
V
(Pin 6/Pin 7): Supply Pin. This pin must be closely
IN
decoupled to GND (Pin 4).
FUNCTIONAL DIAGRAM
V
GND
SW
IN
UV
SLOPE
COMPENSATION
UNDERVOLTAGE
LOCKOUT
VOLTAGE
REFERENCE
1.2V
IPRG
SHUTDOWN
COMPARATOR
–
+
CURRENT
COMPARATOR
0.7μA
I
LIM
+
–
SHDN
I
TH
BUFFER
550kHz
OSCILLATOR
R
S
RS
LATCH
Q
RUN/SS
CURRENT LIMIT
CLAMP
V
IN
NGATE
SWITCHING
LOGIC CIRCUIT
ERROR
AMPLIFIER
V
FB
–
+
INTERNAL
SOFT-START
RAMP
1.2V
I
TH
3872 FD
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LTC3872
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OPERATIO
Main Control Loop
component count; the maximum rating for this pin, 60V,
allows MOSFET sensing in a wide output voltage range.
The LTC3872 is a No R
constant frequency, current
SENSE
mode controller for DC/DC boost, SEPIC and flyback
converter applications. The LTC3872 is distinguished
from conventional current mode controllers because the
current control loop can be closed by sensing the voltage
dropacrossthepowerMOSFETswitchoracrossadiscrete
The RUN/SS pin controls whether the IC is enabled or is in
a low current shutdown state. With the RUN/SS pin below
0.8ꢀV, the chip is off and the input supply current is typi-
cally only ±0μA. With an external capacitor connected to
the RUN/SS pin an optional external soft-start is enabled.
A 0.7μA trickle current will charge the capacitor, pulling
the RUN/SS pin above shutdown threshold and slowly
senseresistor,asshowninFigures±and2.ThisNoR
SENSE
sensing technique improves efficiency, increases power
density and reduces the cost of the overall solution.
rampingRUN/SStolimittheV duringstart-up.Because
ITH
the noise on the SW pin could couple into the RUN/SS
pin, disrupting the trickle charge current that charges the
RUN/SS pin, a ±M resistor is recommended to pull-up the
RUN/SSpinwhenexternalsoft-startisused.WhenRUN/SS
is driven by an external logic, a minimum of 2.7ꢀV logic is
For circuit operation, please refer to the Block Diagram
of the IC and the Typical Application on the front page. In
normal operation, the power MOSFET is turned on when
the oscillator sets the RS latch and is turned off when the
current comparator resets the latch. The divided-down
outputvoltageiscomparedtoaninternal±.2Vreferenceby
recommended to allow the maximum I range.
TH
the error amplifier, which outputs an error signal at the I
TH
Light Load Operation
pin. The voltage on the I pin sets the current comparator
TH
Under very light load current conditions, the I pin volt-
input threshold. When the load current increases, a fall in
TH
age will be very close to the zero current level of 0.8ꢀV.
As the load current decreases further, an internal offset at
the current comparator input will assure that the current
comparatorremainstripped(evenatzeroloadcurrent)and
the regulator will start to skip cycles, as it must, in order
to maintain regulation. This behavior allows the regulator
to maintain constant frequency down to very light loads,
resulting in low output ripple as well as low audible noise
and reduced RF interference, while providing high light
load efficiency.
the FB voltage relative to the reference voltage causes the
I
TH
pin to rise, which causes the current comparator to
trip at a higher peak inductor current value. The average
inductor current will therefore rise until it equals the load
current, thereby maintaining output regulation.
The LTC3872 can be used either by sensing the voltage
drop across the power MOSFET or by connecting the SW
pin to a conventional sensing resistor in the source of the
power MOSFET. Sensing the voltage across the power
MOSFETmaximizesconverterefficiencyandminimizesthe
D
D
L
L
V
V
C
V
V
C
IN
OUT
OUT
IN
OUT
OUT
V
SW
V
V
IN
IN
+
+
SW
NGATE
V
SW
LTC3872
NGATE
GND
LTC3872
SW
R
GND
SENSE
GND
GND
3872 F01
3872 F02
Figure 1. SW Pin (Internal Sense Pin)
Connection for Maximum Efficiency
Figure 2. SW Pin (Internal Sense Pin)
Connection for Sensing Resistor
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LTC3872
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APPLICATIO S I FOR ATIO
Output Voltage Programming
The Peak and Average Input Currents
The control circuit in the LTC3872 is measuring the input
current (either by using the R of the power MOSFET
The output voltage is set by a resistor divider according
to the following formula:
DS(ON)
or by using a sense resistor in the MOSFET source), so
the output current needs to be reflected back to the input
in order to dimension the power MOSFET properly. Based
on the fact that, ideally, the output power is equal to the
input power, the maximum average input current is:
R2
R1
⎛
⎝
⎞
V =1.2V • 1+
⎜
⎟
⎠
O
The external resistor divider is connected to the output
as shown in the Typical Application on the front page,
allowing remote voltage sensing.
IO(MAX)
1–DMAX
Thepeak input current is:
I
=
IN(MAX)
Application Circuits
A basic LTC3872 application circuit is shown on the front
page of this datasheet. External component selection is
driven by the characteristics of the load and the input
supply.
IO(MAX)
1–DMAX
χ
2
⎛
⎝
⎞
⎟
⎠
I
= 1+
•
⎜
IN(PEAK)
χ
Ripple Current I and the Factor
L
Duty Cycle Considerations
χ
The constant in the equation above represents the
percentage peak-to-peak ripple current in the inductor,
relative to its maximum value. For example, if 305 ripple
current is chosen, then = 0.30, and the peak current is
±ꢀ5 greater than the average.
Foraboostconverteroperatinginacontinuousconduction
mode (CCM), the duty cycle of the main switch is:
χ
⎛
⎞
VO + VD – V
IN
D =
⎜
⎟
VO + VD
⎝
⎠
For a current mode boost regulator operating in CCM,
slope compensation must be added for duty cycles above
ꢀ05 in order to avoid subharmonic oscillation. For the
LTC3872, this ramp compensation is internal. Having an
internally fixed ramp compensation waveform, however,
does place some constraints on the value of the inductor
and the operating frequency. If too large an inductor is
where V is the forward voltage of the boost diode. For
D
converters where the input voltage is close to the output
voltage,thedutycycleislowandforconvertersthatdevelop
a high output voltage from a low voltage input supply, the
duty cycle is high. The LTC3872 has a built-in circuit that
allows the extension of the maximum duty cycle while
keeping the minimum switch off time unchanged. This
is accomplished by reducing the clock frequency when
the duty cycle is close to 805. This function allows the
user to obtain high output voltages from low input supply
voltages. The shift of frequency with duty cycle is shown
in the Typical Performance Characteristics section.
used, the resulting current ramp (I ) will be small relative
L
to the internal ramp compensation (at duty cycles above
ꢀ05), and the converter operation will approach voltage
mode(rampcompensationreducesthegainofthecurrent
loop). If too small an inductor is used, but the converter
is still operating in CCM (continuous conduction mode),
the internal ramp compensation may be inadequate to
prevent subharmonic oscillation. To ensure good current
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LTC3872
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APPLICATIO S I FOR ATIO
mode gain and avoid subharmonic oscillation, it is recom-
mended that the ripple current in the inductor fall in the
range of 205 to 405 of the maximum average current.
power MOSFET to go below ground where it is clamped
by the body diode. This ringing is not harmful to the IC
and it has been shown not to contribute significantly to
EMI. Any attempt to damp it with a snubber will degrade
the efficiency.
For example, if the maximum average input current is
χ
±A, choose an I between 0.2A and 0.4A, and a value
L
between 0.2 and 0.4.
Inductor Core Selection
Inductor Selection
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but is very dependent on the
inductanceselected. Asinductanceincreases, corelosses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore, copper losses will in-
crease. Generally, there is a tradeoff between core losses
and copper losses that needs to be balanced.
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the inductor,
the inductor value can be determined using the following
equation:
V
IN(MIN)
L =
•DMAX
ΔIL • f
where:
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper losses and preventing saturation.
Ferrite core material saturates “hard,” meaning that the
inductancecollapsesrapidlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequently, output voltage ripple. Do
not allow the core to saturate!
IO(MAX)
χ
ΔIL = •
1–DMAX
Remember that boost converters are not short-circuit
protected. Under a shorted output condition, the inductor
current is limited only by the input supply capability.
The minimum required saturation current of the inductor
can be expressed as a function of the duty cycle and the
load current, as follows:
Differentcorematerialsandshapeswillchangethesize/cur-
rent and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price vs size requirements and any
radiated field/EMI requirements. New designs for surface
mount inductors are available from Coiltronics, Coilcraft,
Toko and Sumida.
IO(MAX)
1–DMAX
χ
2
⎛
⎞
⎟
⎠
IL(SAT) ≥ 1+
•
⎜
⎝
The saturation current rating for the inductor should be
checkedattheminimuminputvoltage(whichresultsinthe
highest inductor current) and maximum output current.
Operating in Discontinuous Mode
Discontinuous mode operation occurs when the load cur-
rent is low enough to allow the inductor current to run
out during the off-time of the switch. Once the inductor
current is near zero, the switch and diode capacitances
resonate with the inductance to form damped ringing at
±MHz to ±0MHz. If the off-time is long enough, the drain
voltage will settle to the input voltage.
Power MOSFET Selection
The power MOSFET serves two purposes in the LTC3872:
itrepresentsthemainswitchingelementinthepowerpath
and its R
represents the current sensing element
DS(ON)
for the control loop. Important parameters for the power
MOSFET include the drain-to-source breakdown voltage
(BV ),thethresholdvoltage(V
),theon-resistance
DSS
DS(ON)
GS(TH)
Depending on the input voltage and the residual energy
in the inductor, this ringing can cause the drain of the
(R
)versusgate-to-sourcevoltage,thegate-to-source
and gate-to-drain charges (Q and Q , respectively),
GS
GD
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LTC3872
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APPLICATIO S I FOR ATIO
the maximum drain current (I
) and the MOSFET’s
).Logic-level(4.ꢀV
V
is the maximum voltage drop across the
D(MAX)
andR
SENSE(MAX)
power MOSFET. V
thermalresistances(R
GS-RATED
is typically 270mV, ±70mV
SENSE(MAX)
TH(JC)
TH(JA)
V
)thresholdMOSFETsshouldbeusedwheninput
and ±00mV. It is reduced with increasing duty cycle as
showninFigure3.Theρ termaccountsforthetemperature
voltage is high, otherwise if low input voltage operation
is expected (e.g., supplying power from a lithium-ion
battery or a 3.3V logic supply), then sublogic-level (2.ꢀV
T
coefficientoftheR
oftheMOSFET,whichistypically
0.45/°C. Figure 4 illustrates the variation of normalized
R over temperature for a typical power MOSFET.
DS(ON)
DS(ON)
V
) threshold MOSFETs should be used.
GS-RATED
Pay close attention to the BV
specifications for the
Another method of choosing which power MOSFET to
use is to check what the maximum output current is for a
DS(ON)
in discrete values.
DSS
MOSFETsrelativetothemaximumactualswitchvoltagein
theapplication.Manylogic-leveldevicesarelimitedto30V
or less, and the switch node can ring during the turn-off of
the MOSFET due to layout parasitics. Check the switching
waveforms of the MOSFET directly across the drain and
source terminals using the actual PC board layout (not
just on a lab breadboard!) for excessive ringing.
givenR
, sinceMOSFETon-resistancesareavailable
1–DMAX
IO(MAX) = VSENSE(MAX)
•
χ
2
⎛
⎜
⎝
⎞
1+
•RDS(ON) • ρT
⎟
⎠
It is worth noting that the ± – D
relationship between
During the switch on-time, the control circuit limits the
maximum voltage drop across the power MOSFET to
about 270mV, ±00mV and ±70mV at low duty cycle with
MAX
I
and R
can cause boost converters with a
O(MAX)
DS(ON)
wide input range to experience a dramatic range of maxi-
mum input and output current. This should be taken into
consideration in applications where it is important to limit
the maximum current drawn from the input supply.
IPRG tied to V , GND, or left floating respectively. The
IN
peak inductor current is therefore limited to (270mV,
±70mV and ±00mV)/R
the IPRG pin.
depending on the status of
DS(ON)
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
The relationship between the maximum load current, duty
cycle and the R
of the power MOSFET is:
DS(ON)
In order to calculate the junction temperature of the power
MOSFET,thepowerdissipatedbythedevicemustbeknown.
This power dissipation is a function of the duty cycle, the
load current and the junction temperature itself (due to
1–DMAX
RDS(ON) ≤ VSENSE(MAX)
•
χ
⎛
⎜
⎝
⎞
⎟
⎠
1+
•IO(MAX) • ρT
2
the positive temperature coefficient of its R
). As a
DS(ON)
2.0
300
IPRG = HIGH
IPRG = FLOAT
250
1.5
1.0
0.5
0
200
150
100
50
0
IPRG = LOW
50
100
1
20
40
60
80
100
–50
0
150
DUTY CYCLE (%)
JUNCTION TEMPERATURE (°C)
3872 G03
3872 F04
Figure 3. Maximum SENSE Threshold Voltage vs Duty Cycle
Figure 4. Normalized RDS(ON) vs Temperature
3872fa
9
LTC3872
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APPLICATIO S I FOR ATIO
result, some iterative calculation is normally required to
determineareasonablyaccuratevalue.Sincethecontroller
is using the MOSFET as both a switching and a sensing
element, care should be taken to ensure that the converter
is capable of delivering the required load current over all
operating conditions (line voltage and temperature), and
IO(MAX)
1–DMAX
χ
2
⎛
⎝
⎞
⎟
⎠
ID(PEAK) = IL(PEAK) = 1+
•
⎜
The power dissipated by the diode is:
P = I • V
D
O(MAX)
D
for the worst-case specifications for V
and the
and the diode junction temperature is:
SENSE(MAX)
R
of the MOSFET listed in the manufacturer’s data
DS(ON)
sheet.
T = T + P • R
J
A
D
TH(JA)
The R
to be used in this equation normally includes
for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
TH(JA)
The power dissipated by the MOSFET in a boost converter
is:
the R
TH(JC)
2
Remember to keep the diode lead lengths short and to
observe proper switch-node layout (see Board Layout
Checklist) to avoid excessive ringing and increased dis-
sipation.
IO(MAX)
⎛
⎞
PFET
=
• RDS(ON) •DMAX • ρT
⎜
⎟
1– D
⎝
⎠
MAX
IO(MAX)
1.85
+k • VO
•
• CRSS • f
1– D
)
(
MAX
Output Capacitor Selection
2
The first term in the equation above represents the I R
losses in the device, and the second term, the switching
losses.Theconstant,k=±.7,isanempiricalfactorinversely
related to the gate drive current and has the dimension
of ±/current.
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
mustbeconsideredwhenchoosingthecorrectcomponent
for a given output ripple voltage. The effects of these three
parameters (ESR, ESL and bulk C) on the output voltage
ripple waveform are illustrated in Figure ꢀe for a typical
boost converter.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ΔV.
For the purpose of simplicity we will choose 25 for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging ΔV. This percent-
age ripple will change, depending on the requirements
of the application, and the equations provided below can
easily be modified.
T = T + P • R
J
A
FET
TH(JA)
The R
the R
to be used in this equation normally includes
for the device plus the thermal resistance from
TH(JA)
TH(JC)
the case to the ambient temperature (R
). This value
TH(CA)
of T can then be compared to the original, assumed value
J
used in the iterative calculation process.
Output Diode Selection
To maximize efficiency, a fast switching diode with low
forwarddropandlowreverseleakageisdesired.Theoutput
diode in a boost converter conducts current during the
switch off-time. The peak reverse voltage that the diode
must withstand is equal to the regulator output voltage.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to the
peak inductor current.
For a ±5 contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the fol-
lowing equation:
0.01• VO
ESRCOUT
≤
IIN(PEAK)
3872fa
10
LTC3872
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APPLICATIO S I FOR ATIO
capacitor available from Sanyo has the lowest product of
ESR and size of any aluminum electrolytic, at a somewhat
higher price.
where:
IO(MAX)
1–DMAX
χ
2
⎛
⎝
⎞
⎟
⎠
IIN(PEAK)= 1+
•
⎜
In surface mount applications, multiple capacitors may
have to be placed in parallel in order to meet the ESR or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount packages. In the case of
tantalum, it is critical that the capacitors have been surge
tested for use in switching power supplies. An excellent
choice is AVX TPS series of surface mount tantalum. Also,
ceramic capacitors are now available with extremely low
ESR, ESL and high ripple current ratings.
For the bulk C component, which also contributes ±5 to
the total ripple:
IO(MAX)
0.01• VO • f
COUT
≥
Formanydesignsitispossibletochooseasinglecapacitor
type that satisfies both the ESR and bulk C requirements
forthedesign.Incertaindemandingapplications,however,
the ripple voltage can be improved significantly by con-
necting two or more types of capacitors in parallel. For
example, using a low ESR ceramic capacitor can minimize
the ESR step, while an electrolytic capacitor can be used
to supply the required bulk C.
L
D
V
OUT
V
SW
C
R
L
IN
OUT
5a. Circuit Diagram
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on a dedicated PC board (see Board
Layout section for more information on component place-
ment). Lab breadboards generally suffer from excessive
series inductance (due to inter-component wiring), and
these parasitics can make the switching waveforms look
significantly worse than they would be on a properly
designed PC board.
I
IN
I
L
5b. Inductor and Input Currents
I
SW
t
ON
The output capacitor in a boost regulator experiences
high RMS ripple currents, as shown in Figure 6. The RMS
output capacitor ripple current is:
5c. Switch Current
I
VO – V
D
IN(MIN)
t
OFF
IRMS(COUT) ≈IO(MAX)
•
I
O
V
IN(MIN)
5d. Diode and Output Currents
Note that the ripple current ratings from capacitor manu-
facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
ΔV
COUT
V
OUT
(AC)
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
ΔV
ESR
5e. Output Voltage Ripple Waveform
Manufacturers such as Nichicon, United Chemicon and
Sanyoshouldbeconsideredforhighperformancethrough-
hole capacitors. The OS-CON semiconductor dielectric
Figure 5. Switching Waveforms for a Boost Converter
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11
LTC3872
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APPLICATIO S I FOR ATIO
DC current. Each time the MOSFET is switched on and
Input Capacitor Selection
then off, a packet of gate charge Q is transferred from
G
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input and the input current waveform
is continuous (see Figure ꢀb). The input voltage source
impedance determines the size of the input capacitor,
which is typically in the range of ±0μF to ±00μF. A low ESR
capacitor is recommended, although it is not as critical as
for the output capacitor.
V to ground. The resulting dQ/dt is a current that must
IN
be supplied to the Input capacitor by an external supply.
If the IC is operating in CCM:
I
≈ I = f • Q
Q G
Q(TOT)
P = V • (I + f • Q )
IC
IN
Q
G
2. Power MOSFET switching and conduction losses. The
technique of using the voltage drop across the power
MOSFET to close the current feedback loop was chosen
because of the increased efficiency that results from not
having a sense resistor. The losses in the power MOSFET
are equal to:
The RMS input capacitor ripple current for a boost con-
verter is:
V
IN(MIN)
IRMS(CIN) = 0.3 •
•DMAX
L • f
2
IO(MAX)
⎛
⎞
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to
the input of the converter and solid tantalum capacitors
can fail catastrophically under these conditions. Be sure
to specify surge-tested capacitors!
PFET
=
•RDS(ON) •DMAX • ρT
⎜
⎟
1– D
⎝
⎠
MAX
IO(MAX)
1.85
+ k • VO
•
• CRSS • f
1– DMAX
2
The I R power savings that result from not having a
discretesenseresistorcanbecalculatedalmostbyinspec-
tion.
Efficiency Considerations: How Much Does VDS
Sensing Help?
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power (×±005).
2
IO(MAX)
⎛
⎞
PR(SENSE)
=
•RSENSE •DMAX
⎜
⎟
Percent efficiency can be expressed as:
1– D
⎝
⎠
MAX
5 Efficiency = ±005 – (L± + L2 + L3 + …),
To understand the magnitude of the improvement with
where L±, L2, etc. are the individual loss components as a
percentage of the input power. It is often useful to analyze
individuallossestodeterminewhatislimitingtheefficiency
and which change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for the majority
of the losses in LTC3872 application circuits:
this V sensing technique, consider the 3.3V input, ꢀV
DS
output power supply shown in the Typical Application on
thefrontpage.Themaximumloadcurrentis7A(±0Apeak)
and the duty cycle is 395. Assuming a ripple current of
405, the peak inductor current is ±3.8A and the average
is ±±.ꢀA. With a maximum sense voltage of about ±40mV,
the sense resistor value would be ±0mΩ, and the power
dissipated in this resistor would be ꢀ±4mW at maximum
output current. Assuming an efficiency of 905, this
sense resistor power dissipation represents ±.35 of the
overall input power. In other words, for this application,
±. The supply current into V . The V current is the
IN
IN
sum of the DC supply current I (given in the Electrical
Q
Characteristics) and the MOSFET driver and control cur-
rents. The DC supply current into the V pin is typically
IN
the use of V sensing would increase the efficiency by
about 2ꢀ0μA and represents a small power loss (much
DS
approximately ±.35.
less than ±5) that increases with V . The driver current
IN
results from switching the gate capacitance of the power
For more details regarding the various terms in these
MOSFET; this current is typically much larger than the
equations, please refer to the section Boost Converter:
3872fa
12
LTC3872
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APPLICATIO S I FOR ATIO
Power MOSFET Selection.
the direction of the load step) as shown in Figure 6. The
regulator feedback loop acts on the resulting error amp
3. The losses in the inductor are simply the DC input cur-
rentsquaredtimesthewindingresistance.Expressingthis
loss as a function of the output current yields:
output signal to return V to its steady-state value. During
O
this recovery time, V can be monitored for overshoot or
O
ringing that would indicate a stability problem.
2
IO(MAX)
⎛
⎞
A second, more severe transient can occur when con-
necting loads with large (>±μF) supply bypass capacitors.
The discharged bypass capacitors are effectively put in
parallel with C , causing a nearly instantaneous drop in
V . No regulator can deliver enough current to prevent
this problem if the load switch resistance is low and it is
driven quickly. The only solution is to limit the rise time
of the switch drive in order to limit the inrush current
di/dt to the load.
PR(WINDING)
=
•RW
⎜
⎟
1– D
⎝
⎠
MAX
O
4. Losses in the boost diode. The power dissipation in the
boost diode is:
O
P
= I
• V
O(MAX) D
DIODE
The boost diode can be a major source of power loss in
a boost converter. For the 3.3V input, ꢀV output at 7A ex-
ample given above, a Schottky diode with a 0.4V forward
voltage would dissipate 2.8W, which represents 75 of the
input power. Diode losses can become significant at low
output voltages where the forward voltage is a significant
percentage of the output voltage.
Boost Converter Design Example
Thedesignexamplegivenherewillbeforthecircuitshown
on the front page. The input voltage is 3.3V, and the output
is ꢀV at a maximum load current of 2A.
ꢀ. Other losses, including C and C ESR dissipation and
IN
O
±. The duty cycle is:
inductor core losses, generally account for less than 25
⎛
⎞
⎠
VO + VD – V
5 + 0.4 – 3.3
5 + 0.4
of the total additional loss.
IN
D =
=
= 38.9%
⎜
⎟
VO + VD
⎝
Checking Transient Response
2. An inductor ripple current of 405 of the maximum load
current is chosen, so the peak input current (which is also
the minimum saturation current) is:
The regulator loop response can be verified by looking at
theloadtransientresponse.Switchingregulatorsgenerally
take several cycles to respond to an instantaneous step
in resistive load current. When the load step occurs, V
O
IO(MAX)
χ
2
⎛
⎞
immediately shifts by an amount equal to (ΔI
)(ESR),
IIN(PEAK) = 1+
•
= 1.2 •
= 3.9A
LOAD
⎜
⎝
⎟
⎠
2
1– DMAX
1– 0.39
and then C begins to charge or discharge (depending on
O
The inductor ripple current is:
V
OUT
IO(MAX)
200mV/DIV
2
χ
AC COUPLED
ΔIL = •
= 0.4•
=1.3A
1–DMAX
1– 0.39
And so the inductor value is:
V
3.3V
1.3A •550kHz
IN(MIN)
I
L =
•DMAX
=
•0.39=1.8μH
L
500mA/DIV
ΔIL • f
3872 F06
20μs/DIV
The component chosen is a 2.2μH inductor made by
Sumida (part number CEP±2ꢀ-H ±ROMH).
Figure 6. Load Transient Response for a 3.3V Input,
5V Output Boost Converter Application, 0.1A to 1A Step
3872fa
13
LTC3872
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APPLICATIO S I FOR ATIO
capacitors (JMK32ꢀBJ226MM) is required (the input
and return lead lengths are kept to a few inches. As with
the output node, check the input ripple with a single
oscilloscope probe connected across the input capacitor
terminals.
3. Assuming a MOSFET junction temperature of ±2ꢀ°C,
the room temperature MOSFET R
than:
should be less
DS(ON)
1–DMAX
RDS(ON) ≤ VSENSE(MAX)
•
χ
⎛
⎞
1+
•IO(MAX) •ρT
⎜
⎝
⎟
PC Board Layout Checklist
⎠
2
1– 0.39
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3872. These items are illustrated graphically in
the layout diagram in Figure 7. Check the following in
your layout:
= 0.175V •
≈30mΩ
0.4
2
⎛
⎞
1+
•2A •1.5
⎜
⎝
⎟
⎠
The MOSFET used was the Si3460, which has a maximum
of 27mΩ at 4.ꢀV V , a BV
30V, and a gate charge of ±3.ꢀnC at 4.ꢀV V .
R
of greater than
DS(ON)
GS
DSS
±. The Schottky diode should be closely connected be-
tween the output capacitor and the drain of the external
MOSFET.
GS
4. The diode for this design must handle a maximum DC
output current of 2A and be rated for a minimum reverse
2. The input decoupling capacitor (0.±μF) should be con-
voltage of V , or ꢀV. A 2ꢀA, ±ꢀV diode from On Semi-
OUT
nected closely between V and GND.
IN
conductor (MBRB2ꢀ±ꢀL) was chosen for its high power
3. The trace from SW to the switch point should be kept
short.
dissipation capability.
ꢀ. Theoutput capacitorusuallyconsistsofa lowervalued,
low ESR ceramic.
4. Keep the switching node NGATE away from sensitive
small signal nodes.
6. The choice of an input capacitor for a boost converter
depends on the impedance of the source supply and the
amount of input ripple the converter will safely tolerate.
For this particular design two 22μF Taiyo Yuden ceramic
ꢀ. The V pin should connect directly to the feedback
FB
resistors. The resistive divider R± and R2 must be con-
nected between the (+) plate of C
and signal ground.
OUT
IPRG
SW
I
RUN/SS
TH
LTC3872
R
ITH
V
V
IN
FB
C
C
OUT
IN
+
+
GND
NGATE
C
ITH
V
V
OUT
R2
D1
R1
L1
M1
IN
3872 F07
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 7. LTC3872 Layout Diagram (See PC Board Layout Checklist)
3872fa
14
LTC3872
TYPICAL APPLICATIONS
High Efficiency 3.3V Input, 12V Output Boost Converter
4.7M
0.1μF
2.2nF
23.2k
V
IN
I
RUN/SS
V
IN
TH
3.3V
C
IN
L1
2.2μH
100pF
IPRG
10μF
LTC3872
GND
SW
NGATE
M1
V
PDS1040
FB
11.8k
1%
V
OUT
12V
107k
1%
C
22μF
×2
OUT1
+
1.5A
C
OUT2
120μF
3872 F08
COUT1: TAIYO YUDEN TMK325BJ226MM
L1: COILTRONICS DR125-2R2
M1: FAIRCHILD FDS6064N3
V
OUT
12V
AC COUPLED
I
L
5A/DIV
I
LOAD
1A/DIV
STEP FROM
500mA TO 1.5A
3872 F09
100μs/DIV
3872fa
15
LTC3872
TYPICAL APPLICATIONS
High Efficiency 5V Input, 12V Output Boost Converter
4.7M
1nF
I
LOAD
2.2nF
500mA/DIV
STEP FROM
11k
V
IN
I
RUN/SS
V
TH
IN
100mA TO 600mA
5V
C
IN
100p
IPRG
L1
3.3 H
10 F
I
LOAD
LTC3872
5A/DIV
GND
SW
V
12V
2A
M1
V
NGATE
SBM835L
OUT
FB
V
11.8k
1%
OUT
C
OUT1
+
C
OUT2
22 F
2
107k
1%
68 F
3872 TA03b
3872 TA03
500μs/DIV
COUT1: TAIYO YUDEN TMK325BJ226MM
L1: TOKO D124C 892NAS-3R3M
M1: IRF3717
High Efficiency 5V Input, 24V Output Boost Converter
4.7M
0.068μF
1nF
52.3k
100p
V
IN
I
RUN/SS
V
IN
TH
5V
C
IN
IPRG
L1
8.2μH
10μF
LTC3872
GND
SW
NGATE
V
24V
1A
M1
OUT
V
UPS840
FB
12.1k
1%
C
OUT1
+
C
OUT2
10μF
×2
232k
1%
68μF
3872 TA04
C
: TAIYO YUDEN GMK316BJ106ML
OUT1
L1: WURTH WE-HCF 8.2μH 744392-820
M1: SILICONIX Si4884DY
Efficiency
Load Step
100
90
I
LOAD
500mA/DIV
STEP FROM
80
70
60
100mA TO 600mA
I
LOAD
5A/DIV
50
40
30
20
10
0
V
OUT
3872 TA04c
500μs/DIV
1
100
1000
10
LOAD (mA)
3872 TA04b
3872fa
16
LTC3872
TYPICAL APPLICATIONS
High Efficiency 5V Input, 48V Output Boost Converter
1M
0.33μF
63.4k
1%
2.2nF
V
IN
I
RUN/SS
V
TH
IN
5V
C
IN
V
IPRG
IN
L1
10μH
10μF
LTC3872
GND
SW
NGATE
V
M1
D1
FB
12.1k
1%
V
OUT
48V
475k
1%
C
+
OUT1
C
0.5A
OUT2
2.2μF
×3
68μF
3872 TA05
C
: NIPPON CHEMI-CON NTS50X7R2A225KT
OUT1
D1: DIODES, INC. PDS760
L1: SUMIDA CDEP147
M1: VISHAY SILICONIX Si7850DP
Soft-Start
Load Step
RUN/SS
5V/DIV
I
LOAD
200mA/DIV
I
L
5A/DIV
I
L
2A/DIV
V
OUT
20V/DIV
V
OUT
500mV/DIV
AC COUPLED
3872 TA05b
3872 TA05c
40ms/DIV
500μs/DIV
Efficiency
100
90
80
70
60
50
40
30
20
1
10
100
1000
LOAD (mA)
3872 TA05d
3872fa
17
LTC3872
U
PACKAGE DESCRIPTIO
DDB Package
8-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 0ꢀ-08-±702 Rev B)
0.61 0.05
(2 SIDES)
0.70 0.05
2.55 0.05
1.15 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
2.20 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
0.40 0.10
3.00 0.10
(2 SIDES)
TYP
5
R = 0.05
TYP
8
2.00 0.10
PIN 1 BAR
(2 SIDES)
TOP MARK
PIN 1
R = 0.20 OR
(SEE NOTE 6)
0.25 × 45°
0.56 0.05
(2 SIDES)
CHAMFER
4
1
(DDB8) DFN 0905 REV B
0.25 0.05
0.75 0.05
0.200 REF
0.50 BSC
2.15 0.05
(2 SIDES)
0 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3872fa
18
LTC3872
U
PACKAGE DESCRIPTIO
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 0ꢀ-08-±637)
2.90 BSC
(NOTE 4)
0.52
MAX
0.65
REF
1.22 REF
1.50 – 1.75
(NOTE 4)
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.22 – 0.36
8 PLCS (NOTE 3)
0.65 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.95 BSC
0.09 – 0.20
(NOTE 3)
TS8 TSOT-23 0802
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3872fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3872
U
TYPICAL APPLICATIO
3.3V Input, 5V/2A Output Boost Converter
47pF
1 M
1nF
1.8nF
17.4k
V
IN
I
RUN/SS
V
IN
TH
3.3V
C
IN
V
IN
IPRG
L1
1μH
10μF
LTC3872
GND
SW
NGATE
M1
V
D1
FB
11k
1%
V
5V
2A
OUT
34.8k
1%
C
OUT
100μF
×2
3872 TA02
D1: DIODES, INC B320
L1: TOKOFDV0630-1R0
M1: SILICONIX Si3460DV
RELATED PARTS
PART NUMBER
LT®±6±9
DESCRIPTION
Current Mode PWM Controller
Current Mode DC/DC Controller
COMMENTS
300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology
LTC±624
SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design;
V
IN
Up to 36V
LTC±700
No R
Synchronous Step-Up Controller
Up to 9ꢀ5 Efficiency, Operating as Low as 0.9V Input
No R , 7V Gate Drive, Current Mode Control
SENSE
LTC±87±-7
Wide Input Range Controller
SENSE
LTC±872/LTC±872B SOT-23 Boost Controller
Delievers Up to ꢀA, ꢀꢀ0kHz Fixed Frequency, Current Mode
LT±930
±.2MHz, SOT-23 Boost Converter
Inverting ±.2MHz, SOT-23 Converter
Up to 34V Output, 2.6V V ±6V, Miniature Design
IN
LT±93±
Positive-to Negative DC/DC Conversion, Miniature Design
LTC340±/LTC3402
LTC3704
±A/2A 3MHz Synchronous Boost Converters
Positive-to Negative DC/DC Controller
Up to 975 Efficiency, Very Small Solution, 0.ꢀV ≤ V ≤ ꢀV
IN
No R
, Current Mode Control, ꢀ0kHz to ±MHz
SENSE
SENSE
LTC±87±/LTC±87±-7 No R
, Wide Input Range DC/DC Boost Controller No R
SENSE
, Current Mode Control, 2.ꢀV ≤ V ≤ 36V
IN
LTC3703/LTC3703-ꢀ ±00V Synchronous Controller
LTC3803/LTC3803-ꢀ 200kHz Flyback DC/DC Controller
Step-Up or Step Down, 600kHz, SSOP-±6, SSOP-28
Optimized for Driving 6V MOSFETs ThinSOT
3872fa
LT 0407 REV A • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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