LTC3886EUKG#PBF [Linear]
LTC3886 - 60V Dual Output Step-Down Controller with Digital Power System Management; Package: QFN; Pins: 52; Temperature Range: -40°C to 85°C;
| 型号： | LTC3886EUKG#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3886 - 60V Dual Output Step-Down Controller with Digital Power System Management; Package: QFN; Pins: 52; Temperature Range: -40°C to 85°C |
| 文件： | 总120页 (文件大小：1538K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3886
60V Dual Output
Step-Down Controller with Digital
Power System Management
DescripTion
FeaTures
2
The LTC®3886 is a dual PolyPhase DC/DC synchronous
n
PMBus/I C Compliant Serial Interface
2
n
Telemetry Read-Back Includes V , I , V , I
,
step-down switching regulator controller with I C-based
PMBus compliant serial interface. This controller employs
a constant-frequency, current-mode architecture, with high
voltage input and output capability along with program-
mable loop compensation. The LTC3886 is supported by
theLTpowerPlay® softwaredevelopmenttoolwithgraphical
user interface (GUI).
IN IN OUT OUT
Temperature and Faults
n
Programmable Voltage, Current Limit, Digital
Soft-Start/Stop, Sequencing, Margining, OV/UV/OC,
Frequency, and Control Loop Compensation
OutputErrorLessThan 0.5%OverTemperature
Integrated16-BitADCand12-BitDAC
n
n
n
n
n
IntegratedHighSideCurrentSenseAmplifier
InternalEEPROMwithECCandFaultLogging
IntegratedN-ChannelMOSFETGateDrivers
The EXTV pin supports voltages up to 14V allowing for
CC
optimized circuit efficiency and die temperature, and for
the controller output to supply the chip power. Switching
frequency, output voltage, and device address can be
programmed both by digital interface as well as external
configuration resistors. Parameters can be set via the
digital interface or stored in EEPROM. Both outputs have
an independent power good indicator and FAULT function.
Power Conversion
n
Wide V Range: 4.5V to 60V
OUT0 OUT1
Analog Current Mode Control
IN
, V
n
V
Range: 0.5V to 13.8V
n
n
Accurate PolyPhase® Current Sharing for
Up to 6 Phases (100kHz to 750kHz)
Available in a 52-Lead (7mm × 8mm) QFN Package
The LTC3886 can be configured for discontinuous (pulse-
skipping) mode or continuous inductor current mode.
n
L, LT, LTC, LTM, Linear Technology, the Linear logo, µModule, PolyPhase, LTpowerPlay and
LTpowerCAD are registered trademarks of Analog Devices, Inc. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 5481178, 5705919,
5929620, 6100678, 6144194, 6177787, 5408150, 6580258, 6304066, 7420359, 8786268
Patent Pending. Licensed under U.S. Patent 7000125 and other related patents worldwide.
applicaTions
n
Telecom, Datacom, and Storage Systems
n
Industrial and Point of Load Applications
Typical applicaTion
10µF
2Ω
5mΩ
V
IN
18V TO 48V
10µF
1µF
+
–
INTV
TG0
V
I
I
CC IN IN IN
TG1
Efficiency and Power Loss
vs Load Current
0.1µF
0.1µF
BOOST0
SW0
BOOST1
3.1µH
6.82µH
100
90
80
70
60
50
40
30
20
10
0
9
8
7
6
5
4
3
2
1
0
SW1
BG1
V
V
f
= 48V
IN
OUT
= 150kHz
= 12V
BG0
LTC3886*
SW
6.81k
1µF
7.5k
1µF
SDA
SCL
FAULT0
FAULT1
PGOOD0
PGOOD1
FAULT MANAGEMENT
PMBus
ALERT
RUN0
RUN1 SHARE_CLK
INTERFACE
TO/FROM
OTHER LTC DEVICES
+
+
I
I
I
SENSE0
SENSE1
SENSE1
6.81k
7.5k
0.22µF
0.22µF
–
–
I
SENSE0
V
12V
15A
V
EXTV
OUT1
OUT0
5V
15A
CC
+
–
V
V
V
SENSE0
SENSE0
SENSE1
TSNS1
TSNS0
+
I
I
+
TH0
TH1
0.01
0.1
1
10
100
I
I
530µF
530µF
THR0
THR1
10nF
10nF
LOAD CURRENT (A)
V
DD33
GND V
DD25
4700pF
220pF
2200pF
220pF
3883 TA01b
1µF
1µF
*SOME DETAILS OMITTED FOR CLARITY
3886 TA01a
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LTC3886
Table oF conTenTs
Features..................................................... 1
Power Conversion ................................................1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Table of Contents .......................................... 2
Absolute Maximum Ratings.............................. 4
Order Information.......................................... 4
Pin Configuration .......................................... 4
Electrical Characteristics................................. 5
Typical Performance Characteristics ..................10
Pin Functions..............................................13
Block Diagram.............................................15
Operation...................................................16
Overview................................................................. 16
Main Control Loop.................................................. 16
EEPROM ................................................................. 17
Power-Up and Initialization ..................................... 17
Soft-Start................................................................ 18
Time-Based Sequencing......................................... 18
Event-Based Sequencing ........................................ 19
Shutdown ............................................................... 19
Light-Load Current Operation ................................. 19
PWM Loop Compensation......................................20
Switching Frequency and Phase.............................20
Output Voltage Sensing ..........................................20
Output Current Sensing ..........................................20
Input Current Sensing.............................................21
PolyPhase Load Sharing.........................................21
External/Internal Temperature Sense......................21
RCONFIG (Resistor Configuration) Pins..................22
Fault Handling.........................................................23
Status Registers and ALERT Masking.................24
Mapping Faults to FAULT Pins ............................24
Power Good Pins................................................26
CRC Protection ..................................................26
Serial Interface .......................................................26
Communication Protection ................................26
Device Addressing..................................................26
and I
Faults ........................27
Responses to V
OUT
OUT
Output Overvoltage Fault Response ...................27
Output Undervoltage Response .........................27
Peak Output Overcurrent Fault Response...........27
Responses to Timing Faults....................................28
Responses to V OV Faults....................................28
IN
Responses to OT/UT Faults.....................................28
Internal Overtemperature Fault/Warn
Response............................................................28
External Overtemperature and
Undertemperature Fault Response ....................28
Responses to External Faults .................................29
Fault Logging..........................................................29
Bus Timeout Protection ..........................................29
2
Similarity Between PMBus, SMBus and I C
2-Wire Interface......................................................29
PMBus Serial Digital Interface................................30
PMBus Command Summary ............................35
PMBus Commands.................................................35
*Data Format..........................................................40
Applications Information ................................41
Current Limit Programming.................................... 41
+
–
I
and I
Pins......................................... 41
SENSE
SENSE
Low Value Resistor Current Sensing.......................42
Inductor DCR Current Sensing................................43
Slope Compensation and Inductor Peak Current ....44
Inductor Value Calculation ......................................44
Inductor Core Selection ..........................................45
Power MOSFET and Optional Schottky Diode
Selection.................................................................45
C and C
Selection ...........................................46
IN
OUT
Variable Delay Time, Soft-Start and Output
Voltage Ramping ....................................................46
Digital Servo Mode.................................................47
Soft Off (Sequenced Off)........................................48
INTV Regulator....................................................48
CC
Topside MOSFET Driver Supply (C , D ) ................49
B
B
Undervoltage Lockout.............................................50
Fault Indications .....................................................50
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LTC3886
Table oF conTenTs
Open-Drain Pins .....................................................50
Phase-Locked Loop and Frequency
Output Current and Limits ......................................81
Input Current and Limits ....................................83
Temperature............................................................84
External Temperature Calibration........................84
Timing ....................................................................85
Timing—On Sequence/Ramp.............................85
Timing—Off Sequence/Ramp ............................86
Precondition for Restart .....................................87
Fault Response .......................................................87
Fault Responses All Faults..................................87
Fault Responses Input Voltage ...........................88
Fault Responses Output Voltage.........................88
Fault Responses Output Current.........................91
Fault Responses IC Temperature ........................92
Fault Responses External Temperature...............93
Fault Sharing...........................................................94
Fault Sharing Propagation ..................................94
Fault Sharing Response......................................96
Scratchpad .............................................................96
Identification...........................................................97
Fault Warning and Status........................................98
Telemetry..............................................................104
EEPROM Memory Commands.............................. 108
Store/Restore ................................................... 108
Fault Logging.................................................... 109
Fault Log Operation .......................................... 109
Block Memory Write/Read................................ 114
Typical Applications.................................... 115
Package Description ................................... 118
Revision History ........................................ 119
Typical Application ..................................... 120
Related Parts............................................ 120
Synchronization...................................................... 51
Minimum On-Time Considerations..........................52
External Temperature Sense...................................52
Derating EEPROM Retention at Temperature......53
Input Current Sense Amplifier.................................53
External Resistor Configuration Pins (RCONFIG)....54
Voltage Selection................................................54
Frequency Selection ..........................................55
Phase Selection..................................................55
Address Selection Using RCONFIG.....................56
Efficiency Considerations .......................................56
Programmable Loop Compensation .......................57
Checking Transient Response.................................57
PolyPhase Configuration ........................................58
PC Board Layout Checklist .....................................61
PC Board Layout Debugging...................................61
Design Example......................................................63
Additional Design Checks .......................................64
2
Connecting the USB to I C/SMBus/PMBus
Adapter to the LTC3886 In System.........................64
PMBus Communication and Command
Processing..............................................................66
PMBus Command Details ...............................68
Addressing and Write Protect.................................68
General Configuration COMMANDS........................70
On/Off/Margin ........................................................71
ON_OFF_CONFIG ....................................................72
PWM Configuration ................................................73
Voltage....................................................................77
Input Voltage and Limits.....................................77
Output Voltage and Limits..................................78
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LTC3886
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
+
–
V , I , I .............................................. –0.3V to 65V
IN IN IN
Top Gate Transient Voltage (TG0, TG1) .......–0.3V to 71V
BOOST0, BOOST1.......................................–0.3V to 71V
Switch Transient Voltage (SW0, SW1) .......... –5V to 65V
52
50
48 47 46
44 43 42
SW0
TG0
1
2
40 BOOST1
SW1
TG1
39
38
INTV , BG0, BG1, (BOOST0– SW0),
CC
(BOOST1– SW1) .......................................... –0.3V to 6V
+
I
I
4
5
SENSE0
+
–
+
+
+
–
V
, V
, I
, I
,
36
35
34
TSNS1
SENSE0
SENSE0
SENSE1 SENSE0 SENSE1
+
–
TSNS0
V
6
SENSE1
I
I
, EXTV ........................ –0.3V to 15V
................................................... –0.3V to 0.3V
SENSE0 , SENSE1
CC
+
–
V
V
I
7
PGOOD0
SENSE0
53
GND
V
SENSE0
–
8
33 PGOOD1
SENSE0
RUN, SDA, SCL, ALERT............................. –0.3V to 5.5V
+
9
32
31
30
29
I
I
SENSE1
THR1
TH1
ASELn, V
PHAS_CFG, V
, FREQ_CFG,
–
OUTn_CFG
I
10
11
12
SENSE1
.................................. –0.3V to 2.75V
I
V
THR0
DD33
DD25
I
SHARE_CLK
TH0
(V – I ), (V – I )............................ –0.3V to 0.3V
IN
INP
IN
INM
SYNC 13
SCL 14
28 WP
27
PGOOD0, PGOOD1, FAULT, SHARE_CLK,
, I , I , I , V , WP,
V
DD25
I
TH0 TH1 THR0 THR1 DD33
15 16 17 18 19 20 21 22 23 24 25 26
TSNS0, TSNS1, SYNC............................... –0.3V to 3.6V
(EXTV – V ) ......................................................13.2V
CC
IN
INTV Peak Output Current................................100mA
CC
UKG PACKAGE
VARIATION: UKG52(46)
Operating Junction Temperature Range
52-LEAD (7mm × 8mm) PLASTIC QFN
(Notes 2, 15, 16) .............................. –40°C to 125°C*
T
= 125°C, = 31°C/W, = 2°C/W
JA JC
JMAX
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
Storage Temperature Range ................ –65°C to 150°C*
* See Derating EEPROM Retention at Temperature in the Applications
Information section for junction temperatures in excess of 125°C.
Note: Pins omitted to achieve high input voltage rating.
orDer inForMaTion
(http://www.linear.com/product/LTC3886#orderinfo)
LEAD FREE FINISH
LTC3886EUKG#PBF
LTC3886IUKG#PBF
TAPE AND REEL
PART MARKING*
LTC3886UKG
LTC3886UKG
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LTC3886EUKG#TRPBF
LTC3886IUKG#TRPBF
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
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LTC3886
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 16V, EXTVCC = 0V, VRUN0 = 3.3V, VRUN1 = 3.3V
fSYNC = 350kHz (externally driven), and all programmable parameters at factory default unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage
l
V
Input Voltage Range
(Note 12)
(Note 14)
RUN
RUN
4.5
60
V
IN
I
Input Voltage Supply Current
Normal Operation
Q
V
V
= 3.3V, No Caps on TG and BG
= 0V
26
22
mA
mA
V
Undervoltage Lockout Threshold
V
V
Falling
Rising
3.7
3.95
V
V
UVLO
INTVCC
INTVCC
When V > 4.2V
IN
T
Initialization Time
Delay from RESTORE_USER_ALL,
MFR_REST, or V > V Until
35
ms
INIT
INTVCC
UVLO
TON_DELAY Can Begin
Control Loop
V
Range 0 Maximum V
14.0
V
%
OUTR0
OUT
l
Range 0 Set Point Accuracy
Range 0 Resolution
2.0V ≤ V
≤ 13.8V
–0.5
–0.5
0.5
OUT
12
4
Bits
mV
Range 0 LSB Step Size, FSR = 16.38
(Notes 9, 10)
1.0V ≤ V ≤ 6.6V
V
Range 1 Maximum V
7.0
V
%
Bits
mV
OUTR1
OUT
l
l
Range 1 Set Point Accuracy
Range 1 Resolution
0.5
OUT
12
2
Range 1 LSB Step Size, FSR = 8.19V
(Notes 9, 10)
16V < V < 60V
V
V
Line Regulation
Load Regulation
0.02
%/V
LINEREG
IN
l
l
∆V = 1.35V – 0.7V
0.01
–0.01
0.1
–0.1
%
%
LOADREG
ITH
∆V = 1.35V – 2.0V
ITH
g
Resolution
3
5.76
1.00
0.68
5
bits
mmho
mmho
mmho
bits
m0,1
Error Amplifier g
Error Amplifier g
I
I
I
=1.35V
=1.35V
=1.35V
m(MAX)
TH
TH
TH
m(MIN)
Error Amplifier g LSB Step Size
m
R
Resolution
ITHR0,1
Compensation Resistor R
Compensation Resistor R
Input Current
62
0
kΩ
ITHR(MAX)
kΩ
ITHR(MIN)
l
I
V
= 14V
1
2
µA
ISENSE
ISENSE
V
Resolution
3
bits
I(lLIMIT)
l
l
V
Hi Range
Lo Range
68
44
75
50
82
56
mV
mV
ILIM(MAX)
V
Hi Range
Lo Range
37.5
25
mV
mV
ILIM(MIN)
Gate Driver
TG
r
f
TG Transition Time:
Rise Time
Fall Time
(Note 4)
LOAD
LOAD
t
t
C
C
= 3300pF
= 3300pF
30
30
ns
ns
BG
r
f
BG Transition Time:
Rise Time
Fall Time
(Note 4)
LOAD
LOAD
t
t
C
C
= 3300pF
= 3300pF
20
20
ns
ns
TG/BG t
BG/TG t
Top Gate Off to Bottom Gate On Delay Time
Bottom Gate Off to Top Gate On Delay Time
Minimum On-Time
(Note 4) C
(Note 4) C
= 3300pF
10
30
90
ns
ns
ns
1D
LOAD
LOAD
= 3300pF
2D
t
ON(MIN)
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For more information www.linear.com/LTC3886
LTC3886
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 16V, EXTVCC = 0V, VRUN0 = 3.3V, VRUN1 = 3.3V
fSYNC = 350kHz (externally driven), and all programmable parameters at factory default unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OV/UV Output Voltage Supervisor
N
Resolution
9
Bits
V
V
V
V
V
V
V
Range 0 Maximum Threshold
Range 1 Maximum Threshold
Range 0 Step Size, FSR = 16.352V
Range 1 Step Size, FSR = 8.176V
Range 0 Threshold Accuracy
Range 1 Threshold Accuracy
OV Comparator to FAULT Low Time
UV Comparator to FAULT Low Time
14
7
RANGE0
RANGE1
OUSTP0
OUSTP1
THACC0
THACC1
PROPOV1
PROPUV1
V
(Note 10)
32
16
mV
mV
%
l
l
2V < V
1V < V
< 14V
< 7V
2.5
2.5
35
OUT
OUT
%
t
t
V
V
= 10% of Threshold
= 10% of Threshold
µs
µs
OD
OD
100
V
Voltage Supervisor
IN
N
Resolution
9
Bits
V
V
V
V
V
Full-Scale Voltage
Step Size
(Note 11)
4.5
61.32
IN(RANGE)
IN(STP)
120
mV
%
l
l
Threshold Accuracy 12V < V < 60V
3
6
IN(THACCH)
IN(THACCL)
PROP(VIN)
IN
Threshold Accuracy 4.5V < V < 15V
%
IN
t
Comparator Response Time
(VIN_ON and VIN_OFF)
V
= 10% of Threshold
100
µs
OD
Output Voltage Readback
N
Resolution
LSB Step Size
16
250
Bits
µV
V
V
Full-Scale Sense Voltage
Total Unadjusted Error
(Note 10) V
= 0V (Note 8)
> 1.0V
16.384
0.2
V
F/S
RUN
T = 25°C, V
%
%
OUT_TUE
J
OUT
l
l
(Note 8)
0.5
V
Zero-Code Offset Voltage
Conversion Time
500
µV
OS
t
(Note 6)
90
ms
CONVERT
V
IN
Voltage Readback
N
Resolution
(Note 5)
10
Bits
V
V
V
Full-Scale Input Voltage
Total Unadjusted Error
(Note 11)
66.56
F/S
T = 25°C, V > 4.5V
J
0.4
2
%
%
IN_TUE
VIN
l
t
Conversion Time
(Note 6)
90
ms
CONVERT
Output Current Readback
N
Resolution
LSB Step Size
(Note 5)
10
15.26
30.52
61
Bits
µV
µV
µV
µV
+
–
0V ≤ |V
– V
| < 16mV
ISENSE
ISENSE
+
+
+
–
16mV ≤ |V
32mV ≤ |V
64mV ≤ |V
– V
– V
– V
| < 32mV
| < 64mV
| < 100mV
ISENSE
ISENSE
ISENSE
ISENSE
ISENSE
ISENSE
–
–
122
I
I
Full-Scale Output Current
Total Unadjusted Error
Zero-Code Offset Voltage
Conversion Time
(Note 7) R
= 1mΩ
100
A
%
F/S
ISENSE
l
(Note 8) 10mV ≤ V
≤ 100mV
ISENSE
1.5
32
OUT_TUE
V
µV
ms
OS
t
(Note 6)
90
CONVERT
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For more information www.linear.com/LTC3886
LTC3886
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 16V, EXTVCC = 0V, VRUN0 = 3.3V, VRUN1 = 3.3V
fSYNC = 350kHz (externally driven), and all programmable parameters at factory default unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Current Readback
N
Resolution
(Note 5)
10
15.26
30.52
61
Bits
µV
+
+
+
–
–
–
LSB Step Size, Full-Scale Range = 16mV
LSB Step Size, Full-Scale Range = 32mV
LSB Step Size, Full-Scale Range = 64mV
8x Gain, 0V ≤ |I – I | ≤ 5mV
IN IN
4x Gain, 0V ≤ |I – I | ≤ 20mV
2x Gain, 0V ≤ |I – I | ≤ 50mV
µV
IN
IN
µV
IN
IN
+
–
l
l
l
I
I
Total Unadjusted Error (Note 8)
8x Gain, 2.5mV ≤ |I – I | ≤ 5mV
1.6
1.3
1.2
%
%
%
IN_TUE
IIN
IN
+
IN
–
4x Gain, 4mV ≤ |I – I | ≤ 20mV
IN
IN
IN
IN
+
–
2x Gain, 6mV ≤ |I – I | ≤ 50mV
+
–
+
–
= V = 30V
IIN
l
Input Current, I and I
V
= V
2
µA
µV
IN
IN
IN
IIN
V
Zero-Code Offset Voltage
Conversion Time
50
OS
t
(Note 6)
(Note 5)
90
ms
CONVERT
Supply Current Readback
Resolution
N
10
244
Bits
µV
LSB Step Size, Full-Scale Range = 256mV
Total Unadjusted Error
+
l
I
t
20mV ≤ |I – V | ≤ 200mV
2.5
%
CHIP_TUE
CONVERT
IN
IN
Conversion Time
(Note 6)
90
ms
Temperature Readback (T0, T1)
T
Resolution
0.25
°C
RES_T
T0_TUE
External TSNS TUE (Note 8)
l
l
MFR_PWM_MODE_LTC3886[5] = 0
MFR_PWM_MODE_LTC3886[5] = 1
�V
= 72mV (Note 17)
3
7
°C
°C
TSNS
V
V
≤ 1.85mV (Note 17)
TSNS
TI_TUE
Internal TSNS TUE
Update Rate
= 0.0V (Note 8)
1
°C
RUN
t
(Note 6)
90
ms
CONVERT_T
INTV Regulator
CC
l
l
l
V
V
V
V
V
V
V
V
Internal V Voltage No Load
6V < V < 60V
4.8
4.8
4.5
5
5.2
2
V
%
V
INTVCC_VIN
LDO_VIN
CC
IN
INTV Load Regulation
I
CC
= 0mA to 50mA
0.5
5
CC
Internal V Voltage No Load
5.5V < EXTV < 14V
5.2
2
INTVCC_EXT
LDO_EXT
CC
CC
INTV Load Regulation
I
CC
= 0mA to 50mA, EXTV = 12V
0.5
4.7
80
%
V
CC
CC
EXTV Switchover Voltage
EXTV Ramping Positive
4.95
EXT_THRES
EXT_HYS
CC
CC
EXTV Hysteresis Voltage
mV
CC
Regulator
DD33
DD33
LIM
Internal V
Voltage
4.5V < V
3.2
3.3
100
3.5
3.1
3.4
V
mA
V
DD33
INTVCC
I
V
V
V
Current Limit
V
= GND, V = INTV = 4.5V
IN CC
DD33
DD33
DD33
DD33
DD25
V
V
V
V
Overvoltage Threshold
Undervoltage Threshold
DD33_OV
DD33_UV
V
Regulator
DD25
DD25
LIM
Internal V
Voltage
2.5
80
V
DD25
I
V
Current Limit
V
= GND, V = INTV = 4.5V
mA
DD25
IN
CC
Oscillator and Phase-Locked Loop
l
f
Oscillator Frequency Accuracy
SYNC Input Threshold
100kHz < f
< 750kHz Measured
SYNC
10
%
OSC
Falling Edge-to-Falling Edge of SYNC with
SWITCH_FREQUENCY = 100.0 and 750.0
V
V
V
V
Falling
Rising
1
V
V
TH(SYNC)
CLKIN
CLKIN
1.5
l
SYNC Low Output Voltage
I
= 3mA
LOAD
0.2
0.4
5
V
OL(SYNC)
I
SYNC Leakage Current in Slave Mode
0V ≤ V ≤ 3.6V
µA
LEAK(SYNC
PIN
3886fe
7
For more information www.linear.com/LTC3886
LTC3886
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 16V, EXTVCC = 0V, VRUN0 = 3.3V, VRUN1 = 3.3V
fSYNC = 350kHz (externally driven), and all programmable parameters at factory default unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SYNC-0
SYNC to Channel 0 Phase Relationship Based MFR_PWM_CONFIG_LTC3886[2:0] = 0,2,3
0
Deg
Deg
Deg
Deg
on the Falling Edge of Sync and Rising Edge
of TG0
MFR_PWM_CONFIG_LTC3886[2:0] = 5
MFR_PWM_CONFIG_LTC3886[2:0] = 1
MFR_PWM_CONFIG_LTC3886[2:0] = 4,6
60
90
120
SYNC-1
SYNC to Channel 1 Phase Relationship Based MFR_PWM_CONFIG_LTC3886[2:0] = 3
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
on the Falling Edge of Sync and Rising Edge
of TG1
MFR_PWM_CONFIG_LTC3886[2:0] = 0
MFR_PWM_CONFIG_LTC3886[2:0] = 2,4,5
MFR_PWM_CONFIG_LTC3886[2:0] = 1
MFR_PWM_CONFIG_LTC3886[2:0] = 6
EEPROM Characteristics
l
Endurance
(Note 13)
0°C < T < 85°C During EEPROM Write
10,000
10
Cycles
J
Operations
l
l
Retention
(Note 13)
T < 125°C
J
Years
ms
Mass_Write Mass Write Operation Time
STORE_USER_ALL, 0°C < T ≤ 85°C
440
4100
1.35
J
During EEPROM Write Operations
Digital Inputs SCL, SDA, RUNn, FAULTn
l
l
V
V
V
C
Input High Threshold Voltage
Input Low Threshold Voltage
Input Hysteresis
SCL, SDA, RUN, FAULT
SCL, SDA, RUN, FAULT
SCL, SDA
V
V
IH
0.8
IL
0.08
10
V
HYST
PIN
Input Capacitance
10
pF
Digital Input WP
Input Pull-Up Current
I
WP
µA
V
PUWP
Open-Drain Outputs SCL, SDA, FAULTn, ALERT, RUNn, SHARE_CLK, PGOODn
Output Low Voltage = 3mA
Digital Inputs SHARE_CLK, WP
l
V
I
0.4
1.8
OL
SINK
l
l
V
V
Input High Threshold Voltage
Input Low Threshold Voltage
1.5
1.0
V
V
IH
IL
0.6
Leakage Current SDA, SCL, ALERT, RUN
Input Leakage Current
Leakage Current FAULTn, PGOODn
Input Leakage Current
Digital Filtering of FAULTn
Input Digital Filtering FAULTn
Digital Filtering of PGOODn
Output Digital Filtering PG00Dn
Digital Filtering of RUNn
Input Digital Filtering RUNn
PMBus Interface Timing Characteristics
l
l
I
0V ≤ V ≤ 5.5V
5
2
µA
µA
µs
µs
µs
OL
PIN
I
0V ≤ V ≤ 3.6V
GL
PIN
t
3
FAULT
t
60
10
PGOOD
t
RUN
l
l
l
f
t
t
Serial Bus Operating Frequency
10
1.3
0.6
400
kHz
µs
SCL
Bus Free Time Between Stop and Start
BUF
Hold Time After Start Condition. After This
Period, the First Clock Is Generated
µs
HD(STA)
l
l
t
t
t
Repeated Start Condition Setup Time
Stop Condition Setup Time
0.6
0.6
10000
0.9
µs
µs
SU(STA)
SU(STO)
HD(DAT)
Data Hold Time
Receiving Data
Transmitting Data
l
l
0
0.3
µs
µs
3886fe
8
For more information www.linear.com/LTC3886
LTC3886
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 16V, EXTVCC = 0V, VRUN0 = 3.3V, VRUN1 = 3.3V
fSYNC = 350kHz (externally driven), and all programmable parameters at factory default unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
Data Setup Time
Receiving Data
SU,DAT
l
0.1
µs
t
Stuck PMBus Timer Non-Block Reads
Stuck PMBus Timer Block Reads
Measured from the Last PMBus Start Event
32/255
255
ms
ms
TIMEOUT_SMB
l
l
t
t
Serial Clock Low Period
Serial Clock High Period
1.3
0.6
10000
µs
µs
LOW
HIGH
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 8: Part tested with PWM disabled. Evaluation in application
demonstrates capability. TUE (%) = ADC Gain Error (%) + 100 •
[Zero Code Offset + ADC Linearity Error]/Actual Value.
Note 9: All V
commands assume the ADC is used to auto-zero the
OUT
Note 2: The LTC3886 is tested under pulsed load conditions such that T ≈
T . The LTC3886E is guaranteed to meet performance specifications from
A
output to achieve the stated accuracy. LTC3886 is tested in a feedback
loop that servos V to a specified value.
J
OUT
0°C to 85°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3886I is guaranteed over the
Note 10: The maximum programmable V
voltage is 13.8V.
OUT
Note 11: The maximum V voltage is 60V.
IN
Note 12: When V < 6V, INTV must be tied to V .
IN
CC
IN
–40°C to 125°C operating junction temperature range. T is calculated from
J
Note 13: EEPROM endurance is guaranteed by design, characterization
and correlation with statistical process controls. Data retention is
production tested via a high temperature bake at wafer level. The minimum
retention specification applies for devices whose EEPROM has been cycled
less than the minimum endurance specification. The RESTORE_USER_ALL
command (EEPROM read) is valid over the entire operating temperature
range.
the ambient temperature, T , and power dissipation, P , according to the
A
D
following formula:
T = T + (P • )
JA
J
A
D
The maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 14: The LTC3886 quiescent current (I ) equals the I of V plus the
Q
Q
IN
I of EXTV
Q
.
CC
Note 15: The LTC3886 includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
Junction temperature will exceed 125°C when overtemperature protection
is active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 4: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 5: The data format in PMBus is 5 bits exponent (signed) and 11 bits
mantissa (signed). This limits the output resolution to 10 bits though the
internal ADC is 16 bits and the calculations use 32-bit words.
Note 6: The data conversion is done in round robin fashion. All input
signals are continuously converted for a typical latency of 90ms. Unless
the MFR_ADC_CONTROL command is utilized.
Note 16: Write operations above T = 85°C or below 0°C are possible
J
although the Electrical Characteristics are not guaranteed and the EEPROM
will be degraded. Read operations performed at temperatures between
–40°C and 125°C will not degrade the EEPROM. Writing to the EEPROM
above 85°C will result in a degradation of retention characteristics.
Note 7: The IOUT_CAL_GAIN = 1.0mΩ and MFR_IOUT_TC = 0.0. Value as
read from READ_IOUT in amperes.
Note 17: Limits guaranteed by TSNS voltage and current measurements
during test, including ADC readback.
3886fe
9
For more information www.linear.com/LTC3886
LTC3886
Typical perForMance characTerisTics
TA = 25C, VIN = 16V, EXTVCC = 0V, unless otherwise noted.
Efficiency vs Load Current,
VOUT = 12V
Efficiency vs Load Current,
VOUT = 5V
Efficiency and Power Loss
vs Input Voltage
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
98
97
96
95
94
10
8
EFFICIENCY
POWER LOSS
CCM
DCM
CCM
DCM
6
V
V
f
= 48V
V
V
f
= 48V
IN
IN
4
= 12V
= 5V
OUT
V
f
= 12V
OUT
IN
SW
= 150kHz
= 150kHz
SW
= 150kHz
SW
L = 6.8µH
L = 6.8µH
L = 6.8µH
DCR = 1.86mΩ
DCR = 1.86mΩ
DCR = 1.86mΩ
2
0.01
0.1
1
10
100
0.01
0.1
1
10
100
18
28
38
48
LOAD CURRENT (A)
LOAD CURRENT (A)
V
(V)
IN
3886 G01
3883 G02
3886 G03
EXTVCC Switchover
vs Temperature
Load Step
(Forced Continuous Mode)
Load Step
(Pulse-Skipping Mode)
4.710
4.708
4.706
4.704
4.702
4.700
I
I
LOAD
LOAD
5A/DIV
5A/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
3886 G06
3886 G05
V
V
= 12V
50µs/DIV
V
V
= 12V
50µs/DIV
IN
OUT
IN
OUT
= 1.8V
= 1.8V
0.3A TO 5A STEP
0.3A TO 5A STEP
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
3886 G04
Inductor Current at Light Load
Start-Up into a Pre-Biased Load
Soft-Start Ramp
FORCED
CONTINUOUS
MODE
RUN
2V/DIV
RUN
2V/DIV
2A/DIV
V
OUT
V
OUT
1V/DIV
1V/DIV
PULSE-SKIPPING
MODE
2A/DIV
3886 G07
3886 G08
3886 G09
V
V
LOAD
= 12V
1µs/DIV
t
= 10ms
= 5ms
DELAY
5ms/DIV
t
t
= 10ms
= 5ms
5ms/DIV
IN
RISE
RISE
DELAY
= 1.8V
t
OUT
I
= 100µA
V
= 2V
OUT
3886fe
10
For more information www.linear.com/LTC3886
LTC3886
Typical perForMance characTerisTics
TA = 25C, VIN = 16V, EXTVCC = 0V, unless otherwise noted.
Regulated Output Voltage
vs Temperature
Maximum Current Sense Threshold
vs Duty Cycle, VOUT = 0V
Soft-Off Ramp
0.5025
0.5020
0.5015
0.5010
0.5005
0.5000
0.4995
0.4990
0.4985
0.4980
0.4975
55
54
53
52
51
50
49
48
47
46
45
50mV SENSE CONDITION
RUN
2V/DIV
V
OUT
1V/DIV
3886 G10
t
t
= 5ms
DELAY
5ms/DIV
FALL
= 10ms
–50
50
100 125
150
0
30
50
70
90
–25
0
25
75
TEMPERATURE (°C)
DUTY CYCLE (%)
3886 G11
3886 G12
SHARE_CLK Frequency
vs Temperature
Quiescent Current vs Temperature
VOUT Measurement Error vs VOUT
110
105
100
95
25.0
24.5
24.0
23.5
0.6
0.4
0.2
0
23.0
22.5
22.0
–0.2
–0.4
–0.6
90
–50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
50
TEMPERATURE (°C)
100 125
8
12
14
–50 –25
0
25
75
0
2
4
6
10
V
(V)
OUT
3883 G13
3886 G14
3886 G15
VOUT Command INL
VOUT Command DNL
INTVCC Line Regulation
0.8
0.6
0.4
0.2
5.25
5.00
4.75
4.50
4.25
4.00
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
0
–0.2
–0.4
0
20
30
(V)
40
50
60
0
4
8
12
16
0
4
8
12
16
10
V
IN
V
(V)
V
(V)
OUT
OUT
3886 G18
3886 G16
3886 G17
3886fe
11
For more information www.linear.com/LTC3886
LTC3886
Typical perForMance characTerisTics
TA = 25C, VIN = 16V, EXTVCC = 0V, unless otherwise noted.
VOUT OV Threshold
vs Temperature (1V Target)
VOUT OV Threshold
vs Temperature (5V Target)
VOUT OV Threshold
vs Temperature (12V Target)
1.010
1.005
1.000
0.995
5.02
5.01
5.01
5.00
5.00
4.99
12.03
12.02
12.01
12.00
11.99
11.98
0.990
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3886 G19
3886 G20
3886 G21
External Temperature Error
vs Temperature
IOUT Error vs IOUT
IIN Error vs IIN
1.0
0.8
8
6
5
4
3
2
0.6
4
0.4
2
0.2
0
0
1
0
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
–1
–2
–3
10
OUTPUT CURRENT (A)
–50 –25
0
25
50
75 100 125
0
5
15
20
1
2
0
3
TEMPERATURE (°C)
INPUT CURRENT (A)
3886 G22
3886 G23
3886 G24
DC Output Current Matching in a
2-Phase System (LTC3886)
Dynamic Current Sharing During a
Load Transient in a 4-Phase System
Dynamic Current Sharing During a
Load Transient in a 4-Phase System
25
20
15
CURRENT
5A/DIV
CURRENT
5A/DIV
10
5
CHAN 0
CHAN 1
0
3886 G26
3886 G27
20
TOTAL CURRENT (A)
0
5
10 15
25 30 35 40
V
V
SW
= 48V
OUT
= 150kHz
10µs/DIV
= 3mΩ
V
V
= 48V
OUT
= 150kHz
SW
10µs/DIV
IN
IN
= 5V
= 5V
f
f
3886 G25
L = 6.8µH; R
0A TO 10A LOAD STEP
L = 6.8µH; R
10A TO 0A LOAD STEP
= 3mΩ
SENSE
SENSE
3886fe
12
For more information www.linear.com/LTC3886
LTC3886
pin FuncTions
SW0/SW1 (Pins 1, 39): Switch Node Connections to
SCL (Pin 14): Serial Bus Clock Input. Open-drain output,
can hold the output low if clock stretching is enabled. A
pull-up resistor to 3.3V is required in the application.
Inductors. Voltage swings at the pins are from a Schottky
diode (external) voltage drop below ground to V .
IN
TG0/TG1 (Pins 2, 38): Top Gate Driver Outputs. These are
SDA (Pin 15): Serial Bus Data Input and Output. A pull-up
the outputs of floating drivers with a voltage swing equal
resistor to 3.3V is required in the application.
to INTV superimposed on the switch node voltages.
CC
ALERT (Pin 16): Open-Drain Digital Output. Connect the
SMBALERT signal to this pin. A pull-up resistor to 3.3V
is required in the application.
+
+
I
/I
(Pins 4, 9): Current Sense Comparator
SENSE0 SENSE1
Inputs. The(+)inputtothecurrentcomparatorisnormally
connected to the DCR sensing network or current sensing
resistor.
FAULT0/FAULT1 (Pins 17, 18): Digital Programmable
General Purpose Inputs and Outputs. Open-drain output.
A pull-up resistor to 3.3V is required in the application.
–
–
I
/I
(Pins5,10):CurrentSenseComparator
SENSE0 SENSE1
Inputs. The (–) input is connected to the output.
RUN0/RUN1 (Pins 19, 20): Enable Run Input and Output.
Logic high on this pin enables the controller. Open-drain
output holds the pin low until the LTC3886 is out of reset.
This pin should be driven by an open-drain digital output.
A pull-up resistor to 3.3V is required in the application.
TSNS0/TSNS1 (Pins 6, 36): External Diode Temperature
Sense. Connect to the anode of a diode-connected PNP
transistor in order to sense remote temperature. Directly
connect the cathode using a separate ground return path
to Pin 53 of the LTC3886. A bypass capacitor between the
anodeandcathodemustbelocatedincloseproximitytothe
transistor. If external temperature sense elements are not
installed,shortpintogroundandsettheUT_FAULT_LIMIT
to –275°C and the UT_FAULT_RESPONSE to ignore.
ASEL0/ASEL1 (Pin 21/Pin 22): Serial Bus Address Select
Inputs. Connect optional 1% resistor dividers between
V
and GND to these pins to select the serial bus
DD25
interface address. Refer to the Applications Information
section for more detail. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
+
+
V
/V
(Pins 7, 35): Positive Output Voltage
SENSE1
SENSE0
Sense Inputs.
V
/V
(Pins 23, 24): Output Voltage
OUT_CFG1
OUT_CFG0
–
V
(Pin 8): Channel 0 Negative Output Voltage
Select Pins. Connect a 1% resistor divider between the
SENSE0
Sense Input.
chip V , V and GND in order to select output
DD25 OUT_CFG
voltage. If the pin is left open, the IC will use the value
programmed in the EEPROM. Refer to the Applications
Information section for more detail. Minimize capacitance
when the pin is open to assure accurate detection of the
pin state.
I
/I
(Pins 11, 32): Loop Compensation Nodes.
THR0 THR1
I
/I
(Pins 12, 31): Current Control Threshold and
TH0 TH1
Error Amplifier Compensation Nodes. Each associated
channel’scurrentcomparatortrippingthresholdincreases
with its I voltage.
TH
FREQ_CFG (Pin 25): Frequency Select Pin. Connect a
SYNC (Pin 13): External Clock Synchronization Input and
Open-Drain Output Pin. If an external clock is present at
this pin, the switching frequency will be synchronized to
the external clock. If clock master mode is enabled, this
pin will pull low at the switching frequency with a 500ns
pulsewidthtoground.Aresistorpull-upto3.3Visrequired
in the application.
1% resistor divider between the chip V
FREQ_CFG
DD25
and GND in order to select switching frequency. If the pin
is left open, the IC will use the value programmed in the
EEPROM. Refer to the Applications Information section
formoredetail. Minimizecapacitancewhenthepinisopen
to assure accurate detection of the pin state.
3886fe
13
For more information www.linear.com/LTC3886
LTC3886
pin FuncTions
PHAS_CFG (Pin 26): Phase Configuration Input. Connect
an optional 1% resistor divider between V
to this pin to configure the phase of each PWM channel
relative to SYNC. Refer to the Applications Information
section for more detail. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
BG0/BG1 (Pins 50, 42): Bottom Gate Driver Outputs. This
and GND
pin drives the gates of the bottom N-channel MOSFET
DD25
between GND and INTV .
CC
EXTV (Pin 43): External power input to an internal LDO
CC
connected to INTV . This LDO supplies INTV power
CC
CC
bypassing the internal LDO powered from V whenever
IN
V
DD25
(Pin 27): Internally Generated 2.5V Power Sup-
EXTV is higher than 4.7V. See EXTV connection in
CC CC
ply Output. Bypass this pin to GND with a low ESR 1μF
capacitor. Do not load this pin externally except for the
resistor dividers needed for the LTC3886 resistor con-
figuration pins.
the Applications Information Section. Do not float or
exceed 14V on this pin. Decouple this pin to GND with a
minimum of 4.7μF low ESR tantalum or ceramic capaci-
tor. If the EXTV pin is not used, tie the pin to GND. The
CC
EXTV pin may be connected to a higher voltage than
CC
WP (Pin 28): Write Protect Pin Active High. An internal
the V pin. If the EXTV pin is tied to an output of the
IN
CC
10µA current source pulls the pin to V . If WP is high,
DD33
the PMBus writes are restricted.
controller and the external load can pull the output below
–0.3V, a Schottky diode from GND to EXTV must be
CC
SHARE_CLK (Pin 29): Share Clock, Bidirectional Open-
Drain Clock Sharing Pin. Nominally 100kHz. Used to
synchronize the timing between multiple LTC controllers.
Tie all the SHARE_CLK pins together. All LTC controllers
will synchronize to the fastest clock. A pull-up resistor of
used to protect the EXTV pin.
CC
INTV (Pin44):InternalRegulator5VOutput.Thecontrol
CC
circuits are powered from this voltage. Decouple this pin
to GND with a minimum of 4.7μF low ESR tantalum or
ceramic capacitor.
5.49k to V
is required. A pull-up resistor to 3.3V is
DD33
–
required in the application.
I
(Pin 46): Negative Input of High Side Current Sense
IN
Amplifier.
V
(Pin 30): Internally Generated 3.3V Power Supply
DD33
+
Output. BypassthispintoGNDwithalowESR1μFcapaci-
I
(Pin 47): Positive Input of High Side Current Sense
IN
tor. Do not load this pin with external current.
Amplifier.
PGOOD0/PGOOD1 (Pins 34, 33): Power Good Indicator
Outputs. Open-drain logic output that is pulled to ground
when the output exceeds OV/UV thresholds. The output
is deglitched by an internal 60μs filter. A pull-up resistor
to 3.3V is required in the application.
V (Pin 48): Main Input Supply. Decouple this pin to GND
IN
with a capacitor (0.1µF to 1µF). For applications where
the main input power is 5V, tie the V and INTV pins
IN
CC
together. If the input current sense amplifier is not used,
+
–
this pin must be shorted to the I and I pins.
IN
IN
BOOST1/BOOST0 (Pins 40, 52): Boosted Floating Driver
Supplies. The (+) terminal of the bootstrap capacitor con-
nects to this pin. This pin swings from a diode voltage
GND (Exposed Pad Pin 53): Ground. All small-signal and
compensationcomponentsshouldconnecttothisground,
at one point.
drop below INTV up to V + INTV .
CC
IN
CC
3886fe
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For more information www.linear.com/LTC3886
LTC3886
block DiagraM
R
IINSNS
+
–
I
IN
I
IN
V
47
46
EXTV
43
IN
CC
R
VIN
V
48
EXTV
CC
IN
+
C
VCC
C
IN
5V REG
–
INTV
44
CC
+
OV
UV
INTV
CC
PGOOD0
34
PGOOD
V
DD33
30
3.3V
SUBREG
V
DD33
D
B
BOOST0
52
S
R
PWM_CLOCK
Q
C
TG0
2
B
I
I
REV
3k
CMP
xR
yR
R
–
+
M1
FCNT
+
–
SW0
ON
UV
1
+
R
SWITCH
LOGIC
I
I
SENSE
4
REV
UVLO
SS
AND
ANTI-
SHOOT-
THROUGH
–
SENSE
5
V
OUT
I
RANGE SELECT
HI: 1:1
LO: 1:1.5
+
LIM
C
RUN
OV
OUT
BG0
50
M2
C
VCC
SLOPE
COMPENSATION
+
–
–
+
R
4R
4R
+
–
+
8
INTV
CC
UVLO
–
+
+
–
V
V
SENSE
16-BIT
ADC
–
+
–
8:1
+
AO
GM
ACTIVE
CLAMP
I
DAC
LIM
(3 BITS)
MUX
–
+
SENSE
7
R
I
–
+
TH0
PWM0
PWM1
–
+
12
2µA
30µA
–
C
C1
R
TH
I
THR0
11
TSNS0
6
EA
UV
OV
C
TMUX
4R
C2
–
–
–
–
+
+
+
+
GND
53
GND
R
GND
PHASE DET
13 SYNC
9-BIT
IN_ON
THRESHOLD DAC
12-BIT
SET POINT
DAC
9-BIT
UV
9-BIT
OV
V
M2
GND
V
CO
DAC
DAC
PWM
CLOCK
PHASE SELECTOR
CLOCK DIVIDER
V
DD33
V
DD25
V
V
V
STBY
DD33
SHARE_CLK
WP
29
28
2.5V
SUBREG
27
V
DD25
1.22V
PMBus
INTERFACE
(400kHz
SLAVE
MISO
DD33
COMPARE
REF
SCL 14
COMPATIBLE)
GND
SDA
15
16
CLK MOSI
MASTER
MAIN
OSC
(32MHz)
ALERT
3
26 PHAS_CFG
SINC
UVLO
CONTROL
FREQ_CFG
25
23
CONFIG
DETECT
RUN0
19
17
V
OUT0_CFG
CHANNEL
TIMING
MANAGEMENT
21 ASEL0
PROGRAM
ROM
RAM
EEPROM
FAULT0
SYNC
22 ASEL1
3886 F01
Figure 1. Block Diagram, One of Two Channels (CH0) Shown
3886fe
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For more information www.linear.com/LTC3886
LTC3886
operaTion
OVERVIEW
n
n
Internal Die Temperature
The LTC3886 is a dual channel/dual phase, constant fre-
quency, analog current mode controller for DC/DC step-
down applications with a digital interface. The LTC3886
digitalinterfaceiscompatiblewithPMBuswhichsupports
bus speeds of up to 400kHz. A typical application circuit
is shown on the first page of this data sheet.
External System Temperature via Optional Diode
Sense Elements
n
n
n
n
n
Average Output Current
Average Output Voltage
Average Input Voltage
Average Input Current
Major features include:
n
Programmable Output Voltage
Configurable, Latched and Unlatched Individual Fault
and Warning Status
n
n
n
n
n
n
n
n
n
Programmable Input Voltage Comparator
Programmable Current Limit
IndividualchannelsareaccessedthroughthePMBususing
the PAGE command, i.e., PAGE 0 or 1.
Programmable Switching Frequency
Programmable OV and UV Comparators
Programmable On and Off Delay Times
Programmable Output Rise/Fall Times
Programmable Loop Compensation
Dedicated Power Good Pin for Each Channel
Fault reporting and shutdown behavior are fully configu-
rableusingtheFAULTnoutputs. AdedicatedpinforALERT
is provided. The shutdown operation also allows all faults
to be individually masked and can be operated in either
unlatched (retry) or latched modes.
Individual status commands enable fault reporting over
the serial bus to identify the specific fault event. Fault or
warning detection includes the following:
Phase-Locked Loop for Synchronous, PolyPhase
Operation (2, 3, 4 or 6 Phases)
n
n
n
n
n
n
Output Undervoltage/Overvoltage
Input Undervoltage/Overvoltage
Input and Output Overcurrent
Internal Overtemperature
n
Input and Output Voltage/Current, and Temperature
Telemetry
n
n
n
n
Fully Differential Remote Sense on Channel 0
Integrated Gate Drivers
External Overtemperature
Nonvolatile Configuration Memory with ECC
Communication, Memory or Logic (CML) Fault
Optional External Configuration Resistors for Key
Operating Parameters
MAIN CONTROL LOOP
n
Optional Time-Base Interconnect for Synchronization
Between Multiple Controllers
TheLTC3886isaconstant-frequency,current-modestep-
down controller that operates at a user-defined relative
phasing. During normal operation the top MOSFET is
turnedonwhentheclockforthatchannelsetstheRSlatch,
and turned off when the main current comparator, I
resets the RS latch. The peak inductor current at which
n
n
n
Fault Logging
WP Pin to Protect Internal EEPROM Configuration
,
CMP
Standalone Operation After User Factory Configura-
tion
I
I
resetstheRSlatchiscontrolledbythevoltageonthe
pin which is the output of the error amplifier, EA. The
CMP
TH
n
PMBus Version 1.2, 400kHz Compliant Interface
EAnegativeterminalisequaltotheV
voltagedivided
SENSE
The PMBus interface provides access to important power
management data during system operation including:
by 16 (8 if range = 1). The positive terminal of the EA is
3886fe
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For more information www.linear.com/LTC3886
LTC3886
operaTion
connected to the output of a 12-bit DAC with values
ranging from 0V to 1.024V. The output voltage, through
feedback of the EA, will be regulated to 16 times the DAC
output (8 times if range = 1). The DAC value is calculated
bytheparttosynthesizetheusersdesiredoutputvoltage.
Theoutputvoltageisprogrammedbytheusereitherwith
the resistor configuration pins detailed in Table 3 or by
(PWM channels off). At that point the device will respond
at special address 0x7C, which is activated only after an
invalid CRC has been detected. The chip will also respond
at the global addresses 0x5A and 0x5B, but use of these
addresses when attempting to recover from a CRC issue
is not recommended. All power supply rails associated
with either PWM channel of a device reporting an invalid
CRC should remain disabled until the issue is resolved.
the V
command (either from EEPROM, or by PMBus
OUT
command). Refer to the PMBus command section of the
data sheet or the PMBus specification for more details.
The output voltage can be modified by the user at any
time with a PMBus VOUT_COMMAND. This command
will typically have a latency less than 10ms.The user
is encouraged to reference the PMBus Power System
Management Protocol Specification to understand how to
program the LTC3886. This specification can be found at:
LTC recommends that the EEPROM not be written when
die temperature is greater than 85°C. If internal die tem-
perature exceeds 130°C, all EEPROM operations except
RESTORE_USER_ALL and MFR_RESET are disabled. Full
EEPROM operation is not re-enabled until die temperature
falls below 125°C. Refer to the Applications Information
section for equations to predict retention degradation due
to elevated operating temperatures.
http://www.pmbus.org/specs.html
See the Applications Information section or contact the
factoryfordetailsonefficientin-systemEEPROMprogram-
ming, including bulk EEPROM programming, which the
LTC3886 also supports.
Continuing the basic operation description, the current
mode controller will turn off the top gate when the peak
current is reached. If the load current increases, V
SENSE
will slightly droop with respect to the DAC reference.
This causes the I voltage to increase until the average
TH
POWER-UP AND INITIALIꢀATION
inductor current matches the new load current. After the
top MOSFET has turned off, the bottom MOSFET is turned
on. In continuous conduction mode, the bottom MOSFET
stays on until the end of the switching cycle.
The LTC3886 is designed to provide standalone supply
sequencingandcontrolledturn-onandturn-offoperation.
It can operate from a single V input supply (4.5V to 60V)
IN
whilethreeon-chiplinearregulatorsgenerateinternal2.5V,
3.3V and 5V. If V does not exceed 6V, and the EXTV
IN
CC
IN
EEPROM
pin is not driven by an external supply, the INTV and V
CC
The LTC3886 contains internal EEPROM, also referred to
asNVM(nonvolatilememory),witherrorcorrectioncoding
(ECC) to store user configuration settings and fault log
information. EEPROM endurance and retention for user
space and fault log pages are specified in the Absolute
MaximumRatingsandElectricalCharacteristicstable.The
LTC3886 EEPROM also contains a manufacturing section
that has internal redundancy.
pins must be tied together. The LTC3886 EXTV pin can
CC
driven by an external supply to improve efficiency of the
circuit and minimize power on the LTC3886. The EXTV
pin must exceed approximately 4.8V before the INTV
CC
CC
voltage LDO operates from the EXTV pin. To minimize
CC
application power, the EXTV pin can be supplied by a
CC
switching regulator, or an output of the LTC3886. The
EXTV pin voltage may exceed the V pin voltage. The
CC
IN
controllerconfigurationisinitializedbyaninternalthreshold
TheintegrityoftheentireonboardEEPROMischeckedwith
a CRC calculation each time its data is to be read, such as
after a power-on reset or execution of a RESTORE_USER_
ALL command. If a CRC error occurs, the CML bit is set in
the STATUS_BYTE and STATUS_WORD commands, the
EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC
command is set, and the ALERT and RUN pins pulled low
based UVLO where V must be approximately 4.2V and
IN
the 5V, 3.3V and 2.5V linear regulators must be within
approximately 20% of the regulated values. A PMBus
RESTORE_USER_ALL or MFR_RESET command forces
this same initialization.
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LTC3886
operaTion
Duringinitialization,theexternalconfigurationresistorsare
identifiedand/orcontentsoftheEEPROMarereadintothe
controller’scommands.TheBGn,TGn,PGOODnandRUNn
pins are held low. The FAULTn pins are in high impedance
mode. The LTC3886 will use the contents of Tables 12 to
15 to determine the resistor defined parameters. See the
ResistorConfigurationsectionformoredetail.Theresistor
configuration pins only control some of the preset values
of the controller. The remaining values are programmed
in EEPROM either at the factory or by the user.
the respective RUN pins together and to connect all the
respective SHARE_CLK pins together and pull up to V
DD33
witha10kresistor.Thisassuresallchipsbeginsequencing
at the same time and use the same time base.
After the RUNn pin releases and prior to entering a
constant output voltage regulation state, the LTC3886
performs a monotonic initial ramp or “soft-start”. Soft-
start is performed by actively regulating the load voltage
while digitally ramping the target voltage from 0V to the
commanded voltage set-point. Once the LTC3886 is
commanded to turn on, (after power up and initialization)
the controller waits for the user specified turn-on delay
(TON_DELAY) prior to initiating this output voltage ramp.
The rise time of the voltage ramp can be programmed us-
ing the TON_RISE command to minimize inrush currents
associated with the start-up voltage ramp. The soft-start
feature is disabled by setting the value of TON_RISE to
any value less than 0.25ms. The LTC3886 PWM always
uses discontinuous mode during the TON_RISE opera-
tion. In discontinuous mode, the bottom gate is turned
off as soon as reverse current is detected in the inductor.
This will allow the regulator to start up into a pre-biased
load. When the TON_MAX_FAULT_LIMIT is reached, the
part transitions to continuous mode, if so programmed.
If TON_MAX_FAULT_LIMIT is set to zero, there is no time
limit and the part transitions to the desired conduction
If the configuration resistors are not inserted or if the
ignoreRCONFIGbitisasserted(bit6oftheMFR_CONFIG_
ALL_LTC3886 configuration command), the LTC3886
will use only the contents of EEPROM to determine the
DC/DC characteristics. The ASEL0 and ASEL1 values read
at power-up or reset are always respected unless the pins
are open. See the Applications Information section for
more detail.
After the part has initialized, an additional comparator
monitors V . The VIN_ON threshold must be exceeded
IN
before the output power sequencing can begin. After V
IN
is initially applied, the part will typically require 70ms to
initializeandbegintheTON_DELAYtimer.Thereadbackof
voltages and currents require an additional 0ms to 90ms.
SOFT-START
mode after TON_RISE completes and V
has exceeded
OUT
theVOUT_UV_FAULT_LIMITandIOUT_OCisnotpresent.
The part must enter the run state prior to soft-start. The
RUNpinisreleasedbytheLTC3886afterthepartinitializes
and V is greater than the VIN_ON threshold. If multiple
TIME-BASED SEQUENCING
IN
LTC3886s are used in an application, they all hold their
The default mode for sequencing the output on and off is
timebased.TheoutputisenabledafterwaitingTON_DELAY
amount of time following either the RUNn pin going high,
respective run pins low until all devices initialize and
V exceeds the VIN_ON threshold for every device. The
IN
SHARE_CLK pin assures all the devices connected to the
a PMBuscommand to turnon, orthe V pin voltage rising
IN
signalusethesametimebase.TheSHARE_CLKpinisheld
aboveapreprogrammedvoltage.Offsequencingishandled
in a similar way. To assure proper sequencing, make sure
allICsconnecttheSHARE_CLKpinstogetherandRUNpins
together. IftheRUNpinscannotbeconnectedtogetherfor
some reason, set bit 2 of MFR_CHAN_CONFIG_LTC3886
to a 1. This bit requires the SHARE_CLK pin to be clocking
before the power supply output can start. When the RUNn
pin is pulled low, the LTC3886 will hold the pin low for the
MFR_RESTART_DELAY. The minimum MFR_RESTART_
low until the part has initialized after V is applied and V
IN
IN
exceeds the VIN_ON threshold. The LTC3886 can be set
to turn off (or remain off) if SHARE_CLK is low (set bit 2
of MFR_CHAN_CONFIG_LTC3886 to a 1). This allows the
user to assure synchronization across numerous LTC ICs
even if the RUN pins can not be connected together due
to board constraints. In general, if the user cares about
synchronization between chips it is best to connect all
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LTC3886
operaTion
DELAY is TOFF_DELAY + TOFF_FALL + 136ms. This delay
assures proper sequencing of all rails. The LTC3886 cal-
culates this delay internally and will not process a shorter
delay. However, a longer commanded MFR_RESTART_
DELAY will be used by the part. The maximum allowed
value is 65.52 seconds.
VIN_OFF threshold or FAULTn pulled low externally (if the
MFR_FAULT_RESPONSE is set to inhibit). Under these
conditions the power stage is disabled in order to stop
the transfer of energy to the load as quickly as possible.
The shutdown state can be entered from the soft-start or
active regulation states either through user intervention
(de-asserting RUN or the PMBus OPERATION command)
or in response to a detected fault or an external fault via
the bidirectional FAULTn pin, or loss of SHARE_CLK (if
bit 2 of MFR_CHAN_CONFIG_LTC3886 is set to a 1) or
EVENT-BASED SEQUENCING
The PGOODn pin is be asserted when the output UV
thresholdisexceeded.ItispossibletofeedthePGOODnpin
from one LTC3886 into the RUN pin of the next LTC3886
in the sequence. This can be implemented across multiple
LTC3886s. If a fault in the string of rails is detected, only
the faulted rail and downstream rails will fault off. The
rails in the string of devices in front of the faulted rail will
remain on unless commanded off.
V falling below the VIN_OFF threshold.
IN
Inretrymode,thecontrollerrespondstoafaultbyshutting
down and entering the inactive state for a programmable
delay time (MFR_RETRY_DELAY). This delay minimizes
the duty cycle associated with autonomous retries if the
faultthatcausedtheshutdowndisappearsoncetheoutput
is disabled. The retry delay time is determined by the
longer of the MFR_RETRY_DELAY command or the time
requiredfortheregulatedoutputtodecaybelow12.5%of
the programmed value. If multiple outputs are controlled
by the same FAULTn pin, the decay time of the faulted
outputdeterminestheretrydelay.Ifthenaturaldecaytime
of the output is too long, it is possible to remove the volt-
age requirement of the MFR_RETRY_DELAY command
by asserting bit 0 of MFR_CHAN_CONFIG_LTC3886.
Alternatively, the controller can be configured so that it
remainslatched-offfollowingafaultandclearingrequires
user intervention such as toggling RUN or commanding
the part OFF then ON.
Event-Based Sequencing by Cascading PGOODs Into RUN Pins
RUN 0
PG0OD0
START
LTC3886
RUN 1
PGOOD1
RUN 0
RUN 1
PGOOD0
PGOOD1
LTC3886
3886 F02
TO NEXT CHANNEL
IN THE SEQUENCE
Figure 2. Event (Voltage) Based Sequencing
LIGHT-LOAD CURRENT OPERATION
SHUTDOWN
The LTC3886 has two PWM modes of operation, discon-
tinuous conduction mode or forced continuous conduc-
tionmode.ModeselectionisdoneusingtheMFR_PWM_
MODE_LTC3886command(discontinuousconductionis
alwaysthestart-upmode,forcedcontinuousisthedefault
runningmode).
The LTC3886 supports two shutdown modes. The first
mode is continuous conduction mode, with user-defined
turn-off delay (TOFF_DELAY) and ramp down rate (TOFF_
FALL). The controller will draw current from the load to
force TOFF_FALL. The second mode is discontinuous
conduction mode. In discontinuous conduction mode the
controller will not draw current from the load and the fall
timewillbesetbytheoutputcapacitanceandloadcurrent.
If a controller is enabled for discontinuous conduction op-
eration, the inductor current is not allowed to reverse. The
reverse current comparator, I , turns off the bottom gate
The other shutdown mode occurs in response to a fault
condition or loss of SHARE_CLK (if bit 2 of MFR_CHAN_
REV
external MOSFET just before the inductor current reaches
zero, preventing it from reversing and going negative.
CONFIG_LTC3886 is set to a 1) or V falling below the
IN
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LTC3886
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Thus, the controller can operate in discontinuous opera-
tion. In forced continuous operation, the inductor current
is allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined solely
devices is automatically elected to provide clocking, and
the others disable their SYNC outputs.
The LTC3886 will automatically accept an external
SYNC input, disabling its own SYNC drive if necessary.
Whether configured to drive SYNC or not, the LTC3886
can continue PWM operation using its own internal
oscillator if an external clock signal is subsequently lost.
The device can also be programmed to always require
an external oscillator for PWM operation by setting bit 4
of MFR_CONFIG_ALL_LTC3886. The status of the SYNC
driver circuit is indicated by bit 10 of MFR_PADS.
by the voltage on the I pin. In this mode, the efficiency
TH
at light loads is lower than in discontinuous conduction
operation.However,continuousmodeexhibitsloweroutput
ripple and less interference with audio circuitry. Forced
continuous conduction mode may result in reverse induc-
tor current, which can cause the input supply to boost.
The VIN_OV_FAULT_LIMIT can detect this and turn off
the offending channel. However, this fault is based on an
ADC read and can take up to 90ms to detect. If there is a
concern about the input supply boosting, keep the part in
discontinuous conduction.
The MFR_PWM_CONFIG_LTC3886 command can be
usedtoconfigurethephaseofeachchannel.Desiredphase
can also be set from EEPROM or external configuration
resistors as outlined in Table 5. Designated phase is
the relationship between the falling edge of SYNC and
the internal clock edge that sets the PWM latch to turn
on the top power switch. Additional small propagation
delays to the PWM control pins will also apply. Both
channels must be off before the FREQUENCY_SWITCH
and MFR_PWM_CONFIG_LTC3886 commands can be
written to the LTC3886.
PWM LOOP COMPENSATION
The internal PWM loop compensation resistors R
of the LTC3886 can be adjusted using bit[4:0] of the
MFR_PWM_COMP command.
ITHn
ThetransconductanceoftheLTC3886PWMerroramplifiercan
beadjustedusingbit[7:5]oftheMFR_PWM_COMPcommand.
The phase relationships and frequency are independent
of each other, providing numerous application options.
Multiple LTC3886 ICs can be synchronized to realize
a PolyPhase array. In this case the phases should be
separated by 360/n degrees, where n is the number of
phases driving the output voltage rail.
RefertotheProgrammableLoopCompensationsubsection
in the Applications Information section for further details.
SWITCHING FREQUENCY AND PHASE
The switching frequency of the PWM can be established
with an internal oscillator or an external time base. The
internal phase-locked loop (PLL) synchronizes PWM
control to this timing reference with proper phase rela-
tion, whether the clock is provided internally or externally.
The device can also be configured to provide the master
clock to other ICs through PMBus command, EEPROM
setting, or external configuration resistors as outlined in
Tables 4 and 5.
OUTPUT VOLTAGE SENSING
The channel 0 differential amplifier allows remote, differ-
ential sensing of the load voltage with V
pins. The
SENSE0n
) is referenced to GND. The
channel 1 sense pin (V
SENSE1
(telemetry) ADC is fully differential and makes measure-
ments of channels 0 and 1 output voltages at the V
SENSE0n
andV
/GNDpins,respectively.Themaximumallowed
SENSE1
+
–
differential sense voltage for V
to V
is 14V.
As clock master, the LTC3886 will drive its open-drain
SYNC pin at the selected rate with a pulse width of 500ns.
SENSE0
SENSE0
An external pull-up resistor between SYNC and V
DD33
OUTPUT CURRENT SENSING
is required in this case. Only one device connected to
SYNC should be designated to drive the pin. If multiple
LTC3886s programmed as clock masters are wired to the
same SYNC line with a pull-up resistor, just one of the
For DCR current sense applications, a resistor in series
with a capacitor is placed across the inductor. In this
configuration, the resistor is tied to the FET side of the
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LTC3886
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inductor while the capacitor is tied to the load side of
the inductor as shown in Figure 3. If the RC values are
chosensuchthattheRCtimeconstantmatchestheinductor
time constant (L/DCR, where DCR is the inductor series
IIN_CAL_GAIN command. The resulting measured power
stage current is returned by the READ_IIN command.
The LTC3886 uses the RVIN resistor to measure the VIN
pin supply current being consumed by the LTC3886. This
valueisreturnedbytheMFR_READ_ICHIPcommand.The
chipcurrentiscalculatedbyusingtheRvaluestoredinthe
MFR_RVINcommand. RefertothesubsectiontitledInput
Current Sense Amplifier in the Applications Information
section for further detail.
resistance), theresultantvoltage(V )appearingacross
DCR
the capacitor will equal the voltage across the inductor
series resistance and thus represent the current flowing
through the inductor. The RC calculations are based on
the room temperature DCR of the inductor.
The RC time constant should remain constant, as a func-
tionoftemperature.Thisassuresthetransientresponseof
the circuit is the same regardless of the temperature. The
DCR of the inductor has a large temperature coefficient,
approximately 3900ppm/°C. The temperature coefficient
of the inductor must be written to the MFR_IOUT_CAL_
GAIN_TC command. The external temperature is sensed
neartheinductorandisusedtomodifytheinternalcurrent
PolyPhase LOAD SHARING
Multiple LTC3886’s can be connected in parallel in order
to provide a balanced load-share solution by connecting
the necessary pins. Figure 3 illustrates the shared con-
nections required for load sharing.
The SYNC pin should only be enabled on one of the
LTC3886s. The other(s) should be programmed to dis-
able SYNC with the oscillator frequency set to the nominal
value. When bit[7] of the MFR_PWM_CONFIG command
is set, Channel 1 will use the feedback node of Chan-
nel 0 as its point of regulation. Do not assert bit[7] of
MFR_PWM_CONFIG except in a PolyPhase application
limit circuit to maintain an essentially constant current
+
limit with temperature. In this application, the I
SENSE
pin is connected to the FET side of the capacitor while
–
the I
pin is placed on the load side of the capacitor.
SENSE
The current sensed from the input is then given by the
expression V /DCR. V is digitized by the LTC3886’s
DCR
DCR
telemetry ADC with an input range of 100mV, a noise
when both V
TH
pins are connected together and both
OUT
floor of 7µV , and a peak-peak noise of approximately
I
pins are tied together.
RMS
46.5µV. The LTC3886 computes the inductor current
using the DCR value stored in the IOUT_CAL_GAIN com-
mand and the temperature coefficient stored in command
MFR_IOUT_CAL_GAIN_TC. The resulting current value is
returned by the READ_IOUT command.
EXTERNAL/INTERNAL TEMPERATURE SENSE
Externaltemperaturecanbestbemeasuredusingaremote,
diode-connected PNP transistor such as the MMBT3906.
The emitter should be connected to a TSNS pin while the
base and collector terminals of the PNP transistor must
be connected and returned directly to the Pin 53 of the
LTC3886 GND using a Kelvin connection. The bypass ca-
pacitor between the emitter and collector must be located
near the transistor. Two different currents are applied to
the diode (nominally 2μA and 32μA) and the temperature
INPUT CURRENT SENSING
TosensethetotalinputcurrentconsumedbytheLTC3886
and the power stage, a resistor is placed between the sup-
ply voltage and the drain of the top N-channel MOSFET.
+
–
The I and I pins are connected to the sense resistor.
IN
IN
The filtered voltage is amplified by the internal high side
current sense amplifier and digitized by the LTC3886’s
telemetry ADC. The input current sense amplifier has
three gain settings of 2x, 4x, and 8x set by the bit[6:5] of
the MFR_PWM_CONFIG_3886 command. The maximum
differential input sense voltage for the three gain settings
is 50mV, 20mV, and 5mV respectively. The LTC3886
computes the input current using the R value stored in the
is calculated from a ∆V measurement made with the
BE
internal 16-bit monitor ADC.
The LTC3886 also supports direct V based external
BE
temperature measurements. In this case the diode or di-
ode network is trimmed to a specific voltage at a specific
current and temperature. In general this method does not
yield as accurate of a result as the single PNP transistor,
3886fe
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For more information www.linear.com/LTC3886
LTC3886
operaTion
LTC3886 + POWER STAGE
I
I
I
THR0
TH0
+
–
10k 10k 4.99k 10k 10k 10k
I
I
V
V
TH1
SENSE0
SENSE0
FAULT0
+
–
RUN
RUN0
SENSE0
SENSE0
RUN1
ALERT
FAULT
ALERT
FAULT1
SYNC
SYNC (ENABLED)
SHARE_CLK
DD33
PGOOD0
PGOOD1
GND
+
–
I
I
SHARE_CLK
SENSE1
SENSE1
V
PGOOD
V
SENSE1
1µF
1/2 LTC3886 + POWER STAGE
I
TH0
DD33
V
1µF
+
–
I
I
RUN0
SENSE0
SENSE0
ALERT
FAULT0
+
–
V
V
SENSE0
SENSE0
SYNC (DISABLED)
SHARE_CLK
LOAD
PGOOD0
GND
NOTE: SOME CONNECTORS
AND COMPONENTS OMITTED
FOR CLARITY
3886 F03
Figure 3. Load Sharing Connections for 3-Phase Operation
but may function better in noisy applications. Refer to
MFR_PWM_MODE_LTC3886 in the PMBus Command
Detailssectionforadditionalinformationonprogramming
the LTC3886 for these two external temperature sense
configurations.
Ifbit6oftheMFR_CONFIG_ALL_LTC3886configuration
command is asserted in EEPROM, the resistor inputs are
ignored upon power-up except for ASEL0 and ASEL1
which are always respected. The resistor configuration
pinsareonlymeasuredduringpower-upandanexecution
of a RESTORE_USER_ALL or MFR_RESET command.
The calculated temperature is returned by the PMBus
READ_TEMPERATURE_1 command. Refer to the Appli-
cations Information section for details on proper layout
of external temperature sense elements and PMBus
commands that can be used to improve the accuracy of
calculated temperatures.
The V
pin settings are described in Table 3. These
OUTn_CFG
pins select the output voltages for the LTC3886’s analog
PWMcontrollers. Ifthepinisopen, theVOUT_COMMAND
commandisloadedfromEEPROMtodeterminetheoutput
voltage. The default setting is to have the switcher off un-
less the voltage configuration pins are installed.
The READ_TEMPERATURE_2 command returns the
internal junction temperature of the LTC3886 using an
The following parameters are set as a percentage of the
outputvoltageiftheRCONFIGpinsareusedtodetermined
output voltage:
on-chip diode with a ∆V measurement and calculation.
BE
RCONFIG (RESISTOR CONFIGURATION) PINS
n
n
n
n
n
n
n
VOUT_OV_FAULT_LIMIT............................... +10%
VOUT_OV_WARN_LIMIT.............................. +7.5%
VOUT_MAX................................................... +7.5%
VOUT_MARGIN_HIGH..................................... +5%
VOUT_MARGIN_LOW...................................... –5%
VOUT_UV_WARN_LIMIT.............................. –6.5%
VOUT_UV_FAULT_LIMIT................................. –7%
There are six input pins utilizing 1% resistor dividers
between V
and GND to select key operating param-
DD25
eters.ThepinsareASEL0,ASEL1,FREQ_CFG,V
,
OUT0_CFG
V
, PHAS_CFG. If pins are floated, the value
OUT1_CFG
stored in the corresponding EEPROM command is used.
3886fe
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LTC3886
operaTion
The FREQ_CFG pin settings are described in Table 4. This
pinselectstheswitchingfrequency.Thephaserelationships
between the two channels and SYNC pin is determined by
the PHAS_CFG pin described in Table 5. To synchronize
to an external clock, the part should be put into external
clock mode (SYNC output disabled but frequency set
to the nominal value). If no external clock is supplied,
the part will clock at the programmed frequency. If the
application is multi-phase and the SYNC signal between
chips is lost, the parts will not be at the same frequency
increasing the ripple voltage on the output, possibly
producing undesirable operation. If the external SYNC
signal is being generated internally and external SYNC is
not selected, bit 10 of MFR_PADS will be asserted. If no
frequency is selected and the external SYNC frequency is
not present, a PLL_FAULT will occur. If the user does not
wish to see the ALERT from a PLL_FAULT even if there is
not a valid synchronization signal at power-up, the ALERT
mask for PLL_FAULT must be written. See the description
on SMBALERT_MASK for more details. If the SYNC pin
is connected between multiple ICs only one of the ICs
should have the SYNC pin enabled, all other ICs should
be configured to SYNC pin disabled.
FAULT HANDLING
A variety of fault and warning reporting and handling
mechanisms are available. Fault and warning detection
capabilities include:
n
Input OV/FAULT Protection and UV Warning
n
Average Input OC Warn
n
Output OV/UV Fault and Warn Protection
n
n
Output OC Fault and Warn Protection
Internal and External Overtemperature Fault and
Warn Protection
n
n
n
External Undertemperature Fault and Warn Protection
CML Fault (Communication, Memory or Logic)
External Fault Detection via the Bidirectional FAULTn
Pins.
Inaddition, theLTC3886canmapanycombinationoffault
indicatorstotheFAULTnpinusingthepropagateFAULTnre-
sponsecommands,MFR_FAULT_PROPAGATE_LTC3886.
TypicalusageoftheFAULTnpinisasadriverforanexternal
crowbar device, overtemperature alert, overvoltage alert
or as an interrupt to cause a microcontroller to poll the
faultcommands. Alternatively, theFAULTnpincanbeused
as an input to detect external faults downstream of the
controller that require an immediate response.
The ASEL0 and 1 pin settings are described in Table 6.
ASEL1 selects the top 3 bits of the slave address for
the LTC3886. ASEL0 selects the bottom 4 bits of the
slave address for the LTC3886. If ASEL1 is floating, the
3 most significant bits are retrieved from the EEPROM
MFR_ADDRESS command. If ASEL0 is floating, the 4
LSB bits stored in EEPROM MFR_ADDRESS command
are used to determine the 4 LSB bits of the slave address.
For more detail, refer to Table 6.
AsdescribedintheSoft-Startsection,itispossibletocontrol
start-up through concatenated events. If FAULTn is used
to drive the RUN pin of another controller, the unfiltered
VOUT_UV fault limit should be mapped to the FAULTn pin.
Any fault or warning event will cause the ALERT pin to
assert low unless the fault or warning is masked by the
SMBALERT_MASK. The pin will remain asserted low until
the CLEAR_FAULTS command is issued, the fault bit is
written to a 1, bias power is cycled or a MFR_RESET
command is issued, the RUN pin is toggled OFF/ON, or
the part is commanded OFF/ON via PMBus. The MFR_
FAULT_PROPAGATE_LTC3886 command determines
if the FAULTn pin is pulled low when a fault is detected.
Note: Per the PMBus specification, pin programmed pa-
rameters can be overridden by commands from the digital
interface with the exception of the ASELn pins which are
always honored. Do not set any part address to 0x5A or
0x5B because these are global addresses and all parts
will respond to them.
3886fe
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LTC3886
operaTion
Output and input fault event handling is controlled by the
corresponding fault response byte as specified in Tables 7
to 11. Shutdown recovery from these types of faults can
either be autonomous or latched. For autonomous re-
covery, the faults are not latched, so if the fault condition
is not present after the retry interval has elapsed, a new
soft-start is attempted. If the fault persists, the controller
will continue to retry. The retry interval is specified by the
MFR_RETRY_DELAY command and prevents damage to
the regulator components by repetitive power cycling,
assuming the fault condition itself is not immediately
destructive. The MFR_RETRY_DELAY must be greater
than 120ms. It can not exceed 83.88 seconds.
example, if ALERT is masked for all bits in Channel 0
STATUS_VOUT, then ALERT is effectively masked for the
OUT
V
bit in STATUS_WORD for PAGE 0.
The BUSY bit in STATUS_BYTE also asserts ALERT low
and cannot be masked. This bit can be set as a result of
various internal interactions with PMBus communication.
This fault occurs when a command is received that cannot
be safely executed with one or both channels enabled. As
discussed in Application Information, BUSY faults can
be avoided by polling MFR_COMMON before executing
some commands.
If masked faults occur immediately after power up, ALERT
may still be pulled low because there has not been time
to retrieve all of the programmed masking information
from EEPROM.
Status Registers and ALERT Masking
Figure 4 summarizes the internal LTC3886 status reg-
isters accessible by PMBus command. These contain
indication of various faults, warnings and other important
operating conditions. As shown, the STATUS_BYTE and
STATUS_WORD commands also summarize contents of
other status registers. Refer to PMBus Command Details
for specific information.
Status information contained in MFR_COMMON and
MFR_PADS can be used to further debug or clarify the
contents of STATUS_BYTE or STATUS_WORD as shown,
but the contents of these registers do not affect the state
of the ALERT pin and may not directly influence bits in
STATUS_BYTE or STATUS_WORD.
NONE OF THE ABOVE in STATUS_BYTE indicates that
one or more of the bits in the most-significant nibble of
STATUS_WORD are also set.
Mapping Faults to FAULT Pins
The FAULTn pins of the LTC3886 can share faults between
channels and with all LTC PMBus products including the
LTC3880,LTC2974,LTC2978,LTC4676µModule®,etc.In
the event of an internal fault, one or more of the LTC3886s
isconfiguredtopullthebussedFAULTnpinslow.Theother
LTC3886s are then configured to shut down when the
FAULTnpinbusispulledlow. Forautonomousgroupretry,
the faulted LTC3886 channel is configured to release the
FAULTnpinbusafteraretryinterval, assumingtheoriginal
fault has cleared. All the channels in the group then begin
a soft-start sequence. If the fault response is LATCH_OFF,
the FAULTn pin remains asserted low until either the RUN
pin is toggled OFF/ON or the part is commanded OFF/ON.
The toggling of the RUN either by the pin or OFF/ON com-
mand will clear faults associated with the LTC3886. If it is
desired to have all faults cleared when either RUN pin is
toggled, set bit 0 of MFR_CONFIG_ALL_LTC3886 to a 1.
In general, any asserted bit in a STATUS_x register also
pulls the ALERT pin low. Once set, ALERT will remain low
until one of the following occurs.
n
A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_
RESET Command Is Issued
n
The Related Status Bit Is Written to a One
n
The Faulted Channel Is Properly Commanded Off and
Back On
n
The LTC3886 Successfully Transmits Its Address
During a PMBus ARA
n
Bias Power Is Cycled
With some exceptions, the SMBALERT_MASK command
canbeusedtopreventtheLTC3886fromassertingALERT
forbitsintheseregistersonabit-by-bitbasis. Thesemask
settings apply to STATUS_WORD and STATUS_BYTE
in the same fashion as the status bits themselves. For
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
3886fe
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LTC3886
operaTion
STATUS_WORD
STATUS_VOUT
15 VOUT
14 IOUT
13 INPUT
12 MFR_SPECIFIC
11 POWER_GOOD#
10 (reads 0)
7
6
5
4
3
2
1
0
VOUT_OV Fault
VOUT_OV Warning
VOUT_UV Warning
VOUT_UV Fault
VOUT_MAX Warning
TON_MAX Fault
TOFF_MAX Warning
(reads 0)
STATUS_INPUT
7
6
5
4
3
2
1
0
VIN_OV Fault
(reads 0)
VIN_UV Warning
(reads 0)
Unit Off for Insuffcient VIN
(reads 0)
9
8
(reads 0)
(reads 0)
STATUS_BYTE
(PAGED)
IIN_OC Warning
(reads 0)
7
6
5
4
3
2
1
0
BUSY
OFF
VOUT_OV
IOUT_OC
(reads 0)
TEMPERATURE
CML
NONE OF THE ABOVE
STATUS_IOUT
STATUS_MFR_SPECIFIC
7
6
5
4
3
2
1
0
IOUT_OC Fault
(reads 0)
IOUT_OC Warning
(reads 0)
7
6
5
4
3
2
1
0
Internal Temperature Fault
Internal Temperature Warning
EEPROM CRC Error
Internal PLL Unlocked
Fault Log Present
VDD33 UV or OV Fault
VOUT Short Cycled
FAULT Pulled Low By External Device
(PAGED)
(reads 0)
(reads 0)
(reads 0)
(reads 0)
MFR_COMMON
7
6
5
4
3
2
1
0
Chip Not Driving ALERT Low
Chip Not Busy
(PAGED)
(PAGED)
Internal Calculations Not Pending
Output Not In Transition
EEPROM Initialized
(reads 0)
SHARE_CLK_LOW
WP Pin High
STATUS_TEMPERATURE
MFR_PADS
7
6
5
4
3
2
1
0
OT Fault
15 VDD33 OV Fault
14 VDD33 UV Fault
13 (reads 0)
12 (reads 0)
11 Invalid ADC Result(s)
10 SYNC Clocked by External Source
OT Warning
(reads 0)
UT Fault
(reads 0)
(reads 0)
(reads 0)
(reads 0)
MFR_INFO
9
8
7
6
5
4
3
2
1
0
Channel 1 Power Good
Channel 0 Power Good
LTC3886 Forcing RUN1 Low
LTC3886 Forcing RUN0 Low
RUN1 Pin State
15 Reserved
14 Reserved
13 Reserved
12 Reserved
11 Reserved
10 Reserved
9
8
7
6
5
4
3
2
1
0
(PAGED)
STATUS_CML
7
6
5
4
3
2
1
0
Invalid/Unsupported Command
Invalid/Unsupported Data
Packet Error Check Failed
Memory Fault Detected
Processor Fault Detected
(reads 0)
RUN0 Pin State
LTC3886 Forcing FAULT1 Low
LTC3886 Forcing FAULT0 Low
FAULT Pin State
Reserved
Reserved
Reserved
Reserved
Reserved
EEPROM ECC Status
Reserved
Reserved
Reserved
FAULT Pin State
3886 F04
Other Communication Fault
Other Memory or Logic Fault
Reserved
DESCRIPTION
MASKABLE GENERATES ALERT BIT CLEARABLE
General Fault or Warning Event
General Non-Maskable Event
Dynamic
Yes
No
No
No
Yes
Yes
No
Yes
Yes
No
Status Derived from Other Bits
Not Directly
No
Figure 4. LTC3886 Status Register Summary
3886fe
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For more information www.linear.com/LTC3886
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Additional fault detection and handling capabilities are:
write byte, 3) write word, 4) group, 5) read byte, 6) read
word,7)readblock,8)writeblock,9)PAGE_PLUS_READ,
10)PAGE_PLUS_WRITE,11)SMBALERT_MASKreadand
12) SMBALERT_MASK. All read operations will return a
valid PEC if the PMBus master requests it. If the PEC_
REQUIRED bit is set in the MFR_CONFIG_ALL_LTC3886
command, the PMBus write operations will not be acted
upon until a valid PEC has been received by the LTC3886.
Power Good Pins
The PGOODn pins of the LTC3886 are connected to the
opendrainsofinternalMOSFETs.TheMOSFETsturnonand
pullthePGOODnpinslowwhenthechanneloutputvoltage
is not within the channels UV and OV voltage thresholds.
During TON_DELAY and TON_RISE sequencing, the PGn
pin is held low. The PGOODn pin is also pulled low when
therespectiveRUNnpinislow. ThePGOODnpinresponse
is deglitched by an internal 60µs digital filter. The PGOODn
pin and PGOOD status may be different at times due to
internal communication latency of up to 10µs.
Communication Protection
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
CRC Protection
The integrity of the EEPROM memory is checked after a
power-onreset.ACRCerrorwillpreventthecontrollerfrom
leavingtheresetstate. IfaCRCerroroccurs, theCMLbitis
setintheSTATUS_BYTEandSTATUS_WORDcommands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
command, and the ALERT pin will be pulled low. EEPROM
repair can be attempted by writing the desired configura-
tion to the controller and executing a STORE_USER_ALL
command followed by a CLEAR_FAULTS command.
DEVICE ADDRESSING
TheLTC3886offersfourdifferenttypesofaddressingover
the PMBus interface, specifically: 1) global, 2) device, 3)
rail addressing and 4) alert response address (ARA).
Global addressing provides a means of the PMBus master
to address all LTC3886 devices on the bus. The LTC3886
global address is fixed 0x5A (7) or 0xB4 (8) and cannot
be disabled. Commands sent to the global address act the
sameasifPAGEissettoavalueof0xFF.Commandssentare
writtentobothchannelssimultaneously.Globalcommand
0x5B (7) or 0xB6 (8) is paged and allows channel specific
command of all LTC3886 devices on the bus. Other LTC
device types may respond at one or both of these global
addresses; therefore do not read from global addresses.
The LTC3886 manufacturing section of the EEPROM is
mirrored. If both copies are corrupted, the “EEPROM
CRC Fault” in the STATUS_MFR_SPECIFIC command is
set. If this bit remains set after being cleared by issuing a
CLEAR_FAULTS or writing a 1 to this bit, an irrecoverable
internal fault has occurred. There are no provisions for
fieldrepairofEEPROMfaultsinthemanufacturingsection.
Rail addressing provides a means for the bus master to
simultaneouslycommunicatewithallchannelsconnected
together to produce a single output voltage (PolyPhase).
While similar to global addressing, the rail address can
be dynamically assigned with the paged MFR_RAIL_
ADDRESS command, allowing for any logical grouping
of channels that might be required for reliable system
control. Do not read from rail addresses since multiple
LTC devices may respond.
SERIAL INTERFACE
The LTC3886 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either the
EEPROM or an external resistor divider. In addition the
LTC3886alwaysrespondstotheglobalbroadcastaddress
of 0x5A (7) or 0x5B (7).
The serial interface supports the following protocols de-
fined in the PMBus specifications: 1) send command, 2)
3886fe
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Device addressing provides the standard means of the
PMBus master communicating with a single instance of
an LTC3886. The value of the device address is set by a
combination of the ASEL0 and ASEL1 configuration pins
and the MFR_ADDRESS command. Device address-
ing can be disabled by writing a value of 0x80 to the
MFR_ADDRESS.
Output Overvoltage Fault Response
A programmable overvoltage comparator (OV) guards
against transient overshoots as well as long-term over-
voltages at the output. In such cases, the top MOSFET is
turned off and the bottom MOSFET is turned on until the
overvoltage condition is cleared regardless of the PMBus
VOUT_OV_FAULT_RESPONSEcommandbytevalue.This
hardware level fault response delay is typically 2µs from
the overvoltage condition to BG asserted high. Using the
VOUT_OV_FAULT_RESPONSE command, the user can
select any of the following behaviors:
All four means of PMBus addressing require the user to
employdisciplinedplanningtoavoidaddressingconflicts.
Communication to LTC3886 devices at global and rail ad-
dresses should be limited to command write operations.
n
OV Pull-Down Only (OV Cannot Be Ignored)
RESPONSES TO V
AND I
FAULTS
OUT
OUT
n
Shut Down (Stop Switching) Immediately—Latch Off
V
OVandUVconditionsaremonitoredbycomparators.
OUT
n
Shut Down Immediately—Retry Indefinitely Using
the Time Interval Specified in MFR_RETRY_DELAY
The OV and UV limits are set in three ways.
n
As a Percentage of the V
Configuration Pins
if Using the Resistor
OUT
Either the Latch Off or Retry fault responses can be
deglitched in increments of (0-7) • 10µs. See Table 7.
n
n
In EEPROM if Either Programmed at the Factory or
Through the GUI
Output Undervoltage Response
By PMBus Command
The response to an undervoltage comparator output can
be either:
The I and I
overcurrent monitors are performed by
IN
OUT
n
ADC readings and calculations. Thus these values are
Ignore
based on average currents and can have a time latency of
n
Shut Down Immediately—Latch Off
up to 120ms. The I
calculation accounts for the sense
OUT
n
Shut Down Immediately—Retry Indefinitely Using
the Time Interval Specified in MFR_RETRY_DELAY
resistorandthetemperaturecoefficientoftheresistor.The
input current is equal to the voltage measured across the
R
resistor divided by the resistors value as set with
IINSNS
The UV responses can be deglitched. See Table 8.
theMFR_IIN_CAL_GAINcommand.Ifthiscalculatedinput
current exceeds the IN_OC_WARN_LIMIT the ALERT pin
is pulled low and the IIN_OC_WARN bit is asserted in the
STATUS_INPUT command.
Peak Output Overcurrent Fault Response
Due to the current mode control algorithm, peak output
current across the inductor is always limited on a cycle by
cycle basis. The value of the peak current limit is specified
in sense voltage in the EC table. The current limit circuit
operatesbylimitingtheI maximumvoltage.IfDCRsens-
ing is used, the I maximum voltage has a temperature
The digital processor within the LTC3886 provides the
ability to ignore the fault, shut down and latch off or shut
down and retry indefinitely (retry). The retry interval is
set in MFR_RETRY_DELAY and can be from 120ms to
83.88 seconds in 1ms increments. The shutdown for
OV/UV and OC can be done immediately or after a user
selectable deglitch time.
TH
TH
dependency directly proportional to the TC of the DCR
of the inductor. The LTC3886 automatically monitors the
external temperature sensors and modifies the maximum
allowed I to compensate for this term.
TH
3886fe
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LTC3886
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The overcurrent fault processing circuitry can execute the
following behaviors:
n
Shut Down Immediately—Retry Indefinitely Using
the Time Interval Specified in MFR_RETRY_DELAY
n
Current Limit Indefinitely
See Table 11.
n
Shut Down Immediately—Latch Off
RESPONSES TO OT/UT FAULTS
n
Shut Down Immediately—Retry Indefinitely Using
the Time Interval Specified in MFR_RETRY_DELAY
Internal Overtemperature Fault/Warn Response
Theovercurrentresponsescanbedeglitchedinincrements
An internal temperature sensor protects against EEPROM
damage. Above 85°C, no writes to EEPROM are recom-
mended. Above 130°C, the internal overtemperature
warn threshold is exceeded and the part will NACK any
EEPROM related command except RESTORE_USER_ALL
or MFR_RESET and issue a CML fault for Invalid/Unsup-
ported Command. Full EEPROM operation is re-enabled
when the internal temperature has dropped below 125°C.
When the die temperature exceeds 160°C the internal
overtemperature fault response is enabled and the PWM
is disabled until the die temperature drops below 150°C.
Temperature is measured by the ADC. Internal tempera-
ture faults cannot be ignored. Internal temperature limits
cannot be adjusted by the user.
of (0-7) • 16ms. See Table 9.
RESPONSES TO TIMING FAULTS
TON_MAX_FAULT_LIMIT is the time allowed for V
to
OUT
rise and settle at start-up. The TON_MAX_FAULT_LIMIT
condition is predicated upon detection of the VOUT_UV_
FAULT_LIMIT as the output is undergoing a soft-start se-
quence.TheTON_MAX_FAULT_LIMITtimeisstartedafter
TON_DELAY has been reached and a soft-start sequence
is started. The resolution of the TON_MAX_FAULT_LIMIT
is 10µs. If the VOUT_UV_FAULT_LIMIT is not reached
within the TON_MAX_FAULT_LIMIT time, the response
of this fault is determined by the value of the TON_MAX_
FAULT_RESPONSE command value. This response may
be one of the following:
See Table 10.
External Overtemperature and Undertemperature
Fault Response
n
Ignore
n
Shut Down (Stop Switching) Immediately—Latch Off
An external temperature sensor can be used to sense
critical circuit elements like the inductor and power
MOSFETs. The OT_FAULT_RESPONSE and UT_FAULT_
RESPONSE commands are used to determine the appropri-
ate response to an overtemperature and undertemperature
condition, respectively. If no external sense element is used
(notrecommended)settheUT_FAULT_RESPONSEtoignore
and set the UT_FAULT_LIMIT to –275°C. However, not using
an external temperature sense element is not recommended.
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY
This fault response is not deglitched. A value of 0 in
TON_MAX_FAULT_LIMIT means the fault is ignored. The
TON_MAX_FAULT_LIMIT should be set longer than the
TON_RISE time.
See Table 11.
The fault responses are:
RESPONSES TO V OV FAULTS
IN
n
Ignore
V overvoltage is measured with the ADC. The response
IN
n
Shut Down Immediately—Latch Off
is deglitched by the 90ms typical response time of the
n
ADC. The fault responses are:
Shut Down Immediately—Retry Indefinitely Using
the Time Interval Specified in MFR_RETRY_DELAY
n
Ignore
See Table 11.
n
Shut Down Immediately—Latch Off
3886fe
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RESPONSES TO EXTERNAL FAULTS
BUS TIMEOUT PROTECTION
WheneitherFAULTnpinispulledlow,therespectiveFAULTn
bitisde-assertedintheMFR_PADScommand,theFAULTn
bit is set in the STATUS_MFR_SPECIFC command, the
NONE_OF_THE_ABOVE bit is set in the STATUS_BYTE
command,andtheALERTpinispulledlow.Responsesare
notdeglitched.Eachchannelcanbeconfiguredtoignoreor
shut down then retry in response to its FAULTn pin going
lowbymodifyingtheMFR_FAULT_RESPONSEcommand.
ToavoidtheALERTpinassertinglowwhenFAULTispulled
low, assert bit 1 of MFR_CHAN_CONFIG_LTC3886, or
mask the ALERT using the SMBALERT_MASK command.
The LTC3886 implements a timeout feature to avoid per-
sistant faults on the serial interface. The data packet timer
begins at the first START event before the device address
write byte. Data packet information must be completed
within 30ms or the LTC3886 will three-state the bus and
ignore the given data packet. If more time is required,
assert bit 3 of MFR_CONFIG_ALL_LTC3886 to allow
typical bus timeouts of 255ms. Data packet information
includes the device address byte write, command byte,
repeat start event (if a read operation), device address
byte read (if a read operation), all data bytes and the PEC
byte if applicable.
FAULT LOGGING
The LTC3886 allows 255ms PMBus timeouts for block
read data packets. This timeout is proportional to the
length of the block read. The additional block read time-
out applies primarily to the MFR_FAULT_LOG command.
The timeout period defaults to 32ms.
The LTC3886 has fault logging capability. Data is logged
into memory in the order shown in Table 13. The data is
stored in a continuously updated buffer in RAM. When
a fault event occurs, the fault log buffer is copied from
the RAM buffer into EEPROM. Fault logging is allowed at
temperaturesabove85°C;however,retentionof10yearsis
notguaranteed.Whenthedietemperatureexceeds130°C,
the fault logging is delayed until the die temperature drops
below 125°C. The fault log data remains in EEPROM until
a MFR_FAULT_LOG_CLEAR command is issued. Issuing
this command re-enables the fault log feature. Before
re-enabling fault log, be sure no faults are present and a
CLEAR_FAULTS command has been issued.
Theuserisencouragedtouseashighaclockrateaspossible
tomaintainefficientdatapackettransferbetweenalldevices
sharing the serial bus interface. The LTC3886 supports the
full PMBus frequency range from 10kHz to 400kHz.
2
SIMILARITY BETWEEN PMBus, SMBus AND I C
2-WIRE INTERFACE
The PMBus 2-wire interface is an incremental extension
2
of the SMBus. SMBus is built upon I C with some minor
When the LTC3886 powers-up or exits reset state,
it checks the EEPROM for a valid fault log. If a valid
fault log exists in EEPROM, the “Valid Fault Log” bit
in the STATUS_MFR_SPECIFIC command will be set
and an ALERT event will be generated. Also, fault log-
ging will be blocked until the LTC3886 has received a
MFR_FAULT_LOG_CLEARcommandbeforefaultlogging
will be re-enabled.
differences in timing, DC parameters and protocol. The
2
PMBus/SMBusprotocolsaremorerobustthansimpleI C
byte commands because PMBus/SMBus provide time-
outs to prevent persistent bus errors and optional packet
error checking (PEC) to ensure data integrity. In general, a
2
master device that can be configured for I C communica-
tion can be used for PMBus communication with little or
no change to hardware or firmware. Repeat start (restart)
2
The information is stored in EEPROM in the event of any
fault that disables the controller. The FAULTn pin being
externally pulled low will not trigger a fault logging event.
is not supported by all I C controllers but is required for
2
SMBus/PMBus reads. If a general purpose I C controller
is used, check that repeat start is supported.
3886fe
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LTC3886
operaTion
The LTC3886 supports the maximum SMBus clock
speed of 100kHz and is compatible with the higher speed
PMBus specification (between 100kHz and 400kHz) if
MFR_COMMON polling or clock stretching is enabled. For
robustcommunicationandoperationrefertotheNotesec-
tioninthePMBuscommandsummary. Clockstretchingis
enabledbyassertingbit1ofMFR_CONFIG_ALL_LTC3886.
255 bytes of returned data. For this reason, the PMBus
timeout may be extended when reading the fault log.
Figure 6 is a key to the protocol diagrams in this section.
PEC is optional.
A value shown below a field in the following figures is a
mandatory value for that field.
The data formats implemented by PMBus are:
PMBus SERIAL DIGITAL INTERFACE
n
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
TheLTC3886communicateswithahost(master)usingthe
standardPMBusserialbusinterface.TheTimingDiagram,
Figure 5, shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
n
Master reads slave immediately after the first byte.
At the moment of the first acknowledgment (pro-
vided by the slave receiver) the master transmitter
becomes a master receiver and the slave receiver
becomes a slave transmitter.
The LTC3886 is a slave device. The master can com-
municate with the LTC3886 using the following formats:
n
Combined format. During a change of direction
within a transfer, the master repeats both a start
condition and the slave address but with the R/W bit
reversed. In this case, the master receiver terminates
the transfer by generating a NACK on the last byte of
the transfer and a STOP condition.
n
Master transmitter, slave receiver
n
Master receiver, slave transmitter
The following PMBus protocols are supported:
n
Write Byte, Write Word, Send Byte
Refer to Figure 6 for a legend.
n
Read Byte, Read Word, Block Read, Block Write
Handshaking features are included to ensure robust
system communication. Please refer to the PMBus Com-
munication and Command Processing subsection of the
Applications Information section for further details.
n
Alert Response Address
Figures 6-23 illustrate the aforementioned PMBus proto-
cols. AlltransactionssupportPEC (parityerrorcheck)and
GCP(groupcommandprotocol).TheBlockReadsupports
3886fe
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SDA
t
r
t
SU(DAT)
t
t
SP
t
r
HD(SDA)
t
t
t
t
f
BUF
f
LOW
SCL
t
t
t
SU(STO)
HD(STA)
SU(STA)
t
t
HIGH
HD(DAT)
3886 F05
START
CONDITION
REPEATED START
CONDITION
STOP
START
CONDITION CONDITION
Figure 5. Timing Diagram
Table 1. Abbreviations of Supported Data Formats
PMBus
SPECIFICATION
LTC
TERMINOLOGY
L11 Linear
REFERENCE TERMINOLOGY DEFINITION
EXAMPLE
N
Part II ¶7.1
Linear_5s_11s Floating point 16-bit data: value = Y • 2 , b[15:0] = 0x9807 = 10011_000_0000_0111
–13
where N = b[15:11] and Y = b[10:0], both value = 7 • 2 = 854E-6
two’s compliment binary integers.
–12
L16 Linear VOUT_MODE
CF DIRECT
Part II ¶8.2
Part II ¶7.2
Linear_16u
Varies
Floating point 16-bit data: value = Y • 2 , b[15:0] = 0x4C00 = 0100_1100_0000_0000
–12
where Y = b[15:0], an unsigned integer.
value = 19456 • 2 = 4.75
16-bit data with a custom format
defined in the detailed PMBus command
description.
Often an unsigned or two’s compliment
integer.
Reg register bits
Part II ¶10.3
Reg
Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command.
command description.
ASC text characters
Part II ¶22.2.1
ASCII
ISO/IEC 8859-1 [A05]
LTC (0x4C5443)
3886fe
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LTC3886
operaTion
S
START CONDITION
Sr
REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
A
ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P
STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
...
CONTINUATION OF PROTOCOL
3886 F06
Figure 6. PMBus Packet Protocol Diagram Element Key
1
7
1
1
1
S
SLAVE ADDRESS Rd/Wr
A
P
3886 F07
Figure 7. Quick Command Protocol
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
P
3886 F08
Figure 8. Send Byte Protocol
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
PEC
A
P
3886 F09
Figure 9. Send Byte Protocol with PEC
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
P
3886 F10
Figure 10. Write Byte Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
PEC
A
P
3886 F11
Figure 11. Write Byte Protocol with PEC
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
3886 F12
Figure 12. Write Word Protocol
1
7
1
1
8
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
3886 F13
Figure 13. Write Word Protocol with PEC
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1
7
1
1
8
1
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE
A
P
3886 F14
Figure 14. Read Byte Protocol
1
7
1
1
8
1
1
7
1
1
8
1
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE
A
PEC
A
P
3886 F15
Figure 15. Read Byte Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
3886 F16
Figure 16. Read Word Protocol
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
3886 F17
Figure 17. Read Word Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
BYTE COUNT = N
A
…
8
1
8
1
…
…
8
1
1
DATA BYTE 1
A
DATA BYTE 2
A
DATA BYTE N
A
P
3886 F18
Figure 18. Block Read Protocol
1
7
1
1
8
1
1
7
1
1
8
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr SLAVE ADDRESS Rd
A
BYTE COUNT = N
A
…
8
1
8
1
…
…
8
1
8
1
1
DATA BYTE 1
A
DATA BYTE 2
A
DATA BYTE N
A
PEC
A
P
3886 F19
Figure 19. Block Read Protocol with PEC
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1
7
1
1
8
1
8
1
8
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
BYTE COUNT = M
A
DATA BYTE 1
A
…
8
1
8
1
DATA BYTE 2
A
…
DATA BYTE M
A
…
1
7
1
1
8
1
8
1
1
Sr SLAVE ADDRESS Rd
A
BYTE COUNT = N
A
DATA BYTE 1
A
…
8
1
…
…
8
1
1
DATA BYTE 2
A
DATA BYTE N
A
P
3886 F20
Figure 20. Block Write – Block Read Process Call
1
7
1
1
8
1
8
1
8
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
BYTE COUNT = M
A
DATA BYTE 1
A
…
8
1
8
1
DATA BYTE 2
A
…
DATA BYTE M
A
…
1
7
1
1
8
1
8
1
1
Sr SLAVE ADDRESS Rd
A
BYTE COUNT = N
A
DATA BYTE 1
A
…
8
1
…
…
8
1
8
1
1
DATA BYTE 2
A
DATA BYTE N
A
PEC
A
P
3886 F21
Figure 21. Block Write – Block Read Process Call with PEC
1
7
1
1
8
1
1
ALERT RESPONSE
ADDRESS
S
Rd
A
DEVICE ADDRESS
A
P
3886 F22
Figure 22. Alert Response Address Protocol
1
7
1
1
8
1
8
1
1
ALERT RESPONSE
ADDRESS
S
Rd
A
DEVICE ADDRESS
A
PEC
A
P
3886 F23
Figure 23. Alert Response Address Protocol with PEC
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pMbꢀꢁ coMManD suMMary
PMBus COMMANDS
implicitlynotsupportedbythemanufacturer.Attemptingto
access non-supported or reserved commands may result
in a CML command fault event. All output voltage settings
The following tables list supported PMBus commands
and manufacturer specific commands. A complete de-
scription of these commands can be found in the PMBus
Power System Mgt Protocol Specification. Users are
encouraged to reference this specification. Exceptions or
manufacturer specific implementations are listed below
in Table 2. Floating point values listed in the “DEFAULT
VALUE” column are either Linear 16-bit Signed (PMBus
Section 8.3.1) or Linear_5s_11s (PMBus Section 7.1)
format, whichever is appropriate for the command. All
commands from 0xD0 through 0xFF not listed in this
table are implicitly reserved by the manufacturer. Users
should avoid blind writes within this range of commands
to avoid undesired operation of the part. All commands
from 0x00 through 0xCF not listed in this table are
and measurements are based on the VOUT_MODE setting
–12
of 0x14. This translates to an exponent of 2
.
IfPMBuscommandsarereceivedfasterthantheyarebeing
processed, the part may become too busy to handle new
commands. In these circumstances the part follows the
protocols defined in the PMBus Specification v1.1, Part II,
Section 10.8.7, to communicate that it is busy. The part
includes handshaking features to eliminate busy errors
andsimplifyerrorhandlingsoftwarewhileensuringrobust
communication and system behavior. Please refer to the
subsection titled PMBus Communication and Command
Processing in the Applications Information section for
further details.
Table 2. Summary (Note: The Data Format abbreviations are detailed at the end of this table.)
CMD
DATA
DEFAULT
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE PAGE
PAGE
0x00 Provides integration with multi-page PMBus
devices.
R/W Byte
N
Y
Y
Reg
Reg
Reg
0x00
0x40
0x1E
NA
68
72
72
OPERATION
0x01 Operating mode control. On/off, margin high
and margin low.
R/W Byte
R/W Byte
Y
Y
ON_OFF_CONFIG
0x02 RUN pin and PMBus bus on/off command
configuration.
CLEAR_FAULTS
0x03 Clear any fault bits that have been set.
Send Byte
W Block
N
N
N
98
68
69
PAGE_PLUS_WRITE
PAGE_PLUS_READ
0x05 Write a command directly to a specified page.
0x06 Read a command directly from a specified
page.
Block R/W
WRITE_PROTECT
0x10 Level of protection provided by the device
against accidental changes.
R/W Byte
N
Reg
Reg
Y
0x00
69
STORE_USER_ALL
0x15 Store user operating memory to EEPROM.
Send Byte
Send Byte
N
N
NA
NA
108
108
RESTORE_USER_ALL
0x16 Restore user operating memory from
EEPROM.
CAPABILITY
0x19 Summary of PMBus optional communication
protocols supported by this device.
R Byte
N
0xB0
97
SMBALERT_MASK
VOUT_MODE
0x1B Mask ALERT activity
Block R/W
R Byte
Y
Y
Reg
Reg
Y
see CMD 99
–12
–12
0x20 Output voltage format and exponent (2 ).
2
78
80
78
79
0x14
VOUT_COMMAND
VOUT_MAX
0x21 Nominal output voltage set point.
R/W Word
Y
Y
Y
L16
L16
L16
V
V
V
Y
Y
Y
1.0
0x1000
0x24 Upper limit on the commanded output voltage R/W Word
including VOUT_MARGIN_HI.
14.0
0xE000
VOUT_MARGIN_HIGH
0x25 Margin high output voltage set point. Must be R/W Word
greater than VOUT_COMMAND.
1.05
0x10CD
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pMbꢀꢁ coMManD suMMary
CMD
DATA
DEFAULT
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE PAGE
VOUT_MARGIN_LOW
0x26 Margin low output voltage set point. Must be
less than VOUT_COMMAND.
R/W Word
Y
Y
N
N
N
Y
L16
L11
L11
L11
L11
L11
V
V/ms
kHz
V
Y
Y
Y
Y
Y
Y
0.95
80
86
76
77
77
81
0x0F33
VOUT_TRANSITION_
RATE
0x27 Rate the output changes when VOUT
commanded to a new value.
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
0.25
0xAA00
FREQUENCY_SWITCH
0x33 Switching frequency of the controller.
350
0xFABC
VIN_ON
0x35 Input voltage at which the unit should start
power conversion.
6.5
0xCB40
VIN_OFF
0x36 Input voltage at which the unit should stop
power conversion.
V
6.0
0xCB00
IOUT_CAL_GAIN
0x38 The ratio of the voltage at the current sense
pins to the sensed current. For devices using a
fixed current sense resistor, it is the resistance
value in mΩ.
mΩ
1.8
0xBB9A
VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit.
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Word
R/W Byte
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Byte
R/W Word
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
L16
Reg
L16
L16
L16
Reg
L11
Reg
L11
L11
Reg
L11
L11
Reg
L11
Reg
L11
L11
V
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
1.1
79
88
79
80
80
89
82
91
83
84
93
84
85
93
77
88
77
0x119A
VOUT_OV_FAULT_
RESPONSE
0x41 Action to be taken by the device when an
output overvoltage fault is detected.
0xB8
VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit.
VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit.
VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit.
V
V
V
1.075
0x1133
0.925
0x0ECD
0.9
0x0E66
VOUT_UV_FAULT_
RESPONSE
0x45 Action to be taken by the device when an
output undervoltage fault is detected.
0xB8
IOUT_OC_FAULT_LIMIT
0x46 Output overcurrent fault limit.
A
29.75
0xDBB8
IOUT_OC_FAULT_
RESPONSE
0x47 Action to be taken by the device when an
output overcurrent fault is detected.
0x00
IOUT_OC_WARN_LIMIT
0x4A Output overcurrent warning limit.
A
C
20.0
0xDA80
OT_FAULT_LIMIT
0x4F External overtemperature fault limit.
100.0
0xEB20
OT_FAULT_RESPONSE
OT_WARN_LIMIT
0x50 Action to be taken by the device when an
external overtemperature fault is detected,
0xB8
0x51 External overtemperature warning limit.
C
C
85.0
0xEAA8
UT_FAULT_LIMIT
0x53 External undertemperature fault limit.
–40.0
0xE580
UT_FAULT_RESPONSE
VIN_OV_FAULT_LIMIT
0x54 Action to be taken by the device when an
external undertemperature fault is detected.
0xB8
0x55 Input supply overvoltage fault limit.
V
48.0
0xE300
VIN_OV_FAULT_
RESPONSE
0x56 Action to be taken by the device when an input R/W Byte
overvoltage fault is detected.
0x80
VIN_UV_WARN_LIMIT
0x58 Input supply undervoltage warning limit.
R/W Word
V
A
6.3
0xCB26
IIN_OC_WARN_LIMIT
0x5D Input supply overcurrent warning limit.
R/W Word
10.0
0xD280
83
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CMD
DATA
DEFAULT
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE PAGE
TON_DELAY
0x60 Time from RUN and/or Operation on to output R/W Word
rail turn-on.
Y
L11
L11
ms
Y
0.0
85
0x8000
TON_RISE
0x61 Time from when the output starts to rise
until the output voltage reaches the VOUT
commanded value.
R/W Word
Y
ms
Y
8.0
0xD200
85
TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for R/W Word
VOUT to cross the VOUT_UV_FAULT_LIMIT.
Y
Y
Y
Y
Y
Y
Y
L11
Reg
L11
L11
L11
Reg
Reg
ms
Y
Y
Y
Y
Y
10.00
86
91
0xD280
TON_MAX_FAULT_
RESPONSE
0x63 Action to be taken by the device when a TON_ R/W Byte
MAX_FAULT event is detected.
0xB8
TOFF_DELAY
0x64 Time from RUN and/or Operation off to the
start of TOFF_FALL ramp.
R/W Word
R/W Word
R/W Word
R/W Byte
R/W Word
ms
ms
ms
0.0
0x8000
86
TOFF_FALL
0x65 Time from when the output starts to fall until
the output reaches zero volts.
8.00
0xD200
86
TOFF_MAX_WARN_
LIMIT
0x66 Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below 12.5%.
150.0
0xF258
87
STATUS_BYTE
0x78 One byte summary of the unit’s fault
condition.
NA
NA
100
100
STATUS_WORD
0x79 Two byte summary of the unit’s fault
condition.
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
0x7A Output voltage fault and warning status.
0x7B Output current fault and warning status.
0x7C Input supply fault and warning status.
R/W Byte
R/W Byte
R/W Byte
R/W Byte
Y
Y
N
Y
Reg
Reg
Reg
Reg
NA
NA
NA
NA
100
101
101
102
STATUS_TEMPERATURE 0x7D External temperature fault and warning status
for READ_TEMERATURE_1.
STATUS_CML
0x7E Communication and memory fault and
warning status.
R/W Byte
R/W Byte
N
Y
Reg
Reg
NA
NA
102
103
STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state
information.
READ_VIN
READ_IIN
0x88 Measured input supply voltage.
0x89 Measured input supply current.
0x8B Measured output voltage.
0x8C Measured output current.
R Word
R Word
R Word
R Word
N
N
Y
Y
Y
L11
L11
L16
L11
L11
V
A
V
A
C
NA
NA
NA
NA
NA
105
105
105
105
106
READ_VOUT
READ_IOUT
READ_TEMPERATURE_1 0x8D External temperature sensor temperature. This R Word
is the value used for all temperature related
processing, including IOUT_CAL_GAIN.
READ_TEMPERATURE_2 0x8E Internal die junction temperature. Does not
affect any other commands.
R Word
N
L11
C
NA
106
READ_FREQUENCY
READ_POUT
0x95 Measured PWM switching frequency.
0x96 Calculated output power.
R Word
R Word
R Word
R Byte
Y
Y
N
N
L11
L11
L11
Reg
Hz
W
W
NA
NA
106
106
106
97
READ_PIN
0x97 Calculated input power
NA
PMBUS_REVISION
0x98 PMBus revision supported by this device.
Current revision is 1.2.
0x22
MFR_ID
0x99 The manufacturer ID of the LTC3886 in ASCII.
0x9A Manufacturer part number in ASCII.
R String
R String
R Word
N
N
Y
ASC
ASC
L16
LTC
97
MFR_MODEL
MFR_VOUT_MAX
LTC3886 97
0xA5 Maximum allowed output voltage including
VOUT_OV_FAULT_LIMIT.
V
14.0
0xE000
80
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LTC3886
pMbꢀꢁ coMManD suMMary
CMD
DATA
DEFAULT
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE PAGE
USER_DATA_00
0xB0 OEM RESERVED. Typically used for part
serialization.
R/W Word
N
Reg
Y
NA
96
USER_DATA_01
USER_DATA_02
0xB1 Manufacturer reserved for LTpowerPlay.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
NA
NA
96
96
0xB2 OEM RESERVED. Typically used for part
serialization
USER_DATA_03
USER_DATA_04
MFR_INFO
0xB3 An EEPROM word available for the user.
0xB4 An EEPROM word available for the user.
0xB6 Manufacturing Specific Information
0xBD Contact factory.
R/W Word
R/W Word
R Word
Y
N
Reg
Reg
Reg
Y
Y
0x0000
0x0000
NA
96
96
104
114
MFR_EE_UNLOCK
MFR_EE_ERASE
MFR_EE_DATA
0xBE Contact factory.
114
0xBF Contact factory.
114
71
MFR_CHAN_CONFIG_
LTC3886
0xD0 Configuration bits that are channel specific.
R/W Byte
R/W Byte
Y
N
Y
Reg
Reg
Reg
Y
Y
Y
0x1D
0x21
MFR_CONFIG_ALL_
LTC3886
0xD1 General configuration bits.
71
94
MFR_FAULT_
PROPAGATE_LTC3886
0xD2 Configuration that determines which faults are R/W Word
propagated to the FAULT pin.
0x6993
MFR_PWM_COMP
0xD3 PWM loop compensation configuration
0xD4 Configuration for the PWM engine.
R/W Byte
R/W Byte
Y
Y
Reg
Reg
Y
Y
0x70
0xC1
74
73
MFR_PWM_MODE_
LTC3886
MFR_FAULT_RESPONSE 0xD5 Action to be taken by the device when the
FAULT pin is externally asserted low.
R/W Byte
R Byte
Y
N
Y
N
Y
Y
Y
N
Y
Reg
Reg
L11
Reg
L11
L11
L16
L11
L11
Y
0xC0
0xC0
NA
96
92
MFR_OT_FAULT_
RESPONSE
0xD6 Action to be taken by the device when an
internal overtemperature fault is detected.
MFR_IOUT_PEAK
0xD7 Report the maximum measured value of
READ_IOUT since last MFR_CLEAR_PEAKS.
R Word
A
106
106
87
MFR_ADC_CONTROL
MFR_RETRY_DELAY
MFR_RESTART_DELAY
MFR_VOUT_PEAK
MFR_VIN_PEAK
0xD8 ADC telemetry parameter selected for repeated R/W Byte
fast ADC read back
0x00
0xDB Retry interval during FAULT retry mode.
R/W Word
ms
ms
V
Y
Y
350.0
0xFABC
0xDC Minimum time the RUN pin is held low by the R/W Word
LTC3886.
500.0
0xFBE8
87
0xDD Maximum measured value of READ_VOUT
since last MFR_CLEAR_PEAKS.
R Word
R Word
R Word
NA
NA
NA
107
107
107
0xDE Maximum measured value of READ_VIN since
last MFR_CLEAR_PEAKS.
V
MFR_TEMPERATURE_1_ 0xDF Maximum measured value of external
C
PEAK
Temperature (READ_TEMPERATURE_1) since
last MFR_CLEAR_PEAKS.
MFR_READ_IIN_PEAK
0xE1 Maximum measured value of READ_IIN
command since last MFR_CLEAR_PEAKS
R Word
N
L11
A
A
NA
108
MFR_CLEAR_PEAKS
MFR_READ_ICHIP
MFR_PADS
0xE3 Clears all peak values.
Send Byte
R Word
N
N
N
N
NA
NA
99
108
103
70
0xE4 Measured supply current of the LTC3886
L11
Reg
Reg
0xE5 Digital status of the I/O pads.
R Word
NA
2
MFR_ADDRESS
0xE6 Sets the 7-bit I C address byte.
R/W Byte
Y
0x4F
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LTC3886
pMbꢀꢁ coMManD suMMary
CMD
DATA
DEFAULT
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE PAGE
MFR_SPECIAL_ID
0xE7 Manufacturer code representing the LTC3886
and revision
R Word
N
N
N
N
Reg
L11
0x460X
97
MFR_IIN_CAL_GAIN
0xE8 The resistance value of the input current sense R/W Word
element in mΩ.
mΩ
Y
5.0
0xCA80
83
MFR_FAULT_LOG_
STORE
0xEA Command a transfer of the fault log from RAM Send Byte
to EEPROM.
NA
110
114
MFR_FAULT_LOG_
CLEAR
0xEC Initialize the EEPROM block reserved for fault Send Byte
logging.
NA
MFR_FAULT_LOG
MFR_COMMON
0xEE Fault log data bytes.
R Block
R Byte
N
N
Reg
Reg
Y
NA
NA
110
104
0xEF Manufacturer status bits that are common
across multiple LTC chips.
MFR_COMPARE_USER_ 0xF0 Compares current command contents with
ALL EEPROM.
Send Byte
R Word
N
N
N
Y
N
Y
Y
Y
N
NA
NA
109
108
75
MFR_TEMPERATURE_2_ 0xF4 Peak internal die temperature since last MFR_
L11
Reg
CF
C
PEAK
CLEAR_PEAKS.
MFR_PWM_CONFIG_
LTC3886
0xF5 Set numerous parameters for the DC/DC
controller including phasing.
R/W Byte
Y
Y
Y
Y
Y
Y
0x10
MFR_IOUT_CAL_GAIN_
TC
0xF6 Temperature coefficient of the current sensing R/W Word
element.
ppm/
˚C
3900
0x0F3C
81
MFR_RVIN
0xF7 The resistance value of the V pin filter
R/W Word
R/W Word
R/W Word
R/W Byte
Send Byte
L11
CF
mΩ
2000
0x0BE8
78
IN
element in mΩ.
MFR_TEMP_1_GAIN
MFR_TEMP_1_OFFSET
MFR_RAIL_ADDRESS
MFR_RESET
0xF8 Sets the slope of the external temperature
sensor.
1.0
0x4000
84
0xF9 Sets the offset of the external temperature
sensor with respect to –273.1°C
L11
Reg
C
0.0
0x8000
84
0xFA Common address for PolyPhase outputs to
adjust common parameters.
0x80
NA
70
0xFD Commanded reset without requiring a power
down.
73
Note 1: Commands indicated with Y in the EEPROM column indicate that
these commands are stored and restored using the STORE_USER_ALL
and RESTORE_USER_ALL commands, respectively.
Note 4: Some of the unpublished commands are read-only and will
generate a CML bit 6 fault if written.
Note 5: Writing to commands not published in this table is not permitted.
Note 2: Commands with a default value of NA indicate “not applicable”.
Commands with a default value of FS indicate “factory set on a per part
basis”.
Note 3: The LTC3886 contains additional commands not listed in this
table. Reading these commands is harmless to the operation of the IC;
however, the contents and meaning of these commands can change
without notice.
Note 6: The user should not assume compatibility of commands
between different parts based upon command names. Always refer to
the manufacturer’s data sheet for each part for a complete definition of a
command’s function.
LTC strives to keep command functionality compatible between all LTC
devices. Differences may occur to address specific product requirements.
3886fe
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LTC3886
pMbꢀꢁ coMManD suMMary
*DATA FORMAT
L11 Linear_5s_11s
PMBus data field b[15:0]
N
Value = Y • 2
where N = b[15:11] is a 5-bit two’s complement integer and Y = b[10:0] is an 11-bit
two’s complement integer
Example:
For b[15:0] = 0x9807 = ‘b10011_000_0000_0111
–13
–6
Value = 7 • 2 = 854 • 10
From “PMBus Spec Part II: Paragraph 7.1”
L16 Linear_16u
PMBus data field b[15:0]
N
Value = Y • 2
where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit two’s
complement exponent that is hardwired to –12 decimal
Example:
For b[15:0] = 0x9800 = ‘b1001_1000_0000_0000
–12
Value = 38912 • 2 = 9.50
From “PMBus Spec Part II: Paragraph 8.2”
Reg Register
PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Description.
I16 Integer Word
PMBus data field b[15:0]
Value = Y
where Y = b[15:0] is a 16 unsigned integer
Example:
For b[15:0] = 0x9807 = ‘b1001_1000_0000_0111
Value = 38919 (decimal)
CF Custom Format
ASC ASCII Format
Value is defined in detailed PMBus Command Description.
This is often an unsigned or two’s complement integer scaled by an MFR specific
constant.
A variable length string of text characters conforming to ISO/IEC 8859-1 standard.
3886fe
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LTC3886
applicaTions inForMaTion
The Typical Application on the last page of this data sheet
is a common LTC3886 application circuit. The LTC3886
can be configured to use either DCR (inductor resistance)
sensingor lowvalue resistorsensing. The choice between
the two current sensing schemes is largely a design
trade-off between cost, power consumption and accu-
racy. DCR sensing is popular because it saves expensive
current sensing resistors and is more power efficient,
especially in high current applications. The LTC3886 can
nominally account for the temperature dependency of the
DCR sensing element. The accuracy of the current read-
ing and current limit are typically limited by the accuracy
of the DCR of the inductor (which is programmed as the
IOUT_CAL_GAIN register of the LTC3886). However, cur-
rent sensing resistors provide the most accurate current
sense and limiting. Other external component selections
are driven by the load requirement, and begins with the
For the best current limit accuracy, use the 75mV setting.
The 25mV setting will allow for the use of very low DCR
inductors or sense resistors, but at the expense of current
limit accuracy. Peak current limiting is on a cycle-by-cycle
basis. The average inductor current is monitored by the
ADC converter and can provide a warning if too much
average output current is detected. An overcurrent fault
is detected when the I voltage exceeds the limit set by
TH
IOUT_OC_FAULT_LIMIT. The digital processor within the
LTC3886providestheabilitytoeitherignorethefault,shut
down and latch off or shut down and retry indefinitely
(retry). Refer to the overcurrent portion of the Operation
section for more detail.
+
–
I
and I
PINS
SENSE
SENSE
+
–
The I
and I
pins are the inputs to the current
SENSE
SENSE
comparatorandtheA/D. Thecommonmodeinputvoltage
range of the current comparators is 0V to 14V. Both the
SENSE pins are high impedance inputs with small input
currents typically less than 1µA. The high impedance
inputs to the current comparators enable accurate DCR
sensing. Do not float these pins during normal operation.
selection of R
(if R
is used) and inductor value.
SENSE
SENSE
Next, thepower MOSFETs are selected. Then theinput and
output capacitors are selected. Finally the current limit is
selected. All of these components and ranges are required
to be determined prior to selecting the RITH and EA_GM
values in the MFR_PWM_COMP register and calculating
the external compensation components. The current limit
range is required because the two ranges (25mV to 50mV
vs 37.5mV to 75mV) have different EA gains set with bit 7
of the MFR_PWM_MODE_LTC3886 command. The volt-
age RANGE bit also affects the loop gain and impacts the
compensation network. The voltage RANGE is set with bit
1ofMFR_PWM_MODE_LTC3886.Allotherprogrammable
parametersdonotaffecttheloopgain,allowingparameters
to be modified without impacting the transient response
to load changes.
Filter components connected to the I
traces should
SENSE
be placed close to the IC. The positive and negative traces
should be routed differentially and Kelvin connected to
the current sense element, see Figure 24. A non-Kelvin
connection or improper placement can add parasitic in-
ductance and capacitance to the current sense element,
degradingthesignalatthesenseterminalsandmakingthe
programmed current limit perform poorly. In a PolyPhase
system, poor placement of the sensing element will result
in sub-optimal current sharing between power stages. If
DCRsensingisused(Figure25a),senseresistorR1should
be placed close to the inductor to prevent noise from
coupling into sensitive small-signal nodes. The capacitor
C1 should be placed close to the IC pins. Any impedance
CURRENT LIMIT PROGRAMMING
The LTC3886 has two ranges of current limit programming
and a total of eight levels within each range. Refer to the
IOUT_OC_FAULT_LIMITsectionofthePMBuscommands.
Within each range the error amp gain is fixed, resulting
in constant loop gain. The LTC3886 will account for the
temperature coefficient of the inductor DCR and automati-
cally adjust the current limit when inductor temperature
changes. The temperature coefficient of the DCR is stored
in the MFR_IOUT_CAL_GAIN_TC command.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
C
OUT
INDUCTOR OR R
3886 F24
SENSE
Figure 24. Optimal Sense Line Placement
3886fe
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LTC3886
applicaTions inForMaTion
+
–
difference between the I
and I
signal paths
LOW VALUE RESISTOR CURRENT SENSING
SENSE
SENSE
can result in loss of accuracy in the current reading of
the ADC. The current reading accuracy can be improved
by matching the impedance of the two signal paths. To
A typical sensing circuit using a discrete resistor is shown
in Figure 25b. R
output current.
is chosen based on the required
SENSE
accomplish this add a series resistor between V
and
OUT
–
The current comparator has a maximum threshold
determined by the I setting. The input
I
equal to R1. A capacitor of 1µF or greater should
SENSE
V
SENSE(MAX)
LIMIT
be placed in parallel with this resistor. If the peak voltage
common mode range of the current comparator is 0V to
is <75mV at room temperature, R2 is not required.
14V (if V is greater than 15V). The current comparator
IN
threshold sets the peak of the inductor current, yielding
V
IN
V
V
a maximum average output current I
equal to the
INTV
IN
CC
MAX
peak value less half the peak-to-peak ripple current ∆I .
L
BOOST
TG
To calculate the sense resistor value, use the equation:
INDUCTOR
DCR
L
SW
VS ENS E (MAX )
OUT
RS ENS E
=
LTC3886
∆IL
BG
IMAX
+
C2
2
GND
>1µF
R1
C1* R2
+
I
I
SENSE
Due to possible PCB noise in the current sensing loop, the
AC current sensing ripple of ∆V = ∆I • R also
R3
SENSE
L
SENSE
–
SENSE
needs to be checked in the design to get a good signal-to-
noise ratio. In general, for a reasonably good PCB layout,
OPTIONAL
R2
3886 F25a
2 × L
DCR
((R1+ R3)||R2) × C1 =
IOUT_CAL_GAIN = DCR ×
R1 + R2 + R3
a 15mV minimum ∆V
a conservative number to start with, either for R
DCR sensing applications.
voltage is recommended as
SENSE
R3 = R1
or
SENSE
+
–
*PLACE C1 NEAR SENSE , SENSE PINS
Figure 25a. Inductor DCR Current Sense Circuit
For previous generation current mode controllers, the
maximum sense voltage was high enough (e.g., 75mV for
theLTC1628/LTC3728family)thatthevoltagedropacross
the parasitic inductance of the sense resistor represented
a relatively small error. In the newer and higher current
density solutions, the value of the sense resistor can be
less than 1mΩ and the peak sense voltage can be less than
20mV. Also, inductor ripple currents greater than 50%
with operation up to 750kHz are becoming more common.
Under these conditions, the voltage drop across the sense
resistor’s parasitic inductance is no longer negligible. A
typical sensing circuit using a discrete resistor is shown in
Figure 25b. In previous generations of controllers, a small
RC filter placed near the IC was commonly used to reduce
the effects of the capacitive and inductive noise coupled
in the sense traces on the PCB. A typical filter consists of
two series 100Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 200ns.
V
IN
INTV
V
CC
IN
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
BOOST
TG
R
ESL
SW
S
V
OUT
LTC3886
BG
C • 2 ≤ ESL/R
F
RF
S
POLE-ZERO
GND
CANCELLATION
R
R
F
F
+
I
I
SENSE
C
F
–
3886 F25b
SENSE
FILTER COMPONENTS
PLACED NEAR SENSE PINS
Figure 25b. Resistor Current Sense Circuit
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LTC3886
applicaTions inForMaTion
This same RC filter with minor modifications, can be used
to extract the resistive component of the current sense
signalinthepresenceofparasiticinductance.Forexample,
Figure 26 illustrates the voltage waveform across a 2mΩ
resistor with a PCB footprint of 2010. The waveform is
the superposition of a purely resistive component and a
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
data, measure the voltage drop directly across the sense
resistor to extract the magnitude of the ESL step and use
Equation1todeterminetheESL.However,donotoverfilter
the signal. Keep the RC time constant less than or equal to
the inductor time constant to maintain a sufficient ripple
voltage on V
for optimal operation of the current
RSENSE
loop controller.
INDUCTOR DCR CURRENT SENSING
inductor ripple current and the on-time, t , and off-time,
ON
For applications requiring the highest possible efficiency
at high load currents, the LTC3886 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 25a. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such an
inductor, conduction loss through a sense resistor would
reduce the efficiency by a few percent compared to DCR
sensing.
t
, ofthetopswitch, thevalueoftheparasiticinductance
was determined to be 0.5nH using the equation:
OFF
VESL(STEP)
tON •tOFF
tON + tOFF
ESL =
•
(1)
∆IL
If the RC time constant is chosen to be close to the para-
sitic inductance divided by the sense resistor (L/R), the
resultantwaveformlooksresistive, asshowninFigure 27.
For applications using low maximum sense voltages,
check the sense resistor manufacturer’s data sheet for
information about parasitic inductance. In the absence of
If R1 = R3 and the external (R1 + R3)||R2 • C1 time con-
stant is chosen to be exactly equal to the 2 • L/DCR time
constant, assuming R1 = R3, the voltage drop across
the external capacitor,C1, is equal to the drop across the
inductor DCR multiplied by R2/(R1 + R2 + R3). R2 scales
the voltage across the sense terminals for applications
where the DCR is greater than the target sense resistor
value. The DCR value is entered as the IOUT_CAL_GAIN
in mΩ unless R2 is required. If R2 is used:
V
SENSE
20mV/DIV
V
ESL(STEP)
3886 F26
R2
IOUT_CAL_GAIN=DCR•
R1+R2+R3
500ns/DIV
Figure 26. Voltage Measured Directly Across RSENSE
R2 can be removed if there is no need to attenuate the
current sense signal in order to remain within the desired
current sense range. To properly select the external filter
components, the DCR of the inductor must be known. It
can be measured using an accurate RLC meter, but the
DCR tolerance is not always the same and varies with
temperature. Consult the inductor manufacturers’ data
sheets for detailed information. The LTC3886 will correct
for temperature variation if the correct temperature coef-
ficientvalueisenteredintotheMFR_IOUT_CAL_GAIN_TC
command. Typically the resistance has a 3900ppm/°C
coefficient.
V
SENSE
20mV/DIV
3886 F27
500ns/DIV
Figure 27. Voltage Measured After the RSENSE Filter
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LTC3886
applicaTions inForMaTion
AssumingR1=R3,C2canbeoptimizedforaflatfrequency
response using the following equation:
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduc-
ing conduction losses and provides higher efficiency at
heavy loads. Peak efficiency is about the same with either
method. Selecting discontinuous mode will improve the
converterefficiencyatlightloadsregardlessofthecurrent
sensing method.
L
2R1•R2•C1–
2R1+R2
(
)
DCR
C2=
2
R1
Using the inductor ripple current value from the Inductor
ValueCalculationsection,thetargetsenseresistorvalueis:
VSENSE(MAX)
RSENSE(EQUIV)
=
∆IL
To maintain a good signal-to-noise ratio for the current
IMAX
+
2
sense signal, use a minimum ∆V
of 10mV to 15mV.
ISENSE
For a DCR sensing application, the actual ripple voltage
will be determined by the equation:
To ensure that the application will deliver full load current
over the full operating temperature range, be sure to pick
the optimum I
value accounting for tolerance in the
V – V
VOUT
V •f
LIMIT
IN
OUT
∆V
=
•
ISENSE
DCRversustheMFR_IOUT_CAL_GAINparameterentered.
R1•C1
IN
OSC
Next, determine the DCR of the inductor. Use the manu-
facturer’s maximum value, which is usually specified at
20°C. Increase this value to account for tolerances in
the temperature sensing element of 3°C to 5°C and any
additional temperature differences associated with the
proximityofthetemperaturesensorelementtotheinductor.
SLOPE COMPENSATION AND INDUCTOR PEAK
CURRENT
Slope compensation provides stability in constant fre-
quency current mode architectures by preventing sub-
harmonic oscillations at high duty cycles. This is accom-
plished internally by adding a compensation ramp to the
inductor current signal at duty cycles in excess of 35%.
The LTC3886 uses a patented current limit technique that
cancels the effect of the compensating ramp. This allows
the maximum inductor peak current to remain unaffected
throughout all duty cycles.
C1 is usually selected to be in the range of 0.047µF to
4.7µF. This forces (R1 + R3)||R2 to be approximately 2k.
Adding optional elements R3 and C2 shown in Figure 18a
will minimize offset errors associated with the I
leak-
SENSE
age currents. Set R3 equal to the value of R1. Set C2 to a
value of 1µF or greater to ensure adequate noise filtering.
The equivalent resistance (R1 + R3)||R2 is scaled to the
room temperature inductance and maximum DCR:
INDUCTOR VALUE CALCULATION
2•L
Given the desired input and output voltages, the inductor
R1+R3 ||R2=
(
)
value and operating frequency, f , directly determine
OSC
DCR at 20°C •C1
the inductor peak-to-peak ripple current:
The maximum power loss in R1 is related to the duty
cycle, and will occur in continuous mode at the maximum
input voltage:
VOUT V – V
(
)
IN
OUT
IRIPPLE
=
V •fOSC •L
IN
V
IN(MAX) – VOUT •V
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highestefficiencyoperationisobtainedatthe
lowest frequency with a small ripple current. Achieving
this, however, requires a large inductor.
(
)
OUT
PLOSSR1=
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
3886fe
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LTC3886
applicaTions inForMaTion
A reasonable starting point is to choose a ripple current
voltage and maximum output current. Miller capacitance,
MILLER
that is about 40% of I
. Note that the largest ripple
OUT(MAX)
C
, can be approximated from the gate charge curve
current occurs at the highest input voltage. To guarantee
that the ripple current does not exceed a specified maxi-
mum, the inductor should be chosen according to:
usually provided on the MOSFET manufacturers’ data
sheet. C is equal to the increase in gate charge
MILLER
along the horizontal axis while the curve is approximately
flat divided by the specified change in V . This result is
DS
VOUT V – V
(
)
IN
OUT
then multiplied by the ratio of the application applied V
L≥
DS
V •f •IRIPPLE
to the gate charge curve specified V . When the IC is
IN
OSC
DS
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
INDUCTOR CORE SELECTION
VOUT
Once the inductor value is determined, the type of induc-
tor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent
on inductance. As the inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses increase.
Main Switch Duty Cycle=
V
IN
V – V
IN
OUT
Synchronous Switch Duty Cycle=
V
IN
The MOSFET power dissipations at maximum output
current are given by:
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core materials saturate hard, which means that the induc-
tance collapse abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
VOUT
2
PMAIN
=
I
1+δ R
+
(
(
)
(
)
MAX
DS(ON)
V
IN
IMAX
2
2
V
R
DR )(
C
•
(
)
)
IN
MILLER
1
1
+
•f
OSC
VINTVCC – VTH(MIN)
V
TH(MIN)
POWER MOSFET AND OPTIONAL SCHOTTKY DIODE
SELECTION
V – V
2
IN
OUT
PSYNC
=
I
(
1+δ R
DS(ON)
(
)
)
MAX
V
IN
Two external power MOSFETs must be selected for each
output channel in the LTC3886: one N-channel MOSFET
for the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
wheredis the temperature dependency of R
and
DS(ON)
R
(approximately 2Ω) is the effective driver resistance
DR
at the MOSFET’s Miller threshold voltage. V
typical MOSFET minimum threshold voltage.
is the
TH(MIN)
The peak-to-peak gate drive levels are set by the INTV
CC
voltage. This voltage is typically 5V. Consequently, logic-
level threshold MOSFETs must be used in most applica-
tions. Theonlyexceptionisiflowinputvoltageisexpected
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V < 20V
IN
(V < 5V); then, sub-logic level threshold MOSFETs
IN
GS(TH)
the high current efficiency generally improves with larger
(V
< 3V) should be used. Pay close attention to the
specification for the MOSFETs as well; most of the
MOSFETs, while for V > 20V the transition losses rapidly
IN
BV
DSS
increasetothepointthattheuseofahigherR
device
DS(ON)
logic-level MOSFETs are limited to 30V or less.
withlowerC
actuallyprovideshigherefficiency.The
MILLER
Selection criteria for the power MOSFETs include the
synchronous MOSFET losses are greatest at high input
on-resistance, R
, Miller capacitance, C , input
MILLER
voltage when the top switch duty factor is low or during
DS(ON)
3886fe
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a short-circuit when the synchronous switch is on close
to 100% of the period.
the same time. The total RMS power lost is lower when
both channels are operating due to the reduced overlap of
currentpulsesrequiredthroughtheinputcapacitor’sESR.
This is why the input capacitor’s requirement calculated
abovefortheworst-casescenarioisadequateforthedual
controller design. Also, if applicable the power losses
due to the input protection fuse resistance, VIN source
impedance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system.Theoverallbenefitofamultiphasedesignwillonly
be fully realized when the source impedance of the VIN
power supply/battery is included in the efficiency testing.
The drain terminals of the top MOSFETs should be placed
within 1cm of each other and share a common CIN(s).
Separating the sources and CIN may produce undesirable
voltage and current resonances on VIN.
The term (1 +d)is generally given for a MOSFET in the
form of a normalized R
vs Temperature curve,
DS(ON)
butd=0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes connected from ground to
SWnconductduringthedeadtimebetweentheconduction
ofthetwopowerMOSFETs.Thesepreventthebodydiodes
of the bottom MOSFETs from turning on, storing charge
during the dead time and requiring a reverse recovery
period that could cost as much as 3% in efficiency at high
V . A 1A to 3A Schottky is generally a good compromise
IN
for both regions of operation due to the relatively small
averagecurrent.Largerdiodesresultinadditionaltransition
losses due to their larger junction capacitance.
A small (0.1µF to 1µF) bypass capacitor between the chip
V pin and ground, placed close to the LTC3886, is also
IN
C AND C
SELECTION
IN
OUT
suggested. A 2.2Ω to 10Ω R
resistor placed between
VIN
C (C1) and the V pin provides further isolation if mul-
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle (V )/(V ). To prevent
IN
IN
tiple LTC3886s are used.
OUT
IN
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
The selection of C is driven by the effective series
OUT
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆V ) is approximated by:
1/2
IMAX
OUT
CIN Required IRMS
≈
V
V – V
IN
(
OUT )(
)
OUT
V
IN
1
∆VOUT ≈I
ESR+
RIPPLE
8fCOUT
This formula has a maximum at V = 2 • V , where
IN
OUT
I
= I /2. This simple worst-case condition is com-
RMS
OUT
where f is the operating frequency, C
is the output
monlyusedfordesignbecauseevensignificantdeviations
donotoffermuchrelief.Notethatcapacitormanufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
thanrequired.Severalcapacitorsmaybeparalleledtomeet
size or height requirements in the design. Due to the high
operating frequency of the LTC3886, ceramic capacitors
OUT
capacitance and I
is the ripple current in the
RIPPLE
inductor. The output ripple is highest at maximum input
voltage since I increases with input voltage.
RIPPLE
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
The LTC3886 must enter the run state prior to soft-start.
can also be used for C . Always consult the manufacturer
IN
The RUNn pin is released after the part initializes and V
IN
if there is any question.
isgreaterthantheVIN_ONthreshold.IfmultipleLTC3886s
are used in an application, they should be configured to
share the same RUNn pins. They all hold their respective
The benefit of using a LTC3886 in 2-phase operation can
be calculated by using the equation above for the higher
power channel and then calculating the loss that would
have resulted if both controller channels switched on at
RUNn pins low until all devices initialize and V exceeds
IN
the VIN_ON threshold for all devices. The SHARE_CLK
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pin assures all the devices connected to the signal use
the same time base for time delay operations.
The previously described method of start-up sequencing
is time based. For concatenated events it is possible to
control the RUNn pins based on the FAULTn pin of a dif-
ferent controller, or the PGOODn pin(s) of the LTC3886.
The FAULTn pins can be configured to release when the
output voltage of the converter is greater than the VOUT_
UV_FAULT_LIMIT.Itisrecommendedtousethedeglitched
AftertheRUNnpinreleases,thecontrollerwaitsfortheuser-
specified turn-on delay (TON_DELAY) prior to initiating
an output voltage ramp. Multiple LTC3886s and other LTC
parts can be configured to start with equal or unique delay
times. To work within a desired synchronization scheme
all devices must use the same timing clock (SHARE_CLK)
and all devices must share the RUNn pin. This allows the
relative delay of all parts to be synchronized. The actual
variationinthedelayswillbedependentonthehighestclock
rate of the devices connected to the SHARE_CLK pin (all
Linear Technology ICs are configured to allow the fastest
SHARE_CLK signal to control the timing of all devices).
The SHARE_CLK signal can be 10% in frequency, thus
the actual time delays will have proportional variance.
V
UV fault limit because there is little appreciable time
OUT
delaybetweentheconvertercrossingtheUVthresholdand
the FAULTn pin releasing. The deglitched output can be
enabled by setting the Mfr_FAULT_propagate_vout_uvuf
bitintheMFR_FAULT_PROPAGATE_LTC3886command.
Refer to the MFR section of the PMBus commands in this
document. The UV comparator output signal may have
some glitching as the V
signal transitions through the
OUT
comparator threshold. The LTC3886 includes a 250µs
digital deglitch filter to greatly reduce the probability of
multiple transitions. To minimize the risk of FAULTn pins
glitching, make the TON_RISE times less than 100ms. If
unwantedtransitionsstilloccuronFAULTn,placeacapaci-
tor to ground on the FAULTn pin to filter the waveform.
TheRCtime-constantofthefiltershouldbesetsufficiently
fast to assure no appreciable delay is incurred. A delay
of 300µs to 500µs will provide some additional filtering
without significantly delaying the trigger event.
Soft-startisperformedbyactivelyregulatingtheloadvolt-
age while digitally ramping the target voltage from 0.0V
to the commanded voltage set point. The rise time of the
voltage ramp can be programmed using the TON_RISE
commandtominimizeinrushcurrentsassociatedwiththe
start-up voltage ramp. The soft-start feature is disabled
by setting TON_RISE to any value less than 0.250ms. The
LTC3886 will perform the necessary math to assure the
voltage ramp is controlled to the desired slope. However,
thevoltageslopecannotbeanyfasterthanthefundamental
limits of the power stage. The shorter TON_RISE time is
set, the larger the discrete steps in the TON_RISE ramp
will appear. The number of steps in the ramp is equal to
TON_RISE/0.1ms.
DIGITAL SERVO MODE
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODE_LTC3886 command. In digital servo
modetheLTC3886willadjusttheregulatedoutputvoltage
based on the ADC voltage reading. Every 90ms the digital
servoloopwillsteptheLSBoftheDAC(nominally4mVor
2mV depending on the voltage range bit) until the output
is at the correct ADC reading. At power-up this mode
engages after TON_MAX_FAULT_LIMIT unless the limit
is set to 0 (infinite). If the TON_MAX_FAULT_LIMIT is set
to0(infinite),theservobeginsafterTON_RISEiscomplete
and VOUT has exceeded the VOUT_UV_FAULT_LIMIT.
This same point in time is when the output changes from
discontinuous to the programmed mode as indicated in
MFR_PWM_MODE_LTC3886 bit 0. Refer to Figure 28
for details on the VOUT waveform under time-based
The LTC3886 PWM will always use discontinuous mode
during the TON_RISE operation. In discontinuous mode,
the bottom gate is turned off as soon as reverse current
is detected in the inductor. This will allow the regulator to
start up into a pre-biased load.
TheLTC3886doesnotincludeatraditionaltrackingfeature.
However, two outputs can be given the same TON_RISE
and TON_DELAY times to effectively ramp up at the same
time. If the RUN pin is released at the same time and both
LTC3886s use the same time base, the outputs will track
very closely. If the circuit is in a PolyPhase configuration,
all timing parameters for that rail must be the same.
sequencing.
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RUN
DIGITAL SERVO
MODE ENABLED
FINAL OUTPUT
VOLTAGE REACHED
RUN
TON_MAX_FAULT_LIMIT
VOUT_UV_FAULT_LIMIT
DAC VOLTAGE
ERROR (NOT
TO SCALE)
TIME DELAY OF
200ms TO 400ms
V
OUT
V
OUT
3886 F29
TIME
TOFF_DELAY
TOFF_FALL
3886 F28
TIME
TON_RISE
TON_DELAY
Figure 28. Timing Controlled VOUT Rise
Figure 29. TOFF_DELAY and TOFF_FALL
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is set to
ignore (0x00), the servo begins:
main and synchronous MOSFETs turned off. The output
will decay as a function of the load rather than exhibiting
a controlled ramp.
1. After the TON_RISE sequence is complete
The output voltage will ramp as shown in Figure 29 so
long as the part is in forced continuous mode and the
TOFF_FALL time is slow enough that the power stage can
achieve the desired slope. The TOFF_FALL time can only
be met if the power stage and controller can sink sufficient
current to assure the output is at zero volts by the end of
the fall time interval. If the TOFF_FALL time is set shorter
than the time required to discharge the load capacitance,
the output will not reach the desired zero volt state. At the
end of TOFF_FALL, the controller will cease to sink current
2. After the TON_MAX_FAULT_LIMIT time is reached.
3. After the VOUT_UV_FAULT_LIMIT has been exceed or
the IOUT_OC_FAULT_LIMIT is not longer active.
If the TON_MAX_FAULT_LIMIT is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSE is not set
to ignore 0X00, the servo begins:
1. After the TON_RISE sequence is complete;
2. After the TON_MAX_FAULT_LIMIT time has expired
and both VOUT_UV_FAULT and IOUT_OC_FAULT are
not present.
and V
will decay at the natural rate determined by the
OUT
loadimpedance.Ifthecontrollerisindiscontinuousmode,
the controller will not pull negative current and the output
will be pulled low by the load, not the power stage. The
maximum fall time is limited to 1.3 seconds. The shorter
TOFF_FALL time is set, the larger the discrete steps of the
TOFF_FALL ramp will appear. The number of steps in the
ramp is typically TOFF_FALL/0.1ms.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase application only one phase should have
digital servo mode enabled. This will ensure the phases
servo to the same output regulation point.
SOFT OFF (SEQUENCED OFF)
INTV REGULATOR
CC
In addition to a controlled start-up, the LTC3886 also
supports controlled turn-off. The TOFF_DELAY and
TOFF_FALL functions are shown in Figure 29. TOFF_FALL
is processed when the RUN pin goes low or if the part is
commanded off. If the part faults off or FAULTn is pulled
low externally and the part is programmed to respond to
FAULTn, the output will three-state by turning off both the
The LTC3886 features a PMOS linear regulator that sup-
plies power to INTV from the V or EXTV supply.
CC
IN
DD33
CC
INTV powers the gate drivers, V
and much of the
CC
LTC3886 internal circuitry. The linear regulator produces
5V at the INTV pin when V or EXTV is greater than
CC
IN
CC
approximately 5.5V. The regulator can supply a peak cur-
rent of 100mA and must be bypassed to ground with a
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minimum of 1µF ceramic capacitor or low ESR electrolytic
capacitor.Nomatterwhattypeofbulkcapacitorisused,an
additional0.1µFceramiccapacitorplaceddirectlyadjacent
can pull the output below –0.3V, a Schottky diode from
GND to EXTV must be used to protect the EXTV pin.
CC
CC
For applications where V is 5V, tie the V and INTV
CC
IN
IN
totheINTV andGNDpinsishighlyrecommended. Good
CC
pinstogetherandtiethecombinedpinstothe5Vinputwith
a 1Ω or 2.2Ω resistor as shown in Figure 30. To minimize
the voltage drop caused by the gate charge current a low
bypassing is needed to supply the high transient currents
required by the MOSFET gate drivers.
High input voltage application in which large MOSFETs
ESR capacitor must be connected to the V /INTV pins.
IN CC
are being driven at high frequencies may cause the
maximum die junction temperature rating for the
LTC3886 to be exceeded. To reduce die temperature,
the INTVCC current, of which a large percentage is due
to the gate charge current, may be supplied from either
ThisconfigurationwilloverridetheINTV linearregulator
CC
and will prevent INTV from dropping too low. Make sure
CC
theINTV voltageexceedstheR
testvoltageforthe
CC
DS(ON)
MOSFETs which is typically 4.5V for logic level devices.
The UVLO on INTV is set to approximately 4V.
CC
the
V
or EXTV pin. If the LTC3886 internal regula-
CC
tor isINpowered from the
V pin, the power through the
IN
V
IN
IC is equal to VIN • IINTVCC. The gate charge current is
dependent on operating frequency as discussed in the
Efficiency Considerations section. The junction tempera-
ture can be estimated by using the equations in Note 2
of the Electrical Characteristics. For example, at 70°C
ambient, the LTC3886 INTVCC current is limited to less
than 44mA from a 40V supply:
R
LTC3886
INTV
VIN
1Ω
5V
CC
+
C
INTVCC
C
IN
4.7µF
3886 F30
Figure 30. Setup for a 5V Input
T = 70°C + 44mA • 40V • 31°C/W = 125°C
J
TOPSIDE MOSFET DRIVER SUPPLY (C , D )
B
B
To prevent the maximum junction temperature from being
exceeded, the LTC3886 internal LDO can be can powered
External bootstrap capacitors, C , connected to the
B
BOOSTnpinsuppliesthegatedrivevoltagesforthetopside
from the EXTV pin. If the EXTV pin is not used to
CC
CC
MOSFETs. Capacitor C in the Block Diagram is charged
B
power INTV , the EXTV pin must be tied to GND, do
CC
CC
though external diode D from INTV when the SWn pin
B
CC
not float this pin. The V current resulting from the gate
IN
is low. When one of the topside MOSFETs is to be turned
driver and control circuitry will be reduced to a minimum
on, the driver places the C voltage across the gate source
B
by supplying the INTV current from the EXTV pin with
CC
CC
of the desired MOSFET. This enhances the MOSFET and
an external supply or an output derived source.
turnsonthetopsideswitch.Theswitchnodevoltage,SWn,
rises to V and the BOOSTn pin follows. With the topside
IN
Tying the EXTV pin to a 5V supply reduces the junction
CC
MOSFET on, the boost voltage is above the input supply:
temperature in the previous example from 125°C to:
V
B
= V + V
. The value of the boost capacitor
BOOST
IN
INTVCC
T = 70°C + 44mA • 5V • 31°C/W + 2mA • 40V • 31°C/W
J
C needstobe100timesthatofthetotalinputcapacitance
=80°C
of the topside MOSFET(s). The reverse breakdown of the
external Schottky diode must be greater than V
.
Do not tie INTV on the LTC3886 to an external supply
IN(MAX)
CC
because INTV will attempt to pull the external supply
CC
PWM jitter has been observed in some designs operating
at higher V /V ratios. This jitter does not substantially
high and hit current limit, significantly increasing the
IN OUT
die temperature.
affect the circuit accuracy. Referring to Figure 31, PWM
jitter can be removed by inserting a series resistor with a
value of 1Ω to 5Ω between the cathode of the diode and
the BOOSTn pin.
Applyingvoltagesbelow–0.3VtotheEXTV pinmayresult
CC
in permanent damage to the device. If the EXTV pin is
CC
tied to an output of the controller and the external load
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by global address 5B command 0xBD and data 0xC4. The
part will now respond to the correct address. Configure
thepartasdesiredthenissueaSTORE_USER_ALL. When
V
V
IN
IN
1Ω TO 5Ω
C
BOOST
TGATE
B
0.2µF
V is applied a MFR_RESET command must be issued to
IN
D
B
LTC3886
allow the PWM to be enabled and valid ADC conversions
to be read.
SW
INTV
CC
BGATE
GND
C
INTVCC
10µF
FAULT INDICATIONS
3886 F31
The LTC3886 FAULTn pins are configurable to indicate a
variety of faults including OV, UV, OC, OT, timing faults,
peak overcurrent faults. In addition the FAULTn pins can
be pulled low by external sources indicating a fault in
some other portion of the system. The fault response is
configurable and allows the following options:
Figure 31. Boost Circuit to Minimize PWM Jitter
UNDERVOLTAGE LOCKOUT
The LTC3886 is initialized by an internal threshold-based
UVLO where V must be approximately 4V and INTV ,
IN
CC
n
Ignore
V
, V
must be within approximately 20% of the
regulated values. In addition, V
DD33 DD25
must be within ap-
n
DD33
Shut Down Immediately—Latch Off
proximately 7% of the targeted value before the RUN pin
is released. After the part has initialized, an additional
n
Shut Down Immediately—Retry Indefinitely at the
Time Interval Specified in MFR_RETRY_DELAY
comparator monitors V . The VIN_ON threshold must be
IN
exceeded before the power sequencing can begin. When
RefertothePMBussectionofthedatasheetandthePMBus
specification for more details regarding fault responses.
V drops below the VIN_OFF threshold, the SHARE_CLK
IN
pin will be pulled low and V must increase above the
IN
The OV response is always automatic. If an OV condition
is detected, TGn goes low and BGn is asserted.
VIN_ON threshold before the controller will restart. The
normalstart-upsequencewillbeallowedaftertheVIN_ON
threshold is crossed. If FAULTn is held low when V is
IN
OPEN-DRAIN PINS
applied, ALERT will be asserted low even if the part is
programmed to not assert ALERT when FAULTn is held
The LTC3886 has the following open-drain pins:
2
low. If I C communication occurs before the LTC3886 is
3.3V Pins
out of reset and only a portion of the command is seen by
the part, this can be interpreted as a CML fault. If a CML
fault is detected, ALERT is asserted low.
1. FAULTn
2. SYNC
It is possible to program the contents of the EEPROM in
3. SHARE_CLK
theapplicationiftheV
supplyisexternallydriven.This
DD33
4. PGOODn
will activate the digital portion of the LTC3886 without en-
gagingthehighvoltagesections.PMBuscommunications
5VPins(5Vpinsoperatecorrectlywhenpulledto3.3V.)
1. RUNn
2. ALERT
3. SCL
are valid in this supply configuration. If V has not been
IN
applied to the LTC3886, bit 3 (EEPROM Not Initialized)in
MFR_COMMON will be asserted low. If this condition is
detected,thepartwillonlyrespondtoaddresses5Aand5B.
To initialize the part issue the following set of commands:
global address 0x5B command 0xBD data 0x2B followed
4. SDA
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All the above pins have on-chip pull-down transistors that
can sink 3mA at 0.4V. The input low threshold on the pins
is 1.4V. Unless there are transient speed issues associ-
ated with the RC time constant of the resistor pull-up and
parasitic capacitance to ground, a 10k resistor or larger
is generally recommended.
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIꢀATION
The LTC3886 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of
the SYNC pin. The phase relationship between the PWM
controller and the falling edge of SYNC is controlled by the
lower 3 bits of the MFR_PWM_CONFIG_LTC3886 com-
mand. For PolyPhase applications, it is recommended all
the phases be spaced evenly. Thus for a 2-phase system
the signals should be 180° out of phase and a 4-phase
system should be spaced 90°.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time con-
stant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise time:
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
tRISE
3•100pF
RPULLUP
=
=1k
Minimize parasitic capacitance on the SDA and SCL
pins to avoid communication problems. To estimate the
loading capacitance, monitor the signal in question and
measure how long it takes for the desired signal to reach
approximately 63% of the output value. This is one time
constant.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
100kHz and 750kHz. Nominal parts will have a range be-
yond this; however, operation to a wider frequency range
is not guaranteed.
The SYNC pin has an on-chip pull-down transistor with
the output held low for nominally 500ns. If the internal
oscillator is set for 500kHz and the load is 100pF and a
3x time constant is required, the resistor calculation is
as follows:
The PLL has a lock detection circuit. If the PLL should lose
lockduringoperation,bit4oftheSTATUS_MFR_SPECIFIC
command is asserted and the ALERT pin is pulled low. The
fault can be cleared by writing a 1 to the bit. If the user
does not want the ALERT pin to assert if a PLL_FAULT
occurs, the SMBALERT_MASK command can be used to
prevent the alert.
2µs–500ns
3•100pF
RPULLUP
=
=5k
If timing errors are occurring or if the SYNC frequency is
notasfastasdesired,monitorthewaveformanddetermine
if the RC time constant is too long for the application. If
possible reduce the parasitic capacitance. If not reduce
the pull up resistor sufficiently to assure proper timing.
The SHARE_CLK pull-up resistor has a similar equation
with a period of 10μs and a pull-down time of 1µs. The
RC time constant should be approximately 3µs or faster.
If there is no external signal applied to the SYNC pin in
the application, the nominal programmed frequency will
control the PWM circuitry. If FREQUENCY_SWITCH is
programmed to external oscillator, and no external SYNC
signal is present, the LTC3886 PWM engine will run at the
lowest free running frequency of the PLL oscillator. This
may result in excess inductor current and undesirable
operation. If multiple parts share the SYNC signal and
the external SYNC signal is not present, the parts will not
be synchronized and excess voltage ripple on the output
may be present.
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Multiple LTC3886s are required to share one SYNC signal
in PolyPhase configurations, for other configurations
connecting the SYNC pins to form a single SYNC signal
is optional. If the SYNC pin is shared between LTC3886s,
onlyoneLTC3886shouldbeprogrammedwithafrequency
output. All the other LTC3886s should be programmed
to disable their SYNC output. However their frequency
should be programmed to the nominal desired value. If
the LTC3886 is programmed with a frequency output, and
an external signal is present. Bit 10 of MFR_PADS will be
asserted low if this condition exists.
at light loads. If the duty cycle drops below the minimum
on-timelimitinthissituation, asignificantamountofcycle
skipping can occur with correspondingly larger current
and voltage ripple.
EXTERNAL TEMPERATURE SENSE
The LTC3886 is capable of measuring the temperature of
the power stage temperature of each channel. Multiple
methods using silicon junction remote sensors are sup-
ported.Thevoltageproducedbytheremotesensecircuitis
digitizedbytheinternalADC,andthecomputedtemperature
value is returned by the paged READ_TEMPERATURE_1
telemetry command.
If the PWM signal appears to be running at too high a
frequency, monitor the SYNC pin. Extra transitions on
the falling edge will result in the PLL trying to lock on to
noise versus the intended signal. Review routing of digital
control signals and minimize crosstalk to the SYNC signal
to avoid this problem.
The most accurate external temperature measurement
can be made using a diode-connected PNP transistor
such as the MMBT3906 as shown in Figure 32. Bit 5 of
MFR_PWM_MODE_LTC3886 should be set to 0 (∆V
BE
method) when using this sensor configuration. The tran-
sistor should be placed in contact with or immediately
adjacent to the power stage inductor. Its emitter should
be connected to the TSNSn pin while the base and col-
lector terminals of the PNP transistor must be connected
and returned directly to Pin 53 of the LTC3886 using a
Kelvin connection. For best noise immunity, the connec-
tions should be routed differentially and a 10nF capacitor
should be placed in parallel with the diode-connected PNP.
Parasitic PCB trace inductance between the capacitor and
transistor should be minimized. Avoid placing PCB vias
between the transistor and capacitor.
MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, t
, is the smallest time duration
ON(MIN)
that the LTC3886 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn off the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
VOUT
tON(MIN)
<
V •f
IN
OSC
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The LTC3886 also supports direct junction voltage mea-
surements when bit 5 of MFR_PWM_MODE_LTC3886 is
settoone.Thefactorydefaultssupportaresistor-trimmed
dual diode network as shown in Figure 33. This second
measurement method is not generally as accurate as the
first, but it supports legacy power blocks or may prove
necessary if high noise environments prevent use of the
The minimum on-time for the LTC3886 is approximately
90ns. Good PCB layout, minimum 30% inductor current
ripple and at least 10mV to 15mV ripple on the current
sensesignalarerequiredtoavoidincreasingtheminimum
on-time. The minimum on-time can be affected by PCB
switchingnoiseinthevoltageandcurrentloop.Asthepeak
current sense voltage decreases, the minimum on-time
gradually increases to 130ns. This is of particular concern
in forced continuous applications with low ripple current
∆V approach with its lower signal levels.
BE
For either method, the slope of the external temperature
sensor can be modified with the coefficient stored in
MFR_TEMP_1_GAIN. With the ∆V approach, typical
BE
PNPs require temperature slope adjustments slightly
3886fe
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LTC3886
applicaTions inForMaTion
EEPROMstorage. SeetheOperationsectionforotherhigh
temperature EEPROM functional details. Degradation in
datacanbeapproximatedbycalculatingthedimensionless
acceleration factor using the following equation.
TSNS
LTC3886
GND
10nF
MMBT3906
GND
3886 F32
Ea
k
1
1
•
–
AF = e
Figure 32. External ΔVBE Temperature Sense
T
USE+273 TSTRESS+273
495µA
TSNS
where:
AF = acceleration factor
LTC3886
1nF
1.35V AT 25°C
Ea = activation energy = 1.4eV
GND
–5
k = 8.617 • 10 eV/°K
GND
3886 F33
T
T
= is the specified junction temperature
USE
Figure 33. 2D+R Temperature Sense
= actual junction temperature in °C
STRESS
less than 1. The MMBT3906 has a recommended value
of approximately MFR_TEMP_1_GAIN = 0.991 based
on the ideality factor of 1.01. Simply invert the ideality
factor to calculate the MFR_TEMP_1_GAIN. Different
manufacturers and different lots may have different ide-
ality factors. Consult with the manufacturer to set this
value. Characterization over temperature of a prototype
or prototypes is recommended before selecting a final
MFR_TEMP_1_GAIN value when using the direct p-n
junction measurement method.
Asanexample,ifthedeviceisstoredat130°Cfor10hours,
T
= 130°C, and
STRESS
1.4
1
1
•
–
–5
AF = e
=1.66
398 403
8.617•10
indicating the effect is the same as operating the device at
125°C for 10 • 1.66 = 16.6 hours, resulting in a retention
derating of 6.6 hours.
INPUT CURRENT SENSE AMPLIFIER
Theoffsetoftheexternaltemperaturesensecanbeadjusted
using MFR_TEMP_1_OFFSET.
The LTC3886 input current sense amplifier can sense the
supply current into the V pin using an external resistor
IN
If an external temperature sense element is not used, the
TSNSnpinmustbeshortedtoGND. TheUT_FAULT_LIMIT
mustbesetto–275°C,theUT_FAULT_RESPONSEmustbe
set to ignore, and the IOUT_CAL_GAIN_TC to a value of 0.
as well as the power stage current using an external sense
resistor.Unlesscareistakentomitigatethefrequencynoise
causedbythediscontinuousinputcurrent,significantinput
current measurement error may occur. The noise will be
the greatest in high current applications and at large step-
To ensure proper use of these temperature adjustment
parameters, refer to the specific formulas given for the
two methods in the MFR_PWM_MODE_LTC3886 com-
mand section.
down ratios. Careful layout and filtering at the V pin is
recommended to minimize measurement error. The V
IN
IN
pin should be filtered with a resistor and a ceramic capaci-
tor. The filter should be located as close to the V pin as
IN
Derating EEPROM Retention at Temperature
possible. The supply side of the V pin filter should be
IN
EEPROM read operations between –40°C and 125°C will
not affect data storage. But retention will be degraded if
the EEPROM is written above 85°C or stored or operated
above 125°C. If an occasional fault log is generated above
85°C, the slight reduction in data retention in the EEPROM
fault log area will not affect the use of the function or other
Kelvin connected to the supply side of the R
resistor.
IINSNS
A 2Ω resistor should be sufficient for most applications.
The resistor will cause an IR voltage drop from the sup-
ply to the V pin due to the current flowing into the V
IN
IN
pin. To compensate for this voltage drop, the MFR_RVIN
command value should be set to the nominal resistor
3886fe
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LTC3886
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value. The LTC3886 will multiply the MFR_READ_ICHIP
the RCONFIG pin while R
pin and GND. Noisy clock signals should not be routed
near these pins.
is connected between the
BOT
measurement value by the user defined MFR_RVIN value
and add this voltage to the measured voltage at the V pin.
IN
READ_VIN = V
+ (MFR_READ_ICHIP • MFR_RVIN)
VIN_PIN
Voltage Selection
Therefore, the READ_VIN command will return the value
When an output voltage is set using the VOUT_CFGn pins
the following parameters are set as a percentage of the
output voltage:
of the voltage at the supply side of the V pin filter. If no
IN
V filter element is used, set MFR_RVIN = 0.
IN
The capacitor from the drain of the topside MOSFET to
ground should be a low ESR ceramic capacitor. It should
be placed as close as possible to the drain of the topside
MOSFET to supply high frequency transient input current.
This will help prevent noise from the top gate MOSFET
from feeding into the input current sense amplifier inputs
and supply.
n
VOUT_OV_FAULT_LIMIT................................. +10%
n
VOUT_OV_WARN_LIMIT.................................+7.5%
n
VOUT_MAX......................................................+7.5%
n
VOUT_MARGIN_HIGH........................................+5%
n
VOUT_MARGIN_LOW.........................................–5%
n
VOUT_UV_WARN_LIMIT................................ –6.5%
If the input current sense amplifier is not used, short the
n
+
–
VOUT_UV_FAULT_LIMIT................................... –7%
V , I and I and pins together.
IN IN
IN
Refer to Table 3 to set the output voltage using the VOUT_
CFGn pins. 1% resistors must be used to assure proper
operation. If VOUT is seven volts or lower, low range is
used. When VOUT is set using the VOUTn_CFG pins, the
part will turn on the rail modifying the ON_OFF_CONFIG
command, if required, to respond to PMBus commands.
EXTERNAL RESISTOR CONFIGURATION PINS
(RCONFIG)
The LTC3886 is factory programmed to use external
resistor configuration. This allows output voltage, PWM
frequency, PWM phasing, and the PMBus address to be
set by the user without programming the part through the
PMBusinterfaceorpurchasingcustomprogrammedparts.
To use resistor programming, the RCONFIG pin(s) require
Table 3. VOUT_CFGn
R
(kΩ)
R
(kΩ)
V (V)
OUT
ON/OFF
EEPROM
ON
TOP
BOTTOM
0 or Open
10
Open
23.2
15.8
20.5
17.4
17.8
15
EEPROM
12.0
8.0
a resistor divider between V
and GND. The RCONFIG
DD25
pins are only interrogated at initial power up and during a
reset, so modifying their values on the fly while the part is
powered will have no effect. RCONFIG pins on the same IC
can be shared with a single resistor divider if they require
identical programming. Resistors with a tolerance of 1%
or better must be used to assure proper operation. In the
10
ON
16.2
16.2
20
7.0
ON
6.0
ON
5.0
ON
20
3.3
ON
20
12.7
11
2.5
ON
following tables, R
is connected between V
and
TOP
DD25
20
1.8
ON
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
1.5
ON
R
IINSNS
V
IN
1.2
ON
10µF
1.1
ON
TG
M1
M2
LTC3886
1.0
ON
I
I
-
IN
IN
2Ω
0.9
ON
+
SW
BG
V
0.75
0.65
EEPROM
ON
IN
10µF
3886 F34
ON
OFF
Figure 34. Low Noise Input Current Sense Circuit
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Frequency Selection
SWITCHING
FREQUENCY (kHz)
R
TOP
(kΩ)
R
BOT
(kΩ)
The PWM switching frequency is set according to Table 4.
The SYNC pins must be shared in poly-phase configura-
tions where multiple LTC3886s or multiple LTC3886s and
LTC3870s are used to produce the output. If the configu-
ration is not PolyPhase the SYNC pins do not have to be
shared. If the SYNC pins are shared between LTC3886s
only one SYNC pin should be enabled, all other SYNC pins
16.2
20.5
650
16.2
20
17.4
17.8
15
575
500
20
425
20
12.7
11
350
20
300
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
250
should be disabled. A pull-up resistor to V
on the SYNC pin.
is required
DD33
225
200
Forexampleina4-phaseconfigurationclockedat250kHz,
all of the LTC3886s must be set to the desired frequency
and phase and one LTC3886 should be set to the desired
frequency with the SYNC pin disabled. All phasing is with
respect to the falling edge of SYNC.
175
150
125
100
External SYNC Only
For LTC3886 chip 1, set the frequency to 250kHz with 90°
and 270° phase shift with the SYNC pin enabled:
Phase Selection
Frequency: R
= 24.9kΩ and R
= 11.3kΩ
TOP
BOT
The phase of the channels with respect to the falling edge
of SYNC is set using the values in Table 5.
Phase: R
= 30.1kΩ and R
= 1.96kΩ
TOP
BOT
Table 5. PHAS_CFG Resistor Programming
SYNC
For LTC3886 chip 2, set the frequency to 250kHz with 0°
and 180° phase shift and the SYNC pin disabled:
R
(kΩ)
R
(kΩ)
TO
TO
1
OUTPUT
EEPROM
EEPROM
EEPROM
TOP
BOT
SYNC
0
SYNC
Frequency: R
= 24.9kΩ and R
= 11.3kΩ
0 or Open
10
Open
EEPROM
EEPROM
EEPROM
120°
60°
EEPROM
EEPROM
EEPROM
300°
TOP
BOT
23.2
15.8
20.5
17.4
12.7
15
Phase: R
= 24.9kΩ and R
= 11.3kΩ
TOP
BOT
10
All configurations in frequency and phase can be achieved
using the FREQ_CFG and PHAS_CFG pins. In the above
application, if the SYNC pin connection is lost from chip 1,
chip 2 will internally detect the frequency as missing and
continue switching at 250kHz. However, because the
SYNC pin is disconnected between the chips, the output
voltage ripple will likely be higher than desired. Bit 10 of
MFR_PADS will assert low on chip 2 indicating chip 2 is
providing its own internal oscillator when it is expecting
an external SYNC input.
16.2
16.2
20
240°
120°
0°
240°
20
120°
DISABLED
20
12.7
11
0°
240°
20
90°
270°
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
0°
180°
120°
60°
300°
240°
120°
0°
240°
Table 4. FREQ_CFG Resistor Programming
120°
ENABLED
SWITCHING
FREQUENCY (kHz)
EEPROM
0°
240°
R
(kΩ)
R
(kΩ)
TOP
BOT
90°
270°
0 or Open
Open
0°
180°
10
10
23.2
15.8
EEPROM
750
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Address Selection Using RCONFIG
produce the most improvement. Percent efficiency can
be expressed as:
The LTC3886 address is selected based on the program-
ming of the two configuration pins ASEL0 and ASEL1
according to Table 6. ASEL0 programs the bottom four
bits of the device address for the LTC3886, and ASEL1
programs the three most-significant bits. Either portion of
theaddresscanalsoberetrievedfromtheMFR_ADDRESS
value in EEPROM. If both pins are left open, the full 7-bit
MFR_ADDRESS value stored in EEPROM is used to deter-
mine the device address. The LTC3886 always responds
to 7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS
should not be set to either of these values because these
are global addresses and all parts will respond to them.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3886 circuits: 1) IC V current, 2) INTV
IN
CC
2
regulator current, 3) I R losses, 4) Topside MOSFET
transition losses.
1. The V current is the DC supply current given in
IN
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. Supplying the
Table 6. ASELn Resistor Programming
INTV current from the EXTV pin with an external
CC
CC
ASEL1
ASEL0
supplywillreducetheV currentrequiredtoaminimum.
IN
LTC3886 DEVICE
ADDRESS BITS[6:4]
LTC3886 DEVICE
ADDRESS BITS[3:0]
2. INTV current is the sum of the MOSFET driver and
CC
R
(kΩ)
R
(kΩ)
BOT
BINARY
EEPROM
HEX
BINARY
EEPROM
HEX
TOP
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
0 or Open
10
Open
23.2
15.8
20.5
17.4
17.8
15
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
10
16.2
16.2
20
from INTV to ground. The resulting dQ/dt is a cur-
CC
rent out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
20
= f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
20
12.7
11
the topside and bottom side MOSFETs.
20
2
3. I R losses are predicted from the DC resistances of
24.9
24.9
24.9
24.9
24.9
30.1
30.1
Open
11.3
9.09
7.32
5.76
4.32
3.57
1.96
0
111
110
101
100
011
010
001
000
7
6
5
4
3
2
1
0
the fuse (if used), MOSFET, inductor and current sense
resistor.Incontinuousmode,theaverageoutputcurrent
flows through L and R
, but is “chopped” between
SENSE
the topside MOSFET and the synchronous MOSFET. If
thetwoMOSFETshaveapproximatelythesameR
,
DS(ON)
then the resistance of one MOSFET can simply be
summed with the resistances of L and R
to ob-
SENSE
2
tain I R losses. For example, if each R
= 10mΩ,
DS(ON)
R = 10mΩ, R
= 5mΩ, then the total resistance
L
SENSE
is 25mΩ. This results in losses ranging from 2% to
8% as the output current increases from 3A to 15A for
a 5V output, or a 3% to 12% loss for a 3.3V output.
EFFICIENCY CONSIDERATIONS
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
Efficiency varies as the inverse square of V
for the
OUT
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
3886fe
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LTC3886
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andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
Byadjustingtheg andR only,theLTC3886canprovide
m TH
a flexible type II compensation network to optimize the
loop over a wide range of output capacitors. Adjusting
the g will change the gain of the compensation over the
m
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
whole frequency range without moving the pole and zero
location, as shown in Figure 36.
TYPE II COMPENSATION
GAIN
2
Transition Loss = (1.7) V
I
C
f
IN O(MAX) RSS
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
INCREASE g
m
losses can be minimized by making sure that C has ad-
IN
equate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum
of 20µF to 40µF of capacitance having a maximum of
20mΩto50mΩofESR.TheLTC38862-phasearchitecture
typically halves this input capacitance requirement over
competingsolutions.OtherlossesincludingSchottkycon-
duction losses during dead time and inductor core losses
generally account for less than 2% total additional loss.
FREQUENCY
3886 F36
Figure 36. Error Amp gm Adjust
Adjusting the R will change the pole and zero location,
TH
as shown in Figure 37. It is recommended that the user
determines the appropriate value for the g and R using
m
TH
the LTpowerCAD® tool.
TYPE II COMPENSATION
GAIN
PROGRAMMABLE LOOP COMPENSATION
The LTC3886 offers programmable loop compensation
to optimize the transient response without any hardware
change. As shown in Figure 35, the error amplifier gain
g varies from 1.0mmho to 5.73mmho, and the compen-
m
sation resistor R varies from 0kΩ to 62kΩ inside the
TH
INCREASE R
TH
controller. Two compensation capacitors, C and C
,
TH
THP
are required in the design and the typical ratio between
FREQUENCY
3886 F37
C
TH
and C
is 10.
THP
Figure 37. RITH Adjust
CHECKING TRANSIENT RESPONSE
V
+
–
REF
g
m
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
FB
R
TH
load current. When a load step occurs, V
shifts by an
ITH_R
ITH
OUT
3886 F35
amount equal to ∆I
(ESR), where ESR is the effective
LOAD
C
C
THP
TH
series resistance of C . ∆I
also begins to charge or
OUT
LOAD
discharge C
generating the feedback error signal that
OUT
Figure 35. Programmable Loop Compensation
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LTC3886
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forces the regulator to adapt to the current change and
in output current may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
return V
to its steady-state value. During this recov-
OUT
OUT
ery time V
can be monitored for excessive overshoot
phase margin. This is why it is better to look at the I pin
TH
or ringing, which would indicate a stability problem.
The availability of the I pin not only allows optimization
signal which is in the feedback loop and is the filtered and
compensated control loop response. The gain of the loop
TH
of control loop behavior but also provides a DC-coupled
and AC-filtered closed-loop response test point. The DC
step, rise time and settling at this test point truly reflects
the closed-loop response. Assuming a predominantly
second order system, phase margin and/or damping fac-
tor can be estimated using the percentage of overshoot
seen at this pin. The bandwidth can also be estimated
will be increased by increasing R and the bandwidth
ITH
of the loop will be increased by decreasing C . If R is
C
ITH
increasedbythesamefactorthatC isdecreased, thezero
C
frequencywillbekeptthesame,therebykeepingthephase
shift the same in the most critical frequency range of the
feedback loop. The gain of the loop will be proportional to
the transconductance of the error amplifier which is set
using bits[7:5] of the MFR_PWM_COMP command. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance.
by examining the rise time at the pin. The I
external
THR
capacitor shown in the Typical Application circuit will
provide an adequate starting point for most applica-
tions. The programmable parameters that affect loop
gain are the voltage range, bit[1] of the MFR_PWM_
CONFIG_LTC3886 command, the current range, bit 7 of
theMFR_PWM_MODE_LTC3886command,thegmofthe
PWM channel amplifier, bits [7:5] of MFR_PWM_COMP,
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with C , causing a rapid drop in V . No regulator can
OUT
OUT
and the internal R compensation resistor, bits[4:0] of
ITH
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
MFR_PWM_COMP. Be sure to establish these settings
prior to compensation calculation.
The I series internal R - external C filter sets the
TH
ITH
C
C
LOAD
to C
is greater than 1:50, the switch rise time
OUT
dominant pole-zero loop compensation. The internal R
ITH
should be controlled so that the load rise time is limited
to approximately 25 • C . Thus a 10µF capacitor would
value can be modified (from 0Ω to 62kΩ) using bits[4:0]
of the MFR_PWM_COMP command. Adjust the value
LOAD
require a 250µs rise time, limiting the charging current
to about 200mA.
of R to optimize transient response once the final PC
ITH
layout is done and the particular C filter capacitor and
C
outputcapacitortypeandvaluehavebeendetermined.The
output capacitors need to be selected because the various
types and values determine the loop gain and phase. An
output current pulse of 20% to 80% of full-load current
having a rise time of 1µs to 10µs will produce output volt-
PolyPhase CONFIGURATION
WhenconfiguringaPolyPhaserailwithmultipleLTC3886s,
the user must share the SYNC, ITH, SHARE_CLK,
FAULTn, PGOODn and ALERT pins of both parts. Be sure
to use pull-up resistors on FAULTn, PGOODn, SYNC,
SHARE_CLK and ALERT. One of the LTC3886’s SYNC
pin must be set to the desired switching frequency, and
all other FREQUENCY_SWITCH commands must be set
to External Clock. If an external oscillator is provided, set
the FREQUENCY_SWITCH command to External Clock
for all LTC3886s. The relative phasing of all the channels
should be spaced equally. The MFR_RAIL_ADDRESS of
all the devices should be set to the same value.
age and I pin waveforms that will give a sense of the
TH
overall loop stability without breaking the feedback loop.
PlacingapowerMOSFETwitharesistortogrounddirectly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a load step. The MOSFET + R
will produce output
SERIES
currents approximately equal to V /R
. R
OUT SERIES
SERIES
valuesfrom0.1Ωto2Ωarevaliddependingonthecurrent
limit settings and the programmed output voltage. The
initial output voltage step resulting from the step change
3886fe
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R
IINSNS
V
IN
–
+
I
IN
I
IN
TSNS
Q1
LTC3886
+
L
R
SENSE
I
I
SENSE
V
OUT
TG
C1
R
VIN
–
SENSE
SW
V
IN
C
B
C
BOOST
BG
SYNC
M1
M2
VIN
D1
RUN
V
V
1µF
CERAMIC
+
SENSE
SENSE
–
I
INTV
CC
C
TH
+
OUT
+
C
IN
V
V
DD33
DD25
C
INTVCC
GND
3886 F38
Figure 38. Recommended Printed Circuit Layout Diagram, Single Phase Shown
3886fe
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SW1
L1
R
SENSE1
V
OUT1
D1
C
OUT1
R
L1
V
IN
R
IN
C
IN
SW0
L0
R
SENSE0
V
OUT0
D0
C
OUT0
R
L0
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
3886 F39
Figure 39. Branch Current Waveforms
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WhenconnectingaPolyPhaserailwithLTC3886s,connect
current sensing feedback pins. All of these nodes
have very large and fast moving signals and therefore
should be kept on the “output side” of the LTC3886
and occupy minimum PC trace area. If DCR sensing
is used, place the top resistor (Figure 25a, R1) close
to the switching node.
the V pins of the LTC3886s directly back to the supply
IN
voltage through the V pin filter networks.
IN
PC BOARD LAYOUT CHECKLIST
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 38. Figure 39 illustrates the cur-
rent waveforms present in the various branches of the
synchronous regulator operating in the continuous mode.
Check the following in your layout:
9. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV and
CC
EXTV decouplingcapacitors,thebottomofthevoltage
CC
feedback resistive divider and the GND pin of the IC.
+
–
10. Are the I
and I
pins Kelvin connected to the
IN
IN
1. Is the top N-channel MOSFET, M1, located within 1cm
R
sense resistor? This will prevent the PCB
SENSEIN
of C ?
IN
trace resistance from causing errors in the input
currentmeasurement.Thesetracesshouldbeasshort
as possible and routed away from any noisy nodes
such as the switching or boost nodes.
2. Aresignalgroundandpowergroundkeptseparate?The
ground return of C
OUT
must return to the combined
INTVCC
(–) terminals.
C
3. The I trace should be as short as possible.
TH
11. Is the V filter Kelvin connected to the input side
IN
of the R
resistor? This can help improve
4. The loop formed by the top N-channel MOSFET,
SENSEIN
the noise performance of the input current sense
amplifier by reducing the voltage transients between
the amplifier inputs and amplifier supply caused by
the discontinuous power stage current.
Schottky diode and the C capacitor should have
IN
short leads and PC trace lengths.
5. Theoutputcapacitor(–)terminalsshouldbeconnected
as close as possible to the (–) terminals of the input
capacitor by placing the capacitors next to each other
and away from the Schottky loop described in item 4.
PC BOARD LAYOUT DEBUGGING
ItishelpfultouseaDC-50MHzcurrentprobetomonitorthe
currentintheinductorwhiletestingthecircuit.Monitorthe
outputswitchingnode(SWnpin)tosynchronizetheoscil-
loscopetotheinternaloscillatorandprobetheactualoutput
voltageaswell.Checkforproperperformanceovertheoper-
atingvoltageandcurrentrangeexpectedintheapplication.
The frequency of operation should be maintained over
the input voltage range down to dropout and until the
output load drops below the low current operation
threshold.
+
–
6. Are the I
and I
leads routed together
SENSE
SENSE
with minimum PC trace spacing? The filter capacitor
+
–
between I
and I
should be as close as
SENSE
SENSE
possibletotheIC.Ensureaccuratecurrentsensingwith
Kelvin connections at the sense resistor or inductor,
whichever is used for current sensing.
7. Is the INTV decoupling capacitor connected close
CC
to the IC, between the INTV and the power ground
CC
pins?ThiscapacitorcarriestheMOSFETdrivercurrent
peaks. An additional 1µF ceramic capacitor placed
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawell-designed,lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
immediately next to the INTV and GND pins can
CC
help improve noise performance substantially.
8. Keep the switching nodes (SWn), top gate nodes
(TGn),andboostnodes(BOOSTn)awayfromsensitive
small-signal nodes, especially from the voltage and
bandwidth optimization is not required.
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Reduce V from its nominal level to verify operation
the current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due
to high frequency capacitive coupling. If problems are
encountered with high current output loading at lower
IN
of the regulator in dropout. Check the operation of the
undervoltagelockoutcircuitbyfurtherloweringV while
IN
monitoring the outputs to verify operation.
Investigatewhetheranyproblemsexistonlyathigherout-
put currents or only at higher input voltages. If problems
coincidewithhighinputvoltagesandlowoutputcurrents,
look for capacitive coupling between the BOOSTn, SWn,
TGn, and possibly BGn connections and the sensitive
voltage and current pins. The capacitor placed across
input voltages, look for inductive coupling between C ,
IN
SchottkyandthetopMOSFETcomponentstothesensitive
current and voltage sensing traces. In addition, investi-
gate common ground path voltage pickup between these
components and the GND pin of the IC.
10µF
2Ω
5mΩ
V
IN
20V TO 48V
22µF
10µF
1µF
+
–
D1
D2
0.1µF
INTV
TG0
V
I
I
CC IN IN IN
M1
M3
M2
M4
TG1
0.1µF
L0
L1
BOOST0
SW0
BOOST1
SW1
3.7µH
10µH
BG0
BG1
5k
LTC3886
1.61k
SYNC
4.7µF
6.04k
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
4.7µF
PGOOD0
PGOOD1
SDA
V
DD25
V
DD33
SCL
20k
10k
10k
10k
24.9k
11.3k
ALERT
FAULT0
FAULT1
V
V
OUT0_CFG
12.7k
23.2k
23.2k
23.2k
OUT1_CFG
ASEL0
ASEL1
SHARE_CLK
RUN0
FREQ_CFG
RUN1
WP
PHAS_CFG
+
1.61k
6.04k
+
–
I
I
SENSE0
SENSE1
0.470µF
0.470µF
12.1k
–
I
I
SENSE0
SENSE1
V
12V
5A
V
OUT1
OUT0
3.3V
10A
+
V
V
V
SENSE1
SENSE0
SENSE0
–
EXTV
CC
TSNS0
TSNS1
+
I
I
+
TH0
TH1
22µF
4×
150µF
2×
22µF
4×
150µF
2×
I
I
THR0
THR1
V
DD33
GND V
DD25
10nF
4.7µF
10nF
4700pF
4700pF
100pF
100pF
1µF
1µF
L0: WURTH 7443551370 3.7µH
L1: WURTH 74435561100 10µH
M1, M2: INFINEON BSC039N06NS
M3, M4: INFINEON BSC014N06NS
3886 F40
Figure 40. High Efficiency Dual 250kHz 12V/3.3V Step-Down Converter
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DESIGN EXAMPLE
Channel 0 will require 3.5µH and channel 1 will require
10.7µH. The nearest standard values are 3.7µH and 10µH
respectively. At the nominal input the ripple will be:
As a design example for a medium current regulator,
assume V = 48V nominal, V = 55V maximum, V
IN
OUT1
Figure 40).
IN
OUT0
= 3.3V, V
= 12V, I
= 10A and f = 250kHz (see
MAX0,1
VOUT
f•L
VOUT
∆IL(NOM)
=
1–
V
IN(NOM)
The regulated outputs are established by the VOUT_
COMMAND stored in EEPROM or placing the following
Channel 0 will have 3.32A (33%) ripple, and channel 1 will
have 3.6A (36%) ripple. The peak inductor current will be
the maximum DC value plus one-half the ripple current or
11.6Aforchannel0and11.8Aforchannel1.Theminimum
resistordividerbetweenV
theV
pinandGND:
DD25
OUTn_CFG
1. V
2. V
, R
= 20k, R
= 10k, R
= 12.7k
= 23.2k
OUT0_CFG TOP
BOTTOM
, R
OUT1_CFG TOP
BOTTOM
on time occurs on channel 0 at the maximum V , and
IN
The frequency and phase are set by EEPROM or by setting
should not be less than 90ns:
the resistor dividers between V
and GND.
DD25
VOUT
3.3V
•f 55V 250kHz
tON(MIN)
=
=
= 240ns
1. FREQ_CFG, R
= 24.9k, R
= Open, R
= 11.3k
= 0
TOP
BOTTOM
V
(
)
IN(MAX)
2. PHAS_CFG, R
TOP
BOTTOM
The Würth 7443551370 3.7µH (4.9mΩ DCR
at 25°C)
TYP
The address is set to XF where X is the MSB stored in
EEPROM.
channel 0 and the Wurth 744355611000 10µH (7mΩ
DCR at 25°C) channel 1 are the chosen inductors.
TYP
The following parameters are set as a percentage of the
output voltage if the resistor configuration pins are used
to determined output voltage:
2•L
2•3.7µH
R1+R3 =
=
(
)
DCR at 25°C •C1 4.9mΩ•0.47µF
(
)
n
VOUT_OV_FAULT_LIMIT..................................+10%
n
VOUT_OV_WARN_LIMIT.................................+7.5%
R1 = R3 = 1.61kΩ.
n
IOUT_CAL_GAIN= 4.9mΩ
VOUT_MAX......................................................+7.5%
n
VOUT_MARGIN_HIGH........................................+5%
The maximum power loss in R1 is related to the duty
cycle, and will occur in continuous mode at the maximum
input voltage:
n
VOUT_MARGIN_LOW.........................................–5%
VOUT_UV_WARN_LIMIT.................................–6.5%
VOUT_UV_FAULT_LIMIT....................................–7%
n
n
V
IN(MAX) – VOUT •V
(
(
)
OUT
All other user defined parameters must be programmed
into the EEPROM. The GUI can be utilized to quickly set
up the part with the desired operating parameters.
P
LOSS •R1=
R1
55–3.3 •3.3
)
=
= 55.9mW
3.05k
The inductance values are based on a 35% maximum
ripple current assumption (3.5A). The highest value of
ripple current occurs at the maximum input voltage:
The respective values for channel 1 are C1 = 0.47µF, R1 =
R3 = 6.08kΩ, R2 = 12.1kΩ, IOUT_CAL_GAIN = 3.45mΩ
and P
R1 = 84.9mW.
LOSS
VOUT
f•∆IL(MAX)
VOUT
L =
1–
V
IN(MAX)
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The current limit will be set 20% higher than the peak
value to assure variation in components and noise in the
system do not limit the average current.
ADDITIONAL DESIGN CHECKS
Tie FAULT0 and FAULT1 together and pull up to V
with a 10k resistor.
DD33
V
=I
•R
=1.2•11.3A•3.5mΩ=47.46mV
ILIMIT PEAK DCR(MAX)
Tie RUN0 and RUN1 together and pull up to V
a 10k resistor.
with
DD33
TheclosestV
settingis42.9mVor48.2mV.Thevalues
ILIMIT
are entered with the IOUT_OC_FAULT_LIMIT command.
Based on expected variation and measurement in the lab
across the sense capacitor the user can determine the
If there are other LTC PSM parts, connect the RUN pins
betweenchipsandconnecttheFAULTpinsbetweenchips.
Be sure all PMBus pins have resistor pull-up to V
optimalsetting.Forchannel1theV
The closest value is 53.6mV.
valueis49.56mV.
DD33
ILIMIT
and connect these inputs across all LTC PSM parts in the
application.
The power dissipation on the topside MOSFET can be
easily estimated. Choose an INFINEON BSC039N06NS
Tie SHARE_CLK high with a 10k resistor to V
and
DD33
share between all LTC PSM parts in the application.
topside MOSFET. R
= 3.9mΩ, C
= 75pF.
DS(ON)
MILLER
At maximum input voltage with T estimated = 50°C
and a bottom side INFINEON BSC014N06NS MOSFET,
DS(ON)
Be sure a unique address for each chip can be decoded
with the ASEL0 and ASEL1 pins. Refer to Table 6.
R
= 1.45mΩ:
For maximum flexibility, allow board space for R
BOTTOM
as ASEL0 and ASEL1.
and
TOP
3.3V
2
R
for any parameter that is set with resistors such
PMAIN
=
• 11.6 •1+ 0.005 50°C–25°C
(
)
(
)
(
)
55V
•0.0039Ω+ 55V 5.8A •
1
1
2
+
(
) (
)
2
5–2.8 2.8
CONNECTING THE USB TO I C/SMBus/PMBus
ADAPTER TO THE LTC3886 IN SYSTEM
59pF 250kHz = 0.245W
(
)(
)
2
The LTC USB to I C/SMBus/PMBus adapter (DC1613A or
equivalent) can be interfaced to the LTC3886 on the user’s
board for programming, telemetry and system debug.
The adapter, when used in conjunction with LTpowerPlay,
providesapowerfulwaytodebuganentirepowersystem.
Faults are quickly diagnosed using telemetry, fault status
commands and the fault log. The final configuration can
bequicklydevelopedandstoredtotheLTC3886EEPROM.
The loss in the bottom side MOSFET is:
55V –3.3V
(
)
2
PSYNC
=
• 11.6A •
(
)
55V
1+ 0.005 50°C–25°C •0.00145Ω
(
)
(
)
= 0.206W
2
Both MOSFETS have I R losses while the P
equation
MAIN
includes an additional term for transition losses, which
are highest at high input voltages.
Figure 41 illustrates the application schematic for pow-
ering, programming and communication with one or
2
more LTC3886s via the LTC I C/SMBus/PMBus adapter
C is chosen for an RMS current rating of:
IN
regardless of whether or not system power is present. If
system power is not present, the adapter will power the
11.8
55
IRMS
=
3.3 • 55–3.3 1/2 = 2.8A
(
) (
)
LTC3886 through the V
supply pin. To initialize the
DD33
part when V is not applied and the V
pin is pow-
IN
DD33
at temperature. C
is chosen with an ESR of 0.01Ω for
OUT
ered use global address 0x5B command 0xBD data 0x2B
followed by address 0x5B command 0xBD data 0xC4.
The LTC3886 will now communicate normally, and the
project file can be updated. To write the updated project
filetotheEEPROMissueaSTORE_USER_ALLcommand.
low output ripple. The output ripple in continuous mode
will be highest at the maximum input voltage. The output
voltage ripple due to ESR is
V
= R(∆I ) = 0.01Ω • 3.6A = 36mV.
L
ORIPPLE
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V
IN
LTC
100k
100k
CONTROLLER
V
V
IN
HEADER
ISOLATED
3.3V
V
DD33
DD25
TP0101K
SDA
SCL
1µF
1µF
LTC3886
10k
10k
SDA
SCL
WP GND
TO LTC DC1613
2
USB TO I C/SMBus/PMBus
CONTROLLER
V
V
IN
V
DD33
DD25
TP0101K
1µF
1µF
LTC3886
SDA
SCL
WP GND
VGS MAX ON THE TP0101K IS 8V IF V > 16V
IN
CHANGE THE RESISTOR DIVIDER ON THE PFET GATE
3886 F41
Figure 41. LTC Controller Connection
When VIN is applied, a MFR_RESET must be issued to
allow the PWM to be enabled and valid ADCs to be read.
LTpowerPlay:ANINTERACTIVEGUIFORDIGITALPOWER
LTpowerPlay is a powerful Windows-based development
environment that supports Linear Technology digital
power ICs including the LTC3886. The software sup-
ports a variety of different tasks. LTpowerPlay can be
used to evaluate Linear Technology ICs by connecting to
a demo board or the user application. LTpowerPlay can
also be used in an offline mode (with no hardware pres-
ent) in order to build multiple IC configuration files that
can be saved and re-loaded at a later time. LTpowerPlay
provides unprecedented diagnostic and debug features.
It becomes a valuable diagnostic tool during board bring-
up to program or tweak the power system or to diagnose
power issues when bringing up rails. LTpowerPlay utilizes
Becauseoftheadapter’slimitedcurrentsourcingcapabil-
ity, only the LTC3886s, their associated pull-up resistors
2
and the I C pull-up resistors should be powered from
the ORed 3.3V supply. In addition any device sharing
2
the I C bus connections with the LTC3886 should not
have body diodes between the SDA/SCL pins and their
respective V node because this will interfere with bus
DD
communication in the absence of system power. If V
IN
is applied the DC1613A will not supply power to the
LTC3886s on the board. It is recommended the RUNn
pins be held low or no voltage configuration resistors
inserted to avoid providing power to the load until the
part is fully configured.
2
Linear Technology’s USB-to-I C/SMBus/PMBus adapter
to communication with one of the many potential targets
including the DC2155A demo board, or a customer target
system. The software also provides an automatic update
feature to keep the revision current with the latest set of
device drivers and documentation. A great deal of context
sensitive help is available with LTpowerPlay along with
severaltutorialdemos.Completeinformationisavailableat:
TheLTC3886isfullyisolatedfromthehostPC’sgroundby
the DC1613A. The 3.3V from the adapter and the LTC3886
V
pin must be driven to each LTC3886 with a sepa-
DD33
rate PFET. If V is not applied, the V
pins can be in
IN
DD33
parallel because the on-chip LDO is off. The DC1613A’s
3.3V current limit is 100mA but typical V currents
DD33
are under 15mA. The V
does back drive the INTV /
DD33
CC
EXTV pins. Normally this is not an issue if V is open.
http://www.linear.com/ltpowerplay
CC
IN
3886fe
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Figure 42. LTpowerPlay Screen Shot
CMD
WRITE COMMAND
DATA BUFFER
PMBus
WRITE
it copies the data into the Write Command Data Buffer,
indicates to the internal processor that this command
data needs to be fetched, and converts the command to
its internal format so that it can be executed.
DECODER
INTERNAL
PAGE
•
•
•
0x00
0x21
PROCESSOR
CMDS
FETCH,
CONVERT
DATA
AND
EXECUTE
DATA
MUX
VOUT_COMMAND
•
•
•
Two distinct parallel blocks manage command buffering
and command processing (fetch, convert, and execute) to
ensure the last data written to any command is never lost.
CommanddatabufferinghandlesincomingPMBuswrites
by storing the command data to the Write Command Data
Buffer and marking these commands for future process-
ing. The internal processor runs in parallel and handles
the sometimes slower task of fetching, converting and
executing commands marked for processing.
MFR_RESET
x1
0xFD
S
R
CALCULATIONS
PENDING
3886 F43
Figure 43. Write Command Data Processing
PMBus COMMUNICATION AND COMMAND
PROCESSING
The LTC3886 has a one deep buffer to hold the last data
written for each supported command prior to processing
as shown in Figure 43; Write Command Data Processing.
When the part receives a new command from the bus,
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internalprocessorexecutiontimesthatmaybelongrelative
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// wait until chip is not busy
hi/lo, power off/on, moving to a new output voltage set
point, etc.) it will clear bit 4 of MFR_COMMON (‘output
not in transition’). When internal calculations are in
process, the part will clear bit 5 of MFR_COMMON
(‘calculations not pending’). These three status bits can
be polled with a PMBus read byte of the MFR_COMMON
register until all three bits are set. A command im-
mediately following the status bits being set will be
accepted without NACKing or generating a BUSY fault/
ALERT notification. The part can NACK commands for
other reasons, however, as required by the PMBus
spec (for instance, an invalid command or data). An
example of a robust command write algorithm for the
VOUT_COMMAND register is provided in Figure 44.
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonValue & 0x68) == 0x68;
}while(!partReady)
// now the part is ready to receive the next command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
Figure 44. Example of a Command Write of VOUT_COMMAND
toPMBustiming.Ifthepartisbusyprocessingacommand,
and new command(s) arrive, execution may be delayed
or processed in a different order than received. The part
indicateswheninternalcalculationsareinprocessviabit5
of MFR_COMMON (‘calculations not pending’). When the
part is busy calculating, bit 5 is cleared. When this bit is
set, the part is ready for another command. An example
polling loop is provided in Figure 44 which ensures that
commands are processed in order while simplifying error
handling routines.
It is recommended that all command writes (write byte,
write word, etc. ) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwantedALERTnotification. Asimplewaytoachievethis
is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_
WORD()subroutine.Theabovepollingmechanismallows
your software to remain clean and simple while robustly
communicating with the part. For a detailed discussion
of these topics and other special cases please refer to the
application note section located at:
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
or stretch the SCL clock low. Clock stretching can be en-
abled by asserting bit 1 of MFR_CONFIG_ALL_LTC3886.
Clock stretching will only occur if enabled and the bus
communication speed exceeds 100kHz.
www.linear.com/designtools/app_notes
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simplesolutionthatensuresrobustcommunicationwithout
clock stretching. At bus speeds in excess of 100kHz, it is
strongly recommended that the part be configured to en-
able clock stretching. This requires a PMBus master that
supports clock stretching. System software that detects
and properly recovers from the standard PMBus NACK/
BUSY faults is required.
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat com-
plex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
The three hand shaking status bits are in the MFR_
COMMON register. When the part is busy executing an
internal operation, it will clear bit 6 of MFR_COMMON
(‘chip not busy’). When the part is busy specifically
because it is in a transitional VOUT state (margining
The LTC3886 is not recommended in applications with
bus speeds in excess of 400kHz.
3886fe
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LTC3886
pMbuꢀ coMManD DeTails
ADDRESSING AND WRITE PROTECT
CMD
DATA
DEFAULT
COMMAND NAME
PAGE
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
0x00 Provides integration with multi-page PMBus devices. R/W Byte
N
N
Reg
Reg
0x00
PAGE_PLUS_WRITE
0x05 Write a supported command directly to a PWM
channel.
W Block
PAGE_PLUS_READ
WRITE_PROTECT
0x06 Read a supported command directly from a PWM
channel.
Block
R/W
N
N
0x10 Level of protection provided by the device against
accidental changes.
R/W Byte
Y
0x00
2
MFR_ADDRESS
0xE6 Sets the 7-bit I C address byte.
R/W Byte
R/W Byte
N
Y
Reg
Reg
Y
Y
0x4F
0x80
MFR_RAIL_ADDRESS
0xFA Common address for PolyPhase outputs to adjust
common parameters.
PAGE
The PAGE command provides the ability to configure, control and monitor both PWM channels through only one physi-
cal address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating commands for
one PWM channel.
Pages 0x00 and 0x01 correspond to Channel 0 and Channel 1, respectively, in this device.
Setting PAGE to 0xFF applies any following paged commands to both outputs. Reading from the device with PAGE
set to 0xFF is not recommended.
This command has one data byte.
PAGE_PLUS_WRITE
The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command, and then send
the data for the command, all in one communication packet. Commands allowed by the present write protection level
may be sent with PAGE_PLUS_WRITE.
The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send
a non-paged command, the Page Number byte is ignored.
This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a com-
mand that has two data bytes is shown in Figure 45.
1
7
1
1
8
1
8
1
8
1
8
1
SLAVE
ADDRESS
PAGE_PLUS
COMMAND CODE
BLOCK COUNT
(= 4)
PAGE
NUMBER
COMMAND
CODE
S
W
A
A
A
A
A
…
8
1
8
1
8
1
1
LOWER DATA
BYTE
UPPER DATA
BYTE
A
A
PEC BYTE
A
P
3886 F45
Figure 45. Example of PAGE_PLUS_WRITE
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PAGE_PLUS_READ
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command, and then read
the data returned by the command, all in one communication packet .
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access
data from a non-paged command, the Page Number byte is ignored.
This command uses Block Write-Block Read Process Call protocol. An example of the PAGE_PLUS_READ command
with PEC is shown in Figure 46.
1
7
1
1
8
1
8
1
8
1
8
1
SLAVE
ADDRESS
PAGE_PLUS
COMMAND CODE
BLOCK COUNT
(= 2)
PAGE
NUMBER
COMMAND
CODE
S
W
A
A
A
A
A
…
1
7
1
1
8
1
8
1
8
1
8
1
1
SLAVE
ADDRESS
BLOCK COUNT
LOWER DATA
BYTE
UPPER DATA
BYTE
Sr
R
A
A
A
A
PEC BYTE
NA
P
(= 2)
3886 F46
Figure 46. Example of PAGE_PLUS_READ
Note: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another
PAGE_PLUS command. If this is attempted, the LTC3886 will NACK the entire PAGE_PLUS packet and issue a CML
fault for Invalid/Unsupported Data.
WRITE_PROTECT
The WRITE_PROTECT command is used to control writing to the LTC3886 device. This command does not indicate
the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the
value of this command.
BYTE MEANING
0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_
EE_UNLOCK, and STORE_USER_ALL command.
0x40 Disable all writes except to the WRITE_PROTECT, PAGE,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,
OPERATION and CLEAR_FAULTS command. Individual fault
bits can be cleared by writing a 1 to the respective bits in the
STATUS commands.
0x20 Disable all writes except to the WRITE_PROTECT, OPERATION,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,
PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_
ALL. Individual fault bits can be cleared by writing a 1 to the
respective bits in the STATUS commands.
0x10 Reserved, must be 0
0x08 Reserved, must be 0
0x04 Reserved, must be 0
0x02 Reserved, must be 0
0x01 Reserved, must be 0
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When WRITE_PROTECT is set to 0x00, writes to all commands are enabled.
IfWPpinishigh,PAGE,OPERATION,MFR_CLEAR_PEAKS,MFR_EE_UNLOCK,WRITE_PROTECTandCLEAR_FAULTS
commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS
commands.
MFR_ADDRESS
The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,
cannot be deactivated. If RCONFIG is set to ignore, the ASEL0 and ASEL1 pins are still used to determine the LSB and
MSB, respectively, of the channel address. If the ASEL0 and ASEL1 pins are both open, the LTC3886 will use the ad-
dress value stored in EEPROM. If the ASEL0 pin is open, the LTC3886 will use the lower 4 bits of the MFR_ADDRESS
value stored in EEPROM to construct the effective address of the part. If the ASEL1 pin is open, the LTC3886 will use
the upper 3 bits of the MFR_ADDRESS value stored in EEPROM to construct the effective address of the part.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value
of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail
devices do not respond with EXACTLY the same value, the LTC3886 will detect bus contention and may set a CML
communications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
GENERAL CONFIGURATION COMMANDS
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
MFR_CHAN_CONFIG_LTC3886
0xD0
Configuration bits that are channel
R/W Byte
Y
N
Reg
Reg
Y
Y
0x1D
0x21
specific.
MFR_CONFIG_ALL_LTC3886
0xD1
General configuration bits.
R/W Byte
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MFR_CHAN_CONFIG_LTC3886
General purpose configuration command common to multiple LTC products.
BIT MEANING
7
6
5
4
3
Reserved
Reserved
Reserved
Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF.
Short Cycle. When asserted the output will immediate off if commanded ON while waiting for TOFF_DELAY or TOFF_FALL. TOFF_MIN of 120ms
is honored then the part will command ON.
2
1
0
SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled.
ALERT is not pulled low if FAULT is pulled low externally.
Disables the V
decay value requirement for MFR_RETRY_TIME processing. When this bit is set to a 0, the output must decay to less than
OUT
12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low
to high.
This command has one data byte.
MFR_CONFIG_ALL_LTC3886
General purpose configuration command common to multiple LTC products.
BIT MEANING
7
6
5
4
3
2
1
0
Enable Fault Logging
Ignore Resistor Configuration Pins
Disable CML Fault for Quick Command Message.
Disable SYNC output
Enable 255ms PMBus timeout
PMBus command writes require a valid Packet Error Checking, PEC, byte to be accepted.*
Enable the use of PMBus clock stretching
Execute CLEAR_FAULTS on rising edge of either RUN pin.
*PMBus command writes that have a valid PEC byte are always processed.
PMBus command writes that have an invalid PEC byte are not processed
and set a CML status fault.
This command has one data byte.
ON/OFF/MARGIN
CMD
DATA
DEFAULT
COMMAND NAME
ON_OFF_CONFIG
OPERATION
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte
Y
Y
Reg
Reg
Y
Y
0x1E
0x40
0x01 Operating mode control. On/off, margin high and margin R/W Byte
low.
MFR_RESET
0xFD Commanded reset without requiring a power-down.
Send Byte
N
NA
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ON_OFF_CONFIG
The ON_OFF_CONFIG command specifies the combination of RUNn pin input state and PMBus commands needed to
turn the PWM channel on and off.
Supported Values:
VALUE
0x1F
MEANING
OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off.
OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when commanded off.
RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored.
RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.
0x1E
0x17
0x16
Note: A high on the RUN pin is always required to start power conversion. Power conversion will always stop with a low on RUN.
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.
This command has one data byte.
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It
is also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in
the commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin
instructs the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next RESET
or POWER_ON cycle will ramp to that state. If the OPERATION command is modified, for example ON is changed
to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE. The default operation
command is sequence off. If V is applied to a part with factory default programming and the VOUT_CONFIG resistor
IN
configuration pins are not installed, the outputs will be commanded off.
The part defaults to the Sequence Off state.
This command has one data byte.
Supported Values:
VALUE
0xA8
MEANING
Margin high.
Margin low.
0x98
0x80
On (V
back to nominal even if bit 3 of ON_OFF_CONFIG is not set).
OUT
0x40*
0x00*
Soft off (with sequencing).
Immediate off (no sequencing).
*Device does not respond to these commands if bit 3 of ON_OFF_CONFIG is not set.
Programming an unsupported OPERATION value will generate a CML fault and the command will be ignored.
This command has one data byte.
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MFR_RESET
This command provides a means to reset the LTC3886 from the serial bus. This forces the LTC3886 to turn off both
PWM channels, load the operating memory from internal EEPROM, clear all faults and then perform a soft-start of
both PWM channels, if enabled.
This write-only command has no data bytes.
PWM CONFIGURATION
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
MFR_PWM_COMP
0xD3
0xD4
PWM loop compensation configuration
Configuration for the PWM engine.
R/W Byte
R/W Byte
Y
Y
Reg
Reg
Y
Y
0x70
0xC1
MFR_PWM_MODE_
LTC3886
MFR_PWM_CONFIG_
LTC3886
0xF5
0x33
Set numerous parameters for the DC/DC controller R/W Byte
including phasing.
N
N
Reg
L11
Y
Y
0x10
FREQUENCY_SWITCH
Switching frequency of the controller.
R/W
Word
kHz
350
0xFABC
MFR_PWM_MODE_LTC3886
The MFR_PWM_MODE_LTC3886 command sets important PWM controls for each channel. Bits [0] and [6] may be
changed when the addressed channel(s) is on,however the channel(s) must be turned off if any other bits are changed
when the command is issued. The LTC3886 will issue a CML fault and ignore the command and its data if the channel
is on and any bits other than [0] and [6] are changed.
The MFR_PWM_MODE_LTC3886 command allows the user to program the PWM controller to use discontinuous
(pulse-skipping mode), or forced continuous conduction mode.
BIT
MEANING
7
0b
1b
Use High Range of I
Low Current Range
High Current Range
LIMIT
6
5
Enable Servo Mode
External temperature sense:
0: ∆V measurement.
BE
1: Direct voltage measurement.
Reserved
[4:2]
1
V
Range
OUT
0b
1b
The maximum output voltage is 13.2V
The maximum output voltage is 7V
Bit[0] Mode
0b
1b
Discontinuous
Forced Continuous
Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command.
Changing this bit value changes the PWM loop gain and compensation. This bit value cannot be changed when the
channel output is active. Writing this bit when the channel is active will generate a CML fault.
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Bit [6] The LTC3886 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo
is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC
and the VOUT_COMMAND (or the appropriate margined value).
When Bit[5] is cleared, the LTC3886 computes temperature in °C from ∆V measured by the ADC at the TSNSn pin as
BE
T = (G • ∆V • q/(K • ln(16))) – 273.15 + O
BE
When Bit[5] is set, the LTC3886 computes temperature in °C from TSNSn voltage measured by the ADC as
T = (G • (1.35 – V
+ O)/4.3e-3) + 25
TSNSn
For both equations,
–14
G = MFR_TEMP_1_GAIN • 2 , and
O = MFR_TEMP_1_OFFSET
Bit[1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes
the PWM loop gain and compensation. This bit value cannot be changed when the channel output is active. Writing
this bit when the channel is active will generate a CML fault.
B
it[0]determinesifthePWMmodeofoperationisdiscontinuous(pulse-skippingmode),orforcedcontinuousconduction
mode. This command has one data byte. Whenever the channel is ramping on, the PWM mode will be discontinuous,
regardless of the value of this command.
MFR_PWM_COMP
The MFR_PWM_COMP command sets the gm of the PWM channel error amplifiers and the value of the internal R
ITHn
compensation resistors. This command affects the loop gain of the PWM output which may require modifications to
the external compensation network.
BIT
BIT [7:5]
000b
MEANING
EA (mS)
gm
1.00
1.68
2.35
3.02
3.69
4.36
5.04
5.73
001b
010b
011b
100b
101b
110b
111b
BIT [4:0]
00000b
00001b
00010b
00011b
00100b
00101b
R
ITH
(kΩ)
0
0.25
0.5
0.75
1
1.25
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BIT
MEANING
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
01110b
01111b
10000b
10001b
10010b
10011b
10100b
10101b
10110b
10111b
11000b
11001b
11010b
11011b
11100b
11101b
11110b
11111b
1.5
1.75
2
2.5
3
3.5
4
4.5
5
5.5
6
7
8
9
11
13
15
17
20
24
28
32
38
46
54
62
This command has one data byte.
MFR_PWM_CONFIG_LTC3886
The MFR_PWM_CONFIG_LTC3886 command sets the switching frequency phase offset with respect to the falling
edge of the SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low
or the part must be commanded off. If either channel is in the RUN state and this command is written, the command
will be NACK’d and a BUSY fault will be asserted.
BIT
MEANING
7
Use VFBO
0b
1b
Feedback nodes of both channels are independent.
Channel 1 uses the Channel 0 feedback node.
[6:5]
00b
01b
10b
11b
Input current sense gain.
2x gain. 0mV to 50mV range.
4x gain. 0mV to 20mV range.
8x gain. 0mV to 5mV range.
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BIT
MEANING
4
Share Clock Enable : If this bit is 1, the
SHARE_CLK pin will not be released until
V
> VIN_ON. The SHARE_CLK pin will be
IN
pulled low when V < VIN_OFF. If this bit is 0, the
IN
SHARE_CLK pin will not be pulled low when VIN <
VIN_OFF except for the initial application of VIN.
BIT [2:0]
000b
001b
010b
011b
100b
101b
110b
CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES)
0
90
0
180
270
240
120
240
240
300
0
120
60
120
+
Do not assert Bit[7] except for use in a PolyPhase configuration. The V
shared between channels when this bit is asserted.
n, I n, PGOODn and RUNn must be
TH
SENSEn
FREQUENCY_SWITCH
The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of a PMBus device.
Supported Frequencies:
VALUE [15:0]
0x0000
0xEB20
0xFBE8
0xF258
0xF2BC
0xF320
0xF384
0xF3E8
0xFA58
0xFABC
0xFB52
0xFBE8
0x023F
0x028A
0x02EE
RESULTING FREQUENCY (TYP)
External Oscillator
100kHz
125kHz
150kHz
175kHz
200kHz
225kHz
250kHz
300kHz
350kHz
425kHz
500kHz
575kHz
650kHz
750kHz
The part must be in the OFF state to process this command. The RUN pin must be low or both channels must be
commanded off. If the part is in the RUN state and this command is written, the command will be NACK'd and a BUSY
fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be
detected as the PLL locks onto the new frequency.
This command has two data bytes and is formatted in Linear_5s_11s format.
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VOLTAGE
Input Voltage and Limits
DATA
PAGED FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
UNITS
EEPROM
VIN_OV_FAULT_LIMIT
0x55
0x58
0x35
0x36
0xF7
Input supply overvoltage fault limit.
R/W
N
N
N
N
N
L11
L11
L11
L11
L11
V
Y
48.0
Word
0xE300
VIN_UV_WARN_LIMIT
VIN_ON
Input supply undervoltage warning limit.
R/W
Word
V
V
Y
Y
Y
Y
6.3
0xCB26
Input voltage at which the unit should start
power conversion.
R/W
Word
6.5
0xCB40
VIN_OFF
Input voltage at which the unit should stop
power conversion.
R/W
Word
V
6.0
0xCB00
MFR_RVIN
The resistance value of the V pin filter
R/W
Word
mΩ
3000
0x12EE
IN
element in milliohms
VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the input voltage measured by the ADC, in volts, that causes
an input overvoltage fault.
This command has two data bytes in Linear_5s_11s format.
VIN_UV_WARN_LIMIT
The VIN_UV_WARN_LIMIT command sets the value of input voltage measured by the ADC that causes an input under-
voltage warning. This warning is disabled until the input exceeds the input startup threshold value set by the VIN_ON
command and the unit has been enabled. If the VIN_UV_WARN_LIMIT is then exceeded, the device:
• Sets the INPUT Bit Is the STATUS_WORD
• Sets the V Undervoltage Warning Bit in the STATUS_INPUT Command
IN
• Notifies the Host by Asserting ALERT, Unless Masked
VIN_ON
The VIN_ON command sets the input voltage, in volts, at which the unit should start power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_OFF
The VIN_OFF command sets the input voltage, in volts, at which the unit should stop power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
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MFR_RVIN
The MFR_RVIN command is used to set the resistance value of the V pin filter element in milliohms. (See also
IN
READ_VIN). Set MFR_RVIN equal to 0 if no filter element is used.
This command has two data bytes and is formatted in Linear_5s_11s format.
Output Voltage and Limits
DATA
DEFAULT
VALUE
2
0x14
14.0
0xE000
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
R Byte
PAGED FORMAT
Y
UNITS
EEPROM
–12
VOUT_MODE
0x20
Output voltage format and exponent
Reg
L16
–12
(2 ).
VOUT_MAX
0x24
Upper limit on the output voltage
the unit can command regardless of
any other commands.
R/W
Word
Y
V
Y
VOUT_OV_FAULT_ LIMIT
VOUT_OV_WARN_ LIMIT
VOUT_MARGIN_HIGH
0x40
0x42
0x25
Output overvoltage fault limit.
R/W
Y
Y
Y
L16
L16
L16
V
V
V
Y
Y
Y
1.1
Word
0x119A
Output overvoltage warning limit.
R/W
Word
R/W
Word
1.075
0x1133
1.05
0x10CD
Margin high output voltage set
point. Must be greater than VOUT_
COMMAND.
VOUT_COMMAND
0x21
0x26
Nominal output voltage set point.
R/W
Y
Y
L16
L16
V
V
Y
Y
1.0
Word
0x1000
VOUT_MARGIN_LOW
Margin low output voltage set
point. Must be less than VOUT_
COMMAND.
R/W
Word
0.95
0x0F33
VOUT_UV_WARN_ LIMIT
VOUT_UV_FAULT_ LIMIT
MFR_VOUT_MAX
0x43
0x44
0xA5
Output undervoltage warning limit.
Output undervoltage fault limit.
Maximum allowed output voltage.
R/W
Y
Y
Y
L16
L16
L16
V
V
V
Y
Y
0.925
Word
0x0ECD
R/W
Word
R Word
0.9
0x0E66
14.0
0xE000
VOUT_MODE
The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode
(only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write
commands.
This read-only command has one data byte.
VOUT_MAX
The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can com-
mand regardless of any other commands or combinations. The maximum allowed value of this command is 14 volts.
The maximum output voltage the LTC3886 can produce is 14 volts including VOUT_MARGIN_HIGH. However, the
VOUT_OV_FAULT_LIMIT can only be commanded as high as 14 volts.
This command has two data bytes and is formatted in Linear_16u format.
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VOUT_OV_FAULT_LIMIT
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured by the OV supervisor compara-
tor at the sense pins, in volts, which causes an output overvoltage fault.
If the VOUT_OV_FAULT_LIMIT is modified and the part is in the RUN state, allow 10ms after the command is modified
to assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of
MFR_COMMON. Either bit is low if the part is busy. If this wait time is not met, and the VOUT_COMMAND is modified
above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and
possible damage to the switcher.
If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN or 0x00, the FAULT pin will not assert if VOUT_OV_FAULT
is propagated. The LTC3886 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_WARN_LIMIT
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured by the ADC at the sense pins,
in volts, which causes an output voltage high warning. The MFR_VOUT_PEAK value will be used to determine if this
limit has been exceeded.
In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
This condition is detected by the ADC so the response time may be up to 120ms.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_HIGH
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in volts, when
the OPERATION command is set to “Margin High”. The value must be greater than VOUT_COMMAND. The maximum
guaranteed value on VOUT_MARGIN_HIGH is 13.8 volts.
ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
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VOUT_COMMAND
The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed
value on VOUT is 13.2 volts.
ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_LOW
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts,
when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND.
ThiscommandwillnotbeactedonduringTON_RISEandTOFF_FALLoutputsequencing.TheVOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_WARN_LIMIT
The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured by the ADC at the sense pins,
in volts, which causes an output voltage low warning.
In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured by the UV supervisor com-
parator at the sense pins, in volts, which causes an output undervoltage fault.
This command has two data bytes and is formatted in Linear_16u format.
MFR_VOUT_MAX
The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel, including VOUT_OV_FAULT_
LIMIT. If the output voltages are set to high range (Bit 1 of MFR_PWM_MODE_LTC3886 set to a 0) MFR_VOUT_MAX is
14.0V. If the output voltage is set to low range (Bit 1 of MFR_PWM_MODE_LTC3886 set to a 1) the MFR_VOUT_MAX
is 7.0V. Entering a VOUT_COMMAND value greater than this will result in a CML fault and the output voltage setting
will be clamped to the maximum level. This will also result in Bit 3 VOUT_MAX_Warning in the STATUS_VOUT com-
mand being set.
This read only command has 2 data bytes and is formatted in Linear_16u format.
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OUTPUT CURRENT AND LIMITS
DATA
PAGED FORMAT UNITS EEPROM
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
IOUT_CAL_GAIN
0x38
The ratio of the voltage at the current R/W Word
sense pins to the sensed current. For
devices using a fixed current sense
resistor, it is the resistance value in
mΩ.
Y
L11
mΩ
Y
1.8
0xBB9A
MFR_IOUT_CAL_GAIN_TC
IOUT_OC_FAULT_LIMIT
IOUT_OC_WARN_LIMIT
0xF6
0x46
0x4A
Temperature coefficient of the current R/W Word
sensing element.
Y
Y
Y
CF
Y
Y
Y
3900
0x0F3C
Output overcurrent fault limit.
R/W Word
L11
L11
A
A
29.75
0xDBB8
Output overcurrent warning limit.
R/W Word
20.0
0xDA80
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the resistance value of the current sense resistor in milliohms. (see
also MFR_IOUT_CAL_GAIN_TC).
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_CAL_GAIN_TC
TheMFR_IOUT_CAL_GAIN_TCcommandallowstheusertoprogramthetemperaturecoefficientoftheIOUT_CAL_GAIN
sense resistor or inductor DCR in ppm/°C.
This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 •
–6
10 . Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by:
[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)]. DCR sensing will have a typical value of 3900.
The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT, MFR_
READ_IIN_CHAN, IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT.
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IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in amperes. When the controller
is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The programmed overcurrent
fault limit value is rounded up to the nearest one of the following set of discrete values:
25mV/IOUT_CAL_GAIN
28.6mV/IOUT_CAL_GAIN
32.1mV/IOUT_CAL_GAIN
35.7mV/IOUT_CAL_GAIN
39.3mV/IOUT_CAL_GAIN
42.9mV/IOUT_CAL_GAIN
46.4mV/IOUT_CAL_GAIN
50mV/IOUT_CAL_GAIN
37.5mV/IOUT_CAL_GAIN
42.9mV/IOUT_CAL_GAIN
48.2mV/IOUT_CAL_GAIN
53.6mV/IOUT_CAL_GAIN
58.9mV/IOUT_CAL_GAIN
64.3mV/IOUT_CAL_GAIN
69.6mV/IOUT_CAL_GAIN
75mV/IOUT_CAL_GAIN
Low Range (1.5x Nominal Loop Gain)
MFR_PWM_MODE_LTC3886 [7]=0
High Range (Nominal Loop Gain)
MFR_PWM_MODE_LTC3886 [7]=1
Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output
current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:
Peak Current Limit = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).
The LTpowerPlay GUI automatically convert the voltages to currents.
The I
range is set with bit 7 of the MFR_PWM_MODE_LTC3886 command.
OUT
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
If the IOUT_OC_FAULT_LIMIT is exceeded, the device:
• Sets the IOUT bit in the STATUS word
• Sets the IOUT Overcurrent fault bit in the STATUS_IOUT
• Notifies the host by asserting ALERT, unless masked
This command has two data bytes and is formatted in Linear_5s_11s format.
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IOUT_OC_WARN_LIMIT
This command sets the value of the output current measured by the ADC that causes an output overcurrent warning
in amperes. The READ_IOUT value will be used to determine if this limit has been exceeded.
In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format
Input Current and Limits
CMD
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
UNITS
EEPROM
MFR_IIN_CAL_GAIN
0xE8 The resistance value of the input current sense
element in mΩ.
R/W Word
L11
mΩ
Y
5.000
0xCA80
MFR_IIN_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the resistance value of the input current sense resistor in milliohms.
(see also READ_IIN).
This command has two data bytes and is formatted in Linear_5s_11s format.
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0x5D Input overcurrent warning
limit.
TYPE
PAGED
FORMAT
UNITS
EEPROM
IIN_OC_WARN_LIMIT
R/W Word
N
L11
A
Y
10.0
0xD280
IIN_OC_WARN_LIMIT
The IIN_OC_WARN_LIMIT command sets the value of the input current measured by the ADC, in amperes, that causes
a warning indicating the input current is high. The READ_IIN value will be used to determine if this limit has been
exceeded.
In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the INPUT bit in the upper byte of the STATUS_WORD
• Sets the IIN Overcurrent Warning bit[1] in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin
This command has two data bytes and is formatted in Linear_5s_11s format.
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TEMPERATURE
External Temperature Calibration
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
MFR_TEMP_1_GAIN
0xF8
Sets the slope of the external temperature
sensor.
R/W Word
Y
Y
CF
Y
Y
1.0
0x4000
MFR_TEMP_1_OFFSET
0xF9
Sets the offset of the external temperature R/W Word
sensor.
L11
C
0.0
0x8000
MFR_TEMP_1_GAIN
TheMFR_TEMP_1_GAINcommandwillmodifytheslopeoftheexternaltemperaturesensortoaccountfornon-idealities
in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in 16-bit 2’s complement integer. The effective gain adjustment is
–14
N • 2 . The nominal value is 1.
MFR_TEMP_1_OFFSET
The MFR_TEMP_1_OFFSET command will modify the offset of the external temperature sensor to account for non-
idealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in Linear_5s_11s format.
External Temperature Limits
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
UNITS
EEPROM
OT_FAULT_LIMIT
0x4F
0x51
0x53
External overtemperature fault limit.
R/W Word
Y
L11
L11
L11
C
Y
100.0
0xEB20
OT_WARN_LIMIT
UT_FAULT_LIMIT
External overtemperature warning
limit.
R/W Word
Y
Y
C
C
Y
Y
85.0
0xEAA8
External undertemperature fault limit. R/W Word
–40.0
0xE580
OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees
Celsius, which causes an overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this
limit has been exceeded.
This command has two data bytes and is formatted in Linear_5s_11s format.
OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the value of the external sense temperature measured by the ADC, in degrees
Celsius, which causes an overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if
this limit has been exceeded.
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In response to the OT_WARN_LIMIT being exceeded, the device:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has two data bytes and is formatted in Linear_5s_11s format.
UT_FAULT_LIMIT
TheUT_FAULT_LIMITcommandsetsthevalueoftheexternalsensetemperaturemeasuredbytheADC,indegreesCelsius,
whichcausesanundertemperaturefault.TheREAD_TEMPERATURE_1valuewillbeusedtodetermineifthislimithasbeen
exceeded.
Note: If the temp sensors are not installed, the UT_FAULT_LIMIT can be set to –275°C and UT_FAULT_LIMIT response
set to ignore to avoid ALERT being asserted.
This command has two data bytes and is formatted in Linear_5s_11s format.
TIMING
Timing—On Sequence/Ramp
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
TON_DELAY
0x60
Time from RUN and/or Operation on to
R/W Word
Y
Y
L11
L11
ms
ms
Y
Y
0.0
output rail turn-on.
0x8000
TON_RISE
0x61
Time from when the output starts to
rise until the output voltage reaches the
VOUT commanded value.
Maximum time from the start of TON_
RISE for VOUT to cross the VOUT_UV_
FAULT_LIMIT.
R/W Word
R/W Word
R/W Word
8.0
0xD200
TON_MAX_FAULT_LIMIT
VOUT_TRANSITION_RATE
TON_DELAY
0x62
0x27
Y
Y
L11
L11
ms
Y
Y
10.0
0xD280
Rate the output changes when VOUT
commanded to a new value.
V/ms
0.25
0xAA00
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output
voltage starts to rise. Values from 0ms to 83 seconds are valid. The resulting turn-on delay will have a typical delay of
270µs for TON_DELAY = 0 and an uncertainty of 50µs for all values of TON_DELAY.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_RISE
The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output
enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during
TON_RISE events. If TON_RISE is less than 0.25ms, the LTC3886 digital slope will be bypassed and the output voltage
transition will only be controlled by the analog performance of the PWM switcher. The number of steps in TON_RISE
is equal to TON_RISE (in ms)/0.1ms with an uncertainty of 0.1ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
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TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power
up the output without reaching the output undervoltage fault limit, or output overcurrent limit.
A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely.
The maximum limit is 83 seconds.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOUT_TRANSITION_RATE
When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the
output voltage to change this command set the rate in V/ms at which the output voltage changes. This commanded
rate of change does not apply when the unit is commanded on or off. The maximum allowed slope is 4V/ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
Timing—Off Sequence/Ramp
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
FORMAT UNITS EEPROM VALUE
TOFF_DELAY
0x64
0x65
0x66
Time from RUN and/or Operation off to
the start of TOFF_FALL ramp.
Time from when the output starts to fall R/W Word
until the output reaches zero volts.
Maximum allowed time, after TOFF_FALL R/W Word
completed, for the unit to decay below
12.5%.
R/W Word
Y
L11
L11
L11
ms
ms
ms
Y
Y
Y
0.0
0x8000
TOFF_FALL
Y
Y
8.0
0xD200
150
0xF258
TOFF_MAX_WARN_LIMIT
TOFF_DELAY
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output
voltage starts to fall. Values from 0 to 83 seconds are valid. The resulting turn off delay will have a typical delay of
270µs for TOFF_DELAY = 0 and an uncertainty of 50µs for all values of TOFF_DELAY. TOFF_DELAY is not applied
when a fault event occurs
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_FALL
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt-
age is commanded to zero. It is the ramp time of the V
set to high impedance state.
DAC. When the V
DAC is zero, the PWM output will be
OUT
OUT
The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part
to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate.
The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum
fall time is 1.3 seconds. The number of steps in TOFF_FALL is equal to TOFF_FALL (in ms)/0.1ms with an uncertainty
of 0.1ms.
In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by
the output capacitance and load current.
This command has two data bytes and is formatted in Linear_5s_11s format.
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TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to turn off
the output until a warning is asserted. The output is considered off when the V
voltage is less than 12.5% of the
OUT
programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete.
A data value of 0ms means that there is no limit and that the unit can attempt to turn off the output voltage indefinitely.
Other than 0, values from 120ms to 524 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
Precondition for Restart
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
0xDC Minimum time the RUN pin is held
low by the LTC3886.
TYPE
PAGED
FORMAT
UNITS
EEPROM
MFR_RESTART_ DELAY
R/W Word
Y
L11
ms
Y
500
0xFBE8
MFR_RESTART_DELAY
This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length
of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.
Note: The restart delay is different than the retry delay. The restart delay pulls RUN low for the specified time, after
which a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_
FALL + 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time,
set the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_
RESTART_DELAY after the RUN pin is pulled high if the output decay bit 0 is enabled in MFR_CHAN_CONFIG_LTC3886
and the output takes a long time to decay below 12.5% of the programmed value.
This command has two data bytes and is formatted in Linear_5s_11s format.
FAULT RESPONSE
Fault Responses All Faults
DATA
FORMAT
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
UNITS
EEPROM
MFR_RETRY_ DELAY
0xDB
Retry interval during FAULT retry R/W Word
mode.
Y
L11
ms
Y
350
0xFABC
MFR_RETRY_DELAY
This command sets the time in milliseconds between retries if the fault response is to retry the controller at specified
intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has
been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 1ms increments.
Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required
for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is
too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of
MFR_CHAN_CONFIG_LTC3886.
This command has two data bytes and is formatted in Linear_5s_11s format.
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Fault Responses Input Voltage
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
VIN_OV_FAULT_RESPONSE
0x56
Action to be taken by the device when an R/W Byte
input supply overvoltage fault is detected.
Y
Reg 0x80
Y
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input over-
voltage fault. The data byte is in the format given in Table 11.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Set the INPUT bit in the upper byte of the STATUS_WORD
• Sets the VIN Overvoltage Fault bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
Fault Responses Output Voltage
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
VOUT_OV_FAULT_RESPONSE
0x41
0x45
0x63
Action to be taken by the device when an R/W Byte
output overvoltage fault is detected.
Y
Y
Y
Reg
Reg
Reg
Y
Y
Y
0xB8
0xB8
0xB8
VOUT_UV_FAULT_RESPONSE
Action to be taken by the device when an R/W Byte
output undervoltage fault is detected.
TON_MAX_FAULT_
RESPONSE
Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte
VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overvoltage fault. The data byte is in the format given in Table 7.
The device also:
• Sets the VOUT_OV bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
The only values recognized for this command are:
0x00–Part performs OV pull down only, or OV_PULLDOWN.
0x80–The device shuts down (disables the output) and the unit does not attempt to retry. (PMBus, Part II, Section 10.7).
0xB8–The device shuts down (disables the output) and device attempts to retry continuously, without limitation, until
it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down.
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0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is com-
manded OFF then ON or the RUN pin is asserted low then high or RESET through the command or removal of VIN.
The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared
or the part is commanded OFF then ON or the RUN pin is asserted low then high or RESET through the command or
removal of VIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
Any other value will result in a CML fault and the write will be ignored.
This command has one data byte.
Table 7. VOUT_OV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
Part performs OV pull down only or OV_PULLDOWN
(i.e., turns off the top MOSFET and turns on lower MOSFET
while V is > VOUT_OV_FAULT).
For all values of bits [7:6], the LTC3886:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
OUT
01
The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for that
particular fault. If the fault condition is still present at the end of
the delay time, the unit responds as programmed in the Retry
Setting (bits [5:3]).
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
10
11
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
Not supported. Writing this value will generate a CML fault.
• Bias power is removed and reapplied to the LTC3886.
5:3
2:0
Retry Setting
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
000-111 The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
undervoltage fault. The data byte is in the format given in Table 8.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked
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The UV fault and warn are masked until the following criteria are achieved:
1) The TON_MAX_FAULT_LIMIT has been reached
2) The TON_DELAY sequence has completed
3) The TON_RISE sequence has completed
4) The VOUT_UV_FAULT_LIMIT threshold has been reached
5) The IOUT_OC_FAULT_LIMIT is not present
The UV fault and warn are masked whenever the channel is not active.
The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.
This command has one data byte.
Table 8. VOUT_UV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
The PMBus device continues operation without interruption.
(Ignores the fault functionally)
For all values of bits [7:6], the LTC3886:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
01
The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for
that particular fault. If the fault condition is still present at the
end of the delay time, the unit responds as programmed in the
Retry Setting (bits [5:3]).
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
10
11
The device shuts down (disables the output) and responds
according to the retry setting in bits [5:3].
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
Not supported. Writing this value will generate a CML fault.
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
000-111 The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
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TON_MAX_FAULT_RESPONSE
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX
fault. The data byte is in the format given in Table 11.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
• Notifies the host by asserting ALERT pin, unless masked
A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.
This command has one data byte.
Fault Responses Output Current
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
IOUT_OC_FAULT_RESPONSE
0x47
Action to be taken by the device when an R/W Byte
output overcurrent fault is detected.
Y
Reg 0x00
Y
IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overcurrent fault. The data byte is in the format given in Table 9.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT_OC bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
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Table 9. IOUT_OC_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
The LTC3886 continues to operate indefinitely while maintaining
the output current at the value set by IOUT_OC_FAULT_LIMIT
without regard to the output voltage (known as constant-
current or brick-wall limiting).
For all values of bits [7:6], the LTC3886:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
01
10
Not supported.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
The LTC3886 continues to operate, maintaining the output
current at the value set by IOUT_OC_FAULT_LIMIT without
regard to the output voltage, for the delay time set by bits [2:0].
If the device is still operating in current limit at the end of the
delay time, the device responds as programmed by the Retry
Setting in bits [5:3].
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
11
The LTC3886 shuts down immediately and responds as
programmed by the Retry Setting in bits [5:3].
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared by cycling the RUN pin or
removing bias power.
The device attempts to restart continuously, without limitation,
until it is commanded OFF (by the RUN pin or OPERATION
command or both), bias power is removed, or another fault
condition causes the unit to shut down. Note: The retry interval
is set by the MFR_RETRY_DELAY command.
Delay Time
000-111 The number of delay time units in 16ms increments. This
delay time is used to determine the amount of time a unit is
to continue operating after a fault is detected before shutting
down. Only valid for deglitched off response.
Fault Responses IC Temperature
DATA
DEFAULT
VALUE
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM
MFR_OT_FAULT_
RESPONSE
0xD6
Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte
N
Reg
0xC0
MFR_OT_FAULT_RESPONSE
The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal
overtemperature fault. The data byte is in the format given in Table 10.
The LTC3886 also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD, and
• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
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Table 10. Data Byte Contents MFR_OT_FAULT_RESPONSE
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
01
10
Not supported. Writing this value will generate a CML fault.
Not supported. Writing this value will generate a CML fault
For all values of bits [7:6], the LTC3886:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
The device’s output is disabled while the fault is present.
Operation resumes and the output is enabled when the fault
condition no longer exists.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTC3886.
5:3
2:0
Retry Setting
000
The unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001-111 Not supported. Writing this value will generate CML fault.
Delay Time
XXX
Not supported. Value ignored
Fault Responses External Temperature
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
OT_FAULT_ RESPONSE
0x50
Action to be taken by the device when an
external overtemperature fault is detected,
R/W Byte
Y
Reg
Reg
Y
0xB8
0xB8
UT_FAULT_ RESPONSE
0x54
Action to be taken by the device when an
external undertemperature fault is detected.
R/W Byte
Y
Y
OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an external overtem-
perature fault on the external temp sensors. The data byte is in the format given in Table 11.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
This command has one data byte.
UT_FAULT_RESPONSE
The UT_FAULT_RESPONSE command instructs the device on what action to take in response to an external under-
temperature fault on the external temp sensors. The data byte is in the format given in Table 11.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked
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This condition is detected by the ADC so the response time may be up to 90ms.
This command has one data byte.
Table 11. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE
BITS DESCRIPTION
VALUE MEANING
7:6
Response
00
01
10
The PMBus device continues operation without interruption.
For all values of bits [7:6], the LTC3886:
• Sets the corresponding fault bit in the status commands, and
• Notifies the host by asserting ALERT pin, unless masked.
Not supported. Writing this value will generate a CML fault.
The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11
Not supported. Writing this value will generate a CML fault.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUN pin, the OPERATION
command, or the combined action of the RUN pin and
OPERATION command, to turn off and then to turn back on, or
• The device receives a RESTORE_USER_ALL command.
• The device receives a MFR_RESET command.
• The device supply power is cycled.
Retry Setting
5:3
2:0
000
111
The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUN pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
Delay Time
XXX
Not supported. Values ignored
FAULT SHARING
Fault Sharing Propagation
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
0xD2 Configuration that determines which faults
are propagated to the FAULT pins.
TYPE
PAGED FORMAT UNITS EEPROM VALUE
MFR_FAULT_
PROPAGATE_LTC3886
R/W Word
Y
Reg 0x6993
Y
MFR_FAULT_PROPAGATE_LTC3886
The MFR_FAULT_PROPAGATE_LTC3886 command enables the faults that can cause the FAULTn pin to assert low. The
command is formatted as shown in Table 12. Faults can only be propagated to the FAULTn pin if they are programmed
to respond to faults.
This command has two data bytes.
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Table 12: FAULTn Propagate Fault Configuration
The FAULT0 and FAULT1 pins are designed to provide electrical notification of selected events to the user. Some of these events are common to both output
channels. Others are specific to an output channel. They can also be used to share faults between channels.
BIT(S)
SYMBOL
OPERATION
B[15]
VOUT disabled while not decayed.
This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG_LTC3886 is a
zero. If the channel is turned off, by toggling the RUN pin or commanding the part OFF, and then
the RUN is reasserted or the part is commanded back on before the output has decayed, VOUT
will not restart until the 12.5% decay is honored. The FAULT pin is asserted during this condition
if bit 15 is asserted.
B[14]
b[13]
Mfr_FAULT_propagate_short_CMD_
cycle
0: No action
1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high
120ms after sequence off.
Mfr_FAULT_propagate_ton_max_fault
0: No action if a TON_MAX_FAULT fault is asserted
1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted
FAULT0 is associated with page 0 TON_MAX_FAULT faults
FAULT1 is associated with page 1 TON_MAX_FAULT faults
Must be 0
b[12]
b[11]
Reserved
Mfr_FAULT0_propagate_int_ot,
Mfr_FAULT1_propagate_int_ot
Reserved
0: No action if the MFR_OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted
Must be 0
b[10]
b[9]
Reserved
Must be 0
b[8]
Mfr_FAULT0_propagate_ut,
Mfr_FAULT1_propagate_ut
0: No action if the UT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 UT faults
FAULT1 is associated with page 1 UT faults
b[7]
Mfr_FAULT0_propagate_ot,
Mfr_FAULT1_propagate_ot
0: No action if the OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OT faults
FAULT1 is associated with page 1 OT faults
b[6]
b[5]
b[4]
Reserved
Reserved
Mfr_FAULT0_propagate_input_ov,
Mfr_FAULT1_propagate_input_ov
Reserved
0: No action if the VIN_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted
b[3]
b[2]
Mfr_FAULT0_propagate_iout_oc,
Mfr_FAULT1_propagate_iout_oc
0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OC faults
FAULT1 is associated with page 1 OC faults
b[1]
b[0]
Mfr_FAULT0_propagate_vout_uv,
Mfr_FAULT1_propagate_vout_uv
0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 UV faults
FAULT1 is associated with page 1 UV faults
Mfr_FAULT0_propagate_vout_ov,
Mfr_FAULT1_propagate_vout_ov
0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted
FAULT0 is associated with page 0 OV faults
FAULT1 is associated with page 1 OV faults
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Fault Sharing Response
DATA
PAGED FORMAT UNITS EEPROM VALUE
Reg 0xC0
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
0xD5 Action to be taken by the device when the
FAULT pin is asserted low.
TYPE
R/W Byte
MFR_FAULT_RESPONSE
Y
Y
MFR_FAULT_RESPONSE
The MFR_FAULT_RESPONSE command instructs the device on what action to take in response to the FAULTn pin
being pulled low by an external source.
Supported Values:
VALUE
0xC0
MEANING
FAULT_INHIBIT The LTC3886 will disable the respective PWM channel in response to the FAULT pin pulled low.
FAULT_IGNORE The LTC3886 continues operation without interruption.
0x00
The device also:
n
Sets the MFR Bit in the STATUS_WORD.
n
Sets Bit 0 in the STATUS_MFR_SPECIFIC Command to Indicate FAULTn Is Being Pulled Low
n
Notifies the Host by Asserting ALERT, Unless Masked
This command has one data byte.
SCRATCHPAD
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
USER_DATA_00
0xB0
OEM reserved. Typically used for part
serialization.
R/W Word
N
Reg
Y
NA
USER_DATA_01
USER_DATA_02
0xB1
0xB2
Manufacturer reserved for LTpowerPlay.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
NA
NA
OEM reserved. Typically used for part
serialization.
USER_DATA_03
USER_DATA_04
0xB3
0xB4
A EEPROM word available for the user.
A EEPROM word available for the user.
R/W Word
R/W Word
Y
N
Reg
Reg
Y
Y
0x0000
0x0000
USER_DATA_00 through USER_DATA_04
These commands are non-volatile memory locations for customer storage. The customer has the option to write any
value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some of
these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable
inventory control and incompatibility with these products.
These commands have 2 data bytes and are in register format.
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IDENTIFICATION
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
FORMAT UNITS EEPROM VALUE
PMBUS_REVISION
0x98
PMBus revision supported by this device.
R Byte
N
Reg
Reg
FS
0x22
0xB0
Current revision is 1.2.
CAPABILITY
0x19
Summary of PMBus optional communication
protocols supported by this device.
R Byte
N
MFR_ID
0x99
0x9A
0xE7
The manufacturer ID of the LTC3886 in ASCII.
Manufacturer part number in ASCII.
R String
R String
R Word
N
N
N
ASC
ASC
Reg
LTC
MFR_MODEL
MFR_SPECIAL_ID
LTC3886
0x460X
Manufacturer code representing the LTC3886.
PMBus_REVISION
The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTC3886
is PMBus Version 1.2 compliant in both Part I and Part II.
This read-only command has one data byte.
CAPABILITY
This command provides a way for a host system to determine some key capabilities of a PMBus device.
The LTC3886 supports packet error checking, 400kHz bus speeds, and ALERT pin.
This read-only command has one data byte.
MFR_ID
The MFR_ID command indicates the manufacturer ID of the LTC3886 using ASCII characters.
This read-only command is in block format.
MFR_MODEL
The MFR_MODEL command indicates the manufacturer’s part number of the LTC3886 using ASCII characters.
This read-only command is in block format.
MFR_SPECIAL_ID
The 16-bit word representing the part name and revision. 0x46 denotes the part is an LTC3886, X is adjustable by the
manufacturer.
This read-only command has two data bytes.
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FAULT WARNING AND STATUS
DEFAULT
VALUE
NA
See CMD
Details
COMMAND NAME
CLEAR_FAULTS
SMBALERT_MASK
CMD CODE DESCRIPTION
TYPE
PAGED
N
Y
FORMAT UNITS EEPROM
0x03
0x1B
Clear any fault bits that have been set. Send Byte
Mask activity.
Block R/W
Reg
Y
MFR_CLEAR_PEAKS
STATUS_BYTE
0xE3
0x78
Clears all peak values.
One byte summary of the unit’s fault
condition.
Two byte summary of the unit’s fault
condition.
Output voltage fault and warning
status.
Output current fault and warning
status.
Input supply fault and warning status.
External temperature fault and warning R/W Byte
status for READ_TEMERATURE_1.
Send Byte
R/W Byte
N
Y
NA
NA
Reg
Reg
Reg
Reg
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
0x79
0x7A
0x7B
R/W Word
R/W Byte
R/W Byte
R/W Byte
Y
Y
Y
NA
NA
NA
STATUS_INPUT
STATUS_ TEMPERATURE
0x7C
0x7D
N
Y
Reg
Reg
NA
NA
STATUS_CML
0x7E
0x80
Communication and memory fault and R/W Byte
warning status.
N
Y
Reg
Reg
NA
NA
STATUS_MFR_ SPECIFIC
Manufacturer specific fault and state
information.
R/W Byte
MFR_PADS
MFR_COMMON
0xE5
0xEF
Digital status of the I/O pads.
Manufacturer status bits that are
common across multiple LTC chips.
R Word
R Byte
N
N
Reg
Reg
NA
NA
MFR_INFO
0xB6
Manufacturing Specific Information
R Word
N
Reg
NA
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all
status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output
if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain
set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault
occurs within that time frame it may be cleared before the status register is set.
This write-only command has no data bytes.
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut
down for a fault condition are restarted when:
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin
and OPERATION command, to turn off and then to turn back on, or
• MFR_RESET command is issued.
• Bias power is removed and reapplied to the integrated circuit
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SMBALERT_MASK
The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they
are asserted.
Figure 47 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits in
themaskbytealignwithbitsinthespecifiedstatusregister. Forexample, iftheSTATUS_TEMPERATUREcommandcode
is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning
would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE
bits would continue to assert ALERT if set.
Figure 48 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state
of any supported status register, again without PEC.
SMBALERT_MASKcannotbeappliedtoSTATUS_BYTE,STATUS_WORD,MFR_COMMONorMFR_PADS.Factorydefault
maskingforapplicablestatusregistersisshownbelow. ProvidinganunsupportedcommandcodetoSMBALERT_MASK
will generate a CML for Invalid/Unsupported Data.
SMBALERT_MASK Default Setting: (Refer Also to Figure 2)
1
7
1
1
8
1
8
1
8
1
1
SLAVE
ADDRESS
SMBALERT_MASK
COMMAND CODE
STATUS_x
COMMAND CODE
S
W
A
A
A
MASK BYTE
A
P
3886 F47
Figure 47. Example of Setting SMBALERT_MASK
1
7
1
1
8
1
8
1
8
1
SLAVE
ADDRESS
SMBALERT_MASK
COMMAND CODE
BLOCK COUNT
(= 1)
STATUS_x
COMMAND CODE
S
W
A
A
A
A
…
1
7
1
1
8
1
8
1
1
SLAVE
ADDRESS
BLOCK COUNT
(= 1)
Sr
R
A
A
MASK BYTE
NA
P
3886 F48
Figure 48. Example of Reading SMBALERT_MASK
STATUS RESISTER
STATUS_VOUT
ALERT Mask Value MASKED BITS
0x00
0x00
0x00
0x00
0x00
0x11
None
None
None
None
None
STATUS_IOUT
STATUS_TEMPERATURE
STATUS_CML
STATUS_INPUT
STATUS_MFR_SPECIFIC
Bit 4 (internal PLL unlocked), bit 0 (FAULT pulled low by external device)
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET command will also clear the
MFR_*_PEAK data values.
This write-only command has no data bytes.
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STATUS_BYTE
The STATUS_BYTE command returns one byte of information with a summary of the most critical faults. This is the
lower byte of the status word.
STATUS_BYTE Message Contents:
BIT
7*
6
STATUS BIT NAME
MEANING
BUSY
OFF
A fault was declared because the LTC3886 was unable to respond.
This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not
being enabled.
5
4
VOUT_OV
IOUT_OC
VIN_UV
An output overvoltage fault has occurred.
An output overcurrent fault has occurred.
Not supported (LTC3886 returns 0).
3
2
TEMPERATURE
CML
A temperature fault or warning has occurred.
A communications, memory or logic fault has occurred.
1
0*
NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.
*ALERT can be asserted if either of these bits is set. They may be cleared by writing a 1 to their bit position in the STATUS_BYTE, in lieu of a CLEAR_
FAULTS command.
This command has one data byte.
STATUS_WORD
The STATUS_WORD command returns a two-byte summary of the channel's fault condition. The low byte of the
STATUS_WORD is the same as the STATUS_BYTE command.
STATUS_WORD High Byte Message Contents:
BIT
15
14
13
12
11
10
9
STATUS BIT NAME
MEANING
V
An output voltage fault or warning has occurred.
An output current fault or warning has occurred.
An input voltage fault or warning has occurred.
A fault or warning specific to the LTC3886 has occurred.
The POWER_GOOD state is false if this bit is set.
Not supported (LTC3886 returns 0).
OUT
OUT
I
INPUT
MFR_SPECIFIC
POWER_GOOD#
FANS
OTHER
Not supported (LTC3886 returns 0).
8
UNKNOWN
Not supported (LTC3886 returns 0).
If any of the bits in the upper byte are set, NONE_OF_THE_ABOVE is asserted.
This command has two data bytes.
STATUS_VOUT
The STATUS_VOUT command returns one byte of V
status information.
OUT
STATUS_VOUT Message Contents:
BIT
7
MEANING
V
OUT
V
OUT
V
OUT
V
OUT
overvoltage fault.
6
overvoltage warning.
undervoltage warning.
undervoltage fault.
5
4
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3
2
1
0
V
max warning.
OUT
TON max fault.
TOFF max fault.
Not supported (LTC3886 returns 0).
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
STATUS_IOUT
The STATUS_IOUT command returns one byte of I
status information.
OUT
STATUS_IOUT Message Contents:
BIT
7
MEANING
overcurrent fault.
I
OUT
6
Not supported (LTC3886 returns 0).
I overcurrent warning.
OUT
5
4:0
Not supported (LTC3886 returns 0).
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
Any supported fault bit in this command will initiate an ALERT event. This command has one data byte.
STATUS_INPUT
The STATUS_INPUT command returns one byte of V (VINSNS) status information.
IN
STATUS_INPUT Message Contents:
BIT
7
MEANING
overvoltage fault.
V
IN
6
Not supported (LTC3886 returns 0).
V undervoltage warning.
IN
5
4
Not supported (LTC3886 returns 0).
3
Unit off for insufficient V .
IN
2
Not supported (LTC3886 returns 0).
1
I overcurrent warning.
IN
0
Not supported (LTC3886 returns 0).
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
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Any supported fault bit in this command will initiate an ALERT event. Bit 3 of this command is not latched and will not
generate an ALERT even if it is set. This command has one data byte.
STATUS_TEMPERATURE
The STATUS_TEMPERATURE commands returns one byte with status information on temperature. This is a paged
command and is related to the respective READ_TEMPERATURE_1 value.
STATUS_TEMPERATURE Message Contents:
BIT
7
MEANING
External overtemperature fault.
External overtemperature warning.
Not supported (LTC3886 returns 0).
External undertemperature fault.
Not supported (LTC3886 returns 0).
6
5
4
3:0
.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
This command has one data byte.
STATUS_CML
The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.
STATUS_CML Message Contents:
BIT
7
MEANING
Invalid or unsupported command received.
Invalid or unsupported data received.
Packet error check failed.
6
5
4
Memory fault detected.
3
Processor fault detected.
2
Reserved (LTC3886 returns 0).
Other communication fault.
Other memory or logic fault.
1
0
If either bit 3 or bit 4 of this command is set, a serious and significant internal error has been detected. Continued
operation of the part is not recommended if these bits are continuously set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command.
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Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information.
The format for this byte is:
BIT MEANING
7
6
5
4
3
2
0
Internal Temperature Fault Limit Exceeded.
Internal Temperature Warn Limit Exceeded.
Factory Trim Area EEPROM CRC Fault.
PLL is Unlocked
Fault Log Present
V
DD33
UV or OV Fault
FAULT Pin Asserted Low by External Device
If any of these bits are set, the MFR bit in the STATUS_WORD will be set, and ALERT may be asserted.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command. However, the fault log present bit can only be cleared
by issuing the MFR_FAULT_LOG_CLEAR command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
MFR_PADS
This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit
assignments of this command are as follows:
BIT ASSIGNED DIGITAL PIN
15
14
V
V
OV Fault
UV Fault
DD33
DD33
13 Reserved
12 Reserved
11 ADC Values Invalid, Occurs During Start-Up. May Occur Briefly on Current Measurement Channels During Normal Operation
10 SYNC clocked by external device (when LTC3886 configured to drive SYNC pin)
9
8
7
6
5
4
3
2
1
0
Channel 1 Power Good
Channel 0 Power Good
LTC3886 Driving RUN1 Low
LTC3886 Driving RUN0 Low
RUN1 Pin State
RUN0 Pin State
LTC3886 Driving FAULT1 Low
LTC3886 Driving FAULT0 Low
FAULT1 Pin State
FAULT0 Pin State
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A 1 indicates the condition is true.
This read-only command has two data bytes.
MFR_COMMON
The MFR_COMMON command contains bits that are common to all LTC digital power and telemetry products.
BIT
7
MEANING
Chip Not Driving ALERT Low
LTC3886 Not Busy
Calculations Not Pending
LTC3886 Outputs Not in Transition
EEPROM Initialized
Reserved
6
5
4
3
2
1
SHARE_CLK Timeout
WP Pin Status
0
This read-only command has one data byte.
MFR_INFO
The MFR_INFO command contains the EEPROM status bit.
MFR_INFO Data Contents:
BIT
MEANING
15:5 Reserved
4
EEPROM ECC status
0b
Corrections made in the EEPROM user
space
1b
No corrections made in the EEPROM user
space
3:0
Reserved
EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or a EEPROM
bulk read operation. This read-only command has two data bytes.
TELEMETRY
CMD
DEFAULT
COMMAND NAME
READ_VIN
READ_IIN
READ_VOUT
READ_IOUT
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
0x88 Measured input supply voltage.
0x89 Measured input supply current.
0x8B Measured output voltage.
0x8C Measured output current.
0x8D External diode junction temperature. This
is the value used for all temperature related
processing, including IOUT_CAL_GAIN.
R Word
R Word
R Word
R Word
R Word
N
N
Y
Y
Y
L11
L11
L16
L11
L11
V
A
V
A
C
NA
NA
NA
NA
NA
READ_TEMPERATURE_1
READ_TEMPERATURE_2
READ_FREQUENCY
0x8E Internal junction temperature. Does not affect
any other commands.
0x95 Measured PWM switching frequency.
R Word
R Word
N
Y
L11
L11
C
NA
NA
kHz
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CMD
DEFAULT
COMMAND NAME
READ_POUT
READ_PIN
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
0x96 Calculated output power.
0x97 Calculated input power.
0xD7 Report the maximum measured value of
READ_IOUT since last MFR_CLEAR_PEAKS.
R Word
R Word
R Word
Y
N
Y
L11
L11
L11
W
W
A
NA
NA
NA
MFR_IOUT_PEAK
MFR_ADC_CONTROL
MFR_VOUT_PEAK
MFR_VIN_PEAK
0xD8 ADC telemetry parameter selected for repeated R/W Byte
fast ADC read back
N
Y
N
Y
Reg
L16
L11
L11
0x00
NA
0xDD Maximum measured value of READ_VOUT
since last MFR_CLEAR_PEAKS.
R Word
R Word
R Word
V
V
C
0xDE Maximum measured value of READ_VIN since
last MFR_CLEAR_PEAKS.
NA
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of external
Temperature (READ_TEMPERATURE_1) since
last MFR_CLEAR_PEAKS.
NA
MFR_READ_IIN_PEAK
0xE1 Maximum measured value of READ_IIN
command since last MFR_CLEAR_PEAKS.
R Word
N
L11
A
NA
MFR_READ_ICHIP
0xE4 Measured current used by the LTC3886.
R Word
R Word
N
N
L11
L11
A
C
NA
NA
MFR_TEMPERATURE_2_PEAK 0xF4 Peak internal die temperature since last
MFR_CLEAR_PEAKS.
READ_VIN
The READ_VIN command returns the measured V pin voltage, in volts added to READ_ICHIP • MFR_RVIN. This
IN
compensates for the IR voltage drop across the V filter element due to the supply current of the LTC3886.
IN
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_VOUT
The READ_VOUT command returns the measured output voltage in the same format as set by the VOUT_MODE
command.
This read-only command has two data bytes and is formatted in Linear_16u format.
READ_IIN
The READ_IIN command returns the input current, in Amperes, as measured across the input current sense resistor
(see also MFR_IIN_CAL_GAIN).
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_IOUT
The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:
a) the differential voltage measured across the I
b) the IOUT_CAL_GAIN value
pins
SENSE
c) the MFR_IOUT_CAL_GAIN_TC value, and
d) READ_TEMPERATURE_1 value
e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
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READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_2
The READ_TEMPERATURE_2 command returns the LTC3886’s die temperature, in degrees Celsius, of the internal
sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_FREQUENCY
The READ_FREQUENCY command is a reading of the PWM switching frequency in kHz.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_POUT
The READ_POUT command is a reading of the DC/DC converter output power in Watts. POUT is calculated based on
the most recent correlated output voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_PIN
The READ_PIN command is a reading of the DC/DC converter input power in Watts. PIN is calculated based on the
most recent input voltage and current reading.
This read-only command has 2 data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_PEAK
The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_ADC_CONTROL
The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command
runs the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of 90ms.
The user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms.
This command has a latency of up to 2 ADC conversions or approximately 16ms (external temperature conversions
may have a latency of up to 3 ADC conversion or approximately 24ms). It is recommended the part remain in standard
telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be
commanded to monitor the desired parameter for a limited period of time (less then 1 second) then set the command
back to standard round robin mode. If this command is set to any value except standard round robin telemetry (0) all
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warnings and faults associated with telemetry other than the selected parameter are effectively disabled and voltage
servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled.
COMMANDED VALUE
TELEMETRY COMMAND NAME
DESCRIPTION
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Reserved
Reserved
Reserved
READ_TEMPERATURE_1
Channel 1 external temperature
Reserved
READ_IOUT
READ_VOUT
Channel 1 measured output current
Channel 1 measured output voltage
Channel 0 external temperature
Reserved
READ_TEMPERATURE_1
READ_IOUT
READ_VOUT
Channel 0 measured output current
Channel 0 measured output voltage
Internal junction temperature
Measured input supply current
Measured supply current of the LTC3886
Measured input supply voltage
Standard ADC round robin telemetry
READ_TEMPERATURE_2
READ_IIN
MFR_READ_ICHIP
READ_VIN
If a reserved command value is entered, the telemetry will default to Internal IC Temperature and issue a CML fault.
CML faults will continue to be issued by the LTC3886 until a valid command value is entered. The accuracy of the
measured input supply voltage is only guaranteed if the MFR_ADC_CONTROL command is set to standard round robin
telemetry. This write-only command has 1 data byte and is formatted in register format.
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_16u format.
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_1_PEAK
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_1 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
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MFR_READ_IIN_PEAK
TheMFR_READ_IIN_PEAKcommandreportsthehighestcurrent, inAmperes, reportedbytheREAD_IINmeasurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_ICHIP
The MFR_READ_ICHIP command returns the measured input current, in Amperes, used by the LTC3886.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_2_PEAK
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_2 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
EEPROM MEMORY COMMANDS
Store/Restore
CMD
DEFAULT
VALUE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED
FORMAT
UNITS
EEPROM
STORE_USER_ALL
0x15
0x16
0xF0
Store user operating memory to
EEPROM.
Send Byte
N
NA
NA
NA
RESTORE_USER_ALL
Restore user operating memory from Send Byte
EEPROM.
N
N
MFR_COMPARE_USER_ALL
Compares current command contents Send Byte
with EEPROM.
STORE_USER_ALL
The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating
Memory to the matching locations in the non-volatile User EEPROM memory.
Executing this command if the die temperature exceeds 85°C or is below 0°C is not recommended and the data reten-
tion of 10 years cannot be guaranteed. If the die temperature exceeds 130°C, the STORE_USER_ALL command is
disabled. The command is re-enabled when the IC temperature drops below 125°C.
Communication with the LTC3886 and programming of the EEPROM can be initiated when VDD33 is available and VIN
is not applied. To enable the part in this state, using global address 0x5B write MFR_EE_UNLOCK to 0x2B followed by
0xC4. The LTC3886 will now communicate normally, and the project file can be updated. To write the updated project
file to the EEPROM issue a STORE_USER_ALL command. When VIN is applied, a MFR_RESET must be issued to allow
the PWM to be enabled and valid ADCs to be read.
This write-only command has no data bytes.
RESTORE_USER_ALL
The RESTORE_USER_ALL command instructs the PMBus device to copy the contents of the non-volatile User memory
to the matching locations in the Operating Memory. The values in the Operating Memory are overwritten by the value
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retrieved from the User commands. The LTC3886 ensures both channels are off, loads the operating memory from
the internal EEPROM, clears all faults, reads the resistor configuration pins, and then performs a soft-start of both
PWM channels if applicable.
STORE_USER_ALL, MFR_COMPARE_USER_ALL and RESTORE_USER_ALL commands are disabled if the die exceeds
130°C and are not re-enabled until the die temperature drops below 125°C.
This write-only command has no data bytes.
MFR_COMPARE_USER_ALL
The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with
what is stored in non-volatile memory. If the compare operation detects differences, a CML fault will be generated.
This write-only command has no data bytes.
Fault Logging
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
MFR_FAULT_LOG
0xEE
0xEA
Fault log data bytes.
R Block
N
N
CF
Y
NA
NA
MFR_FAULT_LOG_ STORE
Command a transfer of the fault log from RAM Send Byte
to EEPROM.
MFR_FAULT_LOG_CLEAR
0xEC
Initialize the EEPROM block reserved for fault
logging.
Send Byte
N
NA
Fault Log Operation
A conceptual diagram of the fault log is shown in Figure 49. The fault log provides black box capability for the LTC3886.
During normal operation the contents of the status registers, the output voltage/current/temperature readings, the input
voltage readings, as well as the peak values of these quantities, are stored in a continuously updated buffer in RAM.
You can think of the operation as being similar to a strip chart recorder. When a fault occurs, the contents are written
into EEPROM for non volatile storage. The EEPROM fault log is then locked. The part can be powered down with the
fault log available for reading at a later time.
RAM
EEPROM
8
ADC READINGS
CONTINUOUSLY
FILL BUFFER
TIME OF FAULT
TRANSFER TO
EEPROM AND
LOCK
.
.
.
.
.
.
AFTER FAULT
READ FROM
EEPROM AND
LOCK BUFFER
3886 F49
Figure 49. Fault Log Conceptual Diagram
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MFR_FAULT_LOG
The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occur-
rence since the last MFR_FAULT_LOG_CLEAR command was written. The contents of this command are stored in
non-volatile memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this
command are listed in Table 13. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the
command will return a data length of 0. If a fault log is present, the MFR_FAULT_LOG will return a block of data 147
bytes long. The area available for the fault log in EEPROM is smaller than the area in RAM. When reading the fault log
from RAM all six events of cyclical data remain. However, when the fault log is read from EEPROM (after a reset), the
last two events are lost. The read length of 147 bytes remains the same, but the fifth and sixth events are a repeat of
the fourth event. If a fault occurs within the first second of applying power, some of the earlier pages in the fault log
may not contain valid data.
NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.
This read-only command is in block format.
MFR_FAULT_LOG_STORE
The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to EEPROM just as if a fault event
occurred. This command will set bit 3 of the STATUS_MFR_SPECIFIC fault if bit 7 “Enable Fault Logging” is set in the
MFR_CONFIG_ALL_LTC3886 command.
If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature
drops below 125°C.
This write-only command has no data bytes.
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Table 13. Fault Logging
This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.
Data Format Definitions
BYTE = 8 bits interpreted per definition of this command
DATA
DATA
BITS
FORMAT BYTE NUM BLOCK READ COMMAND
Block Length
BYTE
147
The MFR_FAULT_LOG command is a fixed length of 147 bytes
The block length will be zero if a data log event has not been captured
HEADER INFORMATION
Fault Log Preface
[7:0]
[7:0]
ASC
Reg
0
1
Returns LTxx beginning at byte 0 if a partial or complete fault log exists.
Word xx is a factory identifier that may vary part to part.
[15:8]
[7:0]
2
3
Fault Source
[7:0]
Reg
Reg
4
Refer to Table 13a.
MFR_REAL_TIME
[7:0]
5
48 bit share-clock counter value when fault occurred (200µs resolution).
[15:8]
[23:16]
[31:24]
[39:32]
[47:40]
[15:8]
6
7
8
9
10
11
MFR_VOUT_PEAK (PAGE 0)
MFR_VOUT_PEAK (PAGE 1)
MFR_IOUT_PEAK (PAGE 0)
MFR_IOUT_PEAK (PAGE 1)
L16
L16
L11
L11
Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0]
12
13
[15:8]
Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0]
14
15
[15:8]
Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0]
16
17
[15:8]
Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0]
[15:8]
[7:0]
18
19
20
21
22
23
24
25
26
MFR_VIN_PEAK
L11
L11
L11
L11
Peak READ_VIN since last power-on or CLEAR_PEAKS command.
External temperature sensor 0 during last event.
READ_TEMPERATURE1 (PAGE 0)
READ_TEMPERATURE1 (PAGE 1)
READ_TEMPERATURE2
[15:8]
[7:0]
[15:8]
[7:0]
External temperature sensor 1 during last event.
[15:8]
[7:0]
LTC3886 die temperature sensor during last event.
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CYCLICAL DATA
EVENT n
Event “n” represents one complete cycle of ADC reads through the MUX
at time of fault. Example: If the fault occurs when the ADC is processing
step 15, it will continue to take readings through step 25 and then store
the header and all 6 event pages to EEPROM
(Data at Which Fault Occurred; Most Recent Data)
READ_VOUT (PAGE 0)
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
READ_IIN
[15:8]
[7:0]
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
[15:8]
[7:0]
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
EVENT n-1
BYTE
(data measured before fault was detected)
READ_VOUT (PAGE 0)
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
READ_IIN
[15:8]
[7:0]
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
WORD
WORD
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LTC3886
pMbuꢀ coMManD DeTails
STATUS_WORD (PAGE 1)
[15:8]
WORD
WORD
BYTE
63
64
65
66
[7:0]
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
*
*
*
EVENT n-5
(Oldest Recorded Data)
READ_VOUT (PAGE 0)
[15:8]
[7:0]
LIN 16
LIN 16
LIN 16
LIN 16
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
LIN 11
BYTE
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
READ_VOUT (PAGE 1)
READ_IOUT (PAGE 0)
READ_IOUT (PAGE 1)
READ_VIN
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
READ_IIN
[15:8]
[7:0]
STATUS_VOUT (PAGE 0)
STATUS_VOUT (PAGE 1)
STATUS_WORD (PAGE 0)
BYTE
[15:8]
[7:0]
WORD
WORD
WORD
WORD
BYTE
STATUS_WORD (PAGE 1)
[15:8]
[7:0]
STATUS_MFR_SPECIFIC (PAGE 0)
STATUS_MFR_SPECIFIC (PAGE 1)
BYTE
Table 13a: Explanation of Position_Fault Values
POSITION_FAULT VALUE
SOURCE OF FAULT LOG
MFR_FAULT_LOG_STORE
TON_MAX_FAULT Channel 0
VOUT_OV_FAULT Channel 0
VOUT_UV_FAULT Channel 0
IOUT_OC_FAULT Channel 0
TEMP_OT_FAULT Channel 0
TEMP_UT_FAULT Channel 0
VIN_OV_FAULT
0xFF
0x00
0x01
0x02
0x03
0x05
0x06
0x07
0x0A
0x10
0x11
MFR_TEMPERATURE_2_OT_FAULT
TON_MAX_FAULT Channel 1
VOUT_OV_FAULT Channel 1
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LTC3886
pMbuꢀ coMManD DeTails
0x12
0x13
0x15
0x16
0x17
0x1A
VOUT_UV_FAULT Channel 1
IOUT_OC_FAULT Channel 1
OT_FAULT Channel 1
UT_FAULT Channel 1
VIN_OV_FAULT
MFR_TEMPERATURE_2_OT_FAULT
MFR_FAULT_LOG_CLEAR
The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the
STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear.
This write-only command is send bytes.
Block Memory Write/Read
DATA
DEFAULT
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS EEPROM VALUE
MFR_EE_UNLOCK
0xBD
0xBE
0xBF
Unlock user EEPROM for access by MFR_EE_ERASE
R/W Byte
N
N
N
Reg
Reg
Reg
NA
NA
NA
and MFR_EE_DATA commands.
MFR_EE_ERASE
MFR_EE_DATA
Initialize user EEPROM for bulk programming by
MFR_EE_DATA.
R/W Byte
Data transferred to and from EEPROM using
sequential PMBus word reads or writes. Supports bulk
programming.
R/W
Word
All the EEPROM commands are disabled if the die temperature exceeds 130°C. EEPROM commands are re-enabled
when the die temperature drops below 125°C.
MFR_EE_xxxx
The MFR_EE_xxxx commands facilitate bulk programming of the LTC3886 internal EEPROM. Contact the factory for
details.
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LTC3886
Typical applicaTions
High Efficiency 150kHz/5V and 12V Step-Down Converter with DCR Sense
10µF
2Ω
5mΩ
V
IN
18V TO 48V
22µF
10µF
1µF
+
–
D1
D2
0.1µF
INTV
TG0
V
I
I
CC IN IN IN
M1
M3
M2
TG1
0.1µF
L0
L1
BOOST0
SW0
BOOST1
SW1
3.1µH
6.8µH
M4
BG0
BG1
5k
LTC3886
6.81k
1µF
2.5k
SYNC
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
1µF
PGOOD0
PGOOD1
SDA
V
DD25
V
SCL
DD33
20k
10k
10k
10k
24.9k
4.32k
ALERT
FAULT0
FAULT1
V
V
OUT0_CFG
17.8k
23.2k
23.2k
23.2k
OUT1_CFG
ASEL0
ASEL1
SHARE_CLK
RUN0
FREQ_CFG
RUN1
WP
PHAS_CFG
+
2.5k
6.81k
+
–
I
I
SENSE0
SENSE1
0.22µF
0.68µF
–
V
I
V
V
I
OUT0
5V
15A
V
12V
10A
SENSE0
SENSE1
OUT1
+
V
SENSE1
SENSE0
SENSE0
–
EXTV
TSNS1
CC
TSNS0
I
I
+
+
150µF
2×
I
TH0
TH1
150µF
2×
22µF
4×
22µF
4×
*
I
THR0
THR1
GND V
DD25
V
DD33
10nF
4700pF
220pF
4700pF
220pF
10nF
1µF
1µF
4.7Ω*
3886 TA02
L0: WURTH 7443630310 3.1µH
L1: WURTH 7443556680 6.8µH
M1, M2: RENESAS RJK0651DPB
M3, M4: RENESAS RJK0653DPB
*OPTIONAL SCHOTTKY DIODE AND RESISTOR. IF EXTV IS TIED
CC
TO AN OUTPUT OF THE CONTROLLER, A SCHOTTKY DIODE MUST
BE USED TO PROTECT THE EXTV PIN IF THE EXTERNAL OUTPUT
CC
LOAD CAN PULL EXTV BELOW –0.3V
CC
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LTC3886
Typical applicaTions
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LTC3886
Typical applicaTions
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LTC3886
package DescripTion
Please refer to http://www.linear.com/product/LTC3886#packaging for the most recent package drawings.
UKG Package
Variation: UKG52(46)
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1947 Rev Ø)
7.50 ±0.05
6.10 ±0.05
5.00 REF
0.70 ±0.05
4.90 ±0.05
6.50 REF
(2 SIDES)
7.10 ±0.05 8.50 ±0.05
3.90 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 REF
0.75 ±0.05
7.00 ±0.10
(2 SIDES)
R = 0.115
TYP
0.00 – 0.05
40
51
52
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
4.90 ±0.10
8.00 ±0.10
(2 SIDES)
6.50 REF
(2 SIDES)
3.90 ±0.10
1.15 REF
14
27
R = 0.10
TYP
26
15
TOP VIEW
SIDE VIEW
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UKG52(46)) QFN REV
Ø 0413
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
NOTE:
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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LTC3886
revision hisTory
REV
DATE
12/15 Changed target voltage
Corrected B60/B61 pin numbers
Modified R1 + R3||R2 formula
DESCRIPTION
PAGE NUMBER
A
12
14
B
C
4/16
6/16
44
Modified schematics
62, 113, 114, 115, 116
Added Fault Log Operation
109
Deleted V
and V
lines
5
SENSE0(RIN)
SENSE1(RIN)
Electrical Characteristics Table changes
Revised Input Current Sensing and PolyPhase Load Sharing sections
Replaced Figures 28, 29
6, 7
21
48
Revised Table 6
56
D
E
8/16
5/17
EXTV Pin Functions clarification
14, 49
CC
Schematic modifications – optional Schottky diode
Added ECC
115, 116, 117, 120
1, 16, 17
Reduced initialization time
Reduced conversion time
5
6, 7
7
Added I input current to Electrical Characteristics Table
IN
Changed V and V threshold limits
8
IH
IL
3886fe
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
119
LTC3886
Typical applicaTion
High Efficiency 150kHz 2-Phase12V Step-Down Converter with Sense Resistors
10µF
2Ω
5mΩ
V
IN
48V
22µF
10µF
1µF
D1
+ –
I
D2
0.1µF
INTV
TG0
V
I
CC IN IN IN
M1
M3
M2
TG1
0.1µF
L0
6.8µH
L1
6.8µH
BOOST0
SW0
BOOST1
SW1
2mΩ
2mΩ
M4
BG0
BG1
5k
LTC3886
SYNC
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
PGOOD0
PGOOD1
SDA
V
DD25
V
SCL
DD33
10k
10k
10k
10k
24.9k
4.32k
ALERT
FAULT0
FAULT1
V
V
OUT0_CFG
23.2k
23.2k
23.2k
23.2k
OUT1_CFG
ASEL0
ASEL1
SHARE_CLK
RUN0
FREQ_CFG
RUN1
WP
PHAS_CFG
+
30Ω
30Ω
30Ω
30Ω
+
–
I
I
SENSE0
SENSE1
1000pF
1000pF
–
I
V
V
I
SENSE0
SENSE1
+
V
SENSE0
SENSE0
SENSE1
EXTV
–
CC
TSNS1
V
12V
30A
OUT
4.7Ω*
TSNS0
I
I
I
TH0
THR0
TH1
+
*
22µF
4×
150µF
2×
I
THR1
+
10nF
10nF
22µF
4×
150µF
2×
V
DD33
GND V
DD25
6800pF
1µF
1µF
220pF
3886 TA05
L0, L1: COILCRAFT SER2915H-682KL 6.8µH *OPTIONAL SCHOTTKY DIODE AND RESISTOR. IF EXTV
CC
IS TIED TO AN OUTPUT OF THE CONTROLLER, A SCHOTTKY
DIODE MUST BE USED TO PROTECT THE EXTV PIN IF THE
M1, M2: RENESAS RJK0651DPB
M3, M4: RENESAS RJK0653DPB
CC
EXTERNAL OUTPUT LOAD CAN PULL EXTV BELOW –0.3V
CC
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTM®4676A
Dual 13A or Single 26A Step-Down DC/DC µModule
Regulator with Digital Power System Management
V
Up to 26.5V; 0.5V ≤ V
( 0.5%) ≤ 5.4V, 2% I
ADC Accuracy,
IN
OUT
OUT
2
Fault Logging, I C/PMBus Interface, 16mm × 16mm × 5mm, BGA Package
2
LTM4675
LTM4677
Dual 9A or Single 18A Step-Down DC/DC μModule
Regulator with Digital Power System Management
4.5V ≤ V ≤17V; 0.5V ≤ V
≤ 5.5V, 0.5% V
Accuracy I C/PMBus
IN
OUT
OUT
Interface, 11.9mm × 16mm × 3.51mm, BGA Package
2
Dual 18A or Single 36A μModule Regulator with Digital 4.5V ≤ V ≤16V; 0.5V ≤ V
Power System Management
( 0.5%) ≤ 1.8V, I C/PMBus Interface,
IN
OUT
16mm × 16mm × 5.01mm, BGA Package
LTC3870/LTC3870-1 60V Dual Output Multiphase Step-Down Slave
Controller for Current Mode Control Applications with
Digital Power System Management
V
Up to 60V, 0.5V ≤ V
≤ 14V, Very High Output Current Applications
IN
OUT
with Accurate Current Share Between Phases Supporting LTC3880/
LTC3880-1, LTC3883/ LTC3883-1, LTC3886, LTC3887/ LTC3887-1
2
LTC3884
Dual Output MultiPhase Step-Down Controller with
Sub MilliOhm DCR Sensing Current Mode Control and
Digital Power System Management
4.5V ≤ V ≤ 38V, 0.5V ≤ V
Programmable Analog Loop Compensation, Input Current Sense
( 0.5%) ≤ 5.5V, I C/PMBus Interface,
IN
OUT
2
LTC3887/LTC3887-1 Dual Output Multiphase Step-Down DC/DC Controller
with Digital Power System Management
V
Up to 24V, 0.5V ≤ V
≤ 5.5V, Analog Control Loop, I C/PMBus
IN
OUT0,1
Interface with EEPROM and 16-Bit ADC
2
LTC3882/LTC3882-1 Dual Output Multiphase Step-Down DC/DC Voltage Mode
Controller with Digital Power System Management
V
Up to 38V, 0.5V ≤ V ≤ 5.25V, 0.5% V
Accuracy I C/
OUT
IN
OUT1,2
PMBus Interface with EEPROM and 16-Bit ADC
2
LTC3883/LTC3883-1 Single Phase Step-Down DC/DC Controller with Digital
Power System Management
V
Up to 24V, 0.5V ≤ V
≤ 5.5V, Input Current Sense Amplifier, I C/
IN
OUT
PMBus Interface with EEPROM and 16-Bit ADC
LTC2977
8-Channel PMBus Power System Manager Featuring
Accurate Output Voltage Measurement
Fault Logging to Internal EEPROM Monitors Eight Output Voltages,
Input Voltage and Die Temperature
LTC3815
6A Monolithic Synchronous DC/DC Step-Down
Converter with Digital Power System Management
2.25V ≤ V ≤ 5.5V, 0.4V ≤ V
≤ 0.72V , Programmable V
Range
IN
OUT
IN
OUT
25% with 0.1% Resolution, Up to 3MHz Operation with 13-Bit ADC
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120
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