LTC3899EUHF#PBF_技术文档

LTC3899

60V Low I , Triple

Q

Output, Buck/Buck/Boost

Synchronous Controller

DESCRIPTION

FEATURES

DualBuckPlusSingleBoost SynchronousControllers The LTC^®3899 is a high performance triple output (buck/

n

Wide Bias Input Voltage Range: 4.5V to 60V

Outputs Remain in Regulation Through Cold Crank

Down to a 2.2V Input Supply Voltage

buck/boost) DC/DC switching regulator controller that

drives all N-channel synchronous power MOSFET stages.

The constant frequency current mode architecture allows

aphase-lockablefrequencyofupto850kHz. TheLTC3899

n

Buck and Boost Output Voltages Up to 60V

Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE) operates from a wide 4.5V to 60V input supply range.

No External Bootstrap Diodes Required

Low Operating I : 29μA (One Channel On)

When biased from the output of the boost converter or

another auxiliary supply, the LTC3899 can operate from

an input supply as low as 2.2V after start-up.

Q

100% Duty Cycle for Boost Synchronous MOSFET

Phase-Lockable Frequency (75kHz to 850kHz)

Programmable Fixed Frequency (50kHz to 900kHz)

Very Low Dropout Operation: 99% Duty Cycle (Bucks)

The gate drive for the LTC3899 can be programmed from

5V to 10V to allow the use of logic-level or standard-level

FETs and to maximize efficiency. Internal switches in the

top gate drivers eliminate the need for external bootstrap

diodes. The 29μA no-load quiescent current extends op-

eratingruntimeinbattery-poweredsystems.OPTI-LOOP^®

compensationallowsthetransientresponsetobeoptimized

over a wide range of output capacitance and ESR values.

Low Shutdown I : 3.6μA

Q

Fixed or Adjustable Boost Output Voltage Saves I

Q

Small 38-Lead 5mm × 7mm QFN and TSSOP Packages

APPLICATIONS

n

Automotive Always-On and Start-Stop Systems

L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, Linear Technology and the Linear logo are

registered trademarks of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620,

6144194, 6177787, 6580258.

n

Distributed DC Power Systems

n

Multioutput Buck-Boost Applications

TYPICAL APPLICATION

High Efficiency Wide Input Range Dual 5V/8.5V Converter

Efficiency vs Output Current

V

OUT3

95

REGULATED AT 10V

V

= 12V

= 5V

IN

OUT

33µF

WHEN V < 10V

IN

RUN1, 2, 3

V

BIAS

TG1

FOLLOWS V WHEN

IN

94

93

92

91

90

89

88

Burst Mode OPERATION

V

FB3

V

IN

> 10V

0.1µF

TG3

BOOST1

SW1

4.9µH

V

5V

5A

9mΩ

OUT1

0.1µF

BOOST3

SW3

1.2µH

3mΩ

V

BG1

IN

2.2V TO 60V

(START-UP

ABOVE 5V)

LTC3899

33µF

BG3

+

–

SENSE1

357k

–

+

SENSE3

GATE DRIVE (DRV

)

V

CC

FB1

5V

6V

8V

68.1k

220µF

DRV

CC

INTV

CC

4.7µF

0.1µF

10V

TG2

0.1µF

0.01

0.1

1

10

BOOST2

SW2

ITH1,2,3

6.5µH

V

8.5V

3A

15mΩ

OUT2

OUTPUT CURRENT(A)

3899 TA01b

BG2

DRVSET

VPRG3

+

–

SENSE2

649k

V

FB2

GND

68.1k

68µF

3899 TA01a

3899fa

1

For more information www.linear.com/LTC3899

LTC3899

ABSOLUTE MAXIMUM RATINGS ^{(Notes 1, 3)}

PLLIN/MODE, FREQ, DRVSET Voltages....... –0.3V to 6V

Bias Input Supply Voltage (V

).............. –0.3V to 65V

BIAS

EXTV Voltage ......................................... –0.3V to 14V

Topside Driver Voltages

CC

ITH1, ITH2, ITH3, V , V Voltages ......... –0.3V to 6V

BOOST1, BOOST2, BOOST3 .................. –0.3V to 76V

Switch Voltage (SW1, SW2, SW3) ................ –5V to 70V

FB1 FB2

V

Voltage............................................... –0.3V to 65V

FB3

VPRG3, Voltage ........................................... –0.3V to 6V

TRACK/SS1, TRACK/SS2, SS3 Voltages...... –0.3V to 6V

Operating Junction Temperature Range (Note 2)

LTC3899E, LTC3899I......................... –40°C to 125°C

LTC3899H.......................................... –40°C to 150°C

LTC3899MP....................................... –55°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

DRV , (BOOST1-SW1), (BOOST2-SW2),

CC

(BOOST3-SW3)...........................................–0.3V to 11V

BG1, BG2, BG3, TG1, TG2, TG3..........................(Note 8)

RUN1, RUN2, RUN3 Voltages..................... –0.3V to 65V

+

–

+

–

SENSE1 , SENSE2 , SENSE1

SENSE2 Voltages ..................................... –0.3V to 65V

–

SENSE3 , SENSE3 Voltages..................... –0.3V to 65V

PIN CONFIGURATION

TOP VIEW

1

2

VPRG3

TRACK/SS1

TG1

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

ITH1

V

FB1

+

3

SENSE1

38 37 36 35 34 33 32

–

4

SW1

FREQ

PLLIN/MODE

SS3

1

2

31 SW1

5

BOOST1

BG1

FREQ

PLLIN/MODE

SS3

30 BOOST1

6

BG1

3

29

28

7

SW3

+

SENSE3

SW3

4

+

8

TG3

SENSE3

–

SENSE3

5

27 TG3

–

9

BOOST3

BG3

SENSE3

V

BOOST3

6

26

FB3

39

GND

39

10

11

12

13

14

15

16

17

18

19

V

FB3

GND

ITH3

7

25 BG3

V

BIAS

ITH3

INTV

8

24

V

BIAS

CC

EXTV

CC

INTV

CC

RUN1

RUN2

9

23 EXTV

22 DRV

CC

DRV

CC

RUN1

10

CC

BG2

RUN2

RUN3

21

20

RUN3 11

BG2

BOOST2

–

BOOST2

SW2

SENSE2 12

–

13 14 15 16 17 18 19

SENSE2

+

TG2

SENSE2

TRACK/SS2

DRVSET

V

FB2

ITH2

UHF PACKAGE

38-LEAD (5mm × 7mm) PLASTIC QFN

FE PACKAGE

T

JMAX

= 150°C, θ = 34°C/W

JA

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

38-LEAD PLASTIC TSSOP

T

= 150°C, θ = 25°C/W

JA

JMAX

EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

3899fa

2

For more information www.linear.com/LTC3899

LTC3899

ORDER INFORMATION

LEAD FREE FINISH

LTC3899EFE#PBF

LTC3899IFE#PBF

TAPE AND REEL

PART MARKING*

LTC3899FE

3899

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

LTC3899EFE#TRPBF

LTC3899IFE#TRPBF

LTC3899HFE#TRPBF

LTC3899MPFE#TRPBF

LTC3899EUHF#TRPBF

LTC3899IUHF#TRPBF

LTC3899HUHF#TRPBF

38-Lead Plastic TSSOP

LTC3899HFE#PBF

LTC3899MPFE#PBF

LTC3899EUHF#PBF

LTC3899IUHF#PBF

LTC3899HUHF#PBF

LTC3899MPUHF#PBF

38-Lead Plastic TSSOP

38-Lead (5mm × 7mm) Plastic QFN

3899

LTC3899MPUHF#TRPBF 3899

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. (Note 2) V_BIAS= 12V, V_RUN1,2,3= 5V, V_EXTVCC= 0V, V_DRVSET

0V, VPRG3 = Float unless otherwise noted.

=

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Bias Input Supply Operating Voltage Range

Buck Regulated Feedback Voltage

4.5

60

V

BIAS

(Note 4) ITH1,2 Voltage = 1.2V

0°C to 85°C

FB1,2

0.792

0.788

0.800

0.808

0.812

V

l

V

Boost Regulated Feedback Voltage

(Note 4) ITH3 Voltage = 1.2V

VPRG3 = FLOAT

FB3

l

1.182

9.78

11.74

1.200

10.00

12.00

1.218

10.22

12.26

V

VPRG3 = 0V

VPRG3 = INTV

CC

I

Buck Feedback Current

Boost Feedback Current

(Note 4)

–2

50

nA

FB1,2

(Note 4)

FB3

VPRG3 = FLOAT

VPRG3 = 0V

0.01

4

5

0.05

6

7

µA

VPRG3 = INTV

CC

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

(Note 4) V

= 4.5V to 60V

0.002

0.01

0.02

0.1

%/V

%

REFLNREG

LOADREG

BIAS

l

(Note 4) Measured in Servo Loop,

∆ITH Voltage = 1.2V to 0.7V

(Note 4) Measured in Servo Loop,

∆ITH Voltage = 1.2V to 2V

–0.01

2

–0.1

%

g

Transconductance Amplifier g

(Note 4) ITH1,2,3 = 1.2V, Sink/Source 5µA

mmho

m1,2,3

m

3899fa

3

For more information www.linear.com/LTC3899

LTC3899

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. (Note 2) V_BIAS= 12V, V_RUN1,2,3= 5V, V_EXTVCC= 0V, V_DRVSET

0V, VPRG3 = Float unless otherwise noted.

=

SYMBOL

PARAMETER

CONDITIONS

(Note 5), V

MIN

TYP

MAX

UNITS

I

Input DC Supply Current

= 0V

DRVSET

Q

Pulse-Skipping or Forced Continuous Mode RUN1 = 5V and RUN2,3 = 0V or

1.6

0.8

mA

(One Channel On)

RUN2 = 5V and RUN1,3 = 0V or

RUN3 = 5V and RUN1,2 = 0V,

V

FB1,2

= 0.83V (No Load), V = 1.25V

FB3

Pulse-Skipping or Forced Continuous Mode RUN1,2,3 = 5V, V

= 0.83V (No Load),

3

mA

µA

FB1,2

(All Channels On)

V

= 1.25V

FB3

l

Sleep Mode (One Channel On, Buck)

RUN1 = 5V and RUN2,3 = 0V or

RUN2 = 5V and RUN1,3 = 0V

29

55

V

= 0.83V (No Load)

FB1,2

Sleep Mode (One Channel On, Boost)

RUN3 = 5V and RUN1,2 = 0V, V = 1.25V

29

34

50

55

µA

FB3

Sleep Mode (Buck and Boost Channel On)

RUN1 = 5V and RUN2 = 0V or

RUN2 = 5V and RUN1 = 0V, RUN3 = 5V,

V

= 0.83V (No Load), V = 1.25V

FB3

FB1,2

Sleep Mode (All Three Channels On)

RUN1,2,3 = 5V, V

FB3

= 0.83V (No Load),

39

60

10

µA

FB1,2

V

= 1.25V

Shutdown

RUN1,2,3 = 0V

3.6

UVLO

Undervoltage Lockout

DRV Ramping Up

CC

l

DRVSET = 0V or R

≤ 100kΩ

4.0

7.5

4.2

7.8

V

DRVSET

DRVSET = INTV

CC

DRV Ramping Down

CC

l

DRVSET = 0V or R

3.6

6.4

3.8

6.7

4.0

7.0

V

DRVSET

DRVSET = INTV

CC

V

Buck Feedback Overvoltage Protection

Measured at V

Relative to Regulated V

FB1,2

7

10

13

1

%

µA

OVL1,2

FB1,2

+

I

+

–

SENSE Pin Current

Bucks (Channels 1 and 2)

Boost (Channel 3)

SENSE1,2

+

SENSE Pin Current

170

SENSE3

–

SENSE Pins Current

Bucks (Channels 1 and 2)

SENSE1,2

V

< V

> V

– 0.5V

+ 0.5V

1

µA

OUT1,2

INTVCC

700

–

I

–

SENSE Pin Current

Boost (Channel 3) V

+, V – = 12V

SENSE SENSE

µA

SENSE3

DF

MAX(TG)

Maximum Duty Factor for TG

Bucks (Channels 1,2) in Dropout, FREQ = 0V

Boost (Channel 3) in Overvoltage

97.5

99

100

%

DF

MAX(BG)

Maximum Duty Factor for BG

Bucks (Channels 1,2) in Overvoltage

Boost (Channel 3)

100

96

%

I

Soft-Start Charge Current

V

= 0V

8

10

12

µA

V

TRACK/SS1,2

I

= 0V

SS

SS3

l

V

ON RUN Pin On Threshold

Hyst RUN Pin Hysteresis

, V , V Rising

RUN1 RUN2 RUN3

1.22

1.275

75

1.33

RUN1,2,3

mV

RUN1,2,3

Maximum Current Sense Threshold

V

= 0.7V, V – = 3.3V,

SENSE1,2

65

75

85

60

SENSE(MAX)

FB1,2

FB3

= 1.1V, V

+ = 12V

SENSE3

V

SENSE3 Pins Common Mode Range

(BOOST Converter Input Supply Voltage)

2.2

V

SENSE(CM)

Gate Driver

TG1,2,3

Pull-Up On-Resistance

V

= INTV

2.2

1.0

Ω

DRVSET

CC

Pull-Down On-Resistance

BG1,2,3

Pull-Up On-Resistance

Pull-Down On-Resistance

2.2

1.0

Ω

DRVSET

CC

3899fa

4

For more information www.linear.com/LTC3899

LTC3899

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. (Note 2) V_BIAS= 12V, V_RUN1,2,3= 5V, V_EXTVCC= 0V, V_DRVSET

0V, VPRG3 = Float unless otherwise noted.

=

SYMBOL

PARAMETER

CONDITIONS

= 0V, V

MIN

TYP

MAX

UNITS

BDSW1,2,3

BOOST to DRV Switch On-Resistance

V

= INTV

CC

3.7

Ω

CC

SW

DRVSET

TG Transition Time:

Rise Time

Fall Time

(Note 6) V

= INTV

DRVSET

= 3300pF

CC

TG1,2,3 t

C

25

15

ns

r

f

LOAD

BG Transition Time:

Rise Time

Fall Time

(Note 6) V

= INTV

DRVSET

= 3300pF

CC

BG1,2,3 t

C

25

15

ns

r

f

LOAD

TG1,2/BG1,2 Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

C

LOAD

C

LOAD

C

LOAD

C

LOAD

= 3300pF Each Driver, V

= INTV

55

50

85

80

ns

DRVSET

CC

t

1D

BG1,2/TG1,2 Bottom Gate Off to Top Gate On Delay

t

Top Switch-On Delay Time

1D

TG3/BG3 t

CH3 Top Gate Off to Bottom Gate On Delay

Bottom Switch-On Delay Time

1D

BG3/TG3 t

CH3 Bottom Gate Off to Top Gate On Delay

Synchronous Switch-On Delay Time

t

Buck Minimum On-Time

Boost Minimum On-Time

(Note 7) V

= INTV

80

ns

ON(MIN)1,2

ON(MIN)3

DRVSET

CC

120

DRVSET

DRV Linear Regulator

CC

V

DRV Voltage from Internal V

LDO

V

= 0V

BIAS

DRVCC(INT)

CC

BIAS

EXTVCC

7V < V

< 60V, DRVSET = 0V

< 60V, DRVSET = INTV

5.8

9.6

6.0

10.0

6.2

10.4

V

11V < V

BIAS

CC

V

DRV Load Regulation from V

LDO

I

= 0mA to 50mA, V = 0V

EXTVCC

0.9

2.0

%

LDOREG(INT)

CC

BIAS

CC

DRV Voltage from Internal EXTV LDO

7V < V < 13V, DRVSET = 0V

EXTVCC

11V < V

5.8

9.6

6.0

10.0

6.2

10.4

V

DRVCC(EXT)

CC

< 13V, DRVSET = INTV

EXTVCC

CC

V

DRV Load Regulation from Internal

I

= 0mA to 50mA, V = 8.5V,

EXTVCC

DRVSET

0.7

2.0

%

LDOREG(EXT)

CC

EXTV LDO

V

= 0V

CC

EXTV LDO Switchover Voltage

EXTV Ramping Positive

CC

EXTVCC

CC

DRVSET = 0V or R

≤ 100kΩ

4.5

7.4

4.7

7.7

4.9

8.0

V

DRVSET

DRVSET = INTV

CC

V

EXTV Hysteresis

250

5.0

7.0

9.0

mV

V

LDOHYS

CC

Programmable DRV

R

= 50kΩ, V

= 70kΩ, V

= 90kΩ, V

= 0V

DRVCC(50kΩ)

DRVCC(70kΩ)

DRVCC(90kΩ)

CC

DRVSET

EXTVCC

= 0V

6.4

7.6

V

Oscillator and Phase-Locked Loop

f

Programmable Frequency

Low Fixed Frequency

R

=25kΩ, PLLIN/MODE = DC Voltage

= 65kΩ, PLLIN/MODE = DC Voltage

= 105kΩ, PLLIN/MODE = DC Voltage

= 0V, PLLIN/MODE = DC Voltage

105

440

835

350

535

kHz

25kΩ

65kΩ

105kΩ

LOW

FREQ

375

505

V

320

485

75

380

585

850

High Fixed Frequency

= INTV , PLLIN/MODE = DC Voltage

CC

HIGH

SYNC

l

Synchronizable Frequency

PLLIN/MODE = External Clock

l

PLLIN V

PLLIN/MODE Input High Level

PLLIN/MODE Input Low Level

PLLIN/MODE = External Clock

2.5

V

IH

IL

0.5

BOOST3 Charge Pump

I

BOOST3 Charge Pump Available Output

Current

FREQ = 0V, PLLIN/MODE = INTV

BST3

CC

V

= 16.5V, V

= 12V

75

35

µA

BOOST3

SW3

= 19V, V

= 12V

3899fa

5

For more information www.linear.com/LTC3899

LTC3899

ELECTRICAL CHARACTERISTICS

Note 3: This IC includes overtemperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

Continuous operation above the specified absolute maximum operating

junction temperature may impair device reliability or permanently damage

the device.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Ratings for extended periods may affect device reliability and

lifetime.

Note 2: The LTC3899 is tested under pulsed load conditions such that

T ≈ T . The LTC3899E is guaranteed to meet performance specifications

J

A

Note 4: The LTC3899 is tested in a feedback loop that servos V

to a

from 0°C to 85°C. Specifications over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3899I is guaranteed

over the –40°C to 125°C operating junction temperature range, the

LTC3899H is guaranteed over the –40°C to 150°C operating junction

temperature range, and the LTC3899MP is tested and guaranteed over

the –55°C to 150°C operating junction temperature range. High junction

temperatures degrade operating lifetimes; operating lifetime is derated

for junction temperatures greater than 125°C. Note that the maximum

ambient temperature consistent with these specifications is determined by

specific operating conditions in conjunction with board layout, the rated

package thermal impedance and other environmental factors. The junction

ITH1,2,3

specified voltage and measures the resultant V . The specification at

FB1,2,3

85°C is not tested in production and is assured by design, characterization

and correlation to production testing at other temperatures (125°C for

the LTC3899E and LTC3899I, 150°C for the LTC3899H and LTC3899MP).

For the LTC3899I and LTC3899H, the specification at 0°C is not tested in

production and is assured by design, characterization and correlation to

production testing at –40°C. For the LTC3899MP, the specification at 0°C

is not tested in production and is assured by design, characterization and

correlation to production testing at –55°C.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels

temperature (T , in °C) is calculated from the ambient temperature

J

(T , in °C) and power dissipation (P , in Watts) according to the formula:

A

D

T = T + (P • θ )

JA

J

A

D

Note 7: The minimum on-time condition is specified for an inductor

where θ = 34°C/W for the QFN package and where θ = 25°C/W for the

peak-to-peak ripple current >40% of I

(See Minimum On-Time

JA

MAX

TSSOP package.

Considerations in the Applications Information section).

Note 8: Do not apply a voltage or current source to these pins. They must be

connected to capacitive loads only, otherwise permanent damage may occur.

3899fa

6

For more information www.linear.com/LTC3899

LTC3899

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency and Power Loss

vs Output Current (Buck)

Efficiency

vs Output Current (Buck)

Efficiency vs Input Voltage (Buck)

100

90

80

70

60

50

40

30

20

10

0

10000

1000

100

10

100

90

80

70

60

50

40

30

20

10

0

98

96

94

92

90

88

86

84

82

80

BURST EFFICIENCY

V

= 10V

= 20V

= 30V

IN

DRVSET = INTV

CC

DRVSET = 0V

FCM LOSS

PULSE-SKIPPING

LOSS

BURST LOSS

PULSE-SKIPPING

EFFICIENCY

FCM EFFICIENCY

1

FIGURE 12 CIRCUIT

= 5V

Burst Mode OPERATION

V

LOAD

= 5V

= 4A

OUT

V

= 10V

= 5V

V

OUT

IN

OUT

I

0.1

0.0001 0.001

0.01

0.1

1

10

0.0001 0.001

0.01

0.1

1

10

0

10

20

30

40

50

60

OUTPUT CURRENT (A)

INPUT VOLTAGE (V)

3899 G03

3899 G01

3899 G02

Load Step (Buck)

Burst Mode Operation

Load Step (Buck)

Pulse-Skipping Mode

Load Step (Buck)

Forced Continuous Mode

V

OUT

100mV/DIV

AC COUPLED

I

L

2A/DIV

L

I

L

2A/DIV

50µs/DIV

3899 G04

3899 G05

3899 G06

V

= 12V

OUT

FIGURE 12 CIRCUIT

V

= 12V

OUT

V

= 12V

OUT

IN

= 5V

FIGURE 12 CIRCUIT

Inductor Current at Light Load

(Buck)

Buck Regulated Feedback Voltage

vs Temperature

Soft Start-Up (Buck)

808

806

804

802

800

798

796

794

792

RUN1, 2

5V/DIV

FORCED

CONTINUOUS

MODE

V

OUT2

2V/DIV

Burst Mode

OPERATION

1A/DIV

V

OUT1

2V/DIV

PULSE-

SKIPPING

MODE

2µs/DIV

2ms/DIV

FIGURE 12 CIRCUIT

3899 G07

3899 G08

V

= 12V

IN

= 5V

OUT

LOAD

I

= 1mA

FIGURE 12 CIRCUIT

-75 -50 -25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3899 G09

3899fa

7

For more information www.linear.com/LTC3899

LTC3899

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency and Power Loss

vs Output Current (Boost)

Efficiency

Shutdown (RUN) Threshold

vs Temperature

vs Input Voltage (Boost)

100

90

80

70

60

50

40

30

20

10

0

10000

1000

100

10

100

98

96

94

92

90

88

86

84

82

80

1.4

1.35

1.3

DRVSET = INTV

DRVSET = 0V

CC

BURST EFFICIENCY

FCM LOSS

PULSE-SKIPPING

EFFICIENCY

RISING

1.25

1.2

PULSE-SKIPPING

LOSS

FALLING

BURST

LOSS

1.15

1.1

V

= 5V

1

IN

OUT

FIGURE 12 CIRCUIT

= 10V

V

I

= 10V

= 2A

1.05

OUT

LOAD

FCM EFFICIENCY

0.1

OUTPUT CURRENT (A)

0.1

1

0.0001 0.001

0.01

1

10

2

4

6

8

10

12

-75 -50 -25

0

25 50 75 100 125 150

INPUT VOLTAGE (V)

TEMPERATURE (°C)

3899 G11

3899 G10

3899 G12

Load Step (Boost)

Forced Continuous Mode

Load Step (Boost)

Pulse-Skipping Mode

Load Step (Boost)

Burst Mode Operation

V

OUT

V

OUT

500mV/DIV

AC COUPLED

IL

5A/DIV

IL

5A/DIV

IL

5A/DIV

100µs/DIV

3899 G13

3899 G14

3899 G15

V

= 5V

V

= 5V

V

= 5V

IN

OUT

IN

OUT

IN

OUT

= 10V

FIGURE 12 CIRCUIT

Inductor Current at Light Load

(Boost)

Boost Regulated Feedback

Voltage vs Temperature

Soft Start-Up (Boost)

1.212

1.209

1.206

1.203

1.2

RUN3

FORCED

CONTINUOUS

MODE

5V/DIV

Burst Mode

OPERATION

5A/DIV

V

OUT3

2V/DIV

PULSE-

SKIPPING

MODE

1.197

1.194

1.191

1.188

GND

2µs/DIV

2ms/DIV

3899 G16

3899 G17

V

= 7V

IN

FIGURE 12 CIRCUIT

= 10V

OUT

LOAD

I

= 1mA

FIGURE 12 CIRCUIT

-75 -50 -25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3899 G18

3899fa

8

For more information www.linear.com/LTC3899

LTC3899

TYPICAL PERFORMANCE CHARACTERISTICS

DRV_CCand EXTV_CC

EXTV_CCSwitchover and DRV_CC

Voltages vs Temperature

DRV_CCLine Regulation

vs Load Current

11

10

9

6.4

11

10

9

DRV

6.2

6

CC

DRVSET = INTV

EXTV = 0V

CC

5.8

5.6

EXTV = 8.5V

CC

DRVSET = INTV

CC

EXTV RISING

5.4

5.2

8

CC

8

EXTV FALLING

CC

7

5

4.8

EXTV = 5V

CC

DRV

CC

7

6

4.6

4.4

DRVSET = GND

6

EXTV RISING

CC

5

V

BIAS

= 12V

4.2

4

DRVSET = GND

25 50

LOAD CURRENT (mA)

EXTV FALLING

CC

5

4

0

5

10 15 20 25 30 35 40 45 50 55 60 65

INPUT VOLTAGE (V)

0

75

100

125

150

-75 -50 -25

0

25 50 75 100 125 150

TEMPERATURE (°C)

3899 G19

3899 G20

3899 G21

SENSE Pins Total Input Current

vs V_SENSEVoltage

Buck SENSE^–Pin Input Bias

Current vs Temperature

Boost SENSE Pin Total Input

Current vs Temperature

800

700

600

500

400

300

200

100

0

900

800

700

600

500

400

300

200

100

0

200

180

160

140

120

100

80

V

= 12V

IN

V

> INTV + 0.5V

CC

OUT

SENSE1, 2 PINS (BUCK)

+

SENSE3 PIN

SENSE3 PINS (BOOST)

60

40

20

–

V

OUT

< INTV – 0.5V

CC

SENSE3 PIN

0

5

10 15 20 25 30 35 40 45 50 55 60 65

-75 -50 -25

0

25 50 75 100 125 150

-75 -50 -25

0

25 50 75 100 125 150

V

COMMON MODE VOLTAGE (V)

TEMPERATURE (°C)

SENSE

3899 G22

3899 G23

3899 G24

Maximum Current Sense

Threshold vs Duty Cycle

Maximum Current Sense

Threshold vs I_THVoltage

TRACK/SS Pull-Up Current

vs Temperature

100

90

80

70

60

50

40

30

20

10

0

100

80

12

11.5

11

5% DUTY CYCLE

BOOST

BUCK

PULSE-SKIPPING

60

Burst Mode

OPERATION

10.5

10

40

20

9.5

9

0

FORCED CONTINUOUS MODE

–20

–40

8.5

8

0

10 20 30 40 50 60 70 80 90 100

0

0.2 0.4 0.6 0.8

(V)

1

1.2 1.4

-75 -50 -25

0

25 50 75 100 125 150

DUTY CYCLE (%)

V

TEMPERATURE (°C)

ITH

3899 G25

3899 G26

3899 G27

3899fa

9

For more information www.linear.com/LTC3899

LTC3899

TYPICAL PERFORMANCE CHARACTERISTICS

Shutdown Current vs

Input Voltage

Quiescent Current vs Temperature

Shutdown Current vs Temperature

80

70

60

50

40

30

20

10

0

8

7

6

5

4

3

2

1

0

14

12

10

8

V

= 12V

V

= 12V

BIAS

ONE CHANNEL ON

Burst Mode OPERATION

DRVSET = 70kΩ

DRVSET = INTV

CC

6

DRVSET = GND

4

2

0

–75 –50 –25

0

25 50 75 100 125 150

-75 -50 -25

0

25 50 75 100 125 150

0

5

10 15 20 25 30 35 40 45 50 55 60 65

INPUT VOLTAGE (V)

TEMPERATURE (°C)

3899 G30

3899 G28

3899 G29

Oscillator Frequency vs

Temperature

Undervoltage Lockout Threshold

vs Temperature

Buck Foldback Current

100

90

80

70

60

50

40

30

20

10

0

600

550

500

450

400

350

300

8

7.5

7

RISING

FREQ = INTV

CC

DRVSET = INTV

CC

6.5

6

FALLING

5.5

5

4.5

4

DRVSET = GND

RISING

FREQ = GND

FALLING

3.5

3

0

100 200 300 400 500 600 700 800

-75 -50 -25

0

25 50 75 100 125 150

-75 -50 -25

0

25 50 75 100 125 150

FEEDBACK VOLTAGE (mV)

TEMPERATURE (°C)

3899 G31

3899 G32

3899 G33

BOOST3 Charge Pump Output

Voltage vs SW3 Voltage

BOOST3 Charge Pump Charging

Current vs Frequency

BOOST3 Charge Pump Charging

Current vs Switch Voltage

10

9

8

7

6

5

4

3

2

1

0

100

90

80

70

60

50

40

30

20

10

0

120

110

100

90

80

70

60

50

40

30

20

10

0

–55°C

25°C

V

– V

= 4.5V

SW3

BOOST3

25°C

150°C

V

– V

= 7.0V

SW3

150°C

BOOST3

–55°C

150°C

25°C

–55°C

FREQ = 350kHz

10MΩ LOAD BETWEEN BOOST3 AND SW3

V

= 16.5V

BOOST3

SW3

= 12V

FREQ = 350kHz

5

10 15 20 25 30 35 40 45 50 55 60 65

100 200 300 400 500 600 700 800

0

5

10 15 20 25 30 35 40 45 50 55 60 65

SW3 VOLTAGE (V)

OPERATING FREQUENCY (kHz)

SW3 VOLTAGE (V)

3899 G34

3899 G36

3899 G35

3899fa

10

For more information www.linear.com/LTC3899

LTC3899

PIN FUNCTIONS ^(QFN/TSSOP)

theDRVSETpinandGND.TheDRVSETpinalsodetermines

the higher or lower DRV UVLO and EXTV switchover

FREQ (Pin 1/ Pin 5): The frequency control pin for the

internal VCO. Connecting this pin to GND forces the VCO

to a fixed low frequency of 350kHz. Connecting this pin

CC

thresholds,aslistedontheElectricalCharacteristicstable.

ConnectingDRVSETtoGNDorprogrammingDRVSETwith

a resistor chooses the lower thresholds whereas tying

to INTV forces the VCO to a fixed high frequency of

CC

535kHz.Otherfrequenciesbetween50kHzand900kHzcan

be programmed using a resistor between FREQ and GND.

The resistor and an internal 20µA source current create a

voltage used by the internal oscillator to set the frequency.

DRVSET to INTV chooses the higher thresholds. When

CC

programming DRVSET with a resistor, do not choose a

resistor value less than 50k (unless shorting DRVSET to

GND) or higher than 100k.

PLLIN/MODE (Pin 2/Pin 6): External Synchronization

Input to Phase Detector and Forced Continuous Mode

Input. When an external clock is applied to this pin, the

phase-locked loop will force the rising TG1 signal to be

synchronized with the rising edge of the external clock,

andtheregulatorswilloperateinforcedcontinuousmode.

When not synchronizing to an external clock, this input,

which acts on all three controllers, determines how the

LTC3899 operates at light loads. Pulling this pin to ground

selects Burst Mode operation. An internal 100k resistor to

ground also invokes Burst Mode operation when the pin is

DRV (Pin 22/Pin 26): Output of the Internal or External

CC

Low Dropout (LDO) Regulator. The gate drivers are pow-

ered from this voltage source. The DRV voltage is set

CC

by the DRVSET pin. Must be decoupled to ground with a

minimum of 4.7µF ceramic or other low ESR capacitor.

Do not use the DRV pin for any other purpose.

CC

EXTV (Pin 23/Pin 27): External Power Input to an Inter-

CC

nal LDO Connected to DRV . This LDO supplies DRV

CC

power, bypassing the internal LDO powered from V

BIAS

whenever EXTV is higher than its switchover threshold

CC

floated.TyingthispintoINTV forcescontinuousinductor

CC

(4.7V or 7.7V depending on the DRVSET pin). See EXTV

CC

current operation. Tying this pin to a voltage greater than

ConnectionintheApplicationsInformationsection.Donot

float or exceed 14V on this pin. Do not connect EXTV to

1.1V and less than INTV – 1.3V selects pulse-skipping

CC

operation. This can be done by connecting a 100k resistor

a voltage greater than V

. Connect to GND if not used.

BIAS

from this pin to INTV .

CC

V

(Pin24/Pin28):MainSupplyPin.Abypasscapacitor

BIAS

INTV (Pin 8/Pin 12): Output of the Internal 5V Low

CC

should be tied between this pin and the GND pin.

Dropout Regulator. The low voltage analog and digital

circuits are powered from this voltage source. A low ESR

0.1µF ceramic bypass capacitor should be connected

BG1, BG2, BG3 (Pins 29, 21, 25/Pins 33, 25, 29): High

Current Gate Drives for Bottom N-Channel MOSFETs.

Voltage swing at these pins is from ground to DRV .

CC

between INTV and GND, as close as possible to the IC.

CC

INTV should not be used to power or bias any external

CC

BOOST1, BOOST2, BOOST3 (Pins 30, 20, 26/Pins 34,

24, 30): Bootstrapped Supplies to the Topside Floating

Drivers.CapacitorsareconnectedbetweentheBOOSTand

SW pins. Voltage swing at BOOST1 and BOOST2 pins is

circuitry other than to configure FREQ, PLLIN/MODE,

DRVSET AND VPRG3 pins.

RUN1, RUN2, RUN3 (Pins 9, 10, 11/ Pins 13, 14, 15):

RunControlInputsforEachController.Forcinganyofthese

pins below 1.2V shuts down that controller. Forcing all of

these pins below 0.7V shuts down the entire LTC3899,

reducing quiescent current to approximately 3.6µA.

from approximately DRV to (V

+ DRV ). Voltage

OUT3

CC

IN1,2

CC

swing at BOOST3 is from DRV to (V

+ DRV ).

CC

SW1, SW2, SW3 (Pins 31, 19, 28/Pins 35, 23, 32):

Switch Node Connections to Inductors.

DRVSET (Pin 16/Pin 20): Sets the regulated output volt-

TG1, TG2, TG3 (Pins 32, 18, 27/Pins 36, 22, 31): High

CurrentGateDrivesforTop N-ChannelMOSFETs.Theseare

the outputs of floating drivers with a voltage swing equal

age of the DRV LDO regulator. Connecting this pin to

CC

GND sets DRV to 6V whereas connecting it to INTV

CC

sets DRV to 10V. Voltages between 5V and 10V can be

CC

to DRV superimposed on the switch node voltage SW.

CC

programmed by placing a resistor (50k to 100k) between

3899fa

11

For more information www.linear.com/LTC3899

LTC3899

PIN FUNCTIONS ^(QFN/TSSOP)

TRACK/SS1, TRACK/SS2, SS3 (Pins 33, 17, 3/Pins 37,

V

,V (Pins36,14/Pins2,18):Thesepinsreceivethe

FB1 FB2

21, 7):ExternalTrackingandSoft-StartInput. Forthebuck

remotelysensedfeedbackvoltageforeachbuckcontroller

from an external resistive divider across the output.

channels, the LTC3899 regulates the V

voltage to the

FB1,2

smaller of 0.8V, or the voltage on the TRACK/SS1,2 pin.

For the boost channel, the LTC3899 regulates the V

V

(Pins6/Pins10):IfVPRG3isfloating,thispinreceives

FB3

the remotely sensed feedback voltage for the boost con-

voltage to the smaller of 1.2V, or the voltage on the SS3

pin. An internal 10µA pull-up current source is connected

to this pin. A capacitor to ground at this pin sets the ramp

time to final regulated output voltage. Alternatively, a re-

sistor divider on another voltage supply connected to the

TRACK/SS pins of the buck channels allow the LTC3899

buck outputs to track the other supply during start-up.

troller from an external resistive divider across the output.

If VPRG3 is tied to GND or INTV , this pin receives the

CC

remotely sensed output voltage of the boost controller.

+

SENSE1 , SENSE2 , SENSE3 (Pins 37, 13, 4/Pins 3,

17, 8): The (+) Input to the Differential Current Compara-

tors. The ITH pin voltage and controlled offsets between

–

+

the SENSE and SENSE pins in conjunction with R

SENSE

VPRG3 (Pin 34/Pin 38): Channel 3 Output Control Pin.

This pin sets the boost channel to adjustable output mode

using external feedback resistors or fixed 10V/12V output

mode.Floatingthispinallowstheoutputtobeprogrammed

set the current trip threshold. For the boost channel, the

+

SENSE3 pin supplies current to the current comparator.

–

SENSE1 , SENSE2 , SENSE3 (Pins 38, 12, 5/Pins 4,

16, 9): The (–) Input to the Differential Current Compara-

through the V pin using external resistors, regulating

FB3

–

tors. When SENSE1,2 for the buck channels is greater

V

to the 1.2V reference. Connecting this pin to GND or

FB3

–

than INTV , then SENSE1,2 pin supplies current to the

INTV programs the output to 10V or 12V (respectively),

CC

FB3

current comparator.

and V is used to sense the output voltage.

GND (Exposed Pad Pin 39/Exposed Pad Pin 39): Ground.

The exposed pad must be soldered to the PCB for rated

electrical and thermal performance.

ITH1, ITH2, ITH3 (Pins 35, 15, 7/Pins 1, 19, 11): Error

AmplifierOutputsandSwitchingRegulatorCompensation

Points. Eachassociatedchannel’scurrentcomparatortrip

point increases with this control voltage.

3899fa

12

For more information www.linear.com/LTC3899

LTC3899

FUNCTIONAL DIAGRAMS

BUCK CHANNELS 1 AND 2

DRV

CC

V

IN1,2

20µA

BOOST1,2

TG1,2

FREQ

CLK2

CLK1

VCO

C

B

TOP

BOT

DROPOUT

DET

C

IN

BOT

SW1,2

TOP ON

DRV

CC

C

S

R

Q

OUT

BG1,2

GND

PFD

V

OUT1,2

Q

SWITCHING

LOGIC

SHDN

L

R

SENSE

SYNC

DET

PLLIN/MODE

0.425V

+

–

SLEEP

100k

I

R

–

+

CMP

+

–

+

–

3mV

–

+

SENSE1,2

2.8V

–

0.65V

SENSE1,2

R

C

V

B

FB1,2

SLOPE COMP

–

+

0.80V

EA

R

TRACK/SS

A

+

–

OV

0.88V

C

3.5V

ITH1,2

150nA

R

SHDN

RST

C

C2

FOLDBACK

10µA

2(V

FB

)

TRACK/SS1,2

C

SS

SHDN

RUN1,2

3899 FD

2.00V

1.20V

20µA

DRVSET

EXTV

CC

DRV LDO/

CC

UVLO CONTROL

V

BIAS

–

+

–

+

–

+

EN

4.7V/

7.7V

DRV

CC

4R

INTV

CC

LDO

R

INTV

CC

3899fa

13

For more information www.linear.com/LTC3899

LTC3899

FUNCTIONAL DIAGRAMS

BOOST CHANNEL 3

DRV

CC

CHARGE

PUMP

BOOST3

V

OUT3

C

B

BOTTOM

TOP

BOT

TG3

C

OUT

CLK1

S

R

Q

SW3

Q

DRV

CC

C

IN

SHDN

SWITCHING

LOGIC

BG3

GND

V

IN3

PLLIN/MODE

0.425V

+

–

SLEEP

L

R

SENSE

I

R

–

+

CMP

+

–

+

–

3mV

–

SENSE3

2.8V

0.7V

+

SENSE3

+

–

SNSLO

SLOPE COMP

2V

VPRG3

R

B

V

FB3

EA

–

+

V

OUT3

1.2V

SS3

R

A

+

–

OV

C

1.32V

10µA

C

3.5V

ITH3

SS3

150nA

R

C

C2

C

SS

SHDN

SNSLO

RUN3

3899 FD02

OPERATION ^{(Refer to the Functional Diagrams)}

Main Control Loop

peak inductor current at which I

trips and resets the

CMP

latch is controlled by the voltage on the ITH pin, which is

the output of the error amplifier, EA. The error amplifier

The LTC3899 uses a constant frequency, current mode

step-downarchitecture.Thetwobuckcontrollers,channels

1 and 2, operate 180° out of phase with each other. The

boost controller, channel 3, operates in phase with chan-

nel 1. During normal operation, the external top MOSFET

for the buck channels (the external bottom MOSFET for

the boost controller) is turned on when the clock for that

channel sets the RS latch, and is turned off when the

compares the output voltage feedback signal at the V

FB

pin (which is generated with an external resistor divider

connected across the output voltage, V , to ground)

OUT

to the internal 0.800V reference voltage (1.2V reference

voltage for the boost). When the load current increases,

it causes a slight decrease in V relative to the reference,

FB

which causes the EA to increase the ITH voltage until the

average inductor current matches the new load current.

3899fa

main current comparator, I

, resets the RS latch. The

CMP

14

For more information www.linear.com/LTC3899

LTC3899

OPERATION ^{(Refer to the Functional Diagrams)}

After the top MOSFET for the bucks (the bottom MOSFET

for the boost) is turned off each cycle, the bottom MOSFET

is turned on (the top MOSFET for the boost) until either the

inductorcurrentstartstoreverse,asindicatedbythecurrent

Releasing a RUN pin allows a small 150nA internal current

to pull up the pin to enable that controller. Each RUN pin

maybeexternallypulledupordrivendirectlybylogic.Each

RUN pin can tolerate up to 65V (absolute maximum), so it

comparator I , or the beginning of the next clock cycle.

canbeconvenientlytiedtoV

inalways-onapplications

R

BIAS

where one or more controllers are enabled continuously

and never shut down.

DRV /EXTV /INTV Power

CC

Power for the top and bottom MOSFET drivers is derived

from the DRV pin. The DRV supply voltage can be

The start-up of each controller’s output voltage V

OUT

is controlled by the voltage on the TRACK/SS pin

(TRACK/SS1 for channel 1, TRACK/SS2 for channel 2,

SS3 for channel 3). When the voltage on the TRACK/SS

pin is less than the 0.8V internal reference for the bucks

and the 1.2V internal reference for the boost, the LTC3899

CC

programmed from 5V to 10V through control of the

DRVSET pin. When the EXTV pin is tied to a voltage

CC

below its switchover voltage (4.7V or 7.7V depending

on the DRVSET voltage), the V

LDO (low dropout

BIAS

linear regulator) supplies power from V

to DRV . If

regulates the V voltage to the TRACK/SS pin voltage

BIAS

CC

FB

EXTV is taken above its switchover voltage, the V

instead of the corresponding reference voltage. This al-

lows the TRACK/SS pin to be used to program a soft-start

by connecting an external capacitor from the TRACK/SS

pin to GND. An internal 10μA pull-up current charges this

capacitorcreatingavoltagerampontheTRACK/SSpin.As

the TRACK/SS voltage rises linearly from 0V to 0.8V/1.2V

CC

BIAS

LDO is turned off and an EXTV LDO is turned on. Once

CC

enabled, the EXTV LDO supplies power from EXTV

CC

to DRV . Using the EXTV pin allows the DRV power

CC

to be derived from a high efficiency external source such

as one of the LTC3899 buck regulator outputs.

(andbeyonduptoabout4V),theoutputvoltageV

rises

OUT

Each top MOSFET driver is biased from the floating boot-

smoothly from zero (V for the boost) to its final value.

IN

strapcapacitor,C ,whichnormallyrechargesduringeach

B

cycle through an internal switch whenever SW goes low.

AlternativelytheTRACK/SSpinsforbuckchannels1and2

can be used to cause the start-up of V

to track that of

OUT

For buck channels 1 and 2, if the input voltage decreases

to a voltage close to its output, the loop may enter dropout

and attempt to turn on the top MOSFET continuously. The

dropoutdetectordetectsthisandforcesthetopMOSFEToff

for about one-twelfth of the clock period every tenth cycle

another supply. Typically, this requires connecting to the

TRACK/SS pin an external resistor divider from the other

supply to ground (see Applications Information section).

Light Load Current Operation (Burst Mode Operation,

Pulse-Skipping or Forced Continuous Mode)

(PLLIN/MODE Pin)

to allow C to recharge, resulting in about 99% duty cycle.

B

TheINTV supplypowersmostoftheotherinternalcircuits

CC

in the LTC3899. The INTV LDO regulates to a fixed value

CC

The LTC3899 can be enabled to enter high efficiency Burst

Modeoperation,constantfrequencypulse-skippingmode,

orforcedcontinuousconductionmodeatlowloadcurrents.

To selectBurstModeoperation,tiethePLLIN/MODEpinto

GND.To selectforcedcontinuousoperation,tiethePLLIN/

of 5V and its power is derived from the DRV supply.

CC

Shutdown and Start-Up (RUN, TRACK/SS Pins)

The three channels of the LTC3899 can be independently

shut down using the RUN1, RUN2 and RUN3 pins. Pull-

ing a RUN pin below 1.20V shuts down the main control

loop for that channel. Pulling all three pins below 0.7V

disablesallcontrollersandmostinternalcircuits,including

MODE pin to INTV . To select pulse-skipping mode, tie

CC

thePLLIN/MODEpintoaDCvoltagegreaterthan1.1Vand

less than INTV – 1.3V. This can be done by connecting

CC

a 100kΩ resistor between PLLIN/MODE and INTV .

CC

the DRV and INTV LDOs. In this state, the LTC3899

CC

When a controller is enabled for Burst Mode operation,

the minimum peak current in the inductor is set to ap-

proximately 25% of the maximum sense voltage (30%

3899fa

draws only 3.6μA of quiescent current.

15

For more information www.linear.com/LTC3899

LTC3899

OPERATION ^{(Refer to the Functional Diagrams)}

for the boost) even though the voltage on the ITH pin

indicates a lower value. If the average inductor current is

higher than the load current, the error amplifier, EA, will

decrease the voltage on the ITH pin. When the ITH volt-

age drops below 0.425V, the internal sleep signal goes

high (enabling sleep mode) and both external MOSFETs

are turned off. The ITH pin is then disconnected from the

output of the EA and parked at 0.450V.

WhenthePLLIN/MODEpinisconnectedforpulse-skipping

mode,theLTC3899operatesinPWM pulse-skippingmode

at light loads. In this mode, constant frequency operation

is maintained down to approximately 1% of designed

maximum output current. At very light loads, the current

comparator, I

, may remain tripped for several cycles

CMP

and force the external top MOSFET (bottom for the boost)

to stay off for the same number of cycles (i.e., skipping

pulses).Theinductorcurrentisnotallowedtoreverse(dis-

continuous operation). This mode, like forced continuous

operation, exhibits low output ripple as well as low audio

noise and reduced RF interference as compared to Burst

Mode operation. It provides higher low current efficiency

than forced continuous mode, but not nearly as high as

Burst Mode operation.

In sleep mode, much of the internal circuitry is turned off,

reducing the quiescent current that the LTC3899 draws.

If one channel is in sleep mode and the other two are

shut down, the LTC3899 draws only 29μA of quiescent

current (with DRVSET = 0V). If two channels are in sleep

mode and the other shut down, it draws only 34μA of

quiescent current. If all three controllers are enabled in

sleep mode, the LTC3899 draws only 39μA of quiescent

current. In sleep mode, the load current is supplied by

the output capacitor. As the output voltage decreases,

the EA’s output begins to rise. When the output voltage

drops enough, the ITH pin is reconnected to the output

of the EA, the sleep signal goes low, and the controller

resumes normal operation by turning on the top external

MOSFET (the bottom external MOSFET for the boost) on

the next cycle of the internal oscillator.

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN/MODE Pins)

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

The switching frequency of the LTC3899’s controllers can

be selected using the FREQ pin.

When a controller is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to GND, tied to

current comparator (I ) turns off the bottom external

R

MOSFET (the top external MOSFET for the boost) just

before the inductor current reaches zero, preventing it

from reversing and going negative. Thus, the controller

operates discontinuously.

INTV orprogrammedthroughanexternalresistor.Tying

CC

FREQ to GND selects 350kHz while tying FREQ to INTV

CC

selects535kHz. PlacingaresistorbetweenFREQandGND

allows the frequency to be programmed between 50kHz

and 900kHz, as shown in Figure 10.

In forced continuous operation, the inductor current is

allowed to reverse at light loads or under large transient

conditions. The peak inductor current is determined by

the voltage on the ITH pin, just as in normal operation.

In this mode, the efficiency at light loads is lower than in

Burst Mode operation. However, continuous operation

has the advantage of lower output voltage ripple and

less interference to audio circuitry. In forced continuous

mode, the output ripple is independent of load current.

Clocking the LTC3899 from an external source enables

forced continuous mode (see the Frequency Selection

and Phase-Locked Loop section).

A phase-locked loop (PLL) is available on the LTC3899

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

LTC3899’s phase detector adjusts the voltage (through an

internal lowpass filter) of the VCO input to align the turn-

on of controller 1’s external top MOSFET (and controller

3’s external bottom MOSFET) to the rising edge of the

synchronizing signal. Thus, the turn-on of controller 2’s

external top MOSFET is 180° out of phase to the rising

edge of the external clock source.

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LTC3899

OPERATION ^{(Refer to the Functional Diagrams)}

The VCO input voltage is prebiased to the operating fre-

quency set by the FREQ pin before the external clock is

applied. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of TG1. The ability to

prebias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

inductor current. In Burst Mode operation, however, the

internal charge pump turns off if the entire chip is asleep

(if the two buck channels are also asleep or shut down).

With the charge pump off, there would be nothing to pre-

vent the boost capacitor from discharging, resulting in an

insufficient TG voltage needed to keep the top MOSFET

completely on. The charge pump turns back on when the

chip wakes up, and it remains on as long as one of the

buck channels is actively switching.

The typical capture range of the LTC3899’s phase-locked

loop is from approximately 55kHz to 1MHz, with a guaran-

tee to be between 75kHz and 850kHz. In other words, the

LTC3899’s PLL is guaranteed to lock to an external clock

source whose frequency is between 75kHz and 850kHz.

Boost Controller at Low SENSE Pin Common Voltage

The current comparator of the boost controller is powered

+

directly from the SENSE3 pin and can operate to voltages

as low as 2.2V. Since this is lower than the V

UVLO of

BIAS

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.1V (falling). It is recommended

that the external clock source swings from ground (0V)

to at least 2.5V.

the chip, V

can be connected to the output of the boost

BIAS

controller, as illustrated in the typical application circuit in

Figure 12. This allows the boost controller to handle input

voltage transients down to 2.2V while maintaining output

+

voltage regulation. If SENSE3 falls below 2.0V, then

Boost Controller Operation When V > V

IN

OUT

+

switching stops and SS3 is pulled low. If SENSE3 rises

When the input voltage to the boost channel rises above

its regulated V voltage, the controller can behave dif-

back above 2.2V, the SS3 pin will be released, initiating a

new soft-start sequence.

OUT

ferently depending on the mode, inductor current and

voltage. In forced continuous mode, the loop works

V

IN

Buck Controller Output Overvoltage Protection

to keep the top MOSFET on continuously once V rises

IN

The two buck channels have an overvoltage comparator

that guards against transient overshoots as well as other

more serious conditions that may overvoltage the output.

above V . An internal charge pump delivers current to

OUT

the boost capacitor from the BOOST3 pin to maintain a

sufficiently high TG voltage. Because the LTC3899 uses

internal switches and does not require external bootstrap

diodes, the charge pump only has to overcome small

leakage currents (board leakage, etc.).

When the V

pin rises by more than 10% above its

FB1,2

regulation point of 0.800V, the top MOSFET is turned off

and the bottom MOSFET is turned on until the overvoltage

condition is cleared.

In pulse-skipping mode, if V is between 0% and 10%

IN

Buck Foldback Current

above the regulated V

voltage, TG3 turns on if the

OUT

inductor current rises above approximately 3% of the

When the buck output voltage falls to less than 70% of

its nominal level, foldback current limiting is activated,

progressivelyloweringthepeakcurrentlimitinproportion

totheseverityoftheovercurrentorshort-circuitcondition.

Foldback current limiting is disabled during the soft-start

programmed I

current. If the part is programmed in

LIM

Burst Mode operation under this same V window, then

IN

TG3 turns on at the same threshold current as long as

the chip is awake (one of the buck channels is awake and

switching). If both buck channels are asleep or shut down

interval (as long as the V

voltage is keeping up with

FB1,2

in this V window, then TG3 will remain off regardless of

IN

the TRACK/SS1,2 voltage). There is no foldback current

the inductor current.

limiting for the boost channel.

IfV risesmorethan10%abovetheregulatedV voltage

IN

OUT

in any mode, the controller turns on TG3 regardless of the

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For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

–

TheTypicalApplicationonthefirstpageisabasicLTC3899

application circuit. LTC3899 can be configured to use

either DCR (inductor resistance) sensing or low value

resistor sensing. The choice between the two current

sensing schemes is largely a design trade-off between

cost, power consumption and accuracy. DCR sensing

is becoming popular because it saves expensive current

sensing resistors and is more power efficient, especially

in high current applications. However, current sensing

resistors provide the most accurate current limits for the

controller. Other external component selection is driven

by the load requirement, and begins with the selection of

theSENSE3 pinallowsthecurrentcomparatortobeused

in inductor DCR sensing.

Filter components mutual to the sense lines should be

placed close to the LTC3899, and the sense lines should

run close together to a Kelvin connection underneath the

current sense element (shown in Figure 1). Sensing cur-

rent elsewhere can effectively add parasitic inductance

and capacitance to the current sense element, degrading

the information at the sense terminals and making the

programmedcurrentlimitunpredictable.IfDCRsensingis

used (Figure 2b), R1 should be placed close to the switch-

ing node, to prevent noise from coupling into sensitive

small-signal nodes.

R

SENSE

(if R

is used) and inductor value. Next, the

SENSE

powerMOSFETsandSchottkydiodesareselected. Finally,

input and output capacitors are selected.

TO SENSE FILTER

NEXT TO THE CONTROLLER

+

–

SENSE and SENSE Pins

+

–

The SENSE and SENSE pins are the inputs to the cur-

rent comparators.

CURRENT FLOW

+

–

+

–

3899 F03

BuckControllers(SENSE1 /SENSE1 ,SENSE2 /SENSE2 ):

The common mode voltage range on these pins is 0V to

65V (absolute maximum), enabling the LTC3899 to regu-

late buck output voltages up to a nominal 60V (allowing

INDUCTOR OR R

SENSE

Figure 1. Sense Lines Placement with Inductor or Sense Resistor

+

margin for tolerances and transients). The SENSE pin

Low Value Resistor Current Sensing

is high impedance over the full common mode range,

drawing at most 1μA. This high impedance allows the

current comparators to be used in inductor DCR sensing.

A typical sensing circuit using a discrete resistor is shown

in Figure 2a. R

output current.

is chosen based on the required

SENSE

–

The impedance of the SENSE pin changes depending on

–

the common mode voltage. When SENSE is less than

The current comparators have a maximum threshold

of 75mV. The current comparator threshold

INTV – 0.5V, a small current of less than 1μA flows out

V

CC

SENSE(MAX)

–

of the pin. When SENSE is above INTV + 0.5V, a higher

voltage sets the peak of the inductor current, yielding

CC

current (≈700μA) flows into the pin. Between INTV

–

a maximum average output current, I

, equal to the

CC

MAX

0.5V and INTV + 0.5V, the current transitions from the

peak value less half the peak-to-peak ripple current, ∆I .

CC

L

smaller current to the higher current.

To calculate the sense resistor value, use the equation:

+

–

Boost Controller (SENSE3 /SENSE3 ): The common

mode input range for these pins is 2.2V to 60V, allowing

the boost converter to operate from inputs over this full

V

SENSE(MAX)

R

=

SENSE

∆I

L

I

+

MAX

2

+

range. The SENSE3 pin also provides power to the cur-

rent comparator and draws about 170μA during normal

operation (when not shut down or asleep in Burst Mode

operation). There is a small bias current of less than 1μA

When using the buck controllers in very low dropout con-

ditions, the maximum output current level will be reduced

duetotheinternalcompensationrequiredtomeetstability

criteria for buck regulators operating at greater than 50%

–

that flows into the SENSE3 pin. This high impedance on

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For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

can be less than 1mΩ for today’s low value, high current

inductors. In a high current application requiring such

an inductor, power loss through a sense resistor would

cost several points of efficiency compared to inductor

DCR sensing.

V

IN1,2

OUT3

(V

)

BOOST

TG

R

SENSE

V

OUT1,2

IN3

SW

(V

)

LTC3899

BG

If the external (R1||R2) • C1 time constant is chosen to be

exactly equal to the L/DCR time constant, the voltage drop

across the external capacitor is equal to the drop across

theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe

voltage across the sense terminals for applications where

the DCR is greater than the target sense resistor value.

To properly dimension the external filter components, the

DCR of the inductor must be known. It can be measured

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature; consult

the manufacturers’ data sheets for detailed information.

+

SENSE1,2

–

(SENSE3 )

CAP

PLACED NEAR SENSE PINS

–

SENSE1,2

+

(SENSE3 )

GND

3899 F04a

(2a) Using a Resistor to Sense Current

V

IN1,2

OUT3

(V

)

BOOST

INDUCTOR

DCR

TG

SW

BG

Using the inductor ripple current value from the Inductor

ValueCalculationsection,thetargetsenseresistorvalueis:

L

V

(V

OUT1,2

)

IN3

LTC3899

V

SENSE(MAX)

R

=

SENSE(EQUIV)

R1

R2

+

∆I

SENSE1,2

L

–

I

+

(SENSE3 )

MAX

2

C1*

–

SENSE1,2

+

(SENSE3 )

To ensure that the application will deliver full load cur-

rent over the full operating temperature range, determine

GND

(R1||R2) • C1 = L/DCR

= DCR(R2/(R1+R2))

3899 F04b

R , keeping in mind that the minimum value

*PLACE C1 NEAR SENSE PINS

R

SENSE(EQUIV)

for the maximum current sense threshold (V

for the LTC3899 is 65mV.

SENSE(EQ)

)

SENSE(MAX)

(2b) Using the Inductor DCR to Sense Current

Figure 2. Current Sensing Methods

Next, determine the DCR of the inductor. When provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefficient of copper resistance, which is approximately

dutyfactor. AcurveisprovidedintheTypicalPerformance

Characteristics section to estimate this reduction in peak

inductorcurrentdependingupontheoperatingdutyfactor.

0.4%/°C. A conservative value for T

is 100°C.

L(MAX)

Inductor DCR Sensing

To scale the maximum inductor DCR to the desired sense

resistor value (R ), use the divider ratio:

D

For applications requiring the highest possible efficiency

at high load currents, the LTC3899 is capable of sensing

the voltage drop across the inductor DCR, as shown in

Figure 2b. The DCR of the inductor represents the small

amount of DC winding resistance of the copper, which

R

SENSE(EQUIV)

R =

D

DCR

atT

L(MAX)

MAX

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LTC3899

APPLICATIONS INFORMATION

C1isusuallyselectedtobeintherangeof0.1μFto0.47μF.

ThisforcesR1||R2toaround2k, reducingerrorthatmight

MOSFET switching and gate charge losses. In addition to

this basic trade-off, the effect of inductor value on ripple

currentandlowcurrentoperationmustalsobeconsidered.

+

have been caused by the SENSE pin’s 1μA current.

The equivalent resistance R1||R2 is scaled to the tempera-

ture inductance and maximum DCR:

The inductor value has a direct effect on ripple current.

The inductor ripple current, ∆I , decreases with higher

L

inductance or higher frequency. For the buck controllers,

L

R1R2=



∆I increases with higher V :

L

IN

(DCR at 20°C)•C1





1

V



_OUT

IN

∆I_L=

V

1−

The sense resistor values are:

_OUT







f L

( )( )





R1R2

R_D

R1•R_D

1−R_D

R1=



; R2=

For the boost controller, ∆I increases with higher V

:

L

OUT









1

V

IN

V

OUT

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

∆I =

V

1−





L

IN

f L

( )( )





Accepting larger values of ∆I allows the use of low

L

V

− V

•V

inductances, but results in higher output voltage ripple

(

)

IN(MAX)

OUT

P

R1=

LOSS

and greater core losses. A reasonable starting point for

R1

setting ripple current is ∆I = 0.3(I

). The maximum

L

MAX

For the boost controller, the maximum power loss in R1

will occur in continuous mode at V = 1/2 • V

∆I occurs at the maximum input voltage for the bucks

L

:

OUT

and V = 1/2 • V

for the boost.

IN

OUT

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

25% of the current limit (30% for the boost) determined

V

− V •V

(

)

IN

OUT(MAX)

P

R1=

LOSS

R1

Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor,

due to the extra switching losses incurred through R1.

However,DCRsensingeliminatesasenseresistor,reduces

conduction losses and provides higher efficiency at heavy

loads.Peakefficiencyisaboutthesamewitheithermethod.

by R

. Lower inductor values (higher ∆I ) will cause

SENSE

L

this to occur at lower load currents, which can cause a dip

inefficiencyintheupperrangeoflowcurrentoperation. In

Burst Mode operation, lower inductance values will cause

the burst frequency to decrease.

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores. Actual core loss is independent of core size for a

fixedinductorvalue,butitisverydependentoninductance

value selected. As inductance increases, core losses go

down. Unfortunately, increased inductance requires more

turns of wire and therefore copper losses will increase.

Inductor Value Calculation

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

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For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

Ferrite designs have very low core loss and are preferred

for high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates hard, which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

V_OUT

Buck Main Switch Duty Cycle =

V

IN

V − V

IN

OUT

Buck Sync Switch Duty Cycle =

Boost Main Switch Duty Cycle=

Boost Sync Switch Duty Cycle=

V

IN

V_OUT− V

IN

V_OUT

Power MOSFET and Schottky Diode

(Optional) Selection

V

IN

V_OUT

Two external power MOSFETs must be selected for each

controller in the LTC3899: one N-channel MOSFET for the

topswitch(mainswitchforthebucks,synchronousforthe

boost), and one N-channel MOSFET for the bottom switch

(main switch for the boost, synchronous for the bucks).

The MOSFET power dissipations at maximum output

current are given by:

2

V

OUT

P

=

I

(

1+δ R

+

(

)

MAIN_BUCK

OUT(MAX)

DS(ON)

The peak-to-peak drive levels are set by the DRV volt-

CC

IN

age. This voltage can range from 5V to 10V depending on

configurationoftheDRVSETpin.Therefore,bothlogic-level

and standard-level threshold MOSFETs can be used in







I

OUT(MAX)

2



(V )

(R )(C

)•





IN

DR

MILLER

2





most applications depending on the programmed DRV

CC









1

− V

1

voltage. Pay close attention to the BV

the MOSFETs as well.

specification for

+

(f)

DSS



V

THMIN







THMIN

DRVCC



2

V − V

IN

OUT

The LTC3899’s unique ability to adjust the gate drive level

between 5V to 10V (OPTI-DRIVE) allows an application

circuit to be precisely optimized for efficiency. When

adjusting the gate drive level, the final arbiter is the total

input current for the regulator. If a change is made and

the input current decreases, then the efficiency has im-

proved. If there is no change in input current, then there

is no change in efficiency.

P

=

I

(

1+δ R

(

)

SYNC_BUCK

OUT(MAX)

DS(ON)

V

IN

V

− V

V

)

2

(

IN

2

OUT

P

=

I

(

•

)

MAIN_BOOST

OUT(MAX)

V

IN





 



3

I

V

OUT(MAX)

 



OUT

1+δ R

+

•

(

)



 



DS(ON)



V

2

IN



 











1

− V

1

R

C

•

+

(f)

Selection criteria for the power MOSFETs include the

)(

)



DR

MILLER

V







THMIN

DRVCC



on-resistance R

, Miller capacitance C

DS(ON)

, input

MILLER

2

voltage and maximum output current. Miller capacitance,

, can be approximated from the gate charge curve

V

IN

P

=

I

(

1+δ R

DS(ON)

(

)

SYNC_BOOST

OUT(MAX)

C

MILLER

V

OUT

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

MILLER

where δ is the temperature dependency of R

DR

and

DS(ON)

along the horizontal axis while the curve is approximately

R

(approximately 2Ω) is the effective driver resistance

flat divided by the specified change in V . This result is

DS

at the MOSFET’s Miller threshold voltage. V

is the

THMIN

then multiplied by the ratio of the application applied V

DS

typical MOSFET minimum threshold voltage.

to the gate charge curve specified V . When the IC is

DS

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For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

Both MOSFETs have I R losses while the main N-channel

2

ThevalueofC isafunctionofthesourceimpedance, and

IN

ingeneral,thehigherthesourceimpedance,thehigherthe

required input capacitance. The required amount of input

capacitance is also greatly affected by the duty cycle. High

output current applications that also experience high duty

cycles can place great demands on the input supply, both

in terms of DC current and ripple current.

equations for the buck and boost controllers include an

additional term for transition losses, which are highest at

high input voltages for the bucks and low input voltages

for the boost. For V < 20V (higher V for the boost)

IN

the high current efficiency generally improves with larger

MOSFETs, while for V > 20V (lower V for the boost)

IN

the transition losses rapidly increase to the point that the

Inaboostconverter,theoutputhasadiscontinuouscurrent,

use of a higher R device with lower C actu-

DS(ON)

MILLER

so C

must be capable of reducing the output voltage

OUT

ally provides higher efficiency. The synchronous MOSFET

losses for the buck controllers are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

ripple. The effects of ESR (equivalent series resistance)

andthebulkcapacitancemustbeconsideredwhenchoos-

ing the right capacitor for a given output ripple voltage.

The steady ripple due to charging and discharging the

bulk capacitance is given by:

The term (1 + δ) is generally given for a MOSFET in the

I_OUT(MAX)• V − V

(

)

IN(MIN)

OUT

form of a normalized R

vs Temperature curve, but

DS(ON)

Ripple=

where C

V

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

C_OUT•V_OUT•f

is the output filter capacitor.

OUT

Optional Schottky diodes placed across the synchronous

MOSFET conduct during the dead-time between the con-

duction of the two power MOSFETs. This prevents the

body diode of the synchronous MOSFET from turning

on, storing charge during the dead-time and requiring a

reverse recovery period that could cost as much as 3%

The steady ripple due to the voltage drop across the ESR

is given by:

∆V

= I

• ESR

L(MAX)

ESR

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic

and ceramic capacitors are all available in surface mount

packages. Ceramic capacitors have excellent low ESR

characteristics but can have a high voltage coefficient.

Capacitors are now available with low ESR and high ripple

current ratings such as OS-CON and POSCAP.

in efficiency at high V . A 1A to 3A Schottky is generally

IN

a good compromise for both regions of operation due to

the relatively small average current. Larger diodes result

in additional transition losses due to their larger junction

capacitance.

Boost C , C

Selection

IN OUT

The input ripple current in a boost converter is relatively

low (compared with the output ripple current), because

Buck C , C

Selection

IN OUT

TheselectionofC forthetwobuckcontrollersissimplified

IN

this current is continuous. The boost input capacitor C

IN

by the 2-phase architecture and its impact on the worst-

case RMS current drawn through the input network (bat-

tery/fuse/capacitor). It can be shown that the worst-case

capacitor RMS current occurs when only one controller

voltage rating should comfortably exceed the maximum

inputvoltage.Althoughceramiccapacitorscanberelatively

tolerant of overvoltage conditions, aluminum electrolytic

capacitorsarenot.Besuretocharacterizetheinputvoltage

for any possible overvoltage transients that could apply

excess stress to the input capacitors.

is operating. The controller with the highest (V )(I

product needs to be used in the formula shown in Equa-

)

OUT OUT

3899fa

22

For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

tion 1 to determine the maximum RMS capacitor current

requirement. Increasing the output current drawn from

the other controller will actually decrease the input RMS

ripple current from its maximum value. The opt-of-phase

technique typically reduces the input capacitor’s RMS

ripple current by a factor of 30% to 70% when compared

to a single phase power supply solution.

power supply/battery is included in the efficiency testing.

The drains of the top MOSFETs should be placed within

1cmofeachotherandshare acommonC (s). Separating

IN

the drains and C may produce undesirable voltage and

IN

current resonances at V .

IN

A small (0.1μF to 1μF) bypass capacitor between the chip

V

pin and ground, placed close to the LTC3899, is also

BIAS

Incontinuousmode,thesourcecurrentofthetopMOSFET

suggested. A 10Ω resistor placed between C (C1) and

IN

is a square wave of duty cycle (V )/(V ). To prevent

the V

pin provides further isolation.

OUT

IN

BIAS

large voltage transients, a low ESR capacitor sized for the

maximum RMS current of one channel must be used. The

maximum RMS capacitor current is given by:

The selection of C

is driven by the effective series

OUT

resistance (ESR). Typically, once the ESR requirement

is satisfied, the capacitance is adequate for filtering. The

 ^1/2

I_MAX

output ripple (∆V ) is approximated by:

OUT



C_INRequired I_RMS

≈

V

V − V

IN

OUT

(

_OUT)(

)





(1)





V

IN







1



∆V

≈ ∆I ESR+





L

OUT



8•f•C

This formula has a maximum at V = 2V , where I

OUT

IN

OUT

RMS





= I /2. This simple worst-case condition is commonly

OUT

where f is the operating frequency, C

is the output

OUT

usedfordesignbecauseevensignificantdeviationsdonot

offermuchrelief.Notethatcapacitormanufacturers’ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet

size or height requirements in the design. Due to the high

operating frequency of the LTC3899, ceramic capacitors

capacitance and ∆I is the ripple current in the inductor.

L

The output ripple is highest at maximum input voltage

since ∆I increases with input voltage.

L

Setting Buck Output Voltage

The LTC3899 output voltages for the buck controllers are

setbyanexternalfeedbackresistordividercarefullyplaced

across the output, as shown in Figure 3. The regulated

output voltage is determined by:

can also be used for C . Always consult the manufacturer

IN

if there is any question.

The benefit of the LTC3899 2-phase operation can be cal-

culatedbyusingEquation1forthehigherpowercontroller

and then calculating the loss that would have resulted if

both controller channels switched on at the same time.

The total RMS power lost is lower when both controllers

are operating due to the reduced overlap of current pulses

required through the input capacitor’s ESR. This is why

the input capacitor’s requirement calculated above for the

worst-case controller is adequate for the dual controller

design. Also, the input protection fuse resistance, battery

resistance, and PC board trace resistance losses are also

reduced due to the reduced peak currents in a 2-phase

system. The overall benefit of a multiphase design will

only be fully realized when the source impedance of the





R

R_A



_B

V_OUT=0.8V 1+













To improve the frequency response, a feedforward ca-

pacitor, C , may be used. Great care should be taken to

FF

FB

route the V line away from noise sources, such as the

inductor or the SW line.

V

OUT

R

C

FF

LTC3899

V

B

FB

A

3899 F05

Figure 3. Setting Buck Output Voltage

3899fa

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For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

Setting Boost Output Voltage (VPRG3 Pin)

LDOs. In this state, the LTC3899 draws only 3.6µA of

quiescent current.

Through control of the VPRG3 pin the boost controller

output voltage can be set by an external feedback resis-

tor divider or programmed to a fixed 10V or 12V output.

Releasing a RUN pin allows a small 150nA internal current

to pull up the pin to enable that controller. Because of

condensation or other small board leakage pulling the pin

down,itisrecommendedtheRUNpinsbeexternallypulled

up or driven directly by logic. Each RUN pin can tolerate

up to 65V (absolute maximum), so it can be conveniently

Floating VPRG3 allows the boost output voltage to be set

by an external feedback resistor divider placed across

the output, as shown in Figure 4a. The regulated output

voltage is determined by:

tied to V

in always-on applications where one or more

BIAS







controllersareenabledcontinuouslyandnevershutdown.

R



B

A

V

=1.2V 1+





OUT(BOOST)



The RUN pins can be implemented as a UVLO by con-

necting them to the output of an external resistor divider





Tying the VPRG3 to INTV or GND configures the boost

CC

network off V

, as shown in Figure 5.

BIAS

controller in fixed output voltage mode. Figure 4b shows

V

BIAS

how the V pin is used to sense the output voltage in

FB3

this mode. Tying VPRG3 to INTV programs the boost

R

1/3 LTC3899

RUN

B

A

CC

output to 12V, whereas tying VPRG3 to GND programs

the output to 10V.

R

3899 F13

V

OUT3

Figure 5. Using the RUN Pins as a UVLO

LTC3899

VPRG3

TherisingandfallingUVLOthresholdsarecalculatedusing

the RUN pin thresholds and pull-up current:

R

C

FF

B

(FLOAT)

V

FB3

A







R_B

3899 F06a

V

_UVLO(RISING)=1.275V 1+

–150nA •R_B





R

_A

(4a) Setting Boost Output Using External Resistors









R_B

R

LTC3899

V

_{UVLO(FALLING)}=1.20V 1+



V

OUT3

_A

INTV /GND

VPRG3

V

FB3

CC

12V/10V

C

OUT

3899 F06b

Tracking and Soft-Start (TRACK/SS1, TRACK/SS2,

SS3 Pins)

(4b) Setting Boost to Fixed 12V/10V Output

The start-up of each V

is controlled by the volt-

Figure 4. Setting CH3 Output Voltage

OUT

age on the TRACK/SS pin (TRACK/SS1 for channel 1,

TRACK/SS2 for channel 2, SS3 for channel 3). When the

voltage on the TRACK/SS pin is less than the internal

0.8V reference (1.2V reference for the boost channel),

RUN Pins

TheLTC3899isenabledusingtheRUN1, RUN2andRUN3

pins. The RUN pins have a rising threshold of 1.275V with

75mV of hysteresis. Pulling a RUN pin below 1.2V shuts

down the main control loop for that channel. Pulling all

three RUN pins below 0.7V disables the controllers and

the LTC3899 regulates the V pin voltage to the voltage

FB

on the TRACK/SS pin instead of the internal reference.

The TRACK/SS pin can be used to program an external

soft-start function or to allow V

ply during start-up.

to track another sup-

OUT

most internal circuits, including the DRV and INTV

CC

3899fa

24

For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

Soft-start is enabled by simply connecting a capacitor

from the TRACK/SS pin to ground, as shown in Figure 6.

An internal 10μA current source charges the capacitor,

providing a linear ramping voltage at the TRACK/SS pin.

The LTC3899 will regulate its feedback voltage (and hence

LTC3899

TRACK/SS

C

SS

GND

3899 F07

V

) according to the voltage on the TRACK/SS pin, al-

OUT

lowing V

Figure 6. Using the TRACK/SS Pin to Program Soft-Start

to rise smoothly from 0V (V for the boost)

OUT

IN

to its final regulated value. The total soft-start time will

be approximately:

V

X(MASTER)

OUT(SLAVE)

0.8V

t

=C •

SS

SS_BUCK

10µA

1.2V

=C •

SS_BOOST

SS

10µA

Alternatively, the TRACK/SS1 and TRACK/SS2 pins

for the two buck controllers can be used to track two

(or more) supplies during start-up, as shown qualita-

tively in Figures 7a and 7b. To do this, a resistor divider

3889 F08a

TIME

(7a) Coincident Tracking

should be connected from the master supply (V ) to the

X

V

X(MASTER)

TRACK/SS pin of the slave supply (V ), as shown in

OUT

Figure 8. During start-up V

will track V according to

OUT

X

the ratio set by the resistor divider:

OUT(SLAVE)

V_X

R_A

R

_TRACKA+R_TRACKB

R_A+R_B

=

•

V_OUTR_TRACKA

3899 F08b

TIME

For coincident tracking (V

= V during start-up),

X

OUT

(7b) Ratiometric Tracking

Figure 7. Two Different Modes of Output Voltage Tracking

R = R

A

TRACKA

TRACKB

R = R

B

V

OUT

DRV and INTV Regulators (OPTI-DRIVE)

CC

R

B

The LTC3899 features two separate internal P-channel

low dropout linear regulators (LDO) that supply power

V

FB1,2

R

A

at the DRV pin from either the V

supply pin or the

CC

BIAS

V

X

LTC3899

EXTV pin depending on the connections of the EXTV

CC

R

and DRVSET pins. A third P-channel LDO supplies power

at the INTV pin from the DRV pin. DRV powers the

TRACKB

TRACK/SS1,2

CC

gatedriverswhereasINTV powersmuchoftheLTC3899’s

TRACKA

3899 F09

CC

BIAS

internal circuitry. The V

LDO and the EXTV LDO

CC

regulate DRV between 5V to 10V, depending on how

the DRVSET pin is set. Each of these LDOs can supply a

CC

Figure 8. Using the TRACK/SS Pin for Tracking

3899fa

25

For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3899 to be

peak current of at least 50mA and must be bypassed to

ground with a minimum of 4.7μF ceramic capacitor. Good

bypassing is needed to supply the high transient currents

required by the MOSFET gate drivers and to prevent in-

exceeded. The DRV current, which is dominated by the

CC

gate charge current, may be supplied by either the V

teraction between the channels. The INTV supply must

BIAS

CC

LDO or the EXTV LDO. When the voltage on the EXTV

be bypassed with a 0.1μF ceramic capacitor.

CC

pin is less than its switchover threshold (4.7V or 7.7V as

determinedbytheDRVSETpindescribedabove),theV

The DRVSET pin programs the DRV supply voltage as

CC

BIAS

wellastheDRV UVLOandEXTV switchoverthreshold

CC

LDO is enabled. Power dissipation for the IC in this case

is highest and is equal to V • I . The gate charge

voltages. Table 1 summarizes the different DRVSET pin

BIAS DRVCC

configurations along with the voltage settings that go with

current is dependent on operating frequency as discussed

intheEfficiencyConsiderationssection. Thejunctiontem-

perature can be estimated by using the equations given

in Note 2 of the Electrical Characteristics. For example,

each configuration. Tying the DRVSET pin to INTV pro-

CC

gramsDRV to10VandchoosesthehigherUVLO/EXTV

CC

thresholds.TyingtheDRVSETpintoGNDprogramsDRV

to 6V and chooses the lower UVLO/EXTV thresholds.

CC

using the LTC3899 in the QFN package, the DRV current

CC

By placing a 50k to 100k resistor between DRVSET and

is limited to less than 40mA from a 40V supply when not

GND the DRV voltage can be programmed between 5V

CC

using the EXTV supply at a 70°C ambient temperature:

CC

to 10V, as shown in Figure 9. With a resistor on DRVSET,

T = 70°C + (40mA)(40V)(34°C/W) = 125°C

J

the lower UVLO/EXTV thresholds are chosen.

CC

To prevent the maximum junction temperature from be-

Table 1

ing exceeded, the V

supply current must be checked

BIAS

DRV UVLO

EXTV

CC

DRV

RISING / FALLING SWITCHOVER

while operating in forced continuous mode (PLLIN/MODE

= INTV ) at maximum V

CC

DRVSET PIN

VOLTAGE

THRESHOLDS

4.0V / 3.8V

7.5V / 6.7V

4.0V / 3.8V

THRESHOLD

.

BIAS

CC

0V

6V

4.7V

When the voltage applied to EXTV rises above its

CC

INTV

10V

7.7V

CC

switchover threshold, the V

LDO is turned off and the

BIAS

Resistor to GND

50k to 100k

5V to 10V

4.7V

EXTV LDO is enabled. The EXTV LDO remains on as

CC

long as the voltage applied to EXTV remains above the

CC

11

10

switchover threshold minus the comparator hysteresis.

The EXTV LDO attempts to regulate the DRV voltage

CC

tothevoltageasprogrammedbytheDRVSETpin,sowhile

9

EXTV is less than this voltage, the LDO is in dropout

CC

8

7

6

5

and the DRV voltage is approximately equal to EXTV .

CC

When EXTV is greater than the programmed voltage,

up to an absolute maximum of 14V, DRV is regulated

CC

to the programmed voltage.

Using the EXTV LDO allows the MOSFET driver and

CC

4

control power to be derived from one of the LTC3899’s

70

75 80 85 90 95 100

DRVSET PIN RESISTOR (kΩ)

50

65

55 60

switching regulator outputs (4.7V/7.7V ≤ V

≤ 14V)

OUT

LDO when

3899 F10

during normal operation and from the V

BIAS

Figure 9. Relationship Between DRV_CCVoltage

and Resistor Value at DRVSET Pin

theoutputisoutofregulation(e.g.,start-up,shortcircuit).

If more current is required through the EXTV LDO than

CC

is specified, an external Schottky diode can be added

3899fa

26

For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

between the EXTV and DRV pins. In this case, do not

betweenDRV andBOOST.CapacitorC intheFunctional

CC B

CC

apply more than 10V to the EXTV pin and make sure

DiagramischargedthroughthisinternalswitchfromDRV

CC

that EXTV ≤ V

.

when the SW pin is low. When the topside MOSFET is to

CC

BIAS

be turned on, the driver places the C voltage across the

B

Significant efficiency and thermal gains can be realized

by powering DRV from the output, since the V cur-

gate-source of the MOSFET. This enhances the top MOS-

CC

IN

FET switch and turns it on. The switch node voltage, SW,

rent resulting from the driver and control currents will be

scaled by a factor of (Duty Cycle)/(Switcher Efficiency).

rises to V and the BOOST pin follows. With the topside

IN

MOSFET on, the boost voltage is above the input supply:

For 5V to 14V regulator outputs, this means connecting

the EXTV pin directly to V . Tying the EXTV pin to

V

= V + V

(V

= V

+ V

for the

BOOST

IN

DRVCC BOOST

OUT

DRVCC

boost controller). The value of the boost capacitor, C ,

CC

OUT

CC

B

an 8.5V supply reduces the junction temperature in the

previous example from 125°C to:

needs to be 100 times that of the total input capacitance

of the topside MOSFET(s).

T = 70°C + (40mA)(8.5V)(34°C/W) = 82°C

J

Fault Conditions: Buck Current Limit and

Current Foldback

However,for3.3Vandotherlowvoltageoutputs,additional

circuitryisrequiredtoderiveDRV powerfromtheoutput.

CC

The LTC3899 includes current foldback for the buck chan-

nels to help limit load current when the output is shorted

to ground. If the buck output voltage falls below 70% of

its nominal output level, then the maximum sense volt-

age is progressively lowered from 100% to 40% of its

maximum selected value. Under short-circuit conditions

with very low duty cycles, the buck channel will begin

cycle skipping in order to limit the short-circuit current.

In this situation the bottom MOSFET will be dissipating

most of the power but less than in normal operation. The

short-circuit ripple current is determined by the minimum

The following list summarizes the four possible connec-

tions for EXTV :

CC

1. EXTV grounded.ThiswillcauseDRV tobepowered

CC

from the internal V

powerdissipationintheLTC3899athighinputvoltages.

regulator resulting in increased

BIAS

2. EXTV connected directly to the output of one of the

CC

buck regulators. This is the normal connection for a 5V

to 14V regulator and provides the highest efficiency.

3. EXTV_CCconnected to an external supply. If an external

supply is available in the 5V to 14V range, it may be

used to power EXTV_CCproviding it is compatible with

the MOSFET gate drive requirements. Ensure that

on-time, t

, of the LTC3899 (≈80ns), the input volt-

ON(MIN)

age and inductor value:













V

L

IN

∆I

= t

ON(MIN)

EXTV_CC< V_BIAS

.

L(SC)

4. EXTV connected to an output-derived boost network

CC

The resulting average short-circuit current is:

1

off one of the buck regulators. For 3.3V and other low

voltage regulators, efficiency gains can still be realized

I = 40%•I

− ∆I

byconnectingEXTV toanoutput-derivedvoltagethat

LIM(MAX)

SC

L(SC)

CC

2

has been boosted to greater than 4.7V/7.7V.

Fault Conditions: Buck Overvoltage Protection

(Crowbar)

Topside MOSFET Driver Supply (C )

B

Externalbootstrapcapacitors,C ,connectedtotheBOOST

B

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of one of the buck

regulators rises much higher than nominal levels. The

crowbar causes huge currents to flow, that blow the fuse

pinssupplythegatedrivevoltageforthetopsideMOSFET.

The LTC3899 features an internal switch between DRV

CC

and the BOOST pin for each controller. These internal

switches eliminate the need for external bootstrap diodes

3899fa

27

For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

to protect against a shorted top MOSFET if the short oc-

If the external clock frequency is greater than the inter-

curs while the controller is operating.

nal oscillator’s frequency, f , then current is sourced

OSC

continuously from the phase detector output, pulling up

A comparator monitors the buck output for overvoltage

conditions.Thecomparatordetectsfaultsgreaterthan10%

above the nominal output voltage. When this condition

is sensed, the top MOSFET is turned off and the bottom

MOSFET is turned on until the overvoltage condition is

cleared. ThebottomMOSFETremainsoncontinuouslyfor

the VCO input. When the external clock frequency is less

than f , current is sunk continuously, pulling down the

OSC

VCO input.

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal filter capacitor,

CLP, holds the voltage at the VCO input.

aslongastheovervoltageconditionpersists;ifV returns

OUT

to a safe level, normal operation automatically resumes.

AshortedtopMOSFETwillresultinahighcurrentcondition

which will open the system fuse. The switching regulator

will regulate properly with a leaky top MOSFET by altering

the duty cycle to accommodate the leakage.

Note that the LTC3899 can only be synchronized to an

external clock whose frequency is within range of the

LTC3899’s internal VCO, which is nominally 55kHz to

1MHz.Thisisguaranteedtobebetween75kHzand850kHz.

Typically, the external clock (on the PLLIN/MODE pin)

input high threshold is 1.6V, while the input low threshold

is 1.1V. The LTC3899 is guaranteed to synchronize to an

external clock that swings up to at least 2.5V and down

to 0.5V or less.

Fault Conditions: Overtemperature Protection

At higher temperatures, or in cases where the internal

power dissipation causes excessive self heating on chip

(such as DRV short to ground), the overtemperature

CC

shutdown circuitry will shut down the LTC3899. When the

junction temperature exceeds approximately 175°C, the

overtemperaturecircuitrydisablestheDRV LDO,causing

CC

theDRV supplytocollapseandeffectivelyshuttingdown

CC

the entire LTC3899 chip. Once the junction temperature

Rapid phase locking can be achieved by using the FREQ

pin to set a free-running frequency near the desired

synchronization frequency. The VCO’s input voltage is

prebiased at a frequency corresponding to the frequency

set by the FREQ pin. Once prebiased, the PLL only needs

to adjust the frequency slightly to achieve phase lock and

synchronization. Although it is not required that the free-

running frequency be near the external clock frequency,

doingsowillpreventtheoperatingfrequencyfrompassing

through a large range of frequencies as the PLL locks.

drops back to the approximately 155°C, the DRV LDO

CC

turns back on. Long-term overstress (T > 125°C) should

J

be avoided as it can degrade the performance or shorten

the life of the part.

Phase-Locked Loop and Frequency Synchronization

The LTC3899 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a lowpass filter,

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the top MOSFET of controller 1 to be locked

to the rising edge of an external clock signal applied to

the PLLIN/MODE pin. The turn-on of controller 2’s top

MOSFET is thus 180° out of phase with the external clock.

The phase detector is an edge sensitive digital type that

provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

Table 2 summarizes the different states in which the FREQ

pin can be used.

Table 2

FREQ PIN

PLLIN/MODE PIN

DC Voltage

FREQUENCY

350kHz

0V

INTV

DC Voltage

535kHz

CC

Resistor to GND

Any of the Above

DC Voltage

50kHz to 900kHz

External Clock

75kHz to 850kHz

Phase Locked to

External Clock

3899fa

28

For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

1000

900

800

700

600

500

400

300

200

100

Efficiency Considerations

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

0

where L1, L2, etc. are the individual losses as a percent-

age of input power.

15 25 35 45 55 65 75 85 95 105 115 125

FREQ PIN RESISTOR (kΩ)

3899 F11

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

Figure 10. Relationship Between Oscillator

Frequency and Resistor Value at the FREQ Pin

losses in LTC3899 circuits: 1) IC V

current, 2) DRV

BIAS

CC

2

regulator current, 3) I R losses, 4) Topside MOSFET

Minimum On-Time Considerations

transition losses.

Minimum on-time, t

, is the smallest time duration

ON(MIN)

1. The V

current is the DC supply current given in the

BIAS

that the LTC3899 is capable of turning on the top MOSFET

(bottomMOSFETfortheboostcontroller).Itisdetermined

by internal timing delays and the gate charge required to

turn on the top MOSFET. Low duty cycle applications may

approach this minimum on-time limit and care should be

taken to ensure that:

Electrical Characteristics table, which excludes MOS-

FET driver and control currents. V

results in a small (<0.1%) loss.

current typically

BIAS

2. DRV current is the sum of the MOSFET driver and

CC

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge, dQ, moves

V_OUT

t_{ON(MIN)_BUCK}

<

V (f)

IN

V_OUT− V

V_OUT(f)

from DRV to ground. The resulting dQ/dt is a cur-

IN

CC

t_{ON(MIN)_BOOST}

<

rent out of DRV that is typically much larger than the

CC

control circuit current. In continuous mode, I

GATECHG

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

= f(Q + Q ), where Q and Q are the gate charges of

T

B

T

B

the topside and bottom side MOSFETs.

SupplyingDRV fromanoutput-derivedsourcepower

CC

through EXTV will scale the V current required for

CC

IN

The minimum on-time for the LTC3899 is approximately

80ns for the bucks and 120ns for the boost. However, for

the buck channels as the peak sense voltage decreases

the minimum on-time gradually increases up to about

130ns. This is of particular concern in forced continuous

applications with low ripple current at light loads. If the

duty cycle drops below the minimum on-time limit in this

situation, a significant amount of cycle skipping can occur

with correspondingly larger current and voltage ripple.

thedriverandcontrolcircuitsbyafactorof(DutyCycle)/

(Efficiency). For example, in a 20V to 5V application,

10mAofDRV currentresultsinapproximately2.5mA

CC

of V current. This reduces the midcurrent loss from

IN

10% or more (if the driver was powered directly from

V ) to only a few percent.

IN

2

3. I R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resis-

tor and input and output capacitor ESR. In continuous

3899fa

29

For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

load current. When a load step occurs, V

shifts by an

mode the average output current flows through L and

OUT

amount equal to ∆I

, where ESR is the effective

R

, but is chopped between the topside MOSFET

LOAD(ESR)

SENSE

series resistance of C . ∆I

also begins to charge or

and the synchronous MOSFET. If the two MOSFETs

OUT

LOAD

discharge C

generating the feedback error signal that

have approximately the same R

, then the resis-

DS(ON)

OUT

forces the regulator to adapt to the current change and

tance of one MOSFET can simply be summed with the

2

return V

to its steady-state value. During this recov-

can be monitored for excessive overshoot

resistances of L, R

and ESR to obtain I R losses.

= 30mΩ, R = 50mΩ,

ESR

OUT

ery time V

SENSE

For example, if each R

OUT

DS(ON)

L

or ringing, which would indicate a stability problem.

OPTI-LOOPcompensationallowsthetransientresponseto

be optimized over a wide range of output capacitance and

ESR values. The availability of the ITH pin not only allows

optimization of control loop behavior, but it also provides

a DC-coupled and AC-filtered closed-loop response test

point. The DC step, rise time and settling at this test

point truly reflects the closed-loop response. Assuming

a predominantly second order system, phase margin and/

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also

be estimated by examining the rise time at the pin. The

ITH external components shown in Figure 12 circuit will

provide an adequate starting point for most applications.

R

SENSE

= 10mΩ and R

= 40mΩ (sum of both input

andoutputcapacitancelosses),thenthetotalresistance

is 130mΩ. This results in losses ranging from 3% to

13% as the output current increases from 1A to 5A for

a 5V output, or a 4% to 20% loss for a 3.3V output.

Efficiency varies as the inverse square of V

for the

OUT

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

4. Transition losses apply only to the top MOSFET(s) (bot-

tom MOSFET for the boost), and become significant

onlywhenoperatingathighinput(outputfortheboost)

voltages(typically20Vorgreater).Transitionlossescan

be estimated from:

The ITH series R -C filter sets the dominant pole-zero

C

loop compensation. The values can be modified slightly

to optimize transient response once the final PC layout is

done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selected because the various types and values determine

the loop gain and phase. An output current pulse of 20%

to 80% of full-load current having a rise time of 1μs to

10μs will produce output voltage and ITH pin waveforms

that will give a sense of the overall loop stability without

breaking the feedback loop.

2

Transition Loss = (1.7) • V • I

• C

• f

IN

O(MAX)

RSS

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5%

to 10% efficiency degradation in portable systems. It

is very important to include these system level losses

during the design phase. The internal battery and fuse

resistancelossescanbeminimizedbymakingsurethat

C has adequate charge storage and very low ESR at

IN

the switching frequency. A 25W supply will typically

require a minimum of 20μF to 40μF of capacitance

having a maximum of 20mΩ to 50mΩ of ESR. Other

losses including Schottky conduction losses during

dead-time and inductor core losses generally account

for less than 2% total additional loss.

Placing a power MOSFET directly across the output ca-

pacitor and driving the gate with an appropriate signal

generator is a practical way to produce a realistic load step

condition. The initial output voltage step resulting from

the step change in output current may not be within the

bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better

to look at the ITH pin signal which is in the feedback loop

andisthefilteredandcompensatedcontrolloopresponse.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

The gain of the loop will be increased by increasing R

C

and the bandwidth of the loop will be increased by de-

3899fa

30

For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

creasing C . If R is increased by the same factor that C

The equivalent R resistor value can be calculated by

SENSE

using the minimum value for the maximum current sense

threshold (65mV):

C

is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loopsystemandwilldemonstratetheactualoverall

supply performance.

65mV

5.73A

R

≤

≈ 0.01Ω

SENSE

Choosing 1% resistors: R = 25k and R = 78.7k yields

A

B

an output voltage of 3.32V.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

ThepowerdissipationonthetopsideMOSFETcanbeeasily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

with C , causing a rapid drop in V . No regulator can

OUT

results in: R

= 0.035Ω/0.022Ω, C

= 215pF.

DS(ON)

MILLER

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

At maximum input voltage with T(estimated) = 50°C:

3.3V

22V

²



P_MAIN

=

5A

1+ 0.005 50°C−25°C

 

(

)

(

)

(

)





C

to C

is greater than 1:50, the switch rise-time

LOAD

OUT

₂5A

should be controlled so that the load rise-time is limited

to approximately 25 • C . Thus a 10μF capacitor would

0.035Ω + 22V

) (

2.5Ω 215pF •

)(

(

)

(

)

2

LOAD









require a 250μs rise time, limiting the charging current

to about 200mA.

1





+

350kHz =308mW

(

)

6V−2.3V 2.3V

Buck Design Example

A short-circuit to ground will result in a folded back cur-

rent of:

As a design example for one channel, assume V = 12V

IN

(nominal), V = 22V (maximum), V

= 3.3V, I

=

IN

OUT

MAX





80ns 22V

34mV 1

−

(

)





5A, V

= 75mV and f = 350kHz. The inductance

SENSE(MAX)

I_SC=

=3.21A









0.01Ω 2

4.7µH

value is chosen first based on a 30% ripple current as-

sumption. The highest value of ripple current occurs at

the maximum input voltage. Tie the FREQ pin to GND,

generating 350kHz operation. The minimum inductance

for 30% ripple current is:





with a typical value of R

and δ = (0.005/°C)(25°C)

DS(ON)

= 0.125. The resulting power dissipated in the bottom

MOSFET is:

2

P

= (3.21A) (1.125) (0.022Ω) = 255mW

SYNC











V_OUT

f L

( )( )

V_OUT

∆I_L=

1−

which is less than under full-load conditions.

C is chosen for an RMS current rating of at least 3A at

V

^IN(NOM)

IN

temperature assuming only this channel is on. C

is

A 4.7μH inductor will produce 29% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 5.73A. Increasing the ripple

current will also help ensure that the minimum on-time

of 80ns is not violated. The minimum on-time occurs at

OUT

chosen with an ESR of 0.02Ω for low output ripple. The

output ripple in continuous mode will be highest at the

maximum input voltage. The output voltage ripple due to

ESR is approximately:

maximum V :

IN

V

= R (∆I ) = 0.02Ω (1.45A) = 29mV

ESR L P-P

O(RIPPLE)

V

3.3V

22V 350kHz

OUT

t

=

= 429ns

ON(MIN)

V

f

( )

(

)

IN(MAX)

3899fa

31

For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

PC Board Layout Checklist

of C

must return to the combined C

(–) termi-

DRVCC

OUT

nals. The path formed by the top N-channel MOSFET,

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

IC. Figure 11 illustrates the current waveforms present in

the various branches of the 2-phase synchronous buck

regulators operating in the continuous mode. Check the

following in your layout:

Schottky diode and the C capacitor should have short

IN

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible

to the (–) terminals of the input capacitor by placing

the capacitors next to each other and away from the

Schottky loop described above.

1. Are the top N-channel MOSFETs MTOP1 and MTOP2

located within 1cm of each other with a common drain

3. Does the LTC3899V pins’resistivedivider connect to

FB

OUT

the (+) terminal of C ? The resistive divider must be

connection at C ? Do not attempt to split the input

IN

connected between the (+) terminal of C

and signal

OUT

decoupling for the two channels as it can cause a large

ground. The feedback resistor connections should not

be along the high current input feeds from the input

capacitor(s).

resonant loop.

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

SW1

L1

R

SENSE1

V

OUT1

C

R

L1

OUT1

V

IN

R

IN

C

IN

SW2

L2

R

SENSE2

V

OUT2

C

R

L2

OUT2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

3899 F12

Figure 11. Branch Current Waveforms for Bucks

3899fa

32

For more information www.linear.com/LTC3899

LTC3899

APPLICATIONS INFORMATION

–

+

4. Are the SENSE and SENSE leads routed together with

minimumPCtracespacing?Thefiltercapacitorbetween

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required. Only after each

controllerischeckedforitsindividualperformanceshould

both should multiple controllers be turned on at the same

time. A particularly difficult region of operation is when

one buck channel is nearing its current comparator trip

point when the other buck channel is turning on its top

MOSFET. This occurs around 50% duty cycle on either

channel due to the phasing of the internal clocks and may

cause minor duty cycle jitter.

+

–

SENSE and SENSE should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the SENSE resistor.

5. IstheDRV anddecouplingcapacitorconnectedclose

CC

to the IC, between the DRV and the ground pin? This

CC

capacitor carries the MOSFET drivers’ current peaks.

6. Keep the switching nodes (SW1, SW2, SW3), top gate

(TG1, TG2, TG3), and boost nodes (BOOST1, BOOST2,

BOOST3) away from sensitive small-signal nodes,

especially from the opposites channel’s voltage and

current sensing feedback pins. All of these nodes have

verylargeandfastmovingsignalsandthereforeshould

be kept on the output side of the LTC3899 and occupy

minimum PC trace area.

Reduce V from its nominal level to verify operation of

IN

the regulator in dropout. Check the operation of the un-

dervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

7. Useamodifiedstargroundtechnique:alowimpedance,

large copper area central grounding point on the same

side of the PC board as the input and output capacitors

with tie-ins for the bottom of the DRV decoupling

CC

capacitor, the bottom of the voltage feedback resistive

divider and the GND pin of the IC.

PC Board Layout Debugging

Start with one controller at a time. It is helpful to use a

DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

totheinternaloscillatorandprobetheactualoutputvoltage

as well. Check for proper performance over the operating

voltage and current range expected in the application. The

frequencyofoperationshouldbemaintainedovertheinput

voltage range down to dropout and until the output load

drops below the low current operation threshold—typi-

cally 25% of the maximum designed current level in Burst

Mode operation.

for inductive coupling between C , Schottky and the top

IN

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

GND pin of the IC.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

The output voltage under this improper hookup will still

be maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawell-designed,lownoisePCBimplementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

3899fa

33

For more information www.linear.com/LTC3899

LTC3899

TYPICAL APPLICATIONS

V

OUT1

R

B1

A1

68.1k

LTC3899

357k

TG1

MTOP1

V

FB1

C

B1

0.1µF

C

100pF

R

ITH1A

1500pF

L1

4.9µH

R

SNS1

9mΩ

BOOST1

SW1

V

5V

5A

OUT1

ITH1

C

ITH1

C

15k

OUT1A

OUT1B

22µF

220µF

ITH1

MBOT1

BG1

C

SS1

0.1µF

+

SENSE1

TRACK/SS1

C1

1nF

–

SENSE1

V

OUT2

RUN1

RUN2

RUN3

R

B2

A2

649k

68.1k

V

FB2

R

V

ITH2

15k

BIAS

C

2200pF

ITH2

C

BIAS

0.1µF

ITH2

GND

C

68pF

ITH2A

C

DRVCC

4.7µF

DRV

EXTV

CC

C

SS2

0.1µF

TRACK/SS2

TG2

MTOP2

C

B2

0.1µF

L2

6.5µH

V

R

OUT3

FB3

SNS2

BOOST2

SW2

C

V

8.5V

3A

ITH3

15mΩ

OUT2

R

10nF

ITH3

C

3.6k

OUT2A

OUT2B

4.7µF

ITH3

SS3

68µF

MBOT2

BG2

C

820pF

ITH3A

+

SENSE2

C

0.1µF

C2

1nF

SS3

–

SENSE2

V

OUT3

10V*

C

OUT3B

OUT3A

33µF

2.2µF

TG3

MTOP3

FREQ

C

0.1µF

×6

B3

PLLIN/MODE

DRVSET

VPRG3

L3

1.2µH

R

SNS3

BOOST3

SW3

V

3mΩ

IN

2.2V TO 60V

C

IN2

IN1

(START-UP ABOVE 5V)

C

33µF

2.2µF

MBOT3

INTVCC

0.1µF

BG3

×2

×3

–

INTV

CC

SENSE3

*V

OUT3

IS 10V WHEN V < 10V,

IN

C3

1nF

FOLLOWS V WHEN V > 10V

IN IN

+

3899 TA02

SENSE3

Figure 12. High Efficiency Wide Input Range Dual 5V/8.5V Converter

Efficiency and Power Loss vs Load Current

MTOP1, MBOT1: BSZ123N08NS3

MTOP2, MBOT2: BSZ123N08NS3

MTOP3, MBOT3: BSC042NE7NS3

L1: WURTH 744314490

100

90

80

70

60

50

40

30

20

10

0

10k

V

= 12V

OUT

IN

= 5V

EFFICIENCY

1k

L2: WURTH 744314650

L3: WURTH 744325120

C

: SANYO 6TPB220ML

: SANYO 10TPC68M

IN1 OUT3A

OUT1A

OUT2A

, C

100

10

: SUNCON 63HVP33M

POWER LOSS

1

0.1

0.0001 0.001

0.01

0.1

1

10

LOAD CURRENT (A)

3899 TA02b

3899fa

34

For more information www.linear.com/LTC3899

LTC3899

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

FE Package

38-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1772 Rev C)

Exposed Pad Variation AA

4.75 REF

9.60 – 9.80*

(.378 – .386)

4.75

(.187)

REF

38

20

6.60 0.10

4.50 REF

2.74 REF

SEE NOTE 4

6.40

2.74

REF (.252)

(.108)

0.315 0.05

BSC

1.05 0.10

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

19

1.20

(.047)

MAX

4.30 – 4.50*

(.169 – .177)

0.25

REF

0° – 8°

0.50

(.0196)

BSC

0.09 – 0.20

(.0035 – .0079)

0.50 – 0.75

(.020 – .030)

0.05 – 0.15

(.002 – .006)

0.17 – 0.27

FE38 (AA) TSSOP REV C 0910

(.0067 – .0106)

TYP

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE

2. DIMENSIONS ARE IN

FOR EXPOSED PAD ATTACHMENT

MILLIMETERS

(INCHES)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

3. DRAWING NOT TO SCALE

3899fa

35

For more information www.linear.com/LTC3899

LTC3899

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-ꢀ70ꢀ Rev C)

0.70 0.05

5.50 0.05

5.ꢀ5 0.05

4.ꢀ0 0.05

3.ꢀ5 0.05

3.00 REF

PACKAGE

OUTLINE

0.25 0.05

0.50 BSC

5.5 REF

6.ꢀ0 0.05

7.50 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PIN ꢀ NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

0.75 0.05

0.00 – 0.05

3.00 REF

5.00 0.ꢀ0

37

38

0.40 0.ꢀ0

PIN ꢀ

TOP MARK

ꢀ

2

(SEE NOTE 6)

5.ꢀ5 0.ꢀ0

5.50 REF

7.00 0.ꢀ0

3.ꢀ5 0.ꢀ0

(UH) QFN REF C ꢀꢀ07

0.200 REF 0.25 0.05

0.50 BSC

R = 0.ꢀ25

TYP

R = 0.ꢀ0

TYP

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3. ALL DIMENSIONS ARE IN MILLIMETERS

3899fa

36

For more information www.linear.com/LTC3899

LTC3899

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

09/15 Clarified INTV Pin Functions

11

CC

SW1, SW2, SW3 pin callouts corrected

Block Diagram modified

13, 14

3899fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

37

For more information www.linear.com/LTC3899

LTC3899

TYPICAL APPLICATION

V

OUT1

R

A1

68.1k

B1

LTC3899

215k

TG1

MTOP1

V

FB1

C

B1

0.1µF

C

100pF

ITH1A

1500pF

L1

2.4µH

R

SNS1

6mΩ

BOOST1

SW1

V

3.3V

8A

OUT1

R

ITH1

10k

C

ITH1

C

OUT1B

OUT1A

220µF

47µF

ITH1

BG1

MBOT1

×2

C

SS1

0.1µF

+

SENSE1

TRACK/SS1

C1

1nF

–

SENSE1

V

OUT2

RUN1

RUN2

RUN3

R

B2

A2

68.1k

357k

V

FB2

R

V

ITH2

BIAS

C

2.2nF

ITH2

C

BIAS

0.1µF

12.7k

ITH2

GND

C

100pF

ITH2A

C

DRVCC

4.7µF

DRV

EXTV

CC

C

SS2

0.1µF

TRACK/SS2

TG2

MTOP2

V

OUT3

C

B2

0.1µF

R

B3

232k

A3

12.1k

L2

3.3µH

R

SNS2

6mΩ

BOOST2

SW2

V

5V

8A

OUT2

V

FB3

C

ITH3

4.7nF

C

OUT2B

OUT2A

220µF

R

ITH3

4.3k

47µF

BG2

MBOT2

×2

ITH3

C

220pF

ITH3A

+

SENSE2

C2

1nF

C

SS3

0.1µF

–

V

24V

5A

SENSE2

OUT3

SS3

C

OUT3B

OUT3A

33µF

2.2µF

FREQ

TG3

MTOP3

C

0.1µF

×6

B3

PLLIN/MODE

DRVSET

VPRG3

L3

3.7µH

R

SNS3

6mΩ

BOOST3

SW3

MTOP1, MTOP2: BSC057N08NS3

MBOT1, MBOT2: BSC036NE7NS3

MTOP3, MBOT3: BSC042NE7NS3

L1: WÜRTH 744325240

V

IN

12V TO 60V

C

IN2

IN1

C

33µF

2.2µF

MBOT3

INTVCC

BG3

0.1µF

L2: WÜRTH 744325330

×2

×3

L3: WÜRTH 7443551370

–

INTV

CC

SENSE3

C

, C : 6TPB220ML

IN1 OUT3A

OUT1A OUT2A

*V

IS 24V WHEN V < 24V,

IN

FOLLOWS V WHEN V > 24V

IN IN

OUT3

C3

1nF

, C : SUNCON 63HVP33M

+

3899 TA03

SENSE3

Figure 13. High Efficiency Triple 24V/3.3V/5V Converter with 10V Gate Drive

RELATED PARTS

PART NUMBER

LTC3859AL

DESCRIPTION

Triple Output, Buck/Buck/Boost Synchronous

Controller with 28µA Burst Mode I

COMMENTS

4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V

Up to 60V,

Up to 60V

IN

OUT

I = 28µA, Buck V

Range: 0.8V to 24V, Boost V

Q

OUT

LTC3892/LTC3892-1 60V, Low I , Dual 2-Phase Synchronous Step-Down PLL Fixed Frequency 50kHz to 900kHz, 4.5V ≤ V ≤ 60V,

Q

IN

DC/DC Controller with 99% Duty Cycle

0.8V ≤ V

≤ 0.99V , I = 29µA

OUT IN Q

LTC3769

LTC3784

Low I Synchronous Step-Up DC/DC Controller

4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 60V, V

Up to 60V, I = 28µA,

OUT Q

Q

IN

PLL Fixed Frequency 50kHz to 900kHz, 4mm × 4mm QFN-24, TSSOP-20E

4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 60V, V Up to 60V,

Low I , Multiphase, Dual Channel Single Output

Q

IN

OUT

Synchronous Step-Up DC/DC Controller

PLL Fixed Frequency 50kHz to 900kHz , I = 28µA

Q

LTC3890/LTC3890-1 60V, Low I , Dual 2-Phase Synchronous Step-Down PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,

Q

IN

LTC3890-2/LTC3890-3 DC/DC Controller with 99% Duty Cycle

0.8V ≤ V

≤ 24V, I = 50µA

OUT Q

LTC3891

60V, Low I , Synchronous Step-Down DC/DC

PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,

IN

Q

Controller with 99% Duty Cycle

0.8V ≤ V

≤ 24V, I = 50µA

OUT Q

LTC3857/LTC3857-1 Low I , Dual Output 2-Phase Synchronous Step-

Phase-Lockable Fixed Operating Frequency 50kHz to 900kHz,

4V ≤ V ≤ 38V, 0.8V ≤ V ≤ 24V, I = 50µA/170µA

Q

LTC3858/LTC3858-1 Down DC/DC Controller with 99% Duty Cycle

IN

OUT

Q

LTC3864

60V, Low I , High Voltage DC/DC Controller with

Fixed Frequency 50kHz to 850kHz, 3.5V ≤ V ≤ 60V,

IN

Q

100% Duty Cycle

0.8V ≤ V

≤ V , I = 40µA, MSOP-12E, 3mm × 4mm DFN-12

OUT IN Q

LT^®8705

80V V and V

Synchronous 4-Switch

V

Range: 2.8V (Need EXTV > 6.4V) to 80V,

OUT

IN

OUT

IN

CC

Buck-Boost DC/DC Controller

Range: 1.3V to 80V; 4 Regulation Loops

3899fa

LT 0915 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

38

For more information www.linear.com/LTC3899

●

 LINEAR TECHNOLOGY CORPORATION 2015

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3899


型号：	LTC3899EUHF#PBF
厂家：	Linear
描述：	LTC3899 - 60V Low IQ, Triple Output, Buck/Buck/Boost Synchronous Controller; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C
文件：	总38页 (文件大小：903K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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