LTC4007EUFD-1#TR [Linear]
LTC4007-1 - 4A, High Efficiency, Li-Ion Battery Charger; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC4007EUFD-1#TR |
| 厂家： | 
Linear |
| 描述： | LTC4007-1 - 4A, High Efficiency, Li-Ion Battery Charger; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 电源电路 电池 电源管理电路 |
| 文件： | 总24页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4007-1
4A, High Efficiency,
Li-Ion Battery Charger
U
FEATURES
DESCRIPTIO
The LTC®4007-1 is a constant-current/constant-voltage
charger controller for 3- or 4-cell lithium-ion batteries.
The PWM controller uses a synchronous, quasi-constant
frequency, constant off-time architecture that will not
generate audible noise even when using ceramic capaci-
tors. Chargingcurrentisprogrammableto ± 4%accuracy
using a programming resistor. Charging current can also
be monitored as a voltage across the programming
resistor.
■
Charger Controller for 3- or 4-Cell
Lithium-Ion Batteries
■
High Conversion Efficiency: Up to 96%
■
Output Currents Exceeding 4A
■
±0.8% Charging Voltage Accuracy
■
Built-In Charge Termination for Li-Ion Batteries
■
AC Adapter Current Limiting Maximizes Charge Rate*
■
Thermistor Input for Temperature Qualified Charging
■
Wide Input Voltage Range: 6V to 28V
■
0.5V Dropout Voltage; Maximum Duty Cycle: 98%
The output float voltage is pin programmed for cell count
(3 cells or 4 cells) and chemistry (4.2V/4.1V). A timer,
programmed by an external resistor, sets the total charge
time.
■
Programmable Charge Current: ±4% Accuracy
■
Indicator Outputs for Charging, C/10 Current
Detection, AC Adapter Present, Low Battery, Input
Current Limiting and Faults
■
The LTC4007-1 includes a thermistor input, which sus-
pends charging if an unsafe temperature condition is de-
tected. If the cell voltage is less than 3.25V, a low-battery
indicatorassertsandcanbeusedtoprogramatricklecharge
current to safely charge depleted batteries. The FAULT pin
is also asserted and charging terminates if the low-battery
conditionpersistsformorethan1/4ofthetotalchargetime.
Charging Current Monitor Output
■
Available in a 24-Pin 4mm × 5mm QFN Package
U
APPLICATIO S
■
Notebook Computers
■
Portable Instruments
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
*Protected by U.S. Patents including 5723970.
■
Battery-Backup Systems
Li-Ion Chargers
■
U
TYPICAL APPLICATIO
12.6V, 4A Li-Ion Battery Charger
INPUT SWITCH
DCIN
0V TO 28V
LOW BATTERY
THRESHOLD (Per Cell)
(4.2V/4.1V)
0.1µF
AUTO
4.99k
15nF
PART
RESTART
3C4C
DCIN
INFET
CLP
V
LOGIC
LTC4007-1
LTC4007
NO
3.25V/3.173V
2.5V/2.44V
0.025Ω
100k
100k 100k
CHEM
LOBAT
YES
SYSTEM
LOAD
LOBAT
I
I
LTC4007-1 CLN
TGATE
CL
CL
20µF
ACP
SHDN
FAULT
CHG
ACP
Q1
10µH
0.025Ω
SHDN
FAULT
CHG
BGATE
PGND
CSP
Li-Ion
BATTERY
Q2
20µF
3.01k
FLAG
FLAG
NTC
BAT
32.4k
3.01k
PROG
ITH
CHARGING
CURRENT
MONITOR
R
T
THERMISTOR
0.0047µF
0.47µF
GND
6.04k
0.12µF
10k
NTC
Q1: Si4431BDY
Q2: FDC645N
TIMING RESISTOR
(~2 HOURS)
26.7k
309k
40071 TA01
40071f
1
LTC4007-1
W W
U W
U
W U
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
Voltage from DCIN, CLP, CLN to GND ....... +32V/–0.3V
PGND with Respect to GND ................................. ±0.3V
CSP, BAT to GND....................................... +28V/–0.3V
CHEM, 3C4C, RT to GND .............................. +7V/–0.3V
NTC ............................................................ +10V/–0.3V
ACP, SHDN, CHG, FLAG,
FAULT, LOBAT, ICL .............................................. +32V/–0.3V
CLP to CLN ........................................................... ±0.5V
Operating Ambient Temperature Range
TOP VIEW
24 23 22 21 20
ACP
1
2
3
4
5
6
7
19
18
17
16
15
14
13
NC
R
T
PGND
TGATE
CLN
FAULT
GND
25
3C4C
LOBAT
NTC
CLP
FLAG
CHEM
8
9
10 11 12
(Note 4) ............................................. –40°C to 85°C
Operating Junction Temperature ......... –40°C to 125°C
Storage Temperature Range ................. –65°C to 125°C
UFD PACKAGE
24-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 90°C/W
EXPOSED PAD (PIN 25), GND AND PGND SHOULD BE CONNECTED
TOGETHER WITH A LOW OHMIC CONNECTION.
ORDER PART NUMBER
UFD PART MARKING
40071
LTC4007EUFD-1
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
A
●
denotes specifications which apply over the full operating
temperature range (Note 4), otherwise specifications are at T = 25°C. V
= 20V, V
= 12V unless otherwise noted.
DCIN
BAT
SYMBOL PARAMETER
DCIN Operating Range
CONDITIONS
MIN
TYP
MAX
28
UNITS
V
6
I
Operating Current
Sum of Current from CLP, CLN , DCIN
3
5
mA
Q
V
Charge Voltage Accuracy
Nominal Values: 12.3V, 12.6V, 16.4V, 16.8V
(Note 2)
–0.8
–1.0
0.8
1.0
%
%
TOL
●
●
I
Charge Current Accuracy (Note 3)
V
– V
Target = 100mV
–4
–5
4
5
%
%
%
%
TOL
CSP
BAT
V
< 6V, V
– V
Target = 10mV
BAT
±60
±35
BAT
CSP
6V ≤ V
Target = 10mV
≤ V
, V
– V
BAT
LOBAT CSP BAT
T
Measured Sample Time
Battery Leakage Current
R
= 1190k
●
42
60
ms
SAMPLE
RT
Shutdown
DCIN = 0V
SHDN = 3V
●
●
20
35
10
µA
µA
–10
4.2
1
UVLO
Undervoltage Lockout Threshold
Shutdown Threshold at SHDN
SHDN Pin Current
DCIN Rising, V
= 0
●
●
4.7
1.6
–10
2
5.5
2.5
V
V
BAT
µA
mA
Operating Current in Shutdown
V
= 0V, Sum of Current from CLP,
3
SHDN
CLN, DCIN
40071f
2
LTC4007-1
ELECTRICAL CHARACTERISTICS
The
A
●
denotes specifications which apply over the full operating
= 20V, V = 12V unless otherwise noted.
temperature range (Note 4), otherwise specifications are at T = 25°C. V
DCIN
BAT
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Sense Amplifier, CA1
Input Bias Current Into BAT Pin
CA1/I Input Common Mode Low
11.67
µA
V
CMSL
CMSH
●
●
0
1
CA1/I Input Common Mode High
V
– 0.2
CLN
V
1
Current Comparators I
and I
REV
CMP
I
I
Maximum Current Sense Threshold (V
– V
)
BAT
V = 2.5V
ITH
●
140
165
–30
200
mV
mV
TMAX
TREV
CSP
Reverse Current Threshold (V
– V
)
BAT
CSP
Current Sense Amplifier, CA2
Transconductance
Source Current
1
mmho
µA
Measured at I , V = 1.4V
–40
40
TH ITH
Sink Current
Measured at I , V = 1.4V
µA
TH ITH
Current Limit Amplifier
Transconductance
1.4
100
100
mmho
mV
V
Current Limit Threshold
CLP Input Bias Current
●
93
107
110
CLP
CLP
I
nA
Voltage Error Amplifier, EA
Transconductance
Sink Current
1
mmho
µA
Measured at I , V = 1.4V
36
TH ITH
OVSD
Overvoltage Shutdown Threshold as a Percent
of Programmed Charger Voltage
●
●
102
0
107
%
Input P-Channel FET Driver (INFET)
DCIN Detection Threshold (V
– V
)
CLN
DCIN Voltage Ramping Up
0.17
0.25
50
V
DCIN
from V
– 0.1V
CLN
Forward Regulation Voltage (V
– V
)
●
●
●
25
–25
5.8
mV
mV
V
DCIN
CLN
Reverse Voltage Turn-Off Voltage (V
– V
)
DCIN Voltage Ramping Down
–60
5
DCIN
CLN
INFET “On” Clamping Voltage (V
INFET “Off” Clamping Voltage (V
– V
– V
)
I
I
= 1µA
6.5
DCIN
DCIN
INFET
INFET
INFET
)
= –25µA
0.25
V
INFET
Thermistor
NTCVR
Reference Voltage During Sample Time
High Threshold
4.5
V
V
V
NTC
V
NTC
V
NTC
Rising
Falling
≤ 10V
●
●
NTCVR NTCVR NTCVR
• 0.48 • 0.5 • 0.52
Low Threshold
NTCVR NTCVR NTCVR
• 0.115 • 0.125 • 0.135
V
Thermistor Disable Current
10
µA
Indicator Outputs (ACP, CHG, FLAG, LOBAT, I , FAULT
CL
C10TOL
LBTOL
FLAG (C/10) Accuracy
Voltage Falling at PROG
●
0.375
0.397
0.420
V
LOBAT Threshold Accuracy
3C4C = 0V, CHEM = 0V
●
●
●
●
9.233
9.458
9.519
9.750
9.805
10.043
V
V
V
V
3C4C = 0V, CHEM = Open
3C4C = Open, CHEM = 0V
3C4C = Open, CHEM = Open
12.311 12.692 13.074
12.610 13.000 13.390
I
Threshold Accuracy
83
93
1O5
mV
40071f
3
CL
LTC4007-1
ELECTRICAL CHARACTERISTICS
The
A
●
denotes specifications which apply over the full operating
= 20V, V = 12V unless otherwise noted.
temperature range (Note 4), otherwise specifications are at T = 25°C. V
DCIN
BAT
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Low Logic Level of ACP, CHG, FLAG, LOBAT,
, FAULT
I
= 100µA
●
●
0.5
V
OL
OL
I
CL
V
High Logic Level of CHG, LOBAT, I
I
= –1µA
2.7
–1
V
µA
µA
V
OH
OFF
PO
CL
OH
I
I
Off State Leakage Current of ACP, FLAG, FAULT
V
= 3V
1
OH
Pull-Up Current on CHG, LOBAT, I
Timer Defeat Threshold at CHG
V = 0V
–10
CL
1
1
Programming Inputs (CHEM and 3C4C)
V
V
High Logic Level
Low Logic Level
Pull-Up Current
●
●
3.3
345
V
V
IH
IL
I
V = 0V
–14
µA
PI
Oscillator
f
f
Regulator Switching Frequency
255
20
300
25
kHz
kHz
%
OSC
MIN
Regulator Switching Frequency in Drop Out
Regulator Maximum Duty Cycle
Duty Cycle ≥ 98%
DC
V
= V
BAT
98
99
MAX
CSP
Gate Drivers (TGATE, BGATE)
V
V
V
V
High (V
High
– V
)
I
= –1mA
= 3000pF
= 3000pF
= 1mA
50
10
10
50
mV
V
TGATE
BGATE
TGATE
BGATE
CLN
TGATE
TGATE
C
C
4.5
4.5
5.6
5.6
LOAD
Low (V
Low
– V
)
V
CLN
TGATE
LOAD
I
mV
BGATE
TGATE Transition Time
TGATE Rise Time
TGATE Fall Time
TGTR
TGTF
C
LOAD
C
LOAD
= 3000pF, 10% to 90%
= 3000pF, 10% to 90%
50
50
110
100
ns
ns
BGATE Transition Time
BGATE Rise Time
BGATE Fall Time
BGTR
BGTF
C
LOAD
C
LOAD
= 3000pF, 10% to 90%
= 3000pF, 10% to 90%
40
40
90
80
ns
ns
V
V
at Shutdown (V
at Shutdown
– V
)
I
I
= –1µA, DCIN = 0V, CLN = 12V
= 1µA, DCIN = 0V, CLN = 12V
100
100
mV
mV
TGATE
BGATE
CLN
TGATE
TGATE
BGATE
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: See Test Circuit.
Note 3: Does not include tolerance of current sense resistor or current
Note 4: The LTC4007E-1 is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
programming resistor.
40071f
4
LTC4007-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
INFET Response Time to
Reverse Current
Line Regulation
V vs I
OUT OUT
0.10
0.05
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
V
OF PFET (2V/DIV)
gs
V
= 0
gs
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
–0.45
C3C4 = OPEN
V OF PFET (5V/DIV)
s
C3C4 = GND
V = 0V
s
I
(REVERSE) OF
d
3C4C = GND
3C4C = OPEN
PFET (5A/DIV)
I
d
= 0A
13 15 17 19 21 23 25 27 29 31
VDCIN (V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
OUTPUT CURRENT (A)
1.25µs/DIV
TEST PERFORMED ON DEMOBOARD
= 15VDC = 12.6V
40071 G02
40071 G03
V
V
CHARGE
IN
CHARGER = ON
= <10mA
PFET = 1/2 Si4925DY
I
40071 G01
CHARGE
Disconnect/Reconnect Battery
(Load Dump)
PWM Frequency vs Duty Cycle
1A Load Step (Battery Present)
350
300
250
200
150
100
50
3A STEP
CHARGER CURRENT (1A/DIV)
1A STEP
1A STEP
V
FLOAT
1V/DIV
OUTPUT VOLTAGE (500mV/DIV)
PROGRAMMED CURRENT = 10%
3A STEP
RECONNECT
LOAD
STATE
DISCONNECT
DCIN = 15V
DCIN = 20V
DCIN = 24V
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DUTY CYCLE (V /V
LOAD CURRENT = 1A, 2A, 3A
DCIN = 20V
DCIN = 20V
= 12.6V
V
)
FLOAT
OUT IN
V
= 12.6V (3C4C = GND, CHEM = OPEN)
FLOAT
40071 G04
40071 G06
40071 G05
1A Load Step
(Battery Not Present)
Battery Leakage Current vs
Battery Voltage
40
35
30
25
20
15
10
5
VDCIN = 0V
CHARGER CURRENT (500mA/DIV)
OUTPUT VOLTAGE (5V/DIV)
0
0
5
10
15
20
25
30
DCIN = 20V
= 12.6V
BATTERY VOLTAGE (V)
V
FLOAT
40071 G08
40071 G07
40071f
5
LTC4007-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency at 19VDC V
Efficiency at 12.6V with 15VDC V
IN
IN
100
95
90
85
80
75
100
95
90
85
80
75
16.8V
12.6V
0.50
1.00
1.50
2.00
2.50
3.00
0.50
1.00
1.50
2.00
2.50
3.00
CHARGE CURRENT (A)
CHARGE CURRENT (A)
40071 G10
40071 G11
U
U
U
PI FU CTIO S
ACP(Pin 1): Open-Drain output to indicate if the AC
adapter voltage is adequate for charging. This pin is pulled
low by an internal N-channel MOSFET if DCIN is below
BAT. A pull-up resistor is required. The pin is capable of
sinking at least 100µA.
3C4C (Pin 5): Select 3-cell or 4-cell float voltage by
connecting this pin to GND or open, respectively. Internal
14µA pull-up to 5.3V. This pin can also be driven with
open-collector/drain logic levels. High: 4 cell. Low: 3 cell.
LOBAT (Pin 6): Low-Battery Indicator. Active low digital
output. Internal 10µA pull-up to 3.5V. If the battery
voltageisbelow3.25V/cell(or3.173V/cellfor4.1Vchem-
istry batteries) LOBAT will be low. The pin is capable of
sinking at least 100µA. If VLOGIC is greater than 3.3V, add
an external pull-up.
RT (Pin 2): Timer Resistor. The timer period is set by
placing a resistor, RRT , to GND. This resistor is always
required.
The timer period is tTIMER = (1hour • RRT/154K).
If this resistor is not present, the charger will not start.
NTC (Pin 7): A thermistor network is connected from NTC
to GND. This pin determines if the battery temperature is
safe for charging. The charger and timer are suspended
and the FAULT pin is driven low if the thermistor indicates
a temperature that is unsafe for charging. The thermistor
functionmaybedisabledwitha300kto500kresistorfrom
DCIN to NTC.
FAULT (Pin 3): Active low open-drain output that indi-
cates charger operation has stopped due to a low-battery
conditioningerror, orthatchargeroperationissuspended
due to the thermistor exceeding allowed values. A pull-up
resistor is required if this function is used. The pin is
capable of sinking at least 100µA.
GND (Pin 4): Ground for Low Power Circuitry.
ITH(Pin8):ControlSignaloftheInnerLoopoftheCurrent
Mode PWM. Higher ITH voltage corresponds to higher
charging current in normal operation. A 6k resistor, in
series with a capacitor of at least 0.1µF to GND provides
loop compensation. Typical full-scale output current is
40µA. Nominal voltage range for this pin is 0V to 3V.
40071f
6
LTC4007-1
U
U
U
PI FU CTIO S
PROG (Pin 9): Current Programming/Monitoring Input/
Output. An external resistor to GND programs the peak
charging current in conjunction with the current sensing
resistor. The voltage at this pin provides a linear indication
of charging current. Peak current is equivalent to 1.19V.
Zero current is approximately 0.3V. A capacitor from
PROG to ground is required to filter higher frequency
components. The maximum resistance to ground is 100k.
Values higher than 100k can cause the charger to shut
down.
CLP (Pin 15): Positive input to the supply current limiting
amplifier, CL1. The threshold is set at 100mV above the
voltage at the CLN pin. When used to limit supply current,
a filter is needed to filter out the switching noise. If no
current limit function is desired, connect this pin to CLN.
CLN (Pin 16): Negative Reference for the Input Current
Limit Amplifier, CL1. This pin also serves as the power
supply for the IC. A 10µF to 22µF bypass capacitor should
be connected as close as possible to this pin.
TGATE(Pin17):DrivesthetopexternalP-channelMOSFET
of the battery charger buck converter.
ICL (Pin 10): Input Current Limit Indicator. Active low
digital output. Internal 10µA pull-up to 3.5V. Pulled low if
the charger current is being reduced by the input current
limiting function. The pin is capable of sinking at least
100µA. If VLOGIC is greater than 3.3V, add an external
pull-up.
PGND (Pin 18):HighCurrentGroundReturnfortheBGATE
Driver.
NC (Pin 19): No Connect.
BGATE (Pin 20): Drives the bottom external N-channel
MOSFET of the battery charger buck converter.
CSP (Pin 11): Current Amplifier CA1 Input. The CSP and
BAT pins measure the voltage across the sense resistor,
RSENSE, to provide the instantaneous current signals re-
quired for both peak and average current mode operation.
INFET(Pin21):DrivestheGateoftheExternalInputPFET.
SHDN (Pin 22):Charger is shut down and timer is reset
when this pin is HIGH. Internal 10µA pull-up to 3.5V. This
pin can also be used to reset the charger by applying a
positive pulse that is a minimum of 0.1µs long.
BAT (Pin 12): Battery Sense Input and the Negative
Reference for the Current Sense Resistor. A precision
internal resistor divider sets the final float potential on this
pin.Theresistordividerisdisconnectedduringshutdown.
DCIN (Pin 23): External DC Power Source Input. Bypass
thispinwithatleast0.01µF. SeeApplicationsInformation.
CHEM (Pin 13):Select 4.1V or 4.2V cell chemistry by
connecting the pin to GND or open, respectively. Internal
14µA pull-up to 5.3V. Can also be driven with open-
collector/drain logic levels.
CHG (Pin 24): Charge Status Output. When the battery is
being charged, the CHG pin is pulled low by an internal
N-channel MOSFET. Internal 10µA pull-up to 3.5V. If
VLOGIC is greater than 3.3V, add an external pull-up. The
timerfunctioncanbedefeatedbyforcingthispinbelow1V
(or connecting it to GND).
FLAG (Pin 14): Active low open-drain output that indi-
cates when charging current has declined to 10% of
maximum programmed current. A pull-up resistor is
required if this function is used. The pin is capable of
sinking at least 100µA.
Exposed Pad (Pin 25): The exposed pad, GND and PGND
should be connected together with a low ohmic connec-
tion.
40071f
7
LTC4007-1
BLOCK DIAGRA
0.1µF
W
V
IN
DCIN
23
5.8V
INFET
Q3
21
1
CLN
24 CHG
ACP
R
RT
R
T
OSCILLATOR
2
7
TIMER/CONTROLLER
SHDN 22
FAULT
3
32.4k
TBAD
NTC
THERMISTOR
10k
NTC
0.47µF
–
397mV
C/10
FLAG 14
+
35mV
GND
4
–
+
11.67µA
3C4C
5
MUX
3.01k
BAT
CSP
CHEM 13
12
11
–
+
R
SENSE
20µF
+
–
CA1
3.01k
LOBAT
6
921mV
1.19V
Ω
+
g
m
= 1m
EA
–
5k
CLP
CLN
Ω
g
= 1.4m
m
15
–
+
9k
R
15nF
CL1
CL
100mV
Ω
–
+
g
= 1m
m
16
10
CA2
I
1.19V
CL
DCIN
ITH
OSCILLATOR
WATCHDOG
DETECT
8
6K
0.12µF
20µF
t
OFF
+
–
BUFFERED ITH
÷ 5
OV
1.28V
CLN
TGATE
S
+
–
+
17
–
Q1
Q2
Q
I
R
CMP
BGATE
PGND
CHARGE
PWM
LOGIC
20
18
–
+
I
REV
17mV
PROG
9
L1
R
PROG
26.7k
0.0047µF
40071 BD
40071f
8
LTC4007-1
TEST CIRCUIT
LTC4007-1
CHEM
3C4C
V
REF
13
5
+
–
DIVIDER/
MUX
EA
CSP
BAT
ITH
8
11
12
+
–
LT1055
0.6V
40071 TC
U
OPERATIO
drops to 10% of the full-scale charge current, an internal
C/10 comparator will indicate this condition by latching
the FLAG pin low. The charge timer is also reset to 1/4 of
thetotalchargetimewhenFLAGgoeslow.Ifthiscondition
is caused by an input current limit condition, described
below, then the FLAG indicator will be inhibited. When a
time-out occurs, charging is terminated immediately and
the CHG pin is forced to a high impedance state. To restart
the charge cycle manually, simply remove the input volt-
age and reapply it, or set the SHDN pin high momentarily.
When the input voltage is not present, the charger goes
into a sleep mode, dropping battery current drain to 15µA.
This greatly reduces the current drain on the battery and
increases the standby time. The charger is inhibited any
time the SHDN pin is high.
Overview
The LTC4007-1 is a synchronous current mode PWM
step-down(buck)switcherbatterychargercontroller. The
charge current is programmed by the combination of a
program resistor (RPROG) from the PROG pin to ground
and a sense resistor (RSENSE) between the CSP and BAT
pins. The final float voltage is programmed to one of four
values (12.3V, 12.6V, 16.4V, 16.8V) with ±1% maximum
accuracy using pins 3C4C and CHEM. Charging begins
when the potential at the DCIN pin rises above the voltage
atBAT(andtheUVLOvoltage)andtheSHDNpinislow;the
CHG pin is set low. At the beginning of the charge cycle, if
thecellvoltageisbelow3.25V(3.173VifCHEMislow),the
LOBAT pin will be low. The LOBAT indicator can be used
to reduce the charging current to a low value, typically
10% of full scale. If the cell voltage stays below 3.25V for
25% of the total charge time, the charge sequence will be
terminated immediately and the FAULT pin will be set low.
Input FET
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLN pin
and provides the logic indicator of AC present on the ACP
pin. It controls the gate of the input FET to keep a low
forward voltage drop when charging and also prevents
reverse current flow through the input FET.
An external thermistor network is sampled at regular
intervals. If the thermistor value exceeds design limits,
charging is suspended and the FAULT pin is set low. If the
thermistor value returns to an acceptable value, charging
resumesandtheFAULTpinissethigh.Anexternalresistor
on the RT pin sets the total charge time. The timer can be
defeated by forcing the CHG pin to a low voltage.
If the input voltage is less than VCLN, it must go at least
170mVhigherthanVCLN toactivatethecharger.Whenthis
occurs the ACP pin is released and pulled up with an
external load to indicate that the adapter is present. The
As the battery approaches the final float voltage, the
charge current will begin to decrease. When the current
40071f
9
LTC4007-1
U
OPERATIO
Table 1. Truth Table for LTC4007-1 Operation (Supplemental)
PRESENT NEXT
MAX
BATTERY
CURRENT
FROM
STATE
TO
STATE
BATTERY
DCIN VOLTAGE
C/10
C/10
TIMER
STATE
NUMBER
MODE
LATCH LATCH
ACP
CHG
1
Any
MSD
Shut Down by Low
Adapter Voltage
<BAT
0
OFF
LOW
Reset
HIGH
2
3
MSD
SD,
CONDITION,
CHARGE
SD
SD
Charger Shutdown
Shut Down by
Undervoltage Lockout
>BAT
0
OFF
OFF
HIGH
HIGH
Reset
Reset
HIGH
HIGH*
>BAT
and
<UVL
4
5
6
7
SD
CONDITION Start Conditioning a
Depleted Battery
>BAT <3.25V/Cell
>BAT <3.25V/Cell
>BAT <3.25V/Cell
>BAT <3.25V/Cell
10%
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
Programmed
Current
CONDITION CONDITION Input Current Limited
Condition Charging
<10%
Programmed
Current (Note 2)
10%
Programmed
Current
10%
Programmed
Current
Running
Running
CONDITION CONDITION Conditioning a
Depleted Battery
CONDITION CONDITION Timer Defeated (Low
Battery Conditioning
Ignored Forced
LOW
Still Functional)
8
CONDITION
CONDITION
CONDITION
SD
SD
SD
Charger Paused Due to
Thermistor Out of Range
Timeout in
CONDITION Mode
Shut Down by
ACP/SHDN Pin
>BAT <3.25V/Cell
>BAT <3.25V/Cell
>BAT <3.25V/Cell
>BAT >3.25V/Cell
>BAT >3.25V/Cell
OFF
OFF
OFF
HIGH
HIGH
Paused
>T/4
LOW
(Faulted)
9
HIGH
(Faulted)
HIGH
10
11
12
0
Forced
LOW
HIGH
Reset
CONDITION CHARGE Start Normal Charging
Programmed
Current
Programmed
Current
Running
CHARGE
CHARGE Timer Defeated (Low
Battery Conditioning
HIGH
Ignored Forced
LOW
Still Functional)
13
14
CHARGE
CHARGE
CHARGE Top-Off Charging
>BAT >3.25V/Cell
>BAT >3.25V/Cell
0
Programmed
Current
Programmed
Current
HIGH
HIGH
Running
Reset
LOW
CHARGE C/10 Latch is SET
when Battery Current
Is Less than 10% of
1
25µA
Programmed Current
15
16
17
CHARGE
CHARGE
CHARGE
CHARGE Top-Off Charging
>BAT >3.25V/Cell
>BAT >3.25V/Cell
>BAT >3.25V/Cell
1
Programmed
Current
<Programmed
Current (Note 2)
HIGH
HIGH
HIGH
Running
25µA
CHARGE Input Current
Limited Charging
SD
Charger Paused Due to
Thermistor Out of Range
OFF
Paused LOW or
25µA
(Faulted)
18
19
20
21
CHARGE
CHARGE
CHARGE
CHARGE
SD
SD
SD
SD
Shut Down by
ACP/SHDN Pin
Terminated by Low-
Battery Fault (Note 1)
>BAT >3.25V/Cell
>BAT <3.25V/Cell
0
OFF
OFF
OFF
OFF
Forced
LOW
Reset
HIGH
0
HIGH
HIGH
HIGH
>T/4 then HIGH
Reset (Faulted)
>T/4 then HIGH
Reset
>T then
Reset
Terminates After T/4
>BAT
>BAT
V
1
0
FLOAT
Terminates After T
V
FLOAT
*
HIGH
*Most probable condition
Note3:Blankfieldsindicatenochange, notconsidered, orotherstatesimpact
value.
Note 1: If a depleted battery is inserted while the charger is in this state, the
charger must be reset to initiate charging.
Note 4: Battery voltage thresholds do not include comparator hysterisis.
Note 2: See section on “Adapter Limiting”.
Thresholds specify the VLH value.
40071f
10
LTC4007-1
U
OPERATIO
LTC4007-1: State Diagram
1
MASTER
SHUTDOWN
ANY
2
SHUTDOWN
4
3, 8,
9, 10
3, 17, 18,
19, 20, 21
CONDITION
11
5, 6, 7
CHARGE
12, 13, 14, 15, 16
40071 TBL01
gateoftheinputFETisdriventoavoltagesufficienttokeep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLN drops to less than 25mV,
the input FET is turned off slowly. If the voltage between
DCIN and CLN is ever less than –25mV, then the input FET
is turned off in less than 10µs to prevent significant
reverse current from flowing in the input FET. In this
condition, the ACP pin is driven low and the charger is
disabled.
to set the bottom MOSFET on time. The result is a nearly
constant switching frequency over a wide input/output
voltage range. This activity is diagrammed in Figure 1.
The peak inductor current, at which ICMP resets the SR
latch, is controlled by the voltage on ITH. ITH is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
current programmed by RPROG at the PROG pin and
Battery Charger Controller
The LTC4007-1 charger controller uses a constant off-
time, current mode step-down architecture. During nor-
mal operation, the top MOSFET is turned on each cycle
when the oscillator sets the SR latch and turned off when
the main current comparator ICMP resets the SR latch.
WhilethetopMOSFETisoff,thebottomMOSFETisturned
on until either the inductor current trips the current com-
parator IREV or the beginning of the next cycle. The
oscillator uses the equation:
OFF
TGATE
ON
ON
t
BGATE
OFF
OFF
TRIP POINT SET BY ITH VOLTAGE
INDUCTOR
CURRENT
40071 F01
VDCIN – VBAT
VDCIN • fOSC
Figure 1
tOFF
=
40071f
11
LTC4007-1
U
OPERATIO
adjusts ITH until:
If the charging current decreases below 10% to 15% of
programmed current while engaged in input current lim-
iting, BGATEwillbeforcedlowtopreventthechargerfrom
discharging the battery. Audible noise can occur in this
mode of operation.
VREF
RPROG
VCSP – VBAT + 11.67µA • 3.01kΩ
=
3.01kΩ
therefore,
An overvoltage comparator guards against voltage tran-
sient overshoots (>7% of programmed value). In this
case, both MOSFETs are turned off until the overvoltage
condition is cleared. This feature is useful for batteries
which “load dump” themselves by opening their protec-
tion switch to perform functions such as calibration or
pulse mode charging.
⎛ VREF
⎝RPROG
⎞ 3.01kΩ
– 11.67µA •
ICHARGE(MAX)
=
⎜
⎟
⎠ RSENSE
The voltage at BAT is divided down by an internal resistor
divider and is used by error amp EA to decrease ITH if the
divider voltage is above the 1.19V reference. When the
charging current begins to decrease, the voltage at PROG
will decrease in direct proportion. The voltage at PROG is
then given by:
PWM Watchdog Timer
There is a watchdog timer that observes the activity on the
BGATE and TGATE pins. If TGATE stops switching for
more than 40µs, the watchdog activates and turns off the
top MOSFET for about 400ns. The watchdog engages to
prevent very low frequency operation in dropout—a po-
tential source of audible noise when using ceramic input
and output capacitors.
RPROG
3.01kΩ
VPROG = ICHARGE •RSENSE + 11.67µA • 3.01kΩ •
(
)
VPROG is plotted in Figure 2.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter to a preset level (100mV/
RCL). At input current limit, CL1 will decrease the ITH
voltage,therebyreducingchargingcurrent.TheICL indica-
tor output will go low when this condition is detected and
the FLAG indicator will be inhibited if it is not already LOW.
Charger Start-Up
When the charger is enabled, it will not begin switching
until the ITH voltage exceeds a threshold that assures
initial current will be positive. This threshold is 5% to 15%
of the maximum programmed current. After the charger
beginsswitching,thevariousloopswillcontrolthecurrent
at a level that is higher or lower than the initial current. The
duration of this transient condition depends upon the loop
compensation, but is typically less than 100µs.
1.2
1.0
0.8
0.6
0.4
0.2
0
1.19V
0.309V
Thermistor Detection
The thermistor detection circuit is shown in Figure 3. It
requires an external resistor and capacitor in order to
function properly.
60
80
0
20
40
100
I
(% OF MAXIMUM CURRENT)
CHARGE
40071 F02
Thethermistordetectorperformsasample-and-holdfunc-
tion. An internal clock, whose frequency is determined by
Figure 2. V
vs I
CHARGE
PROG
40071f
12
LTC4007-1
U
OPERATIO
the timing resistor connected to RT, keeps switch S1
closed to sample the thermistor:
t
HOLD = 10 • RRT • 17.5pF = 54µs,
for RRT = 309k
tSAMPLE = 127.5 • 20 • RRT • 17.5pF = 13.8ms,
for RRT = 309k
When the tHOLD interval ends the result of the thermistor
testing is stored in the D flip-flop (DFF). If the voltage at
NTC is within the limits provided by the resistor divider
feeding the comparators, then the NOR gate output will be
low and the DFF will set TBAD to zero and charging will
continue. If the voltage at NTC is outside of the resistor
dividerlimits, thentheDFFwillsetTBAD toone, thecharger
will be shut down, FAULT pin is set low and the timer will
be suspended until TBAD returns to zero (see Figure 4).
The external RC network is driven to approximately 4.5V
and settles to a final value across the thermistor of:
4.5V •RTH
RTH + R9
VRTH(FINAL)
=
This voltage is stored by C7. Then the switch is opened for
a short period of time to read the voltage across the
thermistor.
LTC4007-1
CLK
R9
–
32.4k
NTC
7
R
S1
TH
C7
0.47µF
+
~4.5V
10k
NTC
60k
+
–
45k
15k
–
+
TBAD
D
C
Q
40071 F03
Figure 3
CLK
(NOT TO
SCALE)
t
SAMPLE
t
HOLD
VOLTAGE ACROSS THERMISTOR
COMPARATOR HIGH LIMIT
COMPARATOR LOW LIMIT
V
NTC
40071 F04
Figure 4
40071f
13
LTC4007-1
W U U
U
APPLICATIO S I FOR ATIO
Battery Detection
LTC4007-1
PROG
9
It is generally not good practice to connect a battery while
the charger is running. The timer is in an unknown state
and the charger could provide a large surge current into
the battery for a brief time. The Figure 5 circuit keeps the
chargershutdownandthetimerresetwhileabatteryisnot
connected.
R
Z
C
PROG
R
PROG
102k
5V
0V
Q1
2N7002
40071 F06
LTC4007-1
ADAPTER
Figure 6. PWM Current Programming
23 DCIN
POWER
Charging current can be programmed by pulse width
modulating RPROG with a switch Q1 to RPROG at a fre-
quency higher than a few kHz (Figure 6). CPROG must be
increased to reduce the ripple caused by the RPROG
switching. The compensation capacitor at ITH will prob-
ably need to be increased also to improve stability and
prevent large overshoot currents during start-up condi-
tions. Charging current will be proportional to the duty
cycleoftheswitchwithfullcurrentat100%dutycycleand
zero current when Q1 is off.
22 SHDN
SWITCH CLOSED
WHEN BATTERY
CONNECTED
40071 F05
Figure 5
Charger Current Programming
The basic formula for charging current is:
VREF • 3.01kΩ / RPROG – 0.035V
ICHARGE(MAX)
VREF = 1.19V
=
RSENSE
Maintaining C/10 Accuracy
The C/10 comparator threshold that drives the FLAG pin
has a fixed threshold of approximately VPROG = 400mV.
This threshold works well when RPROG is 26.7k, but will
not yield a 10% charging current indication if RPROG is a
different value. There are situations where a standard
valueofRSENSE willnotallowthedesiredvalueofcharging
current when using the preferred RPROG value. In these
cases, wherethefull-scalevoltageacrossRSENSE iswithin
±20mV of the 100mV full-scale target, the input resistors
connected to CSP and BAT can be adjusted to provide the
desired maximum programming current as well as the
correct FLAG trip point.
This leaves two degrees of freedom: RSENSE and RPROG
.
The3.01kinputresistorsmustnotbealteredsinceinternal
currents and voltages are trimmed for this value. Pick
RSENSE by setting the average voltage between CSP and
BAT to be close to 100mV during maximum charger
current. Then RPROG can be determined by solving the
above equation for RPROG
.
VREF • 3.01kΩ
RSENSE •ICHARGE(MAX) + 0.035V
RPROG
=
Table 2. Recommended R
and R
Resistor Values
SNS
(Ω) 1%
PROG
(W)
For example, the desired max charging current is 2.5A but
the best RSENSE value is 0.033Ω. In this case, the voltage
across RSENSE at maximum charging current is only
82.5mV, normally RPROG would be 30.1k but the nominal
FLAG trip point is only 5% of maximum charging current.
If the input resistors are reduced by the same amount as
I
(A)
R
SENSE
R
SENSE
R
PROG
(kΩ) 1%
MAX
1.0
0.100
0.25
0.25
0.5
26.7
2.0
3.0
4.0
0.050
0.033
0.025
26.7
26.7
26.7
0.5
40071f
14
LTC4007-1
W U U
APPLICATIO S I FOR ATIO
the full-scale voltage is reduced then, R4 = R5 = 2.49k and
RPROG = 26.7k, the maximum charging current is still 2.5A
but the FLAG trip point is maintained at 10% of full scale.
U
500
450
400
350
300
250
200
150
100
50
There are other effects to consider. The voltage across the
current comparator is scaled to obtain the same values as
the 100mV sense voltage target, but the input referred
sense voltage is reduced, causing some careful consider-
ation of the ripple current. Input referred maximum com-
paratorthresholdis117mV,whichisthesameratioof1.4x
the DC target. Input referred IREV threshold is scaled back
to –24mV. The current at which the switcher starts will be
reduced as well so there is some risk of boost activity.
Theseconcernscanbeaddressedbyusingaslightlylarger
inductor to compensate for the reduction of tolerance to
ripple current.
0
100
300
500
700
900 1100 1300
R
(kΩ)
RT
40071 F07
Figure 7. t
vs R
RT
TIMER
It is important to keep the parasitic capacitance on the RT
pin to a minimum. The trace connecting RT to RRT should
be as short as possible.
Charger Voltage Programming
PinsCHEMandC3C4areusedtoprogramthechargerfinal
output voltage. The CHEM pin programs Li-Ion battery
chemistry for 4.1V/cell (low) or 4.2V/cell (high). The C3C4
pin selects either 3 series cells (low) or 4 series cells
(high). It is recommended that these pins be shorted to
ground (logic low) or left open (logic high) to effect the
desired logic level. Use open-collector or open-drain out-
puts when interfacing to the CHEM and 3C4C pins from a
logic control circuit.
Soft-Start
The LTC4007-1 is soft started by the 0.12µF capacitor on
the ITH pin. On start-up, ITH pin voltage will rise quickly to
0.5V, then ramp up at a rate set by the internal 40µA pull-
up current and the external capacitor. Battery charging
current starts ramping up when ITH voltage reaches 0.8V
and full current is achieved with ITH at 2V. With a 0.12µF
capacitor, time to reach full charge current is about 2ms
and it is assumed that input voltage to the charger will
reach full value in less than 2ms. The capacitor can be
increased up to 1µF if longer input start-up times are
needed.
Table 3. Charger Voltage Programming
V
(V)
3C4C
LOW
LOW
HIGH
HIGH
CHEM
LOW
HIGH
LOW
HIGH
FINAL
12.3
12.6
16.4
16.8
Input and Output Capacitors
The input capacitor (C2) is assumed to absorb all input
switching ripple current in the converter, so it must have
adequate ripple current rating. Worst-case RMS ripple
currentwillbeequaltoonehalfofoutputchargingcurrent.
Actual capacitance value is not critical. Solid tantalum low
ESR capacitors have high ripple current rating in a rela-
tively small surface mount package, but caution must be
Setting the Timer Resistor
The charger termination timer is designed for a range of
1hour to 3 hour with a ±15% uncertainty. The timer is
programmed by the resistor RRT using the following
equation:
tTIMER = 10 • 227 • RRT • 17.5pF (seconds)
40071f
15
LTC4007-1
W U U
U
APPLICATIO S I FOR ATIO
used when tantalum capacitors are used for input or
output bypass. High input surge currents can be created
when the adapter is hot-plugged to the charger or when a
batteryisconnectedtothecharger. Solidtantalumcapaci-
tors have a known failure mechanism when subjected to
very high turn-on surge currents. Only Kemet T495 series
of “Surge Robust” low ESR tantalums are rated for high
surge conditions such as battery to ground.
is raised to 4Ω with a bead or inductor, only 5% of the
current ripple will flow in the battery.
Inductor Selection
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency gener-
ally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value on
ripple current and low current operation must also be
considered. The inductor ripple current ∆IL decreases
with higher frequency and increases with higher VIN.
The relatively high ESR of an aluminum electrolytic for C1,
located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event. Refer to AN88
for more information.
1
⎛
⎝
VOUT
V
IN
⎞
∆IL =
VOUT 1–
Highest possible voltage rating on the capacitor will mini-
mizeproblems. Consultwiththemanufacturerbeforeuse.
Alternatives include new high capacity ceramic (at least
20µF) from Tokin, United Chemi-Con/Marcon, et al. Other
alternative capacitors include OS-CON capacitors from
Sanyo.
⎜
⎟
⎠
f L
( )( )
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4(IMAX). In no case should
∆IL exceed 0.6(IMAX) due to limits imposed by IREV and
CA1. Remember the maximum ∆IL occurs at the maxi-
mum input voltage. In practice 10µH is the lowest value
recommended for use.
The output capacitor (C3) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
⎛
⎝
VBAT
VDCIN
⎞
0.29 V
1–
(
)
⎜
⎟
⎠
Lower charger currents generally call for larger inductor
values. Use Table 4 as a guide for selecting the correct
inductor value for your application.
BAT
IRMS
=
L1 f
( )( )
For example:
Table 4
MAX AVERAGE
CURRENT (A)
MINIMUM INDUCTOR
VDCIN = 19V, VBAT = 12.6V, L1 = 10µH, and
INPUT VOLTAGE (V)
VALUE (µH)
f = 300kHz, IRMS = 0.41A.
1
1
2
2
3
3
4
4
≤20
>20
≤20
>20
≤20
>20
≤20
>20
40 ±20%
56 ±20%
20 ±20%
30 ±20%
15 ±20%
20 ±20%
10 ±20%
15 ±20%
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
maybeaddedtoincreasebatteryimpedanceatthe300kHz
switching frequency. Switching ripple current splits be-
tween the battery and the output capacitor depending on
the ESR of the output capacitor and the battery imped-
ance. If the ESR of C3 is 0.2Ω and the battery impedance
40071f
16
LTC4007-1
W U U
APPLICATIO S I FOR ATIO
U
Charger Switching Power MOSFET
switch in nearly 100%. The term (1 + δ∆T) is generally
given for a MOSFET in the form of a normalized RDS(ON) vs
temperature curve, but δ = 0.005/°C can be used as an
approximationforlowvoltageMOSFETs.CRSS =QGD/∆VDS
is usually specified in the MOSFET characteristics. The
constant k = 2 can be used to estimate the contributions of
the two terms in the main switch dissipation equation.
and Diode Selection
Two external power MOSFETs must be selected for use
with the charger: a P-channel MOSFET for the top (main)
switch and an N-channel MOSFET for the bottom (syn-
chronous) switch.
The peak-to-peak gate drive levels are set internally. This
voltageistypically6V.Consequently,logic-levelthreshold
MOSFETs must be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; many of the logic
level MOSFETs are limited to 30V or less.
If the charger is to operate in low dropout mode or with a
high duty cycle greater than 85%, then the topside
P-channel efficiency generally improves with a larger
MOSFET.UsingasymmetricalMOSFETsmayachievecost
savings or efficiency gains.
SelectioncriteriaforthepowerMOSFETsincludethe“ON”
resistance RDS(ON), total gate capacitance QG, reverse
transfer capacitance CRSS, input voltage and maximum
output current. The charger is operating in continuous
mode at moderate to high currents so the duty cycles for
the top and bottom MOSFETs are given by:
The Schottky diode D1, shown in the Typical Application
on the back page, conducts during the dead-time between
the conduction of the two power MOSFETs. This prevents
thebodydiodeofthebottomMOSFETfromturningonand
storing charge during the dead-time, which could cost as
much as 1% in efficiency. A 1A Schottky is generally a
good size for 4A regulators due to the relatively small
average current. Larger diodes can result in additional
transition losses due to their larger junction capacitance.
Main Switch Duty Cycle = VOUT/VIN
Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN.
The MOSFET power dissipations at maximum output
current are given by:
The diode may be omitted if the efficiency loss can be
tolerated.
PMAIN = VOUT/VIN(IMAX)2(1 + δ∆T)RDS(ON)
+ k(VIN)2(IMAX)(CRSS)(fOSC
)
Calculating IC Power Dissipation
PSYNC = (VIN – VOUT)/VIN(IMAX)2(1 + δ∆T)RDS(ON)
The power dissipation of the LTC4007-1 is dependent
upon the gate charge of the top and bottom MOSFETs
(QG1 & QG2 respectively) The gate charge is determined
fromthemanufacturer’sdatasheetandisdependentupon
both the gate voltage swing and the drain voltage swing of
the MOSFET. Use 6V for the gate voltage swing and VDCIN
for the drain voltage swing.
Where δ∆T is the temperature dependency of RDS(ON) and
k is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the PMAIN equation
includesanadditionaltermfortransitionlosses,whichare
highest at high input voltages. For VIN < 20V the high
currentefficiencygenerallyimproveswithlargerMOSFETs,
while for VIN > 20V the transition losses rapidly increase
to the point that the use of a higher RDS(ON) device with
lower CRSS actually provides higher efficiency. The syn-
chronous MOSFET losses are greatest at high input volt-
age or during a short circuit when the duty cycle in this
PD = VDCIN • (fOSC (QG1 + QG2) + IQ)
Example:
VDCIN = 19V, fOSC = 345kHz, QG1 = QG2 = 15nC,
IQ = 5mA
PD = 292mW
40071f
17
LTC4007-1
W U U
U
APPLICATIO S I FOR ATIO
Adapter Limiting
input current limit tolerance and use that current to deter-
mine the resistor value.
An important feature of the LTC4007-1 is the ability to
automatically adjust charging current to a level which
avoids overloading the wall adapter. This allows the prod-
uct to operate at the same time that batteries are being
charged without complex load management algorithms.
Additionally, batteries will automatically be charged at the
maximum possible rate of which the adapter is capable.
R
CL = 100mV/ILIM
ILIM = Adapter Min Current –
(Adapter Min Current • 7%)
Table 5. Common R Resistor Values
CL
VALUE*
ADAPTER
RATING (A)
R
R
POWER
R
POWER
CL
(Ω) 1%
CL
CL
DISSIPATION (W)
RATING (W)
1.5
1.8
2
0.06
0.05
0.135
0.25
This feature is created by sensing total adapter output
current and adjusting charging current downward if a
preset adapter current limit is exceeded. True analog
control is used, with closed-loop feedback ensuring that
adapter load current remains within limits. Amplifier CL1
in Figure 8 senses the voltage across RCL, connected
betweentheCLPandCLNpins. Whenthisvoltageexceeds
100mV, the amplifier will override programmed charging
current to limit adapter current to 100mV/RCL. A lowpass
filter formed by 5kΩ and 15nF is required to eliminate
switchingnoise.Ifthecurrentlimitisnotused,CLPshould
be connected to CLN.
0.162
0.25
0.045
0.039
0.036
0.033
0.03
0.18
0.25
2.3
2.5
2.7
3
0.206
0.25
0.225
0.5
0.241
0.5
0.27
0.5
* Values shown above are rounded to nearest standard value.
As is often the case, the wall adapter will usually have at
least a +10% current limit margin and many times one can
simply set the adapter current limit value to the actual
adapter rating (see Table 5).
Note that the ICL pin will be asserted when the voltage
across RCL is 93mV, before the adapter limit regulation
threshold.
Designing the Thermistor Network
There are several networks that will yield the desired
function of voltage vs temperature needed for proper
operation of the thermistor. The simplest of these is the
voltage divider shown in Figure 9. Unfortunately, since the
HIGH/LOW comparator thresholds are fixed internally,
there is only one thermistor type that can be used in this
network; the thermistor must have a HIGH/LOW resis-
tance ratio of 1:7. If this happy circumstance is true for
LTC4007-1
100mV
CLP
+
15
–
15nF
5k
CL1
+
AC ADAPTER
INPUT
R
CL
*
CLN
V
IN
16
+
C
IN
you, then simply set R9 = RTH(LOW)
.
100mV
ADAPTER CURRENT LIMIT
*R
CL
=
40071 F08
LTC4007-1
R9
Figure 8. Adapter Current Limiting
NTC
7
C7
R
TH
Setting Input Current Limit
40071 F09
To set the input current limit, you need to know the
minimum wall adapter current rating. Subtract 7% for the
Figure 9. Voltage Divider Thermistor Network
40071f
18
LTC4007-1
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APPLICATIO S I FOR ATIO
U
Example #2: 100kΩ NTC
LTC4007-1
R9
NTC
7
TLOW = 5°C, THIGH = 50°C
C7
R9A
R
TH
RTH = 100k at 25°C,
RTH(LOW) = 272.05k at 5°C
RTH(HIGH) = 33.195k at 50°C
40071 F10
Figure 10. General Thermistor Network
R9 = 226.9k → 226k (nearest 1% value)
R9A = 1.365M → 1.37M (nearest 1% value)
If you are using a thermistor that doesn’t have a 1:7 HIGH/
LOW ratio, or you wish to set the HIGH/LOW limits to
different temperatures, then the more generic network in
Figure 10 should work.
Example #3: 22kΩ PTC
TLOW = 0°C, THIGH = 50°C
RTH = 22k at 25°C,
RTH(LOW) = 6.53k at 0°C
Once the thermistor, RTH, has been selected and the
thermistor value is known at the temperature limits, then
resistors R9 and R9A are given by:
R
TH(HIGH) = 61.4k at 50°C
R9 = 43.9k → 44.2k (nearest 1% value)
R9A = 154k
For NTC thermistors:
Sizing the Thermistor Hold Capacitor
R9 = 6 RTH(LOW) • RTH(HIGH)/(RTH(LOW) – RTH(HIGH)
)
During the hold interval, C7 must hold the voltage across
the thermistor relatively constant to avoid false readings.
A reasonable amount of ripple on NTC during the hold
interval is about 10mV to 15mV. Therefore, the value of C7
is given by:
R9A=6RTH(LOW) •RTH(HIGH)/(RTH(LOW) –7•RTH(HIGH)
Where RTH(LOW) > 7 • RTH(HIGH)
)
For PTC thermistors:
R9 = 6 RTH(LOW) • RTH(HIGH)/(RTH(HIGH) – RTH(LOW)
)
C7 = tHOLD/(R9/7 • –ln(1 – 8 • 15mV/4.5V))
= 10 • RRT • 17.5pF/(R9/7 • –ln(1 – 8 • 15mV/4.5V)
Example:
R9A =6RTH(LOW)•RTH(HIGH)/(RTH(HIGH)–7• RTH(LOW)
Where RTH(HIGH) > 7 • RTH(LOW)
)
Example #1: 10kΩ NTC with custom limits
R9 = 24.3k
RRT = 309k (~2 hour timer)
C7 = 0.57µF → 0.56µF (nearest value)
TLOW = 0°C, THIGH = 50°C
RTH = 10k at 25°C,
RTH(LOW) = 32.582k at 0°C
RTH(HIGH) = 3.635k at 50°C
R9 = 24.55k → 24.3k (nearest 1% value)
R9A = 99.6k → 100k (nearest 1% value)
40071f
19
LTC4007-1
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APPLICATIO S I FOR ATIO
Disabling the Thermistor Function
General Rules
If the thermistor is not needed, connecting a resistor
between DCIN and NTC will disable it. The resistor should
besizedtoprovideatleast10µAwiththeminimumvoltage
applied to DCIN and 10V at NTC. Do not exceed 30µA.
Generally,a301kresistorwillworkforDCINlessthan15V.
A 499k resistor is recommended for DCIN between 15V
and 24V.
1. Inputcapacitorsneedtobeplacedascloseaspossible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
2. ThecontrolICneedstobeclosetotheswitchingFET’s
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that con-
nect to the switching FET source pins. The IC can be
placedontheoppositesideofthePCBrelativetoabove.
Conditioning Depleted Batteries
Severely depleted batteries, with less than 3.25V/cell,
should be conditioned with a trickle charge to prevent
possible damage. This trickle charge is typically 10% of
the 1C rate of the battery. The LTC4007-1 can automati-
cally trickle charge depleted batteries using the circuit in
Figure 11. If the battery voltage is less than 3.25V/cell
(3.173V/cell if CHEM is low) then the LOBAT indicator will
be low and Q4 is off. This programs the charging current
withRPROG =R6+R14. Chargingcurrentisapproximately
300mA.Whenthecellvoltagebecomesgreaterthan3.25V
the LOBAT indicator goes high, Q4 shorts out R13, then
RPROG = R6. Charging current is then equal to 3A.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
4. Place the output current sense resistor right next to
the inductor output but oriented such that the IC’s
currentsensefeedbacktracesgoingtoresistorarenot
long. The feedback traces need to be routed together
asasinglepaironthesamelayeratanygiventimewith
smallest trace spacing possible. Locate any filter
componentonthesetracesnexttotheICandnotatthe
sense resistor location.
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electricalfieldradiationandhighfrequencyresonantprob-
lems,properlayoutofthecomponentsconnectedtotheIC
is essential. (See Figure 12.) Here is a PCB layout priority
list for proper layout. Layout the PCB using this specific
order.
5. Place output capacitors next to the sense resistor
output and ground.
6. Output capacitor ground connections need to feed
into same copper that connects to the input capacitor
ground before tying back into system ground.
40071f
20
LTC4007-1
W U U
APPLICATIO S I FOR ATIO
U
General Rules (Continued)
10. If possible, place all the parts listed above on the same
PCB layer.
7. Connection of switching ground to system ground or
internal ground plane should be single point. If the
system has an internal system ground plane, a good
way to do this is to cluster vias into a single star point
to make the connection.
11. Copper fills or pours are good for all power connec-
tionsexceptasnotedaboveinRule3.Youcanalsouse
copper planes on multiple layers in parallel too—this
helps with thermal management and lower trace in-
ductance improving EMI performance further.
8. Route analog ground as a trace tied back to IC ground
(analog ground pin if present) before connecting to
any other ground. Avoid using the system ground
plane. CAD trick: make analog ground a separate
ground net and use a 0Ω resistor to tie analog ground
to system ground.
12. For best current programming accuracy provide a
Kelvin connection from RSENSE to CSP and BAT. See
Figure 12 as an example.
It is important to keep the parasitic capacitance on the RT,
CSP and BAT pins to a minimum. The traces connecting
these pins to their respective resistors should be as short
as possible.
9. A good rule of thumb for via count for a given high
current path is to use 0.5A per via. Be consistent.
40071f
21
LTC4007-1
W U U
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APPLICATIO S I FOR ATIO
Q3
INPUT SWITCH
DCIN
0V TO 20V
3A
C1
R1
4.99k
1%
0.1µF
3C4C
DCIN
INFET
CLP
V
*
*
LOGIC
R
CL
R10
R11
R12
0.033Ω
C4
15nF
CHEM
LOBAT
100k 100k 100k
1%
SYSTEM
LOAD
LOBAT
C2
20µF
LTC4007-1
I
I
CLN
CL
CL
R
SENSE
L1
0.033Ω
ACP
SHDN
FAULT
CHG
ACP
TGATE
BGATE
PGND
CSP
Q1
Q2
15µH 3A
1%
BAT
SHDN
FAULT
CHG
D1
C3
R4
3.01k
1%
20µF
FLAG
FLAG
NTC
BAT
R9 32.4k 1%
R5 3.01k 1%
PROG
ITH
R
T
MONITOR
(CHARGING
CURRENT
MONITOR)
C7
0.47µF
R6
26.7k
1%
R7
*PIN OPEN
D1: MBRM140T3
Q1: Si4431BDY
Q2: FDC645N
Q4: 2N7002 OR BSS138
GND
THERMISTOR
C5
6.04k
0.0047µF
1%
R
T
309k
1%
TIMING RESISTOR
(~2 HOURS)
R14
52.3k
1%
C6
0.12µF
Q4
40071 F11
Figure 11. Circuit Application (16.8V/3A) to Automatically Trickle Charge Depleted Batteries
40071f
22
LTC4007-1
W U U
APPLICATIO S I FOR ATIO
U
SWITCH NODE
L1
DIRECTION OF CHARGING CURRENT
V
BAT
HIGH
FREQUENCY
CIRCULATING
PATH
R
SENSE
C2
D1
V
IN
C3
BAT
40071 F13
CSP
BAT
40071 F12
Figure 12. High Speed Switching Path
Figure 13. Kelvin Sensing of Charging Current
U
PACKAGE DESCRIPTION
UFD Package
24-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1696)
2.65 ± 0.10
PIN 1 NOTCH
R = 0.30 TYP
(2 SIDES)
R = 0.115
TYP
0.75 ± 0.05
4.00 ± 0.10
(2 SIDES)
23 24
0.70 ±0.05
0.40 ± 0.05
PIN 1
TOP MARK
(NOTE 6)
4.50 ± 0.05
3.10 ± 0.05
1
2
5.00 ± 0.10
(2 SIDES)
3.65 ± 0.10
(2 SIDES)
2.65 ± 0.05
(2 SIDES)
0.25 ±0.05
0.50 BSC
(UFD25) QFN 0504
0.25 ± 0.05
0.50 BSC
3.65 ± 0.05
(2 SIDES)
4.10 ± 0.05
5.50 ± 0.05
0.200 REF
PACKAGE OUTLINE
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
40071f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC4007-1
U
TYPICAL APPLICATIO
12.6V, 4A Li-Ion Battery Charger
Q3
INPUT SWITCH
DCIN
0V TO 20V
3A
C1
R1
0.1µF
4.99k
1%
3C4C
DCIN
INFET
CLP
V
LOGIC
R
CL
R10
R11
R12
0.033Ω
C4
15nF
CHEM
*
100k 100k 100k
1%
SYSTEM
LOAD
LOBAT
LOBAT
C2
20µF
LTC4007-1
I
I
CLN
CL
CL
R
SENSE
L1
10µH 4A
0.025Ω
ACP
SHDN
FAULT
CHG
ACP
TGATE
BGATE
PGND
CSP
Q1
Q2
1%
BAT
SHDN
FAULT
CHG
D1
C3
20µF
R4
3.01k 1%
FLAG
FLAG
NTC
BAT
R9 32.4k 1%
R5 3.01k 1%
PROG
ITH
CHARGING
CURRENT
MONITOR
R
T
THERMISTOR
C7
0.47µF
C5
0.0047µF
R7
10k
NTC
GND
6.04k
*PIN OPEN
1%
C6
0.12µF
R
D1: MBRS130T3
Q1: Si4431BDY
Q2: FDC645N
R
PROG
26.7k
1%
RT
TIMING RESISTOR
(~2 HOURS)
309k
1%
40071 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT®1511
Constant-Current/Constant-Voltage 3A Battery
Charger with Input Current Limiting
High Efficiency Current Mode PWM with 4A Internal Switch
LT1513
SEPIC Constant- or Programmable-Current/
Constant-Voltage Battery Charger
Charger Input Voltage May Be Higher, Equal to or Lower Than Battery Voltage;
Charges Any Number of Cells Up to 20V, 500kHz Switching Frequency
LT1571
1.5A Switching Charger
1- or 2-Cell Li-Ion, 500kHz or 200kHz Switching Frequency, Termination Flag
LTC1628-PG
LTC1709
2-Phase, Dual Synchronous Step-Down Controller
Minimizes C and C , Power Good Output, 3.5V ≤ V ≤ 36V
IN OUT IN
2-Phase, Dual Synchronous Step-Down Controller
with VID
Up to 42A Output, Minimum C and C , Uses Smallest Components for
IN OUT
Intel and AMD Processors
LT1769
2A Switching Battery Charger
Constant-Current/Constant-Voltage Switching Regulator, Input Current
Limiting Maximizes Charge Current
LTC1778
LTC1960
LTC3711
LTC4006
Wide Operating Range, No R
Step-Down Controller
Synchronous
2% to 90% Duty Cycle at 200kHz, Stable with Ceramic C
OUT
SENSE
Dual Battery Charger/Selector with SPI Interface
Simultaneous Charge or Discharge of Two Batteries, DAC Programmable
Current and Voltage, Input Current Limiting Maximizes Charge Current
No R
TM Synchronous Step-Down Controller
3.5V ≤ V ≤ 36V, 0.925V ≤ V
≤ 2V, for Transmeta, AMD and Intel
SENSE
with VID
IN
OUT
Mobile Processors
Small, High Efficiency, Fixed Voltage,
Lithium-Ion Battery Charger
Constant-Current/Constant-Voltage Switching Regulator with Termination
Timer, AC Adapter Current Limit and Thermistor Sensor in a Small
16-Pin Package
LTC4007
LTC4008
LTC4100
4A High Efficiency, Standalone Li-Ion Battery Charger Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit
and Thermistor Sensor, 16-Pin Narrow SSOP Package
High Efficiency, Programmable Voltage/Current
Battery Charger
Constant-Current/Constant-Voltage Switching Regulator, Resistor Voltage/
Current Programming, AC Adapter Current Limit and Thermistor Sensor
Smart Battery Charger Controller
100% Compliant SMBus 1.1 Support, V : 6.4V to 26V, V
= 0.5V,
IN
DROPOUT
High Efficiency Synchronous Buck Charger
No R
is a trademark of Linear Technology Corporation.
SENSE
40071f
LT/TP 1005 500 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
© LINEAR TECHNOLOGY CORPORATION 2005
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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