LTC4210-4 [Linear]
Hot Swap Controller in 6-Lead SOT-23 Package; 在6引脚SOT- 23封装热插拔控制器
| 型号： | LTC4210-4 |
| 厂家： | 
Linear |
| 描述： | Hot Swap Controller in 6-Lead SOT-23 Package |
| 文件： | 总16页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4210-3/LTC4210-4
Hot Swap Controller in
6-Lead SOT-23 Package
U
FEATURES
DESCRIPTIO
■
Allows Safe Board Insertion and Removal
TheLTC®4210-3/LTC4210-4isa6-pinSOT-23HotSwapTM
controller that allows a board to be safely inserted and
removed from a live backplane. An internal high side
switch driver controls the GATE of an external N-channel
MOSFET for a supply voltage ranging from 2.7V to 7V. The
LTC4210 provides the initial timing cycle and allows the
GATE to be ramped up at an adjustable rate.
from a Live Backplane
■
Adjustable Analog Current Limit
with Circuit Breaker
■
Fast Response Limits Peak Fault Current
■
Automatic Retry or Latch Off On Current Fault
■
Adjustable Supply Voltage Power-Up Rate
■
High Side Drive for External MOSFET Switch
The LTC4210 features a fast current limit loop providing
active current limiting together with a circuit breaker
timer. ThesignalattheONpinturnsthepartonandoffand
is also used for the reset function.
■
Controls Supply Voltages from 2.7V to 7V
■
Undervoltage Lockout
■
Adjustable Overvoltage Protection
Low Profile (1mm) SOT-23 (ThinSOTTM) Package
■
The LTC4210-3 retries on overcurrent fault and the
LTC4210-4 latches off on an overcurrent fault.
U
APPLICATIO S
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
ThinSOT and Hot Swap are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
Hot Board Insertion
■
Electronic Circuit Breaker
■
Industrial High Side Switch/Circuit Breaker
U
TYPICAL APPLICATIO
Single Channel 5V Hot Swap Controller
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
(FEMALE)
(MALE)
R
Q1
Si4410DY
Power-Up Sequence
SENSE
0.01Ω
V
5V
4A
OUT
LONG
V
IN
C
= 470µF
5V
LOAD
+
V
10Ω
0.1µF
ON
(2V/DIV)
470µF
Z1
OPTIONAL
100Ω
V
TIMER
(1V/DIV)
V
CC
SENSE
GATE
20k
SHORT
LONG
100Ω
0.01µF
LTC4210-3
ON
V
OUT
10k
(5V/DIV)
TIMER
GND
I
0.22µF
OUT
(0.5A/DIV)
GND
GND
4210 TA01
Z1: ISMA10A OR SMAJ10A
4210 TA02
10ms/DIV
421034fa
1
LTC4210-3/LTC4210-4
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage (VCC) ............................................... 17V
Input Voltage (SENSE, TIMER) .. –0.3V to (VCC + 0.3V)
Input Voltage (ON)..................................... –0.3V to 17V
Output Voltage (GATE) ........ Internally Limited (Note 3)
Operating Temperature Range
LTC4210-3C/LTC4210-4C ....................... 0°C to 70°C
LTC4210-3I/LTC4210-4I .................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
LTC4210-3CS6
LTC4210-4CS6
LTC4210-3IS6
LTC4210-4IS6
TIMER 1
GND 2
ON 3
6 V
CC
5 SENSE
4 GATE
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
S6 PART MARKING
LTCPJ
LTCPM
LTCPK
LTCPN
TJMAX = 125°C, θJA = 230°C/ W
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult factory for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
CC
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T = 25°C. V = 5V, unless otherwise noted. (Note 2)
A
SYMBOL
PARAMETER
CONDITIONS
Supply Voltage
MIN
TYP
MAX
7.0
UNITS
V
V
●
●
●
2.7
CC
I
V
CC
V
CC
V
CC
Supply Current
0.75
2.5
100
0
3.5
mA
V
CC
V
V
Undervoltage Lockout Release
Undervoltage Lockout Hysteresis
V
CC
Rising
2.2
2.65
LKOR
mV
µA
µA
mV
µA
mA
LKOHYST
INON
I
I
ON Pin Input Current
●
●
●
●
–10
–10
44
10
10
SENSE Pin Input Current
Circuit Breaker Trip Voltage
GATE Pin Pull-Up Current
GATE Pin Pull-Down Current
V
V
V
= V
CC
5
INSENSE
SENSE
V
= (V – V
)
50
56
CB
CB
CC
SENSE
I
I
= 0V
–5
–10
25
–15
GATEUP
GATEDN
GATE
V
V
V
= 1.5V, V
= 3V or
TIMER
ON
CC
GATE
= 3V or
= 0V, V
GATE
– V
= 100mV, V
= 3V
SENSE
GATE
∆V
External N-Channel Gate Drive
GATE Pin Voltage
V
V
V
V
– V , V = 2.7V
●
●
●
●
4.0
4.5
5.0
5.0
6.5
7.5
8.5
7.0
8
V
V
V
V
GATE
GATE
GATE
GATE
GATE
CC CC
– V , V = 3V
10
9.7
8.0
CC CC
– V , V = 3.3V
CC CC
– V , V = 5V
CC CC
V
V
CC
V
CC
V
CC
V
CC
= 2.7V
●
●
●
●
6.7
7.5
9.2
10.7
13.0
13.0
13.0
V
V
V
V
GATE
= 3.0V
10.5
11.8
12.0
= 3.3V
= 5.0V
8.3
10.0
I
I
TIMER Pin Pull-Up Current
TIMER Pin Pull-Down Current
TIMER Pin Threshold
Initial Cycle, V
= 1V
●
●
–2
–5
–8.5
µA
µA
µA
µA
V
V
TIMERUP
TIMERDN
TIMER
During Current Fault Condition, V
= 1V
= 1V
–25
–60
–100
TIMER
After Current Fault Disappears, V
Under Normal Conditions, V
●
2
100
3.5
TIMER
TIMER
= 1V
V
High Threshold, TIMER Rising
Low Threshold, TIMER Falling
●
●
1.22
0.15
1.3
0.2
1.38
0.25
TIMER
V
V
V
TIMER Low Threshold Hysteresis
ON Pin Threshold
100
1.3
80
mV
V
TMRHYST
ON
ON Threshold, ON Rising
●
1.22
1.38
ON Pin Threshold Hysteresis
mV
ONHYST
421034fa
2
LTC4210-3/LTC4210-4
ELECTRICAL CHARACTERISTICS
The
CC
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T = 25°C. V = 5V, unless otherwise noted. (Note 2)
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1
MAX
UNITS
µs
t
t
t
Turn-Off Time (TIMER Rise to GATE Fall)
Turn-Off Time (ON Fall to GATE Fall)
V
V
V
= 0V to 2V Step, V = V = 5V
OFF(TMRHIGH)
OFF(ONLOW)
OFF(VCCLOW)
TIMER CC ON
= 5V to 0V Step, V = 5V
30
30
µs
µs
ON
CC
CC
Turn-Off Time (V Fall to IC Reset)
= 5V to 2V Step, V = 5V
CC
ON
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: An internal Zener clamped the GATE pin to a typical voltage of
12V. External overdrive of the GATE pin beyond the internal Zener voltage
may damage the device. Without a limiting resistor, the GATE capacitance
must be <0.15µF at maximum V
.
CC
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Undervoltage Lockout Threshold
vs Temperature
Supply Current vs Supply Voltage
Supply Current vs Temperature
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.65
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
T
= 25°C
A
S
V
= 5V
V
V
RISING
CC
CC
FALLING
V
V
= 5V
CC
CC
= 3V
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
SUPPLY VOLTAGE (V)
–75 –50 –25
0
25 50 75 100 125 150
–75 –50 –25
0
25 50
75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
LTC4210 • G01
LTC4210 • G02
LTC4210 • G03
V
GATE
vs Supply Voltage
V
vs Temperature
GATE
I
vs Supply Voltage
GATEUP
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
–8.0
–8.5
TA = 25°C
V
= 5V
= 3V
–9.0
CC
–9.5
–10.0
–10.5
–11
V
CC
8
8
–11.5
–12.0
7
7
6
6
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
SUPPLY VOLTAGE (V)
–75 –50 –25
0
25 50 75 100 125 150
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
LTC4210 • G04
LTC4210 • G05
LTC4210 • G06
421034fa
3
LTC4210-3/LTC4210-4
U W
TYPICAL PERFOR A CE CHARACTERISTICS
∆V
vs Supply Voltage
I
vs Temperature
∆V
vs Temperature
GATE
GATEUP
GATE
12
11
10
9
12
11
10
9
–8.0
–8.5
–9.0
V
V
= 5V
= 3V
CC
–9.5
8
8
7
7
–10.0
–10.5
–11
CC
V
V
= 3V
= 5V
CC
CC
6
6
5
5
4
4
–11.5
–12.0
3
3
2
2
25 50
2.5 3.0 3.5 4.0
5.0
6.0 6.5 7.0
–75 –50 –25
0
50
100 125 150
75
–75 –50 –25
0
75 100 125 150
4.5
5.5
25
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
LTC4210 • G07
LTC4210 • G08
LTC4210 • G09
I
(In Initial Cycle)
I
(In Initial Cycle)
I
(During Circuit Breaker
TIMERUP
TIMERUP
TIMERUP
vs Supply Voltage
vs Temperature
Delay) vs Supply Voltage
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
TA = 25°C
V
= 5V
TA = 25 °C
CC
–75 –50 –25
0
25 50 75 100 125 150
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
SUPPLY VOLTAGE (V)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
LTC4210 • G11
LTC4210 • G12
LTC4210 • G10
I
(In Cool-Off Cycle)
I
(In Cool-Off Cycle)
I
(During Circuit Breaker
TIMERDN
TIMERDN
TIMERUP
vs Temperature
vs Supply Voltage
Delay) vs Temperature
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= 5V
TA = 25°C
V
= 5V
CC
CC
25 50
SUPPLY VOLTAGE (V)
2.5 3.0 3.5 4.0
5.0
6.0 6.5 7.0
–75 –50 –25
0
50
100 125 150
75
TEMPERATURE (°C)
–75 –50 –25
0
75 100 125 150
4.5
5.5
25
SUPPLY VOLTAGE (V)
LTC4210 • G13
LTC4210 • G14
LTC4210 • G15
421034fa
4
LTC4210-3/LTC4210-4
U W
TYPICAL PERFOR A CE CHARACTERISTICS
TIMER High Threshold
vs Temperature
TIMER High Threshold
vs Supply Voltage
TIMER Low Threshold
vs Supply Voltage
0.24
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
TA = 25°C
V
= 5V
TA = 25°C
CC
0.23
0.22
0.21
0.20
0.19
0.18
0.17
0.16
4.5 5.0
25 50
TEMPERATURE (°C)
4.5 5.0
5.5 6.0 6.5 7.0
2.5 3.0 3.5 4.0
5.5 6.0 6.5 7.0
–75 –50 –25
0
75 100 125 150
2.5 3.0 3.5 4.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
LTC4210 • G16
LTC4210 • G17
LTC4210 • G18
TIMER Low Threshold
vs Temperature
ON Pin Threshold
vs Supply Voltage
ON Pin Threshold
vs Temperature
0.24
0.23
0.22
0.21
0.20
0.19
0.18
0.17
0.16
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
V
CC
= 5V
TA = 25°C
V
= 5V
CC
HIGH THRESHOLD
HIGH THRESHOLD
LOW THRESHOLD
LOW THRESHOLD
25 50
4.5 5.0
25 50
0
TEMPERATURE (°C)
–75 –50 –25
0
75 100 125 150
2.5 3.0 3.5 4.0
5.5 6.0 6.5 7.0
–75 –50 –25
75 100 125 150
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
LTC4210 • G19
LTC4210 • G20
LTC4210 • G21
t
vs Supply Voltage
t
vs Temperature
OFF(ONLOW)
OFF(ONLOW)
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
TA = 25°C
v
= 5v
= 3v
cc
cc
v
0
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
SUPPLY VOLTAGE (V)
–75 –50 –25
0
25 50 75 100 125 150
TEMPERATURE (°C)
LTC4210 • G22
LTC4210 • G23
421034fa
5
LTC4210-3/LTC4210-4
U W
TYPICAL PERFOR A CE CHARACTERISTICS
V
vs Supply Voltage
CB
V
CB
vs Temperature
58
56
54
52
50
48
46
44
42
58
56
54
52
50
48
46
44
42
TA = 25°C
V
= 5V
CC
4.5 5.0
25 50
TEMPERATURE (°C)
2.5 3.0 3.5 4.0
5.5 6.0 6.5 7.0
–75 –50 –25
0
75 100 125 150
SUPPLY VOLTAGE (V)
LTC4210 • G24
LTC4210 • G25
U
U
U
PI FU CTIO S
TIMER (Pin 1): Timer Input Pin. An external capacitor
CTIMERsetsa272.9ms/µFinitialtimingdelayanda21.7ms/
µF circuit breaker delay. The GATE pin turns off whenever
the TIMER pin is pulled beyond the COMP2 threshold,
such as for overvoltage detection with an external zener.
(EA) controls the external MOSFET to maintain a constant
load current. An external R-C compensation network
should be connected to this pin for current limit loop
stability.
SENSE (Pin 5): Current Limit Sense Input Pin. A sense
resistor between the VCC and SENSE pins sets the analog
current limit. In overload, the EA controls the external
MOSFET gate to maintain the SENSE pin voltage at 50mV
below VCC. When the EA is maintaining current limit, the
TIMER circuit breaker mode is activated. The current limit
loop/circuit breaker mode can be disabled by connecting
the SENSE pin to the VCC pin.
GND (Pin 2): Ground Pin.
ON (Pin 3): ON Input Pin. The ON pin comparator has a
low-to-high threshold of 1.3V with 80mV hysteresis and a
glitch filter. When the ON pin is low, the LTC4210 is reset.
When the ON pin goes high, the GATE turns on after the
initial timing cycle.
GATE (Pin 4): GATE Output Pin. This pin is the high side
gate drive of an external N-channel MOSFET. An internal
charge pump provides a 10µA pull-up current with Zener
clamps to VCC and ground. In overload, the error amplifier
VCC (Pin 6): Positive Supply Input Pin. The operating
supply voltage range is between 2.7V to 7V. An undervolt-
age lockout (UVLO) circuit with a glitch filter resets the
LTC4210 when a low supply voltage is detected.
421034fa
6
LTC4210-3/LTC4210-4
W
BLOCK DIAGRA
6
5
V
SENSE
CC
+
50mV
–
INITIAL UP/LATCH OFF
CURRENT LIMIT
–
UVLO
+
EA
5µA
60µA
GLITCH
FILTER
0.2V
+
COMP1
CHARGE
PUMP
–
TIMER
1
LOGIC
Z1
12V
10µA
4k
+
GATE
4
COMP2
SHUTDOWN
Z2
26V
M5
1.3V
–
INITIAL DOWN/NORMAL
GLITCH
FILTER
2µA
100µA
GND
2
COOL OFF
COMP3
+
–
ON
1.3V
3
4210 BD
W U U
U
APPLICATIO S I FOR ATIO
Hot Circuit Insertion
Overview
When circuit boards are inserted into live backplanes, the
supply bypass capacitors can draw large transient cur-
rents from the backplane power bus as they charge. Such
transient currents can cause permanent damage to con-
nector pins, glitches on the system supply or reset other
boards in the system.
The LTC4210-3/LTC4210-4 is designed to operate over a
range of supplies from 2.7V to 7V. Upon insertion, an
undervoltage lockout circuit determines if sufficient sup-
plyvoltageispresent. WhentheONpingoeshighaninitial
timing cycle assures that the board is fully seated in the
backplane before the MOSFET is turned on. A single timer
capacitor sets the periods for all of the timer functions.
After the initial timing cycle the LTC4210 can either start
up in current limit or with a lower load current. Once the
external MOSFET is fully enhanced and the supply has
rampedup,theLTC4210monitorstheloadcurrentthrough
an external sense resistor. Overcurrent faults are actively
limited to 50mV/RSENSE for a specified circuit breaker
timer limit. The LTC4210-3 will automatically retry after a
current limit fault while the LTC4210-4 latches off. The
LTC4210-3 timer function limits the retry duty cycle to
The LTC4210 is designed to turn a printed circuit board’s
supply voltage ON and OFF in a controlled manner, allow-
ing the circuit board to be safely inserted into or removed
from a live backplane. The LTC4210 can reside either on
the backplane or on the daughter board for hot circuit
insertion applications.
3.8% for MOSFET cooling.
421034fa
7
LTC4210-3/LTC4210-4
W U U
U
APPLICATIO S I FOR ATIO
Undervoltage Lockout
Current Limit Circuit Breaker Function
An internal undervoltage lockout (UVLO) circuit resets the
LTC4210 if the VCC supply is too low for normal operation.
The UVLO has a low-to-high threshold of 2.5V, a 100mV
hysteresis and a high-to-low glitch filter of 30µs. Above
2.5V supply voltage, the LTC4210 will start if the ON pin
conditions are met. A short supply dip below 2.4V for less
than 30µs is ignored to allow for bus supply transients.
The LTC4210 features a current limiting circuit breaker
instead of a traditional comparator circuit breaker. When
there is a sudden load current surge, such as a low
impedance fault, the bus supply voltage can drop signifi-
cantly to a point where the power to an adjacent card is
affected, causing system malfunctions. The LTC4210 fast
response error amplifier (EA) instantly limits current by
reducing the external MOSFET GATE pin voltage. This
minimizes the bus supply voltage drop and permits power
budgeting and fault isolation without affecting neighbor-
ing cards. A compensation circuit should be connected to
the GATE pin for current limit loop stability.
ON Function
The ON pin is the input to a comparator which has a low-
to-high threshold of 1.3V, an 80mV hysteresis and a high-
to-lowglitchfilterof30µs. AlowinputontheONpinresets
the LTC4210 TIMER status and turns off the external
MOSFET by pulling the GATE pin to ground. A low-to-high
transition on the ON pin starts an initial cycle followed by
a start-up cycle. A 10k pull-up resistor connecting the ON
pintothesupplyisrecommended.The10kresistorshunts
any potential static charge on the backplane and reduces
the overvoltage stress at the ON pin during live insertion.
Alternatively, an external resistor divider at the ON pin can
be used to program an undervoltage lockout value higher
than the internal UVLO circuit. An RC filter can be added at
theONpintoincreasethedelaytimeatcardinsertionifthe
internal glitch filter delay is insufficient.
Sense Resistor Consideration
The nominal fault current limit is determined by a sense
resistor connected between VCC and the SENSE pin as
given by Equation 1.
V
50mV
RSENSE(NOM) RSENSE(NOM)
CB(NOM)
ILIMIT(NOM)
=
=
(1)
The power rating of the sense resistor should be rated at
the fault current level.
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4210
VCC and SENSE pins are strongly recommended. The
drawing in Figure 1 illustrates the connections between
the LTC4210 and the sense resistor. PCB layout should be
balanced and symmetrical to minimize wiring errors. In
addition, the PCB layout for the sense resistor should
includegoodthermalmanagementtechniquesforoptimal
sense resistor power dissipation.
GATE Function
During hot insertion of the PCB, an abrupt application of
supply voltage charges the external MOSFET drain/gate
capacitance. This can cause an unwanted gate voltage
spike. An internal proprietary circuit holds GATE low
before the internal circuitry wakes up. This reduces the
MOSFET current surges substantially at insertion. The
GATE pin is held low in reset mode and during the initial
timingcycle. Inthestart-upcycletheGATEpinispulledup
by a 10µA current source. During an overcurrent fault
condition, the error amplifier servoes the GATE pin to
maintain a constant current to the load until the circuit
breaker trips. When the circuit breaker trips, the GATE pin
shuts down abruptly.
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
SENSE RESISTOR
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
W
4210 F01
TO
CC
TO
SENSE
V
Figure 1. Making PCB Connections to the Sense Resistor
421034fa
8
LTC4210-3/LTC4210-4
W U U
APPLICATIO S I FOR ATIO
U
Calculating Current Limit
withCC =47nFandRC =100Ω. Despitethewirelength, the
general rule for AC stability required is CC ≥ 8nF and RC ≤
1kΩ.
For a selected RSENSE, the nominal load current is given by
Equation 1. The minimum load current is given by
Equation 2:
Method 2
V
The compensation network in Figure 2b is similar to the
circuitry used in method 1 but with an additional gate
resistor RG. The RG resistor helps to minimize high
frequencyparasiticoscillationsfrequentlyassociatedwith
the power MOSFET. In some applications, the user may
find that RG helps in short-circuit transient recovery as
well. However, too large of an RG value will slow down the
turn-off time. The recommended RG range is between 5Ω
and 500Ω. RG limits the current flow into the GATE pin’s
internal zener clamp during transient events. The recom-
mended RC and CC values are the same as method 1. The
parasiticcompensationcapacitorCPisrequiredwhen0.2µF
< load capacitance CL < 9µF, otherwise it is optional.
44mV
CB(MIN)
ILIMIT(MIN)
=
=
(2)
RSENSE(MAX) RSENSE(MAX)
where
RSENSE(MAX) = RSENSE • 1+
RTOL
100
⎛
⎝
⎞
⎜
⎟
⎠
The maximum load current is given by Equation 3:
V
56mV
RSENSE(MIN) RSENSE(MIN)
CB(MAX)
ILIMIT(MAX)
where
RSENSE(MIN) = RSENSE • 1–
=
=
(3)
R
Q1
Si4410DY
RTOL
100
⎛
⎞
SENSE
0.007Ω
⎜
⎟
⎠
V
IN
5V
⎝
V
OUT
+
6
5
C
L
V
SENSE
LTC4210*
GATE
If a 7mΩ sense resistor with ±1% tolerance is used for
CC
current limiting, the nominal current limit is 7.14A.
4
From Equations 2 and 3, I
LIMIT(MAX)
= 6.22A and
LIMIT(MIN)
R
C
100Ω
C
I
=8.08A.Forproperoperation,theminimum
C
10nF
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
**USE C IF 0.2µF < C < 9µF,
OTHERWISE NOT REQUIRED
current limit must exceed the circuit maximum operat-
(2a)
Method 1
ing load current with margin. The sense resistor power
P
L
2
rating must exceed V
/R
.
CB(MAX)
SENSE(MIN)
R
Q1
SENSE
0.007Ω
Si4410DY
V
IN
V
OUT
Frequency Compensation
12V
+
6
5
C
L
A compensation circuit should be connected to the GATE
pin for current limit loop stability.
V
SENSE
LTC4210*
GATE
CC
C **
R
G
200Ω
P
2.2nF
4
R
C
100Ω
C
Method 1
C
10nF
The simplest frequency compensation network consists
of RC and CC (Figure 2a). The total GATE capacitance is:
(2b)
Method 2
4210 F02
C
GATE = CISS + CC
(4)
Figure 2. Frequency Compensation
Generally, the compensation value in Figure 2a is suffi-
cient for a pair of input wires less than a foot in length.
Applications with longer input wires may require the RC or
CC value to be increased for better fault transient perfor-
mance. For a pair of three foot input wires, users can start
Parasitic MOSFET Oscillation
There are two possible parasitic oscillations when the
MOSFET operates as a source follower when ramping at
421034fa
9
LTC4210-3/LTC4210-4
W U U
U
APPLICATIO S I FOR ATIO
power-up or during current limiting. The first type of oscil- pin is low. GATE is pulled low and the TIMER pin is pulled
lation occurs at high frequencies, typically above 1MHz. low with a 100µA source. At time point 2, the short pin
ThishighfrequencyoscillationiseasilydampedwithRG as makes contact and ON is pulled high. At this instant, a
mentioned in method 2.
start-up check requires that the supply voltage be above
UVLO,theONpinbeabove1.3VandtheTIMERpinvoltage
be less than 0.2V. When these three conditions are ful-
filled, the initial cycle begins and the TIMER pin is pulled
high with 5µA. At time point 3, the TIMER reaches the
COMP2 threshold and the first portion of the initial cycle
ends. The 100µA current source then pulls down the
TIMER pin until it reaches 0.2V at time point 4. The initial
cycle delay (time point 2 to time point 4) is related to
The second type of oscillation occurs at frequencies
between 200kHz and 800kHz due to the load capacitance
being between 0.2µF and 9µF, the presence of RG and RC
resistance, the absence of a drain bypass capacitor, a
combinationofbuswiringinductanceandbussupplyoutput
impedance. There are several ways to prevent this second
type of oscillation. The simplest way is to avoid load
capacitance below 10µF™, the second choice is connect-
ing an external CP > 1.5nF.
C
TIMER by equation:
tINITIAL ≈ 272.9 • CTIMER ms/µF
(5)
Whichever method of compensation is used, board level
short-circuit testing is highly recommended as board
layoutcanaffecttransientperformance. Besidefrequency
When the initial cycle terminates, a start-up cycle is
activated and the GATE pin ramps high. The TIMER pin
compensation, the total gate capacitance CGATE also continues to be pulled down towards ground.
determines the GATE start-up as in Equation 6. The CGATE
should be kept below 0.15µF at high supply operation as
1
2
3 4 5
6
7
thecapacitiveenergy(0.5•CGATE •VGATE2 )isdischarged
by the LTC4210 internal pull-down transistor. This pre-
vents the internal pull-down transistor from overheating
when the GATE turns off and/or is serving during current
limiting.
>2.5V
V
IN
>1.3V
V
ON
Timer Function
COMP2
100µA
COMP1
V
TIMER
The TIMER pin handles several key functions with an
external capacitor, CTIMER. There are two comparator
thresholds: COMP1 (0.2V) and COMP2 (1.3V). The four
timing current sources are:
5µA
10µA
V
GATE
V
TH
DISCHARGE
BY LOAD
V
OUT
5µA pull-up
4210 F03
60µA pull-up
2µA pull-down
100µA pull-down
RESET
MODE
INITIAL
CYCLE
START-UP
CYCLE
NORMAL
CYCLE
Figure 3. Normal Operating Sequence
The100µAisanonidealcurrentsourceapproximatinga7k
resistor below 0.4V.
Start-Up Cycle Without Current Limit
Initial Timing Cycle
The GATE is released with a 10µA pull-up at time point 4
of Figure 3. At time point 5, GATE reaches the external
MOSFET threshold VTH and VOUT starts to follow the
Whenthecardisbeinginsertedintothebusconnector, the
long pins mate first which brings up the supply VIN at time
point1ofFigure3. TheLTC4210isinresetmodeastheON
421034fa
10
LTC4210-3/LTC4210-4
W U U
APPLICATIO S I FOR ATIO
U
GATE ramp up. If the RSENSE current is below the current
limit, the GATE ramps at a constant rate of:
Gate Start-Up Time
The start-up time without current limit is given by:
∆VGATE IGATE
VTH + V
IGATE
IN
=
(6)
tSTARTUP = CGATE
tSTARTUP = CGATE
•
•
(10)
∆T
CGATE
VTH
IGATE
V
IGATE
IN
where CGATE is the total capacitance at the GATE pin.
+ CGATE
•
The current through RSENSE can be divided into two
components; ICLOAD due to the total load capacitance
(CLOAD) and ILOAD due to the noncapacitive load elements.
The capacitive load typically dominates.
1
2
3
4
5
5A 5B
6
7
>2.5V
V
IN
For a successful start-up without current limit, IRSENSE
ILIMIT
<
>1.3V
:
V
ON
IRSENSE = ICLOAD + ILOAD < ILIMIT
COMP2
100µA
2µA
60µA
V
TIMER
∆VOUT
∆T
⎛
⎞
COMP1
100µA
5µA
IRSENSE = CLOAD
•
+ ILOAD < ILIMIT
10µA
(7)
⎜
⎝
⎟
⎠
<10µA
10µA
V
GATE
Due to the voltage follower configuration, the VOUT ramp
rate approximately tracks VGATE
V
TH
DISCHARGE
BY LOAD
:
V
OUT
∆VOUT ICLOAD ∆VGATE IGATE
REGULATED AT 50mV/R
SENSE
=
≈
=
(8)
∆T
CLOAD
∆T
CGATE
I
RSENSE
4210 F04
RESET
MODE
INITIAL
CYCLE
START-UP
CYCLE
NORMAL
CYCLE
At time point 6, VOUT is approximately VIN but GATE ramp-
up continues until it reaches a maximum voltage. This
maximum voltage is determined either by the charge
pump or the internal clamp.
Figure 4. Operating Sequence with
Current Limiting at Start-Up Cycle
Start-Up Cycle With Current Limit
During current limiting, the second term in Equation 10 is
partly modified from C • V /I to C
IN CLOAD
•
LOAD
If the duration of the current limit is brief during start-up
(Figure 4) and it did not last beyond the circuit breaker
function time out, the GATE behaves the same as in start-
up without current limit except for the time interval be-
tweentimepoint5Aandtimepoint5B. Theservoamplifier
limits IRSENSE by decreasing the IGATE current (<10µA).
GATE
IN GATE
V /I
. The start-up time is now given by:
VTH
IGATE
VTH
V
IN
ICLOAD
tSTARTUP = CGATE
= CGA
•
•
+ CLOAD
+ CLOAD
•
•
(11)
V
IN
TE
IGATE
IRSENSE –ILOAD
50mV
RSENSE
IRSENSE = ILIMIT
=
(9)
For successful completion of current limit start-up cycle
there must be a net current to charge CLOAD and the
current limit duration must be less than tCBDELAY. The
second term in Equation 11 has to fulfill Equation 12.
Equations7and8areapplicablebutwithalowerGATEand
VOUT ramp rate.
421034fa
11
LTC4210-3/LTC4210-4
W U U
U
APPLICATIO S I FOR ATIO
A
B
CIRCUIT BREAKER
TRIPS
V
IN
CLOAD
•
< tCBDELAY
(12)
COMP2
IRSENSE –ILOAD
LATCHED OFF (5µA PULL-UP)
OR RETRY (2µA PULL-DOWN)
V
TIMER
60µA
Circuit Breaker Timer Operation
COMP1
100µA
When a current limit fault is encountered at time point A in
Figure5, thecircuitbreakertimingisactivatedwitha60µA
pull-up. The circuit breaker trips at time point B if the fault
is still present and the TIMER pin voltage reaches the
COMP2 threshold and the LTC4210 shuts down. For a
continuous fault, the circuit breaker delay is:
4210 F05
NORMAL
MODE
FAULT
MODE
Figure 5. A Continuous Fault Timing
CTIMER
60µA
tCBDELAY = 1.3V •
A1
B1
A2
B2
A3 B3
(13)
~50mV/R
SENSE
I
LOAD
Intermittent overloads may exceed the current limit as in
Figure 6, but if the duration is sufficiently short, the TIMER
pin may not reach the COMP2 threshold and the LTC4210
will not shut down. To handle this situation, the TIMER
discharges with 2µA whenever (VCC – SENSE) voltage is
below the 50mV limit and the TIMER voltage is between
the COMP1 and COMP2 thresholds. When the TIMER
voltage falls below the COMP1 threshold, the TIMER pin is
discharged with an equivalent 7k resistor (normal mode,
100µA source) when (VCC – SENSE) voltage is below the
50mV limit. If the TIMER pin does not drop below the
COMP1 threshold, any intermittent overload with an ag-
gregate duty cycle of more than 3.8% will eventually trip
the circuit breaker. Figure 7 shows the circuit breaker
response time in seconds normalized to 1µF. The asym-
metric charging and discharging of TIMER is a fair gauge
of MOSFET heating.
CIRCUIT BREAKER
TRIPS
60µA
60µA
2µA
COMP2
TIMER
60µA
V
COMP1
2µA
LATCHED OFF (5µA PULL-UP)
OR RETRY (2µA PULL-DOWN)
V
10µA
10µA
GATE
4210 F06
CB
FAULT
CB
CB
FAULT
FAULT
Figure 6. Mulitple Intermittent Overcurrent Conditon
1
t
1.3V • 1µF
60µA • D – 2µA
(s/µF) =
C
TIMER
t
1.3V •1µF
(s / µF)=
(14)
0.1
CTIMER
60µA •D – 2µA
(
)
When the circuit breaker trips, the GATE pin is pulled low.
The TIMER enters latchoff mode with a 5µA pull-up for the
LTC4210-4(latched-offversion),whileanautoretry“cool-
off” cycle begins with a 2µA pull-down for the LTC4210-3
(autoretry version). An autoretry cool-off delay of the
LTC4210-3betweenCOMP2andCOMP1thresholdstakes:
0.01
10 20
40
60 70 80
100
0
30
50
90
OVERLOAD DUTY CYCLE, D (%)
4210 F07
Figure 7. Circuit Breaker Timer Response
for Intermittent Overload
CTIMER
tCOOLOFF = 1.1V •
(15)
2µA
421034fa
12
LTC4210-3/LTC4210-4
W U U
APPLICATIO S I FOR ATIO
U
Autoretry After Current Fault (LTC4210-3)
A
B
C
V
Figure8showsthewaveformsoftheLTC4210-3(autoretry
version)duringacircuitbreakerfault. AttimepointB1, the
TIMER trips the COMP2 threshold of 1.3V. The GATE pin
pullstogroundwhileTIMERbeginsa“cool-off”cyclewith
a 2µA pull-down to the COMP1 threshold of 0.2V. At time
point C1, the TIMER pin pulls down with approximately a
7kresistortogroundandaGATEstart-upcycleisinitiated.
If the fault persists, the fault autoretry duty cycle is
approximately 3.8%. Pulling the ON pin low for more than
30µs will stop the autoretry function and put the LTC4210
in reset mode.
CLAMP
COMP2
60µA
V
TIMER
COMP1
V
GATE
0V
0V
V
OUT
REGULATING AT 50mV/R
SENSE
I
LOAD
A1 B1
C1
A2 B2
2µA
2µA
COMP2
COMP1
60µA
60µA
V
TIMER
NORMAL
MODE
LATCHED OFF CYCLE
2410 F09
100µA
CB
FAULT
V
GATE
Figure 9. Latchoff After Overcurrent Fault
V
OUT
Normal Mode/External Timer Control
REGULATING AT 50mV/R
SENSE
Whenever the TIMER pin voltage drops below the COMP1
threshold, but is not in reset mode, the TIMER enters
normal (100µA source) mode with an equivalent 7k resis-
I
LOAD
tive pull-down. Table 1 shows the relationship of tINITIAL
tCBDELAY, tCOOLOFF vs CTIMER
,
NORMAL
MODE
COOL OFF
CYCLE
COOL OFF
CYCLE
.
CB
FAULT
CB
FAULT
4210 F08
If the TIMER pin is pulled beyond the COMP2 threshold,
the GATE pin is pulled to ground immediately. This allows
the TIMER pin to be used for overvoltage detection, see
Figure 11.
Figure 8. Automatic Retry After Overcurrent Fault
Latch-Off After Current Fault (LTC4210-4)
ExternallyforcingtheTIMERpinbelowtheCOMP1thresh-
Figure9showsthewaveformsoftheLTC4210-4(latch-off old will reset the TIMER to normal mode. During over-
version) during a circuit breaker fault. At time point B, the voltage detection, the TIMER’s 100µA pull-down current
TIMER trips the COMP2 threshold. The GATE pin pulls to will continue to be on if (VCC – SENSE) voltage is below
ground while the TIMER pin is latched high by a 5µA pull- 50mV.Ifthe(VCC –SENSE)voltageexceeds50mVduring
up. The TIMER pin eventually reaches the soft-clamped the overvoltage detection, the TIMER current will be the
voltage (VCLAMP) of 2.3V. To clear the latchoff mode, the same as described for latched-off or autoretry mode. See
user can either pull the TIMER pin to below 0.2V externally the section OVERVOLTAGE DETECTION USING TIMER
or cycle the ON pin low for more than 30µs.
PIN for details of the application.
421034fa
13
LTC4210-3/LTC4210-4
W U U If one of U the conditions cannot be met, an external Zener
APPLICATIO S I FOR ATIO
clampshownonFigure10aorFigure10bcanbeused. The
selection of RG should be within the allowed LTC4210
package dissipation when discharging VOUT via the Zener
clamp.
Table 1. t
, t
, t
vs C
INITIAL CBDELAY COOLOFF
TIMER
C
(µF)
t
(ms)
t
(ms)
t
(ms)
COOLOFF
TIMER
INITIAL
CBDELAY
0.033
9.0
0.7
18.2
0.047
0.068
0.082
0.1
12.8
18.6
1
25.9
37.4
45.1
55
In addition to the MOSFET gate drive rating and VGS
1.5
absolute maximum rating, other criteria such as VBDSS
,
22.4
1.8
ID(MAX), RDS(ON), PD, θJA, TJ(MAX) and maximum safe
operating area should also be carefully reviewed. VBDSS
should exceed the maximum supply voltage inclusive of
spikes and ringing. ID(MAX) should be greater than the
current limit, ILIMIT. RDS(ON) determines the MOSFET VDS
whichtogetherwithVCB yieldsanerrorintheVOUT voltage.
At2.7Vsupplyvoltage, thetotalofVDS +VCB of0.1Vyields
3.7% VOUT error.
27.3
2.2
0.22
0.33
0.47
0.68
0.82
1
60.0
4.8
121
90.1
7.2
181.5
258.5
374
128.3
185.6
223.8
272.9
600.5
900.7
10.2
14.7
17.8
21.7
47.7
71.5
451
550
2.2
1210
1815
The maximum power dissipated in the MOSFET is
ILIMIT2 • RDS(ON) and this should be less than the maxi-
mum power dissipation, PD allowed in that package.
Given power dissipation, the MOSFET junction tempera-
ture, TJ can be computed from the operating temperature
(TA) and the MOSFET package thermal resistance (θJA).
The operating TJ should be less than the TJ(MAX) specifi-
cation.
3.3
Power-Off Cycle
The system can be reset by toggling the ON pin low for
more than 30µs as shown at time point 7 of Figure 3. The
GATE pin is pulled to ground. The TIMER capacitor is also
dischargedtoground. CLOAD dischargesthroughtheload.
Alternatively,theTIMERpincanbeexternallydrivenabove
the COMP2 threshold to turn off the GATE pin.
Next review the short-circuit condition under maximum
supply VIN(MAX) conditions and maximum current limit,
ILIMIT(MAX) during the circuit breaker time-out interval of
tCBDELAY with the maximum safe operating area of the
MOSFET. Theoperationduringoutputshort-circuitcondi-
tions must be well within the manufacturer’s recom-
mended safe operating region with sufficient margin. To
ensure a reliable design, fault tests should be evaluated in
the laboratory.
POWER MOSFET SELECTION
Power MOSFETs can be classified by RDSON at VGS gate
drive ratings of 10V, 4.5V, 2.5V and 1.8V. Use the typical
curves ∆VGATE vs Supply Voltage and ∆VGATE vs Tem-
perature to determine whether the gate drive voltage is
adequate for the selected MOSFET at the operating volt-
age.
VIN TRANSIENT PROTECTION
In addition, the selected MOSFET should fulfill two VGS
criteria:
Unlike most circuits, Hot Swap controllers typically are
not allowed the good engineering practice of supply
bypass capacitors, since controlling the surge current to
bypass capacitors at plug-in is the primary motivation for
the Hot Swap controller. Although wire harness, back-
plane and PCB trace inductances are usually small, these
cancreatespikeswhencurrentsaresuddenlydrawn, cut-
off or limited. The transient associated with the GATE turn
1. Positive VGS absolute maximum rating > LTC4210-3/
LTC4210-4 maximum ∆VGATE, and
2. Negative VGS absolute maximum rating > supply
voltage. The gate of the MOSFET can discharge faster
thanVOUT whenshuttingdowntheMOSFETwithalarge
CLOAD
.
421034fa
14
LTC4210-3/LTC4210-4
W U U
APPLICATIO S I FOR ATIO
U
off can be controlled with a snubber and/or transient
voltage suppressor. RC snubber networks are effective
for LTC4210-3/LTC4210-4 applications. The choice of
RC is usually determined experimentally. The value of the
snubber capacitor is usually chosen between 10 to 100
timestheMOSFETCOSS.Thevalueofthesnubberresistor
is typically between 3Ω to 100Ω. A snubber network is
normally sufficient to protect against transient voltages.
However, when input wires are long or EMI beads exist in
the wire harness, a transient suppressor should be used
in conjuction with the snubber to clip off voltage spikes
and reduce ringing. In many cases, a simple short-circuit
test can be performed to determine the need of the
transient voltage suppressor.
OVERVOLTAGE DETECTION USING THE TIMER PIN
Figure 11 shows a supply side overvoltage detection
circuit. A Zener diode, a diode and COMP2 threshold sets
the overvoltage threshold. Resistor RB biases the Zener
diode voltage. Diode D1 blocks forward current in the
Zener during start-up or output short-circuit. RTIMER with
CTIMER sets the overload noise filter.
RELATED PARTS
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.4 MIN
1.50 – 1.75
2.80 BSC
3.85 MAX 2.62 REF
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
421034fa
15
LTC4210-3/LTC4210-4
U
W U U
U
APPLICATIO S I FOR ATIO
R
SENSE
R
SENSE
Q1
Q1
V
CC
V
OUT
V
CC
V
OUT
D1*
D1*
D2*
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE
IS RECOMMENDED)
1N4688 (5V)
R
R
G
200Ω
G
200Ω
GATE
GATE
(10a)
(10b)
Figure 10. Gate Protection Zener Clamp
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
(FEMALE)
(MALE)
R
Q1
Si4410DY
SENSE
0.01Ω
V
5V
4A
OUT
LONG
V
IN
5V
R
R
+
X
B
10k
Z2
C
LOAD
10Ω
Z1
470µF
C
X
6
5
0.1µF
D1
1N4148
R
G
100Ω
V
SENSE
GATE
CC
4
R
TIMER
18Ω
R
ON1
20k
R4
SHORT
LONG
3
1
LTC4210-3
100Ω
ON
C
R
ON2
10k
C
10nF
TIMER
GND
2
C
TIMER
0.22µF
GND
GND
4210 F11
Z1: SMAJ10A Z2: BZX84C6V2
Figure 11. Supply Side Overvoltage Protection
RELATED PARTS
PART NUMBER
LTC1421
DESCRIPTION
COMMENTS
Two Channel, Hot Swap Controller
Operates from 3V to 12V and Supports –12V
Operates from 2.7V to 12V, Reset Output
LTC1422
Single Channel, Hot Swap Controller in SO-8
Negative Voltage Hot Swap Controller in SO-8
Single Channel, Hot Swap Controller
LT1640AL/LT1640AH
LTC1642
Operates from –10V to –80V
Overvoltage Protection to 33V, Foldback Current Limiting
3.3V, 5V, Internal FETs for ±12V
LTC1643AL/LTC1643AH PCI Hot Swap Controller
LTC1647
LTC4211
LTC4230
LTC4251
LTC4252
LTC4253
Dual Channel, Hot Swap Controller
Operates from 2.7V to 16.5V, Separate ON pins for Sequencing
2.5V to 16.5V, Multifunction Current Control
1.7V to 16.5V, Multifunction Current Control
Floating Supply, Three-Level Current Limiting
Floating Supply, Power Good, Three-Level Current Limiting
Floating Supply, Three-Level Current Limiting
Single Channel, Hot Swap Controller
Triple Channel, Hot Swap Controller
–48V Hot Swap Controller in SOT-23
–48V Hot Swap Controller in MSOP
–48V Hot Swap Controller with Triple Supply Sequencing
421034fa
LT 1106 REV A• PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
相关型号：
LTC4210-4CS6#PBF
LTC4210-3 and -4 - Hot Swap Controller in 6-Lead SOT-23 Package; Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C
Linear
LTC4210-4CS6#TR
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6, PLASTIC, MO-193, TSOT-23, 6 PIN, Power Management Circuit
Linear
LTC4210-4CS6#TRMPBF
LTC4210-3 and -4 - Hot Swap Controller in 6-Lead SOT-23 Package; Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C
Linear
LTC4210-4IS6#PBF
LTC4210-3 and -4 - Hot Swap Controller in 6-Lead SOT-23 Package; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C
Linear
LTC4210-4IS6#TR
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO6, PLASTIC, MO-193, TSOT-23, 6 PIN, Power Management Circuit
Linear
©2020 ICPDF网 联系我们和版权申明