LTC4212 [Linear]
Hot Swap Controller with Power-Up Timeout; 热插拔控制器与Power -UP超时
| 型号： | LTC4212 |
| 厂家： | 
Linear |
| 描述： | Hot Swap Controller with Power-Up Timeout |
| 文件： | 总24页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4212
Hot Swap Controller with
Power-Up Timeout
U
DESCRIPTIO
FEATURES
The LTC®4212 is a Hot SwapTM controller that allows a
board to be safely inserted and removed from a live
backplane.Aninternalhighsideswitchdrivercontrolsthe
gateofanexternalN-channelMOSFETforsupplyvoltages
ranging from 2.5V to 16.5V. The LTC4212 provides soft-
start and inrush current limiting during the start-up
period. It features a power-up timeout circuit that discon-
nectsthesystemsupplywhentheonboardsuppliesdonot
enter into regulation within an adjustable timeout period.
The controller interfaces with external supply monitor ICs
or directly with the PGOOD pin of a DC/DC converter. After
normal power-up, a programmable power good glitch
filter can be enabled to filter out short term dips in the
supplies.
■
Allows Safe Board Insertion and Removal
from a Live Backplane
■
Controls Supply Voltages from 2.5V to 16.5V
■
Adjustable Soft-Start with Inrush Current
Limiting
Fast Turn-Off Time
■
■
No External Gate Capacitor is Required
■
Power Good Input with Adjustable Timer and
Glitch Filter
■
Power-Up Timeout Circuit Interfaces with External
Supply Monitors
■
Dual Level Overcurrent Fault Protection
■
Automatic Retry or Latched Mode Operation
■
High Side Drive for an External N-Channel FET
■
MS10 Package
Two current limit comparators provide dual level
overcurrent circuit breaker protection. The slow com-
paratortripsatVCC –50mVandactivatesin18µs. Thefast
comparator trips at VCC – 150mV and typically responds
in 500ns.
U
APPLICATIO S
■
Electronic Circuit Breaker
■
Hot Board Insertion and Removal
The LTC4212 can be configured for both latchoff and
autoretry applications and is available in a 10-pin MSOP
package.
■
Self-Isolating Hot Swap Boards
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
Hot Swap Controller with Power Good Function
BACKPLANE
CONNECTOR CONNECTOR
(FEMALE) (MALE)
EDGE
0.007Ω
Si4410DY
Power-Up Waveforms
V
CC
5V
5V
+
10Ω
100nF
2.5V
1.5A
LT1963-2.5
Z1
ON
10µF
+
+
+
+
5V/DIV
10µF
10µF
10µF
TIMER
1V/DIV
V
SENSE
GATE
10k
10k
CC
3.3V
1.5A
LT1963-3.3
ON
10k
10µF
20k
LTC4212
PGT
PGT
1V/DIV
PGI
FAULT
FAULT
GND
10k
V
CCA
V
CC3
TIMER
PGF
LTC1727-2.5
COMP2.5
COMP3
PGI
5V/DIV
2.1k
V
CC25
0.01µF
4.7nF
270pF
COMP A GND
5ms/DIV
4212 TA01a
GND
Z1 = SMAJ10A (TVS)
4212f
1
LTC4212
W W
U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
Supply Voltage (VCC) ............................................... 17V
Input Voltages
ON, PGI ................................................ –0.3V to 17V
SENSE .................................... –0.3V to (VCC + 0.3V)
TIMER, PGT, PGF ....................................–0.3V to 2V
Output Voltages
TOP VIEW
ON
TIMER
PGT
1
2
3
4
5
10 FAULT
LTC4212CMS
LTC4212IMS
9
8
7
6
V
CC
SENSE
GATE
PGI
PGF
GND
MS PACKAGE
10-LEAD PLASTIC MSOP
GATE ............................... Internally Limited (Note 3)
FAULT .................................................. –0.3V to 17V
Operating Temperature Range
LTC4212C .............................................. 0°C to 70°C
LTC4212I........................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
MS PART
MARKING
TJMAX = 125°C, θJA = 200°C/ W
LTC5
LTC6
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
16.5
1.5
UNITS
V
V
V
V
Supply Voltage Range
Supply Current
●
●
●
2.5
CC
CC
CC
I
ON = High, TIMER = Low
1
mA
V
CC
V
V
Internal V Undervoltage Lockout
V
Low-to-High Transition
2.13
2.34
110
±1
2.47
LKO
CC
CC
V
Undervoltage Lockout Hysteresis
CC
mV
µA
LKOHST
INON
I
I
I
I
ON Input Current
V
V
V
V
= V or GND
±10
±2.5
±10
±10
170
60
ON
CC
FAULT Leakage Current
PGI Pin Input Current
SENSE Input Current
= 15V, Pull-Down Device Off
●
±0.1
±1
µA
LEAK
FAULT
= V or GND
µA
INPGI
PGI
CC
= V or GND
±1
µA
INSENSE
SENSE
CC
V
V
SENSE Trip Voltage (V – V
)
)
Fast Comparator Trips
Slow Comparator Trips
●
●
●
●
130
40
150
50
mV
mV
µA
CB(FAST)
CB(SLOW)
GATEUP
CC
SENSE
SENSE Trip Voltage (V – V
CC
SENSE
I
I
GATE Pull-Up Current
Charge Pump On, V
ON Low
≤ 0.2V
–12.5
130
–10
200
50
–7.5
270
GATE
Normal GATE Pull-Down Current
Fast GATE Pull-Down Current
µA
GATEDOWN
FAULT Latched and Circuit Breaker
Tripped or in UVLO, V = 15V
mA
GATE
∆V
External N-Channel Gate Drive
V
V
V
V
V
V
– V (For V = 2.5V)
●
●
●
●
●
●
4.0
4.5
5.0
10
10
8
8
8
10
16
18
15
V
V
V
V
V
V
GATE
GATE
GATE
GATE
GATE
GATE
GATE
CC
CC
– V (For V = 2.7V)
CC
CC
– V (For V = 3.3V)
CC
CC
– V (For V = 5V)
CC
CC
– V (For V = 12V)
CC
CC
– V (For V = 15V), (Note 3)
CC
CC
V
V
V
V
V
GATE Overvoltage Lockout Threshold
ON Threshold High
●
●
●
●
0.08
1.23
0.4
0.2
1.316
0.455
1.236
28
0.3
1.39
0.5
V
V
V
V
GATEOV
ONHI
ON Threshold Low
ONLO
PGI
Power Good Input Threshold
Power Good Input Hysterisis
1.20
1.26
mV
PGIHST
4212f
2
LTC4212
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1.236
40
MAX
UNITS
V
V
V
V
V
Power Good Glitch Filter High Threshold
Power Good Glitch Filter Hysterisis
Power Good Timer High Threshold
Power Good Timer Low Threshold
Power Good Timer Delta Threshold
Power Good Timer Pin Current
●
1.20
1.26
V
mV
V
PGFHI
PGFHST
PGTHI
PGTLO
PGT∆V
PGT
(Note 4)
●
●
●
0.928
0.640
0.283
0.952 0.976
0.657 0.680
0.295 0.304
V
V
I
Power Good Timer On, C
Power Good Timer On, C
Power Good Timer Off, PGT = 1.5V
Charging, PGT = 0.65V
Discharging, PGT = 0.95V
●
●
–5.61
4.63
–5.1
5.2
5
–4.59
5.77
µA
µA
mA
PGT
PGT
I
I
Power Good Glitch Filter Pin Current
TIMER Current
Power Good Glitch Filter On, C Charging
Power Good Timer Off, PGF = 1.5V
●
●
–5.61
–2.5
-5.1
5
–4.49
–1.5
µA
mA
PGF
PGF
Timer On, V = 1V
–2
5
µA
mA
TMR
TIMER
Timer Off, TIMER = 1.5V
V
TIMER Threshold
TIMER Low to High
TIMER High to Low
●
●
1.20
0.15
1.236
0.200
1.26
0.40
V
V
TMR
V
V
V
FAULT Threshold
Latched Off Threshold, FAULT High to Low
●
1.20
1.236
50
1.26
V
mV
V
FAULT
FAULT Threshold Hysteresis
Output Low Voltage
FAULTHST
OLFAULT
I
= 1.6mA
●
●
0.14
18.16
1
0.4
20
FAULT
t
t
Power Good Time-Out
C
PGT
=10nF, PGT = 0.1V to FAULT Low
16.3
ms
µs
TO
Power Good Input Low at Time-Out to End of 14th PGT Cycle
GATE Discharging
FAULTLO
t
Valid Power Good Glitch to GATE
Discharging
PGF > 1.26V
1.5
µs
FAULTVG
t
t
t
t
t
FAST COMP Trip to GATE Discharging
SLOW COMP Trip to GATE Discharging
FAULT Low to GATE Discharging
Circuit Breaker Reset Delay Time
Turn-Off Time
V
V
V
= 0mV to 200mV Step
= 0mV to 100mV Step
●
●
●
●
500
18
700
30
ns
µs
µs
µs
µs
FAULTFC
FAULTSC
EXTFAULT
RESET
CB
10
1
CB
= 5V to 0V
3
5
FAULT
ON Low to FAULT High
ON Low to GATE Off
120
10
250
OFF
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 3: An internal clamp limits the GATE pin to a minimum of 10V above
V . Driving this pin to voltages beyond the clamp may damage the part. If
CC
a lower GATE pin voltage is desired, use an external zener diode. The GATE
capacitance must be <0.15µF at maximum V
Note 4: Guaranteed by design and not tested in production.
Note 2: All current into device pins are positive; all current out of device
pins are negative; all voltages are referenced to ground unless otherwise
specified.
.
CC
4212f
3
LTC4212
U W
TYPICAL PERFOR A CE CHARACTERISTICS Specifications are T = 25°C. V
CC = 5V, unless
A
otherwise noted.
Undervoltage Lockout
Threshold vs Temperature
Supply Current vs Supply Voltage
Supply Current vs Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5
2.4
RISING EDGE
V
= 16.5V
CC
2.3
FALLING EDGE
2.2
2.1
2.0
V
= 5V
CC
V
= 2.5V
CC
0
2
4
6
8
10 12 14 16 18 20
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75
100 125
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
4212 G01
4212 G02
4212 G03
GATE Voltage vs Supply Voltage
GATE Voltage vs Temperature
VGATE – VCC vs Supply Voltage
30
25
30
25
18
16
14
12
10
8
V
= 16.5V
CC
20
20
15
V
= 5V
CC
15
10
10
5
6
4
V
= 2.5V
50
CC
5
0
2
0
0
0
2
4
6
8
10 12 14 16 18
–50 –25
0
25
75 100 125
0
2
4
6
8
10
18
12 14 16
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4212 G06
4212 G07
4212 G08
GATE Output Source Current vs
Supply Voltage
GATE Output Source Current vs
Temperature
VGATE – VCC vs Temperature
13
12
18
16
14
12
10
8
13
12
V
= 12V
CC
11
11
10
V
= 15V
CC
V
CC
= 16.5V
V
= 5V
CC
10
9
V
= 3.3V
CC
9
8
7
6
V
CC
= 5V
V
CC
= 2.5V
4
8
7
2
0
0
2
4
6
8
10 12 14 16 18 20
–50 –25
0
TEMPERATURE (°C)
100 125
–50 –25
0
25
50
75 100 125
25
50
75
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
4212 G10
4212 G09
4212 G11
4212f
4
LTC4212
U W
TYPICAL PERFOR A CE CHARACTERISTICS Specifications are T = 25°C. V
CC = 5V, unless
A
otherwise noted.
Fast GATE Pull-Down Current vs
Supply Voltage
Fast GATE Pull-Down Current vs
Temperature
VCB (SLOW COMP) vs Supply
Voltage
80
70
60
58
56
54
52
50
48
46
44
42
40
80
70
60
60
50
50
40
40
30
20
30
20
0
2
4
6
8
10 12 14 16 18
0
2
4
6
8
10 12 14 16 18
–50 –25
0
25
50
75 100 125
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4212 G14
4212 G26
4212 G15
SLOW COMP Trips to GATE
Discharging Delay vs Supply
Voltage
VCB (FAST COMP) vs Supply
Voltage
SLOW COMP Trips to GATE
Discharging Delay vs Temperature
170
165
160
155
150
145
140
135
130
26
24
22
20
18
16
14
12
10
26
24
22
20
18
16
14
12
10
V
= 15V
CC
V
= 12V
CC
V
CC
= 16.5V
V = 3V
CC
V
CC
= 5V
25
50
0
2
4
6
8
10 12 14 16 18
0
2
4
6
8
10 12 14 16 18
–50 –25
0
75 100 125
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
4212 G28
4212 G30
4212 G31
FAST COMP Trips to GATE
Discharging Delay vs Supply
Voltage
FAST COMP Trips to GATE
Discharging Delay vs Temperature
Power Good Timeout vs Supply
Voltage
600
500
400
300
200
100
0
21
20
19
18
17
16
15
700
600
500
400
300
200
100
0
V
= 0mV TO 200mV STEP
V
= 0mV TO 200mV STEP
CB
CB
V
= 3V
CC
V
= 5V
CC
V
= 12V
CC
V
= 16.5V
CC
V
= 15V
CC
0
2
4
6
8
10 12 14 16 18
25
50
0
2
4
6
8
10 12 14 16 18
–50 –25
0
75 100 125
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
4212 G40
4212 G32
4212 G33
4212f
5
LTC4212
U W
TYPICAL PERFOR A CE CHARACTERISTICS Specifications are T = 25°C. V
CC = 5V, unless
A
otherwise noted.
Power Good Timeout vs
Temperature
PGI Low at Timeout to GATE
Discharging vs Supply Voltage
PGI Low at Timeout to GATE
Discharging vs Temperature
1.8
1.5
1.2
0.9
0.6
0.3
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
–50 –25
0
25
50
75 100 125
16
–50 –25
0
50
100 125
0
2
4
6
8
10 12 14
18
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4212 G41
4212 G44
4212 G45
PGF and PGT Pin Current
(Timer or Filter Off)
vs Supply Voltage
PGF and PGT Pin Current
(Timer or Filter Off)
vs Temperature
Valid Glitch to GATE Discharging
vs Supply Voltage
10
9
8
7
6
5
4
3
2
1
0
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
8
7
6
5
4
3
2
1
0
PGF
PGT
75 100
TEMPERATURE (°C)
125
–50 –25
0
25
50
75 100 125
0
2
4
6
8
10 12 14 16 18
–50 –25
0
25
50
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4212 G50
4212 G51
4212 G52
Valid Glitch to GATE Discharging
vs Temperature
FAULT VOL vs Supply Voltage
FAULT VOL vs Temperature
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
I
OL
= 5mA
I
= 1mA
4
OL
–50 –25
0
25
50
75 100 125
75
TEMPERATURE (°C)
0
2
6
8
10 12 14 16 18
–50 –25
0
25
50
100 125
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4212 G53
4212 G54
4212 G55
4212f
6
LTC4212
U W
TYPICAL PERFOR A CE CHARACTERISTICS Specifications are T = 25°C. V
CC = 5V, unless
A
otherwise noted.
FAULT Pin Low to GATE
Discharging Time vs Supply
Voltage
FAULT Pin Low to GATE
Discharging Time vs Temperature
Circuit Breaker RESET Time vs
Supply Voltage
4.5
4.0
200
180
4.5
4.0
3.5
3.5
3.0
160
140
3.0
2.5
2.5
2.0
1.5
120
100
80
2.0
1.5
0
2
4
6
8
10 12 14 16 18
0
2
4
6
8
10 12 14 16 18
–50 –25
0
25
50
75 100 125
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
4212 G58
4212 G60
4212 G59
Circuit Breaker RESET Time vs
Temperature
Turn-Off Time vs Supply Voltage
Turn-Off Time vs Temperature
11
10
200
180
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
160
9
8
140
120
7
6
5
9.0
100
80
8.5
8.0
0
2
4
6
8
10 12 14 16 18
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
4212 G62
4212 G61
4212 G63
4212f
7
LTC4212
U
U
U
PI FU CTIO S
ON (Pin 1): On/Off Control Input. The ON pin is used to
enable and disable LTC4212 operation and reset internal
logic and the electronic circuit breaker (ECB). It must be
pulled high (>1.316V) to start the first system timing
cycle.IftheONpinispulledlow(<0.455Vtypical)formore
than 10µs, the internal logic is reset and the GATE pin is
pulled down by a 200µA current to turn off the external
FET. If the ON pin is pulled low for more than 120µs, the
electronic circuit breaker is reset. This pin is tied to a
resistive divider in latch-off applications or to the FAULT
pin and an external RC circuit in auto-retry applications.
threshold 1.236V. When the power good timer times out
(seePin3), PGImustbehightoavoidtrippingtheECBand
to enable the power good glitch filter.
GATE (Pin 7): Gate Output Pin. The output signal at this
pin is the high side gate drive for the external N-channel
FET pass transistor.
As shown in the Block Diagram, an internal charge pump
supplies a 10µA gate current and sufficient gate voltage to
drive the external FET for supply voltages from 2.5V to
16.5V. The internal charge pump and zener clamps at the
charge pump output determine the gate drive voltage
(∆VGATE = VGATE – VCC). The charge pump produces a
minimum 4V of ∆VGATE for supplies in the range of 2.5V <
VCC < 4.75V. For VCC > 4.75V, the ∆VGATE is limited by
zener clamp Z1 connected between the charge pump
output and the VCC pin. The ∆VGATE is typically at 12V and
withguaranteedminimumvalueof10V. ForVCC >15V, the
zener clamp Z2 sets the limitation for ∆VGATE. Z2 clamps
the gate voltage to ground to 28V typically. The minimum
Z2’s clamp voltage is 23V. This effectively sets ∆VGATE to
8V minimum.
TIMER (Pin 2): System Timer Input. An external capacitor
(CTIMER) connected from this pin to ground determines
the duration of the first and second system timing cycles.
The first timing cycle allows time for the board to be
inserted properly. During the second timing cycle, a
soft-start circuit controls the gate of the external
N-channel FET to limit inrush currents from the backplane
supply.
PGT (Pin 3): Power Good Timer Input. An external capaci-
tor (CPGT) connected from this pin to ground sets the
power good time-out period. This is the maximum time
allowed for externally monitored DC/DC converters to
power-up into regulation and pull the PGI pin high. The
nominal time-out cycle is 1.81s/µF and begins from the
end of the second system timing cycle. This pin is pulled
togroundbyaninternalswitchwhenthepowergoodtimer
is disabled or when the ECB is tripped.
SENSE (Pin 8): Circuit Breaker Set Pin. With a sense
resistorplacedinthepowerpathbetweenVCC andSENSE,
theLTC4212’selectroniccircuitbreakertripsifthevoltage
across the sense resistor exceeds the thresholds set
internally for the SLOW COMP and the FAST COMP, as
shown in the Block Diagram. The threshold for the SLOW
COMP is VCB(SLOW) = 50mV, and the electronic circuit
breaker trips if the voltage across the sense resistor
exceeds 50mV for 18µs.
PGF (Pin 4): Power Good Glitch Filter Input. An external
capacitor (CPGF) connected from this pin to ground deter-
mines the power good glitch filter delay. The glitch filter is
enabled if the externally monitored DC/DC converters are
powered up within the power good time-out period (see
Pin 3). If the PGI pin goes low for longer than the filter
delay, the ECB is tripped.
Under transient conditions where large step current
changes can and do occur over shorter periods of time, a
second (fast) comparator instead trips the electronic
circuit breaker. The threshold for the FAST COMP is set at
VCB(FAST) = 150mV, and the circuit breaker trips if the
voltageacrossthesenseresistorexceeds150mVformore
than 500ns. To disable the electronic circuit breaker,
connect the VCC and SENSE pins together.
GND (Pin 5): Device Ground Connection. Connect this pin
to the system’s analog ground plane.
PGI (Pin 6): Power Good Input Pin. This pin is used by the
power good circuit to sense the open drain RST output or
comparator outputs of an external supply monitor IC or
the PGOOD output of a DC/DC converter. It requires an
external pull-up resistor to a voltage above the VFAULT
VCC(Pin9):ThisisthepositivesupplyinputtotheLTC4212.The
LTC4212 operates from 2.5V < VCC < 16.5V, and the supply
currentistypically1mA.Aninternalundervoltagelockoutcircuit
disables the device until the voltage at VCC exceeds 2.34V.
4212f
8
LTC4212
U
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PI FU CTIO S
FAULT (Pin 10): Open Drain FAULT Output or External
FAULT Input. If the FAST COMP, SLOW COMP or the
power good circuit trips the ECB, the FAULT pin is latched
low. TheFAULTpinisanopendrainoutputandistypically
connected by a 10k pull-up resistor to VCC. An external
circuit can also trip the ECB by driving FAULT below
1.236V (typical).
W
BLOCK DIAGRA
V
CC
9
SENSE
8
GATE
0.2V
7
–
+
Z2
Z
Z1
V
(TYP) = 28V
V
(TYP) = 12V
Z
COMP7
V
CC
CHARGE
PUMP
10µA
UVLO
–
–
+
+
150mV
50mV
t
TIMER
+
+
–
–
M3
CB
V
CC
SLOW
FAST
COMP
COMP
0.2V
+
–
200µA
10µA
2µA
COMP3
COMP4
START-UP
CURRENT
18µS
GLITCH FILTER
500ns
DELAY
TIMER
2
TRIPS
ON LOW
GATE
OR UVLO >10µs
REGULATOR CHARGING
M6
+
–
V
+
–
REF
COMP6
V
REF
FAULT
10
NORMAL
CB TRIPS
1.316V
M2
–
LOGIC
1.5µs
DELAY
COMP1
ON
1
GND
5
+
200µA
GATE
PULLDOWN
–
10µs
RESET
ECB
COMP2
0.455V
120µs
+
VALID
GLITCH
DISABLE
GLITCH
FILTER
DISABLE
TIMER
5µA
5µA
COMP5
COMP8
COMP9
–
–
+
+
–
+
M10
M1
V
V
REF
REF
M9
M5
0.95V
M8
M12
V
=
REF
0.95V
0.65V
1.236V
5µA
BG
0.65V
0.2V
4212 BD
4
PGF
6
PGI
3
PGT
4212f
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LTC4212
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OPERATIO
Hot Circuit Insertion
accordingly. The FAULT comparator can also be used to
set a higher undervoltage lockout voltage. If the FAULT
comparator is used for this purpose, the system will wait
for the input voltage to increase above the level set by the
user before starting the second timing cycle. Also, if the
inputvoltagedropsbelowthesetlevelinnormaloperating
mode, the electronic circuit breaker (ECB) trips and the
user must cycle the ON pin or VCC to restart the system.
Whencircuitboardsareinsertedintoorremovedfromlive
backplanes, the supply bypass capacitors can draw huge
transient currents from the backplane power bus as they
charge. The transient current can cause permanent dam-
age to the connector pins as well as cause glitches on the
system supply, causing other boards in the system to
reset.
3.3V
5V
12V
The LTC4212 is designed to turn a printed circuit board’s
supplyvoltagesONandOFFinacontrolledmanner, allow-
ing the circuit board to be safely inserted or removed from
a live backplane.
R1
10k
R1
R1
61.9k
20k
ON PIN
ON PIN
ON PIN
R2
10k
R2
10k
R2
10k
4212 F01
Output Voltage Monitor
(a) V = 3.3V
(b) V = 5V
(c) V = 12V
CC
CC
CC
Unlike other LTC Hot Swap controller products, the
LTC4212 does not have an FB pin and monitors onboard
DC/DCconvertersviaanexternalpowersupplymonitorIC
such as the LTC1326-2.5 or the LTC1727. This allows
several DC/DC converters to be monitored at the same
time. The LTC4212’s PGI or power good input pin is used
to monitor the RST or comparator outputs of the monitor
IC and it can also be tied directly to the PGOOD pin of a
DC/DC converter.
Figure 1. ON Pin Sets the Undervoltage
Lockout Voltage Externally
System Timing
System timing for the LTC4212 is generated by the TIMER
circuitry (see the Block Diagram). If the LTC4212’s inter-
naltimingcircuitisoff,aninternalN-channelFETconnects
the TIMER pin to GND. If the timing circuit is enabled, an
internal 2µA current source is then connected to the
TIMER pin to charge CTIMER at a rate given by Equation 1:
Undervoltage Lockout
The LTC4212’s internal power-on reset circuit initializes
the start-up procedure and ensures the IC is in the proper
state if the input supply voltage exceeds 2.34V. If the
supply voltage falls below 2.23V, the LTC4212 is in
undervoltage lockout (UVLO) mode, and the GATE pin is
pulled low. Since the UVLO circuitry uses hysteresis, the
LTC4212 restarts after the supply voltage rises above
2.34V and the ON pin goes high.
2µA
CTIMER Charge -Up Rate =
(1)
CTIMER
When the TIMER pin voltage reaches COMP4’s threshold
of 1.236V, the TIMER pin is reset to GND. Equation 2 gives
an expression for the timer period:
CTIMER
tTIMER = 1.236V •
In addition, users can utilize the ON comparator (COMP1)
or the FAULT comparator (COMP6) to effectively set up a
higher undervoltage lockout level. Figure 1 shows the
external resistive divider for the ON pin to adjust the
system’s undervoltage lockout voltage. The system will
entertheplug-incycleaftertheONpinrisesabove1.316V.
The resistive divider sets the circuit to turn on when VCC
reaches around 79% of its final value. If a different turn on
VCC voltage is desired change the resistive divider ratio
(2)
2µA
As a design aid, the LTC4212’s timer period as a function
of the CTIMER using standard values from 3.3nF to 0.33µF
is shown in Table 1.
The CTIMER value is vital to ensure a proper start-up and
reliable operation. This timing periodshould not beexces-
sive as an output short can occur at start-up causing the
external MOSFET to overheat. A good starting point is to
4212f
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LTC4212
U
OPERATIO
set CTIMER = 10nF and adjust its value accordingly to suit
the specific applications.
Power Good Timer
The timer consists of COMP9, M8-M12, two 5µA current
sources and 0.65V and 0.95V threshold voltages for
COMP9.
Table 1. tTIMER vs CTIMER
C
t
TIMER
TIMER
0.0033µF
0.0047µF
0.0068µF
0.0082µF
0.01µF
2.0ms
2.9ms
The PGI pin is normally connected to the RST output pin
or comparator outputs of an external supply monitor IC or
to the PGOOD pin of a DC/DC converter and drives a
comparator, COMP8 which has a threshold voltage of
1.236V and 28mV of hysterisis. The RST and PGOOD pins
are typically open drain pins and require an external pull-
up resistor. The upper end of the resistor must be con-
nected to a voltage greater than the upper threshold of the
PGI comparator (1.236V).
4.2ms
5.1ms
6.2ms
0.015µF
0.022µF
0.033µF
0.047µF
0.068µF
0.082µF
0.1µF
9.3ms
13.6ms
20.4ms
29.0ms
42.0ms
50.7ms
61.8ms
92.7ms
136ms
204ms
A capacitor, CPGT, connected from the PGT pin to ground
programs the time-out period generated by the power
good timer according to Equation 3. Table 2 shows the
power good time-out periods for a list of standard capaci-
tor values.
0.15µF
0.22µF
0.33µF
tTIMEOUT = 1.81Ω • CPGT
(3)
Two5µAcurrentsourcesareswitchedinandouttocharge
and discharge CPGT between 0.65V and 0.95V for 14
cycles.
Power-Up Timeout Circuit
The power-up timeout circuit has two functions. During
power-up, it trips the circuit breaker if the DC/DC convert-
ers on the board do not power-up and do not enter
regulationontime. Afternormalpower-up, itisconfigured
to trip the circuit breaker if any of the converters exit
regulationforlongerthanaprogrammabledelay.Oncethe
circuit breaker is tripped, the LTC4212 is latched off and
theboardisdisconnectedfromthesystemsupply. TheON
pinmustbetakenlowfor120µstoresetthecircuitbreaker
and then high to reconnect the board to the backplane
supply.
Table 2. tTIMEOUT vs CPGT
C
t
TIMEOUT
PGT
3.3nF
4.7nF
5.97ms
8.51ms
12.3ms
14.8ms
18.1ms
39.8ms
59.7ms
85.1ms
123ms
148ms
181ms
136ms
398ms
851ms
1230ms
1480ms
1810ms
6.8nF
8.2nF
0.01µF
0.022µF
0.033µF
0.047µF
0.068µF
0.082µF
0.1µF
The power-up timeout circuit uses three pins: PGI or
power good input pin, PGT or power good timer pin and
PGF or power good filter pin. It is enabled at the end of the
second system timing cycle, provided that the FAULT pin
is high. Prior to being enabled or if FAULT is low, the PGT
and PGF pins are pulled to GND by internal N-channel
FETs, M5 and M12 respectively. When enabled, the
power-up timeout circuit starts the power good timer,
which generates a time-out period before the PGI pin is
sampled.
0.22µF
0.33µF
0.47µF
0.68µF
0.82µF
1µF
4212f
11
LTC4212
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OPERATIO
Table 3. tPGF vs CPGF
Since the PGT is pulled to GND by M12 before the power
good circuit is enabled, the first positive ramp at the PGT
pin starts from 0V instead of the 0.65V for the subsequent
13 cycles.
C
t
PGF
PGF
—
5µs
10pF
22pF
33pF
47pF
68pF
82pF
100pF
220pF
330pF
470pF
680pF
820pF
1nF
7.5µs
10.4µs
13.2µs
16.6µs
21.8µs
25.2µs
29.7µs
59.3µs
86.6µs
121.2µs
173µs
208µs
252µs
Power Good Time-Out
At the end of the time-out period, the PGI pin is sampled.
M12 is turned on to discharge CPGT to ground. If the PGI
pin is low when sampled, the DC/DC converters have not
entered into regulation on time and the power good circuit
trips the circuit breaker to latch off the board. If PGI is high
when sampled, the converters powered up into regulation
on time and the board is left powered up. The power good
glitch filter is enabled and it monitors the PGI pin for a low,
anindicationthatatleastoneDC/DCconverterhasdropped
out of regulation. The glitch filter rejects low pulses
shorter than a programmable period.
Soft-Start or Inrush Current Control
Power Good Glitch Filter
The LTC4212 monitors the load current by sensing the
voltage (VCC – VSENSE) developed across an external
sense resistor (RSENSE) connected between the VCC and
SENSE pins. During the second timing cycle (see Normal
Operating Sequence) a soft-start circuit turns on the
external N-channel FET gradually to keep inrush currents
in check. The soft-start circuit monitors and servos the
voltage across RSENSE to 50mV by either connecting a
10µA pull-up current source to the GATE pin when the
voltage across RSENSE is less than 50mV or discharging it
with a 10µA pull-down current source when the voltage
rises above 50mV. Therefore, the inrush current from the
backplane supply is limited to:
A glitch filter consisting of COMP5, M5 and a 5µA current
source rejects PGI low pulses that are shorter than the
duration programmed by an external capacitor, CPGF
,
connected from the PGF pin to GND.
Once the glitch filter is enabled, M5 is switched off
whenever PGI goes low. This allows an internal 5µA
current source to charge the capacitor at the PGF pin. If
PGI stays low for long enough, the voltage at the PGF pin
rises above the upper threshold of COMP5 (1.236V) and
causes the power good circuit to trip the circuit breaker.
For a given CPGF capacitance connected between PGF and
GND, the minimum low PGI pulse width needed to trip the
circuit breaker is given by:
ILIMIT(SOFTSTART) = 50mV/RSENSE
(5)
tPGF = 1.236V • (CPGF)/5µA + 5µs
(4)
Forexample,ILIMIT(SOFTSTART) =5AwhenRSENSE =0.01Ω.
An internal 5pF capacitor and stray MSOP-10 package
capacitance sets tPGF to 5µs nominal when CPGF is omit-
ted. Table 3 shows tPGF values for various standard
capacitors. Tying the PGF pin to ground prevents the
power good glitch filter from tripping the circuit breaker
after normal power-up.
Assuming that the voltage across the sense resistor does
not exceed 50mV, the voltage at the GATE pin rises at rate
given by:
VGATE Slew Rate = dVGATE/dt =10µA/CGATE
(6)
where, CGATE = Power MOSFET gate input capacitance
(CISS).
For example, an Si4410DY (a 30V N-channel power
MOSFET) exhibits an approximate CGATE of 3300pF at
4212f
12
LTC4212
U
OPERATIO
VGS = 10V. From Equation 6, the slew rate is calculated to
be 3.03V/ms.
VCB) is greater than 50mV for 18µs. The FAST COMP trips
thecircuitbreakertoprotectagainstfastloadovercurrents
if the transient voltage across the sense resistor is greater
than 150mV for 500ns.
The inrush current being delivered to the load while the
GATE pin is ramping depends on CLOAD and CGATE. The
external N-channel MOSFET acts as a source follower so
that its source (load) voltage ramps up at the same rate as
the GATE pin. The output current component for capacitor
charging is given by Equation 7:
The timing diagram of Figure 2 illustrates when the
LTC4212’s electronic circuit breaker is armed. After the
first timing cycle, the LTC4212’s FAST COMP is armed at
Time Point 6. This ensures that the system is protected
againstashort-circuitconditionduringthesecondtiming
cycle after CLOAD has been fully charged. At Time Point 8,
SLOW COMP is armed when the internal control loop is
disengaged.
I
INRUSH = CLOAD • dVGATE/dt
(7)
=10µA • CLOAD/CGATE
where, CLOAD is the total capacitance at the load side of the
MOSFET. For example, if CGATE = 3300pF and
CLOAD = 2000µF, the inrush current charging CLOAD is
6.06A. Note that the soft-start circuit will servo the inrush
to ILIMIT(SOFTSTART) or 5A in this example and dVGATE/dt
will be lower than calculated from Equation 6.
The timing diagram in Figure 4 illustrates the operation of
the LTC4212 when the load current conditions exceed the
threshold of SLOW COMP (VCB(SLOW) > 50mV).
Circuit Breaker Reset
Referring to the Block Diagram, the ON pin drives two
internal comparators, COMP1 and COMP2. COMP1 is
referenced to 1.236V and has a hysterisis of 80mV.
COMP2isreferencedto0.5Vandhasahysterisisof45mV.
The outputs of the two comparators drive an internal flip-
flop to generate a typical high and low ON pin threshold of
1.31V and 0.455V respectively.
Frequency Compensation at Soft-Start
If the external MOSFET’s gate input capacitance (CISS) is
greater than 600pF, no external gate capacitor is required
at GATE to stabilize the internal current-limiting loop
during soft-start. Otherwise, connect a gate capacitor
betweentheGATEpinandgroundtoincreasethetotalgate
capacitance to be equal to or above 600pF. The servo loop
that controls the external MOSFET during current limiting
has a unity-gain frequency of about 105kHz and phase
margin of 80° for external MOSFET gate input capaci-
tances of up to 2.5nF.
IfthevoltageattheONpinisdrivenbelow0.455Vformore
than 10µs, all internal control logic except the circuit
breaker is reset. A 200µA pull-down current source is
connected to the GATE pin to pull it down gradually.
Holding the ON pin below 0.455V for 120µs or longer,
resetsthecircuitbreaker.Followingreset,theONpinmust
be taken above 1.316V to start a power-up sequence.
Electronic Circuit Breaker
The LTC4212 features an electronic circuit breaker func-
tion that protects against supply overvoltage, externally-
generatedfaultconditions,shortsorexcessiveloadcurrent
conditions and power good faults. If the circuit breaker
trips, the GATE pin is immediately pulled to ground, the
external N-channel MOSFET is quickly turned OFF and
FAULT is latched low.
Normal Operating Sequence
Figure 2 illustrates the normal power-up sequence for two
different applications. The PGI (RST) and PGF (RST)
waveformsarevalidforapplicationswhichusethePGIpin
to monitor the RST output of a supply monitor IC. The PGI
(PGOOD) and PGF (PGOOD) waveforms refer to applica-
tions that tie the PGI pin to the PGOOD output
of a DC/DC converter. All other waveforms in Figure 2
are common to both applications. The PGI and PGF
waveforms for applications that connect PGI pin to the
The circuit breaker trips whenever the voltage across the
sense resistor exceeds two different levels, set by the
LTC4212’s SLOW COMP and FAST COMP thresholds (see
BlockDiagram). The SLOWCOMPtripsthecircuit breaker
if the voltage across the SENSE resistor (VCC – VSENSE
=
4212f
13
LTC4212
U
OPERATIO
CHECK FOR GATE < 0.2V
GLITCH FILTER TRIPS BREAKER
ON GOES LOW
CHECK FOR FAULT HIGH
FAST COMP ARMED
LOGIC RESET
(200µA GATE PULLDOWN)
SLOW COMP & POWER GOOD CIRCUIT ARMED
PGI SAMPLED
CIRCUIT BREAKER RESET
18
17
1 2
3
4
5
6
7
8
9
10
11 12
13 14
15
16
19 20
21
2V TO 34V
V
CC
ON
TIMER
GATE
V
V
REF
REF
1ST TIMING
CYCLE (C
2ND TIMING
CYCLE (C
1ST TIMING
CYCLE (C
TIMER
)
)
)
TIMER
TIMER
SOFT-START
ACTIVE
DC/DC
CONVERTER
OUTPUT
V
CC
FAULT
0.95V
0.65V
PGT
POWER GOOD
TIME-OUT CYCLE
(C
)
PGT
PGI
(RST)
200ms
MONITOR DELAY
1.236V
PGF
(RST)
PGI
(PGOOD)
1.236V
PGF
(PGOOD)
NORMAL POWER-UP SEQUENCE
POWER GOOD GLITCH
FILTER SEQUENCE
ECB RESET
SEQUENCE
4212 F02
Figure 2. Normal Power-Up, Power Good Glitch Filter and ECB Reset Sequences
4212f
14
LTC4212
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OPERATIO
comparator outputs of a supply monitor such as the
LTC1727 are similar to PGI (PGOOD) and PGF (PGOOD).
applications where PGI monitors the RST output of a
supply monitor like the LTC1326-2.5, the RST and there-
forethePGIpinsareheldlowforanother200msuntilTime
Point 11 (see PGI (RST) waveform). At Time Point 12, the
power good circuit samples the PGI pin. During normal
power-up, PGI will go high before Time Point 12. The
power good circuit disables and resets the power good
timer and M12 is turned ON to pull PGT to ground. The
power good glitch filter is then enabled to monitor the
PGI pin.
First Timing Cycle
When the PC board makes contact with the backplane
(Time Point 1), VCC starts to rise. While VCC < 2.23V, the
LTC4212 is in UVLO mode. The GATE pin is pulled to
ground by a 200µA current source to shut off the external
N-channel MOSFET and the TIMER, PGT and PGF pins are
allpulledlowbyinternalN-channelFETsM6, M5andM12.
When VCC rises above the UVLO threshold of 2.34V (Time
Point 2), the LTC4212 waits for the ON pin to go high ( >
1.316V) and checks that the GATE is low (VGATE < 0.2V)
before initiating the first timing cycle (Time Point 3).
Power Good Glitch Filter Sequence
The power good glitch filter sequence is also shown in
Figure 2 from Time Points 12 through 16. When the glitch
filterisenabled,M5,theinternalN-channelFETthatshorts
the PGF pin to GND is switched OFF whenever PGI is low.
This allows the CPGF capacitor to be charged by an internal
5µA current source towards 1.236V. If the PGF pin voltage
exceeds 1.236V, the power good circuit trips the circuit
breakertolatchthepartoff. TyingPGFtoGNDdisablesthe
glitch filter and prevents the power good from tripping the
circuit breaker after Time Point 12.
ThefirsttimingcyclebeginswiththeTIMERpinupatarate
given by Equation 1. At Time Point 4 (the timing period
programmed by CTIMER), the TIMER pin voltage equals
VTMR = 1.236V. Next the TIMER pin is pulled down by M6
to Time Point 5 where VTMR = 0.2V. At Time Point 5, the
LTC4212checksthattheFAULTpinvoltageishigh(VFAULT
> 1.236V) before initiating the second timing cycle. If
FAULT is forced low externally, the second timing cycle
will not start and the external N-channel FET stays OFF.
For supply monitors such as the LTC1326-2.5, the glitch
filter is less useful. The comparators in the LTC1326-2.5
thatmonitortheDC/DCconvertershaveatypicalpropaga-
tion delay of 13µs. If any of the monitored supplies leave
regulation for more than 13µs, the RST signal will be
pulled low until 200ms after all the supplies re-enter
regulation. The net effect is that the LTC1326-2.5 per-
forms the glitch filtering and rejects pulses shorter than
13µs. The PGOOD output of a DC/DC converter does not
have the 200ms delay of the LTC1326-2.5. Thus any low
PGOOD pulse will immediately cause CPGF to be charged
towards 1.236V (Time Points 13 and 14). CPGF values can
be selected to reject low pulses that are shorter than some
desired pulse width.
Second Timing Cycle
Atthebeginningofthesecondtimingcycle(TimePoint6),
the LTC4212 FAST COMP is armed and the soft-start
circuit is enabled. The GATE pin is ramped up at a rate
givenbyEquation6.Iftheinrushcurrentfromthebackplane
supply (Equation 7) is large enough to cause the voltage
drop across the sense resistor to exceed 50mV, the soft-
start circuit activates to regulate the inrush current (Equa-
tion 5). The soft-start circuit continues to operate until
Time Point 8 when the TIMER pin voltage equals VTMR
1.236V again. At Time Point 8, SLOW COMP is armed and
the power good circuit is enabled.
=
Some supply monitor ICs such as the LTC1727 provide
accesstotheoutputsofcomparatorsmonitoringtheDC/DC
converters as well as the RST output. The comparator
outputs track the converter output voltages. If the LTC4212
PGIpinisusedtomonitortheoutputofacomparatorrather
than the RST output of the LTC1727, CPGF can be selected
to reject low pulses shorter than a desired pulse width.
When the power good circuit is enabled, M12, the internal
N-channel FET shorting the PGT pin to ground is switched
OFFandthepowergoodtimerstarted.TheDC/DCconvert-
ers enter regulation at Time Point 10. In applications
where the PGI pin is connected to the PGOOD pin of a DC/
DCconverter, PGIispulledhighshortlyaftertheconverter
enters into regulation (see PGI (PGOOD) waveform). In
4212f
15
LTC4212
U
OPERATIO
Electronic Circuit Breaker (ECB) Reset Sequence
150mV, SLOW COMP trips the ECB (Time Point 10). If the
voltage across RSENSE jumps above 150mV for 500ns or
more, FAST COMP will trip the ECB.
The ECB reset sequence is shown in Figure 2 from Time
Points17through19. AtTimePoint17, theONpinistaken
low. Ten microseconds later at Time Point 18, the internal
logicisresetanda200µAsourceisconnectedtotheGATE
pin to pull the pin to ground. 120µs after ON goes low
(TimePoint19), theECBisreset. WhentheONpinistaken
high at Time Point 20 a new first timing cycle is started. If
the time from Time Point 17 to Time Point 18 is less than
120µs, the ECB is not reset and taking the ON pin high at
Time Point 20 will not start a new first timing cycle.
When the ECB trips, the GATE pin is driven to GND
immediately to shut off the external N-channel FET and
disconnect the board from the backplane supply. The
FAULT pin is latched to a low state and the power good
circuit is reset. The PGT and PGF pins are shorted to
ground by internal N-channel FETs. In order to reset the
fault latch, the ON pin must be taken low for more than
120µs (Time Points 12 to 14). After that, taking the ON pin
high (Time Point 15) starts a new power-up sequence.
Power Good Timeout Fault Sequence
Autoretry Sequence
Figure 3 shows a power-up sequence in which the DC/DC
converters do not enter regulation on time and the power
good trips the ECB. The sequence is the same as for the
normal power-up in Figure 2 until Time Point 12 when the
power good timer times out and the PGI pin is sampled.
Since PGI is low, the power good circuit trips the ECB. The
GATE pin is pulled to ground immediately to disconnect
power to the board and the FAULT pin is latched to a
low state. The PGT and PGF pins are pulled to GND
internally by N-channel FETs. To reconnect the board to
the backplane supply, the ON pin must be taken low for at
least 120µs to reset the ECB and then high again to start
a new first timing cycle.
Once the circuit breaker trips, the LTC4212 can be config-
uredtoautoretrythatisattempttoreconnectthebackplane
supply automatically. Both FAULT and ON pins are tied
together to an external pull-up resistor to VCC (RAUTO) and
to a delay capacitor (CAUTO) as shown in Figure 5.
Figure 6 shows two autoretry sequences caused by a
persistent short. When the circuit breaker trips (Time
Point 9), an internal N-channel FET at the FAULT pin is
turned on to pull the pin low. This discharges the autoretry
capacitor, CAUTO towards ground. When the ON pin volt-
age drops below 0.455V for 10µs (from Time Point 10),
internal logic is reset and a 200µA current source is
connected to the GATE pin. The GATE pin is already pulled
down to ground at Time Point 9. The circuit breaker is not
Overcurrent Fault Sequence
Figure 4 shows a power-up sequence with SLOW COMP
tripping the ECB. At the beginning of the second timing
cycle(TimePoint6), theGATEpinisconnectedtothesoft-
start circuit and FAST COMP is armed but it does not
usually trip the ECB due to the action of the soft-start
circuit on the GATE pin. The soft-start circuit regulates the
voltage across the RSENSE resistor to 50mV. At Time
Point 8, the soft-start circuit is disconnected. A 10µA
current source pulls the GATE pin up and SLOW COMP is
armed. If a short occurs and the voltage across RSENSE
jumps above 50mV for more than 18µs but is less than
reset so that the FAULT pin continues to discharge CAUTO
.
After the ON pin has dropped below 0.455V for more than
120µs (Time Point 11), the circuit breaker is reset. The
N-channel FET at the FAULT pin is switched off and the
pull-up resistor at the ON pin starts to charge CAUTO
towards the upper 1.316V threshold of the ON pin. Once
the ON pin voltage rises above 1.316V, the first timing
cycleisstarted. Thetotalcoolingoffperiodfortheexternal
N-channel FET starts at Time Point 9 when the circuit
breaker trips to Time Point 15 when the second timing
cycle is started.
4212f
16
LTC4212
U
OPERATIO
CHECK FOR GATE < 0.2V
CHECK FOR FAULT HIGH
FAST COMP ARMED
ON GOES LOW
LOGIC RESET
(200µA GATE PULLDOWN)
SLOW COMP & POWER GOOD CIRCUIT ARMED
PGI SAMPLED
CIRCUIT BREAKER RESET
15
14
1 2
3
4
5
6
7
8
9
10
11 12
13
16 17
19
2.34V
V
CC
ON
TIMER
GATE
V
REF
V
V
REF
REF
2ND TIMING
CYCLE (C
1ST TIMING
CYCLE (C
)
)
TIMER
TIMER
SOFT-START
ACTIVE
V
OUT
DC/DC
CONVERTER
OUTPUT
(RST)
< 200ms
V
OUT
DC/DC
CONVERTER
OUTPUT
(PGOOD)
V
CC
FAULT
0.95V
0.65V
PGT
PGI
POWER GOOD
TIME-OUT CYCLE
(C
)
PGT
PGF
POWER GOOD TIMEOUT FAULT SEQUENCE
ECB RESET
SEQUENCE
4212 F03
Figure 3. Power Good Time-Out Fault and ECB Reset Sequence
4212f
17
LTC4212
U
OPERATIO
It consists of the time the FAULT pin takes to discharge Sense Resistor Considerations
C
AUTO (TimePoints9 to10), the120µs needed to resetthe
The fault current level at which the LTC4212’s internal
electronic circuit breaker trips is determined by a sense
resistorconnectedbetweentheLTC4212’sVCC andSENSE
pins and two separate trip points. The first trip point is set
circuit breaker (Time Points 9 to 11), the time it takes the
pull-up resistor at the ON pin to charge CAUTO above
1.316V (Time Points 11 to 12) and the elapsed time before
theexternalN-channelstartstoconductduringthesecond
timing cycle (Time Points 12 to 16).
3
1
2
4
5
6
7
8
9
10 11
1213 1415
16
2.34V
V
CC
ON
V
V
V
REF
REF
REF
TIMER
GATE
1ST TIMING
CYCLE (C
2ND TIMING
CYCLE (C
1ST TIMING
CYCLE (C )
TIMER
)
)
TIMER
TIMER
SOFT-START
ACTIVE
> 50mV, >18µs
V
– V
= 50mV
SENSE
CC
V
CC
– V
SENSE
DC/DC
CONVERTER
OUTPUT
V
CC
FAULT
0.95V
0.65V
PGT
PGI
POWER GOOD TIMER
ENABLED (C
)
PGT
PGF
4212 F04
Figure 4. Power-Up with Overcurrent, Slow Comparator Trips the Circuit Breaker
4212f
18
LTC4212
U
OPERATIO
BACKPLANE
CONNECTOR CONNECTOR
(FEMALE) (MALE)
EDGE
R
M1
Si4410DY
SENSE
0.007Ω
V
CC
5V
5V
+
1
1
3
+
R
X
2.5V
1.5A
LT1963-2.5
Z1
10µF
10Ω
X
+
+
R
G
2
C
10nF
10µF
10µF
100Ω
9
8
7
R
AUTO
1M
V
SENSE
LTC4212
PGT
GATE
3
+
CC
1
3.3V
1.5A
LT1963-3.3
ON
R4
10k
2
10µF
10µF
C
AUTO
2µF
R5
10
5
6
10k
PGI
PGF
FAULT
GND
3
6
1
V
CCA
V
CC3
R6
2.1k
TIMER
LTC1326-2.5
RST
2
2
3
4
V
CC25
C
C
C
PGF
18pF
TIMER
0.01µF
PGT
180nF
GND
4
GND
4212 F05
Z1 = SMAJ10A (TVS)
Figure 5. LTC4212 Autoretry Application
3
1 2
4
5
6
7
8
9
10
11 12
131415
16 17
18 19
2.34V
CC
V
1.316V
1.31V
ON
0.455V
0.455V
V
REF
V
V
REF
V
REF
REF
TIMER
GATE
1ST
2ND
1ST
2ND
TIMING
CYCLE (C
TIMING
TIMING
TIMING
CYCLE (C
)
CYCLE (C
)
CYCLE (C
)
)
TIMER
TIMER
TIMER
TIMER
SOFT-START ACTIVE
SOFT-START ACTIVE
> 50mV, > 18µs
> 50mV, > 18µs
V
CC
– V
SENSE
50mV
=
V
– V
SENSE
50mV
=
CC
V
– V
SENSE
CC
DC/DC
CONVERTER
OUTPUT
FAULT
0.95V
0.65V
0.95V
0.65V
PGT
PGI
POWER GOOD
POWER GOOD
TIMER ENABLED
TIMER ENABLED
(C
PGT
)
(C )
PGT
PGF
4212 F06
Figure 6. Autoretry Sequence
4212f
19
LTC4212
U
OPERATIO
by the SLOW COMP’s threshold, VCB(SLOW) = 50mV, and
occurs should a load current fault condition exist for more
than 18µs. The current level at which the electronic circuit
breaker trips is given by Equation 8:
Calculating Circuit Breaker Trip Current
For a selected RSENSE value, the nominal load current that
trips the circuit breaker is given by Equation 10:
VCB(SLOW)
50mV
RSENSE
IRC-TT SENSE RESISTOR
ITRIP(SLOW)
=
=
(8)
CURRENT FLOW
TO LOAD
LR251201R010F
OR EQUIVALENT
0.01Ω, 1%, 1W
CURRENT FLOW
TO LOAD
RSENSE
ThesecondtrippointissetbytheFASTCOMP’sthreshold,
VCB(FAST) = 150mV, and occurs during fast load current
transients that exist for 500ns or longer. The current level
at which the circuit breaker trips in this case is given by
Equation 9:
TRACK WIDTH W:
0.03" PER AMP
W
ON 1 OZ COPPER
4212 F07
TO
CC
TO
SENSE
V
VCB(FAST)
150mV
RSENSE
ITRIP(FAST)
=
=
(9)
Figure 7. Making PCB Connections to the Sense Resistor
RSENSE
As a design aid, the currents at which electronic circuit
breaker trips for common values for RSENSE are shown in
Table 4.
VCB(NOM)
50mV
ITRIP(NOM)
=
=
(10)
RSENSE(NOM) RSENSE(NOM)
Table 4. ITRIP(SLOW) and ITRIP(FAST) vs RSENSE
The minimum load current that trips the circuit breaker is
given by Equation 11.
R
SENSE
I
I
TRIP(FAST)
TRIP(SLOW)
0.005Ω
0.006Ω
0.007Ω
0.008Ω
0.009Ω
0.01Ω
10A
30A
8.3A
7.1A
6.3A
5.6A
5A
25A
21A
19A
17A
15A
VCB(MIN)
RSENSE(MAX) RSENSE(MAX)
40mV
ITRIP(MIN)
where
RSENSE(MAX) = RSENSE(NOM) • 1+
=
=
(11)
RTOL
100
For proper circuit breaker operation, Kelvin-sense PCB
connectionsbetweenthesenseresistorandtheLTC4212’s
VCC and SENSE pins are strongly recommended. The
drawing in Figure 7 illustrates the correct way of making
connections between the LTC4212 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
The maximum load current that trips the circuit breaker is
given in Equation 12.
VCB(MAX)
60mV
ITRIP(MAX)
=
=
RSENSE(MIN) RSENSE(MIN)
(12)
The power rating of the sense resistor should accommo-
date steady-state fault current levels so that the compo-
nent is not damaged before the circuit breaker trips.
Table 5 in the Appendix lists sense resistors that can be
used with the LTC4212’s circuit breaker.
where
RSENSE(MIN) = RSENSE(NOM) • 1–
RTOL
100
4212f
20
LTC4212
U
OPERATIO
For example:
external MOSFET should have a ±VGS(MAX) rating that is
higher than the operating input supply voltage to ensure
that the external MOSFET is not destroyed by a negative
VGS voltage. In addition, the ±VGS(MAX) rating of the
MOSFET must be higher than the gate overdrive voltage.
Lower ±VGS(MAX) rating MOSFETs can be used with the
LTC4212 if the GATE overdrive is clamped to a lower
voltage. The circuit in Figure 8 illustrates the use of zener
diodes to clamp the LTC4212’s GATE overdrive signal if
lower voltage MOSFETs are used.
If a sense resistor with 7mΩ ±5% RTOL is used for current
limiting, the nominal trip current ITRIP(NOM) = 7.1A. From
Equations 11 and 12, ITRIP(MIN) = 5.4A and ITRIP(MAX)
9.02A respectively.
=
For proper operation and to avoid the circuit breaker
tripping unnecessarily, the minimum trip current
(ITRIP(MIN)) must exceed the circuit’s maximum operating
load current. For reliability purposes, the operation at the
maximum trip current (ITRIP(MAX)) must be evaluated
carefully. If necessary, two resistors with the same RTOL
can be connected in parallel to yield an RSENSE(NOM) value
that fits the circuit requirements.
R
Q1
SENSE
V
V
OUT
CC
D1*
D2*
R
G
200Ω
GATE
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED)
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
Power MOSFET Selection Criteria
4212 F08
To start the power MOSFET selection process, choose the
maximum drain-to-source voltage, VDS(MAX), and the
maximum drain current, ID(MAX) of the MOSFET. The
VDS(MAX) rating must exceed the maximum input supply
voltage (including surges, spikes, ringing, etc.) and the
ID(MAX) rating must exceed the maximum short-circuit
current in the system during a fault condition. In addition,
consider three other key parameters: 1) the required gate-
source (VGS) voltage drive, 2) the voltage drop across the
drain-to-source on resistance, RDS(ON) and 3) the maxi-
mum junction temperature rating of the MOSFET.
Figure 8. Optional Gate Clamp for Lower VGS(MAX) MOSFETs
The RDS(ON) of the external pass transistor should be low
to make its drain-source voltage (VDS) a small percentage
of VCC. At a VCC = 2.5V, VDS + VRSENSE = 0.1V yields 4%
error at the output voltage. This restricts the choice of
MOSFETs to very low RDS(ON). At higher VCC voltages, the
VDS requirement can be relaxed in which case MOSFET
package dissipation (PD and TJ) may limit the value of
RDS(ON). Table 6 lists some power MOSFETs that can be
used with the LTC4212.
Power MOSFETs are classified into two categories: stan-
dard MOSFETs (RDS(ON) specified at VGS = 10V) and
logic-level MOSFETs (RDS(ON) specified at VGS = 5V). The
absolute maximum rating for VGS is typically ±20V for
standard MOSFETs. However, the VGS maximum rating
for logic-level MOSFETs ranges from ±8V to ±20V de-
pending upon the manufacturer and the specific part
number. The LTC4212’s GATE overdrive as a function of
VCC isillustratedintheTypicalPerformancecurves.Logic-
level MOSFETs are recommended for low supply voltage
applicationsandstandardMOSFETscanbeusedforappli-
cations where supply voltage is greater than 4.75V.
For reliable circuit operation, the maximum junction tem-
perature (TJ(MAX)) for a power MOSFET should not exceed
the manufacturer’s recommended value. This includes
normal mode operation, start-up, current-limit and
autoretry mode in a fault condition. Under normal condi-
tionsthejunctiontemperatureofapowerMOSFETisgiven
by Equation 13:
Note that in some applications, the gate of the external
MOSFET can discharge faster than the output voltage
when the circuit breaker is tripped. This causes a negative
MOSFET Junction Temperature,
J(MAX) ≤ TA(MAX) + θJA • PD
T
(13)
V
GS voltage on the external MOSFET. Usually, the selected
4212f
21
LTC4212
U
OPERATIO
where
of this data sheet. In this case, the LTC4212 is mounted
on thePCBand a20k/10kresistivedividerisconnected to
the ON pin. On the edge connector, R1 is wired to a short
pin.Untiltheconnectorsarefullymated,theONpinisheld
low, keeping the LTC4212 in an off state. Once the
connectors are mated, the resistive divider is connected
to VCC, VON > 1.316V and the LTC4212 begins a start-up
cycle.
PD = (ILOAD)2 • RDS(ON)
θJA = junction-to-ambient thermal resistance
TA(MAX) = maximum ambient temperature
If a short circuit happens during start-up, the external
MOSFET can experience a big single pulse energy. This is
especially true if the applications only employed a small
gate capacitor or no gate capacitor at all. Consult the safe
operating area (SOA) curve of the selected MOSFET to
ensure that the TJ(MAX) is not exceeded during start-up.
PCB Layout Considerations
For proper operation of the LTC4212’s circuit breaker
function, a 4-wire Kelvin connection to the sense resistors
is highly recommended. In Hot Swap applications where
load currents can reach 10A or more, narrow PCB tracks
exhibit more resistance than wider tracks and operate at
more elevated temperatures. Since the sheet resistance of
1 ounce copper foil is approximately 0.54mΩ/square,
track resistances add up quickly in high current applica-
tions. Thus, to keep PCB track resistance and temperature
rise to a minimum, PCB track width must be appropriately
sized. Consult Appendix A of LTC Application Note 69 for
details on sizing and calculating trace resistances as a
function of copper thickness.
Using Staggered Pin Connectors
The LTC4212 can be used on either a printed circuit board
or on the backplane side of the connector. Printed circuit
board edge connectors with staggered pins are recom-
mended as the insertion and removal of circuit boards do
sequence the pin connections. Supply voltage and ground
connections on the printed circuit board should be wired
to the edge connector’s long pins or blades. Control and
status signals (like FAULT and ON) passing through the
card’sedgeconnectorshouldbewiredtoshortlengthpins
or blades.
In the majority of applications, it will be necessary to use
plated-through vias to make circuit connections from
component layers to power and ground layers internal to
the PC board. For 1 ounce copper foil plating, a good
starting point is 1A of DC current per via, making sure the
via is properly dimensioned so that solder completely fills
any void. For other plating thicknesses, check with your
PCB fabrication facility.
PCB Connection Sense
There are a number of ways to use the LTC4212’s ON pin
to detect whether the printed circuit board has been fully
seated in the backplane before the LTC4212 commences
a start-up cycle.
An example is shown in the schematic on the front page
U
APPE DIX
Table5listssomecurrentsenseresistorsthatcanbeused
withthecircuitbreaker.Table6listssomepowerMOSFETs
that are available. Table 7 lists the web sites of several
manufacturers.Sincethisinformationissubjecttochange,
please verify the part numbers with the manufacturer.
Table 5. Sense Resistor Selection Guide
CURRENT LIMIT VALUE
PART NUMBER
LR120601R050
LR120601R025
LR120601R020
WSL2512R015F
LR251201R010F
WSR2R005F
DESCRIPTION
MANUFACTURER
IRC-TT
1A
0.05Ω 0.5W 1% Resistor
0.025Ω 0.5W 1% Resistor
0.02Ω 0.5W 1% Resistor
0.015Ω 1W 1% Resistor
0.01Ω 1.5W 1% Resistor
0.005Ω 2W 1% Resistor
2A
IRC-TT
2.5A
3.3A
5A
IRC-TT
Vishay-Dale
IRC-TT
10A
Vishay-Dale
4212f
22
LTC4212
U
APPE DIX
Table 6. N-Channel Selection Guide
CURRENT LEVEL (A)
PART NUMBER
DESCRIPTION
MANUFACTURER
0 to 2
MMDF3N02HD
MMSF5N02HD
MTB50N06V
Dual N-Channel SO-8
ON Semiconductor
ON Semiconductor
ON Semiconductor
ON Semiconductor
R
= 0.1Ω, C = 455pF
DS(ON)
ISS
2 to 5
Single N-Channel SO-8
= 0.025Ω, C = 1130pF
R
DS(ON)
ISS
5 to 10
10 to 20
Single N-Channel DD Pak
= 0.028Ω, C = 1570pF
R
DS(ON)
ISS
MTB75N05HD
Single N-Channel DD Pak
= 0.0095Ω, C = 2600pF
R
DS(ON)
ISS
Table 7. Manufacturers’ Web Sites
MANUFACTURER
TEMIC Semiconductor
International Rectifier
ON Semiconductor
Harris Semiconductor
IRC-TT
WEB SITE
www.temic.com
www.irf.com
www.onsemi.com
www.semi.harris.com
www.irctt.com
Vishay-Dale
www.vishay.com
www.vishay.com
www.diodes.com
Vishay-Siliconix
Diodes, Inc.
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
0.497 ± 0.076
(.0196 ± .003)
10 9
8
7 6
REF
5.23
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
3.20 – 3.45
(.206)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.126 – .136)
MIN
(.010)
0° – 6° TYP
GAUGE PLANE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
1
2
3
4 5
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
PLANE
NOTE:
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MS) 0603
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
0.50
(.0197)
BSC
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
4212f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC4212
U
TYPICAL APPLICATIO
Monitoring DC/DC Converters with the LTC1326-2.5 Supply Monitor
BACKPLANE
CONNECTOR CONNECTOR
(FEMALE) (MALE)
EDGE
R
M1
Si4410DY
SENSE
0.007Ω
V
CC
5V
5V
+
1
1
3
+
R
X
2.5V
1.5A
LT1963-2.5
Z1
10µF
10Ω
X
+
+
2
C
10µF
10µF
100nF
9
8
7
V
SENSE
LTC4212
PGT
GATE
3
+
R1 10k
CC
1
3.3V
1.5A
LT1963-3.3
ON
R4
10k
2
R3
10k
R2
20k
10µF
10µF
R5
10
5
6
10k
FAULT
GND
PGI
FAULT
GND
3
6
1
V
CCA
V
CC3
R6
2.1k
TIMER
PGF
4
LTC1326-2.5
RST
2
2
3
V
C
C
C
PGF
18pF
CC25
TIMER
PGT
0.01µF
180nF
GND
4
4212 TA02
Z1 = SMAJ10A (TVS)
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1421
Two Channels, Hot Swap Controller
Single Channel, Hot Swap Controller
Negative Voltage Hot Swap Controller
Single Channel, Hot Swap Controller
Operates from 3V to 12V and Supports –12V
Operates from 2.7V to 12V
LTC1422
LT1640AL/LT1640AH
LTC1642
Operates from –10V to –80V
Overvoltage Protection and Foldback Current Limit
3.3V, 5V and ±12V for PCI and CPCI
LTC1643AL/LTC1643AH PCI-Bus Hot Swap Controller
LTC1647
Dual Channel, Hot Swap Controller
Single Channel, Hot Swap Controller
Single Channel, Hot Swap Controller
Triple Channel, Hot Swap Controller
PCI-Bus Hot Swap Controller
Operates from 2.7V to 16.5V
LTC4210-1/LTC4210-2
LTC4211
Hot Swap Controller with Active Current Limiting
Overvoltage and Overcurrent Protection
LTC4230
Triple Hot Swap Controller with Multifunction Current Control
With 3.3V Auxiliary Standby Channel
LTC4241
LTC4251/LTC4251-1/
LTC4251-2
–48V Voltage Hot Swap Controller
Negative Voltage Hot Swap Controller in SOT-23
LTC4252
LTC4253
–48V Hot Swap Controller
–48V Hot Swap Controller in 8-Pin or 10-Pin MSOP
Triple Power Supply Sequenced –48V Hot Swap Controller –48V Hot Swap Controller with Triple Supply Sequencing
in 16-Pin SSOP
LT4256-1/LT4256-2
Positive Voltage Hot Swap Controller
Operates from 10.8V to 80V, Autoretry/Latch Off
4212f
LT/TP 0304 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
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