LTC4217CFE-PBF [Linear]
2A Integrated Hot Swap Controller; 2A集成热插拔控制器
| 型号： | LTC4217CFE-PBF |
| 厂家： | 
Linear |
| 描述： | 2A Integrated Hot Swap Controller |
| 文件： | 总18页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4217
2A Integrated Hot Swap
Controller
FEATURES
DESCRIPTION
n
Small Footprint
The LTC®4217 is an integrated solution for Hot Swap™
applications that allows a board to be safely inserted and
removed from a live backplane. The part integrates a Hot
Swapcontroller,powerMOSFETandcurrentsenseresistor
in a single package for small form factor applications. A
dedicated 12V version (LTC4217-12) contains preset 12V
specific thresholds, while the standard LTC4217 allows
adjustable thresholds.
n
33mΩ MOSFET with R
SENSE
n
Wide Operating Voltage Range: 2.9V to 26.5V
Adjustable, 5% Accurate Current Limit
Current and Temperature Monitor Outputs
Overtemperature Protection
Adjustable Current Limit Timer Before Fault
Power Good and Fault Outputs
Adjustable Inrush Current Control
2% Accurate Undervoltage and Overvoltage
Protection
Available in 20-Lead TSSOP and 16-Lead
5mm × 3mm DFN Packages
n
n
n
n
n
n
n
The LTC4217 provides separate inrush current control
and a 5% accurate 2A current limit with foldback cur-
rent limiting. The current limit threshold can be adjusted
dynamically using an external pin. Additional features
include a current monitor output that amplifies the sense
resistor voltage for ground referenced current sensing
andaMOSFETtemperaturemonitoroutput.Thermallimit,
overvoltage, undervoltage and power good monitoring
are also provided.
n
APPLICATIONS
n
RAID Systems
n
Server I/O Cards
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
n
Industrial
TYPICAL APPLICATION
Power-Up Waveforms
12V, 1.5A Card Resident Application
V
OUT
V
OUT
12V
DD
12V
+
V
12V
10k
IN
1.5A
UV
330μF
10V/DIV
AUTO
RETRY
LTC4217DHC-12
I
IN
0.1A/DIV
FLT
PG
TIMER
I
SET
V
OUT
10V/DIV
INTV
I
ADC
CC
MON
GND
0.1μF
20k
P
G
10V/DIV
4217 TA01a
4217 TA01b
25ms/DIV
4217fc
1
LTC4217
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (V ) ................................. –0.3V to 28V
Operating Temperature Range
DD
Input Voltages
LTC4217C ................................................ 0°C to 70°C
LTC4217I..............................................–40°C to 85°C
Junction Temperature (Notes 4, 5)........................ 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FB, OV, UV.............................................. –0.3V to 12V
TIMER................................................... –0.3V to 3.5V
SENSE .............................V – 10V or – 0.3V to V
DD
DD
Output Voltages
I
, I
................................................. –0.3V to 3V
FE Package Only ............................................... 300°C
SET MON
PG, FLT .................................................. –0.3V to 35V
OUT ............................................–0.3V to V + 0.3V
DD
INTV .................................................. –0.3V to 3.5V
CC
GATE (Note 3)........................................ –0.3V to 33V
PIN CONFIGURATION
LTC4217
LTC4217
LTC4217-12
TOP VIEW
TOP VIEW
SENSE
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
SENSE
V
DD
V
DD
V
1
2
3
4
5
6
7
8
16
15
14
V
I
DD
DD
UV
OV
I
UV
OV
SET
SET
I
I
MON
MON
TIMER
FB
TIMER
13 FB
21
17
SENSE
INTV
CC
FLT
INTV
CC
12 FLT
11 PG
10 GATE
SENSE
GND
OUT
OUT
PG
GND
OUT
OUT
GATE
OUT
SENSE
9
OUT
SENSE 10
DHC PACKAGE
16-LEAD (5mm s 3mm) PLASTIC DFN
FE PACKAGE
T
= 125°C, θ = 43°C/W
JMAX
JA
20-LEAD PLASTIC TSSOP
EXPOSED PAD (PIN 17) IS SENSE,
= 43°C/W SOLDERED, OTHERWISE θ = 140°C/W
T
= 125°C, θ = 38°C/W
JA
JMAX
θ
JA
JA
EXPOSED PAD (PIN 21) IS SENSE,
= 38°C/W SOLDERED, OTHERWISE θ = 130°C/W
θ
JA
JA
4217fc
2
LTC4217
ORDER INFORMATION
LEAD FREE FINISH
LTC4217CDHC-12#PBF
LTC4217IDHC-12#PBF
LTC4217CDHC#PBF
LTC4217IDHC#PBF
LTC4217CFE#PBF
LTC4217IFE#PBF
LEAD BASED FINISH
LTC4217CDHC-12
LTC4217IDHC-12
LTC4217CDHC
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4217CDHC-12#TRPBF 421712
LTC4217IDHC-12#TRPBF 421712
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
20-Lead Plastic TSSOP
–40°C to 85°C
0°C to 70°C
LTC4217CDHC#TRPBF
LTC4217IDHC#TRPBF
LTC4217CFE#TRPBF
LTC4217IFE#TRPBF
TAPE AND REEL
4217
4217
–40°C to 85°C
0°C to 70°C
LTC4217FE
LTC4217FE
PART MARKING*
421712
20-Lead Plastic TSSOP
–40°C to 85°C
TEMPERATURE RANGE
0°C to 70°C
PACKAGE DESCRIPTION
LTC4217CDHC-12#TR
LTC4217IDHC-12#TR
LTC4217CDHC#TR
LTC4217IDHC#TR
LTC4217CFE#TR
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
16-Lead (5mm × 3mm) Plastic DFN
20-Lead Plastic TSSOP
421712
–40°C to 85°C
0°C to 70°C
4217
LTC4217IDHC
4217
–40°C to 85°C
0°C to 70°C
LTC4217CFE
LTC4217FE
LTC4217FE
LTC4217IFE
LTC4217IFE#TR
20-Lead Plastic TSSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC Characteristics
l
l
l
l
l
l
l
l
l
V
Input Supply Range
2.9
26.5
3
V
mA
V
DD
I
DD
Input Supply Current
MOSFET On, No Load
1.6
2.73
9.88
640
V
V
Input Supply Undervoltage Lockout
Input Supply Undervoltage Threshold
Input Supply Undervoltage Hysteresis
Input Supply Overvoltage Threshold
Input Supply Overvoltage Hysteresis
Output Power Good Threshold
Output Power Good Hysteresis
OUT Pin Leakage Current
V
DD
Rising
2.65
9.6
2.85
10.2
760
15.4
305
10.8
213
DD(UVL)
LTC4217-12, V Rising
V
DD(UVTH)
DD
LTC4217-12
520
14.7
183
10.2
127
mV
V
ΔV
DD(UVHYST)
V
LTC4217-12, V Rising
15.05
244
DD(OVTH)
DD
LTC4217-12
mV
V
ΔV
DD(OVHYST)
OUT(PGTH)
V
LTC4217-12, V
LTC4217-12
Rising
10.5
170
OUT
mV
ΔV
OUT(PGHYST)
l
l
l
I
V
OUT
V
OUT
V
OUT
= V
= V
= V
= 0V, V = 26.5V
0
2
70
150
4
90
μA
μA
μA
OUT
GATE
GATE
GATE
DD
= 12V, LTC4217
1
50
= 12V, LTC4217-12
l
l
GATE Pin Turn-On Ramp Rate
MOSFET + Sense Resistor On Resistance
Current Limit Threshold
0.15
15
0.3
33
2
0.55
50
V/ms
mΩ
A
ΔV
/Δt
GATE
R
Note 6
ON
I
V
FB
V
FB
V
FB
V
FB
= 1.23V
1.9
2.1
LIM(TH)
l
l
l
= 1.23V
= 0V
1.85
0.35
0.85
2
2.15
0.7
A
0.5
1
A
1.17
A
= 1.23V, R = 20kΩ
SET
4217fc
3
LTC4217
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
Inputs
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
l
l
l
l
I
OV, UV, FB Pin Input Current
OV, UV, FB Pin Input Resistance
OV, UV, FB Pin Threshold Voltage
OV Pin Hysteresis
V
= 1.2V, LTC4217
0
18
1
23
μA
kΩ
V
IN
IN
R
LTC4217-12
13
1.21
10
IN
V
V
IN
Rising
1.235
20
1.26
30
TH
mV
mV
V
ΔV
ΔV
OV(HYST)
UV(HYST)
UV(RTH)
UV Pin Hysteresis
50
80
110
0.7
30
V
UV Pin Reset Threshold Voltage
FB Pin Power Good Hysteresis
V
UV
Falling
0.55
10
0.62
20
mV
kΩ
ΔV
FB(HYST)
R
I
Pin Output Resistor
SET
19.5
20
20.5
ISET
Outputs
l
l
l
l
l
l
l
l
l
l
l
V
PG, FLT Pin Output Low Voltage
PG, FLT Pin Input Leakage Current
TIMER Pin High Threshold
I
= 2mA
= 30V
0.4
0
0.8
10
V
μA
V
OL
OH
OUT
I
V
OUT
V
V
Rising
Falling
= 0V
1.2
0.1
1.235
0.21
–100
2
1.28
0.3
TIMER(H)
TIMER
V
TIMER Pin Low Threshold
V
V
TIMER(L)
TIMER
I
I
I
TIMER Pin Pull-Up Current
TIMER Pin Pull-Down Current
V
–80
1.4
–120
2.6
μA
μA
%
TIMER(UP)
TIMER
V
= 1.2V
TIMER(DN)
TIMER(RATIO)
TIMER
TIMER Pin Current Ratio I
/I
1.6
2
2.7
TIMER(DN) TIMER(UP)
A
IMON
I
I
Pin Current Gain
Pin Offset Current
I
I
= 2A
47.5
50
52.5
7.5
μA/A
μA
μA
μA
mA
MON
MON
OUT
I
I
I
I
= 132mA
0
OFF(IMON)
GATE(UP)
GATE(DN)
GATE(FST)
OUT
Gate Pull-Up Current
Gate Drive On, V
Gate Drive Off, V
= V
= 12V
OUT
–19
190
–24
250
140
–29
340
GATE
Gate Pull-Down Current
= 18V, V
= 12V
OUT
GATE
Gate Fast Pull-Down Current
Fast Turn Off, V
= 18V, V
= 12V
GATE
OUT
AC Characteristics
l
l
t
Input High (OV), Input Low (UV) to Gate Low
Propagation Delay
V
< 16.5V Falling
8
1
10
5
μs
μs
PHL(GATE)
GATE
t
Short-Circuit to Gate Low
V
= 0, Step I
to 1.2A,
SENSE
PHL(ILIM)
FB
V
< 16.5V Falling
GATE
l
l
l
t
t
t
Turn-On Delay
Step V to 2V, V
> 13V
50
1.5
50
100
2
150
2.7
ms
ms
ms
D(ON)
UV
GATE
Circuit Breaker Filter Delay Time (Internal)
Auto-Retry Turn-On Delay (Internal)
V
FB
= 0V, Step I
to 1.2A
SENSE
D(CB)
100
150
D(AUTO-RETRY)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V
above OUT. Driving this pin to voltages beyond the clamp may damage the
device.
Note 5: T is calculated from the ambient temperature, T , and power
J A
dissipation, P , according to the formula:
D
LTC4217DHC, LTC4217DHC-12: T = T + (P • 43°C/W)
J
A
D
LTC4217FE: T = T + (P • 38°C/W)
J
A
D
Note 6: For the DHC package, switch on-resistance is guaranteed by
design and test correlation.
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
4217fc
4
LTC4217
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 12V unless otherwise noted.
UV Low-High Threshold
vs Temperature
IDD vs VDD
INTVCC Load Regulation
2.0
1.8
1.6
1.4
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.234
1.232
1.230
1.228
1.226
V
= 5V
DD
V
= 3.3V
DD
85°C
25°C
–40°C
1.2
1.0
–50
–25
0
25
50
75
100
0
5
10
15
(V)
20
25
30
0
–2
–4
–6
–8 –10 –12 –14
(mA)
TEMPERATURE (°C)
V
I
DD
LOAD
4217 G01
4217 G02
4217 G03
Timer Pull-Up Current
vs Temperature
Current Limit Delay
UV Hysteresis vs Temperature
(tPHL(ILIM) vs Overdrive)
0.10
0.08
0.06
0.04
–110
–105
–100
–95
1000
100
10
1
–90
0.1
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
0
2
4
6
8
10
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT CURRENT (A)
4217 G06
4217 G04
4217 G05
Current Limit Adjustment
(IOUT vs RSET
Current Limit Threshold Foldback
)
ISET Resistor vs Temperature
2.5
2.0
1.5
1.0
2.5
2.0
1.5
1.0
22
21
20
19
18
0.5
0
0.5
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1k
10k
100k
(Ω)
1M
10M
–50
–25
0
25
50
75
100
FB VOLTAGE (V)
R
TEMPERATURE (°C)
SET
4217 G07
4217 G08
4217 G09
4217fc
5
LTC4217
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 12V unless otherwise noted.
PG, FLT VOUT Low vs ILOAD
RON vs VDD and Temperature
MOSFET SOA Curve
14
12
10
8
60
50
40
30
20
10
0
10
1
PG
FLT
V
= 3.3V, 12V, 24V
DD
1ms
10ms
6
100ms
1s
10s
DC
0.1
0.01
4
T
= 25°C
A
2
MULTIPLE PULSE
DUTY CYCLE = 0.2
0
–50
–25
0
25
50
75
100
0
2
4
6
(mA)
8
10
12
0.1
1
10
100
TEMPERATURE (°C)
I
V
(V)
LOAD
DS
4217 G12
4217 G10
4217 G11
Gate Pull-Up Current
vs Gate Drive
GATE Pull-Up Current
vs Temperature
IMON vs Temperature and VDD
7
6
5
4
3
2
1
0
105
100
95
–26.0
–25.5
–25.0
–24.5
–24.0
V
LOAD
= 3.3V, 12V, 24V
DD
V
= 12V
DD
I
= 2A
90
V
= 3.3V
DD
85
80
0
–5
–10
–15
(μA)
–20
–25
–30
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
I
TEMPERATURE (°C)
GATE
TEMPERATURE (°C)
4217 G15
4217 G14
4217 G13
Gate Drive vs VDD
Gate Drive vs Temperature
VISET vs Temperature
6.2
6.0
5.8
5.6
5.4
5.2
6.15
6.14
6.13
6.12
6.11
6.10
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0
5
10
15
(V)
20
25
30
–50
–25
0
25
50
75
100
–50 –25
0
25 50 75 100 125 150
V
TEMPERATURE (°C)
TEMPERATURE (°C)
DD
4217 G16
4217 G17
4217 G18
4217fc
6
LTC4217
PIN FUNCTIONS
FB: Foldback and Power Good Input. Connect this pin to an
externalresistivedividerfromOUTfortheLTC4217(adjust-
able)version.TheLTC4217-12versionusesafixedinternal
divider with optional external adjustment. Open the pin if
the LTC4217-12 thresholds for 12V operation are desired.
If the voltage falls below 0.6V, the current limit is reduced
using a foldback profile (see the Typical Performance
Characteristics section). If the voltage falls below 1.21V,
the PG pin will pull low to indicate the power is bad.
OV: Overvoltage Comparator Input. Connect this pin to an
externalresistivedividerfromV fortheLTC4217(adjust-
DD
able)version. TheLTC4217-12versionusesafixedinternal
dividerwithoptionalexternaladjustmentfor12Voperation.
Open the pin if the LTC4217-12 thresholds are desired. If
the voltage at this pin rises above 1.235V, an overvoltage is
detected and the switch turns off. Tie to GND if unused.
PG: Power Good Indicator. Open-drain output pulls low
whentheFBpindropsbelow1.21Vindicatingthepoweris
bad. If the FB pin rises above 1.23V and the GATE to OUT
voltage exceeds 4.2V, the open-drain pull-down releases
the PG pin to go high.
FLT: Overcurrent Fault Indicator. Open-drain output pulls
low when an overcurrent fault has occurred and the circuit
breaker trips. For overcurrent auto-retry tie to UV pin (see
the Applications Information section for details).
SENSE: Current Sense Node and MOSFET Drain. The
GATE: Gate Drive for Internal N-channel MOSFET. An
internal 24μA current source charges the gate of the
N-channel MOSFET. At start-up the GATE pin ramps up at
a 0.3V/ms rate determined by internal circuitry. During an
undervoltage or overvoltage condition a 250μA pull-down
current turns the MOSFET off. During a short-circuit or
undervoltage lockout condition, a 140mA pull-down cur-
rent source between GATE and OUT is activated.
current limit circuit controls the GATE pin to limit the
sense voltage between the V and SENSE pins to 15mV
DD
(2A) or less depending on the voltage at the FB pin. The
exposed pad on DHC and FE packages are connected to
SENSE and must be soldered to an electrically isolated
printed circuit board trace to properly transfer the heat
out of the package.
TIMER: Timer Input. Connect a capacitor between this pin
and ground to set a 12ms/μF duration for current limit
before the switch is turned off. If the UV pin is toggled
low while the MOSFET switch is off, the switch will turn
onagainfollowingacooldowntimeof518ms/μFduration.
GND: Device Ground.
I : Current Monitor Output. The current in the internal
MON
MOSFETswitchisdividedby20,000andsourcedfromthis
pin. Placinga20kresistorfromthispintoGNDcreatesa0V
to 2V voltage swing when current ranges from 0A to 2A.
Tie this pin to INTV for a fixed 2ms overcurrent delay
CC
and 100ms auto-retry time.
INTV : Internal 3V Supply Decoupling Output. This pin
CC
UV: Undervoltage Comparator Input. Tie high if unused.
must have a 0.1μF or larger bypass capacitor.
ConnectthispintoanexternalresistivedividerfromV for
DD
I
: Current Limit Adjustment Pin. For a 2A current limit
theLTC4217(adjustable)version.TheLTC4217-12version
SET
value open this pin. This pin is driven by a 20k resistor in
series with a voltage source. The pin voltage is used to
generatethecurrentlimitthreshold.Theinternal20kresistor
drives the UV pin with an internal resistive divider from
V . Open the pin if the preset LTC4217-12 thresholds for
DD
12V operation are desired. If the UV pin voltage falls below
1.15V,anundervoltageisdetectedandtheswitchturnsoff.
Pulling this pin below 0.62V resets the overcurrent fault
andallowstheswitchtoturnbackon(seetheApplications
Information section for details). If overcurrent auto-retry
is desired then tie this pin to the FLT pin.
andanexternalresistorbetweenI andgroundcreatean
SET
attenuator that lowers the current limit value. In order to
match the temperature variation of the sense resistor, the
voltage on this pin increases at the same rate as the sense
resistance increases. Therefore the voltage at I
proportional to temperature of the MOSFET switch.
pin is
SET
V : Supply Voltage and Current Sense Input. This pin
DD
OUT: Output of Internal MOSFET Switch. Connect this pin
directly to the load. In the LTC4217-12 version, the PG
comparatormonitorsaninternalresistivedividerbetween
the OUT pin and GND.
has an undervoltage lockout threshold of 2.73V.
4217fc
7
LTC4217
FUNCTIONAL DIAGRAM
SENSE
(EXPOSED PAD)
GATE
INTERNAL 7.5mΩ
SENSE RESISTOR
INTERNAL 25mΩ
MOSFET
V
OUT
DD
I
I
MON
SET
CLAMP
–
+
CHARGE
PUMP
AND GATE
DRIVER
CS
INRUSH
20k
0.6V POSITIVE
+–
0.3V/ms
TEMPERATURE
COEFFICIENT
REFERENCE
X1
OUT
FB
CM
FOLDBACK
0.6V
OUT
150k
*
V
+
DD
1.235V
+
–
140k
20k
UV
RST
OV
PG
*
20k
*
–
UV
1.235V
LOGIC
PG
*
0.62V
+
–
0.2V
+
–
V
DD
FLT
TM1
TM2
INTV
CC
224k
20k
*
OV
+
–
100μA
*
1.235V
2μA
+
–
V
DD
V
–
+
DD
1.235V
3.1V
GEN
INTV
UVLO1
CC
2.73V
–
UVLO2
TIMER
+
2.65V
4217 BD
GND
*LTC4217-12 (DFN) ONLY
4217fc
8
LTC4217
OPERATION
The Functional Diagram displays the main circuits of the
device. The LTC4217 is designed to turn a board’s supply
voltageonandoffinacontrolledmannerallowingtheboard
to be safely inserted and removed from a live backplane.
The LTC4217 includes a 25mΩ MOSFET and a 7.5mΩ cur-
rent sense resistor. During normal operation, the charge
pump and gate driver turn on the pass MOSFET’s gate to
provide power to the load. The inrush current control is
accomplished by the INRUSH circuit. This circuit limits
the GATE ramp rate to 0.3V/ms and hence controls the
voltage ramp rate of the output capacitor.
has cooled and it is safe to turn it on again. It is suitable
for many applications to use an internal 2ms overcurrent
timer with a 100ms cooldown period. Tying the TIMER
pin to INTV sets this default timing.
CC
The fixed 12V version, LTC4217-12, uses two separate
internal dividers from V to drive the UV and OV pins.
DD
This version also features a divider from OUT to drive the
FB pin. The LTC4217-12 is available in the DFN package
while the LTC4217 (adjustable version) is in the DFN and
TSSOP packages.
The output voltage is monitored using the FB pin and the
PG comparator to determine if the power is available for
the load. The power good condition is signaled by the PG
pin using an open-drain pull-down transistor.
Thecurrentsense(CS)amplifiermonitorstheloadcurrent
usingthevoltagesensedacrossthecurrentsenseresistor.
The CS amplifier limits the current in the load by reduc-
ing the GATE-to-OUT voltage in an active control loop. It
is simple to adjust the current limit threshold using the
TheFunctionalDiagramalsoshowsthemonitoringblocks
of the LTC4217. The two comparators on the left side
include the UV and OV comparators. These comparators
determineiftheexternalconditionsarevalidpriortoturning
on the MOSFET. But first the undervoltage lockout circuits
UVLO1 and UVLO2 must validate the input supply and
current setting (I ) pin. This allows a different threshold
SET
during other times such as start-up.
A short circuit on the output to ground causes significant
power dissipation during active current limiting. To limit
this power, the foldback amplifier reduces the current
limit value from 2A to 0.5A in a linear manner as the
FB pin drops below 0.6V (see the Typical Performance
Characteristics section).
the internally generated 3.1V supply (INTV ) and gener-
CC
ate the power up initialization to the logic circuits. If the
external conditions remain valid for 100ms the MOSFET
is allowed to turn on.
If an overcurrent condition persists, the TIMER pin ramps
up with a 100μA current source until the pin voltage ex-
ceeds 1.2V (comparator TM2). This indicates to the logic
that it is time to turn off the pass MOSFET to prevent
overheating. At this point the TIMER pin ramps down us-
ing the 2μA current source until the voltage drops below
0.2V (Comparator TM1) which tells the logic to start an
internal 100ms timer. At this point, the pass transistor
Other features include MOSFET current and temperature
monitoring. The current monitor (CM) outputs a current
proportionaltothesenseresistorcurrent.Thiscurrentcan
drive an external resistor or other circuits for monitoring
purposes. AvoltageproportionaltotheMOSFETtempera-
ture is output to the I
pin. The MOSFET temperature
SET
allows external circuits to predict failure and shutdown
the system.
APPLICATIONS INFORMATION
The typical LTC4217 application is in a high availability
system that uses a positive voltage supply to distribute
power to individual cards. A complete application circuit
is shown in Figure 1. External component selection is
discussed in detail in the following sections.
Turn-On Sequence
Severalconditionsmustbepresentbeforetheinternalpass
MOSFETcanbeturnedon.FirstthesupplyV mustexceed
DD
itsundervoltagelockoutlevel.Nexttheinternallygenerated
supplyINTV mustcrossits2.65Vundervoltagethreshold.
CC
This generates a 25μs power-on-reset pulse which clears
the fault register and initializes internal latches.
4217fc
9
LTC4217
APPLICATIONS INFORMATION
V
OUT
V
OUT
evident from this graph that the power dissipation at 12V,
300mA for 40ms is in the safe region.
12V
DD
12V
R5
150k
0.8A
LTC4217FE
+
R3
C
L
FB
140k
330μF
R6
UV
FLT
OV
GATE
Adding a capacitor and a 1k series resistor from GATE
to ground will lower the inrush current below the default
value set by the INRUSH circuit. The GATE is charged
with an 24μA current source (when INRUSH circuit is
not driving the GATE). The voltage at the GATE pin rises
20k
R1
224k
R
GATE
1k
12V
C
0.1μF
GATE
R2
20k
R4
20k
R7
10k
PG
I
SET
R
SET
with a slope equal to 24μA/C
and the supply inrush
20k
GATE
TIMER
current is set at:
C
T
INTV
CC
I
MON
ADC
0.1μF
C1
0.1μF
R
MON
20k
GND
CL
CGATE
I
=
•24µA
4217 F01
INRUSH
Figure 1. 0.8A, 12V Card Resident Application
When the GATE voltage reaches the MOSFET threshold
voltage, the switch begins to turn on and the OUT volt-
age follows the GATE voltage as it increases. Once OUT
Afterthepower-on-resetpulse,theLTC4217willgothrough
the following sequence. First, the UV and OV pins must
indicatethattheinputvoltageiswithintheacceptablerange.
All of these conditions must be satisfied for the duration
of 100ms to ensure that any contact bounce during the
insertion has ended.
reaches V , the GATE will ramp up until clamped by the
DD
6.15V Zener between GATE and OUT.
As the OUT voltage rises, so will the FB pin which is moni-
toring it. Once the FB pin crosses its 1.235V threshold and
theGATEtoOUTvoltageexceeds4.2V,thePGpinwillcease
to pull low and indicate that the power is good.
The MOSFET is turned on by charging up the GATE with a
charge pump generated current source whose value is ad-
justedbyshuntingaportionofthepull-upcurrenttoground.
The charging current is controlled by the INRUSH circuit
thatmaintainsaconstantslopeofGATEvoltageversustime
(Figure 2). The voltage at the GATE pin rises with a slope of
0.3V/ms and the supply inrush current is set at:
Parasitic MOSFET Oscillation
When the N-channel MOSFET ramps up the output dur-
ing power-up it operates as a source follower. The source
follower configuration may self-oscillate in the range of
25kHz to 300kHz when the load capacitance is less than
10μF, especially if the wiring inductance from the supply
I
= C • (0.3V/ms)
L
INRUSH
This gate slope is designed to charge up a 1000μF ca-
pacitor to 12V in 40ms, with an inrush current of 300mA.
This allows the inrush current to stay under the current
limit threshold (500mA) for capacitors less than 1000μF.
IncludedintheTypicalPerformanceCharacteristicssection
is a graph of the Safe Operating Area for the MOSFET. It is
to the V pin is greater than 3μH. The possibility of oscil-
DD
lation will increase as the load current (during power-up)
increases. There are two ways to prevent this type of
oscillation. The simplest way is to avoid load capacitances
below 10μF. For wiring inductance larger than 20μH, the
minimumloadcapacitancemayextendto100μF.Asecond
choice is to connect an external gate capacitor C >1.5nF
V
+ 6.15
GATE
DD
P
SLOPE = 0.3V/ms
as shown in Figure 3.
V
DD
OUT
Turn-Off Sequence
The switch can be turned off by a variety of conditions. A
normal turn-off is initiated by the UV pin going below its
1.235V threshold. Additionally, several fault conditions
will turn off the switch. These include an input overvoltage
4217 F02
t1
t2
Figure 2. Supply Turn-On
4217fc
10
LTC4217
APPLICATIONS INFORMATION
Tying the TIMER pin to INTV will force the part to use
LTC4217
CC
the internally generated (circuit breaker) delay of 2ms.
In either case the FLT pin is pulled low to indicate an
overcurrent fault has turned off the pass MOSFET. For a
giventhecircuitbreakertimedelay,theequationforsetting
the timing capacitor’s value is as follows:
GATE
*OPTIONAL
C
P
RC TO LOWER
2.2nF
INRUSH CURRENT
4217 F03
C = t • 0.083(μF/ms)
T
CB
Figure 3. Compensation for Small CLOAD
After the switch is turned off, the TIMER pin begins dis-
chargingthetimingcapacitorwitha2μApull-downcurrent.
WhentheTIMERpinreachesits0.2Vthreshold,aninternal
100ms timer is started. After the 100ms delay, the switch
is allowed to turn on again if the overcurrent fault has been
cleared. Bringing the UV pin below 0.6V and then high will
(OV pin), overcurrent circuit breaker (SENSE pin) or over
temperature.Normallytheswitchisturnedoffwitha250μA
current pulling down the GATE pin to ground. With the
switch turned off, the OUT voltage drops which pulls the
FB pin below its threshold. PG then pulls low to indicate
output power is no longer good.
clear the fault. If the TIMER pin is tied to INTV then the
CC
switch is allowed to turn on again (after an internal 100ms
delay) if the overcurrent fault is cleared.
If V drops below 2.65V for greater than 5μs or INTV
DD
CC
drops below 2.5V for greater than 1μs, a fast shutdown
of the switch is initiated. The GATE is pulled down with a
170mA current to the OUT pin.
Tying the FLT pin to the UV pin allows the part to self-
clear the fault and turn the MOSFET on as soon as TIMER
pin has ramped below 0.2V. In this auto-retry mode the
LTC4217 repeatedly tries to turn on after an overcurrent
at a period determined by the capacitor on the TIMER pin.
The auto-retry mode also functions when the TIMER pin
Overcurrent Fault
The LTC4217 features an adjustable current limit with
foldback that protects against short-circuits or excessive
loadcurrent.Topreventexcessivepowerdissipationinthe
switch during active current limit, the available current is
reduced as a function of the output voltage sensed by the
FB pin. A graph in the Typical Performance Characteristics
curves shows the current limit versus FB voltage.
is tied to INTV .
CC
The waveform in Figure 4 shows how the output latches
off following a short-circuit. The current in the MOSFET
is 0.5A as the timer ramps up.
Current Limit Adjustment
Anovercurrentfaultoccurswhenthecurrentlimitcircuitry
has been engaged for longer than the timeout delay set
by the TIMER. Current limiting begins when the MOSFET
current reaches 0.5A to 2A (depending on the foldback).
The GATE pin is then brought down with a 140mA GATE-
to-OUT current. The voltage on the GATE is regulated in
order to limit the current to less than 2A. At this point, a
circuit breaker time delay starts by charging the external
timing capacitor from the TIMER pin with a 100μA pull-
up current. If the TIMER pin reaches its 1.2V threshold,
the internal switch turns off (with a 250μA current from
GATE to ground). Included in the Typical Performance
Characteristics curves is a graph of the Safe Operating
Area for the MOSFET. From this graph one can determine
the MOSFET’s maximum time in current limit for a given
output power.
The default value of the active current limit is 2A. The
current limit threshold can be adjusted lower by placing
V
OUT
10V/DIV
I
OUT
1A/DIV
ΔV
GATE
10V/DIV
TIMER
2V/DIV
4217 F04
1ms/DIV
Figure 4. Short-Circuit Waveform
4217fc
11
LTC4217
APPLICATIONS INFORMATION
a resistor between the I
pin and ground. As shown in
tor that is charged with this current. When the capacitor
voltage trips the comparator and the capacitor is reset, a
timer is started. The time between resets will indicate the
MOSFET current.
SET
the Functional Diagram the voltage at the I
pin (via
SET
the clamp circuit) sets the CS amplifier’s built-in offset
voltage. This offset voltage directly determines the active
current limit value. With the I pin open, the voltage at
SET
Monitor OV and UV Faults
the I
pin is determined by a positive temperature co-
SET
efficient reference. This voltage is set to 0.618V at room
temperature which corresponds to a 2A current limit at
room temperature.
Protecting the load from an overvoltage condition is the
mainfunctionoftheOVpin. IntheLTC4217-12, aninternal
resistivedivider(drivingtheOVpin)connectstoacompara-
tor to turn off the MOSFET when the V voltage exceeds
AnexternalresistorplacedbetweentheI pinandground
DD
SET
15.05V. IftheV pinsubsequentlyfallsbackbelow14.8V,
forms a resistive divider with the internal 20k sourcing
DD
the switch will be allowed to turn on immediately. In the
LTC4217 the OV pin threshold is 1.23V when rising, and
1.21V when falling out of overvoltage.
resistor. The divider acts to lower the voltage at the I
SET
pin and therefore lower the current limit threshold. The
overallcurrentlimitthresholdprecisionisreducedto 16%
when using a 20k resistor to halve the threshold.
The UV pin functions as an undervoltage protection pin or
as an “ON” pin. In the LTC4217-12 the MOSFET turns off
when V falls below 9.23V. If the V pin subsequently
Using a switch (connected to ground) in series with this
external resistor allows the active current limit to change
only when the switch is closed. This feature can be used
when the start-up current exceeds the typical maximum
load current.
DD
DD
rises above 9.88V for 100ms, the switch will be allowed
to turn on again. The LTC4217 UV turn-on/off thresholds
are 1.23V (rising) and 1.15V (falling).
InthecasesofanundervoltageorovervoltagetheMOSFET
turnsoffandthereisindicationonthePGstatuspin. When
the overvoltage is removed the MOSFET’s gate ramps
up immediately at the rate determined by the INRUSH
block.
Monitor MOSFET Temperature
The voltage at the I pin increases linearly with increas-
SET
ing temperature. The temperature profile of the I pin is
SET
shownintheTypicalPerformanceCharacteristicssection.
Using a comparator or ADC to measure the I
voltage
SET
Power Good Indication
provides an indicator of the MOSFET temperature.
In addition to setting the foldback current limit threshold,
the FB pin is used to determine a power good condition.
The LTC4217-12 uses an internal resistive divider on the
OUT pin to drive the FB pin. The PG comparator indicates
logic high when OUT pin rises above 10.5V. If the OUT pin
subsequentlyfallsbelow10.3Vthecomparatortoggleslow.
OntheLTC4217thePGcomparatordriveshighwhentheFB
pin rises above 1.23V and low when falls below 1.21V.
There is an overtemperature circuit in the LTC4217 that
monitorsaninternalvoltagesimilartotheI pinvoltage.
SET
When the die temperature exceeds 145°C the circuit turns
off the MOSFET until the temperature drops to 125°C.
Monitor MOSFET Current
ThecurrentintheMOSFETpassesthroughasenseresistor.
The voltage on the sense resistor is converted to a cur-
rent that is sourced out of the I
pin. The gain of I
Once the PG comparator is high the GATE pin voltage is
monitored with respect to the OUT pin. Once the GATE
minus OUT voltage exceeds 4.2V the PG pin goes high.
This indicates to the system that it is safe to load the OUT
pin while the MOSFET is completely turned “on”. The PG
pin goes low when the GATE is commanded off (using
the UV, OV or SENSE pins) or when the PG comparator
MON
SENSE
amplifier is 50μA/A from I
for 1A of MOSFET current.
MON
This output current can be converted to a voltage using an
external resistor to drive a comparator or ADC. The voltage
compliance for the I
pin is from 0V to INTV – 0.7V.
MON
CC
A microcontroller with a built-in comparator can build a
simple integrating single-slope ADC by resetting a capaci-
drives low.
4217fc
12
LTC4217
APPLICATIONS INFORMATION
12V Fixed Version
Use the equation for R
FB thresholds. Likewise use the equation for R
decreasing the UV and FB thresholds.
for increasing the OV and
SHUNT1
for
SHUNT2
In the LTC4217-12 the UV, OV and FB pins are driven by
internal dividers which may need to be filtered to prevent
false faults. By placing a bypass capacitor on these pins
the faults are delayed by the RC time constant. Use the
Design Example
Consider the following design example (Figure 6): V =
R value from the electrical characteristics table for this
IN
UVON
IN
12V, I
= 2A. I
OVOFF
= 100mA, C = 330μF, V
=
calculation.
MAX
9.88V,V
INRUSH
=15.05V,V
L
=10.5V.Acurrentlimitfault
PWRGD
In cases where the fixed thresholds need a slight adjust-
triggers an automatic restart of the power-up sequence.
ment, placing a resistor from the UV or OV pins to V
DD
or GND will adjust the threshold up or down. Likewise
V
OUT
V
OUT
12V
DD
UV
LTC4217-12DHC
12V
+
placing a resistor between FB pin to OUT or GND adjusts
C
L
12V
1.5A
330μF
the threshold. Again use the R value from the electrical
IN
R1
10k
characteristics table for this calculation.
FLT
PG
An example in Figure 5 raises the UV turn-on voltage from
9.88V to 10.5V. Increasing the UV level requires adding a
TIMER
INTV
CC
I
MON
ADC
C1
0.1μF
R2
20k
GND
resistor between UV and ground. The resistor, R
,
SHUNT1
4217 F06
can be calculated using electrical table parameters as
follows:
Figure 6. 1.5A, 12V Card Resident Application
R(IN • VOLD
18k •9.88
10.5– 9.88
)
RSHUNT1
=
=
= 287k
The inrush current is defined by the current required to
charge the output capacitor using the fixed 0.3V/ms GATE
charge-up rate. The inrush current is defined as:
V
– V
(
)
(
)
NEW
OLD
In this same figure the OV threshold is lowered from
15.05V to 13.5V. Decreasing the OV threshold requires
adding a resistor between V and OV. This resistor can
be calculated as follows:
0.3V
ms
0.3V
ms
⎛
⎞
⎛
⎞
I
=C •
= 330µF •
=100mA
⎜
⎝
⎟
⎠
⎜
⎝
⎟
⎠
L
INRUSH
DD
As mentioned previously the charge-up time is the out-
put voltage (12V) divided by the output rate of 0.3V/ms
resulting in 40ms. The peak power dissipation of 12V at
100mA(or1.2W)iswithintheSOAofthepassMOSFETfor
40ms(seeMOSFETSOAcurveintheTypicalPerformance
Characteristics section).
⎛
⎜
⎞
⎟
V
– V
R(IN • VOLD
(
)
NEW
OV TH
(
)
)
RSHUNT2
=
=
V TH
⎜
⎝
V
– VNEW
⎟
⎠
(
)
OLD
(
)
⎛
⎞
13.5–1.235
15.05–13.5
18k •15.05
1.235
(
(
)
)
=1.736M
⎜
⎟
⎝
⎠
NextthepowerdissipatedintheMOSFETduringovercurrent
must be limited. The active current limit uses a timer to
prevent excessive energy dissipation in the MOSFET. The
worst-case power dissipation occurs when the voltage
versus current profile of the foldback current limit is at
the maximum. This occurs when the current is 2A and the
voltage is one half of the 12V or 6V. See the Current Limit
Sense Voltage vs FB Voltage in the Typical Performance
Characteristics section to view this profile. In order to
survive 12W, the MOSFET SOA dictates a maximum time
LTC4217-12
V
DD
R
SHUNT2
OV
UV
R
SHUNT1
4217 F05
of 10ms (see SOA graph). Use the internal 2ms timer
Figure 5. Adjusting LTC4217-12 Thresholds
4217fc
13
LTC4217
APPLICATIONS INFORMATION
invoked by tying the TIMER pin to INTV . After the 2ms
There are two V pins on opposite sides of the package
CC
DD
timeout the FLT pin needs to pull-down on the UV pin to
that connect to the sense resistor and MOSFET. The PCB
restart the power-up sequence.
layout should be balanced and symmetrical to each V
DD
pin to balance current in the MOSFET bond wires. Figure 7
shows a recommended layout for the LTC4217.
Sincethedefaultvaluesforovervoltage, undervoltageand
power good thresholds for the 12V fixed version match
the requirements, no external components are required
for the UV, OV and FB pins.
Although the MOSFET is self protected from overtem-
perature, it is recommended to solder the backside of the
packagetoacoppertracetoprovideagoodheatsink.Note
that the backside is connected to the SENSE pin and can-
not be soldered to the ground plane. During normal loads
the power dissipated in the MOSFET is as high as 0.23W.
A 10mm × 10mm area of 1oz copper should be sufficient.
This area of copper can be divided in many layers.
The final schematic in Figure 6 results in very few external
components. The pull-up resistor, R1, connects to the
PG pin while the 20k (R2) converts the I
voltage at a ratio:
current to a
MON
V
= 50[μA/A] • 20k • I = 1[V/A] • I
OUT OUT
IMON
In addition there is a 0.1μF bypass (C1) on the INTV pin.
It is also important to put C1, the bypass capacitor for
CC
the INTV pin as close as possible between the INTV
CC
CC
Layout Considerations
and GND.
In Hot Swap applications where load currents can be 2A,
narrowPCBtracksexhibitmoreresistancethanwidertracks
and operate at elevated temperatures. The minimum trace
width for 1oz copper foil is 0.02" per amp to make sure
the trace stays at a reasonable temperature. Using 0.03"
per amp or wider is recommended. Note that 1oz copper
exhibits a sheet resistance of about 0.5mΩ/square. Small
resistances add up quickly in high current applications.
Additional Applications
TheLTC4217hasawideoperatingrangefrom2.9Vto26.5V.
The UV, OV and PG thresholds are set with few resistors.
All other functions are independent of supply voltage.
Figure 8 shows a 3.3V application with a UV threshold of
2.87V, an OV threshold of 3.77V and a PG threshold of
3.05V. The last page includes a 24V application with a UV
threshold of 19.9V, an OV threshold of 26.3V and a PG
threshold of 20.75V.
V
OUT
LTC4217FE
3.3V
V
3.3V
1.5A
DD
OUT
HEAT SINK
R4
+
14.7k
R1
V
DD
OUT
C
L
FB
17.4k
100μF
R5
10k
UV
FLT
OV
3.3V
R2
3.16k
VIA TO
SINK
R6
10k
R3
10k
PG
TIMER
INTV
CC
I
MON
ADC
C
C
R
MON
20k
T
GND
GND
0.1μF
4217 F08
4217 F07
Figure 7. Recommended Layout
Figure 8. 3.3V, 1.5A Card Resident Application
4217fc
14
LTC4217
PACKAGE DESCRIPTION
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
0.65 0.05
3.50 0.05
1.65 0.05
2.20 0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
4.40 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
0.40 0.10
5.00 0.10
(2 SIDES)
9
16
R = 0.20
TYP
3.00 0.10 1.65 0.10
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
(DHC16) DFN 1103
8
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
4.40 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4217fc
15
LTC4217
PACKAGE DESCRIPTION
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CA
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
4.95
(.195)
20 1918 17 16 15 14 1312 11
6.60 0.10
2.74
(.108)
4.50 0.10
SEE NOTE 4
6.40
(.252)
BSC
2.74
(.108)
0.45 0.05
1.05 0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
4217fc
16
LTC4217
REVISION HISTORY (Revision history begins at Rev C)
REV
DATE
DESCRIPTION
PAGE NUMBER
C
12/09 Revise Features, Description and Typical Application
Revise Absolute Maximum Ratings Storage Temperature Range and Pin Configuration
Revise Electrical Characteristics
1
2
3, 4
Revise Graph G11
6
Update Pin Functions
7
Update Functional Diagram
8
9
Update Operation Section
Revise Figure 1 and Update Values and Equation in Applications Information Section
10-12, 14
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
17
LTC4217
TYPICAL APPLICATION
24V, 1.5A Card Resident Application
V
OUT
LTC4217FE
24V
V
OUT
DD
+
24V
158k
10k
100μF
*
1.5A
FB
200k
UV
FLT
OV
24V
3.24k
10k
10k
PG
TIMER
INTV
CC
I
MON
ADC
GND
20k
0.1μF
4217 TA02
*DIODES INC. SMAJ24A
RELATED PARTS
PART NUMBER
LTC1421
DESCRIPTION
COMMENTS
Dual Channel, Hot Swap Controller
Operates from 3V to 12V, Supports –12V, SSOP-24
Operates from 2.7V to 12V, SO-8
LTC1422
Single Channel, Hot Swap Controller
Single Channel, Hot Swap Controller
Dual Channel, Hot Swap Controller
Dual Channel, Hot Swap Controller
LTC1642A
LTC1645
Operates from 3V to 16.5V, Overvoltage Protection Up to 33V, SSOP-16
Operates from 3V to 12V, Power Sequencing, SO-8 or SO-14
Operates from 2.7V to 16.5V, SO-8 or SSOP-16
LTC1647-1/LTC1647-2/
LTC1647-3
LTC4210
LTC4211
LTC4212
LTC4214
LTC4215
Single Channel, Hot Swap Controller
Single Channel, Hot Swap Controller
Single Channel, Hot Swap Controller
Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6
Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10
Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10
Operates from –6V to –16V, MSOP-10
Negative Voltage, Hot Swap Controller
2
Hot Swap Controller with I C Compatible Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage
Monitoring
LTC4218
LT4220
Single Channel, Hot Swap Controller
Operates from 2.9V to 26.5V, Adjustable Current Limit, SSOP-16
Operates from 2.7V to 16.5V, SSOP-16
Positive and Negative Voltage, Dual
Channels, Hot Swap Controller
LTC4221
LTC4230
Dual Hot Swap Controller/Sequencer
Triple Channels, Hot Swap Controller
Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16
Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20
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LT 1209 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
18
●
●
© LINEAR TECHNOLOGY CORPORATION 2008
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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