LTC4251_12 [Linear]
Negative Voltage Hot Swap Controllers in SOT-23; 采用SOT -23负电压热插拔控制器
| 型号： | LTC4251_12 |
| 厂家： | 
Linear |
| 描述： | Negative Voltage Hot Swap Controllers in SOT-23 |
| 文件： | 总24页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4251/LTC4251-1/
LTC4251-2
Negative Voltage
Hot Swap Controllers in SOT-23
NOT RECOMMENDED FOR NEW DESIGNS
Please See LTC4251B for Drop-In Replacement
FeaTures
DescripTion
The LTC®4251/LTC4251-1/LTC4251-2 negative voltage
Hot Swap™ controllers allow a board to be safely inserted
and removed from a live backplane. Output current is con-
trolled by three stages of current limiting: a timed circuit
breaker, active current limitinganda fastfeedforwardpath
that limits peak current under worst-case catastrophic
fault conditions.
n
Allows Safe Board Insertion and Removal from a
Live –48V Backplane
n
Floating Topology Permits Very High Voltage
Operation
n
Programmable Analog Current Limit with Circuit
Breaker Timer
n
Fast Response Time Limits Peak Fault Current
n
Programmable Timer
Programmable undervoltage and overvoltage detectors
disconnect the load whenever the input supply exceeds
the desired operating range. The supply input is shunt
regulated, allowing safe operation with very high supply
voltages. A multifunction timer delays initial start-up and
controls the circuit breaker’s response time.
n
Programmable Undervoltage/Overvoltage Protection
n
Low Profile (1mm) ThinSOT™ Package
applicaTions
n
Hot Board Insertion
The LTC4251 UV/OV thresholds are designed to match the
standard telecom operating range of –43V to –75V. The
LTC4251-1 UV/OV thresholds extend the operating range
to encompass –36V to –72V. The LTC4251-2 implements
a UV threshold of –43V only.
n
Electronic Circuit Breaker
n
–48V Distributed Power Systems
n
Negative Power Supply Control
n
Central Office Switching
n
Programmable Current Limiting Circuit
n
High Availability Servers
Disk Arrays
All parts are available in the 6-Pin SOT-23 package.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
Hot Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
n
Typical applicaTion
–48V, 2.5A Hot Swap Controller
Start-Up Behavior
–48RTN
R
*
IN
+
–48RTN
(SHORT PIN)
10k
C
GATE
5V/DIV
L
LOAD
500mW
100µF
R1
402k
1%
V
OUT
†
C
D
IN
IN
V
IN
1µF
DDZ13B**
Q1
IRF530S
SENSE
2.5A/DIV
UV/OV GATE
LTC4251
C1
10nF
3
4
TIMER SENSE
1
R2
32.4k
1%
R
10Ω
C
R
V
S
EE
V
OUT
0.02Ω
20V/DIV
C
C
C
T
2
18nF
150nF
425112 TA01
–48V
425112 TA02
1ms/DIV
*TWO 0.25W RESISTORS IN SERIES FOR
R
ON THE PCB ARE RECOMMENDED.
IN
**DIODES, INC.
†RECOMMENDED FOR HARSH ENVIRONMENTS
425112fc
1
LTC4251/LTC4251-1/
LTC4251-2
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1), All Voltages are Referred to VEE
Current into V (100µs Pulse).............................100mA
IN
Minimum V Voltage............................................ –0.3V
IN
TOP VIEW
Gate, UV/OV, Timer Voltage........................ –0.3V to 16V
Sense Voltage ............................................ –0.6V to 16V
Current Out of Sense Pin (20µs Pulse).............. –200mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC4251C/LTC4251-1C/LTC4251-2C ........ 0°C to 70°C
LTC4251I/LTC4251-1I/LTC4251-2I........–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
SENSE 1
6 GATE
V
2
3
5 UV/OV*
4 TIMER
EE
V
IN
S6 PACKAGE
6-LEAD PLASTIC SOT-23
*UV FOR LTC4251-2
T
= 125°C, θ = 256°C/W
JA
JMAX
orDer inForMaTion
LEAD FREE FINISH
LTC4251CS6#PBF
LTC4251IS6#PBF
TAPE AND REEL
PART MARKING
LTUQ
PACKAGE DESCRIPTION
6-Lead Plastic SOT-23
6-Lead Plastic SOT-23
6-Lead Plastic SOT-23
6-Lead Plastic SOT-23
6-Lead Plastic SOT-23
6-Lead Plastic SOT-23
TEMPERATURE RANGE
LTC4251CS6#TRPBF
LTC4251IS6#TRPBF
LTC4251-1CS6#TRPBF
LTC4251-1IS6#TRPBF
LTC4251-2CS6#TRPBF
LTC4251-2IS6#TRPBF
0°C to 70°C
LTUR
–40°C to 85°C
0°C to 70°C
LTC4251-1CS6#PBF
LTC4251-1IS6#PBF
LTC4251-2CS6#PBF
LTC4251-2IS6#PBF
LTQU
LTQV
–40°C to 85°C
0°C to 70°C
LTK6
LTAAZ
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 2, 3)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
13
MAX
UNITS
V
l
V
V
V
V
V
V
to V Zener Voltage
I
IN
I
IN
= 2mA
11.5
14.5
Z
IN
IN
IN
IN
IN
EE
r
Z
to V Zener Dynamic Impedance
= 2mA to 30mA
5
Ω
EE
l
l
I
IN
Supply Current
UV/OV = 4V, V = (V – 0.3V)
0.8
9.2
1
2
mA
V
IN
Z
V
V
V
V
V
Undervoltage Lockout
Undervoltage Lockout Hysteresis
Coming Out of UVLO (Rising V )
11.5
LKO
LKH
CB
IN
V
l
l
l
l
Circuit Breaker Current Limit Voltage
Analog Current Limit Voltage
Fast Current Limit Voltage
V
V
V
= (V
– V )
EE
40
80
50
60
120
300
80
mV
mV
mV
CB
SENSE
= (V
– V )
EE
100
200
ACL
FCL
ACL
FCL
SENSE
= (V
– V
)
EE
150
40
SENSE
I
GATE Pin Output Current
UV/OV = 4V, V
UV/OV = 4V, V
UV/OV = 4V, V
= V , V = 0V (Sourcing)
EE GATE
58
17
190
µA
mA
mA
GATE
SENSE
SENSE
SENSE
– V = 0.15V, V
= 3V (Sinking)
GATE
EE
EE
– V = 0.3V, V
= 1V (Sinking)
GATE
l
V
GATE
External MOSFET Gate Drive
V
GATE
– V , I = 2mA
10
12
V
Z
V
EE IN
425112fc
2
LTC4251/LTC4251-1/
LTC4251-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Gate Low Threshold
UV Threshold High
(Before Gate Ramp-Up)
0.5
V
GATEL
UVHI
l
l
V
LTC4251/LTC4251-2
LTC4251-1
3.075
2.300
3.225
2.420
3.375
2.540
V
V
l
l
V
V
V
V
V
UV Threshold Low
UV Hysteresis
LTC4251/LTC4251-2
LTC4251-1
2.775
2.050
2.925
2.160
3.075
2.270
V
V
UVLO
UVHST
OVHI
LTC4251/LTC4251-2
LTC4251-1
0.30
0.26
V
V
l
l
OV Threshold High
OV Threshold Low
OV Hysteresis
LTC4251
LTC4251-1
5.85
5.86
6.15
6.17
6.45
6.48
V
V
l
l
LTC4251
LTC4251-1
5.25
5.61
5.55
5.91
5.85
6.21
V
V
OVLO
OVHST
LTC4251
LTC4251-1
0.60
0.26
V
V
l
l
I
I
SENSE Input Current
UV/OV Input Current
UV/OV = 4V, V
= 50mV
SENSE
–30
–15
0.1
4
µA
µA
V
SENSE
UV/OV = 4V
1
INP
V
V
Timer Voltage High Threshold
Timer Voltage Low Threshold
Timer Current
TMRH
TMRL
TMR
1
V
I
Timer On (Initial Cycle, Sourcing), V
= 2V
5.8
28
230
5.8
µA
mA
µA
TMR
TMR
Timer Off (Initial Cycle, Sinking), V
= 2V
Timer On (Circuit Breaker, Sourcing), V
= 2V
TMR
Timer Off (Cooling Cycle, Sinking), V
= 2V
µA
TMR
t
t
UV Low to GATE Low
OV High to GATE Low
0.7
1
µs
µs
PLLUG
LTC4251/LTC4251-1
PHLOG
Note 2: All currents into device pins are positive; all currents out of device
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
pins are negative. All voltages are referenced to V unless otherwise
EE
specified.
Note 3: UV/OV = 4V refers to UV = 4V for the LTC4251-2.
Typical perForMance characTerisTics UV/OV = 4V refers to UV = 4V for the LTC4251-2.
IIN vs Temperature
IIN vs VIN
rZ vs Temperature
1000
100
10
2000
1800
1600
1400
1200
1000
800
10
9
V
= (V – 0.3V)
I
IN
= 2mA
IN
Z
T
= –40°C
A
8
T
= 25°C
= 85°C
A
7
6
T
A
5
600
T = 125°C
A
1
4
400
3
200
0.1
0
2
0
2
4
6
8
10 12 14 16 18 20 22
(V)
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
V
TEMPERATURE (°C)
TEMPERATURE (°C)
IN
425112 G02
425112 G01
425112 G03
425112fc
3
LTC4251/LTC4251-1/
LTC4251-2
Typical perForMance characTerisTics UV/OV = 4V refers to UV = 4V for the LTC4251-2.
Undervoltage Lockout VLKO vs
Temperature
Undervoltage Lockout Hysteresis
VLKH vs Temperature
VZ vs Temperature
14.5
14.0
13.5
13.0
12.5
12.0
12.0
11.5
11.0
10.5
10.0
9.5
1.6
1.4
1.2
1
I
= 2mA
IN
0.8
0.6
0.4
0.2
0
9.0
8.5
8.0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G04
425112 G05
425112 G06
Circuit Breaker Current Limit
Voltage VCB vs Temperature
Analog Current Limit Voltage VACL
vs Temperature
Fast Current Limit Voltage VFCL
vs Temperature
60
58
56
54
52
50
48
46
44
42
40
120
115
110
105
100
95
300
275
250
225
200
175
150
90
85
80
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
45
85 105 125
–55 –35 –15
5
45
85 105 125
25
65
25
65
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G07
425112 G08
425112 G09
IGATE (Source) vs Temperature
IGATE (ACL, Sink) vs Temperature
IGATE (FCL, Sink) vs Temperature
70
65
60
55
50
45
40
30
25
20
15
10
5
400
350
300
250
200
150
100
50
UV/0V = 4V
TIMER = 0V
UV/0V = 4V
TIMER = 0V
UV/0V = 4V
TIMER = 0V
V
V
= V
V
V
– V = 0.15V
V
V
– V = 0.3V
SENSE
GATE
EE
SENSE
GATE
EE
SENSE EE
= 0V
= 3V
= 1V
GATE
0
0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G10
425112 G11
425112 G12
425112fc
4
LTC4251/LTC4251-1/
LTC4251-2
Typical perForMance characTerisTics UV/OV = 4V refers to UV = 4V for the LTC4251-2.
VGATE vs Temperature
VGATEL vs Temperature
UV Threshold vs Temperature
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.375
3.275
3.175
3.075
2.975
2.875
2.775
UV/0V = 4V
UV/0V = 4V,
LTC4251/LTC4251-2
V
V
= 0V
V
= 0V,
TMR
SENSE
TMR
= V
GATE THRESHOLD
BEFORE RAMP-UP
EE
V
UVH
V
UVL
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G13
425112 G14
425112 G15
UV Threshold vs Temperature
OV Threshold vs Temperature
OV Threshold vs Temperature
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
6.45
6.25
6.05
5.85
5.65
5.45
5.25
6.51
6.41
6.31
6.21
6.11
6.01
5.91
5.81
5.71
5.61
LTC4251
LTC4251-1
LTC4251-1
V
OVH
V
UVHI
V
OVHI
V
OVLO
V
OVL
V
UVLO
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G16
425112 G17
425112 G18
ISENSE vs Temperature
ISENSE vs (VSENSE – VEE)
TIMER Threshold vs Temperature
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
0.01
0.1
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
TMRH
1.0
10
V
TMRL
UV/0V = 4V
UV/0V = 4V
100
1000
TIMER = 0V
TIMER = 0V
GATE = HIGH
GATE = HIGH
V
– V = 50mV
EE
T = 25°C
SENSE
A
–1.5 –1.0 –0.5
(V
0
0.5 1.0 1.5
– V ) (V)
2.0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
SENSE
EE
425112 G20
425112 G19
425112 G21
425112fc
5
LTC4251/LTC4251-1/
LTC4251-2
Typical perForMance characTerisTics UV/OV = 4V refers to UV = 4V for the LTC4251-2.
ITMR (Circuit Breaking, Sourcing)
vs Temperature
ITMR (Initial Cycle, Sourcing) vs
Temperature
I
TMR (Initial Cycle, Sinking) vs
Temperature
10
9
8
7
6
5
4
3
2
1
0
50
45
40
35
30
25
20
15
10
280
260
240
220
200
180
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G22
425112 G23
425112 G24
ITMR (Cooling Cycle, Sinking)
vs Temperature
t
PLLUG and tPHLOG vs Temperature
10
9
8
7
6
5
4
3
2
1
0
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
t
(LTC4251/LTC4251-1)
PHLOG
t
PLLUG
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
425112 G25
425112 G26
425112fc
6
LTC4251/LTC4251-1/
LTC4251-2
Uv/Ov Refers To The Uv Pin For The Ltc4251-2. The Ov Comparator In The Ltc4251-2 Is Disabled. All
pin FuncTions
References In The Text To Overvoltage, Ov, Vovhi And Vovlo Do Not Apply To The Ltc4251-2.
SENSE (Pin 1): Circuit Breaker/Current Limit SENSE Pin.
Load current is monitored by sense resistor R connected
If SENSE exceeds 50mV while GATE is high, a 230µA
pull-up current charges C . If SENSE drops below 50mV
S
T
between SENSE and V , and controlled in three steps. If
before TIMER reaches 4V, a 5.8µA pull-down current
EE
SENSEexceedsV (50mV),thecircuitbreakercomparator
slowly discharges C . In the event that C eventually
CB
T
T
activatesa230µATIMERpinpull-upcurrent.TheLTC4251/
integrates up to the 4V V
threshold, TIMER latches
TMRH
LTC4251-1/LTC4251-2 latch off when C charges to 4V. If
high with a 5.8µA pull-up source and GATE quickly pulls
low.TheLTC4251/LTC4251-1/LTC4251-2faultlatchesmay
be cleared by either pulling TIMER low with an external
T
SENSE exceeds V
(100mV), the analog current limit
ACL
amplifier pulls GATE down and regulates the MOSFET
current at V /R . In the event of a catastrophic short-
device, or by pulling UV/OV below V .
ACL
S
UVLO
circuit, SENSE may overshoot 100mV. If SENSE reaches
UV/OV(Pin5):Undervoltage/OvervoltageInput. Thisdual
function pin detects undervoltage as well as overvoltage.
V
(200mV), the fast current limit comparator pulls
FCL
GATE low with a strong pull-down. To disable the circuit
The high threshold at the UV comparator is set at V
UVHI
breakerandcurrentlimitfunctions,connectSENSEtoV .
EE
with V
hysteresis. The high threshold at the OV
UVHST
comparator is set at V
Kelvin-sense connections between the sense resistor and
with V
hysteresis. If UV/
OVHI
OVHST
the V and SENSE pins are strongly recommended, see
OV < V
or UV/OV > V
, GATE pulls low. If UV/OV
EE
UVLO
and UV/OV < V
OVHI
Figure 6.
> V
, the LTC4251/LTC4251-1/
UVHI
OVLO
LTC4251-2 attempt to start-up. The internal UVLO at V
IN
V
(Pin 2): Negative Supply Voltage Input. Connect this
EE
alwaysoverridesUV/OV.AlowatUVresetsaninternalfault
latch. A high at OV pulls GATE low but does not reset the
fault latch. A 1nF to 10nF capacitor at UV/OV eliminates
transients and switching noise from affecting the UV/OV
thresholds and prevents glitches at the GATE pin.
pin to the negative side of the power supply.
V (Pin 3): Positive Supply Input. Connect this pin to the
IN
positive side of the supply through a dropping resistor.
A shunt regulator typically clamps V at 13V. An internal
IN
undervoltage lockout (UVLO) circuit holds GATE low until
GATE (Pin 6): N-Channel MOSFET Gate Drive Output.
theV pinisgreaterthanV (9.2V), overridingUV/OV. If
IN
LKO
This pin is pulled high by a 58µA current source. GATE is
UV is high, OV is low and V comes out of UVLO, TIMER
IN
pulled low by invalid conditions at V (UVLO), UV/OV, or
IN
starts an initial timing cycle before initiating a GATE ramp
the fault latch. GATE is actively servoed to control fault
current as measured at SENSE. A compensation capacitor
at GATE stabilizes this loop. A comparator monitors GATE
to ensure that it is low before allowing an initial timing
cycle, GATE ramp up after an overvoltage event, or restart
after a current limit fault.
up. If V drops below approximately 8.2V, GATE pulls low
IN
immediately.
TIMER (Pin 4): Timer Input. TIMER is used to generate
a delay at start-up, and to delay shutdown in the event of
an output overload. TIMER starts an initial timing cycle
when the following conditions are met: UV is high, OV is
low, V clearsUVLO, TIMERpinislow, GATEislowerthan
IN
V
and V
– V < V . A pull-up current of 5.8µA
GATEL
SENSE EE CB
T
then charges C , generating a time delay. If C charges to
T
V
(4V) the timing cycle terminates, TIMER quickly
TMRH
pulls low and GATE is activated.
425112fc
7
LTC4251/LTC4251-1/
LTC4251-2
block DiagraM
V
3
IN
V
V
IN
V
–
+
OVHI
OV**
58µA
6
GATE
V
EE
+
–
0.5V
UV/OV*
5
–
+
EE
UV
V
UVLO
V
V
IN
IN
LOGIC
+
–
230µA
5.8µA
4V
–
+
FCL
200mV
V
IN
V
+
–
EE
22µA
4
TIMER
–
+
+
ACL
V
= 10mV
OS
5k
1V
5.8µA
V
EE
+
–
–
V
V
EE
V
EE
EE
+
–
1
SENSE
CB
50mV
V
+
–
EE
2
425112 BD
*UV FOR THE LTC4251-2
** THE OV COMPARATOR IS DISABLED FOR LTC4251-2
V
EE
425112fc
8
LTC4251/LTC4251-1/
LTC4251-2
operaTion Note that for simplicity, the following assumptions are made in the text. Firstly, UV/OV also means the UV
pin of the LTC4251-2. Secondly, all overvoltage conditions and references to OV, VOVHI and VOVLO do not apply to the LTC4251-2 as the
OV comparator in this part is disabled.
LONG
Hot Circuit Insertion
–48RTN
R
IN
10k
When circuit boards are inserted into a live backplane, the
supplybypasscapacitorscandrawhugetransientcurrents
from the power bus as they charge. The flow of current
damages the connector pins and glitches the power bus,
causing other boards in the system to reset. The LTC4251/
LTC4251-1/LTC4251-2 are designed to turn on a circuit
board supply in a controlled manner, allowing insertion or
removal without glitches or connector damage.
500mW
†
R1
402k
1%
D
SHORT
C
IN
1µF
IN
DDZ13B**
V
IN
UV/OV
TIMER
+
LTC4251
C
L
C1
10nF
100µF
TYP
V
EE
SENSE GATE
R2
32.4k
1%
R
C
C
C
C
T
10Ω
18nF
4
150nF
3
LONG
–48V
2
1
425112 F02
R
S
Q1
IRF530S
Initial Start-Up
20mΩ
**DIODES, INC.
†RECOMMENDED FOR HARSH ENVIRONMENTS
TheLTC4251/LTC4251-1/LTC4251-2resideonaremovable
circuit board and control the path between the connector
and load or power conversion circuitry with an external
MOSFET switch (see Figure 1). Both inrush control and
short-circuit protection are provided by the MOSFET.
Figure 2. –48V, 2.5A Hot Swap Controller
Interlock Conditions
Astart-upsequencecommencesoncefiveinitial“interlock”
conditions are met:
A detailed schematic is shown in Figure 2. –48V and
–48RTNreceivepowerthroughthelongestconnectorpins,
and are the first to connect when the board is inserted.
The GATE pin holds the MOSFET off during this time. UV/
OV determines whether or not the MOSFET should be
turned on based upon internal, high accuracy thresholds
and an external divider. UV/OV does double duty by also
monitoringwhetherornottheconnectorisseated.Thetop
of the divider detects –48RTN by way of a short connector
pin that is the last to mate during the insertion sequence.
1. The input voltage V exceeds 9.2V (V
)
IN
LKO
2. The voltage at UV/OV falls within the range of V
to
UVHI
V
(UV > V
, LTC4251-2)
OVLO
UVHI
3. The (SENSE – V ) voltage is <50mV (V )
EE
CB
4. The voltage on the timer capacitor (C ) is less than 1V
T
(V
)
TMRL
5. GATE is less than 0.5V (V
)
GATEL
The first two conditions are continuously monitored and
the latter three are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
PLUG-IN BOARD
–48RTN
+
+
ISOLATED
DC/DC
LTC4251
+
LOW
VOLTAGE
CIRCUITRY
C
LOAD
CONVERTER
MODULE
–48V
–
–
BACKPLANE
425112 F01
TIMER begins the start-up sequence by sourcing 5.8µA
into C . If V or UV/OV falls out of range, the start-up
T
IN
Figure 1. Basic LTC4251 Hot Swap Topology
cycle stops and TIMER discharges C to less than 1V,
T
then waits until the aforementioned conditions are once
again met. If C successfully charges to 4V, TIMER pulls
T
low and GATE is released. GATE sources 58µA (I
charging the MOSFET gate and associated capacitance.
),
GATE
425112fc
9
LTC4251/LTC4251-1/
LTC4251-2
operaTion
In this way the circuit breaker function will also respond
to low duty cycle overloads, and accounts for fast heating
and slow cooling characteristic of the MOSFET.
Two modes of operation are possible during the time the
MOSFET is first turning on, depending on the values of
external components, MOSFET characteristics and nomi-
nal design current. One possibility is that the MOSFET
will turn on gradually so that the inrush into the load
capacitance remains a low value. The output will simply
ramp to –48V and the MOSFET will be fully enhanced.
A second possibility is that the load current exceeds the
Higher overloads are handled by an analog current limit
loop. If the drop across R reaches 100mV, the current
S
limiting loop servos the MOSFET gate and maintains a
constant output current of 100mV/R . Note that because
S
SENSE>50mV,TIMERchargesC duringthistimeandthe
T
current limit threshold of 100mV/R . In this case, the
S
LTC4251/LTC4251-1/LTC4251-2willeventuallyshutdown.
LTC4251/LTC4251-1/LTC4251-2 will ramp the output by
Low impedance failures on the load side of the LTC4251/
LTC4251-1/LTC4251-2 coupled with 48V or more driving
potential can produce current slew rates well in excess of
50A/µs. Under these conditions, overshoot is inevitable. A
fastSENSEcomparatorwithathresholdof200mVdetects
overshoot and pulls GATE low much harder and hence
much faster than can the weaker current limit loop. The
sourcing 100mV/R current into the load capacitance.
S
It is important to set the timer delay so that, regardless
of which start-up mode is used, the start-up time is less
than the TIMER delay time. If this condition is not met,
the LTC4251/LTC4251-1/LTC4251-2 may shutdown after
one TIMER delay.
100mV/R current limit loop then takes over, and servos
Board Removal
S
the current as previously described. As before, TIMER
If the board is withdrawn from the card cage, the UV/OV
divider is the first to lose connection. This shuts off the
MOSFET and commutates the flow of current in the con-
nector. When the power pins subsequently separate, there
is no arcing.
runs and latches the LTC4251/LTC4251-1/LTC4251-2 off
when C reaches 4V.
T
The LTC4251/LTC4251-1/LTC4251-2 circuit breaker latch
is reset by either pulling UV/OV momentarily low, or
dropping the input voltage V below the internal UVLO
IN
Current Control
threshold of 8.2V.
Three levels of protection handle short-circuit and over-
load conditions. Load current is monitored by SENSE and
Although short-circuits are the most obvious fault type,
several operating conditions may invoke overcurrent
protection. Noise spikes from the backplane or load, input
stepscausedbytheconnectionofasecond,highervoltage
supply, transient currents caused by faults on adjacent
circuitboardssharingthesamepowerbus,ortheinsertion
of non-hot swappable products could cause higher than
anticipated input current and temporary detection of an
resistor R . There are three distinct thresholds at SENSE:
S
50mV for a timed circuit breaker function; 100mV for an
analog current limit loop; and 200mV for a fast, feedfor-
ward comparator which limits peak current in the event
of a catastrophic short-circuit.
If, owingtoanoutputoverload, thevoltagedropacrossR
S
overcurrent condition. The action of TIMER and C rejects
T
exceeds50mV,TIMERsources230µAintoC .C eventually
T
T
theseeventsallowingtheLTC4251/LTC4251-1/LTC4251-2
to “ride out” temporary overloads and disturbances that
wouldtripasimplecurrentcomparatorandinsomecases,
blow a fuse.
charges to a 4V threshold and the LTC4251/LTC4251-1/
LTC4251-2 latchoff. If the overload goes away and SENSE
measures less than 50mV, C slowly discharges (5.8µA).
T
425112fc
10
LTC4251/LTC4251-1/
LTC4251-2
applicaTions inForMaTion
SHUNT REGULATOR
OV turning off at V
OVHI
A fast responding shunt regulator clamps the V pin to
OV turning on at V
OVLO
IN
13V (V ). Power is derived from –48RTN by an external
Z
The UV and OV trip point ratio for LTC4251 is designed to
matchthestandardtelecomoperatingrangeof43Vto75V.
The LTC4251-2 implements a UV threshold of 43V only.
current limiting resistor, R . A 1µF decoupling capacitor,
IN
C filters supply transients and contributes a short delay
IN
at start-up.
Adivider(R1,R2)isusedtoscalethesupplyvoltage.Using
R1 = 402k and R2 = 32.4k gives a typical operating range
of 43.2V to 74.4V. The under- and overvoltage shutdown
thresholds are then 39.2V and 82.5V. 1% divider resis-
tors are recommended to preserve threshold accuracy.
The same resistor values can be used for the LTC4251-2.
To meet creepage requirements R may be split into two
IN
or more series connected units, such as two 5.1k or three
3.3kresistors.Thisintroducesawidertotalspacingthanis
possible with a single component while at the same time
ballasting the potential across the gap under each resistor.
The LTC4251 is fundamentally a low voltage device that
operates with –48V as its reference ground. To further
protect against arc discharge into its pins, the area in and
aroundtheLTC4251andallassociatedcomponentsshould
befreeofanyotherplanessuchaschassisground, return,
or secondary-side power and ground planes.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100µA, and
defineanimpedanceatUV/OVof30k.Inmostapplications,
30k impedance coupled with 300mV UV hysteresis makes
theLTC4251/LTC4251-1/LTC4251-2insensitivetonoise.If
more noise immunity is desired, add a 1nF to 10nF filter
V is rated handle 30mA within the thermal limits of the
IN
capacitor from UV/OV to V .
EE
package,andistestedtosurvivea100µs,100mApulse.To
The UV and OV trip point thresholds for the LTC4251-1 are
designed to encompass the standard telecom operating
range of –36V to –72V.
protect V against damage from higher amplitude spikes,
IN
clamp V to V with a 13V Zener diode. Star connect
IN
EE
V
and all V referred components to the sense resistor
EE
EE
Kelvin terminal as illustrated in Figure 2, keeping trace
lengthsbetweenV , C , D andV asshortaspossible.
A divider (R1, R2) is used to scale the supply voltage.
Using R1 = 442k and R2 = 34.8k gives a typical operating
range of 33.2V to 81V. The typical under- and overvoltage
shutdownthresholdsarethen29.6Vand84.5V.1%divider
resistorsarerecommendedtopreservethresholdaccuracy.
IN IN IN
EE
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
Internal circuitry monitors V for undervoltage. The exact
IN
thresholds are defined by V
and its hysteresis, V
LKO
.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100µA, and
define an impedance at UV/OV of 32k. In most applica-
tions, 32k impedance coupled with 260mV UV hysteresis
makes the LTC4251-1 insensitive to noise. If more noise
immunity is desired, add a 1nF to 10nF filter capacitor
LKO
LKH
When V rises above 9.2V (V ) the chip is enabled;
IN
below 8.2V (V -V ) it is disabled and GATE is pulled
LKO LKH
low. TheUVLOfunctionatV shouldnotbeconfusedwith
IN
the UV/OV pin. These are completely separate functions.
from UV/OV to V .
EE
UV/OV COMPARATORS
Two hysteretic comparators for detecting under- and
overvoltage conditions, with the following thresholds,
monitor the dual function UV/OV pin:
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the three
remaining interlock conditions are met.
UV turning on at V
UV turning off at V
UVHI
UVLO
425112fc
11
LTC4251/LTC4251-1/
LTC4251-2
applicaTions inForMaTion
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load,
but it will not reset the circuit breaker latch. Returning the
supply voltage to an acceptable range restarts the GATE
pinprovidedallinterlockconditionsexceptTIMERaremet.
Intermittent overloads may exceed the 50mV threshold
at SENSE, but if their duration is sufficiently short TIMER
will not reach 4V and the LTC4251/LTC4251-1/LTC4251-2
will not latch off. To handle this situation, the TIMER
discharges C slowly with a 5.8µA pull-down whenever
T
the SENSE voltage is less than 50mV. Therefore any in-
termittent overload with an aggregate duty cycle of 2.5%
or more will eventually trip the circuit breaker and latch
off the LTC4251/LTC4251-1/LTC4251-2. Figure 3 shows
the circuit breaker response time in seconds normalized
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor, C , is used
at TIMER to provide timing for the LTC4251/LTC4251-1/
LTC4251-2.Fourdifferentcharginganddischargingmodes
are available at TIMER:
T
to 1µF. The asymmetric charging and discharging of C is
T
a fair gauge of MOSFET heating.
10
1. 5.8µA slow charge; initial timing delay
2. 230µA fast charge; circuit breaker delay
3. 5.8µA slow discharge; circuit breaker “cool-off”
1
4. Low impedance switch; resets capacitor after initial
timingdelay,inundervoltagelockout,andinovervoltage
t
4
=
C (µF) (235.8 • D) – 5.8
T
0.1
For initial startup, the 5.8µA pull-up is used. The low im-
pedance switch is turned off and the 5.8µA current source
is enabled when the four interlock conditions are met. C
charges to 4V in a time period given by:
T
0.01
0
20
40
60
80
100
FAULT DUTY CYCLE, D (%)
425112 F03
4V • C
5.8µA
T
t =
Figure 3. Circuit Breaker Response Time
(1)
), the low impedance switch
TMRH
GATE
When C reaches 4V (V
T
turns on and discharges C . The GATE output is enabled
GATE is pulled low to V under any of the following
T
EE
and the load turns on.
conditions: in UVLO, during the initial timing cycle, in an
overvoltage condition, or when the LTC4251/LTC4251-1/
LTC4251-2arelatchedoffafterashort-circuit.WhenGATE
turns on, a 58µA current source charges the MOSFET gate
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than 50mV across R ,
S
and any associated external capacitance. V limits gate
IN
the TIMER pin charges C with 230µA. If C charges to
T
T
drive to no more than 14.5V.
4V, the GATE pin pulls low and the LTC4251/LTC4251-1/
Gate-drain capacitance (C ) feed through at the first
GD
LTC4251-2 latch off. The part remains latched off until
abrupt application of power can cause a gate-source
either the UV/OV pin is momentarily pulsed low, or V
IN
voltage sufficient to turn on the MOSFET. A unique circuit
dips into UVLO and is then restored. The circuit breaker
pulls GATE low with practically no usable voltage at V ,
IN
timeout period is given by
and eliminates current spikes at insertion. A large external
4V • C
230µA
gate-sourcecapacitoristhusunnecessaryforthepurpose
T
t =
of compensating C . Instead, a smaller value (≥10nF)
(2)
GD
capacitor C is adequate. C also provides compensation
C
C
for the analog current limit loop.
425112fc
12
LTC4251/LTC4251-1/
LTC4251-2
applicaTions inForMaTion
SENSE
TIMER commences charging C (Trace 4) while the
T
analog current limit loop maintains the fault current at
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier, and
the fast current limit (FCL) comparator. Each of these
100mV/R , which in this case is 5A (Trace 2). Note that
S
the backplane voltage (Trace 1) sags under load. When C
T
reaches 4V, GATE turns off, the load current drops to zero
and the backplane rings up to over 100V. The positive peak
is usually limited by avalanche breakdown in the MOSFET,
and can be further limited by adding a transient voltage
suppressor across the input from – 48V to –48RTN, such
as Diodes Inc. SMAT70A.
three measures the potential of SENSE relative to V . If
EE
SENSE exceeds 50mV, the CB comparator activates the
230µATIMER pull-up. At100mV, the ACL amplifierservos
the MOSFET current, and at 200mV the FCL compara-
tor abruptly pulls GATE low in an attempt to bring the
MOSFET current under control. If any of these conditions
persists long enough for TIMER to charge C to 4V (see
A low impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 4, Trace 1, can
robchargefromoutputcapacitorsonadjacentcards. When
the faulty card shuts down, current flows in to refresh the
capacitors. IfLTC4251, LTC4251-1orLTC4251-2sareused
throughout, they respond by limiting the inrush current to
T
Equation (2)), the LTC4251/LTC4251-1/LTC4251-2 latch
off and pull GATE low.
IftheSENSEpinencountersavoltagegreaterthan100mV,
theACLamplifierwillservoGATEdownwardsinanattempt
to control the MOSFET current. Since GATE overdrives the
MOSFETinnormaloperation,theACLamplifierneedstime
to discharge GATE to the threshold of the MOSFET. For a
mild overload, the ACL amplifier can control the MOSFET
current, but in the event of a severe overload the current
may overshoot. At SENSE = 200mV, the FCL comparator
a value of 100mV/R . If C is sized correctly, the capacitors
S
T
will recharge long before C times out.
T
SUPPLY RING
SUPPLY RING
OWING
TO CURRENT
OVERSHOOT
OWING TO
MOSFET
–48RTN
50V/DIV
TURN-OFF
takes over, quickly discharging the GATE pin to near V
TRACE 1
TRACE 2
EE
potential. FCL then releases, and the ACL amplifier takes
over. All the while TIMER is running. The effect of FCL is
to add a nonlinear response to the control loop in favor
of reducing MOSFET current.
ONSET OF OUTPUT
SHORT-CIRCUIT
SENSE
200mV/DIV
GATE
10V/DIV
FAST CURRENT
LIMIT
TRACE 3
TRACE 4
ANALOG
CURRENT LIMIT
Owing to inductive effects in the system, FCL typically
overcorrectsthecurrentlimitloop,andGATEundershoots.
TIMER
5V/DIV
LATCH OFF
C
RAMP
TIMER
A zero in the loop (resistor R in series with the gate
C
425112 F04
2ms/DIV
capacitor) helps the ACL amplifier recover.
Figure 4. Output Short-Circuit Behavior
(All Waveforms are Referenced to VEE)
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load-side low impedance
short is shown in Figure 4. Initially, the current overshoots
MOSFET SELECTION
The external MOSFET switch must have adequate safe
operating area (SOA) to charge the load capacitance on
start-up and handle short-circuit conditions until TIMER
latchoff. These considerations take precedence over DC
current ratings. A MOSFET with adequate SOA for a given
application can always handle the required current, but
the opposite cannot be said. Consult the manufacturer’s
MOSFET data sheet for safe operating area and effective
transient thermal impedance curves.
the analog current limit level of V
= 100mV (Trace 2)
SENSE
astheGATEpinworkstobringV undercontrol(Trace3).
GS
The overshoot glitches the backplane in the negative
direction, and when the current is reduced to 100mV/R
S
the backplane responds by glitching in the positive
direction.
425112fc
13
LTC4251/LTC4251-1/
LTC4251-2
applicaTions inForMaTion
MOSFET selection is a three-step process. First, R is
calculated, and then the time required to charge the load
capacitance is determined. This timing, along with the
maximum short-circuit current and maximum input volt-
age defines an operating point that is checked against the
MOSFET’s SOA curve.
Substituting Equation (4) for I
(6) with (2) gives:
and equating
(7)
INRUSH(MIN)
S
C • V
•R • 230µA
S
(4V • 80mV)
L
SUPPLY (MAX)
C =
T
Returning to Equation (2), the TIMER period is calcu-
lated and used in conjunction with V and
To begin a design, first specify the required load current
SUPPLY(MAX)
and load capacitance, I and C . The circuit breaker current
L
L
I
to check the SOA curves of a prospec-
SHORT-CIRCUIT(MAX)
trip point (50mV/R ) should be set to accommodate the
S
tive MOSFET.
As a numerical design example, consider a 30W load,
which requires 1A input current at 36V. If V
maximum load current. Note that maximum input current
to a DC/DC converter is expected at V
given by:
. R is
SUPPLY (MIN)
S
=
SUPPLY(MAX)
72V and C = 100µF, Equation (3) gives R
= 40mΩ;
L
SENSE
40mV
Equation (7) gives C = 207nF. To account for errors in
R =
T
S
I
(3)
L(MAX)
R
SENSE
, C , TIMER current (230µA) and TIMER threshold
T
(4V), the calculated value should be multiplied by 1.5,
where 40mV represents the guaranteed minimum circuit
breaker threshold.
giving a nearest standard value of C = 330nF.
T
If a short-circuit occurs, a current of up to 120mV/40mΩ
= 3A will flow in the MOSFET for 5.7ms as dictated by
T
based on this criterion. The IRF530S can handle 100V and
3A for 10ms, and is safe to use in this application.
During the initial charging process, the LTC4251/
LTC4251-1/LTC4251-2mayoperatetheMOSFETincurrent
C = 330nF in Equation (2). The MOSFET must be selected
limit, forcing 80mV to 120mV across R . The minimum
S
inrush current is given by:
80mV
I
=
INRUSH(MIN)
SUMMARY OF DESIGN FLOW
(4)
R
S
To summarize the design flow, consider the application
shown in Figure 2, which was designed for 50W:
Maximum short-circuit current limit is calculated using
maximum V , or:
SENSE
Calculate maximum load current: 50W/36V = 1.4A; allow-
120mV
ing 83% converter efficiency, I
= 1.7A.
IN (MAX)
I
=
SHORT-CIRCUIT(MAX)
(5)
R
S
Calculate R : from Equation (3) R = 20mΩ.
S
S
Calculate C : from Equation (7) C = 150nF (including
The TIMER capacitor C must be selected based on the
T
T
T
1.5X correction factor).
slowest expected charging rate; otherwise TIMER might
time out before the load capacitor is fully charged. A value
CalculateTIMERperiod:fromEquation(2)theshort-circuit
time-out period is t = 2.6ms.
for C is calculated based on the maximum time it takes
T
the load capacitor to charge. That time is given by:
Calculate maximum short-circuit current: from Equation
(5) maximum short-circuit current could be as high as
120mV/20mΩ = 6A.
C • V C • V
I
L
SUPPLY(MAX)
I
INRUSH(MIN)
t
=
=
CL CHARGE
(6)
Consult MOSFET SOA curves: the IRF530S can handle
6A at 72V for 5ms, so it is safe to use in this application.
425112fc
14
LTC4251/LTC4251-1/
LTC4251-2
applicaTions inForMaTion
FREQUENCY COMPENSATION
resistor.PCBlayoutshouldbebalancedandsymmetricalto
minimize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
The LTC4251/LTC4251-1/LTC4251-2 typical frequency
compensation network for the analog current limit loop
is a series R (10Ω) and C connected to V . Figure 5
C
C
EE
depicts the relationship between the compensation ca-
pacitor C and the MOSFET’s C . The line in Figure 5
C
ISS
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
is used to select a starting value for C based upon the
C
MOSFET’s C specification. Optimized values for C are
ISS
C
shown for several popular MOSFETs. Differences in the
SENSE RESISTOR
TRACK WIDTH W:
optimized value of C versus the starting value are small.
C
W
0.03" PER AMP
ON 1 OZ COPPER
Nevertheless, compensation values should be verified by
board level short-circuit testing.
425112 F06
As seen in Figure 4 previously, at the onset of a short-
circuitevent,theinputsupplyvoltagecanringdramatically
owing to series inductance. If this voltage avalanches the
MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
TO
TO
EE
SENSE
V
Figure 6. Making PCB Connections to the Sense Resistor
TIMING WAVEFORMS
System Power-Up
60
Figure 7 details the timing waveforms for a typical
power-up sequence in the case where a board is already
installed in the backplane and system power is applied
abruptly. At time point 1, the supply ramps up, together
MTY100N10E
50
40
IRF3710
30
with UV/OV and V . V follows at a slower rate as set
OUT IN
IRF540
by the V bypass capacitor. At time point 2, V exceeds
IRF530
IN
IN
20
V
V
and the internal logic checks for V
, TIMER < V
< UV/OV <
LKO
OVLO
UVHI
IRF740
10
, GATE < V
and SENSE < V .
TMRL
GATEL CB
When all conditions are met, an initial timing cycle starts
0
0
4000
MOSFET C (pF)
6000
2000
8000
and the TIMER capacitor is charged by a 5.8µA current
ISS
source pull-up. At time point 3, TIMER reaches the V
TMRH
425112 F05
threshold and the initial timing cycle terminates. The
Figure 5. Recommended Compensation
Capacitor CC vs MOSFET CISS
TIMER capacitor is then quickly discharged. At time point
4, the V
threshold is reached and the conditions of
and SENSE < V must be satisfied before
TMRL
GATE < V
GATEL
CB
SENSE RESISTOR CONSIDERATIONS
a start-up cycle is allowed to begin. GATE sources 58µA
intotheexternalMOSFETgateandcompensationnetwork.
When the GATE voltage reaches the MOSFET’s threshold,
current begins flowing into the load capacitor. At time
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the V and
SENSE pins are strongly recommended. The drawing in
Figure 6 illustrates the correct way of making connections
betweentheLTC4251/LTC4251-1/LTC4251-2andthesense
EE
point5, theSENSEvoltage(V
–V )reachestheV
SENSE
EE CB
threshold and activates the TIMER. The TIMER capacitor
425112fc
15
LTC4251/LTC4251-1/
LTC4251-2
applicaTions inForMaTion
is charged by a 230µA current-source pull-up. At time
point 6, the analog current limit loop activates. Between
time point 6 and time point 7, the GATE voltage is held
essentially constant and the sense voltage is regulated at
decline.Attimepoint7,theloadcurrentfallsandthesense
voltage drops below V . The analog current limit loop
ACL
shuts off and the GATE pin ramps further. At time point
8, the sense voltage drops below V and TIMER now
CB
V
. As the load capacitor nears full charge, its current
discharges through a 5.8µA current source pull-down.
ACL
begins to decline. At point 7, the load current falls and
At time point 9, GATE reaches its maximum voltage as
the sense voltage drops below V . The analog current
determined by V .
ACL
IN
limit loop shuts off and the GATE pin ramps further. At
Undervoltage Lockout Timing
time point 8, the sense voltage drops below V and
CB
TIMER now discharges through a 5.8µA current source
InFigure9,whenUV/OVdropsbelowV
(timepoint1),
UVLO
pull-down. At time point 9, GATE reaches its maximum
TIMER and GATE pull low. If current has been flowing, the
SENSE pin voltage decreases to zero as GATE collapses.
voltage as determined by V .
IN
When UV/OV recovers and clears V
(time point 2),
UVHI
Live Insertion with Short Pin Control of UV/OV
an initial time cycle begins followed by a start-up cycle.
In this example as shown in Figure 8, power is delivered
through long connector pins whereas the UV/OV divider
makescontactthroughashortpin.Thisensuresthepower
connections are firmly established before the LTC4251/
LTC4251-1/LTC4251-2 are activated. At time point 1, the
Undervoltage Timing with Overvoltage Glitch
In Figure 10, when UV/OV clears V
(time point 1),
UVHI
an initial timing cycle starts. If the system bus voltage
overshoots V as shown at time point 2, TIMER dis-
OVHI
power pins make contact and V ramps through V
.
IN
LKO
charges. At time point 3, the supply voltage recovers and
At time point 2, the UV/OV divider makes contact and
drops below the V
threshold. The initial timing cycle
OVLO
its voltage exceeds V . In addition, the internal logic
UVHI
< UV/OV < V
restarts followed by a start-up cycle.
checks for V
, TIMER < V
, GATE
TMRL
UVHI
OVHI
< V
and SENSE < V . When all conditions are met,
Overvoltage Timing
GATEL
CB
an initial timing cycle starts and the TIMER capacitor
During normal operation, if UV/OV exceeds V
as
OVHI
is charged by a 5.8µA current source pull-up. At time
shown at time point 1 of Figure 11, the TIMER status is
unaffected. Nevertheless, GATE pulls down and discon-
nects the load. At time point 2, UV/OV recovers and drops
point 3, TIMER reaches the V
threshold and the ini-
TMRH
tial timing cycle terminates. The TIMER capacitor is then
quickly discharged. At time point 4, the V threshold
TMRL
below the V
threshold. A gate ramp up cycle ensues.
OVLO
is reached and the conditions of GATE < V
and
GATEL
If the overvoltage glitch is long enough to deplete the
load capacitor, a full start-up cycle may occur as shown
between time points 3 through 6.
SENSE < V must be satisfied before a start-up cycle is
CB
allowed to begin. GATE sources 58µA into the external
MOSFET gate and compensation network. When the
GATE voltage reaches the MOSFET’s threshold, current
begins flowing into the load capacitor. At time point 5, the
Timer Behavior
In Figure 12a, the TIMER capacitor charges at 230µA if
SENSE voltage (V
– V ) reaches the V threshold
SENSE
EE CB
the SENSE pin exceeds V . It is discharged with 5.8µA
and activates the TIMER. The TIMER capacitor is charged
by a 230µA current source pull-up. At time point 6, the
analog current limit loop activates. Between time point
6 and time point 7, the GATE voltage is held essentially
CB
if the SENSE pin is less than V . In Figure 12b, when
CB
TIMERexceedsV
,TIMERislatchedhighbythe5.8µA
TMRH
pull-up and GATE pulls down immediately. In Figure 12c,
multiple momentary faults cause the TIMER capacitor to
integrate until it latches.
constant and the sense voltage is regulated at V . As
ACL
the load capacitor nears full charge, its current begins to
425112fc
16
LTC4251/LTC4251-1/
LTC4251-2
applicaTions inForMaTion
V
IN
CLEARS V , CHECK V
LKO UVHI
<UV/0V < V
OVLO
, TIMER< V , GATE < V
TMRL GATEL
AND SENSE < V
CB
.
TIMER CLEARS V
, CHECK GATE < V
TMRL
AND SENSE < V .
CB
GATEL
1
2
3
4
5 6
7 8
9
GND-V
EE
UV/0V
V
LKO
V
IN
V
TMRH
5.8µA
TIMER
GATE
230µA
5.8µA
V
TMRL
5.8µA
58µA
58µA
V
V
ACL
SENSE
CB
V
OUT
425112 F07
INITIAL TIMING CYCLE
START-UP CYCLE
Figure 7. System Power-Up Timing (All Waveforms are Referenced to VEE)
UV/0V CLEARS V , CHECK V < V
UVHI IN
– V , TIMER < V , GATE < V
LKH TMRL GATEL
AND SENSE < V .
CB
LKO
TIMER CLEARS V
, CHECK GATE < V
AND SENSE < V .
CB
TMRL
GATEL
1
2
3
4
5 6
7 8
9
GND-V
EE
V
UVHI
UV/0V
V
LKO
V
IN
V
TMRH
5.8µA
TIMER
GATE
230µA
5.8µA
V
TMRL
5.8µA
58µA
58µA
V
V
ACL
CB
SENSE
V
OUT
425112 F08
INITIAL TIMING CYCLE
START-UP CYCLE
Figure 8. Power-Up Timing with a Short-Pin (All Waveforms are Referenced to VEE)
425112fc
17
LTC4251/LTC4251-1/
LTC4251-2
applicaTions inForMaTion
Analog Current Limit and Fast Current Limit
An initial timing cycle is initiated if UV/OV is used for reset.
IfTIMERisusedforreset,theinitialtimingcycleisskipped.
InFigure13a,whenSENSEexceedsV ,GATEisregulated
ACL
by the analog current limit amplifier loop. When SENSE
Internal Soft-Start
drops below V , GATE is allowed to pull up. In Figure
ACL
An internal soft-start feature ramps the positive input of
the analog current limit amplifier during initial start-up.
The ramp duration is approximately 200µs. This feature
reduces load current dl/dt at start-up. As illustrated in
Figure 15, soft-start is initiated by a TIMER transition from
13b, when a severe fault occurs, SENSE exceeds V
FCL
and GATE immediately pulls down until the analog current
amplifier can establish control. If TIMER reaches V
GATE pulls low and latches off.
,
TMRH
Resetting a Fault Latch
V
to V
or when UV/OV falls below the V
TMRL OVLO
TMRH
threshold after an OV fault. After soft-start duration, load
current is limited by V /R .
As shown in Figure 14, a latched fault is reset by either
ACL
S
pullingUV/OVbelowV
orpullingTIMERbelowV
.
UVLO
TMRL
V
DROPS BELOW V
. TIMER, GATE, AND SENSE ARE PULLED TO V .
UV/0V
2
UVLO EE
V
CLEARS V
, CHECK TIMER < V
, GATE < V
3
AND SENSE < V .
GATEL CB
TIMER CLEARS V
UV/0V
UVHI
TMRL
, CHECK GATE < V
AND SENSE < V .
CB
TMRL
GATEL
1
4
5 6
7 8 9
V
UVHI
UV/0V
V
UVLO
V
TMRH
5.8µA
230µA
TIMER
GATE
5.8µA
V
TMRL
5.8µA
58µA
58µA
V
V
ACL
CB
SENSE
425112 F09
INITIAL TIMING CYCLE
START-UP CYCLE
Figure 9. Undervoltage Lockout Timing (All Waveforms are Referenced to VEE)
425112fc
18
LTC4251/LTC4251-1/
LTC4251-2
applicaTions inForMaTion
V
UV/0V
CLEARS V
. CHECK TIMER < V
, GATE < V AND SENSE < V .
GATEL CB
UVHI
TMRL
V
OVERSHOOTS V
AND TIMER ABORTS INITIAL TIMING CYCLE.
UV/0V
OVHI
V
DROPS BELOW V
AND TIMER RESTARTS INITIAL TIMING CYCLE.
UV/0V
OVLO
TIMER CLEARS V
, CHECK GATE < V
AND SENSE < V .
CB
TMRL
GATEL
1
2 3
4
5
6 7
8 9 10
V
OVHI
V
OVLO
UV/0V
TIMER
GATE
V
UVHI
V
TMRH
5.8µA
230µA
5.8µA
V
TMRL
5.8µA
58µA
58µA
V
V
ACL
CB
SENSE
425112 F10
START-UP CYCLE
INITIAL TIMING CYCLE
Figure 10. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE)
V
OVERSHOOTS V AND GATE PULLS TO V . TIMER UNAFFECTED.
OVHI EE
UV/0V
V
UV/0V
DROPS BELOW V AND GATE RESTARTS.
OVLO
1
2
3 4
5 6
7
V
OVHI
UV/0V
V
OVLO
V
TMRH
230µA
TIMER
5.8µA
5.8µA
5.8µA
5.8µA
58µA
GATE
58µA
V
V
ACL
CB
SENSE
425112 F11
Figure 11. Overvoltage Timing (All Waveforms are Referenced to VEE)
425112fc
19
LTC4251/LTC4251-1/
LTC4251-2
applicaTions inForMaTion
TIMER LATCHES OFF
2
5.8µA
1
2
1
V
V
TMRH
TMRL
230µA
TIMER
GATE
230µA
5.8µA
TIMER
GATE
5.8µA
V
V
ACL
CB
V
ACL
SENSE
V
SENSE
CB
V
OUT
V
OUT
CB FAULT
425112 F12a
CB FAULT
425112 F12b
(12a) Momentary Circuit-Breaker Fault
(12b) Circuit-Breaker Time-Out
TIMER LATCHES OFF
4
5.8µA
1
2
3
230µA
V
TMRH
5.8µA
230µA
TIMER
GATE
V
V
ACL
SENSE
CB
V
OUT
425112 F12c
(12c) Multiple Circuit-Breaker Faults
Figure 12. Timer Behavior (All Waveforms are Referenced to VEE)
425112fc
20
LTC4251/LTC4251-1/
LTC4251-2
applicaTions inForMaTion
TIMER LATCHES OFF
1
2
1 2
3 4
5.8µA
V
TMRH
V
TMRH
230µA
TIMER
GATE
TIMER
GATE
230µA
5.8µA
5.8µA
58µA
V
V
FCL
ACL
V
ACL
V
SENSE
SENSE
CB
V
CB
V
V
OUT
OUT
425112 F13b
425112 F13a
(13a) Analog Current Limit Fault
(13b) Fast Current Limit Fault
Figure 13. Current Limit Behavior (All Waveforms are Referenced to VEE)
END OF INITIAL TIMING CYCLE
1
2
3
4
5
6
RESET LATCHED TIMER FAULT BY EXTERNAL LOW PULSE.
1 2 3 4 5 6
5.8µA
V
TMRH
5.8µA
TIMER
GATE
V
TMRH
230µA
~V
V
TMRL
230µA
TIMER
5.8µA
V
TMRL
5.8µA
GS(th)
58µA
58µA
GATE
58µA
V
ACL
V
V
ACL
SENSE
V
CB
SENSE
CB
V
+ 10mV
ACL
INTERNAL
SOFT-START
REFERENCE
425112 F14
10mV
425112 F15
Figure 14. Latched Fault Reset Timing
(All Waveforms are Referenced to VEE)
Figure 15. Internal Soft-Start Timing
(All Waveforms are Referenced to VEE)
425112fc
21
LTC4251/LTC4251-1/
LTC4251-2
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.4 MIN
1.50 – 1.75
(NOTE 4)
2.80 BSC
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
425112fc
22
LTC4251/LTC4251-1/
LTC4251-2
revision hisTory (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
3/11
Revised Typical Application drawings
Replaced Shunt Regulator section in Applications Information section
Revised Short-Circuit Operation section
Not recommended for new designs
1, 24
11
13
C
3/12
1
425112fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC4251/LTC4251-1/
LTC4251-2
Typical applicaTions
–48RTN
R
IN
+
–48RTN
(SHORT PIN)
10k
C
L
LOAD
500mW
100µF
R1
402k
1%
3
†
C
D
IN
IN
V
IN
1µF
DDZ13B**
5
4
6
1
Q1
IRF540
UV/OV GATE
LTC4251
C1
10nF
R3
22Ω
3
4
TIMER SENSE
R2
32.4k
1%
1
R
C
V
EE
R
S
PUSH-
RESET
10Ω
S1
C
82nF
0.01Ω
2
C
C
T
22nF
2
425112 TA03
–48V
**DIODES, INC.
†RECOMMENDED FOR HARSH ENVIRONMENTS
Figure 16. –48V/5A Application with Reverse SENSE Pin Limiting and Push-Reset at TIMER Pin
–48RTN
R
IN
R3
31.6k
+
L
–48RTN
(SHORT PIN)
10k
C
LOAD
500mW
100µF
R1
442k
1%
V
3
OUT
†
C
D1
D
IN
IN
V
IN
1µF
BZX84C36
DDZ13B**
5
4
6
1
Q1
IRF540S
UV/OV GATE
LTC4251-1
C1
10nF
R4
22Ω
3
TIMER SENSE
1
R2
34.8k
1%
R
C
R
V
S
EE
10Ω
0.02Ω
2
C
C
T
C
2
220nF
22nF
4
425112 TA04
–48V
**DIODES, INC.
†RECOMMENDED FOR HARSH ENVIRONMENTS
Figure 17. Power-Limited Circuit Breaker Application
relaTeD parTs
PART NUMBER
LT1640AH/LT1640AL
LT1641-1/LT1641-2
LTC1642
DESCRIPTION
COMMENTS
Negative High Voltage Hot Swap Controllers in SO-8
Positive High Voltage Hot Swap Controllers in SO-8
Fault Protected Hot Swap Controller
Negative High Voltage Supplies from –10V to –80V
Supplies from 9V to 80V, Latched Off/Autoretry
3V to 16.5V, Overvoltage Protection up to 33V
LTC1921
Dual –48V Supply and Fuse Monitor
1V UV and 1.5V OV Threshold Accuracy, 200V Transient
Protection, Drives Three Optoisolators for Status
LT4250
–48V Hot Swap Controller in SO-8
Active Current Limiting, Supplies from –20V to –80V
LTC4252-1/ LTC4252-2
Negative Voltage Hot Swap Controller in MSOP
Fast Active Current Limiting with Drain Accelerated Response,
Supplies from –15V
LTC4253
Negative Voltage Hot Swap Controller with
3-Output Sequencer
Fast Active Current Limiting with Drain Accelerated Response,
Supplies from –15V
425112fc
LT 0312 REV C • PRINTED IN USA
24 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2001
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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