LTC4252A-1IMSPBF [Linear]
Negative Voltage Hot Swap Controllers; 负电压热插拔控制器型号: | LTC4252A-1IMSPBF |
厂家: | Linear |
描述: | Negative Voltage Hot Swap Controllers |
文件: | 总36页 (文件大小:387K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
Negative Voltage
Hot Swap Controllers
U
FEATURES
DESCRIPTIO
■
Allows Safe Board Insertion and Removal from a
The LTC®4252 negative voltage Hot SwapTM controller
allows a board to be safely inserted and removed from a
livebackplane.Outputcurrentiscontrolledbythreestages
of current limiting: a timed circuit breaker, active current
limiting and a fast feedforward path that limits peak
current under worst-case catastrophic fault conditions.
Live –48V Backplane
■
Floating Topology Permits Very High Voltage
Operation
■
Programmable Analog Current Limit With Circuit
Breaker Timer
■
Fast Response Time Limits Peak Fault Current
Adjustable undervoltage and overvoltage detectors dis-
connect the load whenever the input supply exceeds the
desired operating range. The LTC4252’s supply input is
shunt regulated, allowing safe operation with very high
supply voltages. A multifunction timer delays initial start-
up and controls the circuit breaker’s response time. The
circuit breaker’s response time is accelerated by sensing
excessive MOSFET drain voltage, keeping the MOSFET
within its safe operating area (SOA). An adjustable soft-
start circuit controls MOSFET inrush current at start-up.
■
Programmable Soft-Start Current Limit
■
Programmable Timer with Drain Voltage
Accelerated Response
■
±1% Undervoltage/Overvoltage Threshold Accuracy
(LTC4252A)
■
Adjustable Undervoltage/Overvoltage Protection
■
LTC4252-1/LTC4252A-1: Latch Off After Fault
■
LTC4252-2: Automatic Retry After Fault
■
Available in 8-Pin and 10-Pin MSOP Packages
U
TheLTC4252-1/LTC4252A-1latchoffafteracircuitbreaker
fault times out. The LTC4252-2 provides automatic retry
after a fault. The LTC4252A-1/LTC4252A-2 feature tight
±1% undervoltage/overvoltage threshold accuracy. The
LTC4252 is available in either an 8-pin or 10-pin MSOP.
APPLICATIO S
■
Hot Board Insertion
■
Electronic Circuit Breaker
■
–48V Distributed Power Systems
■
Negative Power Supply Control
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
■
Central Office Switching
■
High Availability Servers
■
ATCA
U
TYPICAL APPLICATIO
Start-Up Behavior
–48V/2.5A Hot Swap Controller
GND
R
IN
+
3× 1.8k IN SERIES
C
L
GATE
1/4W EACH
100µF
LOAD
EN
5V/DIV
C
IN
1µF
R3
GND
5.1k
(SHORT PIN)
V
R1
402k
1%
IN
LTC4252-1
PWRGD
SENSE
2.5A/DIV
V
OUT
*
OV
R
D
1M
UV
DRAIN
GATE
R2
32.4k
1%
Q1
IRF530S
V
OUT
TIMER
SS
20V/DIV
C
T
SENSE
V
EE
0.33µF
R
R
S
0.02Ω
C
C1
10nF
C
10Ω
C
SS
68nF
C
18nF
PWRGD
10V/DIV
4252-1/2 TA01
–48V
1ms/DIV
4252-1/2 TA01a
* M0C207
425212fb
1
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
W W U W
ABSOLUTE AXI U RATI GS
All Voltages Referred to V (Note 1)
EE
Current into VIN (100µs Pulse) ........................... 100mA
VIN, DRAIN Pin Minimum Voltage ....................... –0.3V
Input/Output Pins
(Except SENSE and DRAIN) Voltage ..........–0.3V to 16V
SENSE Pin Voltage ................................... –0.6V to 16V
Current Out of SENSE Pin (20µs Pulse)........... –200mA
Current into DRAIN Pin (100µs Pulse) ................. 20mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range
LTC4252-1C/LTC4252-2C
LTC4252A-1C/LTC4252A-2C ................... 0°C to 70°C
LTC4252-1I/LTC4252-2I
LTC4252A-1I/LTC4252A-2I ............... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
V
1
2
3
4
5
10 TIMER
IN
V
SS
SENSE
1
2
3
4
8 TIMER
7 UV/OV
6 DRAIN
5 GATE
IN
PWRGD
SS
9
8
7
6
UV
OV
DRAIN
GATE
SENSE
V
EE
V
EE
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 160°C/W
TJMAX = 125°C, θJA = 160°C/W
ORDER PART NUMBER
MS8 PART MARKING
ORDER PART NUMBER
MS PART MARKING
LTC4252-1CMS8
LTC4252-2CMS8
LTC4252-1IMS8
LTC4252-2IMS8
LTWM
LTWP
LTRQ
LTRR
LTC4252-1CMS
LTC4252-2CMS
LTC4252A-1CMS
LTC4252A-2CMS
LTC4252-1IMS
LTC4252-2IMS
LTC4252A-1IMS
LTC4252A-2IMS
LTWN
LTWQ
LTAFX
LTAGE
LTRS
LTRT
LTAFY
LTAGF
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
425212fb
2
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 2)
A
LTC4252-1/-2
MIN TYP MAX MIN TYP MAX UNITS
LTC4252A-1/-2
SYMBOL PARAMETER
CONDITIONS
V
V
V
V
V
V
– V Zener Voltage
I
I
= 2mA
●
11.5 13 14.5
5
11.5 13
14.5
V
Ω
Z
IN
IN
IN
IN
IN
EE
IN
IN
r
– V Zener Dynamic Impedance
= 2mA to 30mA
5
Z
EE
I
Supply Current
UV = OV = 4V, V = (V – 0.3V)
●
●
0.8
2
0.9
9
2
mA
V
IN
IN
Z
V
V
V
V
Undervoltage Lockout
Undervoltage Lockout Hysteresis
Coming Out of UVLO (Rising V )
9.2 11.5
1
10
LKO
LKH
CB
IN
0.5
V
Circuit Breaker Current Limit Voltage
Analog Current Limit Voltage
V
V
= (V
– V )
EE
●
●
40
80
50
60
45
50
55
mV
mV
CB
SENSE
= (V
– V ),
EE
100 120
ACL
ACL
SENSE
SS = Open or 2.2V
V
V
Analog Current Limit Voltage
Circuit Breaker Voltage
V
= (V – V ),
●
●
1.05 1.20 1.38
V/V
ACL
CB
ACL
SENSE
EE
SS = Open or 1.4V
= (V – V )
EE
V
V
Fast Current Limit Voltage
SS Voltage
V
FCL
150 200 300
150 200 300
mV
V
FCL
SS
SENSE
After End of SS Timing Cycle
2.2
100
22
1.4
50
28
R
SS Output Impedance
SS Pin Current
kΩ
µA
SS
I
UV = OV = 4V, V
= V
= V
,
,
SS
SENSE
= 0V (Sourcing)
EE
V
SS
UV = OV = 0V, V
28
28
mA
SENSE
EE
V
SS
= 2V (Sinking)
V
V
Analog Current Limit Offset Voltage
10
10
mV
V/V
OS
+V
SS
Ratio (V
+ V ) to SS Voltage
0.05
0.05
ACL OS
V
ACL
OS
I
GATE Pin Output Current
UV = OV = 4V, V
= V
,
●
40
10
58
17
80
40
10
58
17
80
µA
mA
mA
GATE
SENSE
EE
V
GATE
= 0V (Sourcing)
UV = OV = 4V, V
– V = 0.15V,
EE
SENSE
V
GATE
= 3V (Sinking)
UV = OV = 4V, V
– V = 0.3V,
190
190
SENSE
EE
V
GATE
V
GATE
V
GATEH
= 1V (Sinking)
V
V
External MOSFET Gate Drive
Gate High Threshold
– V , I = 2mA
●
12
V
12
V
Z
V
V
GATE
EE IN
Z
= V – V , I = 2mA,
GATE IN
2.8
2.8
GATEH
IN
for PWRGD Status (MS Only)
V
V
V
V
V
V
V
V
V
Gate Low Threshold
(Before Gate Ramp-Up)
0.5
0.5
V
V
GATEL
UVHI
UVLO
UV
UV Pin Threshold HIGH
UV Pin Threshold LOW
UV Pin Threshold
●
●
●
●
●
●
●
●
●
●
3.075 3.225 3.375
2.775 2.925 3.075
V
Low-to-High Transition
3.05 3.08 3.11
292 324 356
V
UV Pin Hysteresis
(●
for LTC4252A Only)
300
mV
V
UVHST
OVHI
OVLO
OV
OV Pin Threshold HIGH
OV Pin Threshold LOW
OV Pin Threshold
5.85 6.15 6.45
5.25 5.55 5.85
V
Low-to-High Transition
for LTC4252A Only)
5.04 5.09 5.14
V
OV Pin Hysteresis
(●
600
82
102 122
mV
µA
µA
V
OVHST
SENSE
INP
I
I
SENSE Pin Input Current
UV, OV Pin Input Current
TIMER Pin Voltage High Threshold
TIMER Pin Voltage Low Threshold
UV = OV = 4V, V
UV = OV = 4V
= 50mV
–15 –30
–15 –30
SENSE
±0.1 ±1
±0.1 ±1
V
V
4
1
4
1
TMRH
TMRL
V
425212fb
3
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. (Note 2)
A
LTC4252-1/-2
MIN TYP MAX MIN TYP MAX UNITS
LTC4252A-1/-2
SYMBOL PARAMETER
TIMER Pin Current
CONDITIONS
I
Timer On (Initial Cycle/Latchoff/
Shutdown Cooling, Sourcing),
5.8
5.8
µA
TMR
V
= 2V
TMR
Timer Off (Initial Cycle, Sinking),
= 2V
28
28
mA
µA
µA
µA
V
TMR
Timer On (Circuit Breaker, Sourcing,
= 0µA), V = 2V
230
630
5.8
230
630
5.8
I
DRN
TMR
Timer On (Circuit Breaker, Sourcing,
= 50µA), V = 2V
I
DRN
TMR
Timer Off (Circuit Breaker/
Shutdown Cooling, Sinking),
V
= 2V
TMR
∆I
[(I
TMR
at I
= 50µA) – (I
at I = 0µA)] Timer On (Circuit Breaker with
DRN
8
8
µA/µA
TMRACC
DRN
TMR
∆I
∆I
I
= 50µA)
DRN
DRN
DRN
V
DRAIN Pin Voltage Low Threshold
DRAIN Leakage Current
For PWRGD Status (MS Only)
= 5V (4V for LTC4252A)
2.385
2.385
V
µA
V
DRNL
I
V
±0.1 ±1
±0.1 ±1
DRNL
DRAIN
V
V
DRAIN Pin Clamp Voltage
PWRGD Output Low Voltage
I
= 50µA
DRN
7
6
DRNCL
PGL
I
I
= 1.6mA (MS Only)
= 5mA (MS Only)
●
●
0.2
0.4
1.1
0.2
0.4
1.1
V
V
PG
PG
I
t
PWRGD Pull-Up Current
SS Default Ramp Period
V
= 0V (Sourcing) (MS Only)
PWRGD
●
40
58
80
40
58
80
µA
µs
PGH
SS
SS pin floating, V ramps from
0.2V to 2V
180
SS
SS pin floating, V ramps from
0.1V to 0.9V
230
µs
SS
t
t
UV Low to Gate Low
OV High to Gate Low
0.4
0.4
0.4
0.4
µs
µs
PLLUG
PHLOG
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to V unless otherwise
EE
specified.
425212fb
4
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
r vs Temperature
V vs Temperature
I
vs Temperature
Z
Z
IN
10
9
2000
1800
1600
1400
1200
1000
800
14.5
14.0
13.5
13.0
12.5
12.0
I
= 2mA
V
= (V – 0.3V)
I
IN
= 2mA
IN
IN
Z
8
7
6
5
600
4
400
3
200
2
0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G04
4252-1/2 G03
4252-1/2 G01
Undervoltage Lockout V
vs Temperature
Undervoltage Lockout Hysteresis
vs Temperature
LKO
V
LKH
I
vs V
IN
IN
12.0
11.5
11.0
10.5
10.0
9.5
1000
100
10
1.5
1.3
T
= –40°C
A
T
= 25°C
= 85°C
A
1.1
T
A
0.9
0.7
0.5
T
= 125°C
A
9.0
1
8.5
8.0
0.1
–55 –35 –15
5
25 45 65 85 105 125
0
2
4
6
8
10 12 14 16 18 20 22
(V)
–55 –35 –15
5
25 45 65 95 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
V
IN
4252-1/2 G05
4252-1/2 G02
4252-1/2 G06
Analog Current Limit Voltage
vs Temperature
Circuit Breaker Current Limit
Voltage V vs Temperature
Fast Current Limit Voltage V
vs Temperature
FCL
V
CB
ACL
120
115
110
105
100
95
300
275
250
225
200
175
150
60
58
56
54
52
50
48
46
44
42
40
90
85
80
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G08
4252-1/2 G09
4252-1/2 G07
425212fb
5
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
I
(Sinking) vs Temperature
V
SS
vs Temperature
R
vs Temperature
SS
SS
45
40
35
30
25
20
15
10
5
110
108
106
104
102
100
98
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
UV = OV = V
= V
EE
SENSE
I
= 2mA
IN
SS
V
= 2V
96
94
92
0
90
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45
125
65 85 105
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G28
4252-1/2 G39
4252-1/2 G26
V
vs Temperature
(V
+ V )/V vs Temperature
I
(Sourcing) vs Temperature
OS
ACL
OS SS
GATE
70
11.0
10.8
10.6
10.4
10.2
10.0
9.8
0.060
0.058
0.056
0.054
0.052
0.050
0.048
0.046
0.044
0.042
0.040
UV/0V = 4V
TIMER = 0V
V
V
= V
= 0V
65
60
55
50
45
40
SENSE
GATE
EE
9.6
9.4
9.2
9.0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G10
4252-1/2 G29
4252-1/2 G30
I
(ACL, Sinking)
I
(FCL, Sinking)
GATE
GATE
vs Temperature
vs Temperature
V
vs Temperature
GATE
400
350
300
250
200
150
100
50
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
30
25
20
15
10
5
UV/0V = 4V
TIMER = 0V
UV/0V = 4V
TIMER = 0V
SENSE EE
UV/0V = 4V
TIMER = 0V
V
V
– V = 0.3V
V
= V
V
V
– V = 0.15V
SENSE
= 1V
EE
SENSE
GATE
EE
= 3V
GATE
0
0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
45
85 105 125
–55 –35 –15
5
25 45 65 85 105 125
25
65
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G12
4252-1/2 G13
4252-1/2 G11
425212fb
6
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
V
vs Temperature
V
vs Temperature
GATEL
UV Threshold vs Temperature
GATEH
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.375
3.275
3.175
3.075
2.975
2.875
2.775
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
UV/0V = 4V
TIMER = 0V
GATE THRESHOLD
BEFORE RAMP-UP
V
I
= V – V
IN
,
GATE
GATEH
IN
= 2mA
(MS ONLY)
V
UVH
V
UV
V
UVL
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G14
4252-1/2 G15
4252-1/2 G31
I
vs Temperature
I
vs (V
– V )
OV Threshold vs Temperature
SENSE
SENSE
SENSE EE
6.45
6.25
6.05
5.85
5.65
5.45
5.25
5.05
4.85
–10
–12
–14
–16
–18
–20
–22
–24
–26
–28
–30
0.01
0.1
V
OVH
1.0
V
OVL
10
UV/0V = 4V
TIMER = 0V
GATE = HIGH
UV/0V = 4V
V
OV
100
1000
TIMER = 0V
GATE = HIGH
V
– V = 50mV
EE
T
A
= 25°C
SENSE
–55 –35 –15
5
25 45 65 85 105 125
–1.5 –1.0 –0.5
(V
0
0.5 1.0 1.5
– V ) (V)
2.0
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
SENSE
EE
4252-1/2 G16
4252-1/2 G18
4252-1/2 G17
I
(Initial Cycle, Sourcing)
I
(Initial Cycle, Sinking)
TIMER Threshold
vs Temperature
TMR
TMR
vs Temperature
vs Temperature
50
45
40
35
30
25
20
15
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9
8
7
6
5
4
3
2
1
0
TIMER = 2V
TIMER = 2V
V
TMRH
V
TMRL
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
85
105 125
–55 –35 –15
5
25 45 65
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G21
4252-1/2 G19
4252-1/2 G20
425212fb
7
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
I
(Circuit Breaker, Sourcing)
I
(Circuit Breaker, I
= 50µA,
I
(Cooling Cycle, Sinking)
TMR
TMR
DRN
TMR
vs Temperature
Sourcing) vs Temperature
vs Temperature
690
670
650
630
610
590
570
550
280
260
240
220
200
180
10
9
8
7
6
5
4
3
2
1
0
TIMER = 2V
DRN
TIMER = 2V
DRN
TIMER = 2V
I
= 50µA
I
= 0µA
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G32
4252-1/2 G22
4252-1/2 G23
I
vs V
DRAIN
DRN
I
vs I
∆I
/∆I
vs Temperature
TMR
DRN
TMRACC DRN
10
100
9.0
8.8
8.6
8.4
8.2
8.0
7.8
7.6
7.4
7.2
7.0
I
= 2mA
IN
TIMER ON
(CIRCUIT BREAKING,
10
1
I
= 50µA)
DRN
0.1
1
T
= 125°C
A
0.01
T
A
= 85°C
0.001
0.0001
0.00001
T
2
= 25°C
A
T
= –40°C
A
0.1
0
4
6
8
10 12 14 16
(V)
0.001
0.01
0.1
(mA)
1
10
–55 –35 –15
5
25 45 65 85 105 125
I
V
TEMPERATURE (°C)
DRN
DRAIN
4252-1/2 G33
4252-1/2 G25
4252-1/2 G34
V
DRNL
vs Temperature
V
vs Temperature
V
PGL
vs Temperature
DRNCL
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
8.0
7.8
7.6
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
3.0
2.5
2.0
1.5
1.0
0.5
0
I
= 50µA
DRN
(MS ONLY)
FOR PWRGD STATUS (MS ONLY)
I
= 10mA
PG
I
I
= 5mA
PG
= 1.6mA
PG
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4252-1/2 G35
4252-1/2 G36
4252-1/2 G37
425212fb
8
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U W
TYPICAL PERFOR A CE CHARACTERISTICS
t
and t
PHLOG
PLLUG
t
SS
vs Temperature
I
vs Temperature
vs Temperature
PGH
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
62
61
60
59
58
57
56
55
220
210
200
190
180
170
160
150
SS PIN FLOATING,
RAMPS FROM 0.2V TO 2V
V
= 0V
PWRGD
V
(MS ONLY)
SS
t
PLLUG
t
PHLOG
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE °(C)
TEMPERATURE (°C)
4252-1/2 G38
4252-1/2 G24
4252-1/2 G27
U
U
U
PI FU CTIO S
(MS/MS8)
VIN (Pin 1/Pin 1): Positive Supply Input. Connect this pin
to the positive side of the supply through a dropping
resistor. A shunt regulator clamps VIN at 13V. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the VIN pin is greater than VLKO, overriding UV and OV. If
UV is high, OV is low and VIN comes out of UVLO, TIMER
starts an initial timing cycle before initiating a GATE ramp-
up. If VIN drops below approximately 8.2V, GATE pulls low
immediately.
source. The GATE pin is held low until SS exceeds 20 • VOS
= 0.2V. SS is internally shunted by a 100k resistor (RSS)
which limits the SS pin voltage to 2.2V(50k resistor and
1.4V for the LTC4252A). This corresponds to an analog
current limit SENSE voltage of 100mV (60mV for the
LTC4252A). If the SS capacitor is omitted, the SS pin
ramps up in about 180µs. The SS pin is pulled low under
any of the following conditions: in UVLO, in an undervolt-
age condition, in an overvoltage condition, during the
initial timing cycle or when the circuit breaker fault times
out.
PWRGD (Pin 2/Not Available): Power Good Status Out-
put (MS only). At start-up, PWRGD latches low if DRAIN
is below 2.385V and GATE is within 2.8V of VIN. PWRGD
status is reset by UV, VIN (UVLO) or a circuit breaker fault
timeout.Thispinisinternallypulledhighbya58µAcurrent
source.
SENSE (Pin 4/Pin 3): Circuit Breaker/Current Limit Sense
Pin. Load current is monitored by a sense resistor RS
connected between SENSE and VEE, and controlled in
three steps. If SENSE exceeds VCB (50mV), the circuit
breaker comparator activates a (230µA + 8 • IDRN) TIMER
pull-upcurrent.IfSENSEexceedsVACL,theanalogcurrent
limit amplifier pulls GATE down to regulate the MOSFET
current at VACL/RS. In the event of a catastrophic short-
circuit, SENSE may overshoot. If SENSE reaches VFCL
(200mV), thefastcurrentlimitcomparatorpullsGATElow
with a strong pull-down. To disable the circuit breaker and
current limit functions, connect SENSE to VEE.
SS (Pin 3/Pin 2): Soft-Start Pin. This pin is used to ramp
inrush current during start up, thereby effecting control
over di/dt. A 20x attenuated version of the SS pin voltage
is presented to the current limit amplifier. This attenuated
voltage limits the MOSFET’s drain current through the
sense resistor during the soft-start current limiting. At the
beginning of a start-up cycle, the SS capacitor (CSS) is
ramped by a 22µA (28µA for the LTC4252A) current
425212fb
9
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U
U
U
PI FU CTIO S
(MS/MS8)
VEE (Pin 5/Pin 4): Negative Supply Voltage Input. Connect
UV (Pin 9/Pin 7): Undervoltage Input. The active low
threshold at the UV pin is set at 2.925V with 0.3V hyster-
esis. If UV < 2.925V, PWRGD pulls high, both GATE and
TIMER pull low. If UV rises above 3.225V, this initiates an
initial timing cycle followed by GATE start-up. The
LTC4252A UV pin is set at 3.08V with 324mV hysteresis.
If UV < 2.756V, PWRGD pulls high, both GATE and TIMER
pull low. If UV rises above 3.08V, this initiates an initial
timingcyclefollowedbyGATEstart-up. TheinternalUVLO
at VIN always overrides UV. A low at UV resets an internal
fault latch. A 1nF to 10nF capacitor at UV prevents tran-
sients and switching noise from affecting the UV thresh-
olds and prevents glitches at the GATE pin.
this pin to the negative side of the power supply.
GATE (Pin 6/Pin 5): N-Channel MOSFET Gate Drive Out-
put. Thispinispulledhighbya58µAcurrentsource. GATE
is pulled low by invalid conditions at VIN (UVLO), UV, OV,
or a circuit breaker fault timeout. GATE is actively servoed
to control the fault current as measured at SENSE. A
compensation capacitor at GATE stabilizes this loop. A
comparator monitors GATE to ensure that it is low before
allowing an initial timing cycle, GATE ramp-up after an
overvoltage event or restart after a current limit fault.
During GATE start-up, a second comparator detects if
GATE is within 2.8V of VIN before PWRGD is set (MS
package only).
TIMER (Pin 10/Pin 8): Timer Input. TIMER is used to
generate an initial timing delay at start-up and to delay
shutdown in the event of an output overload (circuit
breaker fault). TIMER starts an initial timing cycle when
the following conditions are met: UV is high, OV is low, VIN
DRAIN (Pin 7/Pin 6): Drain Sense Input. Connecting an
external resistor, RD, between this pin and the MOSFET’s
drain (VOUT) allows voltage sensing below 6.15V (5V for
LTC4252A) and current feedback to TIMER. A comparator
detects if DRAIN is below 2.385V and together with the
GATE high comparator sets the PWRGD flag. If VOUT is
clearsUVLO, TIMERpinislow, GATEislowerthanVGATEL
,
SS < 0.2V, and VSENSE – VEE < VCB. A pull-up current of
5.8µA then charges CT, generating a time delay. If CT
chargestoVTMRH (4V),thetimingcycleterminates,TIMER
quickly pulls low and GATE is activated.
above VDRNCL, DRAIN clamps at approximately VDRNCL
.
The current through RD is internally multiplied by 8 and
added to TIMER’s 230µA pullup current during a circuit
breakerfaultcycle.ThisreducesthefaulttimeandMOSFET
heating.
If SENSE exceeds 50mV while GATE is high, a circuit
breaker cycle begins with a 230µA pull-up current charg-
ing CT. If DRAIN is approximately 7V (6V for LTC4252A)
during this cycle, the timer pull-up has an additional
current of 8 • IDRN. If SENSE drops below 50mV before
TIMER reaches 4V, a 5.8µA pull-down current slowly
discharges the CT. In the event that CT eventually inte-
grates up to the VTMRH threshold, the circuit breaker trips,
GATE quickly pulls low and PWRGD pulls high. The
LTC4252-1 TIMER pin latches high with a 5.8µA pull-up
source. This latched fault is cleared by either pulling
TIMER low with an external device or by pulling UV below
VUVLO. The LTC4252-2 starts a shutdown cooling cycle
following an overcurrent fault. This cycle consists of 4
discharging ramps and 3 charging ramps. The charging
and discharging currents are 5.8µA and TIMER ramps
between its 1V and 4V thresholds. At the completion of a
shutdown cooling cycle, the LTC4252-2 attempts a start-
up cycle.
OV(Pin8/Pin7):OvervoltageInput.Theactivehighthresh-
old at the OV pin is set at 6.15V with 0.6V hysteresis. If OV
> 6.15V, GATE pulls low. When OV returns below 5.55V,
GATE start-up begins without an initial timing cycle. The
LTC4252A OV pin is set at 5.09V with 102mV hysteresis.
If OV > 5.09V, GATE pulls low. When OV returns below
4.988V, GATE start-up begins without an initial timing
cycle. If an overvoltage condition occurs in the middle of
an initial timing cycle, the initial timing cycle is restarted
after the overvoltage condition goes away. An overvoltage
condition does not reset the PWRGD flag. The internal
UVLO at VIN always overrides OV. A 1nF to 10nF capacitor
at OV prevents transients and switching noise from affect-
ing the OV thresholds and prevents glitches at the GATE
pin.
425212fb
10
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
W
BLOCK DIAGRA
V
IN
–
+
DRAIN
V
IN
2.385V
6.15V
(5V)
8×
1×
V
EE
V
IN
1×
1×
58µA
V
EE
PWRGD **
GATE
V
IN
6.15V
(5.09V)
–
58µA
V
EE
OV *
UV *
+
–
2.8V
–
V
IN
+
–
V
EE
(+)
+
2.925V
(3.08V)
+
( )
–
V
IN
–
+
LOGIC
V
IN
230µA
5.8µA
4V
–
+
0.5V
TIMER
+
–
–
+
FCL
200mV
+
V
EE
–
V
5.8µA
EE
1V
EE
V
V
IN
22µA
(28µA)
+
SS
V
OS
= 10mV
ACL
95k
(47.5k)
+
–
–
V
EE
R
SS
+
–
V
EE
5k
SENSE
(2.5k)
CB
50mV
V
EE
V
EE
+
–
4252-1/2 BD
V
EE
*OV AND UV ARE TIED TOGETHER ON THE MS8 PACKAGE. OV AND UV ARE SEPARATE PINS ON THE MS PACKAGE
** ONLY AVAILABLE IN THE MS PACKAGE
FOR COMPONENTS, CURRENT AND VOLTAGE WITH TWO VALUES, VALUES IN PARENTHESES REFER
TO THE LTC4252A. VALUES WITHOUT PARENTHESES REFER TO THE LTC4252
425212fb
11
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U
OPERATIO
Hot Circuit Insertion
Interlock Conditions
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient cur-
rents from the power bus as they charge. The flow of
current damages the connector pins and glitches the
power bus, causing other boards in the system to reset.
The LTC4252 is designed to turn on a circuit board supply
in a controlled manner, allowing insertion or removal
without glitches or connector damage.
A start-up sequence commences once these “interlock”
conditions are met.
1. The input voltage VIN exceeds VLKO (UVLO).
2. The voltage at UV > VUVHI
.
3. The voltage at OV < VOVLO
.
4. The (SENSE – VEE) voltage is < 50mV (VCB).
5. The voltage at SS is < 0.2V (20 • VOS).
Initial Start-Up
6. The voltage on the TIMER capacitor (CT) is < 1V (VTMRL).
7. The voltage at GATE is < 0.5V (VGATEL).
The LTC4252 resides on a removable circuit board and
controls the path between the connector and load or
powerconversioncircuitrywithanexternalMOSFETswitch
(see Figure 1). Both inrush control and short-circuit pro-
tection are provided by the MOSFET.
The first three conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
A detailed schematic for the LTC4252A is shown in Fig-
ure 2. –48V and –48RTN receive power through the
longest connector pins and are the first to connect when
the board is inserted. The GATE pin holds the MOSFET off
during this time. UV and OV determine whether or not the
MOSFET should be turned on based upon internal high
accuracythresholdsandanexternaldivider. UVandOVdo
doubledutybyalsomonitoringwhetherornottheconnec-
torisseated.Thetopofthedividerdetects–48RTNbyway
of a short connector pin that is the last to mate during the
insertion sequence.
TIMER begins the start-up sequence by sourcing 5.8µA
intoCT.IfVIN,UVorOVfallsoutofrange,thestart-upcycle
stopsandTIMERdischargesCT tolessthan1V, thenwaits
until the aforementioned conditions are once again met. If
CT successfully charges to 4V, TIMER pulls low and both
SS and GATE pins are released. GATE sources 58µA
(IGATE), chargingtheMOSFETgateandassociatedcapaci-
tance. The SS voltage ramp limits VSENSE to control the
inrush current. PWRGD pulls active low when GATE is
within 2.8V of VIN and DRAIN is lower than VDRNL
.
LONG
PLUG-IN BOARD
LONG
–48RTN
R
IN
+
–48RTN
+
+
3 × 1.8k IN SERIES
C
LOAD
1/4W EACH
100µF
ISOLATED
DC/DC
LTC4252
+
LOW
VOLTAGE
CIRCUITRY
R1
390k
1%
C
LOAD
SHORT
C
IN
1µF
CONVERTER
MODULE
V
OV
UV
IN
LONG
–48V
–
–
LTC4252A-1
TIMER
SS
BACKPLANE
C1
10nF
4252-1/2 F01
DRAIN
SENSE GATE
V
EE
Figure 1. Basic LTC4252 Hot Swap Topology
C
SS
68nF
R2
30.1k
1%
R
D
1M
R
C
C
C
T
0.68µF
C
10Ω
10nF
LONG
–48V
4252-1/2 F02
R
S
0.02Ω
Q1
IRF530S
Figure 2. –48V, 2.5A Hot Swap Controller
425212fb
12
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U
OPERATIO
Two modes of operation are possible during the time the
MOSFET is first turning on, depending on the values of
external components, MOSFET characteristics and nomi-
nal design current. One possibility is that the MOSFET will
turn on gradually so that the inrush into the load capaci-
tance remains a low value. The output will simply ramp to
–48V and the LTC4252 will fully enhance the MOSFET. A
secondpossibilityisthattheloadcurrentexceedsthesoft-
startcurrentlimitthresholdof[VSS(t)/20–VOS]/RS.Inthis
case the LTC4252 will ramp the output by sourcing soft-
start limited current into the load capacitance. If the soft-
start voltage is below 1.2V, the circuit breaker TIMER is
held low. Above 1.2V, TIMER ramps up. It is important to
set the timer delay so that, regardless of which start-up
mode is used, the TIMER ramp is less than one circuit
breaker delay time. If this condition is not met, the
LTC4252-1 may shut down after one circuit breaker delay
time whereas the LTC4252-2 may continue to autoretry.
Higher overloads are handled by an analog current limit
loop. If the drop across RS reaches VACL, the current
limiting loop servos the MOSFET gate and maintains a
constant output current of VACL/RS. In current limit
mode, VOUT typically rises and this increases MOSFET
heating. If VOUT > VDRNCL, connecting an external resis-
tor, RD, between VOUT and DRAIN allows the fault timing
cycle to be shortened by accelerating the charging of the
TIMERcapacitor. TheTIMERpull-upcurrentisincreased
by 8 • IDRN. Note that because SENSE > 50mV, TIMER
charges CT during this time and the LTC4252 will even-
tually shut down.
Low impedance failures on the load side of the LTC4252
coupled with 48V or more driving potential can produce
current slew rates well in excess of 50A/µs. Under these
conditions, overshoot is inevitable. A fast SENSE com-
parator with a threshold of 200mV detects overshoot and
pulls GATE low much harder and hence much faster than
the weaker current limit loop. The VACL/RS current limit
loop then takes over and servos the current as previously
described. As before, TIMER runs and shuts down the
LTC4252 when CT reaches 4V.
Board Removal
If the board is withdrawn from the card cage, the UV and
OV divider is the first to lose connection. This shuts off the
MOSFET and commutates the flow of current in the
connector. When the power pins subsequently separate,
there is no arcing.
If CT reaches 4V, the LTC4252-1 latches off with a 5.8µA
pull-up current source whereas the LTC4252-2 starts a
shutdown cooling cycle. The LTC4252-1 circuit breaker
latchisresetbyeitherpullingUVmomentarilylowordrop-
ping the input voltage VIN below the internal UVLO thresh-
old or pulling TIMER momentarily low with a switch. The
LTC4252-2 retries after its shutdown cooling cycle.
Current Control
Three levels of protection handle short-circuit and over-
load conditions. Load current is monitored by SENSE and
resistor RS. There are three distinct thresholds at SENSE:
50mV for a timed circuit breaker function; 100mV for an
analog current limit loop (60mV for the LTC4252A); and
200mV for a fast, feedforward comparator which limits
peak current in the event of a catastrophic short-circuit.
Although short-circuits are the most obvious fault type,
several operating conditions may invoke overcurrent
protection. Noisespikesfromthebackplaneorload, input
steps caused by the connection of a second, higher
voltage supply, transient currents caused by faults on
adjacentcircuitboardssharingthesamepowerbusorthe
insertion of non-hot-swappable products could cause
higher than anticipated input current and temporary de-
tection of an overcurrent condition. The action of TIMER
and CT rejects these events allowing the LTC4252 to “ride
out” temporary overloads and disturbances that could
tripasimplecurrentcomparatorand,insomecases,blow
a fuse.
If, owingtoanoutputoverload, thevoltagedropacrossRS
exceeds 50mV, TIMER sources 230µA into CT. CT eventu-
ally charges to a 4V threshold and the LTC4252 shuts off.
IftheoverloadgoesawaybeforeCT reaches4VandSENSE
measures less than 50mV, CT slowly discharges (5.8µA).
In this way the LTC4252’s circuit breaker function re-
sponds to low duty cycle overloads and accounts for fast
heating and slow cooling characteristics of the MOSFET.
425212fb
13
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U
W
U U
APPLICATIO S I FOR ATIO
SHUNT REGULATOR
UV/OV COMPARATORS (LTC4252)
A fast responding regulator shunts the LTC4252 VIN pin.
Power is derived from –48RTN by an external current
limiting resistor. The shunt regulator clamps VIN to 13V
(VZ). A 1µF decoupling capacitor at VIN filters supply
transients and contributes a short delay at start-up. RIN
should be chosen to accommodate both VIN supply cur-
rent and the drive required for an optocoupler if the
PWRGD function on the 10-pin MS package is used.
Higher current through RIN results in higher dissipation
for RIN and the LTC4252. An alternative is a separate NPN
buffer driving the optocoupler as shown in Figure 3.
Multiple 1/4W resistors can replace a single higher power
RIN resistor.
An UV hysteretic comparator detects undervoltage condi-
tions at the UV pin, with the following thresholds:
UV low-to-high (VUVHI) = 3.225V
UV high-to-low (VUVLO) = 2.925V
An OV hysteretic comparator detects overvoltage condi-
tions at the OV pin, with the following thresholds:
OV low-to-high (VOVHI) = 6.150V
OV high-to-low (VOVLO) = 5.550V
The UV and OV trip point ratio is designed to match the
standard telecom operating range of 43V to 82V when
connected together as in the typical application. A divider
(R1, R2) is used to scale the supply voltage. Using R1 =
402k and R2 = 32.4k gives a typical operating range of
43.2V to 82.5V. The undervoltage shutdown and overvolt-
age recovery thresholds are then 39.2V and 74.4V. 1%
divider resistors are recommended to preserve threshold
accuracy.
INTERNAL UNDERVOLTAGE LOCKOUT (UVLO)
A hysteretic comparator, UVLO, monitors VIN for
undervoltage. The thresholds are defined by VLKO and its
hysteresis, VLKH. When VIN rises above VLKO the chip is
enabled; below (VLKO – VLKH) it is disabled and GATE is
pulled low. The UVLO function at VIN should not be
confused with the UV/OV pin(s). These are completely
separate functions.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100µA and
define an impedance at UV/OV of 30kΩ. In most applica-
GND
R
IN
+
10k
C
R4
22k
L
1/2W
100µF
Q2
C
IN
LOAD
EN
R5
2.2k
GND
1
1µF
(SHORT PIN)
R1
V
IN
432k
1%
LTC4252-1
PWRGD
*
9
8
2
7
6
4
UV
R
D
1M
R2
4.75k
1%
OV
DRAIN
GATE
10
3
Q1
IRF530S
TIMER
SS
R3
38.3k
1%
C
T
SENSE
V
EE
330nF
R
R
S
0.02Ω
C
5
C2
10nF
C
10Ω
C
SS
68nF
C
18nF
4252-1/2 F03
–48V
* M0C207
Q2: MMBT5551LT1
Figure 3. –48V/2.5A Application with Different Input Operating Range
425212fb
14
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U
W U U
APPLICATIO S I FOR ATIO
tions, 30kΩ impedance coupled with 300mV UV hyster-
esismakestheLTC4252insensitivetonoise.Ifmorenoise
immunityisdesired,adda1nFto10nFfiltercapacitorfrom
UV/OV to VEE.
gives a typical operating range of 43V to 71V. The under-
voltageshutdown andovervoltagerecoverythresholdsare
then38.5Vand69.6Vrespectively.1%dividerresistorsare
recommended to preserve threshold accuracy.
Separate UV and OV pins are available in the 10-pin MS
package and can be used for a different operating range
such as 35.5V to 76V as shown in Figure 3. Other combi-
nations are possible with different resistor arrangements.
The R1-R2 divider values shown in Figure 2 set a standing
current of slightly more than 100µA and define an imped-
ance at UV/OV of 28kΩ. In most applications, 28kΩ
impedance coupled with 324mV UV hysteresis makes the
LTC4252A insensitive to noise. If more noise immunity is
desired, add a 1nF to 10nF filter capacitor from UV/OV to
VEE.
UV/OV COMPARATORS (LTC4252A)
A UV hysteretic comparator detects undervoltage condi-
tions at the UV pin, with the following thresholds:
The UV and OV pins can be used for a wider operating
range such as 35.5V to 76V as shown in Figure 4. Other
combinations are possible with different resistor
arrangements.
UV low-to-high (VUV) = 3.08V
UV high-to-low (VUV – VUVHST) = 2.756V
An OV hysteretic comparator detects overvoltage condi-
tions at the OV pin, with the following thresholds:
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the other
interlock conditions are met. A high-to-low transition in
theUVcomparatorimmediatelyshutsdowntheLTC4252,
pulls the MOSFET gate low and resets the latched PWRGD
high.
OV low-to-high (VOV) = 5.09V
OV high-to-low (VOV – VOVHST) = 4.988V
The UV and OV trip point ratio is designed to match the
standard telecom operating range of 43V to 71V when
connectedtogetherasinFigure2.Adivider(R1,R2)isused
toscalethesupplyvoltage.UsingR1=390kandR2=30.1k
GND
R
IN
+
10k
C
R4
22k
L
1/2W
100µF
Q2
C
IN
1µF
LOAD
EN
R5
2.2k
GND
1
(SHORT PIN)
R1
V
IN
LTC4252A-1
PWRGD
464k
1%
*
9
8
2
7
6
4
UV
R
D
1M
R2
10k
1%
OV
DRAIN
GATE
10
3
Q1
IRF530S
TIMER
SS
R3
34k
1%
C
T
SENSE
V
EE
0.68µF
R
R
S
0.02Ω
C
5
C2
10nF
C
10Ω
SS
68nF
C
C
10nF
4252-1/2 F04
–48V
* M0C207
Q2: MMBT5551LT1
Figure 4. –48V/2.5A Application with Wider Input Operating Range
425212fb
15
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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APPLICATIO S I FOR ATIO
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load.
However, it will not reset the circuit breaker TIMER,
PWRGD flag or shutdown cooling timer. Returning the
supply voltage to an acceptable range restarts the GATE
pin if all the interlock conditions except TIMER are met.
Only during the initial timing cycle does an OV condition
reset the TIMER.
4) Low impedance switch; resets the TIMER capacitor
after an initial timing delay, in UVLO, in UV and in OV
during initial timing.
For initial start-up, the 5.8µA pull-up is used. The low
impedance switch is turned off and the 5.8µA current
source is enabled when the interlock conditions are met.
CT charges to 4V in a time period given by:
4V •CT
5.8µA
t =
(2)
DRAIN
Connecting an external resistor, RD, to the dual function
DRAINpinallowsVOUT sensing*withoutitbeingdamaged
by large voltage transients. Below 5V, negligible pin leak-
age allows a DRAIN low comparator to detect VOUT less
than 2.385V (VDRNL). This condition, together with the
GATE low comparator, sets the PWRGD flag.
When CT reaches 4V (VTMRH), the low impedance switch
turns on and discharges CT. A GATE start-up cycle begins
and both SS and GATE are released.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than a 50mV drop across
RS, the TIMER pin charges CT with (230µA + 8 • IDRN). If
CTchargesto4V,theGATEpinpullslowandtheLTC4252-1
latchesoffwhiletheLTC4252-2startsashutdowncooling
cycle. The LTC4252-1 remains latched off until the UV pin
is momentarily pulsed low or TIMER is momentarily
discharged low by an external switch or VIN dips below
UVLO and is then restored. The circuit breaker timeout
period is given by:
If VOUT > VDRNCL, the DRAIN pin is clamped at about
VDRNCL and the current flowing in RD is given by:
VOUT − VDRNCL
IDRN
≈
(1)
RD
This current is scaled up 8 times during a circuit breaker
fault and is added to the nominal 230µA TIMER current.
ThisacceleratesthefaultTIMERpull-upwhentheMOSFET’s
drain-sourcevoltageexceedsVDRNCLandeffectivelyshort-
ens the MOSFET heating duration.
4V •CT
230µA + 8•IDRN
t =
(3)
TIMER
If VOUT < 5V, an internal PMOS device isolates any DRAIN
pin leakage current, making IDRN = 0µA in Equation (3). If
VOUT > VDRNCLduring the circuit breaker fault period, the
charging of CT accelerates by 8 • IDRN of Equation (1).
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor CT is used at
TIMER to provide timing for the LTC4252. Four different
charging and discharging modes are available at TIMER:
Intermittent overloads may exceed the 50mV threshold at
SENSE, but, if their duration is sufficiently short, TIMER
willnotreach4VandtheLTC4252willnotshuttheexternal
MOSFET off. To handle this situation, the TIMER dis-
charges CT slowly with a 5.8µA pull-down whenever the
SENSE voltage is less than 50mV. Therefore, any intermit-
tent overload with VOUT > 5V and an aggregate duty cycle
1) A 5.8µA slow charge; initial timing and shutdown
cooling delay.
2) A (230µA + 8 • IDRN) fast charge; circuit breaker delay.
3) A 5.8µA slow discharge; circuit breaker "cool off" and
shutdown cooling.
*VOUT as viewed by the MOSFET; i.e., VDS
.
425212fb
16
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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APPLICATIO S I FOR ATIO
10
SOFT-START
I
= 0µA
DRN
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFET’s SOA rating if powering up into an active load. If
SS floats, an internal current source ramps SS from 0V to
2.2V for the LTC4252 or 0V to 1.4V for the LTC4252A in
about 230µs. Connecting an external capacitor CSS from
SS to ground modifies the ramp to approximate an RC
response of:
1
0.1
t
4
=
C (µF)
[(235.8 + 8 • I
) • D – 5.8]
DRN
T
0.01
0
20
40
60
80
100
FAULT DUTY CYCLE (%)
⎛
⎞
t
⎛
⎞
⎟
⎟
⎠
−
4252-1/2 F05
⎜
⎝
⎟
⎠
R
•C
SS SS
⎜
VSS(t) ≈ VSS • 1− e
⎜
⎝
(6)
Figure 5. Circuit-Breaker Response Time
of 2.5% or more will eventually trip the circuit breaker and
shutdowntheLTC4252.Figure5showsthecircuitbreaker
An internal resistive divider (95k/5k for the LTC4252 or
47.5k/2.5k for the LTC4252A) scales VSS(t) down by 20
times to give the analog current limit threshold:
response time in seconds normalized to 1µF for IDRN
=
0µA. The asymmetric charging and discharging of CT is a
fair gauge of MOSFET heating.
VSS(t)
VACL(t) =
− VOS
(7)
20
The normalized circuit response time is estimated by
This allows the inrush current to be limited to VACL(t)/RS.
Theoffsetvoltage, VOS (10mV), ensuresCSS issufficiently
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
t
4
=
(4)
CT (µF)
235.8 + 8•I
•D − 5.8
(
)
[
]
DRN
SHUTDOWN COOLING CYCLE
For the LTC4252-1 (latchoff version), TIMER latches high
with a 5.8µA pull-up after the circuit breaker fault TIMER
reaches 4V. For the LTC4252-2 (automatic retry version),
a shutdown cooling cycle begins if TIMER reaches the 4V
threshold. TIMER starts with a 5.8µA pull-down until it
reaches the 1V threshold. Then, the 5.8µA pull-up turns
back on until TIMER reaches the 4V threshold. Four 5.8µA
pull-down cycles and three 5.8µA pull-up cycles occur
between the 1V and 4V thresholds, creating a time interval
given by:
GATE
GATE is pulled low to VEE under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out. When GATE turns
on, a 58µA current source charges the MOSFET gate and
any associated external capacitance. VIN limits the gate
drive to no more than 14.5V.
7 •3V •CT
Gate-drain capacitance (CGD) feedthrough at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at VIN
tSHUTDOWN
=
(5)
5.8µA
At the 1V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
425212fb
17
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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APPLICATIO S I FOR ATIO
and eliminates current spikes at insertion. A large external
gate-sourcecapacitoristhusunnecessaryforthepurpose
of compensating CGD. Instead, a smaller value (≥ 10nF)
capacitor CC is adequate. CC also provides compensation
for the analog current limit loop.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load side low impedance
short is shown in Figure 6 for the LTC4252. Initially, the
current overshoots the fast current limit level of VSENSE
200mV(Trace2)astheGATEpinworkstobringVGS under
control (Trace 3). The overshoot glitches the backplane in
the negative direction and when the current is reduced to
100mV/RS, the backplane responds by glitching in the
positive direction.
=
GATE has two comparators: the GATE low comparator
looks for < 0.5V threshold prior to initial timing or a GATE
start-up cycle; the GATE high comparator looks for < 2.8V
relative to VIN and, together with the DRAIN low compara-
tor, sets PWRGD status during GATE startup.
TIMERcommenceschargingCT (Trace4)whiletheanalog
currentlimitloopmaintainsthefaultcurrentat100mV/RS,
which in this case is 5A (Trace 2). Note that the backplane
voltage (Trace 1) sags under load. Timer pull-up is accel-
erated by VOUT. When CT reaches 4V, GATE turns off,
PWRGD pulls high, the load current drops to zero and the
backplane rings up to over 100V. The transient associated
with the GATE turn off can be controlled with a snubber to
reduce ringing and a transient voltage suppressor (such
asDiodesInc.SMAT70A)toclipofflargespikes.Thechoice
of RC for the snubber is usually done experimentally. The
value of the snubber capacitor is usually chosen between
10 to 100 times the MOSFET COSS. The value of the snub-
ber resistor is typically between 3Ω to 100Ω.
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier and
thefastcurrentlimit(FCL)comparator.Eachofthesethree
measures the potential of SENSE relative to VEE. When
SENSE exceeds 50mV, the CB comparator activates the
230µATIMERpull-up.At100mV(60mVfortheLTC4252A),
the ACL amplifier servos the MOSFET current and, at
200mV, the FCL comparator abruptly pulls GATE low in an
attempt to bring the MOSFET current under control. If any
of these conditions persists long enough for TIMER to
charge CT to 4V (see Equation 3), the LTC4252 shuts
down and pulls GATE low.
SUPPLY RING OWING TO
CURRENT OVERSHOOT
SUPPLY RING OWING TO
MOSFET TURN OFF
If the SENSE pin encounters a voltage greater than VACL
,
the ACL amplifier will servo GATE downwards in an
attempt to control the MOSFET current. Since GATE over-
drives the MOSFET in normal operation, the ACL amplifier
needs time to discharge GATE to the threshold of the
MOSFET.ForamildoverloadtheACLamplifiercancontrol
the MOSFET current, but in the event of a severe overload
the current may overshoot. At SENSE = 200mV the FCL
comparator takes over, quickly discharging the GATE pin
to near VEE potential. FCL then releases and the ACL
amplifier takes over. All the while TIMER is running. The
effect of FCL is to add a nonlinear response to the control
loop in favor of reducing MOSFET current.
–48RTN
50V/DIV
ONSET OF OUTPUT SHORT-CIRCUIT
FAST CURRENT LIMIT
SENSE
200mV/DIV
GATE
10V/DIV
ANALOG CURRENT LIMIT
TIMER
5V/DIV
LATCH OFF
C
RAMP
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop and GATE under-
shoots. A zero in the loop (resistor RC in series with the
gate capacitor) helps the ACL amplifier to recover.
TIMER
4252-1/2 F06
0.5ms/DIV
Figure 6. Output Short-Circuit Behavior of LTC4252
425212fb
18
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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A low impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 6 Trace 1, can
rob charge from output capacitors on adjacent cards.
When the faulty card shuts down, current flows in to
refresh the capacitors. If LTC4252s are used by the other
cards, they respond by limiting the inrush current to a
value of 100mV/RS. If CT is sized correctly, the capacitors
will recharge long before CT times out.
To begin a design, first specify the required load current
and Ioad capacitance, IL and CL. The circuit breaker
current trip point (VCB/RS) should be set to accommodate
the maximum load current. Note that maximum input
current to a DC/DC converter is expected at VSUPPLY(MIN)
RS is given by:
.
VCB(MIN)
IL(MAX)
RS =
(8)
where VCB(MIN) = 40mV (45mV for LTC4252A) represents
the guaranteed minimum circuit breaker threshold.
POWER GOOD, PWRGD
PWRGD latches low if GATE charges up to within 2.8V of
VIN andDRAINpullsbelowVDRNL duringstart-up.PWRGD
is reset in UVLO, in a UV condition or if CT charges up to
4V. An overvoltage condition has no effect on PWRGD
status. A58µAcurrentpullsthispinhighduringreset. Due
to voltage transients between the power module and
PWRGD, optoisolation is recommended. This pin pro-
vides sufficent drive for an optocoupler. Figure 19 shows
an alternative NPN configuration with a limiting base
resistor for the PWRGD interface. The module enable
input should have protection from the negative input
current.
During the initial charging process, the LTC4252 may
operate the MOSFET in current limit, forcing (VACL) be-
tween 80mV to 120mV (VACL is 54mV to 66mV for
LTC4252A) across RS. The minimum inrush current is
given by:
80mV
RS
IINRUSH(MIN)
=
(9)
Maximum short-circuit current limit is calculated using
the maximum VACL. This gives
120mV
ISHORTCIRCUIT(MAX)
=
(10)
RS
MOSFET SELECTION
The TIMER capacitor CT must be selected based on the
slowest expected charging rate; otherwise TIMER might
time out before the load capacitor is fully charged. A value
forCT iscalculatedbasedonthemaximumtimeittakesthe
load capacitor to charge. That time is given by:
The external MOSFET switch must have adequate safe
operating area (SOA) to handle short-circuit conditions
until TIMER times out. These considerations take prece-
dence over DC current ratings. A MOSFET with adequate
SOAforagivenapplicationcanalwayshandletherequired
current, but the opposite may not be true. Consult the
manufacturer’sMOSFETdatasheetforsafeoperatingarea
and effective transient thermal impedance curves.
C L•VSUPPLY(MAX)
C •V
I
tCL(CHARGE)
=
=
(11)
IINRUSH(MIN)
The maximum current flowing in the DRAIN pin is given
by:
MOSFET selection is a 3-step process by assuming the
absenseofasoft-startcapacitor.First,RS iscalculatedand
thenthetimerequiredtochargetheloadcapacitanceisde-
termined. This timing, along with the maximum short-cir-
cuit current and maximum input voltage defines an oper-
atingpointthatischeckedagainsttheMOSFET’sSOAcurve.
VSUPPLY(MAX)− VDRNCL
IDRN(MAX)
=
(12)
RD
425212fb
19
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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APPLICATIO S I FOR ATIO
Approximating a linear charging rate as IDRN drops from
IDRN(MAX) to zero, the IDRN component in Equation (3) can
be approximated with 0.5 • IDRN(MAX). Rearranging equa-
tion, TIMER capacitor CT is given by:
was appropriate. The ratio (RSS • CSS) to tCL(CHARGE) is a
good gauge as a large ratio may result in the time-out
period expiring. This gauge is determined empirically with
board level evaluation.
tCL(CHARGE) • 230µA + 4 •I
(
)
SUMMARY OF DESIGN FLOW
DRN(MAX)
CT =
(13)
4V
To summarize the design flow, consider the application
shown in Figure 2 with the LTC4252A. It was designed for
80W.
Returning to Equation (3), the TIMER period is calculated
and used in conjunction with VSUPPLY(MAX) and
ISHORTCIRCUIT(MAX) to check the SOA curves of a prospec-
tive MOSFET.
Calculate the maximum load current: 80W/43V = 1.86A;
allowing for 83% converter efficiency, IIN(MAX) = 2.2A.
As a numerical design example, consider a 30W load,
Calculate RS: from Equation (8) RS = 20mΩ.
which requires 1A input current at 36V. If VSUPPLY(MAX)
=
Calculate ISHORTCIRCUIT(MAX): from Equation (10)
72V and CL = 100µF, RD = 1MΩ, Equation (8) gives RS =
40mΩ; Equation (13) gives CT = 441nF. To account for
errorsinRS, CT, TIMERcurrent(230µA), TIMERthreshold
(4V), RD, DRAIN current multiplier and DRAIN voltage
clamp (VDRNCL), the calculated value should be multiplied
by 1.5, giving the nearest standard value of CT = 680nF.
66mV
20mΩ
ISHORTCIRCUIT(MAX)
=
= 3.3A
Select a MOSFET that can handle 3.3A at 71V: IRF530S.
Calculate CT: from Equation (13) CT = 322nF. Select
CT = 680nF, which gives the circuit breaker time-out pe-
riod t = 5.6ms.
If a short-circuit occurs, a current of up to 120mV/
40mΩ = 3A will flow in the MOSFET for 5.6ms as dictated
by CT = 680nF in Equation (3). The MOSFET must be
selected based on this criterion. The IRF530S can handle
100Vand3Afor10msandissafetouseinthisapplication.
Consult MOSFET SOA curves: the IRF530S can handle
3.3A at 100V for 8.2ms, so it is safe to use in this
application.
Computingthemaximumsoft-startcapacitorvalueduring
soft-start to a load short is complicated by the nonlinear
MOSFET’s SOA characteristics and the RSSCSS response.
An overly conservative but simple approach begins with
the maximum circuit breaker current, given by:
Calculate CSS: using Equations (14) and (15) select
CSS = 68nF.
FREQUENCY COMPENSATION
The LTC4252A typical frequency compensation network
for the analog current limit loop is a series RC (10Ω) and
CC connected to VEE. Figure 7 depicts the relationship
betweenthecompensationcapacitorCC andtheMOSFET’s
CISS. The line in Figure 7 is used to select a starting value
for CC based upon the MOSFET’s CISS specification. Opti-
mized values for CC are shown for several popular
MOSFETs. Differences in the optimized value of CC versus
the starting value are small. Nevertheless, compensation
values should be verified by board level short-circuit
testing.
VCB(MAX)
ICB(MAX)
=
(14)
RS
where VCB(MAX) = 60mV (55mV for the LTC4252A).
FromtheSOAcurvesofaprospectiveMOSFET, determine
the time allowed, tSOA(MAX). CSS is given by:
tSOA(MAX)
CSS
=
(15)
0.916•RSS
In the above example, 60mV/40mΩ gives 1.5A. tSOA(MAX)
for the IRF530S is 40ms. From Equation (15), CSS
437nF. Actual board evaluation showed that CSS = 100nF
=
425212fb
20
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
60
NTY100N10
50
40
30
SENSE RESISTOR
TRACK WIDTH W:
W
0.03" PER AMP
ON 1 OZ COPPER
IRF3710
IRF540S
20
10
0
4252-1/2 F08
IRF530S
IRF740
TO
SENSE
TO
EE
V
0
2000
4000
6000
8000
MOSFET C (pF)
ISS
4252-1/2 F07
Figure 8. Making PCB Connections to the Sense Resistor
Figure 7. Recommended Compensation
Capacitor C vs MOSFET C
C
ISS
time point 1, the supply ramps up, together with UV/OV,
As seen in Figure 6 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramati-
callyowingtoseriesinductance. Ifthisvoltageavalanches
theMOSFET,currentcontinuestoflowthroughtheMOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
V
OUT and DRAIN. VIN and PWRGD follow at a slower rate
as set by the VIN bypass capacitor. At time point 2, VIN
exceeds VLKO and the internal logic checks for UV > VUVHI
,
OV < VOVLO, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS
and TIMER < VTMRL. If all conditions are met, an initial
timing cycle starts and the TIMER capacitor is charged by
a 5.8µA current source pull-up. At time point 3, TIMER
reaches the VTMRH threshold and the initial timing cycle
terminates. The TIMER capacitor is quickly discharged. At
time point 4, the VTMRL threshold is reached and the
conditions of GATE < VGATEL, SENSE < VCB and
SS < 20 • VOS must be satisfied before a GATE ramp-up
cycle begins. SS ramps up as dictated by RSS • CSS (as in
Equation 6); GATE is held low by the analog current limit
(ACL) amplifier until SS crosses 20 • VOS. Upon releasing
GATE, 58µA sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connectionsbetweenthesenseresistorandtheLTC4252’s
VEE and SENSE pins are strongly recommended. The
drawing in Figure 8 illustrates the correct way of making
connections between the LTC4252 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
TIMING WAVEFORMS
System Power-Up
V
ACL(t) (Equation 7) and soft-start limits the slew rate of
the load current. If the SENSE voltage (VSENSE – VEE)
reaches the VCB threshold at time point 7, the circuit
breaker TIMER activates. The TIMER capacitor, CT, is
chargedbya(230µA+8•IDRN)currentpull-up.Astheload
capacitor nears full charge, load current begins to decline.
Figure 9 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
425212fb
21
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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APPLICATIO S I FOR ATIO
V
CLEARS V , CHECK UV > V
, OV < V
, GATE < V
, SENSE < V , SS < 20 • V AND TIMER < V
IN
LKO
UVHI
OVLO
GATEL
CB
OS
TMRL
TIMER CLEARS V
, CHECK GATE < V
, SENSE < V AND SS < 20 • V
CB OS
TMRL
GATEL
1
2
3 4 56
7
8 9 10 11
GND – V OR
EE
(–48RTN) – (–48V)
UV/OV
V
V
LKO
IN
V
TMRH
230µA + 8 • I
DRN
5.8µA
TIMER
5.8µA
5.8µA
V
TMRL
58µA
V
– V
GATEH
IN
GATE
SS
58µA
V
GATEL
20 • (V
20 • (V + V
+ V
)
)
ACL
OS
CB
OS
OS
20 • V
V
V
ACL
SENSE
CB
V
OUT
V
V
DRNCL
DRNL
DRAIN
PWRGD
4252-1/2 F09
GATE
START-UP
INITIAL TIMING
Figure 9. System Power-Up Timing (All Waveforms are Referenced to V )
EE
At time point 8, the load current falls and the SENSE
voltage drops below VACL(t). The analog current limit loop
shuts off and the GATE pin ramps further. At time point 9,
the SENSE voltage drops below VCB, the fault TIMER cycle
ends, followed by a 5.8µA discharge cycle (cool off). The
durationbetweentimepoints7and9mustbeshorterthan
one circuit breaker delay to avoid a fault time out during
GATEramp-up.WhenGATErampspasttheVGATEH thresh-
old at time point 10, PWRGD pulls low. At time point 11,
GATE reaches its maximum voltage as determined by VIN.
makescontactthroughashortpin.Thisensuresthepower
connections are firmly established before the LTC4252 is
activated.Attimepoint1,thepowerpinsmakecontactand
VIN rampsthroughVLKO.Attimepoint2,theUV/OVdivider
makes contact and its voltage exceeds VUVHI. In addition,
the internal logic checks for OV < VOVHI, GATE < VGATEL
,
SENSE < VCB, SS < 20 • VOS and TIMER < VTMRL. If all
conditions are met, an initial timing cycle starts and the
TIMER capacitor is charged by a 5.8µA current source
pull-up. At time point 3, TIMER reaches the VTMRH thresh-
old and the initial timing cycle terminates. The TIMER
capacitor is quickly discharged. At time point 4, the VTMRL
Live Insertion with Short Pin Control of UV/OV
threshold is reached and the conditions of GATE < VGATEL
,
In the example shown in Figure 10, power is delivered
through long connector pins whereas the UV/OV divider
SENSE < VCB and SS < 20 • VOS must be satisfied before
425212fb
22
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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APPLICATIO S I FOR ATIO
UV CLEARS V
, CHECK OV < V
, GATE < V
, SENSE < V , SS < 20 • V AND TIMER < V
UVHI
OVHI
GATEL
CB
OS
TMRL
TIMER CLEARS V
, CHECK GATE < V
, SENSE < V AND SS < 20 • V
CB OS
TMRL
GATEL
1
2
3 4 56
7
8 9 1011
GND – V OR
EE
(–48RTN) – (–48V)
V
UVHI
V
UV/OV
V
IN
LKO
V
TMRH
230µA + 8 • I
DRN
5.8µA
TIMER
GATE
5.8µA
V
5.8µA
TMRL
58µA
V
– V
GATEH
IN
58µA
V
GATEL
20 • (V
20 • (V + V
+ V
)
)
ACL
OS
SS
CB
OS
OS
20 • V
V
V
ACL
CB
SENSE
V
OUT
V
V
DRNCL
DRNL
DRAIN
PWRGD
GATE
START-UP
4252-1/2 F10
INITIAL TIMING
Figure 10. Power-Up Timing with a Short Pin (All Waveforms are Referenced to V )
EE
a GATE start-up cycle begins. SS ramps up as dictated by
RSS • CSS; GATE is held low by the analog current limit
amplifier until SS crosses 20 • VOS. Upon releasing GATE,
58µA sources into the external MOSFET gate and compen-
sation network. When the GATE voltage reaches the
MOSFET’s threshold, current begins flowing into the load
capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
VACL(t) and soft-start limits the slew rate of the load
current. If the SENSE voltage (VSENSE – VEE) reaches the
VCB threshold at time point 7, the circuit breaker TIMER
activates.TheTIMERcapacitor,CT,ischargedbya(230µA
+ 8 • IDRN) current pull-up. As the load capacitor nears full
charge, load current begins to decline. At point 8, the load
current falls and the SENSE voltage drops below VACL(t).
The analog current limit loop shuts off and the GATE pin
ramps further. At time point 9, the SENSE voltage drops
below VCB and the fault TIMER cycle ends, followed by a
5.8µA discharge cycle (cool off). When GATE ramps past
VGATEH threshold at time point 10, PWRGD pulls low. At
time point 11, GATE reaches its maximum voltage as
determined by VIN.
425212fb
23
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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APPLICATIO S I FOR ATIO
Undervoltage Timing
starts. If the system bus voltage overshoots VOVHI as
shown at time point 2, TIMER discharges. At time point 3,
the supply voltage recovers and drops below the VOVLO
threshold. The initial timing cycle restarts, followed by a
GATE start-up cycle.
InFigure11whenUVpindropsbelowVUVLO(timepoint 1),
the LTC4252 shuts down with TIMER, SS and GATE all
pulling low. If current has been flowing, the SENSE pin
voltage decreases to zero as GATE collapses. When UV
recovers and clears VUVHI (time point 2), an initial timer
cycle begins followed by a GATE start-up cycle.
Overvoltage Timing
During normal operation, if the OV pin exceeds VOVHI as
shownattimepoint1ofFigure13, theTIMERandPWRGD
status are unaffected. Nevertheless, SS and GATE pull
down and the load is disconnected. At time point 2, OV
recovers and drops below the VOVLO threshold. A GATE
start-up cycle begins. If the overvoltage glitch is long
enough to deplete the load capacitor, a full start-up cycle
as shown between time points 4 through 7 may occur.
VIN Undervoltage Lockout Timing
The VIN undervoltage lockout comparator, UVLO, has a
similartimingbehaviorastheUVpintimingexceptitlooks
for VIN < (VLKO – VLKH) to shut down and VIN > VLKO to
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When VIN exits undervoltage
lockout, the UV and OV comparators are enabled.
Circuit Breaker Timing
Undervoltage Timing with Overvoltage Glitch
In Figure 14a, the TIMER capacitor charges at 230µA if the
SENSE pin exceeds VCB but VDRN is less than 5V. If the
SENSE pin drops below VCB before TIMER reaches the
In Figure 12, both UV and OV pins are connected together.
WhenUVclearsVUVHI (timepoint1), aninitialtimingcycle
UV DROPS BELOW V
. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
UVLO
UV CLEARS V
, CHECK OV CONDITION, GATE < V
UVHI
, SENSE < V , SS < 20 • V AND TIMER < V
GATEL
CB
OS
TMRL
TIMER CLEARS V
, CHECK GATE < V
TMRL
, SENSE < V AND SS < 20 • V
GATEL CB OS
1
2
3 4 56
7
8 910 11
V
UVHI
UVLO
UV
V
V
TMRH
230µA + 8 • I
DRN
5.8µA
TIMER
5.8µA
V
TMRL
5.8µA
58µA
V
IN
– V
GATEH
GATE
58µA
V
GATEL
20 • (V
20 • (V + V
+ V
)
)
ACL
OS
CB
OS
OS
SS
20 • V
V
V
ACL
SENSE
CB
V
V
DRNCL
DRAIN
DRNL
PWRGD
GATE
START-UP
4252-1/2 F11
INITIAL TIMING
Figure 11. Undervoltage Timing (All Waveforms are Referenced to V )
EE
425212fb
24
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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UV/OV CLEARS V
, CHECK OV CONDITION, GATE < V
, SENSE < V , SS < 20 • V AND TIMER < V
GATEL CB OS TMRL
UVHI
UV/OV OVERSHOOTS V
AND TIMER ABORTS INITIAL TIMING CYCLE
OVHI
UV/OV DROPS BELOW V
AND TIMER RESTARTS INITIAL TIMING CYCLE
OVLO
TIMER CLEARS V
, CHECK GATE < V
, SENSE < V AND SS < 20 • V
TMRL
GATEL
CB
OS
10 12
9 11
1
2
3
4 5 67
8
V
OVHI
V
OVLO
UV/OV
V
UVHI
V
TMRH
230µA + 8 • I
DRN
5.8µA
TIMER
GATE
5.8µA
V
TMRL
5.8µA
58µA
V
IN
– V
GATEH
58µA
V
GATEL
20 • (V
20 • (V + V
+ V
)
)
ACL
OS
SS
CB
OS
OS
20 • V
V
V
ACL
SENSE
DRAIN
CB
V
V
DRNCL
DRNL
PWRGD
GATE
START-UP
4252-1/2 F12
INITIAL TIMING
Figure 12. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to V )
EE
OV OVERSHOOTS V
. GATE AND SS ARE PULLED DOWN, PWRGD AND TIMER ARE UNAFFECTED
OVHI
OV DROPS BELOW V
, CHECK GATE < V
OVLO
, SENSE < V AND SS < 20 • V
GATEL CB OS
1
2 34
5
67 8 9
V
OVHI
OV
V
OVLO
V
TMRH
5.8µA
230µA + 8 • I
58µA
TIMER
GATE
DRN
5.8µA
58µA
V
– V
GATEH
IN
V
GATEL
20 • (V
+ V
)
OS
ACL
20 • (V + V
)
OS
SS
CB
20 • V
OS
V
V
ACL
CB
SENSE
4252-1/2 F13
GATE
START-UP
Figure 13. Overvoltage Timing (All Waveforms are Referenced to V )
EE
425212fb
25
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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APPLICATIO S I FOR ATIO
CB TIMES OUT
2
CB TIMES OUT
1
2
1
1
2
3
4
V
V
V
TMRH
TMRH
TMRH
5.8µA
230µA + 8 • I
5.8µA
230µA + 8 • I
230µA + 8 • I
DRN
TIMER
TIMER
GATE
SS
TIMER
GATE
SS
230µA + 8 • I
DRN
DRN
DRN
GATE
SS
V
V
V
V
V
V
ACL
ACL
ACL
CB
CB
CB
SENSE
SENSE
SENSE
V
OUT
V
OUT
V
OUT
V
V
DRNCL
DRNCL
DRAIN
DRAIN
DRAIN
PWRGD
PWRGD
PWRGD
CB FAULT
CB FAULT
CB FAULT
CB FAULT
4252-1/2 F14
(14a) Momentary Circuit-Breaker Fault
(14b) Circuit-Breaker Time Out
(14c) Multiple Circuit-Breaker Fault
Figure 14. Circuit-Breaker Timing Behavior (All Waveforms are Referenced to V )
EE
VTMRH threshold, TIMERisdischargedby5.8µA. InFigure
14b, when TIMER exceeds VTMRH, GATE pulls down
immediately and the LTC4252 shuts down. In Figure 14c,
multiple momentary faults cause the TIMER capacitor to
integrate and reach VTMRH. GATE pull down follows and
theLTC4252shutsdown.Duringshutdown,theLTC4252-1
latches TIMER high with a 5.8µA pull-up current source;
the LTC4252-2 activates a shutdown cooling cycle.
pole mechanical pushbutton switch, this may not be
feasible. A double pole, single throw pushbutton switch
removes this restriction by connecting the second switch
to the SS pin. With this method, both the SS and TIMER
pins are released at the same time (see Figure 24).
Shutdown Cooling Cycle (LTC4252-2)
Figure 16 shows the timer behavior of the LTC4252-2. At
time point 2, TIMER exceeds VTMRH, GATE pulls down
immediately and the LTC4252 shuts down. TIMER starts
a shutdown cooling cycle by discharging TIMER with
5.8µA to the VTMRL threshold. TIMER then charges with
5.8µA to the VTMRH threshold. There are four 5.8µA
discharge phases and three 5.8µA charge phases in this
shutdown cooling cycle spanning time points 2 and 3. At
time point 3, the LTC4252 automatic retry occurs with a
start-up cycle. Good thermal management techniques are
highlyrecommended;powerandthermaldissipationmust
be carefully evaluated when implementing the automatic
retry scheme.
Resetting a Fault Latch (LTC4252-1)
The latched circuit breaker fault of LTC4252-1 benefits
from long cooling time. It is reset by pulling the UV pin
below VUVLO with a switch. Reset is also accomplished by
pulling the VIN pin momentarily below (VLKO – VLKH). A
third reset method involves pulling the TIMER pin below
VTMRL as shown in Figure 15. An initial timing cycle is
skipped if TIMER is used for reset. An initial timing cycle
is generated if reset by the UV pin or the VIN pin.
The duration of the TIMER reset pulse should be smaller
than the time taken to reach 0.2V at SS pin. With a single
425212fb
26
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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SWITCH RESETS LATCHED TIMER
SWITCH RELEASES SS
1
2 34
5
67 8 9
5.8µA
TIMER
V
V
TMRH
230µA + 8 • I
5.8µA
5.8µA
DRN
TMRL
58µA
V
– V
GATEH
IN
GATE
SS
58µA
V
GATEL
20 • (V
+ V
)
)
ACL
OS
20 • (V + V
CB
OS
OS
20 • V
V
V
ACL
CB
SENSE
DRAIN
V
V
DRNCL
DRNL
PWRGD
4252-1/2 F15
GATE START-UP
MOMENTARY DPST SWITCH RESET
Figure 15. Pushbutton Reset of LTC4252-1’s Latched Fault
(All Waveforms are Referenced to V )
EE
CIRCUIT BREAKER TIMES OUT
RETRY
3 45
1
2
6
78 9 10
V
TMRH
230µA + 8 • I
230µA + 8 • I
DRN
5.8µA
TMRL
5.8µA
5.8µA
DRN
5.8µA
5.8µA
5.8µA
5.8µA
5.8µA
TIMER
5.8µA
V
58µA
V
IN
– V
GATEH
58µA
GATEL
GATE
SS
V
20 • (V
ACL
+ V
)
)
OS
20 • (V + V
CB
OS
OS
20 • V
V
V
ACL
SENSE
CB
V
OUT
V
V
DRNCL
DRAIN
DRNL
PWRGD
4252-1/2 F16
GATE
START-UP
SHUTDOWN COOLING
CB FAULT
Figure 16. Shutdown Cooling Timing Behavior of LTC4252-2 (All Waveforms are Referenced to V )
EE
425212fb
27
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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APPLICATIO S I FOR ATIO
Analog Current Limit and Fast Current Limit
shown in Figure 18a. If a soft-start capacitor, CSS, is
connected to this SS pin, the soft-start response is modi-
fied from a linear ramp to an RC response (Equation 6), as
shown in Figure 18b. This feature allows load current to
slowly ramp-up at GATE start-up. Soft-start is initiated at
time point 3 by a TIMER transition from VTMRH to VTMRL
(timepoints1to2)orbytheOVpinfallingbelowtheVOVLO
threshold after an OV condition. When the SS pin is below
0.2V, the analog current limit amplifier holds GATE low.
Above 0.2V, GATE is released and 58µA ramps up the
compensation network and GATE capacitance at time
point 4. Meanwhile, the SS pin voltage continues to ramp
up. When GATE reaches the MOSFET’s threshold, the
MOSFETbeginstoconduct.DuetotheMOSFET’shighgm,
the MOSFET current quickly reaches the soft-start control
value of VACL(t) (Equation 7). At time point 6, the GATE
voltage is controlled by the current limit amplifier. The
soft-start control voltage reaches the circuit breaker volt-
age, VCB, at time point 7 and the circuit breaker TIMER
activates. As the load capacitor nears full charge, load
CB TIMES OUT
In Figure 17a, when SENSE exceeds VACL, GATE is regu-
lated by the analog current limit amplifier loop. When
SENSE drops below VACL, GATE is allowed to pull up. In
Figure 17b, when a severe fault occurs, SENSE exceeds
V
FCL and GATE immediately pulls down until the analog
current amplifier establishes control. If the severe fault
causes VOUT to exceed VDRNCL, the DRAIN pin is clamped
at VDRNCL. IDRN flows into the DRAIN pin and is multiplied
by 8. This extra current is added to the TIMER pull-up
current of 230µA. This accelerated TIMER current of
[230µA+8 • IDRN] produces a shorter circuit breaker fault
delay. Careful selection of CT, RD and MOSFET can help
prevent SOA damage in a low impedance fault condition.
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 180µs (or 0V to
1.4V in 230µs for the LTC4252A) at GATE start-up, as
12
34
1
2
V
TMRH
V
TMRH
230µA + 8 • I
DRN
230µA + 8 • I
DRN
5.8µA
TIMER
TIMER
5.8µA
GATE
SS
GATE
SS
V
V
ACL
CB
V
FCL
SENSE
SENSE
V
ACL
V
CB
V
V
OUT
OUT
V
DRNCL
DRAIN
DRAIN
4252-1/2 F17
PWRGD
PWRGD
(17a) Analog Current Limit Fault
(17b) Fast Current Limit Fault
Figure 17. Current Limit Behavior (All Waveforms are Referenced to V )
EE
425212fb
28
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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END OF INTIAL TIMING CYCLE
END OF INTIAL TIMING CYCLE
12 34 567
7a
8
9
10 11
5.8µA
12 3 4 5 6
7
8
9
10 11
V
V
230µA + 8 • I
230µA + 8 • I
TMRH
TMRH
DRN
DRN
5.8µA
TIMER
GATE
TIMER
GATE
V
V
TMRL
TMRL
58µA
58µA
V
– V
V
– V
GATEH
IN
GATEH
IN
V
V
GS(th)
GS(th)
58µA
+ V
58µA
20 • (V
20 • (V
SS
)
+ V
)
OS
ACL
OS
ACL
20 • (V + V
)
OS
20 • (V + V
CB
)
SS
CB
OS
20 • V
20 • V
OS
OS
V
V
V
ACL
CB
ACL
SENSE
SENSE
V
CB
V
V
DRNCL
DRNCL
V
V
DRNL
DRNL
DRAIN
DRAIN
PWRGD
PWRGD
4252-1/2 F18
(18a) Without External C
(18b) With External C
SS
SS
Figure 18. Soft-Start Timing (All Waveforms are Referenced to V )
EE
current begins to decline below VACL(t). The current limit
loop shuts off and GATE releases at time point 8. At time
point 9, the SENSE voltage falls below VCB and TIMER
deactivates.
R6
VCB
=
(16)
R4 VSUPPLY(MAX)
If R6 is 27Ω, R4 is 38.3k. The peak circuit breaker power
limit is:
Large values of CSS can cause premature circuit breaker
time out as VACL(t) may exceed the VCB potential during
the circuit breaker delay. The load capacitor is unable to
achieve full charge in one GATE start-up cycle. A more
serioussideeffectoflargeCSS valuesisSOAdurationmay
be exceeded during soft-start into a low impedance load.
A soft-start voltage below VCB will not activate the circuit
breaker TIMER.
2
V
+ VSUPPLY(MAX)
(
)
SUPPLY(MIN)
POWERMAX
=
4 • VSUPPLY(MIN) • VSUPPLY(MAX)
•POWERSUPPLY(MIN)
(17)
= 1.064 •POWERSUPPLY(MIN)
when
VSUPPLY = 0.5 • (VSUPPLY(MIN) + VSUPPLY(MAX)) = 57V.
Power Limit Circuit Breaker
The peak power at the fault current limit occurs at the
supply overvoltage threshold. The fault current limited
power is:
Figure 19 shows the LTC4252A-1 in a power limit circuit
breaking application. The SENSE pin is modulated by the
boardsupplyvoltage, VSUPPLY. Thezenervoltage, VZ isset
to be the same as the low supply operating voltage,
VSUPPLY(MIN) = 43V. If the goal is to have the high supply
operating voltage, VSUPPLY(MAX) = 71V giving the same
power at VSUPPLY(MIN), then resistors R4 and R6 are
selected using the ratio:
POWERFAULT
=
VSUPPLY
R6
R4
⎛
⎝
⎞
⎟
⎠
(18)
• V
– V
– V •
(
)
⎜
ACL
SUPPLY
Z
RS
425212fb
29
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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GND
+
R
IN
R4
38.3k
C
L
100µF
3× 1.8k
1/4W EACH
C
R5
IN
LOAD
EN
GND
(SHORT PIN)
1
1µF
100k
V
R1
IN
D1
390k
*
V
LTC4252A-1
PWRGD
BZV85C43
OUT
1%
9
8
2
7
6
4
UV
R
1M
D
OV
DRAIN
GATE
10
3
Q1
IRF530S
TIMER
SS
R6 27Ω
R2
30.1k
1%
C
T
SENSE
V
EE
0.68µF
R
R
S
0.02Ω
C
5
C1
10nF
C
10Ω
C
SS
68nF
C
10nF
4252-1/2 F19
–48V
*FMMT493
Figure 19. Power Limit Circuit Breaking Application
Circuit Breaker with Foldback Current Limit
Capacitor C3 and resistor R4 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C3 and R4, capacitor C2 pulls the gate of Q1 up to
a voltage roughly equal to VEE • C2/CGS(Q1) before the
LTC4252A powers up. By placing capacitor C3 in parallel
withthegatecapacitanceofQ1andisolatingthemfromC2
using resistor R4, the problem is solved. The value of C3
is given by:
Figure 20 shows the LTC4252A in a foldback current limit
application. When VOUT is shorted to the –48V RTN
supply, current flows through resistors R4 and R5. This
results in a voltage drop across R5 and a corresponding
reductioninvoltagedrop acrossthesenseresistor, RS, as
the ACL amplifier servos the sense voltage between the
SENSE and VEE pins to about 60mV. The short-circuit
current through RS reduces as the VOUT voltage increases
duringanoutputshort-circuitcondition. Withoutfoldback
current limiting resistor R5, the current is limited to 3A
during analog current limit. With R5, the short-circuit
current is limited to 0.5A when VOUT is shorted to 71V.
VSUPPLY(MAX)
VGS(TH),Q1
C3 =
• C2 + C
(
)
GD(Q1)
(20)
C3 ≈ 35 • C2 for VSUPPLY(MAX) = 71V
where VGS(TH),Q1 is the MOSFET’s minimum gate thresh-
old and VSUPPLY(MAX) is the maximum operating input
voltage.
Inrush Control Without a Sense Resistor
During Power-Up
Figure21showstheLTC4252Ainanapplicationwherethe
inrush current is controlled without a sense resistor dur-
ing power-up. This setup is suitable only for applications
that don’t require short-circut protection from the
LTC4252A. ResistorR4andcapacitorC2actasafeedback
network to accurately control the inrush current. The C2
capacitor can be calculated with the following equation:
Diode-ORing
Figure 22 shows the LTC4252 used as diode-oring with
Hot Swap capability in a dual –48V power supply applica-
tion. The conventional diode-OR method uses two high
power diodes and heat sinks to contain the large heat
dissipation of the diodes. With the LTC4252 controlling
the external FETs Q2 and Q3 in a diode-OR manner, the
smallturn-onvoltageacrossthefullyenhancedQ2andQ3
reduces the power dissipation significantly.
IGATE •CL
C2 =
(19)
I
INRUSH
where IGATE = 58µA and CL is the total load capacitance.
425212fb
30
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
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APPLICATIO S I FOR ATIO
–48V RTN
(LONG PIN)
+
R
IN
C
L
3× 1.8k
100µF
1/4W EACH
LOAD
EN
R3
5.1k
C
IN
1µF
–48V RTN
(SHORT PIN)
1
V
R1
IN
LTC4252A-1
390k
*
V
1%
2
7
OUT
8
OV
PWRGD
R
1M
D
9
UV
DRAIN
R4
C1
38.3k
10nF
10
6
4
Q1
TIMER
GATE
IRF530S
R5 27Ω
R2
30.1k
1%
3
C
T
SS
SENSE
V
EE
0.68µF
R
R
S
C
5
C
10Ω
C
0.02Ω
SS
68nF
C
10nF
4252-1/2 F20
–48V
*MOC207
Figure 20. Circuit Breaker with Foldback Current Limit Application
–48V RTN
(LONG PIN)
+
R
IN
C
L
3× 1.8k
100µF
1/4W EACH
LOAD
EN
R3
C
IN
1µF
5.1k
–48V RTN
(SHORT PIN)
1
V
R1
390k
1%
IN
LTC4252A-1
*
V
2
7
OUT
8
9
OV
UV
PWRGD
R
1M
D
DRAIN
C2
10nF
100V
C1
10nF
R4
1k
1%
10
3
6
4
Q1
TIMER
SS
GATE
IRF530S
R2
30.1k
1%
C
T
SENSE
V
EE
0.68µF
C3
330nF
25V
5
C
SS
68nF
4252-1/2 F21
–48V
*MOC207
Figure 21. Inrush Control Without a Sense Resistor Application
At power-up, Q5 and Q8 are held off low by the SS pin of
the LTC4252; resistors R5 and R8 pull the SENSE pin
closed to VEE. VEE is connected to the power supply with
lower voltage through the body diodes Q2 or Q3 until Q2
or Q3 is turned on. This allows the LTC4252 to perform a
start-up cycle and ramp up the SS and GATE voltage.
resistors R3 and R6. The ACL amplifier of the LTC4252
servos the sense voltage to about 100mV as the GATE
voltageregulatesQ2andQ3.CurrentflowsintoR4,Q4and
R7, Q7asQ2andQ3turnon. Therespectivenodevoltages
attheR3andR4connectionandtheR6andR7connection
are always kept equal to their respective sense voltages by
the Q4 and Q2 VDS drop and the Q7 and Q3 VDS drop
assuming the Q5 and Q8 VDS drop is negligible.
As the SS voltage ramps up to 2.2V, it turns on Q5 and Q8
and pulls TIMER low through Q6 and Q9. The sense
voltage rises as current flows into R5 and R8 through
425212fb
31
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U
W
U U
APPLICATIO S I FOR ATIO
Hot Swap SECTION
–48V RTN
R
IN1
3× 1.8k IN SERIES
1/4W EACH
LOAD
MODULE
C
IN
1
R1
1µF
R
D
420k
V
IN
1M
7
8
6
5
UV/OV
TIMER
DRAIN
GATE
C1
10nF
Q1
IRF530S
R
C1
LTC4252-1
C
R2
32.4k
T
10Ω
0.33µF
C
C1
22nF
2
3
SS
SENSE
V
EE
RS
0.02Ω
4
C
SS
68nF
DIODE-OR CIRCUIT FOR CHANNEL A
–48V A
R
IN2
3× 1.8k IN SERIES
1/4W EACH
1
V
IN
R3
9
2
7
DRAIN
UV
PWRGD
12k
C
IN2
1µF
R4
150Ω
Q5
FDV301N
LTC4252-2
10
3
4
6
TIMER
SENSE
Q4
BSS131
Q6
FDV301N
SS
OV
8
Q2
GATE
IRF530S
V
EE
R
R5
560Ω
C2
10Ω
5
C
C2
22nF
DIODE-OR CIRCUIT FOR CHANNEL B
–48V B
R
IN3
3× 1.8k IN SERIES
1/4W EACH
1
V
IN
R6
12k
9
2
7
DRAIN
UV
PWRGD
C
IN3
1µF
R7
150Ω
Q8
FDV301N
LTC4252-2
10
3
4
6
TIMER
SENSE
Q7
BSS131
Q9
FDV301N
SS
OV
8
Q3
IRF530S
GATE
V
EE
R
R8
560Ω
C3
10Ω
5
C
C3
22nF
4252-1/2 F22
Figure 22. –48V/2.5A Diode-OR Application
425212fb
32
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U
W
U U
APPLICATIO S I FOR ATIO
The internal fault latches of the LTC4252 are disabled as
the TIMER pin is always held low by the SS voltage when
Q2 and Q3 are in analog current limit.
current flow. The sense voltage is lifted up and causes the
fast comparator of LTC4252 to trip and pull the GATE low
instantly. The channel A supply short will not cause Q3 of
channel B diode-OR circuit to turn off.
If both power supplies from channel A and B are exactly
equal, then equal load current will flow through Q2 and Q3
to the load module via the Hot Swap section.
Similarly, when the channel B supply is shorted to the
–48V RTN (or GND), large current flows into Q7 momen-
tarily and creates a voltage drop across R7, which in turn
reducesthegate-to-sourcevoltageofQ7, thuslimitingthe
currentflow. Theincreaseinsensevoltagewilltripthefast
comparator of LTC4252 and pull the GATE low instantly.
The channel B supply short will not cause Q2 of channel A
diode-OR circuit to turn off. The load short at the output of
Q1 is protected by the Hot Swap section.
If the channel A supply is greater than the channel B by
more than 100mV, the sense voltage will rise above the
fast comparator trip threshold of 200mV, the GATE will be
pulled low and Q2 is turned off. The GATE ramps up and
regulates Q2 when the channel A supply is equal to the
channel B supply. Likewise, if the channel B supply is
greater than channel A by more than 100mV, it trips the
fast comparator and GATE is pulled low and Q3 is turned
off. The GATE ramps up and regulates Q3 when the
channel B supply is equal to the channel A supply.
Using an EMI Filter Module
Many applications place an EMI filter module in the power
path to prevent switching noise of the module from being
injected back onto the power supply. A typical application
using the Lucent FLTR100V10 filter module is shown in
Figure 23. When using a filter, an optoisolator is required
to prevent common mode transients from destroying the
PWRGD and ON/OFF pins.
Resistors R4, R7 and external FETs Q4 and Q7 limit the
current flow into Q5 and Q8 during their respective supply
source short. When the channel A supply is shorted to the
–48V RTN (or GND), large current flows into Q4 momen-
tarily and creates a voltage drop across R4, which in turn
reduces the gate-to-source voltage of Q4, limiting the
–48V RTN
(LONG PIN)
R
IN
3× 1.8k
1/4W
1
2
9
8
+
+
+
C
V
V
5V
R3
IN
IN
OUT
1µF
5.1k
–48V RTN
(SHORT PIN)
1
SENSE
7
V
R1
390k
1%
IN
LTC4252A-1
TRIM
*
ON/OFF
+
2
7
8
9
C6
100µF
16V
OV
PWRGD
LUCENT
JW050A1-E
+
+
V
V
OUT
UV
DRAIN
IN
LUCENT
FLTR100V10
C2
0.1µF
100V
R
C1
+
D
C3
0.1µF
100V
C4
100µF
100V
C5
1M
6
5
10nF
0.1µF
–
10
3
6
4
SENSE
Q1
IRF530S
1N4003
100V
TIMER
SS
GATE
4
–
–
–
–
R2
30.1k
1%
V
V
C
V
V
IN
OUT
T
IN
OUT
CASE
SENSE
0.68µF
R
10Ω
R
S
0.02Ω
CASE
V
C
EE
3
5
C
SS
68nF
C
C
10nF
4252-1/2 F20
*MOC207
–48V
Figure 23. Typical Application Using a Filter Module
425212fb
33
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.52
(.0205)
REF
0.65
(.0256)
BSC
0.42 ± 0.038
(.0165 ± .0015)
8
7 6
5
TYP
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ± 0.152
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
0.127 ± 0.076
(.009 – .015)
(.005 ± .003)
0.65
(.0256)
BSC
TYP
MSOP (MS8) 0204
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
425212fb
34
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U
PACKAGE DESCRIPTIO
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
REF
0.50
0.305 ± 0.038
(.0120 ± .0015)
TYP
(.0197)
10 9
8
7 6
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4 5
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.127 ± 0.076
(.005 ± .003)
MSOP (MS) 0603
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
425212fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
35
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
U
TYPICAL APPLICATIO
GND
R
IN
+
C
L
2× 5.1k IN SERIES
LOAD
100µF
1/4W EACH
GND
1
C
IN
(SHORT PIN)
R1
V
OUT
1µF
V
IN
LTC4252-1
R
1M
402k
1%
D
7
8
2
6
5
3
UV/OV
TIMER
SS
DRAIN
GATE
R2
Q1
IRF540S
32.4k
C
1%
T
SENSE
V
EE
150nF
R
C
10Ω
R
S
0.01Ω
R3
22Ω
4
C1
10nF
C
SS
PUSH
RESET
27nF
C
C
22nF
4252-1/2 F24
–48V
Figure 24. –48V/5A Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1640AH/LT1640AL Negative High Voltage Hot Swap Controllers in SO-8
Negative High Voltage Supplies from –10V to –80V
Supplies from 9V to 80V, Latched Off/Autoretry
3V to 16.5V, Overvoltage Protection up to 33V
Operates from –6V to –16V
LT1641-1/LT1641-2
LTC1642
Positive High Voltage Hot Swap Controllers in SO-8
Fault Protected Hot Swap Controller
Negative Voltage Hot Swap Controller
Dual Supply Hot Swap Controller
LTC4214
LTC4220
±2.2V to ±16.5V Operation
LT4250
–48V Hot Swap Controller in SO-8
Active Current Limiting, Supplies from –20V to –80V
Fast Active Current Limiting, Supplies from –15V
LTC4251/LTC4251-1
LTC4253
–48V Hot Swap Controllers in SOT-23
–48V Hot Swap Controller with Sequencer
Fast Current Limiting with Three Sequenced Power Good Outputs,
Supplies from –15V
425212fb
LT 0406 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2001
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