LTC4260CGN#TRPBF [Linear]
LTC4260 - Positive High Voltage Hot Swap Controller with I<sup>2</sup>C Compatible Monitoring; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C;
| 型号： | LTC4260CGN#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC4260 - Positive High Voltage Hot Swap Controller with I<sup>2</sup>C Compatible Monitoring; Package: SSOP; Pins: 24; Temperature Range: 0°C to 70°C 监控 控制器 |
| 文件： | 总28页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4260
Positive High Voltage
Hot Swap Controller with
2
I C Compatible Monitoring
U
FEATURES
DESCRIPTIO
The LTC®4260 Hot SwapTM controller allows a board to be
safely inserted and removed from a live backplane. Using
an external N-channel pass transistor, the board supply
voltage can be ramped up at an adjustable rate. An I2C
interface and onboard ADC allow monitoring of board
current, voltage and fault status.
■
Allows Safe Insertion into Live Backplane
■
8-Bit ADC Monitors Current and Voltage
I2CTM/SMBus Interface
■
■
Wide Operating Voltage Range: 8.5V to 80V
■
High Side Drive for External N-Channel MOSFET
■
Input Overvoltage/Undervoltage Protection
■
Optional Latchoff or Autoretry After Faults
The device features adjustable analog foldback current
limit with latch off or automatic restart after the LTC4260
remains in current limit beyond an adjustable time-out
delay.
■
Alerts Host After Faults
Foldback Current Limiting
■
■
Available in 24-Lead SO, 24-Lead Narrow
SSOP and 32-Lead (5mm × 5mm) QFN Packages
The controller has additional features to interrupt the host
when a fault has occurred, notify when output power is
good,detectinsertionofaloadcardandpower-upineither
the on or off state.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
I2C is a trademark of Philips Electronics N.V.
U
APPLICATIO S
■
Electronic Circuit Breakers
Live Board Insertion
Computers, Servers
■
■
U
TYPICAL APPLICATIO
3A, 48V Card Resident Application
Power Up Waveforms
0.010Ω
FDB3632
V
OUT
48V
48V
C
L
= 1000µF
+
C
L
43.5k
V
IN
50V/DIV
49.9k
10Ω
100k
6.8nF
SENSE GATE SOURCE
I
IN
2A/DIV
3.57k
0.1µF
1.74k
2.67k
UV
OV
SDAO
SDAI
SCL
V
DD
V
OUT
*
FB
BD_PRST
ADIN
50V/DIV
SDA
SCL
ALERT
LTC4260
TIMER
GPIO
5V/DIV
24k
ALERT
ON
GPIO
INTV
GND
CC
4260 TA01
4260 TA02
0.1µF
68nF
25ms/DIV
GND
BACKPLANE PLUG-IN
CARD
*DIODES INC. SMBT70A
4260f
1
LTC4260
W W U W
ABSOLUTE AXI U RATI GS (Notes 1, 2)
Supply Voltages (VDD) ............................ –0.3V to 100V
Input Voltages
ALERT, SDAO ...........................................–0.3V to 6.5V
Supply Voltage (INTVCC) ......................... –0.3V to 6.2V
Operating Temperature Range
LTC4260C ............................................... 0°C to 70°C
LTC4260I............................................. –40°C to 85°C
Storage Temperature Range
SENSE ............................ VDD – 10V or –0.3V to VDD
SOURCE .......................... GATE – 5V to GATE + 0.3V
BD_PRST, FB, ON, OV, UV ................... –0.3V to 12V
ADR0-ADR2, TIMER, ADIN ..... –0.3V toINTVCC + 0.3V
SCL, SDAI ........................................... –0.3V to 6.5V
Output Voltages
GN, SW Packages............................. –65°C to 150°C
UH Package ...................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
GPIO................................................... –0.3V to 100V
GATE (Note 3) ..................................... –0.3V to 100V
GN, SW Packages Only..................................... 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
TOP VIEW
SENSE
1
2
3
4
5
6
7
8
9
24 GATE
1
2
GATE
SOURCE
NC
24
23
22
21
20
19
18
17
16
15
14
13
SENSE
32 31 30 29 28 27 26 25
V
DD
23 SOURCE
V
DD
NC
NC
1
2
3
4
5
6
7
8
24 NC
23 NC
NC
NC
22 NC
3
NC
UV
21 NC
4
NC
NC
NC
NC
22
21
UV
20 GPIO
19 INTV
5
GPIO
OV
UV
33
GND
ON
6
INTV
CC
GND
ON
CC
OV
20 GPIO
INTV
18 FB
7
FB
GND
ON
19
18 FB
17 ADR2
CC
SCL
SDAI
17 ADR2
16 ADR1
15 ADR0
14 BD_PRST
13 ADIN
8
ADR2
ADR1
ADR0
BD_PRST
ADIN
SCL
9
SCL
SDAI
SDAO
ALERT
TIMER
SDAO 10
ALERT 11
TIMER 12
10
11
12
9
10 11 12 13 14 15 16
SW PACKAGE
24-LEAD PLASTIC SO
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
GN PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 34°C/W
TJMAX = 125°C, θJA = 85°C/W
TJMAX = 125°C, θJA = 75°C/W
EXPOSED PAD (PIN 33) PCB ELECTRICAL CONNECTION OPTIONAL
ORDER
PART NUMBER
ORDER
PART NUMBER
ORDER
PART NUMBER
UH PART
MARKING
LTC4260CUH
LTC4260IUH
LTC4260CGN
LTC4260IGN
LTC4260CSW
LTC4260ISW
4260
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted.
SYMBOL
General
PARAMETER
CONDITIONS
MIN
8.5
7
TYP
MAX
UNITS
V
DD
Input Supply Range
Input Supply Current
●
●
●
80
5
V
I
2
mA
DD
V
V
DD
Supply Undervoltage Lockout
V Falling
DD
7.45
7.9
V
4260f
DD(UVL)
2
LTC4260
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
Supply Undervoltage Lockout INTV Falling
MIN
3.4
5
TYP
3.8
5.5
MAX
4.2
6
UNITS
INTV
INTV
V
●
●
V
V
CC(UVL)
CC
CC
CC
Internal Regulator Voltage
Gate Drive
t
Turn-On Delay
●
50
100
150
ms
D
∆V
GATE
External N-Channel Gate Drive
GATE
V
V
= 20V to 80V
= 8.5V to 20V
●
●
10
4.5
14
6
18
18
V
V
DD
DD
(V
– V
)
SOURCE
I
I
I
I
External N-Channel Pull-Up Current
External N-Channel Fast Pull-Down
External N-Channel Pull-Down Current
SOURCE Pin Input Current
Gate Drive On, V
= 0V
●
●
●
●
–14
400
0.7
–18
600
1
–22
1000
1.4
µA
mA
mA
µA
GATE(UP)
GATE(FST)
GATE(DN)
SOURCE
GATE
Fast Turn Off, V
= 48V, V
= 38V
SOURCE
GATE
Gate Drive Off, V
SOURCE = 48V
= 58V, V
= 48V
GATE
SOURCE
200
400
600
Input Pins
V
ON Pin Threshold Voltage
ON Pin Hysteresis
V
Rising
●
●
●
●
●
●
●
●
●
●
●
1.19
60
1.235
130
0
1.27
200
±1
V
mV
µA
V
ON(TH)
ON
∆V
ON(HYST)
I
ON Pin Input Current
V
V
= 1.2V
Rising
ON(IN)
ON
OV
V
OV Pin Threshold Voltage
OV Pin Hysteresis
3.43
70
3.5
90
3.56
120
±1
OV(TH)
∆V
mV
µA
V
OV(HYST)
I
OV Pin Input Current
V
V
= 3.5V
Rising
0
OV(IN)
OV
UV
V
UV Pin Threshold Voltage
UV Pin Hysteresis
3.43
310
3.5
380
0
3.56
440
±2
UV(TH)
∆V
mV
µA
V
UV(HYST)
I
UV Pin Input Current
V
V
= 3.5V
Falling
UV(IN)
UV
UV
V
UV Pin Reset Threshold Voltage
UV Pin Reset Threshold Hysteresis
Current Limit Sense Voltage Threshold
1.18
80
1.235
160
1.27
250
UV(RTH)
∆V
∆V
mV
UV(RHYST)
V
V
= 3.5V
= 0V
●
●
40
10
50
20
60
30
mV
mV
SENSE(TH)
FB
FB
(V – V
DD
)
SENSE
I
SENSE Pin Input Current
Foldback Pin Power Good Threshold
FB Pin Power Good Hysteresis
Foldback Pin Input Current
BD_PRST Input Threshold
BD_PRST Hysteresis
V
= 48V
SENSE
●
●
●
●
●
●
●
●
70
3.43
80
100
3.5
100
0
130
3.56
120
±2
µA
V
SENSE(IN)
V
FB Rising
FB
∆V
mV
µA
V
FB(HYST)
I
FB = 3.5V
FB
V
V
Rising
BD_PRST
1.2
70
1.235
130
–10
1.8
80
1.27
190
–16
2
BD_PRST(TH)
∆V
mV
µA
V
BD_PRST(HYST)
I
BD_PRST Pullup Current
GPIO Pin Input Threshold
GPIO Pin Hysteresis
BD_PRST = 0V
–7
BD_PRST
V
V
Rising
1.6
GPIO(TH)
GPIO
∆V
mV
V
GPIO(HYST)
V
GPIO Pin Output Low Voltage
GPIO Pin Input Leakage Current
ADIN Pin Input Resistance
ADIN Pin Input Current
I
= 2mA
= 80V
●
●
●
●
0.25
0
0.5
GPIO(OL)
GPIO
I
V
V
V
±10
µA
MΩ
µA
GPIO(IN)
GPIO
ADIN
ADIN
R
= 1.28V
= 2.56V
2
10
ADIN
I
0
±1
ADIN
Timer
V
V
TIMER Pin High Threshold
TIMER Pin Low Threshold
TIMER Pin Pull-Up Current
TIMER Pin Pull-Down Current
TIMER Pin Current Ratio
V
V
V
V
Rising
Falling
= 0V
●
●
●
●
●
1.2
0.1
–80
1.4
1.6
1.235
0.2
–100
2
1.28
0.3
V
V
TIMER(H)
TIMER(L)
TIMER
TIMER
TIMER
TIMER
I
I
I
–120
2.6
µA
µA
%
TIMER(UP)
TIMER(DN)
TIMER(RATIO)
= 1.3V
2
2.7
I
/I
TIMER(DN) TIMER(UP)
4260f
3
LTC4260
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 48V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
AC Parameters
t
t
t
Input High (ON) to GATE High
Propagation Delay
C
C
V
= 1pF
= 1pF
●
●
●
1
3
3
1
µs
µs
µs
PLH(GATE)
PHL(GATE)
PHL(SENSE)
GATE
GATE
Input High (OV, BD_PRST), Input Low
(ON, UV) to GATE Low Propagation Delay
0.5
0.4
(V – SENSE) High to GATE Low
DD
– SENSE = 200mV, C
= 10nF
DD
GATE
ADC
Resolution (No Missing Codes)
Integral Nonlinearity
(Note 4)
●
8
Bits
V
– SENSE (Note 5)
●
●
●
–2
–1.25
–1.25
0.5
0.2
0.2
2
1.25
1.25
LSB
LSB
LSB
DD
SOURCE
ADIN
Offset Error
V
– SENSE
●
●
●
–1.5
–1
–1
1.5
1
1
LSB
LSB
LSB
DD
SOURCE
ADIN
1LSB Step Size
Full-Scale Voltage
Conversion Rate
V
– SENSE (Note 6)
●
●
●
292
392
9.8
300
400
10
308
408
10.2
µV
mV
mV
DD
SOURCE
ADIN
V
– SENSE (Note 7)
●
●
●
74.9
100.4
2.51
76.8
102.4
2.560
78.7
104.4
2.61
mV
V
V
DD
SOURCE
ADIN
10
Hz
2
I C Interface
V
ADR0 to ADR2 Input High Voltage
Threshold
●
INTV
INTV
INTV
CC
V
ADR(H)
CC
CC
– 0.6
0.25
–80
1.6
– 0.45
– 0.25
0.65
80
V
ADR0 to ADR2 Input Low Voltage Threshold
ADR0 to ADR2 Input Current
SDAI, SCL Input Threshold
SDAI, SCL Input Current
●
●
●
●
●
●
●
0.45
V
µA
V
ADR(L)
I
ADR0 to ADR2 = 0V, 5.5V
SCL, SDAI = 5V
ADR(IN)
V
1.8
0
2
SDAI,SCL(TH)
SDAI,SCL(IN)
I
±1
µA
V
V
V
SDAO Output Low Voltage
I
I
= 5mA
= 5mA
0.2
0.2
0
0.4
0.4
±1
SDAO(OL)
ALERT(OL)
SDAO
ALERT Output Low Voltage
SDAO, ALERT Input Current
V
ALERT
I
SDAO, ALERT = 5V
µA
SDAO,ALERT(IN)
2
I C Interface Timing (Note 4)
f
t
Maximum SCL Clock Frequency
Operates with f ≤ f
400
kHz
SCL(MAX)
BUF(MIN)
SCL
SCL(MAX)
Minimum Bus Free Time Between
Stop/Start Condition
0.12
30
1.3
600
600
µs
t
t
Minimum Repeated Start Condition
Set-Up Time
ns
ns
SU,STA(MIN)
HD,STA(MIN)
Minimum Hold Time After (Repeated) Start
Condition
140
t
t
t
t
t
Minimum Stop Condition Set-Up Time
Minimum Data Set-Up Time Input
Minimum Data Hold Time Input
Minimum Data Hold Time Output
Maximum Suppressed Spike Pulse Width
SCL, SDA Input Capacitance
30
30
600
100
0
ns
ns
ns
ns
ns
pF
SU,STO(MIN)
SU,DAT(MIN)
HD,DATI(MIN)
HD,DATO(MIN)
SP(MAX)
–100
500
110
5
300
50
900
250
10
C
SDAI Tied to SDAO
X
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
4260f
4
LTC4260
ELECTRICAL CHARACTERISTICS
Note 3: Limits on maximum rating is defined as whichever limit occurs
first. An internal clamp limits the GATE pin to a minimum of 10V above
source. Driving this pin to voltages beyond the clamp may damage the
device.
Note 6: 1LSB step size specification is guaranteed by full-scale voltage
measurement and by design.
Note 7: Full-scale current sense specification corresponds to code 200.
Codes above 200 may be discarded by offset cancellation.
Note 4: Guaranteed by design and not subject to test.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
precise analog input voltage. Maximum specifications are limited by the
LSB step size and the single shot measurement. Typical specificatons are
measured from the 1/4, 1/2 and 3/4 areas of the quantization band.
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C, VDD = 48V unless otherwise noted.
UV Low-High Threshold
vs Temperature
IDD vs VDD
INT VCC vs ILOAD
3.54
3.52
3.50
3.48
3.0
2.5
2.0
1.5
1.0
6
5
4
3
2
1
0
V
= 48V
DD
V
= 12V
DD
85°C
25°C
–40°C
CAUTION: DRAWING CURRENT
FROM INTV INCREASES POWER
CC
DISSIPATION AND T
J
3.46
–50 –25
0
25
50
75
100
0
20
40
V
60
(V)
80
100
0
–2
–4
I
–6
(mA)
–8
–10
TEMPERATURE (°C)
LOAD
DD
4260 G02
4260 G01
4260 G18
ON, BD_PRST Low-High
Threshold vs Temperature
ON, BD_PRST Hysteresis
vs Temperature
UV Hysteresis vs Temperature
0.16
0.15
0.14
0.13
0.12
0.11
0.10
1.245
1.240
1.235
1.230
0.39
0.38
0.37
0.36
1.225
1.220
0.35
0.34
–50
0
25
50
75
100
–25
–50
0
25
50
75
100
–25
–50
0
25
50
75
100
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4260 G05
4260 G04
4260 G03
4260f
5
LTC4260
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C, VDD = 48V unless otherwise noted.
Current Limit Propagation Delay
vs Sense Voltage
TIMER Pull-Up Current
vs Temperature
Current Limit Sense Voltage
vs FB Voltage
1000
100
10
60
50
40
30
20
10
0
–110
–105
–100
–95
1
0.1
–90
2.5
FB VOLTAGE (V)
3
0
0.5
1
1.5
2
3.5
4
0
50
100 150 200 250 300 350
–50 –25
0
25
50
75
100
CURRENT LIMIT SENSE VOLTAGE (V – V
) (mV)
SENSE
TEMPERATURE (°C)
DD
4260 G07
4260 G08
4260 G06
I
GATE Pull Up vs Temperature
Gate Drive vs IGATE
Gate Drive vs VDD
–25
–20
–15
–10
16
16
14
12
10
8
85°C
14
12
10
V
= 80V
DD
25°C
–40°C
V
= 48V
DD
6
8
6
4
V
= 12V
–10
DD
4
2
0
–50
–25
0
25
50
75
100
25
35
40
0
–5
–15
–20
5
10
15
20
V
30
TEMPERATURE (°C)
I
(µA)
(V)
DD
GATE
4260 G09
4260 G10
4260 G11
ADC Total Unadjusted Error
vs Code (ADIN Pin)
GPIO VOUT Low vs ILOAD
Gate Drive vs Temperature
2
1
16
15
14
13
14
12
10
8
0
6
4
–1
–2
12
11
2
0
128
192
0
256
–50
0
25
TEMPERATURE (°C)
50
75
100
0
10
20
30
(mA)
40
50
60
64
–25
CODE
I
LOAD
4260 G14
4260 G12
4260 G13
4260f
6
LTC4260
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C, VDD = 48V unless otherwise noted.
ADC Full-Scale Error
vs Temperature (ADIN Pin)
ADC INL vs Code (ADIN Pin)
ADC DNL vs Code (ADIN Pin)
2
1
0.50
0.25
0
0.50
0.25
0
0
–1
–0.25
–0.50
–0.25
–0.50
–2
–50
–25
0
25
50
75
100
128
192
128
192
0
64
256
0
256
64
TEMPERATURE (°C)
CODE
CODE
3708 G15
4260 G17
4260 G16
U
U
U
PI FU CTIO S
ADIN: ADC Input. A voltage between 0V and 2.56V applied Exposed Pad (Pin 33, UH Package): Exposed Pad may be
to this pin can be measured by the onboard ADC. Tie to left open or connected to device ground.
ground if unused.
FB: Foldback and Power Good Input. A resistive divider
ADR0 to ADR2: Serial Bus Address Inputs. Tying these fromtheoutputvoltageistiedtothispin.Whenthevoltage
pins to ground, open or INTVCC configures one of 27 pos- at this pin drops below 3.41V, the output power is consid-
sible addresses. See Table 1 in Applications Information. ered bad and the current limit is reduced. The power bad
condition can be indicated with the GPIO pin and a power
ALERT: Fault Alert Output. Open-drain logic output that
bad fault can be logged in this condition. See Applications
can be pulled to ground when a fault occurs to alert the
Information.
host controller. A fault alert is enabled by the ALERT
register. This device is compatible with SMBus alert GATE: Gate Drive for External N-Channel FET. An internal
protocol. See Applications Information. Tie to ground if 18µA current source charges the gate of the external
unused.
N-channel MOSFET. A resistor and capacitor network
from this pin to ground sets the turn-on rate and compen-
sates the active current limit. During turn-off there is a
1mA pull-down current. During a short circuit or under-
voltage lockout (VDD or INTVCC), a 600mA pull-down
current source between GATE and SOURCE is activated.
BD_PRST: Board Present Input. Ground this pin to enable
the N-channel FET to turn on after 100ms debounce delay.
When this pin is high, the FET is off. An internal 10µA
currentsourcepullsupthispin. Transitionsonthispinwill
berecordedintheFAULTregister.Ahigh-to-lowtransition
activates the logic to read the state of the ON pin and clear GND: Device Ground.
Faults. See Applications Information.
4260f
7
LTC4260
U
U
U
PI FU CTIO S
GPIO: General Purpose Input/Output. Open-drain logic
output and logic input. Defaults to pull low to indicate
power is bad. Configure according to Table 3.
SENSE: Current Sense Input. Connect this pin to the
output of the current sense resistor. The current limit
circuit controls the GATE pin to limit the sense voltage
between the VDD and SENSE pins to 50mV or less depend-
ing on the voltage at the FB pin. This pin is used as an input
to the 8-bit ADC.
NC: No Connect. Unconnected pins. These pins provide
extra distance between high and low voltage pins.
ON: On Control Input. A rising edge turns on the external
N-channel FET and a falling edge turns it off. This pin is
also used to configure the state of the FET ON bit (and
hence the external FET) at power up. For example if the ON
pinistiedhigh,thentheFETONcontrolbit(A3)willgohigh
100ms after power-up. Likewise if the ON pin is tied low
then the part will remain off after power-up until the FET
ON control bit is set high using the I2C bus. A high-to-low
transition on this pin will clear faults.
SOURCE: N-Channel MOSFET Source Connection and
ADC Input. Connect this pin to the source of the external
N-channel MOSFET switch. This pin also serves as the
ADC input to monitor output voltage. The pin provides a
returnforthegatepull-downcircuitandasasupplyforthe
charge pump circuit.
TIMER: Timer Input. Connect a capacitor between this
pinandgroundtoseta12ms/µFdurationforcurrentlimit
before the switch is turned off. The duration of the off
time is 518ms/µF when autoretry during current limit is
enabled. A minimum value of 0.1nF must be connected
to this pin.
OV (GN/UH Packages): Overvoltage Comparator Input.
Connect this pin to an external resistive divider from VDD.
If the voltage at this pin rises above 3.5V, an overvoltage
fault is detected and the switch turns off. Tie to GND if
unused.
UV: Undervoltage Comparator Input. Connect this pin to
an external resistive divider from VDD. If the voltage at this
pinfallsbelow3.12V,anundervoltagefaultisdetectedand
the switch turns off. Pulling this pin below 1.2V resets all
faults and allows the switch to turn back on. Tie to INTVCC
if unused.
SCL: Serial Bus Clock Input. Data at the SDA pin is shifted
in or out on rising edges of SCL. This is a high impedance
pin that is generally driven by an open-collector output
from a master controller. An external pull-up resistor or
current source is required.
VDD:SupplyVoltageandCurrentSenseInput. Thispinhas
an undervoltage lockout threshold of 7.45V.
SDAI: Serial Bus Data Input. A high impedance input used
for shifting in address, command or data bits. Normally
tied to SDAO to form the SDA line.
INTVCC: Internal Low Voltage Supply Decoupling Output.
Connecta0.1µFcapacitorfromthispintoground.Thispin
can be used to drive the other pins to logic high and has an
undervoltage lockout threshold of 3.8V.
SDAO:SerialBusDataOutput. Open-drainoutputusedfor
sendingdatabacktothemastercontrolleroracknowledg-
ing a write operation. Normally tied to SDAI to form the
SDA line. An external pull-up resistor or current source is
required.
VDDK (UH Package): Same as VDD. Connect this pin to
VDD. VDDK tied to VDD internally with 18Ω.
4260f
8
LTC4260
U
U
W
FU CTIO AL DIAGRA
UH ONLY
V
V
SENSE
DD
DDK
FB
18Ω
INTERNAL
POWER
GATE
CHARGE
PUMP
AND
–
3.5V
+
20mV TO
50mV
UVS
OVS
CS
SOURCE
UV
GATE
+
+
UV
–
DRIVER
–
+
FOLDBACK
2V
+
–
OV
+
GN/UH ONLY
OV
3.5V
–
PWRGD
FET ON
PG
3.5V
–
1.235V
+
RESET
RST
GPIO
–
+
–
INTV
CC
GP
LOGIC
1.8V
BOARD
PRESENT
1.235V
10µA
+
–
BP
BD_PRST
0.2V
+
–
INTV
CC
TM1
100µA
ON
+
–
TIMER
ONS
ON
2µA
1.235V
+
–
V
DD
TM2
INTV
CC
5.5V
GEN
1.235V
V
–
+
DD
V
UVLO
DD
UVLO1
+
–
7.45V
UVLO2
V
CC
UVLO
3.8V
V
DD
– SENSE
SDAI
8
5
ADIN
SDAO
A/D CONVERTER
SOURCE
2
I C
SCL
2
ALERT
I C ADDR
1 OF 27
EXPOSED
PAD
GND
ADR0 ADR1 ADR2
4260 BD
UH ONLY
4260f
9
LTC4260
W U
W
TI I G DIAGRA
SDAI/SDAO
t
SP
t
t
SU,STA
t
SU, DAT
t
t
BUF
HD, DATO,
HD, DATI
t
HD, STA
t
SU, STO
t
SP
4260 TD01
SCL
t
HD, STA
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
U
OPERATIO
TheFunctionalDiagramdisplaysthemainfunctionalareas
of this device. The LTC4260 is designed to turn a board’s
supply voltage on and off in a controlled manner, allowing
the board to be safely inserted or removed from a live
backplane.Duringnormaloperation,thechargepumpand
gate driver turn on the external N-channel pass FET’s gate
to pass power to the load. The gate driver uses a charge
pump that derives its power from the SOURCE pin. When
the SOURCE pin is at ground, the charge pump is powered
fromaninternal12VsupplyderivedfromVDD. Thisresults
in a 200µA current load on the SOURCE pin when the gate
is up. Also included in the gate driver is an internal 15V
gate-to-source clamp.
0.2V (comparator TM1) which tells the logic that the pass
transistor has cooled and it is safe to turn it on again.
The output voltage is monitored using the FB pin and the
PG comparator to determine if the power is available for
the load. The power good condition is signalled by the
GPIO pin using an open-drain pull-down transistor. The
GPIO pin can also be used as a general purpose input (GP
comparator) or output pin.
The Functional Diagram shows the monitoring blocks of
the LTC4260. The group of comparators on the left side
includes the UV, OV, RST, BP and ON comparators. These
comparators are used to determine if the external condi-
tions are valid prior to turning on the FET. But first the two
undervoltage lockout circuits UVLO1 and UVLO2 must
validate the input supply and the internally generated 5.5V
supply(INTVCC)andgeneratethepowerupinitializationto
the logic circuits.
Thecurrentsense(CS)amplifiermonitorstheloadcurrent
using the difference between the VDD and SENSE pin
voltage. The CS amplifier limits the current in the load by
reducing the GATE-to-SOURCE voltage in an active con-
trol loop. The CS amplifier requires 100µA input bias
current from both the VDD and the SENSE pins.
Included in the LTC4260 is an 8-bit A/D converter. The
converter has a 3-input mux to select between the ADIN
pin, the SOURCE pin and the VDD – SENSE voltage.
A short circuit on the output to ground causes significant
power dissipation during active current limiting. To limit
thispower,thefoldbackamplifierreducesthecurrentlimit
value from 50mV to 20mV (referred to the VDD minus
SENSE voltage) in a linear manner as the FB pin drops
below 2V (see Typical Performance curves).
An I2C interface is provided to read the A/D registers. It
also allows the host to poll the device and determine if
faults have occurred. If the ALERT line is used as an
interrupt, the host can respond to a fault in real time. The
typical SDA line is divided into an SDAI (input) and SDAO
(output).Thissimplifiesapplicationsusinganoptoisolator
driven directly from the SDAO output. The I2C device
addressisdecodedusingtheADR0,ADR1andADR2pins.
Theseinputshavethreestateseachthatdecodeintoatotal
of 27 device addresses.
If an overcurrent condition persists, the TIMER pin ramps
up with a 100µA current source until the pin voltage
exceeds 1.2V (comparator TM2). This indicates to the
logic that it is time to turn off the pass FET to prevent
overheating. At this point the TIMER pin ramps down
usingthe2µAcurrentsourceuntilthevoltagedropsbelow
4260f
10
LTC4260
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APPLICATIO S I FOR ATIO
U
cleared and the control registers are set or cleared as
described in the register section.
The typical LTC4260 application is in a high availability
system that uses a positive voltage supply to distribute
power to individual cards. The device measures card
voltages and currents and records past and present fault
conditions.ThesystemquerieseachLTC4260overtheI2C
periodically and reads the stored information.
After the power-on-reset pulse, the LTC4260 will go
through the following turn-on sequence. First, the UV and
OV pins must indicate that the input power is within the
acceptable range and the BD_PRST pin must be pulled
low. All of these conditions must be satisfied for duration
of 100ms to ensure that any contact bounce during
insertion has ended.
The basic LTC4260 application circuit is shown in Fig-
ure 1. External component selection is discussed in detail
in the Design Example section.
When these initial conditions are satisfied, the ON pin is
checked.Ifitishigh,theexternalswitchturnson.Ifitislow,
theexternalswitchturnsonwhentheONpinisbroughthigh
or if a serial bus turn-on command is received.
Turn-On Sequence
The power supply on a board is controlled by placing an
external N-channel pass transistor (Q1) in the power path.
Notethatsenseresistor(RS)detectscurrentandcapacitor
C1 controls the GATE slew rate. Resistor R6 compensates
the current control loop while R5 prevents high frequency
oscillations in Q1. Resistors R1, R2 and R3 provide
undervoltage and overvoltage sensing.
The switch is turned on by charging up the GATE with a
18µA current source (Figure 2). The voltage at the GATE
pin rises with a slope equal to 18µA/C1 and the supply
inrush current is set at:
CL
C1
Several conditions must be present before the external
switch can be turned on. First the external supply VDD
must exceed its undervoltage lockout level. Next the
internally generated supply INTVCC must cross its 4.5V
undervoltage threshold. This generates a 60µs to 120µs
power-on-reset pulse. During reset the fault registers are
IINRUSH
=
•18µA
WhentheGATEvoltagereachestheFETthresholdvoltage,
the switch begins to turn on and the SOURCE voltage
follows the GATE voltage as it increases.
R
Q1
FDB3632
S
0.010Ω
V
V
OUT
48V
IN
48V
+
R7
43.5k
1%
C
L
R1
Z1*
330µF
49.9k
R6
R5
10Ω
SMBT70A
1%
100k
R8
3.57k
1%
R4
100k
C
F
C1
6.8nF
24
0.1µF
R2
1.74k
1%
4
2
1
23
UV V
OV
ON
SDAI
SDA0
SCL
SENSE GATE
SOURCE
DD
R3
2.67k
1%
5
7
9
10
8
11
18
13
FB
ADIN
GPIO
20
14
12
LTC4260GN
SDA
SCL
BD_PRST
TIMER
GND
ALERT
ALERT
C
INTV
CC
T
ADR0 ADR1 ADR2
68nF
19
15
16
NC
17
6
4260 F01
GND
C3
0.1µF
*DIODES, INC
BACKPLANE PLUG-IN
CARD
Figure 1. 5A, 48V Card Resident Application
4260f
11
LTC4260
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APPLICATIO S I FOR ATIO
V
DD
+ 13V
GATE
Overcurrent Fault
The LTC4260 features an adjustable current limit with
foldback that protects against short circuits or excessive
load current. To protect against excessive power dissipa-
tion in the switch during active current limit, the available
current is reduced as a function of the output voltage
sensed by the FB pin. The device also features a variable
overcurrent response time. A graph in the Typical Perfor-
mance curves shows the delay from a voltage step at the
SENSE pin until the GATE voltage starts falling, as a
function of overdrive.
SLOPE = 18µA/C1
V
V
DD
OUT
4260 F02
t
1
t
2
Figure 2. Supply Turn-On
Anovercurrentfaultoccurswhenthecurrentlimitcircuitry
hasbeenengagedforlongerthanthetime-outdelaysetby
the TIMER pin. Current limiting begins when the current
sense voltage between the VDD and SENSE pins reaches
20mVto50mV(dependingonthefoldback). TheGATEpin
is then brought down with a 600mA GATE-to-SOURCE
current. The voltage on the GATE is regulated in order to
limit the current sense voltage to less than 50mV. At this
point, a circuit breaker time delay starts by charging the
externaltimingcapacitorfromtheTIMERpinwitha100µA
pull-up current. If the TIMER pin reaches its 1.2V thresh-
old, the external switch turns off (with a 1mA current from
GATE to ground). The overcurrent present bit, C2, and the
overcurrent fault bit, D2, are set at this time.
As the SOURCE voltage rises, so will the FB pin which is
monitoring it. If the voltage across the current sense
resistor RS gets too high, the inrush current will then be
limited by the internal current limit circuitry. Once the FB
pin crosses its 3.5V threshold, the GPIO pin, in its default
configuration, will cease to pull low and indicate that the
power is now good.
Turn-Off Sequence
The switch can be turned off by a variety of conditions. A
normal turn-off is initiated by the ON pin going low or a
serial bus turn-off command. Additionally, several fault
conditions will turn off the switch. These include an input
overvoltage (OV pin), input undervoltage (UV pin), over-
current circuit breaker (SENSE pin) or BD_PRST going
high. Writing a logic one into the UV, OV or overcurrent
fault bits will also turn off the switch if their autoretry bits
are set to false.
The circuit breaker time delay is given by:
tCB = CT • 12 [ms/µF]
After the switch is turned off, the TIMER pin begins
discharging the timing capacitor with a 2µA pull-down
current. When the TIMER pin reaches its 0.2V threshold,
the overcurrent present bit, C2, is cleared, and the switch
will be allowed to turn on again if the overcurrent fault has
been cleared. However, if the overcurrent autoretry bit,
A2, has been set then the switch turns on again automati-
cally (without resetting the overcurrent fault). Use a mini-
mum value of 0.1nF for CT.
Normally the switch is turned off with a 1mA current
pulling down the GATE pin to ground. With the switch
turnedoff, theSOURCEvoltagedropsandwhentheFBpin
crosses below its threshold, GPIO pulls low to indicate
that the output power is no longer good.
If the VDD pin falls below 7.5V for greater than 5µs or
INTVCC drops below 3.8V for greater than 1µs, a fast
shutdown of the switch is initiated. The GATE pin is pulled
down with a 600mA current to the SOURCE pin.
ThewaveforminFigure3showshowtheoutputlatchesoff
following a short circuit. The drop across the sense
resistor is held at 20mV as the timer ramps up.
4260f
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LTC4260
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APPLICATIO S I FOR ATIO
U
undervoltage autoretry has been disabled by clearing bit
A1. When power is applied to the device, if UV is below its
3.12V threshold after INTVCC crosses its 4.5V undervolt-
agelockoutthreshold, anundervoltagefaultwillbelogged
in the fault register.
V
OUT
50V/DIV
I
OUT
5A/DIV
∆V
GATE
10V/DIV
Board Present Change of State
TIMER
2V/DIV
Whenever the BD_PRST pin toggles, bit D4 is set to
indicate a change of state. When the BD_PRST pin goes
high, indicatingboardremoval, theswitchturnsoffimme-
diately (with a 1mA current from GATE to ground) and
clears the board present bit, C4. If the BD_PRST pin is
pulledlow,indicatingaboardinsertion,allfaultbitsexcept
D4 will be cleared and the board present bit, C4, is set. If
the BD_PRST pin remains low for 100ms the state of the
ON pin will be captured in the FET On Control bit A3. This
turns the switch on if the ON pin is tied high. There is an
internal 10µA pull-up current source on the BD_PRST pin.
4260 F03
100µs/DIV
Figure 3. Short-Circuit Waveforms
During a short circuit, if the current limit sense voltage
exceeds 150mV, the active current limit enters a high
current protection mode that immediately turns off the
output transistor by pulling the GATE-to-SOURCE voltage
to zero. Current in the output transistor drops from tens of
amps to zero in a few hundred nanoseconds. The input
voltage will drop during the high current and then spike
upwards due to parasitic inductances when the FET shuts
off (see Supply Transients). Following this event, the part
may turn on again after a delay (typically the 100ms
normal turn-on delay if the input voltage drops below the
UVLO threshold) and enters active current limit before
shutting off.
If the system shuts down due to a fault, it may be desirable
to restart the system simply by removing and reinserting
a load card. In cases where the LTC4260 and the switch
reside on a backplane or midplane and the load resides on
a plug-in card, the BD_PRST pin can be used to detect
when the plug-in card is removed (see Figure 4). Once the
plug-in card is reinserted the fault register is cleared
(except for D4). After 100ms the state of the ON pin is
latched into bit A3 of the control register. At this point the
system will start up again.
Overvoltage Fault
An overvoltage fault occurs when the OV pin rises above
its 3.5V threshold. This shuts off the switch immediately
(with a 1mA current from GATE to ground) and sets the
overvoltage present bit, C0, and the overvoltage fault bit
D0. If the OV pin subsequently falls back below the
threshold for 100ms, the switch will be allowed to turn on
again unless the overvoltage autoretry has been disabled
by clearing bit A0.
If a connection sense on the plug-in card is driving the
BD_PRST pin, the insertion or removal of the card may
cause the pin voltage to bounce. This will result in
clearing the fault register when the card is removed. The
pin can be debounced using a filter capacitor, CBD_PRST
,
on the BD_PRST pin as shown in Figure 4. The filter time
is given by:
Undervoltage Fault
tFILTER = CBD_PRST • 123 [ms/µF]
An undervoltage fault occurs when the UV pin falls below
its 3.12V threshold. This turns off the switch immediately
(with a 1mA current from GATE to ground) and sets the
undervoltagepresentbit,C1,andtheundervoltagefaultbit
D1. If the UV pin subsequently rises above the threshold
for 100ms, the switch will turn on again unless the
FET Short Fault
A FET short fault will be reported if the data converter
measures a current sense voltage greater than or equal to
2mVwhiletheFETisturnedoff.ThisconditionsetstheFET
short present bit, C5, and the FET short fault bit D5.
4260f
13
LTC4260
W U U
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APPLICATIO S I FOR ATIO
OUT
23
Once the ALERT signal has been released for one fault, it
will not be pulled low again until the FAULT register
indicates a different fault has occurred or the original fault
is cleared and it occurs again. Note that this means
repeated or continuing faults will not generate alerts until
the associated FAULT register bit has been cleared.
LTC4260
SOURCE
10µA
BD_PRST 14
+
–
LOAD
C
BD_PRST
1.235V
Resetting Faults
GND
6
Faults are reset with any of the following conditions. First,
a serial bus command writing zeros to the FAULT register
Dwillcleartheassociatedfaults.Second,theentireFAULT
register is cleared when the switch is turned off by either
the ON pin or bit A3 going from high to low, or if the UV pin
is brought below its 1.23V reset threshold, or if INTVCC
falls below its 3.8V undervoltage lockout threshold. Fi-
nally, when BD_PRST is brought from high to low, only
FAULT bits D0-D3 and D5 are cleared, the bit D4 that
indicatesaBD_PRSTchangeofstatewillbeset.Faultsthat
are still present (as indicated in the STATUS Register C)
cannot be cleared.
4260 F04
CONNECTOR
PLUG-IN
CARD
MOTHERBOARD
Figure 4. Plug-In Card Insertion/Removal
Power Bad Fault
ApowerbadfaultwillbereportediftheFBpindropsbelow
its 3.41V threshold while the FET is on. This pulls the GPIO
pin low immediately, when configured as PWRGD, and
setsthepowerbadpresentbit, C3, andthepowerbadfault
bit D3. A circuit will prevent a power bad fault if the GATE-
to-SOURCE voltage is low, eliminating false power bad
faults during power-up or power-down. If the FB pin
subsequentlyrisesbackabovethethreshold, theGPIOpin
will return to a high impedance state and bit C3 will be
cleared.
The FAULT register will not be cleared when autoretrying.
When autoretry is disabled the existence of a D0, D1 or D2
fault keeps the switch off. As soon as the fault is cleared,
the switch will turn on. If autoretry is enabled, then a high
valueinC0, C1orC2willholdtheswitchoffandtheFAULT
register is ignored. Subsequently, when the C0, C1 and C2
bits are cleared, the switch is allowed to turn on again
Fault Alerts
When any of the fault bits in FAULT register D are set, an
optional I2C bus alert can be generated by setting the
appropriate bit in the ALERT register B. This allows only
selected faults to generate alerts. At power-up the default
state is to not alert on faults. If an alert is enabled, the
corresponding fault will cause the ALERT pin to pull low.
After the bus master controller broadcasts the Alert Re-
sponse Address, the LTC4260 responds with its address
ontheSDAlineandreleasesALERTasshowninFigure11.
If there is a collision between two LTC4260s responding
with their addresses simultaneously, then the device with
the lower address wins arbitration and responds first. The
ALERT line will also be released if the device is addressed
by the bus master.
Data Converter
The LTC4260 incorporates an 8-bit data converter that
continuously monitors three different voltages. The
SOURCE pin uses a 1/40 resistive divider to monitor a full-
scale voltage of 102.4V with 0.4V resolution (divider
converts102.4Vto2.56V).TheADINpinismonitoredwith
a 2.56V full scale and 10mV resolution, and the voltage
between the VDD and SENSE pins is monitored with a
76.8mV full scale and 300µV resolution.
TheresultsfromeachconversionarestoredinregistersE,
F and G and are updated 10 times per second. Setting
CONTROLregisterbitA5invokesatestmodethathaltsthe
data converter updates so that registers E, F and G can be
written to and read from for software testing.
4260f
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LTC4260
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APPLICATIO S I FOR ATIO
U
Gate Pin Voltage
Supply Transient Protection
A curve of gate drive vs VDD is shown in the Typical
Performance curves. At the minimum input supply volt-
age of 8.5V, the minimum gate drive voltage is 4.5V.
Whentheinputsupplyvoltageishigherthan20V,thegate
drive is at least 10V and a regular N-FET can be used. In
applications over a 8.5V to 20V range, a logic level N-FET
must be used to maintain adequate gate enhancement.
The GATE pin is clamped at a typical value of 15V above
the SOURCE pin.
The LTC4260 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 100V. However,
spikes above 100V may damage the part. During a short-
circuit condition, the large change in currents flowing
through the power supply traces can cause inductive
voltage spikes which could exceed 100V. To minimize the
spikes, the power trace inductance should be minimized
by using wider traces or heavier trace plating. Adding a
snubber circuit will dampen the voltage spikes. It is built
using a 100Ω resistor in series with a 0.1µF capacitor
betweenVDD andGND.Asurgesuppressor,Z1inFigure 1,
at the input will clamp the voltage spikes.
Configuring the GPIO Pin
Table3describesthepossiblestatesoftheGPIOpinusing
the control register bits A6 and A7. At power-up, the
defaultstateisfortheGPIOpintogohighimpedancewhen
power is good (FB pin greater than 3.5V). Other uses for
the GPIO pin are to pull down when power is good, a
general purpose output and a general purpose input.
Design Example
Asadesignexample, takethefollowingspecifications:VIN
= 48V, IMAX = 5A, IINRUSH = 1A, CL= 330µF, VUVON = 43V,
VUVOFF=38.5V,VOVOFF=70V,VPWRGDUP=46V,VPWRGDDN
= 45V and I2CADDRESS = 1010011. The selection of the
sense resistor, RS, is set by the overcurrent threshold of
50mV:
Compensating the Active Current Loop
The active current limit circuit is compensated using the
resistorR6andtheslewratecapacitorC1.ThevalueforC1
is calculated to limit the inrush current. The suggested
value for R6 is 100k. This value should work for most pass
FETs (Q1). If the gate capacitance of Q1 is very small then
the best method to compensate the loop is to add a ≈10nF
capacitor between the GATE and SOURCE terminals.
50mV 50mV
RS =
=
= 0.010Ω
IMAX
5A
The FET should be sized to handle the power dissipation
during the inrush charging of the output capacitor COUT
.
The method used to determine the power is the principle:
EC = Energy in CL= Energy in Q1
Thus:
Supply Transients
TheLTC4260isdesignedtoridethroughsupplytransients
caused by load steps. If there is a shorted load and the
parasitic inductance back to the supply is greater than
0.5µH, there is a chance that the supply could collapse
before the active current limit circuit brings down the
GATE pin. In this case the undervoltage monitors turn off
the pass FET. The undervoltage lockout circuit has a 5µs
filter time after VDD drops below 7.5V. The UV pin reacts
in 2µs to shut the GATE off, but it is recommended to add
afiltercapacitorCF topreventunwantedshutdowncaused
by short transient. Eventually either the UV pin or the
undervoltage lockout responds to bring the current under
control before the supply completely collapses.
EC = 1/2 CV2 = 1/2(0.33mF)(48V)2 = 0.38J
Calculate the time it takes to charge up COUT
:
CL • V
330µF • 48V
IN
tCHARGUP
=
=
= 16ms
I
1A
INRUSH
The average power dissipated in the FET:
EC 0.38J
PDISS
=
=
≅ 24W
tCHARGUP 16ms
4260f
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LTC4260
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APPLICATIO S I FOR ATIO
The SOA (safe operating area) curves of candidate FETs
must be evaluated to ensure that the heat capacity of the
package can stand 24W for 16ms. The SOA curves of the
Fairchild FDB3632 provide for 1A at 50V (50W) for 10ms,
satisfying the requirement.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is recommended. The minimum trace width for 1oz cop-
per foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. Using 0.03" per amp or wider is
recommended. Note that 1oz copper exhibits a sheet
resistance of about 530µΩ/ꢀ. Small resistances add up
quickly in high current applications. To improve noise
immunity, put the resistive divider to the UV, OV and FB
pins close to the device and keep traces to VDD and GND
short. It is also important to put C3, the bypass capacitor
for the INTVCC pin, as close as possible between INTVCC
and GND. A 0.1µF capacitor from the UV pin (and OV pin
through resistor R2) to GND also helps reject supply
noise. Figure 5 shows a layout that addresses these
issues. Note that a surge suppressor, Z1, is placed be-
tween supply and ground using wide traces.
The inrush current is set to 1A using C1:
IGATE(UP)
18µA
1A
C1= CL
= 0.33mF
= 5.9nF
I
INRUSH
Default values of R5 = 10Ω and R6 = 100k are chosen as
discussed previously.
The power dissipated in the FET during overcurrent must
be limited. The active current limit uses a timer to prevent
excessive energy dissipation in the FET. The worst-case
power occurs when the voltage versus current profile of
the foldback current limit is at the maximum. This occurs
when the current is 5A and the voltage is 1/2 of the 48V or
24V. See the Current Limit Sense Voltage vs FB Voltage in
the Typical Performance curves to view this profile. In
order to survive 120W, the FET SOA curve dictates the
maximum time at this power level. This particular FET
allows 300W at 1ms or less. Therefore, it is acceptable to
set the current limit timeout using CT to be 0.81ms:
V
IN
I
SENSE RESISTOR R
S
LOAD
SENSE
R1
R2
R3
V
DD
LTC4260
C
F
UV
Z1
OV
C3
GND
INTV
0.81ms
CC
CT =
= 68nF
FB
12 ms/µF
[
]
R
8
Note the minimum value for CT is 0.1nF.
Choose R1, R2, R3, R7 and R8 for the UV, OV and PG
threshold voltages:
V
OVRISING = 71.2V, VOVFALLING = 69.44V (using VOV(TH)
=
4260 F05
3.5V rising and 3.41V falling)
I
GND
LOAD
V
UVRISING = 43V, VUVFALLING = 38.5V, (using VUV(TH)
=
3.5V rising and 3.12V falling)
Figure 5. Recommended Layout for
R1, R2, R3, R8, CF, C3, Z1 and RS
VPGRISING = 46.14V, VPGFALLING = 45V, (using VFB = 3.5V
rising and 3.411V falling)
In addition a 0.1µF ceramic bypass capacitor is placed on
the INTVCC pin. The complete circuit is shown in Figure 1.
4260f
16
LTC4260
W U U
APPLICATIO S I FOR ATIO
U
Digital Interface
Acknowledge
The LTC4260 communicates with a bus master using a
2-wire interface compatible with the I2C bus and the
SMBus, an I2C extension for low power devices.
The acknowledge signal is used for handshaking between
the transmitter and the receiver to indicate that the last
byte of data was received. The transmitter always releases
the SDA line during the acknowledge clock pulse. When
the slave is the receiver, it must pull down the SDA line so
that it remains LOW during this pulse to acknowledge
receipt of the data. If the slave fails to acknowledge by
leavingSDAHIGH,thenthemastercanabortthetransmis-
sion by generating a STOP condition. When the master is
receiving data from the slave, the master must pull down
the SDA line during the clock pulse to indicate receipt of
the data. After the last byte has been received the master
will leave the SDA line HIGH (not acknowledge) and issue
a STOP condition to terminate the transmission.
The LTC4260 is a read-write slave device and supports
SMBus bus Read Byte, Write Byte, Read Word and Write
Word commands. The second word in a Read Word
command will be identical to the first word. The second
word in a Write Word command is ignored. The data
formats for these commands are shown in Figures 7 to10.
Using Optoisolators with SDA
The LTC4260 separates the SDA line into SDAI and SDAO.
If optoisolators are not used then tie SDAI and SDAO
together to construct a normal SDA line. When using
optoisolatorsconnecttheSDAItotheoutputoftheincom-
ing opto and connect the SDAO to the input of the out-
going opto (see Figure 13).
Write Protocol
The master begins communication with a START condi-
tion followed by the seven bit slave address and the R/W
bitsettozero. TheaddressedLTC4260acknowledgesthis
and then the master sends a command byte which indi-
cates which internal register the master wishes to write.
The LTC4260 acknowledges this and then latches the
lower three bits of the command byte into its internal
Register Address pointer. The master then delivers the
data byte and the LTC4260 acknowledges once more and
latches the data into its internal register. The transmission
is ended when the master sends a STOP condition. If the
mastercontinuessendingaseconddatabyte, asinaWrite
Word command, the second data byte will be acknowl-
edged by the LTC4260 but ignored.
START and STOP Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with a
START condition by transitioning SDA from high to low
while SCL is high. When the master has finished commu-
nicating with the slave, it issues a STOP condition by
transitioning SDA from low to high while SCL is high. The
bus is then free for another transmission.
I2C Device Addressing
Twenty-seven distinct bus address are configurable using
the three-state ADR0-ADR2 pins. Table 1 shows the
correspondence between pin states and addresses. Note
thataddressbitsB7andB6areinternallyconfiguredto10.
In addition, the LTC4260 will respond to two special
addresses. Address (1011 111)b is a mass write used to
writetoallLTC4260, regardlessoftheirindividualaddress
settings. Themasswritecanbemaskedbysettingregister
bit A4 to zero. Address (0001 100)b is the SMBus Alert
Response Address. If the LTC4260 is pulling low on the
ALERT pin, it will acknowledge this address using the
SMBus Alert Response Protocol.
Read Protocol
The master begins a read operation with a START condi-
tion followed by the seven bit slave address and the R/W
bitsettozero. TheaddressedLTC4260acknowledgesthis
and then the master sends a command byte that indicates
which internal register the master wishes to read. The
LTC4260 acknowledges this and then latches the lower
three bits of the command byte into its internal Register
Addresspointer.ThemasterthensendsarepeatedSTART
condition followed by the same seven bit address with the
4260f
17
LTC4260
W U U
U
APPLICATIO S I FOR ATIO
R/W bit now set to one. The LTC4260 acknowledges and
sends the contents of the requested register. The trans-
mission is ended when the master sends a STOP condi-
tion.Ifthemasteracknowledgesthetransmitteddatabyte,
as in a Read Word command, the LTC4260 will repeat the
requested register as the second data byte.
by the special Alert Response Address (0001 100)b with
the R/W bit set to one. Any LTC4260 that is pulling its
ALERT pin low will acknowledge and begin sending back
its individual slave address.
An arbitration scheme ensures that the LTC4260 with the
lowest address will have priority; all others will abort their
response. The successful responder will then release its
ALERT pin while any others will continue to hold their
ALERTpinslow.Pollingmayalsobeusedtosearchforany
LTC4260 that have detected faults. Any LTC4260 pulling
its ALERT pin low will also release it if it is individually
addressed during a read or write transaction.
Note that the Register Address pointer is not cleared at the
end of the transaction. Thus the Receive Byte protocol can
be used to repeatedly read a specific register.
Alert Response Protocol
The LTC4260 implements the SMBus Alert Response
ProtocolasshowninFigure11.Ifenabledtodosothrough
the ALERT register B, the LTC4260 will respond to faults
by pulling the ALERT pin low. Multiple LTC4260s can
share a common ALERT line and the protocol allows a
master to determine which LTC4260s are pulling the line
low. The master begins by sending a START bit followed
The ALERT signal will not be pulled low again until the
FAULT register indicates a different fault has occurred or
the original fault is cleared and it occurs again. Note that
this means repeated or continuing faults will not generate
alerts until the associated FAULT register bit has been
cleared.
SDA
SCL
a6 - a0
1 - 7
b7 - b0
b7 - b0
8
9
1 - 7
8
9
1 - 7
8
9
S
P
START
CONDITION
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
CONDITION
4260 F06
Figure 6. Data Transfer Over I2C or SMBus
4260f
18
LTC4260
W U U
APPLICATIO S I FOR ATIO
U
S
ADDRESS W A
COMMAND
A
0
DATA
b7:b0
A
0
P
1 0 a4:a0
0
0
X X X X X b2:b0
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
4260 F07
Figure 7. LTC4260 Serial Bus SDA Write Byte Protocol
S
ADDRESS W A
1 0 a4:a0
COMMAND
A
0
DATA
b7:b0
A
0
DATA
A
0
P
0
0
X X X X X b2:b0
X X X X X X X X
4260 F08
Figure 8. LTC4260 Serial Bus SDA Write Word Protocol
S
ADDRESS W A
1 0 a4:a0
COMMAND
A
0
S
ADDRESS
1 0 a4:a0
R
1
A
0
DATA
b7:b0
A
1
P
0
0
X X X X X b2:b0
4260 F09
Figure 9. LTC4260 Serial Bus SDA Read Byte Protocol
S
ADDRESS W A
1 0 a4:a0
COMMAND
A
0
S
ADDRESS
1 0 a4:a0
R
1
A
0
DATA
b7:b0
A
0
DATA
b7:b0
A
1
P
0
0
X X X X X b2:b0
4260 F10
Figure 10. LTC4260 Serial Bus SDA Read Word Protocol
ALERT
RESPONSE
ADDRESS
DEVICE
S
R
1
P
A
0
A
1
ADDRESS
0 0 0 1 1 0 0
1 0 a4:a0
4260 F11
Figure 11. LTC4260 Serial Bus SDA Alert Response Protocol
4260f
19
LTC4260
W U U
U
APPLICATIO S I FOR ATIO
Table 1. LTC4260 I2C Device Addressing
HEX DEVICE
LTC4260
ADDRESS PINS
DESCRIPTION
ADDRESS
BINARY DEVICE ADDRESS
h
6
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
3
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
2
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
R/W
0
ADR2
X
ADR1
X
ADR0
X
Mass Write
BE
19
Alert Response
1
X
X
X
0
1
80
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
NC
H
L
82
L
NC
NC
H
2
84
L
NC
NC
L
3
86
L
4
88
L
L
5
8A
8C
8E
L
H
H
6
L
L
NC
H
7
L
L
8
90
NC
NC
NC
NC
NC
NC
NC
NC
H
NC
H
L
9
92
NC
NC
H
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
94
NC
NC
L
96
98
L
9A
9C
9E
H
H
L
NC
H
L
A0
A2
A4
A6
A8
AA
AC
AE
B0
B2
B4
NC
H
L
H
NC
NC
H
H
NC
NC
L
H
H
L
H
H
H
H
L
NC
H
H
L
L
H
L
NC
H
H
L
H
L
4260f
20
LTC4260
W U U
APPLICATIO S I FOR ATIO
U
Table 2. LTC4260 Register Addresses and Contents
REGISTER
ADDRESS*
REGISTER
NAME
READ/WRITE
R/W
DESCRIPTION
Controls Whether the Part Retries After Faults, Set the Switch State
00h
CONTROL (A)
ALERT (B)
STATUS (C)
FAULT (D)
SENSE (E)
SOURCE (F)
ADIN (G)
01h
R/W
Controls Whether the ALERT Pin is Pulled Low After a Fault is Logged in the Fault Register
02h
R
System Status Information
Fault Log
03h
R/W
04h
R/W**
R/W**
R/W**
ADC Current Sense Voltage Data
ADC SOURCE Voltage Data
ADC ADIN Voltage Data
05h
06h, 07h
*Register address MSBs b7-b3 are ignored.
**Writable if bit A5 set.
Table 3. CONTROL Register A (00h)—Read/Write
BIT
NAME
OPERATION
Configures Behavior of GPIO Pin
A7:6
GPIO Configure
FUNCTION
A6
0
A7 GPIO PIN
Power Good (Default)
Power Bad
0
1
0
1
GPIO = C3
GPIO = C3
GPIO = B6
GPIO = Hi-Z
0
General Purpose Output
General Purpose Input
1
1
A5
A4
A3
A2
A1
A0
Test Mode Enable
Test Mode Halts ADC Operation and Enables Writes to ADC Registers
1 = Enable Test Mode, 0 = Disable Test Mode (Default)
Mass Write Enable
FET On Control
Enables Mass Write Using Address (1011 111)b
1 = Enable Mass Write (Default), 0 = Disable Mass Write
Turns FET On and Off
1 = Turn FET On, 0 = Turn FET Off. Defaults to ON Pin State at End of Debounce Delay
Overcurrent Autoretry
Undervoltage Autoretry
Overvoltage Autoretry
Enables Autoretry After an Overcurrent Fault
1 = Retry Enabled, 0 = Retry Disabled (Default)
Enables Autoretry After an Undervoltage Fault
1 = Retry Enabled (Default), 0 = Retry Disabled
Enables Autoretry After an Overvoltage Fault
1 = Retry Enabled (Default), 0 = Retry Disabled
4260f
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LTC4260
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U
APPLICATIO S I FOR ATIO
Table 4. ALERT Register B (01h)—Read/Write
BIT
B7
B6
B5
NAME
OPERATION
Reserved
Not Used
GPIO Output
FET Short Alert
Output Data Bit to GPIO Pin When Configured as Output. Defaults to 0
Enables Alert for FET Short Condition
1 = Enable Alert, 0 = Disable Alert (Default)
B4
B3
B2
B1
B0
BD_PRST State Change Alert
Power Bad Alert
Enables Alert When BD_PRST Changes State
1 = Enable Alert, 0 = Disable Alert (Default)
Enables Alert when Output Power is Bad
1 = Enable Alert, 0 = Disable Alert (Default)
Overcurrent Alert
Enables Alert for Overcurrent Condition
1 = Enable Alert, 0 = Disable Alert (Default)
Undervoltage Alert
Overvoltage Alert
Enables Alert for Undervoltage Condition
1 = Enable Alert, 0 = Disable Alert (Default)
Enables Alert for Overvoltage Condition
1 = Enable Alert, 0 = Disable Alert (Default)
Table 5. STATUS Register C (02h)—Read Only
BIT
NAME
OPERATION
C7
FET On
Indicates State of FET
1 = FET On, 0 = FET Off
C6
C5
C4
C3
C2
C1
C0
GPIO Input
State of the GPIO Pin
1 = GPIO High, 0 = GPIO Low
FET Short Present
Board Present
Power Bad
Indicates Potential FET Short if Current Sense Voltage Exceeds 2mV While FET is Off
1 = FET is Shorted, 0 = FET is Not Shorted
Indicates if a Board is Present When BD_PRST is Low
1 = BD_PRST Pin Low, 0 = BD_PRST Pin High
Indicates Power is Bad When FB is Low
1 = FB Low, 0 = FB High
Overcurrent
Undervoltage
Overvoltage
Indicates Overcurrent Condition During Cool Down Cycle
1 = Overcurrent, 0 = Not Overcurrent
Indicates Input Undervoltage When UV is Low
1 = UV Low, 0 = UV High
Indicates Input Overvoltage When OV is High
1 = OV High, 0 = OV Low
4260f
22
LTC4260
W U U
APPLICATIO S I FOR ATIO
U
Table 6. FAULT Register D (03h)—Read/Write
BIT
D7:6
D5
NAME
OPERATION
Reserved
FET Short Fault Occurred
Indicates Potential FET Short was Detected When Measured Current Sense Voltage Exceeded 2mV
While FET was Off
1 = FET was Shorted, 0 = FET is Good
D4
D3
D2
D1
D0
Board Present Changes State
Power Bad Fault Occurred
Overcurrent Fault Occurred
Undervoltage Fault Occurred
Overvoltage Fault Occurred
Indicates that a Board was Inserted or Extracted When BD_PRST Changed State
1 = BD_PRST Changed State, 0 = BD_PRST Unchanged
Indicates Power was Bad When FB Went Low
1 = FB was Low, 0 = FB was High
Indicates Overcurrent Fault Occurred
1 = Overcurrent Fault Occurred, 0 = No Overcurrent Faults
Indicates Input Undervoltage Fault Occurred When UV Went Low
1 = UV was Low, 0 = UV was High
Indicates Input Overvoltage Fault Occurred When OV Went High
1 = OV was High, 0 = OV was Low
Table 7. SENSE Register E (04h)—Read/Write
BIT
NAME
OPERATION
E7:0
SENSE Voltage Data
V -SENSE Current Sense Voltage Data. 8-Bit Data with 300µV LSB and 76.8mV Full Scale
DD
Table 8. SOURCE Register F (05h)—Read/Write
BIT
NAME
OPERATION
F7:0
SOURCE Voltage Data
SOURCE Pin Voltage Data. 8-Bit Data with 400mV LSB and 102.4V Full Scale
Table 9. ADIN Register G (06h)—Read/Write
BIT
NAME
OPERATION
G7:0
ADIN Voltage Data
ADIN Pin Voltage Data. 8-Bit Data with 10mV LSB and 2.56V Full Scale
4260f
23
LTC4260
W U U
U
APPLICATIO S I FOR ATIO
R
Q1
Si7880DP
S
0.003Ω
V
IN
12V
+
R7
6.65k
1%
C
L
R1
5.76k
1%
1000µF
R5
10Ω
R6
100k
R8
C
F
2.94k
1%
C1
R2
1k
0.1µF
22nF
25V
1%
4
2
1
24
23
R4
100k
R3
2.05k
1%
UV V
SENSE GATE
SOURCE
DD
5
10
9
8
11
7
18
13
20
14
12
OV
FB
SDAO
SDAI
SCL
ALERT
ON
ADIN
GPIO
SDA
SCL
ALERT
LTC4260GN
BD_PRST
TIMER
INTV ADR0 ADR1 ADR2 GND
C
CC
T
0.68µF
19
15
16
NC
17
6
C3
0.1µF
4260 F12
GND
BACKPLANE PLUG-IN
CARD
Figure 12. 12A, 12V Card Resident Application
R
Q1
FDB3632
S
0.01Ω
GND
OUTPUT
R1
49.9k
1%
INTV
CC
R5
10Ω
C1
6.8nF
R10
3.4k
R9
10k
R6
100k
3.3V
R2
1.74k
1%
R7
43.7k
1%
4
2
1
24
23
SOURCE
C
F
0.1µF
UV V
SENSE GATE
DD
R3
2.67k
1%
5
9
18
13
20
14
12
MOC207
OV
FB
R8
3.57k
1%
ADIN
GPIO
–48V
INTV
SDAI
SDA
LTC4260GN
CC
10
8
7
SDA0
SCL
C
L
R4
5.1k
BD_PRST
TIMER
330µF
100V
ON INTV ADR0 ADR1 ADR2 GND
CC
16
NC
17
6
19
15
C
INTV
CC
T
MOC207
68nF
C3
R12
10k
R13
3.4k
0.1µF
SCL
R14
1k
R15
100Ω
Q2
CMPTA42
MOC207
OPTIONAL 5V
C2
0.1µF
–48V
V
–48V
IN
–48V
4260 F13
BACKPLANE
PLUG-IN
CARD
Figure 13. 3A, –48V Card Resident Application
4260f
24
LTC4260
U
PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 14 13
.045 ±.005
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.254 MIN
.150 – .165
1
2
3
4
5
6
7
8
9 10 11 12
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015
(0.38
±
±
.004
0.10)
.0532 – .0688
(1.35 – 1.75)
× 45°
.004 – .0098
(0.102 – 0.249)
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN24 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
4260f
25
LTC4260
U
PACKAGE DESCRIPTIO
SW Package
24-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
.050 BSC .045 ±.005
.030 ±.005
TYP
.598 – .614
(15.190 – 15.600)
NOTE 4
N
24 23 22 21 20 19 18
16 15 14 13
17
N
.325 ±.005
.420
MIN
.394 – .419
(10.007 – 10.643)
NOTE 3
1
2
3
N/2
N/2
RECOMMENDED SOLDER PAD LAYOUT
.291 – .299
(7.391 – 7.595)
NOTE 4
2
3
5
7
8
9
10
1
4
6
11 12
.037 – .045
.093 – .104
.010 – .029
(0.940 – 1.143)
× 45°
(2.362 – 2.642)
(0.254 – 0.737)
.005
(0.127)
RAD MIN
0° – 8° TYP
.050
(1.270)
BSC
.004 – .012
.009 – .013
(0.102 – 0.305)
NOTE 3
(0.229 – 0.330)
.014 – .019
.016 – .050
(0.356 – 0.482)
TYP
(0.406 – 1.270)
NOTE:
1. DIMENSIONS IN
INCHES
(MILLIMETERS)
S24 (WIDE) 0502
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
4260f
26
LTC4260
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
(4 SIDES)
R = 0.115
TYP
0.75 ± 0.05
5.00 ± 0.10
(4 SIDES)
31 32
0.00 – 0.05
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ± 0.10
(4-SIDES)
(UH) QFN 0603
0.200 REF
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
4260f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC4260
U
TYPICAL APPLICATIO
3A, 48V Backplane Resident Application with Insertion Activated Turn-On
0.01Ω
FDB3632
V
V
OUT
48V
IN
48V
SMAT70B
43.5k
3.57k
49.9k
10Ω
100k
6.8nF
100k
0.1µF
1.74k
2.67k
UV V
OV
ON
SDAI
SDA0
SCL
SENSE GATE
LTC4260
SOURCE
FB
DD
LOAD
GPIO
BD_PRST
ADIN
1µF
TIMER
GND
ALERT
INTV
ADR0 ADR1 ADR2
CC
68nF
4260 TA03
NC
0.1µF
BACKPLANE PLUG-IN
CARD
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group
4260f
LT/TP 0904 1K • PRINTED IN USA
28 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2004
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