LTC4261_15_技术文档

LTC4261/LTC4261-2

Negative Voltage

Hot Swap Controllers with

2

ADC and I C Monitoring

FEATURES

DESCRIPTION

Allows Safe Insertion into Live –48V Backplanes

The LTC^®4261/LTC4261-2 negative voltage Hot Swap^TM

controllersallowaboardtobesafelyinsertedandremoved

n

10-Bit ADC Monitors Current and Voltages

2

n

I C/SMBus Interface or Single-Wire Broadcast Mode from a live backplane. Using an external N-channel pass

n

Floating Topology Allows Very High Voltage

Operation

Independently Adjustable Inrush and Overcurrent

Limits

Controlled Soft-Start Inrush

Adjustable UV/OV Thresholds and Hysteresis

Sequenced Power Good Outputs with Delays

Adjustable Power Good Input Timeout

Programmable Latchoff or Auto-Retry After Faults

Alerts Host After Faults

Available in 28-Lead Narrow SSOP and 24-Lead

(4mm × 5mm) QFN Packages

transistor, the board supply voltage can be ramped at an

adjustable rate. The devices feature independently adjust-

able inrush current and overcurrent limits to minimize

stresses on the pass transistor during start-up, input

step and output short conditions. The LTC4261 defaults

to latch-off while the LTC4261-2 defaults to auto-retry on

overcurrent faults.

An I²C interface and onboard 10-bit ADC allow monitoring

of board current, voltage and fault status. A single-wire

broadcast mode is available to simplify the interface by

eliminating two optoisolators.

n

The controllers have additional features to interrupt the

host when a fault has occurred, notify when output power

is good, detect insertion of a board and turn off the pass

transistor if an external supply monitor fails to indicate

power good within a timeout period.

APPLICATIONS

n

AdvancedTCA Systems

n

Telecom Infrastructure

n

–48V Distributed Power Systems

Power Monitors

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot

Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of

their respective owners. Protected by U.S. Patents, including 7382167, 8194379, 8230151.

n

TYPICAL APPLICATION

–48V/200W Hot Swap Controller with I²C and ADC

–48V RTN

Start-Up Behavior

453k

1%

4 × 1k IN SERIES

1/4W EACH

V

–48V INPUT

50V/DIV

IN

UV = 38.5V

UVL

UVH

ADIN2

OV

PGI

ALERT

SDAO

SDAI

SCL

ADIN

PGIO

PG

UV RELEASE

AT 43V

16.9k

1%

V

OV = 72.3V

OV RELEASE

AT 71V

OUT

+

LTC4261CGN

+

330µF

100V

50V/DIV

V

IN

INTV

ON

CC

LOAD

ON

SENSE

0.5A/DIV

11.8k

1%

SS

TMR EN V

SENSE GATE DRAIN RAMP

EE

–

V

IN

1M

1k

PG

50V/DIV

47nF

1µF

220nF

47nF

10Ω

42612 TA01b

10nF

100V

5%

0.1µF

10ms/DIV

0.008Ω

1%

V

OUT

–48V INPUT

42612 TA01

Q1

IRF1310NS

42612fd

1

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

(Notes 1, 2)

ABSOLUTE MAXIMUM RATINGS

V (Note 3).......................................... –0.3V to 10.65V

Operating Ambient Temperature Range

IN

Drain (Note 4) .......................................... –0.3V to 3.5V

PGI, ON, ALERT, SDAO, SDAI, SCL, ADIN, ADIN2,

OV, SENSE, ADR1, ADR0, FLTIN, TMR,

LTC4261C ................................................ 0°C to 70°C

LTC4261I .............................................–40°C to 85°C

Storage Temperature Range

SS, RAMP Voltages ...................–0.3V to INTV + 0.3V

SSOP ................................................. –65°C to 150°C

QFN.................................................... –65°C to 125°C

Lead Temperature (Soldering, 10 sec)

CC

UVL, UVH, EN ............................................ –0.3V to 10V

GATE Voltage .................................. –0.3V to V + 0.3V

IN

PG, PGIO Voltages .................................... –0.3V to 80V

SSOP Only........................................................300°C

Supply Voltage (INTV ).......................... –0.3V to 5.5V

CC

PIN CONFIGURATION

TOP VIEW

1

2

PGIO

PG

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PGI

ON

TOP VIEW

3

EN

ALERT

SDAO

SDAI

SCL

24 23 22 21 20

4

ADR1

ADR0

ADIN

FLTIN

SDAO

SDAI

SCL

1

2

3

4

5

6

7

19

18

17

16

15

14

13

EN

5

ADR1

ADR0

ADIN

6

7

INTV

CC

INTV

25

CC

8

V

IN

UVL

UVH

ADIN2

OV

UVL

V

IN

9

TMR

SS

UVH

OV

TMR

SS

10

11

12

13

14

8

9

10 11 12

RAMP

NC

DRAIN

GATE

V

EE

UFD PACKAGE

24-LEAD (4mm × 5mm) PLASTIC QFN

= 125°C, θ = 45°C/W

SENSE

T

JMAX

JA

EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

GN PACKAGE

28-LEAD PLASTIC SSOP

= 125°C, θ = 85°C/W

T

JMAX

JA

ORDER INFORMATION

LEAD FREE FINISH

LTC4261CGN#PBF

LTC4261IGN#PBF

TAPE AND REEL

PART MARKING*

LTC4261CGN

LTC4261IGN

LTC4261IGN-2

4261

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC4261CGN#TRPBF

LTC4261IGN#TRPBF

LTC4261CGN-2#TRPBF

LTC4261IGN-2#TRPBF

LTC4261CUFD#TRPBF

LTC4261IUFD#TRPBF

28-Lead Plastic SSOP

0°C to 70°C

28-Lead Plastic SSOP

–40°C to 85°C

0°C to 70°C

LTC4261CGN-2#PBF

LTC4261IGN-2#PBF

LTC4261CUFD#PBF

LTC4261IUFD#PBF

LTC4261CUFD-2#PBF

LTC4261IUFD-2#PBF

28-Lead Plastic SSOP

–40°C to 85°C

0°C to 70°C

24-Lead (4mm × 5mm) Plastic QFN

4261

–40°C to 85°C

0°C to 70°C

LTC4261CUFD-2#TRPBF 42612

LTC4261IUFD-2#TRPBF 42612

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

42612fd

2

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at I_IN= 5mA, T_A= 25°C. (Note 2)

SYMBOL

General

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Shunt Regulator Voltage at V

I

= 5mA

10.65

11.2

370

2

11.8

600

5

V

mV

mA

V

Z

IN

Shunt Regulator Load Regulation

= 5mA to 25mA

DV

IN

Z

I

IN

V

Supply Current

V

= V – 0.3V

IN

Z

V

Undervoltage Lockout Threshold

Undervoltage Lockout Hysteresis

Rising

8.5

0.3

9

9.5

1

IN(UVLO)

0.7

5

V

DV

IN(UVLO)

INTV

Internal Regulator Voltage

I

= 1mA to 20mA, I = 25mA

4.75

5.25

V

CC

LOAD

IN

Gate Drive

l

V

GATE Pin Output High Voltage

GATE Pin Pull-Up Current

GATE Turn-Off Current

V

= 10.65V

10

–7.5

45

10.25

–11.5

90

10.5

–15.5

120

140

1.5

V

µA

mA

µs

GATEH

IN

I

= 4V

GATE(UP)

GATE(OFF)

GATE

= 400mV, V

= 4V

GATE

SENSE

Gate Off, V

= 4V

60

110

0.5

GATE

t

SENSE High to Current Limit

Propagation Delay

V

SENSE

V

SENSE

= 100mV, GATE Open

= 300mV, GATE Open

PHL(SENSE)

0.2

0.5

µs

GATE Off Propagation Delay

Input High (OV, EN, PGI), Input Low (ON, UVL),

GATE Open

0.2

0.5

µs

PHL(GATE)

l

t

I

Circuit Breaker Gate Off Delay

RAMP Pin Current

V

< 2V, GATE Open

GATE

440

–18

2.43

–7

530

–20

2.56

–10

12

620

–22

2.69

–13

20

µs

µA

V

PHLCB

V

SS

= 2.56V

RAMP

V

SS Pin Clamp Voltage

SS Pin Pull-Up Current

SS Pin Pull-Down Current

SS

I

V

= 0V

µA

mA

SS(UP)

SS(DN)

SS

= 2.56V

6

SS

Input Pins

l

V

UVH Threshold Voltage

UVL Threshold Voltage

V

Rising

Falling

LTC4261C

LTC4261I

2.534

2.522

2.56

2.586

2.598

V

UVH(TH)

UVH

l

V

LTC4261C

LTC4261I

2.263

2.254

2.291

2.319

2.328

UVL(TH)

UVL

l

Built-In UV Hysteresis

UVH and UVL Tied Together

256

269

15

282

mV

V

DV

UV(HYST)

UVH, UVL Minimum Hysteresis

UVL Reset Threshold Voltage

UVL Reset Hysteresis

dV

UV

l

V

V Falling

UVL

1.12

1.21

60

1.30

UVLR(TH)

mV

V

DV

UVLR(HYST)

l

V

OV Pin Threshold Voltage

V

OV

Rising

LTC4261C

LTC4261I

1.744

1.735

1.770

1.796

1.805

OV(TH)

l

OV Pin Hysteresis

18

45

37.5

50

62

55

2

mV

V

DV

OV(HYST)

Current Limit Sense Voltage Threshold

ON, EN, PGI, FLTIN Threshold Voltage

ON, EN, PGI, FLTIN Hysteresis

PGIO Pin Input Threshold Voltage

PGIO Pin Input Hysteresis

V

– V

SENSE

EE

SENSE

V

ON, EN, PGI, FLTIN Falling or Rising

0.8

1.4

170

1.25

100

0

INPUT(TH)

mV

V

DV

INPUT(HYST)

PGIO(TH)

l

V

PGIO

Rising

1.10

1.40

2

mV

µA

DV

PGIO(HYST)

I

ON, EN, UVH, UVL, OV, SENSE, PGI,

FLTIN Input Current

ON, EN, UVH, UVL, OV, SENSE, PGI, FLTIN = 3V

INPUT

42612fd

3

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at I_IN= 5mA, T_A= 25°C. (Note 2)

SYMBOL

Timer

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

TMR Pin High Threshold

TMR Pin Low Threshold

TMR Pin Pull-Up Current

V

Rising

Falling

2.43

40

2.56

75

2.69

110

–13

V

mV

µA

TMR(H)

TMR(L)

TMR

V

TMR

I

Turn-On and Auto-Retry (Except OC) Delays,

= 0.2V

–7

–10

TMR(UP)

V

TMR

l

Power Good, PGI Check and OC Auto-Retry

Delays, V = 0.2V

–3.5

6

–5

12

5

–6.5

20

7

µA

mA

µA

TMR

I

TMR Pin Pull-Down Current

Delays Except PGI Check or OC Auto-Retry,

= 2.56V

TMR(DN)

V

TMR

PGI Check and OC Auto-Retry Delays,

= 2.56V

3

V

TRM

Output Pins

l

V

PG, PGIO Pins Output Low

I

, I = 3mA

PG PGIO

0.8

0.15

1.6

0.4

V

PWRGD

I

, I

= 500µA

PG PGIO

l

I

PG, PGIO Pins Leakage Current

PG, PGIO = 80V

0

10

µA

PWRGD

ADC

l

Resolution (No Missing Codes)

Integral Nonlinearity

(Note 5)

10

Bits

LSB

mV

V

INL

SENSE

0.5

2.5

1.25

1.75

1.25

65.2

2.606

1.8

ADIN2/OV, ADIN

SENSE

0.25

V

OS

Offset Error

ADIN2/OV, ADIN

SENSE

Full-Scale Voltage

Total Unadjused Error

62.8

64

ADIN2/OV, ADIN

SENSE

2.514

2.560

%

ADIN2/OV, ADIN

1.6

%

Conversion Rate

5.5

2

7.3

10

0

9

Hz

R

ADIN

ADIN, ADIN2 Pins Input Resistance

ADIN, ADIN2 Pins Input Current

ADIN, ADIN2 = 1.28V

ADIN, ADIN2 = 2.56V

MW

µA

I

2

ADIN

2

I C Interface

l

V

ADR0, ADR1 Input High Threshold

INTV

CC

– 0.3

V

ADR(H)

CC

– 0.8

– 0.5

l

V

ADR0, ADR1 Input Low Threshold

ADR0, ADR1 Input Current

0.3

0.5

0.8

V

µA

V

ADR(L)

I

ADR0, ADR1 = 0V, 5V

80

ADR(IN)

ADR0, ADR1 = 0.8V, (INTV – 0.8V)

10

CC

V

ALERT Pin Output Low Voltage

SDAO Pin Output Low Voltage

SDAO, ALERT Input Current

SDAI, SCL Input Threshold

SDAI, SCL Input Current

I

= 4mA

0.2

0

0.4

5

ALERT(OL)

ALERT

V

SDAO(OL)

SDAO

I

SDAO, ALERT = 5V

µA

V

SDAO,ALERT(IN)

V

1.6

1.8

0

2

SDAI,SCL(TH)

SDAI,SCL(IN)

I

SDAI, SCL = 5V

2

µA

42612fd

4

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at I_IN= 5mA, T_A= 25°C. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

2

I C Interface Timing (Note 5)

f

t

Maximum SCL Clock Frequency

Minimum SCL Low Period

Minimum SCL High Period

400

kHz

µs

SCL(MAX)

LOW

0.65

50

1.3

600

1.3

ns

HIGH

Minimum Bus Free Time Between Stop/

Start Condition

0.12

µs

BUF(MIN)

t

Minimum Hold Time After (Repeated)

Start Condition

140

30

600

ns

HD,STA(MIN)

SU,STA(MIN)

Minimum Repeated Start Condition

Set-Up Time

t

Minimum Stop Condition Set-Up Time

Minimum Data Hold Time Input

Minimum Data Hold Time Output

Minimum Data Set-Up Time Input

30

–100

600

30

600

0

ns

SU,STO(MIN)

HD,DATI(MIN)

HD,DATO(MIN)

SU,DAT(MIN)

SP(MAX)

300

900

100

250

Maximum Suppressed Spike Pulse

Width

50

25

110

t

Stuck-Bus Reset Time

SCL or SDAI Held Low

SDAI Tied to SDAO

66

5

ms

pF

RST

C

SCL,SDA Input Capacitance

10

X

The pin can be safely tied to higher voltages through a resistor that limits

the current below 50mA.

Note 4: An internal clamp limits the DRAIN pin to a minimum of 3.5V.

Driving this pin to voltages beyond the clamp may damage the part. The

pin can be safely tied to higher voltages through a resistor that limits the

current below 2mA.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive, all voltages are referenced to

device GND (V ) unless otherwise specified.

EE

Note 5: Guaranteed by design and not subject to test.

Note 3: An internal shunt regulator limits the V pin to a minimum of

IN

10.65V. Driving this pin to voltages beyond 10.65V may damage the part.

42612fd

5

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

I_IN= 5mA, T_A= 25°C, unless otherwise noted

TYPICAL PERFORMANCE CHARACTERISTICS

Shunt Regulator Voltage

vs Input Current

Shunt Regulator Voltage

vs Temperature

INTV_CCvs Load Current

30

25

11.35

11.30

11.25

11.20

5.06

I

IN

= 25mA

I

= 5mA

IN

5.04

5.02

5.00

4.98

4.96

20

15

10

5

11.15

11.10

0

10.8

11

11.2

11.4

11.6

11.8

–50

–25

0

25

50

75

100

10

LOAD CURRENT (mA)

0

5

15

20

SHUNT REGULATOR VOLTAGE AT V (V)

TEMPERATURE (°C)

IN

42612 G01

42612 G02

42612 G03

GATE Output High Voltage

vs Temperature

GATE Pull-Up Current

vs GATE Voltage

GATE Turn-Off Current

vs SENSE Voltage

10.5

10.4

10.3

10.2

10.1

10.0

–12

–10

–8

–6

–4

–2

0

100

10

1

V

= 4V

V

= 10.65V

GATE

IN

–50

0

25

50

75

100

200

300

400

500

–25

0

4

6

8

10

12

0

2

TEMPERATURE (°C)

GATE VOLTAGE (V)

V

(mV)

SENSE

42612 G06

42612 G04

42612 G05

UVH Threshold vs Temperature

UVL Threshold vs Temperature

RAMP Pin Current vs Temperature

–22.0

–21.5

–21.0

–20.5

–20.0

–19.5

–19.0

2.575

2.570

2.565

2.560

2.555

2.550

2.545

2.305

2.300

2.295

2.290

2.285

2.280

2.275

–50

0

25

50

75

100

–50

0

25

50

75

100

–50

0

25

50

75

100

–25

TEMPERATURE (°C)

42612 G07

42612 G08

42612 G09

42612fd

6

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

I_IN= 5mA, T_A= 25°C, unless otherwise noted

TYPICAL PERFORMANCE CHARACTERISTICS

Current Limit Voltage

vs Temperature

52.0

OV Hysteresis vs Temperature

OV Threshold vs Temperature

1.785

1.780

1.775

1.770

1.765

1.760

1.755

50

45

40

35

51.5

51.0

50.5

50.0

49.5

49.0

30

25

–50

0

25

50

75

100

–50

0

25

50

75

100

–50

0

25

50

75

100

–25

TEMPERATURE (°C)

42612 G10

42612 G11

42612 G12

Current Limit Propagation Delay

(t_PHL(SENSE)) vs V_SENSE

PG, PGIO Output Low

vs Load Current

ADC Total Unadjusted Error

vs Code (ADIN Pin)

1000

1.0

0.5

6

5

C

= 1pF

GATE

T

= 85°C

A

4

3

T

= 25°C

A

0

2

1

0

–0.5

–1.0

T

= –40°C

A

100

0

100

200

V

300

400

500

512

768

0

1024

0

2

4

6

8

10

256

LOAD CURRENT (mA)

(mV)

CODE

SENSE

42612 G13

42612 G15

42612 G14

ADC Full-Scale Error vs

Temperature (ADIN Pin)

ADC INL vs Code (ADIN Pin)

ADC DNL vs Code (ADIN Pin)

3

2

1.0

0.5

1.0

0.5

1

0

–1

–2

–3

–0.5

–1.0

–0.5

–1.0

–50

0

25

50

75

100

–25

512

768

512

768

0

1024

0

1024

256

TEMPERATURE (°C)

CODE

42612 G16

42612 G17

42612 G18

42612fd

7

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

PIN FUNCTIONS ^(SSOP/QFN)

ADIN (Pin 23/Pin 16): ADC Input. A voltage between 0V

GATE (Pin 15/Pin 10): N-Channel FET Gate Drive Output.

This pin is pulled up by an internal current source I

and 2.56V applied to this pin is measured by the on-chip

GATE

ADC. Tie to V if unused.

(11.5µA when the SS pin reaches its clamping voltage).

GATE stays low until V and INTV cross the UVLO

EE

IN

CC

ADIN2 (Pin 10/NA): Second ADC Input. Not available on

QFN package.

thresholds, UV and OV conditions are satisified and an

adjustable timer delay expires. During turn-off, caused by

ADR0, ADR1 (Pins 24, 25/Pins 17, 18): Serial Bus Ad-

faults or undervoltage lockout (V or INTV ), a 110mA

IN

CC

dress Inputs. Tying these pins to V , OPEN or INTV

pull-down current between GATE and V is activated.

EE

CC

EE

configures one of nine possible addresses. See Table 1

INTV (Pin 7/Pin 4): Low Voltage (5V) Supply Output.

CC

in Applications Information.

This is the output of the internal linear regulator with an

internal UVLO threshold of 4.25V. This voltage powers up

the data converter and logic control circuitry. Bypass this

ALERT(Pin3/Pin24):FaultAlertOutput. Open-drainlogic

outputthatpullstoV whenafaultoccurstoalertthehost

EE

controller. A fault alert is enabled by the ALERT register.

pin with a 0.1µF capacitor to V .

EE

See Applications Information. Connect to V if unused.

EE

ON (Pin 2/Pin 23): On Control Input. A rising edge turns

on the external N-channel FET while a falling edge turns it

off. This pin is also used to configure the state of the FET

ON register bit D3 in the CONTROL register (and hence

the external FET) at power-up. For example if the ON pin

is tied high, then the register bit D3 goes high one timer

cycleafterpower-up.Likewise,iftheONpinistiedlow,then

the device remains off after power-up until the register bit

DRAIN (Pin 16/Pin 11): Drain Sense Input. Connect an

external1Mresistorbetweenthispinandthedrainterminal

(V ) of the N-channel FET. When the DRAIN pin volt-

OUT

age is less than 1.77V and the GATE pin voltage is above

V – 1.2V the power good outputs are asserted after a

Z

delay. The voltage at this pin is internally clamped to 4V.

EN(Pin26/Pin19):DeviceEnableInput.Pulllowtoenable

the N-channel FET to turn-on after a start-up debounce

delay set by the TMR pin. When this pin is pulled high, the

FET is off. Transitions on this pin will be recorded in the

FAULT register. A high-to-low transition activates the logic

to read the state of the ON pin and clear faults. Requires

external pull-up. Debouncing with an external capacitor

is recommended when used to monitor board present.

2

D3 is set high using the I C bus. A high-to-low transition

on this pin clears faults.

OV (Pin 11/Pin 7): Overvoltage Detection Input. Connect

this pin to an external resistive divider from V . If the

EE

voltage at the pin rises above 1.77V, the N-channel FET is

turned off. The overvoltage condition does not affect the

status of the power good outputs. On the QFN package,

this pin is also measured by the on-chip ADC. Connect

Connect to V if unused.

EE

to V if unused.

EE

Exposed Pad (Pin 25, QFN Only): Exposed Pad may be

left open or connected to device ground (V ).

PG(Pin27/Pin20):PowerGoodStatusOutput.Thisopen-

EE

drain pin pulls low and stays latched a timer delay after

FLTIN (Pin 22/NA): General Purpose Fault Input. If this

pin pulls low, the FAULT register bit B7 is latched to “1.”

This pin is used to sense an external fault condition and

its status does not affect the FET control functions of the

LTC4261. Not available on the QFN package. Connect to

the FET is on (when GATE reaches V – 1.2V and DRAIN

Z

is within 1.77V of V ). The power good output is reset

EE

in all GATE pull-down events except an overvoltage fault.

Connect to V if unused.

EE

INTV if unused.

CC

42612fd

8

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

(SSOP/QFN)

PIN FUNCTIONS

PGI (Pin 1/Pin 22): Power Good Input. This pin along with

the PGI check timer serves as a watchdog to monitor the

power-up of the DC/DC converter. The PGI pin must be low

before the PGI check timer expires, otherwise the GATE

pin pulls down and stays latched and a power bad fault

is logged into the FAULT register. The PGI timer is started

after the second power good is latched and its delay is

equal to four times the start-up debounce delay. Connect

SDAO (Pin 4/Pin 1): Serial Bus Data Output. Open-drain

output used for sending data back to the master controller

or acknowledging a write operation. An external pull-up

resistororcurrentsourceisrequired. Normallyconnected

to the input of the outgoing optoisolator that outputs to

the SDA port of the master controller. In the single-wire

broadcast mode, the SDAO pin sends out selected data

that is encoded with an internal clock.

to V if unused.

EE

SENSE (Pin 14/Pin 9): Current Limit Sense Input. Load

PGIO (Pin 28/Pin 21): General Purpose Input/Output.

Open-drain logic output and logic input. Defaults to pull

low a timer delay after the PG pin goes low to indicate a

secondpowergoodoutput.ConfigureaccordingtoTable6.

current through the external sense resistor (R ) is moni-

S

tored and controlled by an active current limit amplifier

to 50mV/R . Once V

reaches 50mV, a circuit breaker

S

SENSE

timerstartsandturnsoffthepasstransistorafter530µs.In

the event of a catastrophic short circuit, if V crosses

SENSE

RAMP (Pin 18/Pin 12): Inrush Current Ramp Control

250mV, a fast response comparator immediately pulls the

Pin. The inrush current is set by placing a capacitor (C )

R

GATEpindowntocontrolthecurrentoftheN-channelFET.

between the RAMP pin and the drain terminal of the FET.

At start-up, the GATE pin is pulled up by I

until the

SS (Pin 19/Pin 13): Soft-Start Input. Connect a capaci-

tor to this pin to control the rate of rise of inrush current

(dI/dt) during start-up. An internal 10µA current source

GATE(UP)

pass transistor begins to turn on. A current, I

, then

RAMP

flows through C to ramp down the output voltage V

.

R

OUT

The value of I

is controlled by the SS pin voltage.

charging the external soft-start capacitor (C ) creates

RAMP

SS

When the SS pin reaches its clamp voltage (2.56V), I

= 20µA. The ramp rate of V

set the inrush current: I

a voltage ramp. This voltage is converted to a current to

charge the GATE pin up and to ramp the output voltage

down. The SS pin is internally clamped to 2.56V limiting

RAMP

and the load capacitor C

= (C /C ) • I

OUT

L

.

INRUSH

L

R

RAMP

I

to 11.5µA and I

to 20µA. If the SS capacitor

GATE(UP)

RAMP

SCL (Pin 6/Pin 3): Serial Bus Clock Input. Data at the

SDAI pin is shifted in and data at the SDAO pin is shifted

out on rising edges of SCL. This is a high impedance pin

that is generally connected to the output of the incoming

optoisolatordrivenbytheSCLportofthemastercontroller.

An external pull-up resistor or current source is required.

is absent, the SS pin ramps from 0V to 2.56V in 220µs.

TMR(Pin20/Pin14):DelayTimerInput.Connectacapaci-

tor (C ) to this pin to create timing delays at start-up,

TMR

when power good outputs pull down, during PGI check

and when auto-retrying after faults (except overvoltage

fault). Internal pull-up currents of 10µA and 5µA and

pull-down currents of 5µA and 12mA configure the delay

Pull up to INTV if unused.

CC

SDAI (Pin 5/Pin 2): Serial Bus Data Input. This is a high

impedance input pin used for shifting in command bits,

data bits and SDAO acknowledge bits. An external pull-up

resistororcurrentsourceisrequired. Normallyconnected

to the output of the incoming optoisolator that is driven

by the SDA port of the master controller. If the master

controller separates SDAI and SDAO, data read at SDAO

periods as multiples of a nominal delay of 256ms • C

/

TMR

µF. Delays for start-up and auto-retry following undervolt-

age or power bad fault are the same as the nominal delay.

Delays for sequenced power good outputs are twice of the

nominal delay. Delays for PGI check and auto-retry fol-

lowing overcurrent fault are four times the nominal delay.

2

needs to be echoed back to SDAI for proper I C commu-

nication. Pull up to INTV if unused.

CC

42612fd

9

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

PIN FUNCTIONS ^(SSOP/QFN)

V

(Pin 13/Pin 8): Negative Supply Voltage Input and

UVH (Pin 9/Pin 6): Undervoltage High Level Input. Con-

EE

Device Ground. Connect this pin to the negative side of

nect this pin to an external resistive divider from V . If

EE

the power supply.

the voltage at the UVH pin rises above 2.56V the pass

transistor is allowed to turn on. A small capacitor at this

pinpreventstransientsandswitchingnoisefromaffecting

V (Pin 21/Pin 15): Positive Supply Input. Connect this

IN

pin to the positive supply through a dropping resistor. An

the UVH threshold. Connect to INTV if unused.

CC

internal shunt regulator clamps V at 11.2V. An internal

IN

undervoltage lockout (UVLO) circuit holds the GATE low

UVL (Pin 8/Pin 5): Undervoltage Low Level Input. Con-

nect this pin to an external resistive divider from V . If

until V is above 9V. Bypass this pin with a 1µF capacitor

IN

EE

to V .

the voltage at the UVL pin drops below 2.291V, the pass

transistor is turned off and the power good outputs go

high impedance. Pulling this pin below 1.21V resets faults

and allows the pass transistor to turn back on. Connect

EE

to INTV if unused.

CC

42612fd

10

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

BLOCK DIAGRAM

V

IN

INTV

CC

V

IN

11.2V

UVLO:

IN

INTV = 4.25V

CC

V

–

CC

V

= 9V

+

GATE

20µA

V

5V

EE

SSA

RAMP

SENSE

+

–

10µA

50nA

3pF

V

EE

–

+

ACL

50mV

+

V

EE

–

V

EE

+

–

2.56V

SS

V

EE

40¥

V

SENSE

SSC

PG

UVL

UVH

OV

UVL

UVH

+

–

2.291V

2.56V

V

EE

PGIO

+

–

V

OV

EE

FLTIN

PGI

+

–

LOGIC

1.77V

5µA

EN

5µA

ON

–

+

DRAIN

DC

TMR

+

–

1.77V

4V

2.56V

5µA

–

+

GC

V

EE

V

– 1.2V

Z

12mA

GATE

2

ADR0

ADR1

SCL

8

I C DEVICE ADDRESS

SINGLE-WIRE ENABLE

= 2.56V

A0

•

DECODER

MUX

SDAI

A7

A8

SDAO

2

I C

INTERFACE

V

REF

ADIN

10

ALERT

ADIN2/OV

10-BIT ADC

REGISTER

V

SENSE

V

EE

42612 BD

42612fd

11

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

OPERATION

The LTC4261/LTC4261-2 are designed to turn a board’s

supply voltage on and off in a controlled manner, allowing

theboardtobesafelyinsertedorremovedfromalive–48V

backplane.Thedevicesalsofeatureanonboard10-bitADC

and I²C interface that allows monitoring board current,

voltages and faults. The main functional circuits of the

LTC4261/LTC4261-2 are illustrated in the Block Diagram.

The DRAIN and the GATE voltages are monitored to de-

termine if power is available for the load. Two power good

signals are sequenced on the PG pin (first power good

signal)andthePGIOpin(secondpowergoodsignal),each

with a debounce delay that is twice the start-up delay. The

PGIO pin can also be used as a general purpose input or

output. The PGI pin serves as a watchdog to monitor the

output of the DC/DC module. If the module output fails to

come up, the LTC4261/LTC4261-2 shut down.

In normal operation after a start-up debounce delay, the

GATE pin turns on the external N-channel FET passing

power to the load. The GATE pin is powered by a shunt

regulated 11.2V supply on the V_INpin that is derived

from –48V RTN through a dropping resistor. The turn-on

sequence starts by pulling the SS pin up. The voltage at

the SS pin is converted to a current, I_GATE(UP), pulling the

GATE up. When the pass FET starts to turn on and charge

the load capacitor, the inrush current flowing through the

FET is a function of the capacitor at RAMP (C_R), the load

capacitor (C_L) and the ramp current (I_RAMP) that flows

from the RAMP pin to C_R:

The TMR pin generates delays for initial start-up, auto-

retry following a fault, power good outputs and PGI check.

The logic circuits a re powered by an internally generated

5V supply (available on the INTV_CCpin). Prior to turning

on the pass FET, both V_INand INTV_CCvoltages must ex-

ceed their undervoltage lockout thresholds. In addition,

the control inputs UVH, UVL, OV, EN, ON and PGI are

monitored by comparators. The FET is held off until all

start-up conditions are met.

A10-bitanalog-to-digitalconverter(ADC)isincludedinthe

LTC4261/LTC4261-2. The ADC measures SENSE resistor

voltage as well as voltage at the ADIN2/OV (SSOP/QFN)

andADINpins.Theresultsarestoredinon-boardregisters.

C_L

C_R

I

= I_RAMP•

INRUSH

I_RAMPand I_GATE(UP)are approximately proportional to

the SS pin voltage and are limited to 20µA and 11.5µA,

respectivelywhenSSreachesitsclampingvoltage(2.56V).

An I²C interface is provided to read the ADCdata registers.

It also allows the host to poll the device and determine if a

faulthasoccurred.IftheALERTlineisusedasaninterrupt,

the host can respond to a fault in real time. The SDA line

is divided into SDAI (input) and SDAO (output) to facili-

tate opto coupling with the system host. Two three-state

pins, ADR0 and ADR1, are used to decode eight device

addresses. The interface can also be configured through

the ADR0 and ADR1 pins for a single-wire broadcast

mode, sending ADC data and faults status through the

SDAO pin to the host without clocking the SCL line. This

single-wire, one-way communication simplifies system

design by eliminating two optocouplers on SCL and SDAI

that are required by an I²C interface.

TheACLamplifierisusedforovercurrentandshort-circuit

protection.ItmonitorstheloadcurrentthroughtheSENSE

pin voltage and a sense resistor R_S. In an overcurrent

condition, the ACL amplifier limits the current to 50mV/

R_Sby pulling down GATE in an active servo loop. After a

530µs timeout, the ACL amplifier turns off the pass FET.

In the event of a catastrophic short circuit, when V_SENSE

crosses 250mV, a fast response comparator immediately

pulls the GATE pin down.

42612fd

12

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

The LTC4261/LTC4261-2 are ideally suited for –48V

distributed power systems and AdvancedTCA systems.

A basic 200W application circuit using the LTC4261 is

shown in Figure 1. A more complete application circuit

with AdvancedTCA connections is shown in Figure 2.

Input Power Supply

Power for the LTC4261/LTC4261-2 is derived from the

–48V RTN through an external current limiting resistor

(R ) to the V pin. An internal shunt regulator clamps

IN

–48V RTN

R

IN

R3

453k

1%

4 × 1k IN SERIES

1/4W EACH

7

21

8

9

22

1

6

5

4

INTV

V

IN

CC

UVL

UVH

ADIN2

OV

SS

TMR

EN

FLTIN

PGI

SCL

SDAI

SDAO

ALERT

UV = 38.5V

R2

16.9k

1%

UV RELEASE

AT 43V

10

11

19

20

26

2

+

C

L

OV = 72.3V

+

330µF

100V

V

IN

OV RELEASE

AT 71V

3

LTC4261CGN

MODULE2

+

ON

V

IN

PGIO 28 PWRGD2

–

IN

MODULE1

ON

ADR1

ADRO

25

24

27 PWRGD1

PG

23

ON

V

–

ADIN

IN

V

SENSE GATE DRAIN RAMP

EE

13

14

15

16

18

C

UV

100nF

IN

SS

220nF

1µF

R

10Ω

R

1M

R

1k

C

47nF

G

D

F

G

R1

11.8k

1%

C

VCC

0.1µF

TMR

47nF

C

R

C

F

10nF

100V

5%

R

S

33nF

0.008Ω

1%

V

OUT

–48V INPUT

R10

10k 1%

R11

402k 1%

Q1

IRF1310NS

42612 F01

Figure 1. –48V/200W Hot Swap Controller Using LTC4261 with Current,

Input Voltage and V_DSMonitoring (5.6A Current Limit, 0.66A Inrush)

MBRM5100

10A

RTN A

A

MBRM5100

10A

R3

412k

1%

RTN B

UV TURN OFF = 34.2V

UV RELEASE = 37.5V

OV TURN OFF = 74.8V

OV RELEASE = 73.2V

R12

10k

Q9

2N5401

ENABLE A

ENABLE B

R13

10k

R

604Ω

1%

H

Q10

2N5401

8

9

UVL

UVH

ADIN2

OV

SS

TMR

EN

R2

19.1k

1%

R10

R11

R14

R15

100k

10

11

19

20

26

2

100k 100k

100k

1N4148

×2

C

UV

100nF

LTC4261CGN

ON

ADR1

ADR0

25

24

V

SENSE GATE DRAIN RAMP

EE

13

C

SS

330nF

14

15

16

18

R1

10.5k

1%

R

1k

C

47nF

G

D

F

G

C

R16

100k

TMR

330nF

V

10Ω

1M

EE

LTC4354

C

R

C

EN

1µF

C

33nF

F

7A

10nF

100V

5%

HZS5C1

R

S

–48V A

–48V B

0.008Ω

5%

B

42612 F02a

Q1

IRF1310NS

BACKPLANE

PLUG-IN

CARD

Figure 2a. 200W AdvancedTCA Hot Swap Controller with Input/Output Monitoring

and Power Good Watchdog Using LTC4261 in I²C Mode (Part One)

42612fd

13

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

RTN

the voltage at V to 11.2V (V ) and provides power to the

IN

Z

GATE driver. The data converter and logic control circuits

are powered by an internal linear regulator that derives

5V from the 11.2V supply. The 5V output is available at

100Ω

V

OR

CC

IN

BCP56

INTV

10.5V OR 4.3V

42612 F03

the INTV pin for driving external circuits (up to 20mA

CC

Figure 3. NPN Buffer Relieves R_INof Excessive Dissipation

when Supplying External Loads

load current).

Bypass capacitors of 1µF and 0.1µF are recommended

Initial Start-Up and Inrush Control

at V and INTV , respectively. R should be chosen to

IN

CC

IN

accommodate the maximum supply current requirement

SeveralconditionsmustbesatisfiedbeforetheFETturn-on

of the LTC4261/LTC4261-2 (5mA) plus the supply current

sequence is started. First the voltage at V must exceed

IN

required by any external devices driven by the V and

IN

its 9V undervoltage lockout level. Next the internal supply

INTV pins at the minimum intended operation voltage.

CC

INTV must cross its 4.25V undervoltage lockout level.

CC

This generates a 100µs to 160µs power-on-reset pulse

during which the FAULT register bits are cleared and the

CONTROL register bits are set or cleared as described in

the register section. After the power-on-reset pulse, the

voltages at the UVH, UVL and OV pins must satisfy UVH

> 2.56V, UVL > 2.291V and OV < 1.77V to indicate that

the input power is within the acceptable range and the EN

pin must be pulled low. All the above conditions must be

satisfiedthroughoutthedurationofthestart-updebounce

V_48V(MIN)– V_Z(MAX)

R_IN≤

I_IN(MAX)+ I_EXTERNAL

The maximum power dissipation in the resistor is:

2

)

V

_48V(MAX)– V_Z(MIN)

(

P_MAX

=

R_IN

If the power dissipation is too high for a single resistor,

use multiple resistors in series or supply external loads

from a separate NPN buffer as illustrated in Figure 3.

delaythatissetbyanexternalcapacitor(C

)connected

TMR

to the TMR pin. C

is charged with a pull-up current of

TMR

–48V RTN OUTPUT

A

R17

R18

100k

1%

R4

20k

OUTPUT

100k

SENSE

R

1%

SUPPLY

IN

8 × 240Ω IN SERIES

MONITOR

+

Q11

2N5401

Q12

2N5401

V

IN

1/4W EACH

5V

+

V

OUT

V

IN

V

OUT

DD

R21

1k

LUCENT

LTC2900

LUCENT

FLTR100V10

MOC207

Q8

JW050A1-E

R19

2.49k

1%

R20

2.49k

1%

RST

GND

C

IN

1µF

VCC

0.1µF

ON/OFF

R6

R7A

10k

R7B

10k

R7

–

100k

V

OUT

CASE

IN

OUT

CASE

V

EE

V

EE

V

OUT

–

R8

7.5k

R9

5.1k

EE

V

7

21

23

ADIN

IN

22

1

6

INTV

V

IN

CC

FLTIN

PGI

SCL

V

OUT

EE

5V

5

C

L

SDAI

R22

1k

R23

1k

R24

5.1k

4000µF

+

100V

Q5

28

27

Q6

Q7

LTC4261CGN

PGIO

PG

0V TRANSIENT

RESEVOIR

CAPACITOR

V

CC

ANODE

CC

ANODE

CATHODE

V

O

V

O

V

DD

SCL

SDA

4

3

CATHODE

GND

MOC207

SDAO

ALERT

GND

Q3

Q4

MICRO-

CONTROLLER

PS9113

V

CC

ANODE

CC

ANODE

V

EE

R

L

V

O

ALERT RST

CATHODE V

GND

CATHODE

GND

OUT

R

L

HCPL-0300

6N139

343Ω

V

MBRM5100

OUT

7 × 2.4k, 0805

EACH 28.7W

42612 F02b

B

Figure 2b. 200W AdvancedTCA Hot Swap Controller with Input/Output Monitoring

and Power Good Watchdog Using LTC4261 in I²C Mode (Part Two)

42612fd

14

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

10µA until the voltage at TMR reaches 2.56V. C

is then

During board insertion and input power step, an internal

TMR

quickly discharged with a 12mA current. The initial delay

expires when TMR is brought below 75mV. The duration

of the start-up delay is given by:

clamp turns on to hold the RAMP pin low. Capacitor C

F

and resistor R suppress the noise at the RAMP pin. For

proper operation, R • C should not exceed 50µs. The

F

R

F

recommended value of C is 3 • C .

R

C_TMR

t_D= 256ms •

1µF

Power Good Monitors

Ifanyoftheaboveconditionsisviolatedbeforethestart-up

When V of the pass transistor falls below 1.77V and

DS

delay expires, C

is quickly discharged and the turn-on

GATE pulls above V – 1.2V, an internal power good signal

TMR

Z

sequenceisrestarted. Afteralltheconditionsarevalidated

throughout the start-up delay, the ON pin is then checked.

If it is high, the FET will be turned on. Otherwise, the FET

will be turned on when the ON pin is raised high or the FET

ON bit D3 in the CONTROL register is set to “1” through

is latched and a series of three delay cycles are started

as shown in Figure 4. When the first delay cycle with a

duration of 2t expires, the PG pin pulls low as a power

D

good signal to turn on the first module. When the second

delaycycle(2t )expires,thePGIOpinpullslowasapower

D

2

the I C interface.

good signal to turn on the second module. The third delay

cycle with a duration of 4t is for PGI check. Before the

D

The FET turn-on sequence follows by charging an external

third delay cycle expires, the PGI pin must be pulled low

by an external supply monitor (such as the LTC2900 in

Figure 2) to keep the FET on. Otherwise, the FET is turned

off and the power bad fault (PBAD) is logged in the FAULT

capacitor at the SS pin (C ) with a 10µA pull-up current

SS

and the voltage at SS (V ) is converted to a current

SS

(I

) of 11.5µA· V /2.56V for GATE pull-up. When

GATE(UP)

SS

the GATE reaches the FET threshold voltage, the inrush

register. The 2t timer delay is obtained by charging C

D

TMR

with a 12mA

currentstartstoflowthroughtheFETandacurrent(I

)

RAMP

with a 5µA current and discharging C

TMR

of20µA·V /2.56VflowsoutoftheRAMPpinandthrough

SS

current when TMR reaches 2.56V. For the 4t timer delay,

D

an external capacitor (C ) connected between RAMP and

R

the charging and discharging currents of C

are both

TMR

V

. The SS voltage is clamped to 2.56V, which cor-

OUT

5µA. The power good signals at PG and PGIO are reset in

responds to I

= 11.5µA and I

= 20µA. The

GATE(UP)

RAMP

all FET turn-off conditions except the overvoltage fault.

RAMP pin voltage is regulated at 1.1V and the ramp rate

of V

determines the inrush current:

OUT

Turn-Off Sequence and Auto-Retry

C_L

In any of the following conditions, the FET is turned off

by pulling down GATE with a 110mA current, and C_SS

and C_TMRare discharged with 12mA currents.

I_INRUSH= 20µA •

C_R

TheramprateofV determinesdI/dtoftheinrushcurrent:

SS

1. The ON pin is low or the ON bit in the CONTROL reg-

ister is set to 0.

dI_INRUSH

dt

C_L

1µF

= 20µA •

•

C_R256ms •C_SS

2. The EN pin is high.

If C is absent, an internal circuit pulls the SS pin from

SS

0V to 2.56V in about 220µs.

3. The voltage at UVL is lower than 2.291V and the volt-

age at UVH is lower than 2.56V (undervoltage fault).

When V

is ramped down to V , I

returns to

. Figure 4

OUT

EE GATE

the GATE pin and pulls the GATE up to V

4. The voltage at OV is higher than 1.77V (overvoltage

fault).

GATEH

illustrates the start-up sequence of the LTC4261/

LTC4261-2.

5. The voltage at V is lower than 9V (V undervoltage

IN

lockout).

42612fd

15

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

RTN_V

EE

UVH

PWRGD1

DELAY

PWRGD2

DELAY

PGI CHECK

DELAY

START-UP DELAY

TMR

SS

1x

2x

4x

V

– 1.2V

Z

GATE

V

OUT

1.77V

50mV

LOAD 1 + LOAD 2

LOAD 1

SENSE

INRUSH

LATCHED

INTERNAL

PWRGD

PWRGD1

READY

PG

PWRGD2

READY

PGIO

POWER BAD

PGI

NORMAL PGI

42612 F04

Figure 4. LTC4261 Turn-On Sequence

to 0, the FET is latched off upon the fault condition. If

the auto-retry bit is set to 1, after the fault condition is

cleared, a delay timer is started. After the timer expires,

the FET enters the auto-retry mode and GATE is pulled

up. The auto-retry delay following the undervoltage fault

6. The voltage at INTV is lower than 4.25V (INTV

CC

undervoltage lockout).

7. V

> 50mV and the condition lasts longer than

SENSE

530µs (overcurrent fault).

or the power bad fault has a duration of t . The auto-

8. The PGI pin is high when the PGI check timer expires

D

retry delay following the overcurrent fault has a duration

(power bad fault).

of 4t for extra cooling time. The auto-retry following the

D

For conditions 1, 2, 5, 6, after the condition is cleared,

the LTC4261/LTC4261-2 will automatically enter the FET

turn-on sequence as previously described.

overvoltage fault does not have a delay. The auto-retry

control bits and their defaults at power up are listed in

Table 6. Note that the LTC4261 defaults to latch-off while

the LTC4261-2 defaults to auto-retry following the over-

current fault.

For any of the fault conditions 3, 4, 7, 8, the FET off

mode is programmable by the corresponding auto-retry

bit in the CONTROL register. If the auto-retry bit is set

42612fd

16

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

EN and ON

and starting a 530µs circuit breaker timer and 250mV for

a fast GATE pull-down to limit peak current in the event

of a catastrophic short circuit or an input step.

Figure 5 shows a logic diagram for EN and ON as they

relate to GATE, ALERT and internal registers A4, A7, B4,

C4 and D3. Also affecting GATE is the status of UV, OV

and several other fault conditions. The EN and ON pins

have 0.8V to 2V logic thresholds relative to V with a

maximum input leakage current of 2µA.

In an overcurrent condition, when the voltage drop across

R exceeds 50mV, the current limit loop is engaged and

S

an internal 530µs circuit breaker timer is started. The

EE

current limit loop servos the GATE to maintain a constant

output current of 50mV/R . When the circuit breaker

S

Register bit A4 indicates the present state of EN, and B4

is set high whenever EN changes state. Rising and falling

edges at the ON pin set and clear FET-on control bit, D3.

Another path allows a falling edge at EN to latch a high

state at the ON pin (such as when ON is permanently

pulled high) into D3 after a time delay. Both B4 and D3

can be set or cleared directly by I C, and both are cleared

low whenever INTV drops below its UVLO threshold.

The condition of the GATE pin output is controlled by

register bit A7, which is the AND of A4, D3 and the ab-

sence of UV, OV and other faults.

timer expires, the FET is turned off by pulling GATE down

with a 110mA current, the capacitors at SS and TMR are

discharged and the power good signals are reset. At this

time, the overcurrent present bit A2 and the overcurrent

fault bit B2 are set, and the circuit breaker timer is reset.

2

After the FET is turned off, the overcurrent present bit

A2 is cleared. If the overcurrent auto-retry bit D2 has

been set, the FET will turn on again automatically after

CC

a cooling time of 4t . Otherwise, the FET will remain off

D

until the overcurrent fault bit B2 is reset. When the over-

current fault bit is reset (see Resetting Faults), the FET

Overcurrent Protection and Overcurrent Fault

is allowed to turn on again after a delay of 4t . The 4t

D

cooling time associated with the overcurrent fault will not

be interrupted by any other fault condition. See Figure 6

for operation of LTC4261/LTC4261-2 under overcurrent

condition followed by auto-retry.

The LTC4261/LTC4261-2 feature two levels of protec-

tion from short-circuit and overcurrent conditions. Load

current is monitored by the SENSE pin and resistor

R . There are two distinct thresholds for the voltage at

S

SENSE: 50mV for engaging the active current limit loop

ABSENCE OF UV/OV AND OTHER FAULTS

GATE ON

A4

A7

INTV UVLO

CC

CLR

STATE-CHANGE

DETECTOR

ALERT*

S

EN

Q

B4

C4

S

ALERT

Q

R/W

CLR

1 t

D

TIMER

DELAY

2

I C ALERT RESPONSE

READ ANY REGISTER

2

I C

ON

*B4 • C4 IS ONE OF SEVEN CONDITIONS

THAT CAN GENERATE AN ALERT OUTPUT.

SEE TABLE 5

R/W

CLR

S

R

EDGE

DETECTOR

42612 F05

D3

Q

INTV UVLO

CC

Figure 5. Logic Block Diagram of EN and ON Pins

42612fd

17

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

PWRGD1

DELAY

PWRGD2

DELAY

OC COOLING DELAY

TMR

2x

4x

SS

V

– 1.2V

Z

GATE

V

OUT

1.77V

50mV

530µs

SENSE

INRUSH

PG

PGIO

42612 F06

Figure 6. Overcurrent Fault and Auto-Retry

In the case of a low impedance short circuit on the load

side or an input step during battery replacement, current

overshoot is inevitable. A fast SENSE comparator with a

threshold of 250mV detects the overshoot and immedi-

ately pulls GATE low. Once the SENSE voltage drops to

50mV, the current limit loop takes over and servos the

current as previously described. If the short-circuit con-

dition lasts longer than 530µs, the FET is shut down and

the overcurrent fault is registered.

the current limit loop in the event of an input step. The

maximum value of the inrush current is given by:

45mV

R_S

I_INRUSH≤ 0.8 •

–I_LOAD

where the 0.8 factor is used as a worst case margin com-

bined with the minumum threshold (45mV).

The active current limit circuit is compensated using the

capacitor C with a series resistor R (10W) connected

G

Inthecaseofaninputstep,afteraninternalclamppullsthe

RAMP pin down to 1.1V, the inrush control circuit takes

over and the current limit loop is disengaged before the

circuitbreakertimerexpires.Fromthispointon,thedevice

between GATE and V , as shown in Figure 1. The sug-

EE

gested value for C is 50nF. This value should work for

G

most pass transistors (Q1).

works as in the initial start-up: V

is ramped down at the

Overvoltage Fault

OUT

rate set by I

and C followed by GATE pull-up. The

RAMP

R

An overvoltage fault occurs when the OV pin rises above

its 1.77V threshold. This shuts off the pass transistor

immediately, sets the overvoltage present bit A0 and

the overvoltage fault bit B0, and pulls the SS pin down.

Note that the power good signals are not affected by the

overvoltage fault. If the OV pin subsequently falls back

below the threshold, the pass transistor will be allowed

power good signals on the PG and PGIO pins, the TMR

pin, and the SS pin are not interrupted through the input

step sequence. The waveform in Figure7 shows how the

LTC4261/LTC4261-2respondstoaninputstep.

Note that the current limit threshold should be set

sufﬁciently high to accommodate the sum of the load

current and the inrush current to avoid engagement of

to turn on again immediately (without delay) unless the

42612fd

18

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

72V

RTN – V

EE

36V

0V

TMR

SS

2.56V

V

GATEH

GATE

FET V

TH

V

OUT

50mV

LOAD + INRUSH

SENSE

LOAD

0V

LOAD

PG

0V

PGIO

42612 F07

Figure 7. –36V to –72V Step Response

overvoltage auto-retry has been disabled by clearing reg-

ister bit D0.

an undervoltage shutdown threshold of 38.5V and an

overvoltage shutdown threshold of 72.3V.

The UV hysteresis can be adjusted by separating the

Undervoltage Comparator and Undervoltage Fault

UVH and the UVL pins with a resistor R (Figure 8). To

H

The LTC4261/LTC4261-2 provide two undervoltage pins,

UVH and UVL, for adjustable UV threshold and hyster-

esis. The UVH and UVL pins have the following accurate

thresholds:

increase the UV hysteresis, the UVL tap should be placed

above the UVH tap as in Figure 8a. To reduce the UV hys-

teresis, place the UVL tap under the UVH tap as in Figure

8b. UV hysteresis referred to the UVL pin is given by:

For UVH rising, V

For UVL falling, V

= 2.56V, turn on

= 2.291V, turn off

UVH(TH)

UVL(TH)

for V_UVL≥ V_UVH

,

R_H

R1+ R2

DV_UVL(HYST)= DV_UV(HYST)+ 2.56V •

Both UVH and UVL pins have a minimum hysteresis of

or for V_UVL< V_UVH

,

dV (15mV typical). In either a rising or a falling input

UV

supply, the undervoltage comparator works in such a way

that both the UVH and the UVL pins have to cross their

thresholds for the comparator output to change state.

R_H

DV_UVL(HYST)= DV_UV(HYST)– 2.56V •

R1+ R2+ R_H

< V , the minimum UV hysteresis allowed is

UVH

For V

UVL

The UVH, UVL, and OV threshold ratio is designed to

match the standard telecom operating range of 43V to

71V and UV hysteresis of 4.5V when UVH and UVL are

tied together as in Figure 1, where the built-in UV hyster-

esis referred to the UVL pin is:

the minimum hysteresis at UVH and UVL: dV = 15mV

UV

when R

= 0.11 • (R1 + R2)

H(MAX)

The design of the LTC4261/LTC4261-2 protects the UV

comparator from chattering even when R is larger than

H

R

.

H(MAX)

DV

= V

– V

= 0.269V

UV(HYST)

UVH(TH)

UVL(TH)

An undervoltage fault occurs when the UVL pin falls

Using R1 = 11.8k, R2 = 16.9k and R3 = 453k as in Figure 1

gives a typical operating range of 43.0V to 70.7V, with

below 2.291V and the UVH pin falls below 2.56V – dV .

UV

This activates the FET turn-off and sets the undervoltage

42612fd

19

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

–48V RTN

FET Short Fault

R3

AFETshortfaultwillbereportedifthedataconvertermea-

sures a current sense voltagegreaterthan orequalto 2mV

while the FET is turned off. This condition sets the FET

short present bit A5 and the FET short fault bit B5.

453k

1%

UVL

UVH

0V

UVH

UVL

0V

R

H

R

H

TURN-ON = 46V

TURN-OFF = 38.5V

HYSTERESIS = 7.5V

TURN-ON = 43V

TURN-OFF = 41.2V

HYSTERESIS = 1.8V

1.91k

1%

1.91k

1%

R2

15k

1%

R2

15k

1%

Power Bad Fault

After the FET is turned on and the power good outputs

pull PG and PGIO low, a delay timer with duration of 4t is

R1

11.8k

1%

11.8k

1%

D

started and the level of the PGI pin is checked (Figure 3).

If the PGI pin is pulled below its 1.4V threshold before

the PGI check timer expires, the FET will remain on.

Otherwise, the FET is immediately turned off, the power

good signals are reset and the power bad present bit A3

and the power bad fault bit B3 are set. After the FET is

turned off, the power bad present bit A3 will be cleared.

If the PGI pin is subsequently pulled low, the FET will

remain off unless the power bad auto-retry has been en-

abled by setting bit D4 or the power bad fault bit B3 is

cleared. In either of those two conditions, the FET will

42612 F08

V

EE

(8a)

(8b)

Figure 8. Adjustment of Undervoltage Thresholds

for Larger (8a) or Smaller (8b) Hysteresis

present bit A1 and the undervoltage fault bit B1. The

power good signals at PG and PGIO are also reset.

The undervoltage present bit A1 is cleared when the

UVH pin rises above 2.56V and the UVL pin rises above

2.291V + dV . After a delay of t , the FET will turn on

again unless the undervoltage auto-retry has been dis-

UV

D

turn on again following a delay of t and the PGI pin is

D

abled by clearing bit D1.

checked again as described above.

When power is applied to the device, if UVL is below

External Fault Monitors

the 2.291V threshold and UVH is below 2.56V – dV

UV

after INTV crosses its undervoltage lock out threshold

CC

The FLTIN pin (SSOP only) and the PGIO pin, when con-

ﬁgured as general purpose input, allow monitoring of ex-

ternal fault conditions such as broken fuses. If FLTIN is

pulled below its 1.4V threshold, bit B7 in the FAULT reg-

ister is set. An associated alert bit, C7, is also available

in the ALERT register. When the PGIO pin is conﬁgured

as general purpose input, if the voltage at PGIO is above

1.25V, both bit A6 in the STATUS register and bit B6 in

the FAULT register are set, though there is no alert bit as-

sociated with this fault. The external fault conditions do

not directly affect the GATE control functions.

(4.25V), an undervoltage fault will be logged in the fault

register.

Because of the compromises of selecting from a table of

discrete resistor values (1% resistors in 2% increments,

0.1% resistors in 1% increments), best possible OV and

UV accuracy is achieved using separate dividers for each

pin. This increases the total number of resistors from

three or four to as many as six, but maximizes accuracy,

greatly simpliﬁes calculations and facilitates running

changes to accommodate multiple standards or custom-

ization without any board changes.

Fault Alerts

To improve noise immunity, put the resistive divider to

the UV and OV pins close to the chip and keep traces to

When any of the fault bits in FAULT register B is set, an

optionalbusalertcanbegeneratedbysettingtheappropri-

ate bit in the ALERT register C. This allows only selected

faultstogeneratealerts.Atpower-upthedefaultstateisnot

to alert on faults. If an alert is enabled, the corresponding

RTN and V short. A 0.1µF capacitor from the UVH or

EE

UVL pin (and OV pin through resistor R2) to V helps

EE

reject supply noise.

42612fd

20

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

A2 or A3 will hold the FET off and the FAULT register is

ignored. Subsequently, when the A0, A1, A2 and A3 bits

are cleared, the FET is allowed to turn on again.

fault will cause the ALERT pin to pull low. After the bus

master controller broadcasts the alert response address,

the LTC4261/LTC4261-2 will respond with its address on

the SDA line and release ALERT as shown in Figure 14.

If there is a collision between two LTC4261’s responding

with their addresses simultaneously, then the device with

the lower address wins arbitration and responds first. The

ALERT line will also be released if the device is addressed

by the bus master.

Turning the LTC4261/LTC4261-2 On and Off

Many methods of on/off control are possible using the

2

ON, EN, UV/OV, FLTIN or PGIO pins along with the I C

port. The EN pin works well with logic inputs or ﬂoat-

2

ing switch contacts; I C control is intended for systems

where the board operates only under command of a cen-

tral control processor and the ON pin is useful with sig-

nals referenced to RTN, as are the UV (UVH, UVL) and

OV pins. PGIO and FLTIN control nothing directly, but are

Once the ALERT signal has been released for one fault,

it will not be pulled low again until the FAULT register

indicates a different fault has occurred, or the original

fault is cleared and it occurs again. Note that this means

repeated or continuing faults will not generate alerts until

the associated FAULT register bit has been cleared.

2

useful for I C monitoring of connection sense or other

important signals.

2

On/off control is possible with or without I C interven-

Resetting Faults

tion. Further, the LTC4261/LTC4261-2 may reside on

either the removable board or on the backplane. Even

Faults are reset with any of the following conditions.

First, writing zeros to the FAULT register B will clear the

associated fault bits. Second, the entire FAULT register

is cleared when either the ON pin or bit D3 goes from

2

when operating autonomously, the I C port can still ex-

ercise control over the GATE output, although depending

on how they are connected, EN and ON could subse-

2

quently override conditions set by I C. UV, OV and other

high to low, or if INTV falls below its 4.25V undervolt-

CC

fault conditions seize control as needed to turn off the

age lockout. Pulling the UVL pin below its 1.21V reset

threshold also clears the entire FAULT register. When the

UVL pin is brought back above 1.21V but below 2.291V,

the undervoltage fault bit B1 is set if the UVH pin is below

2.56V. This can be avoided by holding the UVH pin above

2.56V while toggling the UVL pin to reset faults. Finally,

when EN is brought from high to low, all fault bits except

bit B4 are cleared. The bit B4 that indicates an EN change

of state will be set.

2

GATE output, regardless of the state of EN, ON or the I C

port. Figure 9 shows ﬁve conﬁgurations of on/off control

of the LTC4261/LTC4261-2.

Determining factors in selecting a pin conﬁguration for

autonomous operation are the polarity and voltage of the

controlling signal.

Optical Isolation. Figure 9a shows an opto-isolator driv-

ing the ON pin. Rising and falling edges at the ON pin

turn the GATE output on and off. If ON is already high

Fault bits with associated conditions that are still pres-

ent (as indicated in the STATUS Register A) cannot be

cleared. The FAULT register will not be cleared when

auto-retrying. When auto-retry is disabled, the existence

of B0 (overvoltage), B1 (undervoltage), B2 (overcurrent)

or B3 (power bad) fault keeps the FET off. After the fault

when power is applied, GATE is delayed one t period.

D

The status of ON can be examined or overridden through

2

the I C port at register bit D3. This circuit works in both

backplane and board resident applications.

Logic Control. Figure 9b shows an application using log-

ic signal control. Again, the ON pin is used as an input;

all remarks made concerning opto-isolator control apply

here as well.

bit is cleared and a delay of t (for B0, B1 and B3) or 4t

D

(for B4) expires, the FET will turn on again. Note that if

the overvoltage fault bit B0 is cleared by writing a zero

2

through I C, the FET is allowed to turn on without a de-

lay. If auto-retry is enabled, then a high value in A0, A1,

42612fd

21

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

Ejector Switch or Loop-Through Connection Sense.

Floating switch contacts or a connection sense loop also

work well with the ON pin, replacing the phototransistor

in Figure 9a. If an insertion debounce delay is desired,

use the EN pin as shown in Figure 9c. Like Figures 9a

and 9b, this circuit works on either side of the backplane

connector.

Data Converter

The LTC4261/LTC4261-2 incorporates a 10-bit DΣ ana-

log-to-digital converter (ADC) that continuously moni-

tors three different voltages at (in the sequence of)

SENSE, ADIN2/OV (SSOP/QFN) and ADIN. The DΣ ar-

chitecture inherently averages signal noise during the

measurement period. The voltage between the SENSE

pin and V_EEis monitored with a 64mV full scale and

62.5µV resolution, and the data is stored in registers E

and F. The ADIN and the ADIN2/OV pins are monitored

with a 2.56V full scale and 2.5mV resolution. The data

for the ADIN2/OV pin is stored in registers G and H. The

data for the ADIN pin is stored in registers I and J.

Short Pin to RTN. Figure 9d uses the UV divider string to

detect board insertion. This method works equally well in

both backplane and board resident applications.

AdvancedTCA Style Control. Figure 2 shows an ATCA

application using EN as the interface to the LTC4261.

2

Register bit A4 allows the I C port to monitor the status

of EN and by setting C4 high, bit B4 can generate an alert

to instantly report any changes in the state of EN.

The results in registers E, F, G, H, I and J are updated at

a frequency of 7.3Hz. Setting CONTROL register bit D5

invokes a test mode that halts updating of these registers

so that they can be written to and read from for software

testing. By invoking the test mode right before reading

the ADC data registers, the 10-bit data separated in two

registers are synchronized.

2

I C Only Control. To lock out EN and ON, use the con-

ﬁguration shown in Figure 9e and control the GATE pin

with register bit D3. The circuit defaults off at power up.

To default on, connect the ON pin to INTV . Either FLTIN

CC

or PGIO can be used as an input to monitor a connection

sense or other control signal. PGIO is conﬁgured as an

input by setting register bits D6 and D7 high; its input

state is stored at location B6. FLTIN is always an input

whose state is available from register bit B7. FLTIN gen-

erates an alert if C7 is set high.

The ADIN and ADIN2 pins can be used to monitor input

and output voltages of the Hot Swap controller as shown

in Figures 1 and 2.

LOOP OR

SWITCH

5V

1k

1M

INTV

ON

INTV

CC

100k

LTC4261

EN

ON

EN

ON

V

EE

V

EE

10nF

47k

–48V

(9a) Opto-Isolator Control

(9b) Logic Control

(9c) Contact Debounce Delay Upon

Insertion for Use with an Ejector

Switch or Loop-Through Style

Connection Sense

–48V

RTN

453k

INTV

ON

CC

ON

EN

CC

DEFAULT

ON

SDAO

SDAI

SCL

LTC4261

2

UVL

UVH

I C

LTC4261

DEFAULT

OFF

28.7k

V

EE

EN

–48V

INPUT

42612 F09

–48V

2

(9d) Short Pin Connection Sense to RTN

(9e) I C-Only Control

Figure 9. On/Off Control of the LTC4261

42612fd

22

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

Configuring the PGIO Pin

The FET is selected to handle the maximum power dissi-

pation during start-up or an input step. The latter usually

results in a larger power due to summation of the inrush

Table 6 describes the possible states of the PGIO pin us-

ing the CONTROL register bits D6 and D7. At power-up

the default state is for the PGIO pin to pull low when

the second power good signal is ready. Other uses for

the PGIO pin are to go high impedence when the sec-

ond power good is ready, a general purpose output and a

general purpose input. When the PGIO pin is conﬁgured

as a general purpose output, the status of bit C6 is sent

out to the pin. When it is conﬁgured as a general pur-

pose input, if the input voltage at PGIO is higher than

1.25V, both bit A6 in the STATUS register and bit B6 in

the FAULT register are set. If the input voltage at PGIO

subsequently drops below 1.25V, bit A6 is cleared. Bit

B6 can be cleared by resetting the FAULT register as de-

scribed previously.

current charging C and the load current. For a 36V input

L

2

step, the total P t in the FET is approximated by:

t

3

2

P²t = 36V •I

•

(

)

MAX

where t is the time it takes to charge up C :

L

C_L• 36V 330µF • 36V

t =

=

= 18ms

I_INRUSH

0.66A

2

which gives a P t value of 244W s.

2

Now the P t given by the SOA (safe operating area)

2

curves of candidate FETs must be higher than 244W s.

The SOA curves of the IRF1310NS provide for 5A at 50V

2

(250W) for 10ms, which gives a P t value of 625W s and

satisﬁes the requirement.

Design Example

As a design example, consider the 200W application with

Sizing R1, R2 and R3 for the required UV and OV thresh-

old voltages:

C = 330µF as shown in Figure 1. The operating voltage

L

range is from 43V to 71V with a UV turn-off threshold of

V

= 43V, V

= 38.5V, (using

38.5V.

UV(RISING)

UV(FALLING)

= 2.56V and V

= 2.291V)

UVH(TH)

The design ﬂow starts with calculating the maximum in-

put current:

V

= 72.3V, V

OV(FALLING)

= 70.7V (using

OV(RISING)

= 1.77V rising and 1.7325V falling)

OV(TH)

200W

36V

I_MAX

=

= 5.6A

Layout Considerations

where 36V is the minimum input voltage.

To achieve accurate current sensing, a Kelvin connection

is recommended (Figure 10). The minimum trace width

for 1oz copper foil is 0.02" per amp to make sure the

trace stays at a reasonable temperature. Using 0.03" per

amp or wider is recommended. Note that 1oz copper ex-

hibits a sheet resistance of about 530µW/square. Small

resistances add up quickly in high current applications.

The selection of the sense resistor, R , is determined by

S

the minimum current limit threshold and maximum input

current:

DV_SENSE(MIN)

45mV

5.6A

R_S=

=

= 8mW

I_MAX

The V pin of the LTC4261 should be connected to a

The inrush current is set to 0.66A using C :

EE

R

separate plane that is different from the main –48V in-

I_RAMP

I_INRUSH

20µA

0.66A

put plane. To improve noise immunity, as shown in

C_R= C_L•

= 330µF •

= 10nF

Figure 10, the V connections of all capacitors, resistive

EE

2

dividers, opto-isolators and I C common must be made

directly to the local V plane, not the –48V input plane.

The value of R and C are chosen to 1k and 33nF as

F

EE

discussed previously.

42612fd

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For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

command will be identical to the ﬁrst word. The second

word in a Write Word command is ignored. The data for-

matsforthesecommandsareshowninFigures12to15.

V

PLANE

EE

LTC4261 V PIN

EE

TO SENSE PIN

MOSFET

ALL CAPACITORS

ALL RESISTIVE DIVIDERS

ALL OPTO-ISOLATORS

2

G

I C COMMON

D

Using Opto-Isolators with SDA

•

R

S

•

42612 F10

The LTC4261/LTC4261-2 split the SDA line into SDAI (in-

put) and SDAO (output) for convenience of opto-coupling

with the host. If opto-isolators are not used then tie SDAI

and SDAO together to form a normal SDA line. When us-

ing opto-isolators, connect the SDAI pin to the output of

the incoming opto-isolator and connect the SDAO pin to

the input of the outgoing opto-isolator (see Figure 2). If

the SDAI and SDAO on the master controller are not tied

together, the ACK bit of SDAO must be returned back to

SDAI. If the ALERT line is used as an interrupt for the

host to respond to a fault in real time, connect the ALERT

pin to an opto-isolator in a way similar to that for the

SDAO pin as shown in Figure 2.

VIAS

–48V INPUT PLANE

Figure 10. Layout Example of V_EEPlane, –48V Input Plane and

Sense Resistor Connection

2

I C Interface

2

The LTC4261/LTC4261-2 feature an I C interface to pro-

vide access to the ADC data registers and four other regis-

ters for monitoring and control of the pass FET. Figure11

2

shows a general data transfer format using the I C. The

LTC4261/LTC4261-2 are read-write slave devices and

supportSMBusbusReadByte,WriteByte,ReadWordand

Write Word commands. The second word in a Read Word

SDA

SCL

a6 - a0

1 - 7

b7 - b0

8

9

1 - 7

8

9

1 - 7

8

9

S

P

START

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

CONDITION

42612 F11

Figure 11. Data Transfer over I²C or SMBus

S

ADDRESS W A

0 0 1 a3:a0

COMMAND

A

DATA

A

P

S

ADDRESS W A

0 0 1 a3:a0

COMMAND

X X X X b3:b0

A

DATA

A

DATA

A

P

0

X X X X b3:b0

0

b7:b0

0

b7:b0

0

X X X X X X X X

0

42612 F13

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

A: ACKNOWLEDGE (LOW)

A: NOT ACKNOWLEDGE (HIGH)

R: READ BIT (HIGH)

Figure 13. LTC4261 Serial Bus SDA Write Word Protocol

W: WRITE BIT (LOW)

S: START CONDITION

S

ADDRESS W A

0 0 1 a3:a0

COMMAND

A

S

ADDRESS

R

A

DATA

A

P

P: STOP CONDITION

0

X X X X b3:b0

0

0 0 1 a3:a0

1

0

b7:b0

1

42612 F12

42612 F14

Figure 12. LTC4261 Serial Bus SDA Write Byte Protocol

Figure 14. LTC4261 Serial Bus SDA Read Byte Protocol

S

ADDRESS W A

0 0 1 a3:a0

COMMAND

A

S

ADDRESS

R

A

DATA

A

DATA

A

P

0

X X X X b3:b0

0

0 0 1 a3:a0

1

0

b7:b0

0

b7:b0

1

42612 F15

Figure 15. LTC4261 Serial Bus SDA Read Word Protocol

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For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

START and STOP Conditions

leases the SDA line during the acknowledge clock pulse.

When the slave is the receiver, it must pull down the SDA

line so that it remains LOW during this pulse to acknowl-

edge receipt of the data. If the slave fails to acknowl-

edge by leaving SDA HIGH, then the master can abort

the transmission by generating a STOP condition. When

the master is receiving data from the slave, the master

must pull down the SDA line during the clock pulse to

indicate receipt of the data. After the last byte has been

received the master will leave the SDA line HIGH (not

acknowledge) and issue a STOP condition to terminate

the transmission.

When the bus is idle, both SCL and SDA must be high. A

bus master signals the beginning of a transmission with

a START condition by transiting SDA from high to low

while SCL is high. When the master has ﬁnished com-

municating with the slave, it issues a STOP condition by

transiting SDA from low to high while SCL is high. The

bus is then free for another transmission.

Stuck-Bus Reset

2

The LTC4261/LTC4261-2 I C interface features a stuck-

bus reset timer. The low conditions of the SCL and the

SDAI pins are ORed to start the timer. The timer is reset

when both SCL and SDAI are pulled high. If the SCL pin

or the SDAI pin is held low for over 66ms, the stuck-bus

Write Protocol

The master begins communication with a START con-

dition followed by the seven bit slave address and the

R/W bit set to zero. The addressed LTC4261/LTC4261-2

acknowledge this and then the master sends a command

byte which indicates which internal register the master

wishes to write. The LTC4261/LTC4261-2 acknowledge

this and then latch the lower four bits of the command

byte into its internal Register Address pointer. The master

then delivers the data byte and the LTC4261/LTC4261-2

acknowledge once more and latch the data into its inter-

nal register. The transmission is ended when the master

sends a STOP condition. If the master continues sending

a second data byte, as in a Write Word command, the

second data byte will be acknowledged by the LTC4261/

LTC4261-2 but ignored.

2

timer will expire and the internal I C state machine will

be reset to allow normal communication after the stuck-

low condition is cleared. When the SCL pin and the SDAI

pin are held low alternatively, if the ORed low period of

SCL and SDAI exceeds 66ms before the timer reset con-

dition (both SCL and SDAI are high) occurs, the stuck-

2

bus timer will expire and the I C state machine is reset.

2

I C Device Addressing

2

Any of eight distinct I C bus addresses are selectable us-

ing the three-state pins ADR0 and ADR1, as shown in

Table 1. Note that the conﬁguration of ADR0 = L and ADR1

= H is used to enable the single-wire broadcasting mode.

2

For the eight I C bus addresses, address bits B6, B5 and

B4 are conﬁgured to (001) and the least signiﬁcant bit B0

is the R/W bit. In addition, the LTC4261/LTC4261-2 will

respond to two special addresses. Address (0011 111)

is a mass write used to write to all LTC4261/LTC4261-2s,

regardless of their individual address settings. Address

(0001 100) is the SMBus Alert Response Address. If the

LTC4261/LTC4261-2 are pulling low on the ALERT pin,

it will acknowledge this address using the SMBus Alert

Response Protocol.

Read Protocol

The master begins a read operation with a START con-

dition followed by the seven bit slave address and the

R/W bit set to zero. The addressed LTC4261/LTC4261-2

acknowledge this and then the master sends a command

byte that indicates which internal register the master

wishes to read. The LTC4261/LTC4261-2 acknowledge

this and then latch the lower four bits of the command

byte into its internal Register Address pointer. The mas-

ter then sends a repeated START condition followed by

the same seven bit address with the R/W bit now set to

one. The LTC4261/LTC4261-2 acknowledge and send the

contents of the requested register. The transmission is

Acknowledge

The acknowledge signal is used for handshaking be-

tween the transmitter and the receiver to indicate that the

last byte of data was received. The transmitter always re-

ended when the master sends a STOP condition. If the

42612fd

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For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

master acknowledges the transmitted data byte, as in a

Read Word command, the LTC4261/LTC4261-2 will re-

peat the requested register as the second data byte. Note

that the Register Address pointer is not cleared at the

end of the transaction. Thus the Receive Byte protocol

can be used to repeatedly read a speciﬁc register.

this means repeated or continuing faults will not gener-

ate alerts until the associated FAULT register bit has been

cleared.

Single-Wire Broadcast Mode

TheLTC4261/LTC4261-2providesasingle-wirebroadcast

mode in which selected register data are sent out to the

SDAO pin without clocking the SCL line (Figure 17). The

single-wire broadcast mode is enabled by setting the

Alert Response Protocol

The LTC4261/LTC4261-2 implement the SMBus Alert

Response Protocol as shown in Figure 16. If enabled

to do so through the ALERT register C, the LTC4261/

LTC4261-2 will respond to faults by pulling the ALERT

pin low. Multiple LTC4261/LTC4261-2s can share a com-

mon ALERT line and the protocol allows a master to de-

termine which LTC4261/LTC4261-2s are pulling the line

low. The master begins by sending a START bit followed

by the special Alert Response Address (0001 100)b with

the R/W bit set to one. Any LTC4261/LTC4261-2 that is

pulling its ALERT pin low will acknowledge and begin

sending back its individual slave address.

2

ADR1 pin high and the ADR0 pin low (the I C interface is

disabled). At the end of each conversion of the three ADC

channels, a stream of eighteen bits are broadcasted to

SDAO with a serial data rate of 15.3kHz 20% in a format

as illustrated in Figure 18. The data bits are encoded with

an internal clock in a way similar to Manchester encoding

that can be easily decoded by a microcontroller or FPGA.

Each data bit consists of a noninverting phase and an

inverting phase. During the conversion of each ADC chan-

nel, SDAO is idle at high. At the end of the conversion, the

SDAO pulls low. The START bit indicates the beginning of

data broadcasting and is used along with the dummy bit

(DMY) to measure the internal clock cycle (i.e., the serial

data rate). Following the DMY bit are two channel code

bits CH1 and CH0 labeling the ADC channel (see Table

10). Ten data bits of the ADC channel (ADC9-0) and three

FAULT register bits (B2, B1 and B0) are then sent out. A

parity bit (PRTY) ends each data stream. After that the

SDAO line enters the idle mode with SDAO pulled high.

ALERT

RESPONSE

ADDRESS

DEVICE

ADDRESS

S

R

P

A

0 0 0 1 1 0 0

1

0

0 0 1 a3:a0 0

1

42612 F16

Figure 16. LTC4261 Serial Bus SDA Alert Response Protocol

An arbitration scheme ensures that the LTC4261/

LTC4261-2 with the lowest address will have priority;

all others will abort their response. The successful re-

sponder will then release its ALERT pin while any others

will continue to hold their ALERT pins low. Polling may

also be used to search for any LTC4261/LTC4261-2 that

have detected faults. Any LTC4261/LTC4261-2 pulling its

ALERT pin low will also release it if it is individually ad-

dressed during a read or write transaction.

The following data reception procedure is recommended:

0. Wait for INTV rising edge.

CC

1. Wait for SDAO falling edge.

2. The first falling edge could be a glitch, so check again

after a delay of 10µs. If back to high, wait again. If still

low, it is the START bit.

The ALERT signal will not be pulled low again until the

FAULT register indicates a different fault has occurred or

the original fault is cleared and it occurs again. Note that

3. Use the following low-to-high and high-to-low transis-

tions to measure 1/2 of the internal clock cycle.

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26

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

–48V RTN

6 × 0.51k IN SERIES

1/4W EACH

5V

7.5k

INTV

V

IN

CC

ADR1

ADR0

SDAI

SCL

V

CC

LTC4261

1µF

V

DD

ANODE

R

D

IN

L

MICRO-

CONTROLLER

0.1µF

CATHODE V

GND

SDAO

V

OUT

EE

HCPL-0300

–48V INPUT

42612 F17

Figure 17. Single-Wire Broadcast Mode

INTERNAL

CLK

.. .. ..

DATA

START DMY

CH1

CH0 ADC9

ADC0

OC

UV

OV

PRTY

SDAO

4261 F18

START

Figure 18. Single-Wire Broadcast Data Format

4. Wait for the second low-to-high transistion (middle of

DMY bit).

The above procedure can be ported to a microcontroller

or used to design a state machine in FPGA. Code should

have timeouts in case an edge is missed. Abort the read

if it takes more than double the typical time (1.2ms) for

all 18 bits to be clocked out.

5. Wait 3/4 of a clock cycle.

6. Sample bit CH1, wait for transistion.

7. Wait 3/4 of a clock cycle.

A typical application circuit with the LTC4261/LTC4261-2

in the broadcast mode is illustrated in Figure 19, where

8. Sample bit CH0, wait for transistion.

9. Wait 3/4 of a clock cycle.

input voltage, V of the FET and V

are monitored.

DS

SENSE

Register Addresses and Contents

10. Sample ADC9, wait for transistion.

11. Continue until all bits are read.

The register addresses and contents are summerized in

Table 1 and Table 2. The function of each register bit is

detailed in Tables 3 to 9.

42612fd

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For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

Table 1. LTC4261 Device Addressing

HEX DEVICE

ADDRESS

LTC4261

ADDRESS PINS

DESCRIPTION

BINARY DEVICE ADDRESS

h

6

0

5

0

4

1

0

1

3

1

0

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R/W

0

ADR1

X

ADR0

X

Mass Write

3E

19

20

22

24

26

28

2A

2C

2E

Alert Response

1

X

0

1

2

3

4

5

6

7

8

X

L

X

L

NC

H

X

H

X

L

X

NC

H

L

X

NC

H

X

NC

H

Single-Wire Broadcast Mode

L

H = Tie to INV ; L = Tie to V ; NC = No connect, open; X = Don’t care

CC

EE

Table 2. LTC4261 Register Address and Contents

REGISTER

ADDRESS*

REGISTER

NAME

READ/WRITE

R

DESCRIPTION

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

STATUS (A)

FAULT (B)

System Status Information

Fault Log and PGIO Input

R/W

ALERT (C)

CONTROL (D)

SENSE (E)

SENSE (F)

ADIN2/OV (G)

ADIN2/OV (H)

ADIN (I)

R/W

Controls Whether the ALERT Pin is Pulled Low After a Fault is Logged in the Fault Register

Controls Whether the Part Retries After Faults, Set the On/Off Switch State

ADC Current Sense Voltage Data (8 MSBs)

R/W

R/W**

ADC Current Sense Voltage Data (2 LSBs)

ADC ADIN2/OV (SSOP/QFN) Voltage Data (8 MSBs)

ADC ADIN2/OV (SSOP/QFN) Voltage Data (2 LSBs)

ADC ADIN Voltage Data (8 MSBs)

ADIN (J)

ADC ADIN Voltage Data (2 LSBs)

*Register address MSBs b7-b4 are ignored. **Writable if bit D5 set.

42612fd

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For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

Table 3. STATUS Register A (00h)—Read Only

BIT

A7

A6

A5

A4

A3

A2

A1

A0

NAME

OPERATION

FET On

Indicates State of FET; 1 = FET On, 0 = FET Off

PGIO Input

FET Short

EN

Indicates State of the PGIO Pin when Configured to General Purpose Input: 1 = PGIO High, 0 = PGIO Low

Indicates Potential FET Short if Current Sense Voltage Exceeds 2mV While FET is Off; 1 = FET is Shorted, 0 = FET is Not Shorted

Indicates State of the EN Pin; 1 = EN Pin High, 0 = EN Pin Low

Power Bad

Overcurrent

Undervoltage

Overvoltage

Indicates Power is Bad when PGI is High at the End of the PGI Check Timer; 1 = PGI High, 0 = PGI Low

Indicates Overcurrent Condition; 1 = Overcurrent, 0 = Not Overcurrent

Indicates Input Undervoltage when Both UVH and UVL are Low; 1 = UVH and UVL Low, 0 = UVH or UVL High

Indicates Input Overvoltage when OV is High; 1 = OV High, 0 = OV Low

Table 4. FAULT Register B (01h)—Read/Write

BIT

NAME

OPERATION

B7

External Fault

Occurred

Latched to 1 if FLTIN Goes Low; 1 = FLTIN Low State Detected, 0 = FLTIN has Not Been Low

B6

B5

B4

B3

B2

B1

B0

PGIO Input

Latched to 1 if the PGIO Pin Goes High when Configured to General Purpose Input; 1 = PGIO High Detected,

0 = PGIO has Been Low

High Occurred

FET Short Fault Indicates Potential FET Short was Detected When Measured Current Sense Voltage Exceeded 2mV While FET was Off;

Occurred

1 = FET Short Fault Occurred, 0 = No FET Short Fault

EN Changed

State

Indicates That a Board was Inserted or Extracted when EN Changed State; 1 = EN Changed State, 0 = EN Unchanged

Power Bad

Fault Occurred 0 = No Power Bad Fault

Indicates Power was Bad when PGI was High at the End of the PGI Check Timer; 1 = Power Bad Fault Occurred,

Overcurrent

Fault Occurred

Indicates Overcurrent Fault Occurred; 1 = Overcurrent Fault Occurred, 0 = No Overcurrent Fault

Indicates Input Undervoltage Fault Occurred when Both UVH and UVL went Low; 1 = Undervoltage Fault Occurred,

Undervoltage

Fault Occurred 0 = No Undervoltage Fault

Overvoltage

Fault Occurred

Indicates Input Overvoltage Fault Occurred when OV was High; 1 = Overvoltage Fault Occurred, 0 = No Overvoltage Fault

Table 5. ALERT Register C (02h)—Read/Write

BIT

NAME

OPERATION

C7

External Fault

Alert

Enables Alert for External Fault When FLTIN was Low; 1 = Enable Alert, 0 = Disable Alert (Default)

C6

C5

C4

PGIO Output

Output Data Bit to PGIO Pin when Configured as Output. Defaults to 0

FET Short Alert Enables Alert for FET Short Fault; 1 = Enable Alert, 0 = Disable Alert (Default)

EN State

Change Alert

Enables Alert when EN Changed State; 1 = Enable Alert, 0 Disable Alert (Default)

Enables Alert for Power Bad Fault; 1 = Enable Alert, 0 Disable Alert (Default)

Enables Alert for Overcurrent Fault; 1 = Enable Alert, 0 Disable Alert (Default)

Enables Alert for Undervoltage Fault; 1 = Enable Alert, 0 Disable Alert (Default)

Enables Alert for Overvoltage Fault; 1 = Enable Alert, 0 Disable Alert (Default)

C3

C2

C1

C0

Power Bad

Alert

Overcurrent

Alert

Undervoltage

Alert

Overvoltage

Alert

42612fd

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For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

APPLICATIONS INFORMATION

Table 6. CONTROL Register D (03h)—Read/Write

BIT

NAME

OPERATION

D7:6 PGIO Configure

Configures Behavior of PGIO Pin

FUNCTION

D6

D7

0

PGIO PIN

Open Drain

PGIO = C6

PGIO = Hi-Z

Power Good (Default)

Power Good

0

1

General Purpose Output

General Purpose Input

0

1

D5

D4

Test Mode Enable Test Mode Halts ADC Operation and Enables Writes to ADC Registers; 1 = Enable Test Mode, 0 = Disable Test Mode (Default)

Power Bad

Auto-Retry

Enables Auto-Retry After a Power Bad Fault; 1 = Retry Enabled, 0 = Retry Disabled (Default)

D3

D2

FET On Control

Turns FET On and Off; 1 = Turn FET On, 0 = Turn FET Off. Defaults to ON Pin State at End of Start-Up Debounce Delay

Overcurrent

Auto-Retry

Enables Auto-Retry After an Overcurrent Fault; 1 = Retry Enabled (Default, LTC4261-2),

0 = Retry Disabled (Default, LTC4261)

D1

D0

Undervoltage

Auto-Retry

Enables Auto-Retry After an Undervoltage Fault; 1 = Retry Enabled (Default), 0 = Retry Disabled

Overvoltage

Auto-Retry

Enables Auto-Retry After an Overvoltage Fault; 1 = Retry Enabled (Default), 0 = Retry Disabled

Table 7. SENSE Registers E (04h) and F (O5h)—Read/Write

BIT

NAME

OPERATION

E7:0, F7:6

F5:0

SENSE Voltage Data

Reserved

10-Bit Data of Current Sense Voltage with 62.5µV LSB and 64mV Full Scale

Always Returns 0, Not Writable

Table 8. ADIN2/OV Registers G (06h) and H (O7h)—Read/Write

BIT

NAME

ADIN2/OV Voltage Data 10-Bit Data of ADIN2/OV (SSOP/QFN) Voltage with 2.5mV LSB and 2.56V Full Scale

Reserved Always Returns 0, Not Writable

OPERATION

G7:0, H7:6

H5:0

Table 9. ADIN Registers I (08h) and J (O9h)—Read/Write

BIT

NAME

OPERATION

I7:0, J7:6

J5:0

ADIN Voltage Data

Reserved

10-Bit Data of ADIN Voltage with 2.5mV LSB and 2.56V Full Scale

Always Returns 0, Not Writable

Table 10. ADC Channel Labeling for Single-Wire Broadcast Mode

CH1

0

CH0

0

ADC CHANNEL

SENSE Voltage

0

1

ADIN2/OV (SSOP/QFN) Voltage

ADIN Voltage

1

0

42612fd

30

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

TYPICAL APPLICATION

Using the LTC4261 and a Thermistor to Monitor Temperature

–48V RTN

6 × 0.51k IN SERIES

1/4W EACH

100k AT 25°C

1%

VISHAY

NTCS0402E3104*HT

V

IN

30.1k

1%

LTC4261CGN

SDAO

2

ADIN

SDAI

SCL

I C

10k

1µF

1%

V

EE

–48V INPUT

42612 TA02

T (°C) = 38.05 • (V

(V) – 0.1458), 20°C < T < 60°C

ADIN

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641 Rev B)

.386 – .393*

(9.804 – 9.982)

.045 .005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 .004

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

(0.38 0.10)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 REV B 0212

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

42612fd

31

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UFD Package

24-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-ꢀ696 Rev A)

0.70 0.05

4.50 0.05

3.ꢀ0 0.05

2.65 0.05

2.00 REF

3.65 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

3.00 REF

4.ꢀ0 0.05

5.50 0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.05 TYP

PIN ꢀ NOTCH

2.00 REF

R = 0.20 OR C = 0.35

R = 0.ꢀꢀ5

TYP

0.75 0.05

4.00 0.ꢀ0

(2 SIDES)

23

24

0.40 0.ꢀ0

PIN ꢀ

TOP MARK

(NOTE 6)

ꢀ

2

5.00 0.ꢀ0

(2 SIDES)

3.00 REF

3.65 0.ꢀ0

2.65 0.ꢀ0

(UFD24) QFN 0506 REV A

0.25 0.05

0.200 REF

0.50 BSC

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

42612fd

32

For more information www.linear.com/LTC4261

LTC4261/LTC4261-2

REVISION HISTORY ^{(Revision history begins at Rev C)}

REV

DATE

DESCRIPTION

PAGE NUMBER

C

9/11

Change to Electrical Characteristics Gate Turn-Off Current

Update to Typical Performance Characteristics graph G06

Update to Pin Functions SDAI (Pin 5/Pin 2) description

Update to Block Diagram

3

6

9

11

Text changes to Operations section

Added Figure 3

12

14

Update to Figure 4

16

14, 17, 18, 22, 24

34

Text changes to Applications Information

Update to Typical Applications Figure 17

D

6/14

Separated V connection of LTC4261 and related components from –48V input plane in circuit figures

1, 13, 20, 22, 27, 31, 34

EE

Added patent numbers

1

3

Changed delay conditions to GATE Open from C

= 1pF

GATE

Layout Considerations section: Added paragraph and Figure 10 on separating local V plane from -48V

23, 24

EE

input plane

42612fd

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnecFtoiornmofoirtsecinircfouirtms aastidoenscwriwbewd.hlienreeainr.wcoillmn/oLtTinCf4rin2g6e1on existing patent rights.

33

LTC4261/LTC4261-2

TYPICAL APPLICATIONS

–48V RTN

R

IN

6 × 0.51k IN SERIES

R3

432k

1%

1/4W EACH

R4

7.5k

5V

ON INTV

V

IN

CC

UVL

UVH

SDAI

SCL

R2

15.8k

V

ADIN2

OV

ADR1

CC

1%

V

C

DD

L

ANODE

R

L

D

LTC4261CGN

IN

330µF

100V

R1

MICRO-

CONTROLLER

SDAO

ADIN

CATHODE V

GND

OUT

11.5k

ADR0

1%

SS

TMR EN V

SENSE GATE DRAIN

RAMP

EE

HCPL-0300

C

TMR

IN

1µF

47nF

R

D

C

R

G

C

F

VCC

SS

C

G

10Ω 1M

33nF

R

1k

0.1µF

220nF

47nF

C

R

S

10nF

100V

5%

0.02Ω

1%

V

OUT

–48V INPUT

Q1

R6

10k 1%

R7

402k 1%

IRF1310NS

4261 F19

Figure 19. Application Circuit of the LTC4261 in Single-Wire Broadcast Mode

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1640AH/LT1640AL

LTC1921

Negative High Voltage Hot Swap Controllers in SO-8 Negative High Voltage Supplies from –10V to –80V

Dual –48V Supply and Fuse Monitor

–48V Hot Swap Controllers in SO-8

–48V Hot Swap Controllers in SOT-23

–48V Hot Swap Controllers in MS8

UV/OV Monitor, –10V to –80V Operation, MSOP Package

Active Current Limiting, Supplies from –18V to –80V

Fast Active Current Limiting, Supplies from –15V

LT4250L/LT4250H

LTC4251/LTC4251-1

LTC4252-1/LTC4252-2

LTC4252A-1/LTC4252A-2

Fast Active Current Limiting, Supplies from –15V,

1ꢀ UV/OV (LTC4252A)

LTC4253

–48V Hot Swap Controller with Sequencer

Fast Current Limiting with Three Sequenced Power Good Outputs,

Supplies from –15V

2

LTC4260

LTC4354

Positive High Voltage Hot Swap Controller

With I C and ADC, Supplies from 8.5V to 80V

Negative Voltage Diode-OR Controller and Monitor

Controls Two N-Channel MOSFETs, 1.2µs Turn-Off, 80V Operation

42612fd

LT 0614 REV D • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

34

For more information www.linear.com/LTC4261

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC4261

●

 LINEAR TECHNOLOGY CORPORATION 2005


型号：	LTC4261_15
厂家：	Linear
描述：	Negative Voltage Hot Swap Controllers with ADC and I2C Monitoring 监控
文件：	总34页 (文件大小：341K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC4261_15 [Linear]

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