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LTC4267CDHC#TRPBF [Linear]

LTC4267 - Power over Ethernet IEEE 802.3af PD Interface with Integrated Switching Regulator; Package: DFN; Pins: 16; Temperature Range: 0°C to 70°C;
LTC4267CDHC#TRPBF
型号： LTC4267CDHC#TRPBF
厂家： Linear    Linear
描述：

LTC4267 - Power over Ethernet IEEE 802.3af PD Interface with Integrated Switching Regulator; Package: DFN; Pins: 16; Temperature Range: 0°C to 70°C

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LTC4270/LTC4271  
++  
+
12-Port PoE/PoE /LTPoE  
PSE Controller  
FeAtures  
Description  
n
12 Independent PSE Channels  
The LTC®4270/LTC4271 chipset is a 12-port power sourc-  
ing equipment (PSE) controller designed for use in IEEE  
802.3at Type 1 and Type 2 (high power) compliant Power  
over Ethernet (PoE) systems. Transformer-isolated com-  
munication protocol replaces expensive opto-couplers  
and complex isolated 3.3V supply resulting in significant  
BOMcostsavings.TheLTC4270/LTC4271chipsetdelivers  
n
Compliant with IEEE 802.3at Type 1 and 2  
n
Chipset Provides Electrical Isolation  
Reduced BOM Cost  
Eliminates up to 6 High Speed Opto-Couplers  
Eliminates Isolated 3.3V Power Supply  
n
Low Power Dissipation  
0.25Ω Sense Resistance Per Channel  
lowest-in-industryheatdissipationbyutilizinglow-R  
external MOSFETs and 0.25Ω sense resistors.  
DS(ON)  
n
Very High Reliability 4-Point PD Detection  
2-Point Forced Voltage  
Advancedpowermanagementfeaturesincludeper-port12-  
bit current monitoring ADCs, DAC-programmable current  
limit, and versatile fast shut-down of preselected ports.  
Advanced power management host software is available  
under a no-cost license. PD discovery uses a proprietary  
dual-mode 4-point detection mechanism ensuring excel-  
lent immunity from false PD detection. Midspan PSEs  
are supported with 2-event classification and a 2 second  
2-Point Forced Current  
n
V
and V  
Monitoring  
EE  
PORT  
n
n
n
n
1 Second Rolling I  
Averaging  
PORT  
Supports 2-Pair and 4-Pair Output Power  
2
1MHz I C Compatible Serial Control Interface  
Available In Three Power Grades  
™
++  
A-Grade – LTPoE  
38.7W to 90W  
+
B-Grade – PoE 25.5W  
2
backoff timer. The LTC4270/LTC4271 includes an I C  
serial interface operable up to 1MHz.  
C-Grade – PoE 13W  
n
Available In 52-Lead 7mm × 8mm (LTC4270)  
and 24-Lead 4mm × 4mm (LTC4271) QFN Packages  
The LTC4270/LTC4271 is available in multiple power  
grades allowing delivered PD power up to 90W.  
ApplicAtions  
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks  
++  
and LTPoE is a trademark of Linear Technology Corporation. All other trademarks are the  
property of their respective owners.  
n
PoE PSE Switches/Routers  
PoE PSE Midspans  
n
typicAl ApplicAtion  
3.3V  
0.1µF  
V
DD33  
XIO0  
XIO1  
OUTn  
GP0  
GP1  
0.22µF  
100V  
S1B  
PORTn  
NO ISOLATION  
REQUIRED ON  
I C INTERFACE  
CPD  
CPA  
LTC4270/LTC4271 FAMILY  
LTC4270  
MID  
2
100Ω  
100Ω  
100Ω  
–54V  
RESET  
MSD  
AUTO  
INT  
•
•
•
•
MAX  
GATEn  
S1B  
–54V  
3.3V  
DELIVERED  
0.25Ω  
100Ω  
++  
+
PoE PoE POWER  
GRADE ISOLATION LTPoE  
SENSEn  
CND  
DPD  
CNA  
DPA  
LTC4271  
LTC4270  
SCL  
SDAIN  
SDAOUT  
l
l
l
l
l
A
B
C
Transformer  
Transformer  
Transformer  
90W  
25.5W  
13W  
0.22µF  
100V  
S1B  
100Ω  
100Ω  
100Ω  
l
PORT1  
OUT1  
3.3V  
–54V  
100Ω  
AD0  
AD1  
AD2  
AD3  
AD6  
S1B  
GATE1  
0.25Ω  
DND  
DNA  
–54V  
SENSE1  
VSSK AGND  
V
DGND  
CAP1  
CAP2  
EE  
2nF 2kV  
1µF  
0.1µF  
+
>47µF  
SYSTEM  
BULK CAP  
1µF  
–54V  
–54V  
42701 TA01a  
42701fb  
1
LTC4270/LTC4271  
Absolute MAxiMuM rAtings ltc4270  
(Note 1, Note 4)  
Supply Voltages  
AGND – V ........................................... –0.3V to 80V  
Operating Ambient Temperature Range  
LTC4270I .............................................–40°C to 85°C  
Junction Temperature (Note 2) ............................ 125°C  
Storage Temperature Range ......................–65 to 150°C  
EE  
VSSK (Note 7) ..................... V – 0.3V to V + 0.3V  
EE  
EE  
Digital Pins  
XIOn ................................. V – 0.3V to CAP2 + 0.3V  
EE  
Analog Pins  
SENSEn, GATEn, OUTn ........ V – 0.3V to V + 80V  
EE  
EE  
EE  
CAP2 (Note 13) ....................... V –0.3V to V + 5V  
EE  
CPA, CNA, DPA, DNA..............V – 0.3V to V + 0.3  
EE  
EE  
Absolute MAxiMuM rAtings ltc4271  
(Note 1)  
Supply Voltages  
Analog Pins  
V
– DGND ......................................... –0.3V to 3.6V  
CAP1 (Note 13) ...........................–0.3V to DGND + 2V  
DD  
Digital Pins  
CPD, CND, DPD, DND ..........DGND – 0.3 to V + 0.3  
DD  
SCL, SDAIN, SDAOUT, INT, RESET, MSD, ADn, AUTO,  
Junction Temperature (Note 2) ............................ 125°C  
MID, GPn ........................DGND – 0.3V to V + 0.3V  
Storage Temperature Range ......................–65 to 150°C  
DD  
Operating Ambient Temperature Range  
LTC4271I..............................................–40°C to 85°C  
42701fb  
2
LTC4270/LTC4271  
pin conFigurAtion  
LTC4270  
LTC4271  
TOP VIEW  
52 51 50 49 48 47 46 45 44 43 42 41  
TOP VIEW  
SENSE1  
GATE1  
OUT1  
1
2
3
4
5
6
7
8
9
40 SENSE12  
39 GATE12  
OUT12  
38  
37  
24 23 22 21 20 19  
18 SCL  
SENSE2  
GATE2  
OUT2  
SENSE11  
AD0  
AD1  
AD2  
AD3  
AD6  
MID  
1
2
3
4
5
6
36 GATE11  
OUT11  
SDAIN  
17  
16  
35  
SDAOUT  
25  
CAP2  
34 AGND  
33 SENSE10  
32 GATE10  
31 OUT10  
30 SENSE9  
29 GATE9  
28 OUT9  
53  
VSSK  
DGND  
15 INT  
SENSE3  
GATE3  
14  
RESET  
13 DNC  
OUT3 10  
SENSE4 11  
GATE4 12  
OUT4 13  
7
8
9 10 11 12  
XIO0 14  
27 XIO1  
UF PACKAGE  
24-LEAD (4mm × 4mm) PLASTIC QFN  
15 16 17 18 19 20 21 22 23 24 25 26  
T
= 125°C, θ = 37°C/W  
JA  
JMAX  
EXPOSED PAD (PIN 25) IS DGND, MUST BE SOLDERED TO PCB  
UKG PACKAGE  
52-LEAD (7mm × 8mm) PLASTIC QFN  
T
= 125°C, θ = 40°C/W  
JA  
JMAX  
EXPOSED PAD (PIN 53) IS VSSK, MUST BE SOLDERED TO PCB  
orDer inForMAtion  
LEAD FREE FINISH  
TAPE AND REEL  
PART MARKING PACKAGE DESCRIPTION  
MAX PWR TEMPERATURE RANGE  
LTC4271IUF#PBF  
LTC4271IUF#TRPBF  
4271  
–40°C to 85°C  
24-Lead (4mm × 4mm) Plastic QFN  
52-Lead (7mm × 8mm) Plastic QFN  
52-Lead (7mm × 8mm) Plastic QFN  
52-Lead (7mm × 8mm) Plastic QFN  
LTC4270AIUKG#PBF  
LTC4270BIUKG#PBF  
LTC4270CIUKG#PBF  
LTC4270AIUKG#TRPBF  
LTC4270BIUKG#TRPBF  
LTC4270CIUKG#TRPBF  
LTC4270AUKG  
LTC4270BUKG  
LTC4270CUKG  
90W  
–40°C to 85°C  
–40°C to 85°C  
–40°C to 85°C  
25.5W  
13W  
Consult LTC Marketing for parts specified with wider operating temperature ranges.  
Consult LTC Marketing for information on non-standard lead based finish parts.  
For more information on lead free part marking, go to: http://www.linear.com/leadfree/  
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/  
42701fb  
3
LTC4270/LTC4271  
electricAl chArActeristics The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.  
(Notes 3 & 4)  
SYMBOL PARAMETER  
CONDITIONS  
AGND – V  
MIN  
TYP  
MAX  
UNITS  
V
EE  
Main PoE Supply Voltage  
EE  
l
l
l
For IEEE Type 1 Compliant Output  
For IEEE Type 2 Compliant Output  
45  
51  
54.75  
57  
57  
57  
V
V
V
++  
For LTPoE Compliant Output  
l
l
l
Undervoltage Lock-Out  
AGND – V  
20  
25  
3.3  
2.7  
1.84  
4.3  
9
30  
V
V
EE  
V
V
Supply Voltage  
V
V
V
V
– DGND  
– DGND  
3.0  
3.6  
DD  
DD  
DD  
Undervoltage Lock-Out  
V
DD  
V
V
Internal Regulator Supply Voltage  
Internal Regulator Supply Voltage  
– DGND  
V
CAP1  
CAP2  
CAP1  
CAP2  
– V  
V
EE  
l
l
l
I
V
V
V
Supply Current  
Supply Resistance  
Supply Current  
(AGND – V ) = 55V  
15  
12  
15  
mA  
kΩ  
mA  
EE  
EE  
EE  
DD  
EE  
R
V
< 15V  
EE  
EE  
I
DD  
(V – DGND) = 3.3V  
DD  
10  
Detection  
l
l
Detection Current – Forced Current First Point, AGND – V  
= 9V  
OUTn  
220  
143  
240  
160  
260  
180  
µA  
µA  
OUTn  
Second Point, AGND – V  
= 3.5V  
Detection Voltage – Forced Voltage AGND – V  
First Point  
, 5µA ≤ I ≤ 500µA  
OUTn  
OUTn  
7
3
8
4
9
5
V
V
l
l
Second Point  
l
l
l
l
l
Detection Current Compliance  
Detection Voltage Compliance  
Detection Voltage Slew Rate  
Min. Valid Signature Resistance  
Max. Valid Signature Resistance  
AGND – V  
AGND – V  
AGND – V  
= 0V  
0.8  
0.9  
12  
mA  
V
OUTn  
OUTn  
V
OC  
, Open Port  
, C = 0.15µF  
10.4  
0.01  
18.5  
32  
V/µs  
kΩ  
kΩ  
OUTn PORT  
15.5  
27.5  
17  
29.7  
Classification  
l
l
V
Classification Voltage  
AGND – V  
, 0mA ≤ I ≤ 50mA  
OUTn  
16.0  
53  
20.5  
67  
V
CLASS  
OUTn  
Classification Current Compliance  
Classification Threshold Current  
V
= AGND  
61  
mA  
OUTn  
l
l
l
l
l
Class 0-1  
Class 1-2  
Class 2-3  
Class 3-4  
5.5  
6.5  
14.5  
23  
33  
48  
7.5  
mA  
mA  
mA  
mA  
mA  
13.5  
21.5  
31.5  
45.2  
15.5  
24.5  
34.9  
50.8  
Class 4-Overcurrent  
AGND – V , 0.1mA ≤ I ≤ 5mA  
CLASS  
l
l
V
MARK  
Classification Mark State Voltage  
Mark State Current Compliance  
7.5  
53  
9
10  
67  
V
OUTn  
V
OUTn  
= AGND  
61  
mA  
Gate Driver  
l
l
GATE Pin Pull-Down Current  
Port Off, V  
Port Off, V  
= V + 5V  
0.4  
mA  
mA  
GATEn  
GATEn  
EE  
= V + 1V  
0.08  
0.12  
30  
EE  
GATE Pin Fast Pull-Down Current  
GATE Pin On Voltage  
V
GATEn  
V
GATEn  
= V + 5V  
mA  
V
EE  
l
– V , I  
= 1µA  
8
12  
14  
EE GATEn  
42701fb  
4
LTC4270/LTC4271  
electricAl chArActeristics The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.  
(Notes 3 & 4)  
SYMBOL PARAMETER  
Output Voltage Sense  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
l
l
V
PG  
Power Good Threshold Voltage  
V
– V  
EE  
2
2.4  
2.8  
V
OUTn  
OUT Pin Pull-Up Resistance to  
AGND  
0V ≤ (AGND – V ) ≤ 5V  
300  
500  
700  
kΩ  
OUT  
V
CUT  
Overcurrent Sense Voltage  
V
– V ,  
SENSEn EE  
l
l
hpen = 0Fh, cutn = D4h  
89  
152  
94  
159  
99  
168  
mV  
mV  
hpen = 0Fh, cutn = E2h (Note 12)  
l
l
l
l
Overcurrent Sense in AUTO Pin  
Mode  
Class 0, Class 3  
Class 1  
89  
26  
94  
28  
99  
30  
mV  
mV  
mV  
mV  
Class 2  
49  
52  
55  
Class 4  
152  
159  
168  
V
LIM  
Active Current Limit in 802.3af  
Compliant Mode  
V
V
– V , hpen = 0Fh, limn = 80h, (AGND–V ) = 55V  
SENSEn  
EE  
EE  
EE  
l
l
< V  
< AGND – 29V  
102  
25  
106  
112  
50  
mV  
mV  
OUT  
AGND – V  
= 0V (Note 12)  
OUT  
Active Current Limit in High Power hpen = 0Fh, limn = C0h, AGND–V = 55V  
EE  
l
l
l
Mode  
V
V
– V = 0 – 10V  
204  
102  
25  
212  
106  
225  
115  
50  
mV  
mV  
mV  
OUT  
EE  
AGND – V  
EE  
+ 23V < V  
< AGND – 29V  
OUT  
= 0V (Note 12)  
OUT  
Active Current Limit in AUTO Pin  
Mode  
V
< V  
< AGND – 10V, AGND–V = 55V  
OUT EE  
EE  
l
l
Class 0 to Class 3  
Class 4  
102  
204  
106  
212  
112  
225  
mV  
mV  
l
l
V
V
DC Disconnect Sense Voltage  
Short-Circuit Sense  
V
V
– V , rdis Bit = 0  
2.6  
1.3  
3.8  
1.9  
4.9  
mV  
mV  
MIN  
SENSE  
SENSE  
EE  
– V , rdis Bit = 1 (Note 12)  
2.45  
EE  
V
– V – V (Note 12)  
EE LIM  
SC  
SENSEn  
l
l
rdis Bit = 0  
rdis bit = 1  
125  
70  
200  
100  
255  
125  
mV  
mV  
Port Current Readback  
Resolution  
No Missing Codes, Reported as 14-Bits  
– V  
12  
Bits  
LSB Weight  
V
30.518  
25.1  
µV/LSB  
SENSEn  
EE  
Conversion Period  
ms/  
Convert  
Port Voltage Readback  
Resolution  
No Missing Codes, Reported as 14-Bits  
– V  
12  
Bits  
LSB Weight  
V
5.8350  
mV/LSB  
SENSEn  
EE  
Digital Interface  
l
l
l
V
Digital Input Low Voltage  
ADn, RESET, MSD, GPn, AUTO, MID (Note 6)  
SCL, SDAIN (Note 6)  
0.8  
1.0  
V
V
V
ILD  
2
I C Input Low Voltage  
V
Digital Input High Voltage  
Digital Output Voltage Low  
(Note 6)  
2.2  
IHD  
l
l
I
I
= 3mA, I = 3mA  
0.4  
0.7  
V
V
SDAOUT  
SDAOUT  
INT  
= 5mA, I = 5mA  
INT  
Internal Pull Up to V  
ADn, RESET, MSD, GPn  
50  
50  
kΩ  
kΩ  
DD  
Internal Pull Down To DGND  
AUTO, MID  
42701fb  
5
LTC4270/LTC4271  
electricAl chArActeristics The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.  
(Notes 3 & 4)  
SYMBOL PARAMETER  
XIO  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
l
l
l
l
V
OLX  
V
OHX  
XIO Digital Output Low  
V
V
V
V
– V , I = 5mA  
EE XIOn  
0.7  
V
V
XIOn  
XIOn  
XIOn  
XIOn  
XIO Digital Output High  
– V , I  
= 100µA  
3.5  
3.4  
EE XIOn  
XIO Digital Input Low Voltage  
XIO Digital Input High Voltage  
Internal Pull Up to CAP2  
– V  
– V  
0.8  
V
EE  
EE  
V
XIO0, XIO1  
50  
kΩ  
PSE Timing Characteristics  
t
t
t
t
t
t
Detection Time  
Beginning To End of Detection (Note 7)  
(Note 7)  
220  
12  
ms  
ms  
ms  
ms  
ms  
ms  
DET  
Class Event Duration  
Class Event Turn On Duration  
Mark Event Duration  
Last Mark Event Duration  
CLE  
l
C
= 0.6µF (Note 7)  
PORT  
0.1  
60  
CLEON  
ME  
(Note 7, Note 11)  
(Note 7, Note 11)  
8.6  
22  
l
l
16  
15  
MEL  
PON  
Power On Delay in AUTO Pin Mode From End of Valid Detect to Application of Power to Port  
(Note 7)  
l
Turn-On Rise Time  
(AGND – V ): 10% to 90% of (AGND - V ) C  
=
24  
µs  
OUT  
EE PORT  
0.15µF (Note 7)  
l
l
l
Turn-On Ramp Rate  
Turn-On Class Transition  
Fault Delay  
C
C
= 0.15µF (Note 7)  
= 0.15µF (Note 7)  
10  
V/µs  
ms  
s
PORT  
PORT  
t
t
0.1  
TOCL  
From I  
(Note 7)  
or I Fault to Next Detect  
1.0  
1.1  
ED  
CUT  
LIM  
l
l
l
Midspan Mode Detection Backoff  
Power Removal Detection Delay  
R
= 15.5kΩ (Note 7)  
2.3  
1.0  
52  
2.5  
1.3  
59  
2.7  
2.5  
66  
s
s
PORT  
From Power Removal After t to Next Detect (Note 7)  
DIS  
t
t
Maximum Current Limit Duration (Note 7)  
During Port Start-Up  
ms  
START  
l
Maximum Overcurrent Duration  
After Port Start-Up  
(Note 7)  
52  
59  
66  
ms  
CUT  
l
l
Maximum Overcurrent Duty Cycle (Note 7)  
5.8  
10  
6.3  
12  
6.7  
14  
%
t
Maximum Current Limit Duration  
After Port Start-Up – t Enabled  
t
= 1 (Note 7, Note 12)  
ms  
LIM  
LIM  
LIM  
l
l
l
Maximum Current Limit Duration  
t
= 0 (Note 7, Note 12)  
52  
1.6  
320  
59  
66  
3.6  
380  
ms  
ms  
ms  
LIM  
After Port Start-Up – t as t  
LIM  
CUT  
t
t
t
Maintain Power Signature (MPS)  
Pulse Width Sensitivity  
Current Pulse Width to Reset Disconnect Timer (Note 7,  
Note 8)  
MPS  
Maintain Power Signature (MPS)  
Dropout Time  
(Note 7, Note 5)  
350  
2
DIS  
Masked Shut Down Delay  
(Note 7)  
(Note 7)  
6.5  
3
µs  
s
MSD  
2
l
l
I C Watchdog Timer Duration  
1.5  
3
Minimum Pulse Width for Masked (Note 7)  
Shut Down  
µs  
l
Minimum Pulse Width for RESET (Note 7)  
4.5  
µs  
42701fb  
6
LTC4270/LTC4271  
electricAl chArActeristics The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V and VDD – DGND = 3.3V unless otherwise noted.  
(Notes 3 & 4)  
SYMBOL PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
2
I C Timing  
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
t
t
Clock Frequency  
(Note 7)  
1
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
µs  
ns  
SCLK  
Bus Free Time  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
Figure 5 (Notes 7, 9)  
(Notes 7, 9, 10)  
480  
240  
480  
240  
60  
1
2
3
4
5
5
6
7
8
r
Start Hold Time  
SCL Low Time  
SCL High Time  
SDAIN Data Hold Time  
Data Clock to SDAOUT Valid  
Data Set-Up Time  
130  
80  
Start Set-Up Time  
240  
240  
Stop Set-Up Time  
SCL, SDAIN Rise Time  
SCL, SDAIN Fall Time  
Fault Present to INT Pin Low  
Stop Condition to INT Pin Low  
ARA to INT Pin High Time  
SCL Fall to ACK Low  
120  
60  
f
150  
1.5  
1.5  
130  
(Notes 7, 9, 10)  
(Notes 7, 9)  
(Notes 7, 9)  
Note 1: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. With the exception of (V  
DGND), exposure to any Absolute Maximum Rating condition for extended  
periods may affect device reliability and lifetime.  
Note 7: Guaranteed by design, not subject to test.  
Note 8: The IEEE 802.3af specification allows a PD to present its  
Maintain Power Signature (MPS) on an intermittent basis without being  
disconnected. In order to stay powered, the PD must present the MPS for  
–
DD  
Note 2: This IC includes overtemperature protection that is intended  
to protect the device during momentary overload conditions. Junction  
temperature will exceed 140ºC when overtemperature protection is active.  
Continuous operation above the specified maximum operating junction  
temperature may impair device reliability.  
Note 3: All currents into device pins are positive; all currents out of device  
pins are negative.  
Note 4: The LTC4270 operates with a negative supply voltage (with  
respect to AGND). To avoid confusion, voltages in this data sheet are  
referred to in terms of absolute magnitude.  
t
within any t  
time window.  
MPS  
MPDO  
Note 9: Values Measured at V and V  
Note 10: If a fault condition occurs during an I C transaction, the INT pin  
will not be pulled down until a stop condition is present on the I C bus.  
Note 11: Load characteristics of the LTC4270 during Mark: 7V < (AGND –  
ILD  
IHD  
2
2
V
) < 10V or I  
OUTn  
< 50µA.  
OUT  
Note 12: See the LTC4271 Software Programming documentation for  
information on serial bus usage and device configuration and status  
registers.  
Note 13: Do not source or sink current from CAP1 and CAP2.  
Note 5: t is the same as t  
defined by IEEE 802.3at  
DIS  
MPDO  
Note 6: The LTC4271 digital interface operates with respect to DGND. All  
logic levels are measured with respect to DGND.  
42701fb  
7
LTC4270/LTC4271  
typicAl perForMAnce chArActeristics  
802.3af Power On Sequence in  
AUTO Pin Mode  
802.3at Power On Sequence in  
AUTO Pin Mode  
Power On Sequence with 10VPP  
60Hz Noise  
0
–10  
–20  
–30  
–40  
–50  
–60  
0
–10  
–20  
–30  
–40  
–50  
–60  
5
0
AGND  
AGND  
PORT OFF  
FORCED VOLTAGE  
DETECTION  
AGND  
FORCED CURRENT  
DETECTION  
FORCED CURRENT  
DETECTION  
–5  
FORCED VOLTAGE  
DETECTION  
FORCED VOLTAGE  
DETECTION  
–10  
–15  
–20  
–25  
FORCED CURRENT  
DETECTION  
VEE = –55V  
CLASS 4 PD  
VEE = –55V  
CLASS 3 PD  
802.3af  
CLASSIFICATION  
802.3at  
CLASSIFICATION  
802.3af  
CLASSIFICATION  
POWER ON  
50ms/DIV  
POWER ON  
VEE  
VEE  
DETECT WITH 60Hz NOISE  
NORMAL DETECT  
POWER ON  
50ms/DIV  
50ms/DIV  
42701 G01  
42701 G02  
42701 G03  
Classification Transient Response  
to 40mA Load Step  
Powering Up into a 180µF Load  
VEE = –54V  
Classification Current Compliance  
0
AGND  
V
DD  
V
EE  
= 3.3V  
= –54V  
–2  
–4  
40mA  
PORT  
CURRENT  
20mA/DIV  
PORT VOLTAGE  
20V/DIV  
–6  
VEE  
0mA  
–8  
LOAD FULLY CHARGED  
–10  
–12  
–14  
–16  
–18  
–20  
PORT CURRENT  
200mA/DIV  
FOLDBACK  
425mA  
CURRENT LIMIT  
PORT  
VOLTAGE  
1V/DIV  
0mA  
GATE VOLTAGE  
10V/DIV  
FET ON  
–20V  
VEE  
0
10  
20  
30  
40  
50  
60  
70  
50µs/DIV  
5ms/DIV  
CLASSIFICATION CURRENT (mA)  
42701 G04  
42701 G05  
42701 G06  
VDD Supply Current vs Voltage  
VEE Supply Current vs Voltage  
15.0  
12.0  
9.0  
9.0  
8.5  
8.0  
7.5  
7.0  
6.5  
6.0  
6.0  
3.0  
0.0  
85°C  
25°C  
–40  
85°C  
25°C  
–40  
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6  
–60  
–50  
–40  
–30  
–20  
V
SUPPLY VOLTAGE (V)  
V
SUPPLY VOLTAGE (V)  
DD  
EE  
42701 G07  
42701 G08  
42701fb  
8
LTC4270/LTC4271  
typicAl perForMAnce chArActeristics  
802.3at ILIM Threshold  
vs Temperature  
802.3at ICUT Threshold  
vs Temperature  
166  
164  
162  
160  
158  
156  
154  
152  
664  
656  
648  
640  
632  
624  
616  
608  
220  
880  
864  
848  
832  
816  
PORT 1  
PORT 1  
REG 47h = E2h  
REG 48h = C0h  
R
SENSE  
= 0.25Ω  
R
SENSE  
= 0.25Ω  
216  
212  
208  
204  
–40 –20  
0
20 40 60 80 100 120  
TEMPERATURE (°C)  
–40 –20  
0
20 40 60 80 100 120  
TEMPERATURE (°C)  
42701 G10  
42701 G09  
DC Disconnect Threshold  
vs Temperature  
802.3at Current Limit Foldback  
2.50  
2.25  
2.00  
1.75  
1.50  
1.25  
10  
9
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
225  
200  
175  
150  
125  
100  
75  
PORT 1  
PORT 1  
REG 48h = C0h  
R = 0.25Ω  
SENSE  
REG 47h = E2h  
R
SENSE  
= 0.25Ω  
8
7
50  
6
25  
5
0
–40 –20  
0
20 40 60 80 100 120  
TEMPERATURE (°C)  
–54  
–45  
–36  
–27  
–18  
–9  
0
V
(V)  
OUTn  
42701 G11  
42701 G12  
INT and SDAOUT Pull Down  
Voltage vs Load Current  
MOSFET Gate Drive With Fast  
Pull Down  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
GND  
V
V
= 3.3V  
= –54V  
DD  
EE  
PORT  
VOLTAGE  
20V/DIV  
V
V
EE  
EE  
FAST PULL DOWN  
GATE  
VOLTAGE  
10V/DIV  
CURRENT LIMIT  
50Ω  
FAULT  
APPLIED  
PORT  
CURRENT  
500mA/DIV  
50Ω FAULT REMOVED  
0mA  
0.0  
0
10  
20  
30  
40  
50  
60  
100µs/DIV  
LOAD CURRENT (mA)  
42701 G14  
42701 G13  
42701fb  
9
LTC4270/LTC4271  
test tiMing DiAgrAMs  
t
CLASSIFICATION  
DET  
FORCED-  
VOLTAGE  
FORCED-CURRENT  
0V  
t
ME  
V
t
PORTn  
MEL  
V
OC  
V
MARK  
15.5V  
20.5V  
V
CLASS  
t
CLE  
t
CLE  
PD  
CONNECTED  
t
CLEON  
t
PON  
V
EE  
INT  
42701 F01  
Figure 1. Detect, Class and Turn-On Timing in AUTO Pin or Semi-auto Modes  
V
LIM  
0V  
V
CUT  
V
TO V  
EE  
SENSEn  
t
, t  
START CUT  
INT  
42701 F02  
Figure 2. Current Limit Timing  
V
SENSEn  
V
MIN  
TO V  
EE  
INT  
t
t
DIS  
MPS  
42701 F03  
Figure 3. DC Disconnect Timing  
42701fb  
10  
LTC4270/LTC4271  
test tiMing DiAgrAMs  
V
GATEn  
V
EE  
t
MSD  
MSD  
42701 F04  
Figure 4. Shut Down Delay Timing  
t
t
r
3
t
t
f
4
SCL  
t
t
t
t
t
5
6
7
8
2
SDA  
42701 F05  
t
1
Figure 5. I2C Interface Timing  
42701fb  
11  
LTC4270/LTC4271  
i2c tiMing DiAgrAMs  
SCL  
SDA  
AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0  
ACK  
AD6  
1
0
START BY  
MASTER  
ACK BY  
SLAVE  
ACK BY  
SLAVE  
ACK BY  
SLAVE  
STOP BY  
MASTER  
FRAME 1  
SERIAL BUS ADDRESS BYTE  
FRAME 2  
REGISTER ADDRESS BYTE  
FRAME 3  
DATA BYTE  
42701 F06  
Figure 6. Writing to a Register  
SCL  
SDA  
AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK  
AD6  
AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK  
AD6  
1
0
1
0
START BY  
MASTER  
ACK BY  
SLAVE  
ACK BY  
SLAVE  
REPEATED  
START BY  
MASTER  
ACK BY  
SLAVE  
NO ACK BY  
MASTER  
STOP BY  
MASTER  
FRAME 1  
SERIAL BUS ADDRESS BYTE  
FRAME 2  
REGISTER ADDRESS BYTE  
FRAME 1  
FRAME 2  
DATA BYTE  
SERIAL BUS ADDRESS BYTE  
42701 F07  
Figure 7. Reading from a Register  
SCL  
SDA  
AD6  
1
0
AD3 AD2 AD1 AD0 R/W  
FRAME 1  
ACK  
D7 D6 D5 D4 D3 D2 D1 D0  
ACK  
STOP BY  
MASTER  
START BY  
MASTER  
ACK BY  
SLAVE  
NO ACK BY  
MASTER  
FRAME 2  
DATA BYTE  
SERIAL BUS ADDRESS BYTE  
42701 F08  
Figure 8. Reading the Interrupt Register (Short Form)  
SCL  
SDA  
0
0
0
1
1
0
0
R/W  
ACK  
AD6  
1
0
AD3 AD2 AD1 AD0  
1
ACK  
STOP BY  
MASTER  
START BY  
MASTER  
ACK BY  
SLAVE  
NO ACK BY  
MASTER  
FRAME 1  
ALERT RESPONSE ADDRESS BYTE  
FRAME 2  
SERIAL BUS ADDRESS BYTE  
42701 F09  
Figure 9. Reading from Alert Response Address  
42701fb  
12  
LTC4270/LTC4271  
pin Functions  
LTC4270  
AGND (Pin 34): Analog Ground. Connect AGND to the  
return for the V supply.  
EE  
SENSEn (Pins 1, 4, 8, 11, 15, 18, 21, 24, 30, 33, 37,  
40): Port n Current Sense Input. SENSEn monitors the  
external MOSFET current via a 0.5Ω or 0.25Ω sense  
V (Pins 41, 51, 52): Main PoE Supply Input. Connect to  
EE  
a –45V to –57V supply, relative to AGND. Voltage depends  
++  
resistor between SENSEn and V . Whenever the voltage  
on PSE type (Type 1, Type 2 or LTPoE .)  
EE  
acrossthesenseresistorexceedstheovercurrentdetection  
DNA (Pin 47): Data Transceiver Negative Input Output  
(Analog). Connect to DND through a data transformer.  
threshold V , the current limit fault timer counts up. If  
CUT  
the voltage across the sense resistor reaches the current  
DPA (Pin 48): Data Transceiver Positive Input Output  
(Analog). Connect to DPD through a data transformer.  
limit threshold V , the GATEn pin voltage is lowered to  
LIM  
maintain constant current in the external MOSFET. See  
Applications Information for further details. If the port is  
CNA (Pin 49): Clock Transceiver Negative Input Output  
(Analog). Connect to CND through a data transformer.  
unused, the SENSEn pin must be tied to V .  
EE  
GATEn (Pins 2, 5, 9, 12, 16, 19, 22, 25, 29, 32, 36, 39):  
Port n Gate Drive. GATEn should be connected to the gate  
of the external MOSFET for port n. When the MOSFET is  
turned on, the gate voltage is driven to 12V (typ) above  
CPA (Pin 50): Clock Transceiver Positive Input Output  
(Analog). Connect to CPD through a data transformer.  
VSSK(ExposedPadPin53):KelvinSensetoV . Connect  
EE  
to sense resistor common node. Do not connect directly  
V . During a current limit condition, the voltage at GATEn  
EE  
to V plane. See Layout Guide.  
EE  
will be reduced to maintain constant current through the  
externalMOSFET.Ifthefaulttimerexpires,GATEnispulled  
down, turning the MOSFET off and recording a port fault  
event. If the port is unused, float the GATEn pin.  
Common Pins  
NC, DNC (LTC4271 Pins 7,13; LTC4270 Pins 42, 43, 44,  
45, 46): All pins identified with “NC” or “DNC” must be  
left unconnected.  
OUTn (Pins 3, 6, 10, 13, 17, 20, 23, 26, 28, 31, 35, 38):  
PortnOutputVoltageMonitor.OUTnshouldbeconnected  
to the output port. A current limit foldback circuit limits  
the power dissipation in the external MOSFET by reducing  
the current limit threshold when the drain-to-source volt-  
age exceeds 10V. The port n Power Good bit is set when  
LTC4271  
AD0(Pin1):AddressBit0.Tietheaddresspinshighorlow  
2
to set the starting I C serial address to which the LTC4271  
responds. The chip will respond to this address plus the  
next two incremental addresses. The base address of the  
the voltage from OUTn to V drops below 2.4V (typ). A  
EE  
500k resistor is connected internally from OUTn to AGND  
when the port is idle. If the port is unused, the OUTn pin  
must be floated.  
first four ports will be (A 10A A A A )b. The second and  
6 3 2 1 0  
third groups of four ports will respond at the next two  
logical addresses. Internally pulled up to V .  
DD  
CAP2 (Pin 7): Analog Internal 4.3V Power Supply Bypass  
AD1 (Pin 2): Address Bit 1. See AD0.  
AD2 (Pin 3): Address Bit 2. See AD0.  
AD3 (Pin 4): Address Bit 3. See AD0.  
AD6 (Pin 5): Address Bit 6. See AD0.  
Capacitor. Connect 0.1µF ceramic cap to V .  
EE  
XIO0(Pin14):GeneralPurposeDigitalInputOutput.Logic  
signal between V and V + 4.3V. Internal pull up.  
EE  
EE  
XIO1(Pin27):GeneralPurposeDigitalInputOutput.Logic  
signal between V and V + 4.3V. Internal pull up.  
MID(Pin6):MidspanModeInput.Whenhigh,theLTC4271  
actsasamidspandevice. InternallypulleddowntoDGND.  
EE  
EE  
42701fb  
13  
LTC4270/LTC4271  
pin Functions  
CPD (Pin 8): Clock Transceiver Positive Input Output  
(Digital). Connect to CPA through a data transformer.  
See Applications Information for more information.  
SDAIN (Pin 17): Serial Data Input. High impedance data  
2
CND (Pin 9): Clock Transceiver Negative Input Output  
(Digital). Connect to CNA through a data transformer.  
inputfortheI Cserialinterfacebus.TheLTC4271usestwo  
pinstoimplementthebidirectionalSDAfunctiontosimplify  
2
optoisolation of the I C bus. To implement a standard  
DPD (Pin 10): Data Transceiver Positive Input Output  
(Digital). Connect to DPA through a data transformer.  
bidirectional SDA pin, tie SDAOUT and SDAIN together.  
See Applications Information for more information.  
DND (Pin 11): Data Transceiver Negative Input Output  
(Digital). Connect to DNA through a data transformer.  
SCL (Pin 18): Serial Clock Input. High impedance clock  
2
input for the I C serial interface bus. The SCL pin should  
2
V
(Pins 12, 20): V IO Power Supply. Connect to  
DD  
be connected directly to the I C SCL bus line. SCL must  
DD33  
2
a 3.3V power supply relative to DGND. V  
must be  
be tied high if the I C serial interface bus is not used.  
DD33  
bypassed to DGND near the LTC4271 with at least a 0.1μF  
capacitor.  
CAP1(Pin19):CorePowerSupplyBypassCapacitor.Con-  
nect a 1µF Bypass capacitance to DGND for the internal  
1.8V regulator. Do not use other capacitor values.  
RESET(Pin14):ResetInput,ActiveLow.WhentheRESET  
pin is low, the LTC4270/LTC4271 is held inactive with all  
ports off and all internal registers reset to their power-up  
states. When RESET is pulled high, the LTC4271 begins  
normal operation. RESET can be connected to an external  
capacitor or RC network to provide a power turn-on delay.  
Internal filtering of the RESET pin prevents glitches less  
than 1μs wide from resetting the LTC4270/LTC4271.  
AUTO (Pin 21): AUTO Pin Mode Input. AUTO pin mode  
allows the LTC4271 to detect and power up a PD even if  
2
there is no host controller present on the I C bus. The  
AUTO pin determines the state of the internal registers  
when the LTC4271 is reset or comes out of V UVLO  
DD  
(seeLTC4271SoftwareProgrammingdocumentation).The  
states of these register bits can subsequently be changed  
Internally pulled up to V .  
DD  
2
viatheI Cinterface.InternallypulleddowntoDGND.Must  
INT (Pin 15): Interrupt Output, Open Drain. INT will pull  
low when any one of several events occur in the LTC4271.  
It will return to a high impedance state when bits 6 or 7  
are set in the Reset PB register (1Ah). The INT signal can  
be used to generate an interrupt to the host processor,  
eliminating the need for continuous software polling. In-  
dividual INT events can be disabled using the INT Mask  
register (01h). See LTC4271 Software Programming  
documentation for more information. The INT pin is only  
be tied locally to either V or DGND.  
DD  
GP1 (Pin 22): General Purpose Digital Input Output for  
customer applications. Referenced to DGND.  
GP0 (Pin 23): General Purpose Digital Input Output for  
customer applications. Referenced to DGND.  
MSD (Pin 24): Maskable Shutdown Input. Active low.  
When pulled low, all ports that have their corresponding  
mask bit set in the mconfig register (17h) will be reset.  
Internal filtering of the MSD pin prevents glitches less  
than 1μs wide from resetting ports. The MSD Pin Mode  
register can configure the MSD pin polarity. Internally  
2
updated between I C transactions.  
SDAOUT (Pin 16): Serial Data Output, Open Drain Data  
2
Output for the I C Serial Interface Bus. The LTC4271 uses  
two pins to implement the bidirectional SDA function to  
pulled up to V .  
DD  
2
simplify optoisolation of the I C bus. To implement a stan-  
DGND(ExposedPadPin25):DigitalGround.DGNDshould  
dardbidirectionalSDApin,tieSDAOUTandSDAINtogether.  
be connected to the return from the V supply.  
DD  
42701fb  
14  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
OVERVIEW  
++  
to 90W of delivered power to a LTPoE PD. The LTPoE  
++  
specification provides reliable detection and classification  
extensions to the existing IEEE PoE protocols that are  
backwardcompatibleandinteroperablewithexistingType  
PoweroverEthernet,orPoE,isastandardprotocolforsend-  
ing DC power over copper Ethernet data wiring. The IEEE  
group that administers the 802.3 Ethernet data standards  
added PoE powering capability in 2003. This original PoE  
spec, known as 802.3af, allowed for 48V DC power at up  
to 13W. This initial specification was widely popular, but  
13W was not adequate for some requirements. In 2009,  
the IEEE released a new standard, known as 802.3at or  
++  
1andType2PDs.UnlikeotherproprietaryPoE solutions  
++  
Linear’s LTPoE provides mutual identification between  
++  
the PSE and PD. This ensures the LTPoE PD knows it  
may use the requested power at start-up because it has  
++  
++  
detected a LTPoE PSE. LTPoE PSEs can differentiate  
++  
between a LTPoE PD and all other types of IEEE compli-  
+
PoE , increasing the voltage and current requirements to  
++  
ant PDs allowing LTPoE PSEs to remain compliant and  
provide 25W of power.  
interoperable with existing equipment.  
The IEEE standard also defines PoE terminology. A device  
that provides power to the network is known as a PSE, or  
powersourcingequipment,whileadevicethatdrawspower  
from the network is known as a PD, or powered device.  
PSEs come in two types: Endpoints (typically network  
switches or routers), which provide data and power; and  
Midspans, which provide power but pass through data.  
MidspansaretypicallyusedtoaddPoEcapabilitytoexisting  
non-PoE networks. PDs are typically IP phones, wireless  
access points, security cameras, and similar devices.  
LTC4270/LTC4271 Product Family  
The LTC4270/LTC4271 family is a fourth generation  
12-port PSE controller that implements 12 PSE ports in  
either an endpoint or midspan design. Virtually all neces-  
sary circuitry is included to implement an IEEE 802.3at  
compliant PSE design, requiring only an external power  
MOSFET and sense resistor per channel; these minimize  
power loss compared to alternative designs with onboard  
MOSFETs and increase system reliability in the event a  
single channel fails.  
++  
PoE Evolution  
All grades of the LTC4270/LTC4271 family offer advanced  
fourth generation PSE features, including per-port cur-  
+
Even during the process of creating the IEEE PoE 25.5W  
specification it became clear that there was a significant  
and increasing need for more than 25.5W of delivered  
power. The A-grade LTC4270/LTC4271 chipset responds  
to this market by allowing a reliable means of providing up  
rent monitoring, V monitoring, port current policing,  
EE  
one second current averaging and four general purpose  
input/output pins.  
CAT 5  
20Ω MAX  
ROUNDTRIP  
0.05µF MAX  
PSE  
PD  
RJ45  
4
RJ45  
4
5
5
GND  
1N4002  
SPARE PAIR  
×4  
0.22µF  
100V  
X7R  
1
1
DGND  
AGND  
5µF ≤ C  
IN  
≤ 300µF  
SMAJ58A  
58V  
Tx  
Rx  
Tx  
3.3V  
V
DD33  
INT  
1/12  
LTC4270/  
LTC4271  
2
3
2
3
INTERRUPT  
DATA PAIR  
DATA PAIR  
SMAJ58A  
SCL  
SDAIN  
SDAOUT  
2
I C  
0.1µF  
1N4002  
×4  
Rx  
V
EE  
SENSE GATE OUT  
1µF  
GND  
6
6
100V  
X7R  
DC/DC  
CONVERTER  
R
CLASS  
PWRGD  
+
OUT  
S1B  
V
0.25Ω  
LTC4265  
–48V  
7
8
7
–48V  
–48V  
OUT  
–
IN  
8
S1B  
SPARE PAIR  
42701 F10  
Figure 10. Power over Ethernet System Diagram  
42701fb  
15  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
The LTC4270/LTC4271 chipset implements a proprietary  
isolation scheme for inter-chip communication. This  
architecture dramatically reduces BOM cost by replacing  
expensiveopto-isolatorsandisolatedpowersupplieswith  
a single low-cost transformer.  
resistance and turns on the power. When the PD is later  
disconnected, the PSE senses the open circuit and turns  
power off. The PSE also turns off power in the event of a  
current fault or short circuit.  
When a PD is detected, the PSE optionally looks for a  
classification signature that tells the PSE the maximum  
power the PD will draw. The PSE can use this information  
toallocatepoweramongseveralports,topolicethecurrent  
consumptionofthePD,ortorejectaPDthatwilldrawmore  
power than the PSE has available. The classification step  
is optional; if a PSE chooses not to classify a PD, it must  
assume that the PD is a 13W (full 802.3af power) device.  
The LTC4270/LTC4271 comes in three grades which sup-  
port different PD power levels.  
The A-grade LTC4270/LTC4271 chipset extends PoE  
++  
++  
power delivery capabilities to LTPoE levels. LTPoE  
is a Linear Technology proprietary specification allowing  
++  
for the delivery of up to 90W to LTPoE compliant PDs.  
++  
TheLTPoE architectureextendstheIEEEphysicalpower  
negotiationtoinclude38.7W,52.7W,70Wand90Wpower  
levels. The A-grade LTC4270/LTC4271 also incorporates  
all B- and C-grade features.  
New in 802.3at  
Thenewer802.3atstandardsupersedes802.3afandbrings  
several new features:  
The B-grade LTC4270/LTC4271 is a fully IEEE-compliant  
Type 2 PSE supporting autonomous detection, classifica-  
tion and powering of Type 1 and Type 2 PDs. The B-grade  
LTC4270/LTC4271alsoincorporatesallC-grade features.  
A PD may draw as much as 25.5W. Such PDs (and the  
PSEs that support them) are known as Type 2. Older  
13W 802.3af equipment is classified as Type 1. Type 1  
PDs will work with all PSEs; Type 2 PDs may require  
Type 2 PSEs to work properly. The LTC4270/LTC4271  
is designed to work in both Type 1 and Type 2 PSE de-  
signs, and also supports non-standard configurations  
at higher power levels.  
The C-grade LTC4270/LTC4271 is a fully autonomous  
802.3af Type 1 PSE solution. Intended for use only with  
theAUTOpintiedhigh, theC-gradechipsetautonomously  
supports detection, classification and powering of Type 1  
PDs.AsaType1PSE,twoeventclassificationisprohibited  
and Class 4 PDs are automatically treated as Class 0 PDs.  
The Classification protocol is expanded to allow Type 2  
PSEs to detect Type 2 PDs, and to allow Type 2 PDs to  
determine if they are connected to a Type 2 PSE. Two  
versions of the new Classification protocol are avail-  
able: an expanded version of the 802.3af Class Pulse  
protocol, and an alternate method integrated with the  
existing LLDP protocol (using the Ethernet data path).  
The LTC4270/LTC4271 fully supports the new Class  
Pulse protocol and is also compatible with the LLDP  
protocol(whichisimplementedinthedatacommunica-  
tions layer, not in the PoE circuitry).  
PoE BASICS  
Common Ethernet data connections consist of two or four  
twisted pairs of copper wire (commonly known as CAT-5  
cable), transformer-coupled at each end to avoid ground  
loops. PoE systems take advantage of this coupling ar-  
rangement by applying voltage between the center-taps  
of the data transformers to transmit power from the PSE  
to the PD without affecting data transmission. Figure 10  
shows a high level PoE system schematic.  
Fault protection current levels and timing are adjusted to  
reduce peak power in the MOSFET during a fault; this  
allows the new 25.5W power levels to be reached using  
the same MOSFETs as older 13W designs.  
To avoid damaging legacy data equipment that does not  
expect to see DC voltage, the PoE spec defines a protocol  
that determines when the PSE may apply and remove  
power. Valid PDs are required to have a specific 25k  
common mode resistance at their input. When such a PD  
is connected to the cable, the PSE detects this signature  
42701fb  
16  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
Extended Power LTPoE  
++  
OPERATING MODES  
A-grade LTC4270/LTC4271 parts add the capability to  
autonomously deliver up to 90W of power to the PD.  
The LTC4270/LTC4271 includes 12 independent ports,  
each of which can operate in one of four modes: manual,  
semi-auto, AUTO pin, or shutdown.  
++  
LTPoE PDs may forgoe 802.3 LLDP support and rely  
++  
solely on the LTPoE Physical Classification to negotiate  
Table 2. Operating Modes  
++  
power with LTPoE PSEs; this greatly simplifies high-  
MODE  
AUTO OPMD DETECT/ POWER-UP  
AUTOMATIC  
/I  
power PD implementations.  
PIN  
CLASS  
I
CUT LIM  
ASSIGNMENT  
++  
LTPoE may be optionally enabled for A-grade LTC4270/  
AUTO Pin  
1
11b  
Enabled Automatically  
at Reset  
Yes  
LTC4271s by setting both the High Power Enable and  
++  
LTPoE Enable bits.  
Reserved  
Semi-auto  
0
0
11b  
10b  
N/A  
N/A  
N/A  
No  
++  
The higher levels of LTPoE delivery impose additional  
layout and component selection constraints. LTC4270 pin  
selectsallowtheAUTOpinmodeLTC4271toautonomously  
power up to supported power levels. If the AUTO pin is  
high, the XIO1 and XIO0 pins are sampled at reset to de-  
termine the maximum deliverable power. PDs requesting  
more than the available power limits are not powered.  
Host  
Enabled  
Upon  
Request  
Manual  
0
01b  
Once  
Upon  
Request  
Upon  
Request  
No  
Shutdown  
0
00b  
Disabled  
Disabled  
No  
In manual mode, the port waits for instructions from the  
host system before taking any action. It runs a single  
detection or classification cycle when commanded to by  
the host, and reports the result in its Port Status register.  
The host system can command the port to turn on or off  
the power at any time.  
++  
Table 1. LTPoE AUTO Pin Mode Maximum Delivered Power  
Capabilities  
POWER  
38.7W  
52.7W  
70W  
XIO1  
XIO0  
0
0
1
1
0
1
0
1
In semi-auto mode, the port repeatedly attempts to detect  
and classify any PD attached to it. It reports the status of  
these attempts back to the host, and waits for a command  
from the host before turning on power to the port. The  
host must enable detection (and optionally classification)  
for the port before detection will start.  
90W  
BACKWARDS COMPATIBILITY  
TheLTC4270/LTC4271chipsetisdesignedtobebackward  
compatible with the LTC4266, operating in Type 2 mode,  
without software changes; only minor layout changes  
are required to implement a fully compliant IEEE 802.3at  
design.  
AUTO pin mode operates the same as semi-auto mode  
except it will automatically turn on the power to the port if  
detectionissuccessful.AUTOpinmodewillautonomously  
set the I  
and I values based on the class result. This  
CUT  
LIM  
operational mode is only valid if the AUTO pin is high at  
Some LTC4266 registers have been obsoleted in the  
LTC4270/LTC4271chipset.Theobsoletedregistersarenot  
required for 802.3at compliant PSE operation. For more  
details about software differences between the LTC4266  
and LTC4270/LTC4271, refer to the LTC4271 Software  
Programming document.  
reset or power-up and remains high during operation.  
In shutdown mode, the port is disabled and will not detect  
or power a PD.  
Regardless of which mode it is in, the LTC4270/LTC4271  
will remove power automatically from any port that gener-  
ates a current limit fault. It will also automatically remove  
power from any port that generates a disconnect event if  
disconnect detection is enabled. The host controller may  
Operation with high power mode disabled is obsoleted in  
the LTC4270/LTC4271 chipset. All operations previously  
available in low power mode are fully implemented as a  
subset of the high power mode capabilities.  
also command the port to remove power at any time.  
42701fb  
17  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
Reset and the AUTO/MID Pins  
10V. The PSE must accept resistances that fall between  
19k and 26.5k, and it must reject resistances above 33k  
or below 15k (shaded regions in Figure 11). The PSE may  
choose to accept or reject resistances in the undefined  
areasbetweenthemust-acceptandmust-rejectranges. In  
particular,thePSEmustrejectstandardcomputernetwork  
ports, manyofwhichhave150Ωcommon-modetermina-  
tion resistors that will be damaged if power is applied to  
them (the black region at the left of Figure 11).  
The initial LTC4270/LTC4271 configuration depends on  
the state of the AUTO and MID pins during reset. Reset  
occurs at power-up, or whenever the RESET pin is pulled  
low or the global Reset All bit is set. Changing the state of  
AUTO or MID after power-up will not properly change the  
portbehavioroftheLTC4270/LTC4271untilaresetoccurs.  
Althoughtypicallyusedwithahostcontroller,theLTC4270/  
LTC4271 can also be used in a standalone mode with no  
connection to the serial interface. If there is no host pres-  
ent, the AUTO pin must be tied high so that, at reset, all  
portswillbeconfiguredtooperateautomatically.Eachport  
will detect and classify repeatedly until a PD is discovered,  
RESISTANCE 0Ω  
10k  
20k  
30k  
150Ω (NIC)  
23.75k  
26.25k  
26.5k  
PD  
PSE  
15k 19k  
33k  
42701 F11  
set I  
and I  
according to the classification results,  
CUT  
LIM  
Figure 11. IEEE 802.3af Signature Resistance Ranges  
apply power to valid PDs, and remove power when a PD  
is disconnected.  
4-Point Detection  
Table 3 shows the I  
and I  
values that will be auto-  
LIM  
CUT  
matically set in standalone (AUTO pin) mode, based on  
the discovered class.  
TheLTC4270/LTC4271usesa4-pointdetectionmethodto  
discover PDs. False-positive detections are minimized by  
checkingforsignatureresistancewithbothforced-current  
and forced-voltage measurements.  
Table 3. ICUT and ILIM Values in Standalone Mode  
CLASS  
Class 1  
ICUT  
ILIM  
112mA  
206mA  
375mA  
638mA  
425mA  
425mA  
425mA  
850mA  
Initially, two test currents are forced onto the port (via the  
OUTn pin) and the resulting voltages are measured. The  
detectioncircuitrysubtractsthetwoV-Ipointstodetermine  
the resistive slope while removing offset caused by series  
diodes or leakage at the port (see Figure 12). If the forced-  
current detection yields a valid signature resistance, two  
test voltages are then forced onto the port and the result-  
ing currents are measured and subtracted. Both methods  
must report valid resistances for the port to report a valid  
detection. PD signature resistances between 17k and 29k  
(typically) are detected as valid and reported as Detect  
Good in the corresponding Port Status register. Values  
outside this range, including open and short circuits, are  
also reported. If the port measures less than 1V at the  
first forced-current test, the detection cycle will abort and  
Short Circuit will be reported. Table 4 shows the possible  
detection results.  
Class 2  
Class 3 or 0  
Class 4  
The automatic setting of I  
and I values only occurs  
LIM  
CUT  
if the LTC4270/LTC4271 is reset with the AUTO pin high.  
Ifthestandaloneapplicationisamidspan,theMIDpinmust  
be tied high to enable correct midspan detection timing.  
DETECTION  
Detection Overview  
To avoiddamagingnetworkdevicesthatwerenotdesigned  
to tolerate DC voltage, a PSE must determine whether the  
connected device is a real PD before applying power. The  
IEEEspecificationrequiresthatavalidPDhaveacommon-  
mode resistance of 25k 5% at any port voltage below  
42701fb  
18  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
a power-on command unless the current detect result is  
detect good. Any other detect result will generate a t  
START  
fault if a power-on command is received. In high power  
mode the port must be placed in manual mode to force a  
port on regardless of detect outcome.  
275  
FIRST  
DETECTION  
POINT  
25kΩ SLOPE  
165  
Behavior in AUTO pin mode is similar to semi-auto; how-  
ever, afterdetectgoodisreportedandtheportisclassified  
(if classification is enabled), it is automatically powered  
on without further intervention. In standalone (AUTO pin)  
SECOND  
DETECTION  
POINT  
VALID PD  
0V-2V  
OFFSET  
mode, the I  
and I thresholds are automatically set;  
VOLTAGE  
CUT  
LIM  
42701 F12  
see the Reset and the AUTO/MID Pins section for more  
Figure 12. PD Detection  
information.  
The signature detection circuitry is disabled when the  
port is initially powered up with the AUTO pin low, in  
shutdown mode, or when the corresponding Detect En-  
able bit is cleared.  
Table 4. Detection Status  
MEASURED PD SIGNATURE  
Incomplete or Not Yet Tested  
< 2.4k  
DETECTION RESULT  
Detect Status Unknown  
Short Circuit  
Detection of Legacy PDs  
Capacitance > 2.7µF  
C
too High  
too Low  
PD  
2.4k < R < 17k  
R
SIG  
ProprietaryPDsthatpredatetheoriginalIEEE802.3afstan-  
dardarecommonlyreferredtotodayaslegacydevices.One  
type of legacy PD uses a large common mode capacitance  
(>10μF) as the detection signature. Note that PDs in this  
range of capacitance are defined as invalid, so a PSE that  
detects legacy PDs is technically noncompliant with the  
IEEE spec. The LTC4270/LTC4271 can be configured to  
detect this type of legacy PD. Legacy detection is disabled  
bydefault,butcanbemanuallyenabledonaper-portbasis.  
When enabled, the port will report Detect Good when it  
sees either a valid IEEE PD or a high-capacitance legacy  
PD. With legacy mode disabled, only valid IEEE PDs will  
be recognized.  
PD  
17k < R < 29k  
Detect Good  
R too High  
SIG  
PD  
> 29k  
> 50k  
Open Circuit  
Voltage > 10V  
Port Voltage Outside Detect Range  
More on Operating Modes  
Theport’soperatingmodedetermineswhentheLTC4270/  
LTC4271 runs a detection cycle. In manual mode, the port  
will idle until the host orders a detect cycle. It will then  
run detection, report the results, and return to idle to wait  
for another command.  
Insemi-automode, theLTC4270/LTC4271autonomously  
polls a port for PDs, but it will not apply power until com-  
manded to do so by the host. The Port Status register is  
updated at the end of each detection cycle.  
CLASSIFICATION  
802.3af Classification  
A PD may optionally present a classification signature to  
the PSE to indicate the maximum power it will draw while  
operating. The IEEE specification defines this signature  
as a constant current draw when the PSE port voltage is  
Ifavalidsignatureresistanceisdetectedandclassification  
is enabled, the port will classify the PD and report that  
result as well. The port will then wait for at least 100ms (or  
2secondsifmidspanmodeisenabled), andwillrepeatthe  
detection cycle to ensure that the data in the Port Status  
register is up-to-date.  
in the V  
range (between 15.5V and 20.5V), with the  
CLASS  
currentlevelindicatingoneof5possiblePDclasses.Figure  
13 shows a typical PD load line, starting with the slope of  
the25k signatureresistorbelow10V, thentransitioningto  
If the port is in semi-auto mode and high power opera-  
tion is enabled, the port will not turn on in response to  
42701fb  
19  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
the classification signature current (in this case, Class 3)  
802.3at 2-Event Classification  
in the V  
range. Table 5 shows the possible clas-  
CLASS  
sification values.  
The802.3atspecificationdefinestwomethodsofclassify-  
ing a Type 2 PD. A-grade and B-grade LTC4270/LTC4271  
parts support 802.3at 2-event classification.  
Table 5. 802.3af and 802.3at Classification Values  
CLASS  
Class 0  
Class 1  
Class 2  
Class 3  
Class 4  
RESULT  
One method adds extra fields to the Ethernet LLDP data  
protocol; although the LTC4270/LTC4271 is compatible  
with this classification method, it cannot perform clas-  
sification directly since it doesn’t have access to the data  
path. LLDP classification requires the PSE to power the  
PD as a standard 802.3af (Type 1) device. It then waits for  
the host to perform LLDP communication with the PD and  
updatethePSEportdata.TheLTC4270/LTC4271supports  
No Class Signature Present; Treat Like Class 3  
3W  
7W  
13W  
25.5W (Type 2)  
If classification is enabled, the port will classify the PD  
immediatelyafterasuccessfuldetectioncycleinsemi-auto  
or AUTO pin modes, or when commanded to in manual  
mode. It measures the PD classification signature by ap-  
plying 18V for 12ms (both values typical) to the port via  
the OUTn pin and measuring the resulting current; it then  
reports the discovered class in the Port Status register.  
If the LTC4270/LTC4271 is in AUTO pin mode, it will ad-  
changing the I and I  
levels on the fly, allowing the  
LIM  
CUT  
host to complete LLDP classification.  
The second 802.3at classification method, known as  
2-event classification or ping-pong, is supported by  
the LTC4270/LTC4271. A Type 2 PD that is request-  
ing more than 13W will indicate Class 4 during normal  
802.3af classification. If the LTC4270/LTC4271 sees  
Class 4, it forces the port to a specified lower voltage  
(called the mark voltage, typically 9V), pauses briefly, and  
then re-runs classification to verify the Class 4 reading  
(Figure1).ItalsosetsabitintheHighPowerStatusregister  
to indicate that it ran the second classification cycle. The  
second cycle alerts the PD that it is connected to a Type  
2 PSE which can supply Type 2 power levels.  
ditionally use the classification result to set the I  
and  
CUT  
I
thresholds. See the Reset and the AUTO/MID Pin  
LIM  
section for more information.  
The classification circuitry is disabled when the port is  
initially powered up with the AUTO pin low, in shutdown  
mode,orwhenthecorrespondingClassEnablebitiscleared.  
60  
PSE LOAD LINE  
OVER  
CURRENT  
50  
2-event ping-pong classification is enabled by setting a bit  
in the port’s High Power Mode register. Note that a ping-  
pongenabledportonlyrunsthesecondclassificationcycle  
when it detects a Class 4 device; if the first cycle returns  
Class 0 to 3, the port determines it is connected to a Type 1  
PD and does not run the second classification cycle.  
48mA  
40  
30  
20  
10  
0
CLASS 4  
CLASS 3  
33mA  
23mA  
CLASS 2  
TYPICAL  
CLASS 3  
PD LOAD  
LINE  
14.5mA  
6.5mA  
CLASS 1  
CLASS 0  
Invalid Type 2 Class Combinations  
The 802.3at specification defines a Type 2 PD class  
signature as two consecutive Class 4 results; a Class 4  
followed by a Class 0-3 is not a valid signature. In AUTO  
pin mode, the LTC4270/LTC4271 will power a detected  
PDregardlessoftheclassificationresults,withoneexcep-  
tion: if the PD presents an invalid Type 2 signature (Class  
4 followed by Class 0 to 3), the LTC4270/LTC4271 will  
not provide power and will restart the detection process.  
0
5
10  
15  
20  
25  
VOLTAGE (V  
)
CLASS  
42701 F13  
Figure 13. PD Classification  
42701fb  
20  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
To aid in diagnosis, the Port Status register will always  
report the results of the last class pulse, so an invalid  
Class 4–Class 2 combination would report a second class  
pulse was run in the High Power Status register (which  
implies that the first cycle found class 4), and Class 2 in  
the Port Status register.  
depends on several factors: the class of the PD, the volt-  
age of the main supply (V ), the type of PSE (Type 1 or  
EE  
Type 2), the sense resistor (0.5Ω or 0.25Ω), the SOA of  
the MOSFET, and whether or not the system is required  
to enforce class current levels.  
Per the IEEE specification, the LTC4270/LTC4271 will al-  
low the port current to exceed I  
for a limited period of  
CUT  
POWER CONTROL  
time before removing power from the port, whereas it will  
actively control the MOSFET gate drive to keep the port  
The primary function of the LTC4270/LTC4271 is to  
control the delivery of power to the PSE port. It does this  
by controlling the gate drive voltage of an external power  
MOSFETwhilemonitoringthecurrentviaanexternalsense  
resistorandtheoutputvoltageattheOUTpin.Thiscircuitry  
current below I . The port does not take any action to  
LIM  
limit the current when only the I threshold is exceeded,  
CUT  
but does start the t  
timer. If the current drops below  
CUT  
the I  
current threshold before its timer expires, the  
CUT  
t
timer counts back down, but at 1/16 the rate that it  
CUT  
serves to couple the raw V input supply to the port in  
EE  
counts up. If the t  
timer reaches 60ms (typical) the  
CUT  
a controlled manner that satisfies the PDs power needs  
port is turned off and the port t  
fault is set. This allows  
CUT  
while minimizing both power dissipation in the MOSFET  
the current limit circuitry to tolerate intermittent overload  
signalswithdutycyclesbelowabout6%;longerdutycycle  
overloads will turn the port off.  
and disturbances on the V backplane.  
EE  
Inrush Control  
The I current limiting circuit is always enabled and ac-  
Once the command has been given to turn on a port, the  
LTC4270/LTC4271 ramps up the GATE pin of that port’s  
external MOSFET in a controlled manner. Under normal  
power-up circumstances, the MOSFET gate will rise until  
the port current reaches the inrush current limit level  
(typically 425mA), at which point the GATE pin will be  
LIM  
tively limiting port current. The t timer is enabled only  
LIM  
when the t Enable bit is set. This allows t to be set  
LIM  
LIM  
to a shorter value than t  
to provide more aggressive  
CUT  
MOSFET protection and turn off a port before MOSFET  
damage can occur. The t  
timer starts when the I  
LIM  
LIM  
threshold is exceeded. When the t timer reaches 12ms  
servoed to maintain the specified I  
current. During  
LIM  
INRUSH  
(typical) the port is turned off and the port t  
set. When the t  
fault is  
this inrush period, a timer (t  
) runs. When output  
LIM  
START  
Enable bit is disabled t behaviors  
chargingiscomplete,theportcurrentwillfallandtheGATE  
pin will be allowed to continue rising to fully enhance the  
LIM  
LIM  
are tracked by the t timer, which counts up during both  
CUT  
I
and I  
events.  
MOSFET and minimize its on-resistance. The final V is  
LIM  
CUT  
GS  
nominally 12V. The inrush period is maintained until the  
I
is typically set to a lower value than I to allow the  
CUT  
LIM  
t
timer expires. At this time if the inrush current limit  
START  
port to tolerate minor faults without current limiting.  
level is still exceeded, the port will be turned back off and  
a t fault reported.  
Per the IEEE specification, the LTC4270/LTC4271 will  
START  
automatically set I to 425mA (shown in bold in Table 6)  
LIM  
during inrush at port turn-on, and then switch to the  
Current Limit  
programmed I setting once inrush has completed. To  
LIM  
Each LTC4270/LTC4271 port includes two current limit-  
maintain IEEE compliance, I should be kept at 425mA  
LIM  
ing thresholds (I  
and I ), each with a corresponding  
CUT  
LIM  
for all Type 1 PDs, and 850mA if a Type 2 PD is detected.  
timer (t  
and t ). Setting the I  
and I thresholds  
CUT LIM  
CUT  
LIM  
I
is automatically reset to 425mA when a port turns off.  
LIM  
42701fb  
21  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
Table 6. Example Current Limit Settings  
INTERNAL REGISTER SETTING (hex)  
The shaded areas in Table 6 indicate settings that may  
require a larger external MOSFET, additional heat sinking,  
or setting t Enable.  
LIM  
I
(mA)  
R
SENSE  
= 0.5Ω  
R
SENSE  
= 0.25Ω  
LIM  
53  
88  
MOSFET Fault Detection  
106  
159  
213  
266  
319  
372  
08  
89  
80  
8A  
09  
8B  
88  
LTC4270/LTC4271 PSE ports are designed to tolerate  
significant levels of abuse, but in extreme cases it is pos-  
sible for the external MOSFET to be damaged. A failed  
MOSFET may short source to drain, which will make the  
port appear to be on when it should be off; this condition  
may also cause the sense resistor to fuse open, turning  
off the port but causing the LTC4270 SENSE pin to rise  
to an abnormally high voltage. A failed MOSFET may also  
short from gate to drain, causing the LTC4270 GATE pin  
to rise to an abnormally high voltage. The LTC4270 OUT,  
SENSE and GATE pins are designed to tolerate up to 80V  
faults without damage.  
08  
89  
425  
478  
00  
8E  
92  
CB  
10  
D2  
40  
4A  
50  
5A  
60  
52  
80  
531  
8A  
584  
638  
90  
9A  
C0  
CA  
D0  
DA  
E0  
49  
40  
4A  
50  
5A  
60  
52  
744  
850  
If the LTC4270/LTC4271 sees any of these conditions for  
more than 180μs, it disables all port functionality, reduces  
the gate drive pull-down current for the port and reports  
a FET Bad fault. This is typically a permanent fault, but  
the host can attempt to recover by resetting the port, or  
by resetting the entire chip if a port reset fails to clear the  
fault. If the MOSFET is in fact bad, the fault will quickly  
return, and the port will disable itself again. The remaining  
ports of the LTC4270/LTC4271 are unaffected.  
956  
1063  
1169  
1275  
1488  
1700  
1913  
2125  
2338  
2550  
2975  
An open or missing MOSFET will not trigger a FET Bad  
fault, but will cause a t  
fault if the LTC4270/LTC4271  
START  
attempts to turn on the port.  
I
Foldback  
LIM  
Port Current Readback  
The LTC4270/LTC4271 features a two-stage foldback  
circuit that reduces the port current if the port voltage falls  
below the normal operating voltage. This keeps MOSFET  
power dissipation at safe levels for typical 802.3af MOS-  
FETs, even at extended 802.3at power levels. Current limit  
and foldback behavior are programmable on a per-port  
basis.  
The LTC4270/LTC4271 measures the current at each port  
with an internal A/D converter. Port data is only valid when  
the port power is on and reads zero at all other times. The  
converter has two modes:  
•ꢀ 100ms mode: Samples are taken continuously and the  
measured value is updated every 100ms  
•ꢀ 1s mode: Samples are taken continuously; a moving 1  
Table 6 gives examples of recommended I  
settings.  
register  
LIM  
second average is updated every 100ms  
The LTC4270/LTC4271 will support current levels well  
beyond the maximum values in the 802.3at specification.  
42701fb  
22  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
Port Current Policing  
Masked Shutdown  
The LTC4270/LTC4271 can augment t  
current moni-  
The LTC4270/LTC4271 provides a low latency port shed-  
ding feature to quickly reduce the system load when  
required. By allowing a pre-determined set of ports to  
be turned off, the current on an overloaded main power  
supply can be reduced rapidly while keeping high priority  
devices powered. Each port can be configured to high or  
low priority; all low-priority ports will shut down within  
6.5μs after the MSD pin is pulled low, high priority ports  
will remain powered. If a port is turned off via MSD, the  
correspondingDetectionandClassificationEnablebitsare  
cleared, so the port will remain off until the host explicitly  
re-enables detection.  
CUT  
toring with a policing function to track the one second  
current averages. A port violating the user-specified Port  
Police Threshold will be shut off with both a t  
and  
CUT  
Police event recorded. A port current Police event can be  
differentiated from a port t violation by reading both  
CUT  
events bits; both bits are set for a Police violation while  
only the t bit is set for t timer violations.  
CUT  
CUT  
Port Voltage Readback  
The LTC4270/LTC4271 measures the output voltage at  
each port with an internal A/D converter. Port data is  
only valid when the port power is on and reads zero at  
all other times.  
In the LTC4270/LTC4271 chipset the active level of MSD  
is register configurable as active high or low. The default  
is LTC4266-compatible active low behavior.  
Disconnect  
V
Readback  
EE  
TheLTC4270/LTC4271monitorspoweredportstoensure  
thePDcontinuestodrawtheminimumspecifiedcurrent.A  
disconnecttimercountsupwheneverportcurrentisbelow  
7.5mA(typ),indicatingthatthePDhasbeendisconnected.  
The LTC4270/LTC4271 measures the V voltage with an  
internal 12-bit A/D converter.  
EE  
If the t timer expires, the port will be turned off and the  
General Purpose IO  
DIS  
disconnect bit in the fault event register will be set. If the  
Two sets of general purpose IO pins are available in the  
LTC4270/LTC4271chipset.Thefirstsetofgeneralpurpose  
IO are GP1 and GP0. These fully bidirectional IO are 3.3V  
CMOS IO on the LTC4271 chip.  
current returns before the t timer runs out, the timer  
DIS  
resets. As long as the PD exceeds the minimum current  
level more often than t , it will remain powered.  
DIS  
Although not recommended, the DC disconnect feature  
can be disabled by clearing the corresponding enable bits.  
Note that this defeats the protection mechanisms built  
into the IEEE specification, since a powered port will stay  
powered after the PD is removed. If the still-powered port  
is subsequently connected to a non-PoE data device, the  
device may be damaged.  
The second set of general purpose IO pins are XIO1 and  
XIO0. These fully bidirectional IO are 4.3V CMOS IO on  
the LTC4270 chip.  
Code Download  
LTC4271 firmware is field-upgradable by downloading  
and executing RAM images. RAM images are volatile  
The LTC4270/LTC4271 does not include AC disconnect  
circuitry, but includes AC Disconnect Enable bits to main-  
taincompatibilitywiththeLTC4259A.IftheACDisconnect  
Enable bits are set, DC disconnect will be used.  
and must be re-downloaded after each V power cycle,  
DD  
but will remain valid during reset and V power events.  
EE  
Contact Linear Technology for code download procedures  
and RAM images.  
42701fb  
23  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
SERIAL DIGITAL INTERFACE  
2
2
I C ADDRESS  
I C ADDRESS  
LTC4271  
LTC4271  
Overview  
0100000  
0100001  
0100010  
0100111  
0101000  
0101001  
3.3V  
The LTC4270/LTC4271 communicates with the host us-  
ing a standard SMBus/I C 2-wire interface. The LTC4270/  
AD0  
AD1  
AD2  
AD3  
AD6  
AD0  
AD1  
AD2  
AD3  
AD6  
2
LTC4271 is a slave-only device, and communicates with  
the host master using the standard SMBus protocols.  
Interrupts are signaled to the host via the INT pin. The  
Timing Diagrams (Figures 5 through 9) show typical  
communicationwaveformsandtheirtimingrelationships.  
More information about the SMBus data protocols can be  
found at www.smbus.org.  
SCL  
SCL  
SDAIN  
SDAIN  
SDAOUT  
SDAOUT  
TheLTC4270/LTC4271requiresboththeV andV sup-  
DD  
EE  
42701 F15  
SCL  
SDA  
ply rails to be present for the serial interface to function.  
Figure 14. Example I2C Bus Addressing  
Bus Addressing  
The LTC4270/LTC4271’s primary 7-bit serial bus address  
Interrupts and SMBAlert  
is A 10A A A A b, with bit 6 controlled by AD6 and the  
6
3 2 1 0  
lower four bits set by the AD3-AD0 pins; this allows up  
to 10 LTC4270/LTC4271s, on a single bus. Ten LTC4270/  
LTC4271 are equivalent to 30 quad PSEs or 120 ports. All  
LTC4270/LTC4271salsorespondtothebroadcastaddress  
0110000b, allowing the host to write the same command  
(typically configuration commands) to multiple LTC4270/  
LTC4271sinasingletransaction.IftheLTC4270/LTC4271  
is asserting the INT pin, it will also respond to the alert  
responseaddress(0001100b)pertheSMBusspecification.  
Most LTC4270/LTC4271 port events can be configured  
to trigger an interrupt, asserting the INT pin and alerting  
the host to the event. This removes the need for the host  
to poll the LTC4270/LTC4271, minimizing serial bus traf-  
fic and conserving host CPU cycles. Multiple LTC4270/  
LTC4271s can share a common INT line, with the host  
using the SMBAlert protocol (ARA) to determine which  
LTC4270/LTC4271 caused an interrupt.  
Register Description  
Each LTC4270/LTC4271 is logically composed of three  
quads of four ports each. Each quad occupies separate,  
For information on serial bus usage and device configura-  
tion and status, refer to the LTC4271 Software Program-  
ming documentation.  
2
contiguous I C addresses. The AD6, AD3-0 pins set the  
address of the base quad while the remaining quads are  
2
consecutively numbered. I C addresses outside of the  
x10xxxxbrangeareconsideredillegalandwillnotrespond.  
Each internal quad is independent of the other quads, with  
the exception of writes to the Chip Reset, MSD Inversion  
andGeneralPurposeInputOutputregisters.Theseregisters  
are global in nature and will affect all quads.  
ISOLATION REQUIREMENTS  
IEEE 802.3 Ethernet specifications require that network  
segments (including PoE circuitry) be electrically isolated  
from the chassis ground of each network interface de-  
vice. However, network segments are not required to be  
isolated from each other, provided that the segments are  
connected to devices residing within a single building on  
a single power distribution system.  
42701fb  
24  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
For simple devices such as small PoE switches, the isola-  
tion requirement can be met by using an isolated main  
power supply for the entire device. This strategy can be  
used if the device has no electrically conducting ports  
other than twisted-pair Ethernet. In this case, the SDAIN  
and SDAOUT pins can be tied together and will act as a  
In the LTC4270/LTC4271, V should be delivered by the  
DD  
host controller’s non-isolated 3.3V supply. To maintain  
required isolation AGND and DGND must not be con-  
nected in any way.  
Main PoE Power Supply  
2
standard I C/SMBus SDA pin.  
V
EE  
is the main isolated PoE supply that provides power  
to the PDs. Because it supplies a relatively large amount  
of power and is subject to significant current transients,  
it requires more design care than a simple logic supply.  
If the device is part of a larger system, contains additional  
external non-Ethernet ports, or must be referenced to  
protective ground for some other reason, the Power over  
Ethernet subsystem must be electrically isolated from the  
rest of the system.  
For minimum IR loss and best system efficiency, set V  
EE  
near maximum amplitude (57V), leaving enough margin  
to account for transient over or undershoot, temperature  
drift, andthelineregulationspecificationsoftheparticular  
power supply used.  
TheLTC4270/LTC4271chipsetsimplifiesPSEisolationby  
allowing the LTC4271 chip to reside on the non-isolated  
side. There it can receive power from the main logic sup-  
2
Bypass capacitance between AGND and V is very im-  
ply and connect directly to the I C/SMBus bus. Isolation  
EE  
portant for reliable operation. If a short circuit occurs at  
one of the output ports it can take as long as 1μs for the  
LTC4270 to begin regulating the current. During this time  
the current is limited only by the small impedances in the  
circuit and a high current spike typically occurs, causing a  
between the LTC4271 and LTC4270 is implemented using  
aproprietarytransformer-basedcommunicationprotocol.  
Additional details are provided in the Serial Bus Isolation  
section of this data sheet.  
voltage transient on the V supply and possibly causing  
EE  
EXTERNAL COMPONENT SELECTION  
the LTC4270/LTC4271 to reset due to a UVLO fault. A 1μF,  
100V X7R capacitor placed near the V pin along with an  
EE  
Power Supplies and Bypassing  
electrolyticbulkcapacitorofatleast47µFisrecommended  
The LTC4270/LTC4271 requires two supply voltages to  
to minimize spurious resets.  
operate. V requires 3.3V (nominally) relative to DGND.  
DD  
V
EE  
requires a negative voltage of between –45V and  
Serial Bus Isolation  
–57V for Type 1 PSEs, –51V to –57V for Type 2 PSEs,  
The LTC4270/LTC4271 chipset uses transformers to  
isolate the LTC4271 from the LTC4270. In this case, the  
SDAIN and SDAOUT pins can be shorted to each other  
++  
or –54.75V to –57V for LTPoE PSEs, relative to AGND.  
Digital Power Supply  
2
and tied directly to the I C/SMBus bus. The transformers  
V
provides digital power for the LTC4271 processor,  
DD  
should be 10BASE-T or 10/100BASE-T with a 1:1 turns  
ratio. It is important that the selected transformers do not  
havecommon-modechokes.Thesetransformerstypically  
provide 1500V of isolation between the LTC4271 and the  
LTC4270. For proper operation strict layout guidelines  
must be met.  
and draws a maximum of 15mA. A ceramic decoupling  
cap of at least 0.1μF should be placed from V to DGND,  
DD  
as close as practical to each LTC4271 chip. A 1.8V core  
voltage supply is generated internally and requires a 1µF  
ceramic decoupling cap between the CAP1 pin and DGND.  
42701fb  
25  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
3.3V  
0.1µF  
V
XIO0  
XIO1  
0.22µF  
100V  
DD33  
GP0  
GP1  
S1B  
S1B  
NO ISOLATION  
REQUIRED ON  
I C INTERFACE  
CPD  
CPA  
PORTn  
OUTn  
MID  
2
100Ω  
100Ω  
–54V  
RESET  
MSD  
AUTO  
INT  
•
•
•
GATEn  
3.3V  
3.3V  
0.25Ω  
100Ω  
100Ω  
–54V  
SENSEn  
CND  
DPD  
CNA  
DPA  
T1  
T2  
LTC4271  
LTC4270  
SCL  
SDAIN  
SDAOUT  
0.22µF  
100V  
S1B  
S1B  
100Ω  
100Ω  
•
PORT1  
OUT1  
–54V  
100Ω  
AD0  
AD1  
AD2  
AD3  
AD6  
100Ω  
GATE1  
DND  
DNA  
0.25Ω  
SENSE1  
VSSK AGND  
–54V  
V
DGND  
CAP1  
CAP2  
EE  
1µF  
2nF, 2kV  
0.1µF  
+
>47µF  
SYSTEM  
1µF  
BULK CAP  
–54V  
–54V  
42701 F16  
Figure 15. LTC4270/LTC4271 Proprietary Isolation  
External MOSFET  
0.25Ωresistor. InordertomeettheI andI accuracy  
CUT LIM  
required by the IEEE specification, the sense resistors  
should have 1% tolerance or better, and no more than  
200ppm/°Ctemperaturecoefficient.Inaddition,thesense  
resistors must meet strict layout guidelines.  
CarefulselectionofthepowerMOSFETiscriticaltosystem  
reliability. LTC recommends either Fairchild IRFM120A,  
FDT3612, FDMC3612 or Philips PHT6NQ10T for their  
proven reliability in Type 1 and Type 2 PSE applications.  
SOA curves are not a reliable specification for MOSFET  
selection.ContactLTC ApplicationsbeforeusingaMOSFET  
other than one of these recommended parts.  
Port Output Cap  
Each port requires a 0.22μF cap across its outputs to keep  
the LTC4270 stable while in current limit during startup  
or overload. Common ceramic capacitors often have sig-  
nificant voltage coefficients; this means the capacitance is  
reduced as the applied voltage increases. To minimize this  
problem, X7R ceramic capacitors rated for at least 100V  
are recommended and must be located close to the PSE.  
Sense Resistor  
The LTC4270/LTC4271 is designed to use 0.25Ω current  
sense resistors to reduce power dissipation. Four com-  
monly available 1Ω resistors (sized according to power  
dissipation) can be used in parallel in place of a single  
42701fb  
26  
LTC4270/LTC4271  
ApplicAtions inForMAtion  
ESD/Cable Discharge Protection  
LAYOUT GUIDELINES  
Ethernet ports can be subject to significant ESD events  
when long data cables, each potentially charged to thou-  
sands of volts, are plugged into the low impedance of the  
RJ45jack. To protectagainstdamage, eachportrequiresa  
Strict adherence to board layout, parts placement and  
routing guidelines is critical for optimal current reading  
accuracy, IEEE compliance, system robustness, and  
thermal dissipation. Refer to the DC1682A Demo Board  
as a layout reference. Contact LTC Applications to obtain  
a full set of layout guidelines, example layouts and BOMs.  
pair of clamp diodes; one to AGND and one to V (Figure  
EE  
16). An additional surge suppressor is required for each  
LTC4270 chip from V to AGND. The diodes at the ports  
EE  
steer harmful surges into the supply rails, where they are  
0.22µF  
S1B  
A
PORTn  
GND  
absorbed by the surge suppressor and the V bypass  
EE  
OUTn  
capacitance. The surge suppressor has the additional  
LTC4270  
SMAJ58A  
–54V  
0.1µF  
benefit of protecting the LTC4270 from transients on the  
GATEn  
V
EE  
supply.  
S1B  
SENSEn  
V
EE  
S1B diodes work well as port clamp diodes, and an  
0.25Ω  
SMAJ58AorequivalentisrecommendedfortheV surge  
EE  
42701 F17  
suppressor.  
Figure 16. LTC4270 Discharge Protection  
42701fb  
27  
LTC4270/LTC4271  
typicAl ApplicAtion  
•
•
•
•
42701fb  
28  
LTC4270/LTC4271  
pAckAge Description  
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.  
UF Package  
24-Lead Plastic QFN (4mm × 4mm)  
(Reference LTC DWG # 05-08-1697)  
0.70 0.05  
4.50 0.05  
3.10 0.05  
2.45 0.05  
(4 SIDES)  
PACKAGE OUTLINE  
0.25 0.05  
0.50 BSC  
BOTTOM VIEW—EXPOSED PAD  
R = 0.115  
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS  
PIN 1 NOTCH  
R = 0.20 TYP OR  
0.35 × 45° CHAMFER  
0.75 0.05  
4.00 0.10  
(4 SIDES)  
TYP  
23 24  
PIN 1  
TOP MARK  
(NOTE 6)  
0.40 0.10  
1
2
2.45 0.10  
(4-SIDES)  
(UF24) QFN 0105  
0.200 REF  
0.25 0.05  
0.00 – 0.05  
0.50 BSC  
NOTE:  
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION  
(WGGD-X)—TO BE APPROVED  
5. EXPOSED PAD SHALL BE SOLDER PLATED  
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION  
ON THE TOP AND BOTTOM OF PACKAGE  
2. DRAWING NOT TO SCALE  
3. ALL DIMENSIONS ARE IN MILLIMETERS  
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE  
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT  
42701fb  
29  
LTC4270/LTC4271  
pAckAge Description  
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.  
UKG Package  
52-Lead Plastic QFN (7mm × 8mm)  
(Reference LTC DWG # 05-08-1729 Rev Ø)  
7.50 0.05  
6.10 0.05  
5.50 REF  
(2 SIDES)  
0.70 0.05  
6.45 0.05  
6.50 REF  
(2 SIDES)  
7.10 0.05 8.50 0.05  
5.41 0.05  
PACKAGE OUTLINE  
0.25 0.05  
0.50 BSC  
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS  
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED  
5.50 REF  
(2 SIDES)  
0.75 0.05  
7.00 0.10  
(2 SIDES)  
R = 0.115  
TYP  
0.00 – 0.05  
51  
52  
0.40 0.10  
PIN 1 TOP MARK  
(SEE NOTE 6)  
1
2
PIN 1 NOTCH  
R = 0.30 TYP OR  
0.35 × 45°C  
CHAMFER  
6.45 0.10  
8.00 0.10  
(2 SIDES)  
6.50 REF  
(2 SIDES)  
5.41 0.10  
(UKG52) QFN REV  
Ø 0306  
R = 0.10  
TYP  
0.25 0.05  
0.50 BSC  
TOP VIEW  
SIDE VIEW  
0.200 REF  
0.00 – 0.05  
BOTTOM VIEW—EXPOSED PAD  
0.75 0.05  
NOTE:  
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE  
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE  
2. DRAWING NOT TO SCALE  
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT  
5. EXPOSED PAD SHALL BE SOLDER PLATED  
3. ALL DIMENSIONS ARE IN MILLIMETERS  
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE  
42701fb  
30  
LTC4270/LTC4271  
revision history  
REV  
DATE  
DESCRIPTION  
PAGE NUMBER  
A
9/11  
Updated Absolute Maximum Ratings.  
Updated Electrical Characteristics.  
Updated GATEn pin description.  
Updated Inrush Control section.  
Updated Power Supplies and Bypassing section.  
Updated Typical Applications.  
2
4, 5, 6, 7  
13  
21  
25  
28, 32  
1, 5, 15, 23  
1, 16, 17  
2
B
3/12  
Removed temperature readback feature.  
++  
Changed LTPoE power levels from 35W, 45W to 38.7W, 52.7W respectively.  
Removed Lead Temperature.  
Updated Electrical Characteristics (removed temperature dots).  
Clarified AUTO Pin mode relationship to Reset Pin.  
Modified Related Parts.  
5, 6  
17-18  
32  
42701fb  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-  
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.  
31  
LTC4270/LTC4271  
typicAl ApplicAtion  
3.3V 0.1µF  
1µF  
12  
11  
GP0  
V
DD33  
XIO0  
CPA  
XIO1  
2
GP1  
CPD  
MID  
1
OUT12  
GATE12  
SENSE12  
100Ω  
3.3V  
RESET  
MSD  
AUTO  
INT  
•
•
•
–54V  
–54V  
0.22µF  
100V  
X7R  
100Ω  
LTC4271  
LTC4270  
S1B  
SCL  
T2  
CND  
DPD  
CNA  
DPA  
SDAIN  
OUT1  
GATE1  
SENSE1  
SDAOUT  
AD0  
AD1  
AD2  
AD3  
AD6  
100Ω  
3.3V  
•
RS  
RJ45  
CTOR  
100Ω  
0.25Ω, 1% FDMC3612  
T3  
1
DND  
DNA  
AGND  
RJ45  
CONNECTOR  
1µF  
2
3
4
5
6
7
8
S1B  
T1  
V
VSSK  
DGND CAP1  
CAP2 EE  
1
1µF  
100V  
X7R  
SMAJ58A  
2nF 2000V  
1µF  
2
3
4
5
6
7
•
•
•
0.01µF  
200V  
0.01µF  
200V  
75Ω 75Ω  
–54V  
PHY  
•
ISOLATED  
(NETWORK  
PHYSICAL  
LAYER  
ISOLATED  
GND  
8
•
•
•
•
>47µF  
SYSTEM  
BULK CAP  
0.01µF  
200V  
0.01µF  
200V  
+
CHIP)  
75Ω 75Ω  
–54V  
42701 F16  
relAteD pArts  
PART NUMBER DESCRIPTION  
COMMENTS  
LTC4257-1  
LTC4263  
LTC4265  
LTC4266  
LTC4266A  
IEEE 802.3af PD Interface Controller  
Single IEEE 802.3af PSE Controller  
IEEE 802.3at PD Interface Controller  
Quad IEEE 802.3at PoE PSE Controller  
Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class  
Internal FET Switch  
Internal 100V, 1A Switch, 2-Event Classification Recognition  
With Programmable I /I , 2-Event Classification, and Port Current and Voltage Monitoring  
CUT LIM  
++  
Quad LTPoE PSE Controller  
Provides Up to 90W. Backwards Compatible with IEEE 802.3af and IEEE 802.3at PDs. With  
Programmable I /I , 2-Event Classification, and Port Current and Voltage Monitoring  
CUT LIM  
LTC4266C  
LTC4267  
Quad IEEE 802.3af PSE Controller  
With Programmable I /I , 1-Event Classification, and Port Current and Voltage Monitoring  
CUT LIM  
IEEE 802.3af PD Interface With Integrated  
Switching Regulator  
Internal 100V, 400mA Switch, Dual Inrush Current, Programmable Class  
LTC4267-1  
LTC4267-3  
LTC4269-1  
LTC4269-2  
LTC4278  
IEEE 802.3af PD Interface With Integrated  
Switching Regulator  
Internal 100V, 400mA Switch, Programmable Class, 200kHz Constant Frequency PWM  
Internal 100V, 400mA Switch, Programmable Class, 300kHz Constant Frequency PWM  
IEEE 802.3af PD Interface With Integrated  
Switching Regulator  
IEEE 802.3af PD Interface With Integrated  
Flyback Switching Regulator  
2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,  
50kHz to 250kHz, Aux Support  
IEEE 802.3af PD Interface With Integrated  
Forward Switching Regulator  
2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz to  
500kHz, Aux Support  
IEEE 802.3af PD Interface With Integrated  
Flyback Switching Regulator  
2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,  
50kHz to 250kHz, 12V Aux Support  
LTC4274  
Single IEEE 802.3at PoE PSE Controller  
With Programmable I /I , 2-Event Classification, and Port Current and Voltage Monitoring  
CUT LIM  
++  
LTC4274A  
Single LTPoE PSE Controller  
Provides Up to 90W. Backwards Compatible with IEEE 802.3af and IEEE 802.3at PDs. With  
Programmable I /I , 2-Event Classification, and Port Current and Voltage Monitoring  
CUT LIM  
LTC4274C  
LTC4311  
Single IEEE 802.3af PSE Controller  
With Programmable I /I , 1-Event Classification, and Port Current and Voltage Monitoring  
CUT LIM  
2
2
SMBus/ I C Accelerator  
Improved I C Rise Time, Ensures Data Integrity  
42701fb  
LT 0312 REV B • PRINTED IN USA  
32 LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com  
LINEAR TECHNOLOGY CORPORATION 2011  

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