LTC4268CDKD-1-TRPBF [Linear]
High Power PD with Synchronous NoOpto Flyback Controller; 高功率PD与同步NoOpto反激式控制器
| 型号： | LTC4268CDKD-1-TRPBF |
| 厂家： | 
Linear |
| 描述： | High Power PD with Synchronous NoOpto Flyback Controller |
| 文件： | 总48页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4268-1
High Power PD with
Synchronous NoOpto
Flyback Controller
FEATURES
DESCRIPTION
The LTC®4268-1 is an integrated Powered Device (PD)
controllerandswitchingregulatorintendedforIEEE802.3af
and high power PoE applications up to 35W. By including
a precision dual current limit, the LTC4268-1 keeps inrush
below IEEE 802.3af current limit levels to ensure interop-
erability success while enabling high power applications
with a 750mA operational current limit.
n
Robust 35W PD Front End
n
IEEE 8X02.3af Compliant
n
Rugged 750mA Power MOSFET with Precision Dual
Level Current Limit
n
High Performance Synchronous Flyback Controller
n
IEEE Isolation Obtained without an Optoisolator
n
Adjustable Frequency from 50kHz to 250kHz
n
Tight Multi-Output Regulation with Load
The LTC4268-1 synchronous, current-mode, flyback
controller generates multiple supply rails in a single
conversion providing for the highest system efficiency
while maintaining tight regulation across all outputs. The
LTC4268-1includesLinearTechnology’spatentedNoOpto
feedback topology to provide full IEEE 802.3af isolation
without the need of optoisolator circuitry.
Compensation
Onboard 25k Signature Resistor
n
n
Programmable Classification Current to 75mA
n
Complete Thermal and Over-Current Protection
n
Available in Compact 32-Pin 7mm × 4mm DFN
Package
APPLICATIONS
The oversized power path and high performance flyback
controller of the LTC4268-1 combine to make the ultimate
solutionforpowerhungryPoEapplicationssuchasWAPs,
PTZ security cameras, RFID readers and ultra-efficient
802.3af applications running near the 12.95W limit.
n
VoIP Phones with Advanced Display Options
n
Dual-Radio Wireless Access Points
n
PTZ Security Cameras
n
RFID Readers
Industrial Controls
n
The LTC4268-1 is available in a space saving 32-pin DFN
package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 5841643.
n
Magnetic Card Readers
n
High Power PoE Systems
TYPICAL APPLICATION
35W High Efficiency PD Solution
3.3V
+
+
470μF
×4
•
≥5μF
100pF
56Ω
28.7k
1%
BAS21
20Ω
T1
47k
47Ω
•
T1
SMAJ58A
100k
B0540W
•
3.01k
1%
DF1501S
FMMT618
47μF
Si4490DY
Si7336ADP
~ +
–54V FROM
DATA PAIR
~ –
FMMT718
0.1μF
+
V
PWRGD PWRGD UVLO I
V
CC
FB PG
SENSE
PORTP
LIM_EN
DF1501S
~ +
~ –
1μF
0.02Ω
330Ω
SHDN
–54V FROM
SPARE PAIR
–
SENSE
15Ω
LTC4268-1
R
CLASS
SG
2.2nF
0.1μF
10nF
20k
V
CMP
T2
V
V
NEG
PGDLY
t
SYNC
R
ENDLY
OSC GND SFST C
CMP
PORTN
ON
CMP
•
•
R
10k
12k
169k
100k
47pF
CLASS
BAT54
T1: PA1477NL
T2: PA0184
42681 TA01a
0.033μF
42681fa
1
LTC4268-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
V
V
V
Voltage .......................................... 0.3V to –90V
PORTN
SHDN
NC
1
2
32 V
PORTP
Voltage...................V
+ 90V to V
–0.3V
NEG
PORTN
PORTN
31 NC
to GND Voltage (Note 3)
CC
R
3
30 PWRGD
29 PWRGD
CLASS
Low Impedance Source ......................... –0.3V to 18V
I
4
LIM_EN
Current Fed..........................................30mA into V
CC
V
V
V
5
28
27
26
V
V
V
PORTN
PORTN
NEG
NEG
NEG
R
, I
Voltage ...V
+ 7V to V
– 0.3V
– 0.3V
CLASS LIM_EN
PORTN
PORTN
+ 90V to V
PORTN
6
SHDN Voltage ................V
PWRGD Voltage (Note 3)
PORTN
7
PORTN
NC
8
25 NC
33
Low Impedance Source ....V
+ 11V to V
– 0.3V
NEG
NEG
SG
9
24 PG
Current Fed..........................................................5mA
V
t
10
11
23 PGDLY
CC
PWRGD Voltage.............V
+ 80V to V
– 0.3V
22
21
R
PORTN
PORTN
ON
CMP
CMP
PWRGD Current.....................................................10mA
Current.....................................................100mA
ENDLY 12
SYNC 13
SFST 14
OSC 15
FB 16
C
20 SENSE+
19 SENSE–
18 UVLO
R
CLASS
–
+
SENSE , SENSE Voltage........................ –0.5V to +0.5V
UVLO, SYNC Voltage...................................–0.3V to V
CC
17
V
CMP
FB Current.............................................................. 2mA
V
Current ......................................................... 1mA
CMP
DKD32 PACKAGE
32-LEAD (7mm × 4mm) PLASTIC DFN
Operating Ambient Temperature Range (Notes 4, 5)
LTC4268-1C............................................. 0°C to 70°C
LTC4268-1I .......................................... –40°C to 85°C
Junction Temperature (Note 5) ............................. 150°C
Storage Temperature Range................... –65°C to 150°C
T
= 150°C,θ = 49°C/W, θ = 4.7°C/W
JA JC
JMAX
EXPOSED PAD (PIN 33) MUST BE SOLDERED TO
HEATSINKING PLANE THAT IS ELECTRICALLY CONNECTED TO GND
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4268CDKD-1#PBF
LTC4268IDKD-1#PBF
LTC4268CDKD-1#TRPBF 42681
0°C to 70°C
–40°C to 85°C
32-Lead (7mm × 4mm) Plastic DFN
32-Lead (7mm × 4mm) Plastic DFN
LTC4268IDKD-1#TRPBF
42681
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4268CDKD-1
LTC4268IDKD-1
LTC4268CDKD-1#TR
LTC4268IDKD-1#TR
42681
42681
0°C to 70°C
–40°C to 85°C
32-Lead (7mm × 4mm) Plastic DFN
32-Lead (7mm × 4mm) Plastic DFN
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
42681fa
2
LTC4268-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k,
RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Supply Voltage
Voltage with Respect to V
Pin
PORTP
PORT
(Notes 6, 7, 8, 9, 10)
l
l
l
l
l
IEEE 802.3af System
Signature Range
–57
–10.1
–21
–40.2
–31.5
V
V
V
V
V
–1.5
–12.5
–37.7
–29.8
Classification Range
UVLO Turn-On Voltage
UVLO Turn-Off Voltage
–38.9
–30.6
l
l
l
l
V
V
CC
V
CC
V
CC
V
CC
Turn-On Voltage
Turn-Off Voltage
Hysteresis
Voltage with Respect to GND
Voltage with Respect to GND
14
8
15.3
9.7
16.6
11
V
V
V
V
TURNON
V
TURNOFF
V
V
– V
TURNOFF
4
5.6
7.2
HYST
TURNON
V
Shunt Regulator Voltage
I
= 15mA, V = 0V, Voltage with
UVLO
19.5
20.2
CLAMP
VCC
Respect to GND
l
l
l
I
I
V
V
Supply Current
V
= Open (Note 11)
CMP
4
6.4
180
10
mA
μA
V
VCC
CC
Start-Up Current
V
= 10V
CC
400
VCC_START
CC
V
Feedback Regulation Voltage
1.22
1.237
200
1.251
FB
I
Feedback Pin Input Bias Current
R
Open
nA
A/V
FB_BIAS
CMP
l
l
g
Feedback Amplifier
Transconductance
700
25
1000
1400
90
m
I
Feedback Amplifier Source or Sink
Current
55
μA
FB
V
Feedback Amplifier Clamp Voltage
V
FB
V
FB
= 0.9V
= 1.4V
2.56
0.84
V
V
FBCLAMP
l
%V
Reference Voltage Line Regulation
Feedback Amplifier Voltage Gain
Soft-Start Charging Current
Soft-Start Discharge Current
Control Pin Threshold (VCMP)
PG, SG, Output High Level
12V ≤ V ≤ 18V
0.005
1500
20
0.02
25
%/V
V/V
μA
mA
V
REF
CC
A
V
V
CMP
V
SFST
V
SFST
= 1.2V to 1.7V
= 1.5V
I
I
16
SFST
SFST
= 1.5V, V
= 0V
0.8
1.3
1
UVLO
V
Duty Cycle = Min
CMP_THLD
l
l
V
V
,
6.6
7.4
8
V
PG_HIGH
SG_HIGH
V
V
,
PG, SG, Output Low Level
0.01
0.05
V
PG_LOW
SG_LOW
l
V
V
,
PG, SG, Output Shutdown Strength
PG, SG Rise Time
V
C
C
= 0V; I , I = 20mA
1.4
15
2.3
V
ns
PG_SHDN
SG_SHDN
UVLO
PG SG
t
t
,
, C = 1nF
PG SG
PG_RISE
SG_RISE
t
t
,
PG, SG Fall Time
, C = 1nF
PG SG
15
ns
PG_FALL
SG_FALL
l
V
Switch Current Threshold at Maximum
CMP
Measured at V
88
3
100
110
mV
SENSE_LIM
SENSE+
V
Sense Threshold vs V
0.07
205
V/V
mV
V
ΔV
/ΔV
SENSE CMP
CMP
l
l
V
Sense Pin Overcurrent Fault Voltage
Shutdown High Level Input Voltage
V , V < 1V
SENSE+ SFST
230
57
SENSE_OC
IH_SHDN
V
With Respect to V
High Level = Shutdown (Note 12)
PORTN
l
V
Shutdown Low Level Input Voltage
With Respect to V
0.45
V
IL_SHDN
PORTN
42681fa
3
LTC4268-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k,
RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
100
4
TYP
MAX
UNITS
kΩ
l
l
R
Shutdown Input Resistance
With Respect to V
INPUT_SHDN
PORTN
PORTN
V
I
High Level Input Voltage
With Respect to V
High Level Enables Current Limit
(Note 13)
V
IH_ILIM
LIM_EN
l
l
l
V
I
Low Level Input Voltage
Supply Current
With Respect to V (Note 13)
1
3
V
mA
mA
IL_ILIM
VPORTN
IN_CLASS
LIM_EN
PORTN
I
I
V
V
V
= –54V
PORTN
PORTN
IC Supply Current During Classification
Current Accuracy During Classification
Signature Resistance
= –17.5V, V
(Note 14)
Tied to V
0.55
0.62
0.70
PORTN
NEG
PORTP
l
l
10mA < I
< 75mA
PORTN
3.5
26
%
ΔI
CLASS
CLASS
–12.5V ≤ V
≤ –21V (Notes 15, 16)
R
–1.5V ≤ V
≤ –10.1V, SHDN Tied
PORTN
23.25
kΩ
SIGNATURE
to V
, IEEE 802.3af Two-Point
PORTN
Measurement (Notes 8, 9)
R
Invalid Signature Resistance
–1.5V ≤ V
≤ –10.1V, SHDN Tied
10
11.8
0.5
kΩ
INVALID
PORTN
to V
, IEEE 802.3af Two-Point
PORTP
Measurement (Notes 8, 9)
l
V
Active Low Power Good Output Voltage I = 1mA, V
= –54V, PWRGD
V
PWRGD_OUT
PORTN
Referenced to V
PORTN
l
l
I
Active Low Power Good Output Leakage
V
= 0V, V
= 57V
PWRGD
1
μA
V
PWRGD_LEAK
PORT
V
Active High Power Good Output Voltage I = 0.5mA, V
= –52V, V = –4V
NEG
0.35
PWRGD_OUT
PWRGD_VCLAMP
PWRGD_LEAK
PORTN
PWRGD Referenced to V
(Note 17)
NEG
l
l
l
l
l
l
V
Active High Power Good Voltage
Limiting Clamp
I = 2mA, V
= 0V, PWRGD Referenced to
12
14
16.5
1
V
NEG
(Note 3)
V
NEG
I
Active High Power Good Output Leakage
V
V
= 11V with Respect to V
,
μA
PWRGD
NEG
NEG
= V
= –54V
PORTN
R
On-Resistance
I = 700mA, V
= –48V, Measured from
0.5
0.6
0.8
Ω
Ω
ON
PORTN
(Note 16)
NEG
V
to V
PORTN
I
I
I
I
V
Leakage
V
= –57V, V
= SHDN = V =
NEG
1
μA
mA
mA
A
OUT_LEAK
LIM_HI
LIM_LO
LIM_DISA
OUT
PORTN
PORTP
0V (Note 15)
Input Current Limit, High Level
Input Current Limit, Low Level
V
= –54V, V
= –53V I
700
250
1.2
750
300
1.45
800
350
1.65
PORTN
NEG
LIM_EN
Floating (Notes 18, 19)
V
= –54V, V
= –53V
NEG
PORTN
(Notes 18, 19)
Safeguard Current Limit When I is
V
V
= –54V,
PORTN
NEG
(Notes 18, 19, 20)
LIM
Disabled
= –52.5V I
Tied To V
LIM_EN PORTN
l
f
Oscillator Frequency
C
= 100pF
84
33
100
110
200
kHz
pF
ns
ns
ns
%
OSC
OSC
C
Oscillator Capacitor Value
Minimum Switch on Time
Flyback Enable Delay Time
PG Turn-On Delay Time
Maximum Switch Duty Cycle
SYNC Pin Threshold
(Note 21)
OSC
t
t
t
200
265
200
88
ON(MIN)
ENDLY
PGDLY
l
l
DC
85
ON(MAX)
V
1.53
40
2.1
V
SYNC
R
SYNC Pin Input Resistance
kΩ
SYNC
42681fa
4
LTC4268-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 14V, SG open, VCMP = 1.5V, VSENSE = 0V, RCMP = 1k, RtON = 90k,
RPGDLY = 27.4k, RENDLY = 90k, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
I
Feedback Pin Load Compensation
Current
V
with V = 0V
SENSE
20
μA
LCOMP
RCMP
V
V
Load Comp to V
Offset Voltage
V
= 20mV, V = 1.23V
1
mV
V
LCOMP
SENSE
SENSE+
FB
l
UVLO Pin Threshold
1.215
1.237
1.265
UVLO
I
I
UVLO Pin Bias Current
V
UVLO
V
UVLO
= 1.2V
= 1.3V
–0.25
–4.50
0
–3.4
0.25
–2.5
μA
μA
UVLOL
UVLOH
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 11: Supply current does not include gate charge current to the
MOSFETs. See Application Information.
Note 12: To disable the 25k signature, tie SHDN to V
( 0.1V) or hold
PORTP
SHDN high with respect to V . See Applications Information.
IN
Note 2: All voltages are with respect to V
pin unless otherwise noted.
PORTP
Note13: I
pin is pulled high internally and for normal operation
LIM_EN
Note 3: Active High PWRGD internal clamp circuit self-regulates to 14V
should be left floating. To disable current limit, tie I
Applications Information.
to V . See
LIM_EN IN
with respect to V . V has internal 20V clamp with respect to GND.
NEG CC
Note 4: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Note 14: I
does not include classification current programmed at
IN_CLASS
Pin 3. Total supply current in classification mode will be I
(See Note 15).
+ I
CLASS
IN_CLASS
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 15: I
is the measured current flowing through R
. ΔI
CLASS
CLASS CLASS
accuracy is with respect to the ideal current defined as I
= 1.237/
CLASS
R
. T
is the time for I
to settle to within 3.5% of ideal.
CLASS CLASSRDY
CLASS
Note 5: T is calculated from the ambient temperature T and power
J
A
The current accuracy specification does not include variations in R
resistance. The total classification current for a PD also includes the IC
quiescent current (I ). See Applications Information.
Note 16: This parameter is assured by design and wafer level testing.
Note 17: Active high power good is referenced to V and is valid for
CLASS
dissipation P according to the formula:
DIS
T = T + (P • 49°C/W)
J
A
DIS
IN_CLASS
Note 6: The LTC4268-1 operates with a negative supply voltage in the
range of –1.5V to –57V. To avoid confusion, voltages in this data sheet
are referred to in terms of absolute magnitude. Terms such as “maximum
negative voltage” refer to the largest negative voltage and a “rising
negative voltage” refers to a voltage that is becoming more negative.
Note 7: In IEEE 802.3af systems, the maximum voltage at the PD jack is
defined to be –57V.
Note 8: The LTC4268-1 is designed to work with two polarity protection
diodes in series with the input. Parameter ranges specified in the Electrical
Characteristics are with respect to LTC4268-1 pins and are designed to
meet IEEE 802.3af specifications when the drop from the two diodes is
NEG
V
– V
≥ 4V.
PORTP
NEG
Note 18: The LTC4268-1 includes a dual current limit. At turn on, before
C1 is charged, the LTC4268-1 current level is set to I . After C1 is
charged and with I
LIMIT_LOW
floating, the LTC4268-1 switches to I
.
LIM_EN
LIMIT_HIGH
. The
With I
pin tied low, the LTC4268-1 switches to I
LIM_EN
LIMIT_DISA
LTC4268-1 stays in I
below the UVLO turn-off threshold or a thermal overload occurs.
or I
until the input voltage drops
LIMIT_HIGH
LIMIT_DISA
Note 19: The LTC4268-1 features thermal overload protection. In the event
of an over temperature condition, the LTC4268-1 will turn off the power
MOSFET, disable the classification load current, and present an invalid
power good signal. Once the LTC4268-1 cools below the over temperature
limit, the LTC4268-1 current limit switches to I
operation resumes.
included. See Applications Information.
Note 9: Signature resistance is measured via the two-point ΔV/ΔI method
as defined by IEEE 802.3af. The LTC4268-1 signature resistance is offset
from 25k to account for diode resistance. With two series diodes, the total
PD resistance will be between 23.75k and 26.25k and meet IEEE 802.3af
specifications. The minimum probe voltages measured at the LTC4268-1
pins are –1.5V and –2.5V. The maximum probe voltages are –9.1V and
–10.1V.
Note 10: The LTC4268-1 includes hysteresis in the UVLO voltages to
preclude any start-up oscillation. Per IEEE 802.3af requirements, the
LTC4268-1 will power up from a voltage source with 20Ω series resistance
on the first trial.
and normal
LIMIT_LOW
Note 20: I
is a safeguard current limit that is activated when the
LIMIT_DISA
normal input current limit (I
Currents at or near I
may require a reduced maximum ambient operating temperature in order
to avoid tripping the thermal overload protection.
) is defeated using the I
LIMIT_HIGH
pin.
LIM_EN
will cause significant package heating and
LIMIT_DISA
Note 21: Component value range guaranteed by design.
42681fa
5
LTC4268-1
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
Input Current vs Input Voltage
Input Current vs Input Voltage
0.5
0.4
0.3
0.2
12.0
11.5
100
80
T
= 25°C
CLASS 1 OPERATION
T
= 25°C
A
A
CLASS 5*
11.0
60
85°C
10.5
10.0
CLASS 4
CLASS 3
–40°C
40
CLASS 2
CLASS 1
0.1
0
20
0
9.5
9.0
CLASS 0
0
–4
–6
–8
–10
–2
0
–20
–30
–40
–50
–60
–12
–14
–16
–18
–20
–22
–10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
*OPTIONAL CLASS 5 CURRENT
42681 G01
42681 G03
42681 G02
Signature Resistance vs Input
Voltage
Class Operation vs Time
On Resistance vs Temperature
1.0
0.8
0.6
0.4
28
27
$V V2 – V1
T
= 25°C
A
RESISTANCE =
=
INPUT
VOLTAGE
10V/DIV
$I
DIODES: DF1501S
= 25°C
I – I
2 1
T
A
IEEE UPPER LIMIT
26
25
24
LTC4268-1 + 2 DIODES
CLASS
CURRENT
20mA/DIV
LTC4268-1 ONLY
IEEE LOWER LIMIT
0.2
0
23
22
–50
0
25
50
75
100
–25
TIME (10μs/DIV)
V1: –1
V2: –2
–3
–4
–5
–6
–7
–8
–9
–10
JUNCTION TEMPERATURE (°C)
INPUT VOLTAGE (V)
42681 G06
42681 G04
42681 G05
Active Low PWRGD: Output Low
Voltage vs Current
Active High PWRGD: Output Low
Voltage vs Current
Current Limit vs Input Voltage
1.0
0.8
0.6
0.4
0.2
0
800
600
400
200
4
3
2
1
0
–40°C
85°C
T
= 25°C
T
= 25°C
A
A
GND – V
= 4V
NEG
HIGH CURRENT MODE
LOW CURRENT MODE
–40°C
85°C
0
0.5
1
1.5
2
0
2
4
6
8
10
–40
–45
–50
–55
–60
INPUT CURRENT (mA)
INPUT VOLTAGE (V)
INPUT CURRENT (mA)
42681 G08
42681 G07
42681 G09
42681fa
6
LTC4268-1
TYPICAL PERFORMANCE CHARACTERISTICS
VCC(ON) and VCC(OFF) vs
Temperature
VCC Start-Up Current vs
Temperature
V
CC Current vs Temperature
10
9
16
15
14
13
12
11
10
9
300
250
200
150
V
CC(ON)
DYNAMIC CURRENT C = 1nF,
PG
C
SG
= 1nF, f
= 100kHz
OSC
8
7
6
STATIC PART CURRENT
= 14V
100
50
0
V
CC(OFF)
5
4
V
CC
3
8
–25
0
50
75 100 125
50
TEMPERATURE (°C)
100 125
–50
25
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
TEMPERATURE (°C)
42681 G10
42681 G12
42681 G11
SENSE Fault Voltage vs
Temperature
Oscillator Frequency vs
Temperature
SENSE Voltage vs Temperature
110
108
106
104
102
100
98
110
108
106
104
102
100
98
220
215
210
205
200
195
190
185
180
+
FB = 1.1V
+
SENSE = V
WITH V
C
= 100pF
OSC
SENSE
SENSE
–
SENSE = V
SENSE
= 0V
–
WITH V
= 0V
SENSE
96
96
94
94
92
92
90
90
–50
0
25
50
75 100 125
50
TEMPERATURE (°C)
125
–25
–50 –25
0
25
50
75 100 125
–50
0
25
75 100
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
42681 G13
42681 G14
42681 G15
Feedback Pin Input Bias vs
Temperature
VFB vs Temperature
VFB Reset vs Temperature
1.240
1.239
1.238
1.237
1.236
1.235
1.234
1.233
1.232
1.231
1.230
300
250
200
150
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
R
CMP
OPEN
100
50
0
–50
0
25
50
75 100 125
–25
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–25
0
50
75 100 125
–50
25
TEMPERATURE (°C)
TEMPERATURE (°C)
42681 G16
42681 G17
42681 G18
42681fa
7
LTC4268-1
TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Amplifier Output
Current vs VFB
Feedback Amplifier Source and
Sink Current vs Temperature
Feedback Amplifier gm vs
Temperature
70
50
70
65
60
55
1100
1050
1000
950
SOURCE CURRENT
125°C
V
FB
= 1.1V
25°C
–40°C
SINK
30
CURRENT
V
= 1.4V
FB
10
–10
–30
–50
–70
50
45
40
900
0.9
1
1.1
1.2
(V)
1.3
1.4
1.5
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
V
FB
42681 G19
42681 G20
42681 G21
Feedback Amplifier Voltage Gain
vs Temperature
UVLO vs Temperature
IUVLO Hysteresis vs Temperature
1700
1650
1600
1550
1500
1450
1400
1350
1300
1250
1200
1150
1100
1.250
1.245
1.240
1.235
3.7
3.6
3.5
3.4
3.3
3.2
3.1
1.230
1.225
1.220
3.0
–25
0
50
75 100 125
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50
25
–50 –25
0
25
75
–50 –25
0
25
75
TEMPERATURE (°C)
42681 G22
42681 G23
42681 G24
Soft-Start Charge Current vs
Temperature
PG, SG Rise and Fall Times vs
Load Capacitance
VCC Clamp Voltage vs
Temperature
21.5
21.0
20.5
20.0
19.5
19.0
23
22
21
20
19
18
17
16
15
80
70
60
50
40
30
20
10
0
T
= 25°C
I
= 10mA
CC
A
FALL TIME
RISE TIME
–25
0
50
75 100 125
–50
25
–50 –25
0
25
50
75 100 125
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE (°C)
TEMPERATURE (°C)
CAPACITANCE (nF)
42681 G25
42681 G27
42681 G26
42681fa
8
LTC4268-1
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum PG On Time vs
Temperature
Enable Delay Time vs
Temperature
PG Delay Time vs Temperature
325
305
285
265
340
330
320
310
300
290
280
270
260
300
250
R
ENDLY
= 90k
R
= 158k
tON(MIN)
R
R
= 27.4k
= 16.9k
PGDLY
PGDLY
200
150
100
245
225
205
50
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–25
0
50
75 100 125
–50
25
–50 –25
0
25
75
50
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
42681 G30
42681 G28
42681 G29
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Used to command the
V
(Pin 10): Converter Voltage Supply. Bypass this pin
CC
LTC4268-1 to present an invalid signature and remain
to GND with 4.7μF or greater. This pin has a 20V clamp
inactive.ConnectingSHDNtoV
lowersthesignature
to ground. V has an undervoltage lockout function that
PORTP
CC
resistancetoaninvalidvalueanddisablesotherLTC4268-1
turns on when V is approximately 15.3V and off at 9.7V.
CC
operations. If unused, tie SHDN to V
.
Inaconventional“trickle-charge”bootstrappedconfigura-
PORTN
tion, the V supply current increases significantly during
CC
NC (Pin 2): No internal connection.
turn-on causing a benign relaxation oscillation action on
R
(Pin 3): Class Select Input. Used to set the current
the V pin if the part does not start normally.
CLASS
CC
the LTC4268-1 maintains during classification. Connect a
t
ON
(Pin11):PrimarySwitchMinimumOnTimeControl. A
resistor between R and V . (See Table 2.)
CLASS
PORTN
programmingresistor(R )toGNDsetstheminimumtime
Ton
I
(Pin 4): Input Current Limit Enable. Used for
for each cycle. See Applications Information for details.
LIM_EN
controlling the LTC4268-1 current limit behavior during
ENDLY (Pin 12): Enable Delay Time Control. The enable
delay time is set by a programming resistor (R
GND and disables the feedback amplifier for a fixed time
after the turn-off of the primary-side MOSFET. This allows
the leakage inductance voltage spike to be ignored for
flyback voltage sensing. See Applications Information
for details.
powered operation. For normal operation, float I to
enableI
LIM_EN
todisable
) to
ENDLY
current. TieI
toV
LIMIT_HIGH
LIM_EN
PORTN
input current limit. Note that the inrush current limit will
always be active. See Applications Information.
V
(Pins 5, 6, 7): Power Input. Tie to the PD Input
PORTN
through the diode bridge. Pins 5, 6 and 7 must be electri-
cally tied together.
SYNC (Pin 13): External Sync Input. This pin is used to
synchronize the internal oscillator with an external clock.
The positive edge of the clock causes the oscillator to
dischargecausingPGtogolow(off)andSGhigh(on).The
sync threshold is typically 1.5V. Tie to ground if unused.
See Applications Information for details.
NC (Pin 8): No internal connection.
SG (Pin 9): Secondary Gate Driver Output. This pin pro-
vides an output signal for a secondary-side synchronous
switch. Large dynamic currents may flow during voltage
transitions. See the Applications Information for details.
42681fa
9
LTC4268-1
PIN FUNCTIONS
SFST (Pin 14): Soft Start. This pin, in conjunction with a
enough to start the part. The bias current on this pin has
hysteresissuchthatthebiascurrentissourcedwhenUVLO
threshold is exceeded. This introduces a hysteresis at the
pin equivalent to the bias current change times the imped-
ance of the upper divider resistor. The user can control
the amount of hysteresis by adjusting the impedance of
capacitor (C
) to GND, controls the ramp-up of peak
SFST
primary current through the sense resistor. It is also used
to control converter inrush at start-up. The SFST clamps
the V
voltage and thus limits peak current until soft
CMP
start is complete. The ramp time is approximately 70ms
per μF of capacitance. Leave SFST open if not using the
soft-start function.
the divider. Tie the UVLO pin to V if you are not using
CC
this function. See the Applications Information for details.
This pin is used for the UVLO function of the switching
regulator. The PD interface section has an UVLO defined
by the IEEE 802.3af specification.
OSC (Pin 15): Oscillator. This pin in conjunction with an
external capacitor (C ) to GND defines the controller
OSC
oscillator frequency. The frequency is approximately
100kHz • 100/C
(pF).
SENSE–, SENSE+ (Pins 19, 20): Current Sense Inputs.
These pins are used to measure primary side switch cur-
rent through an external sense resistor. Peak primary side
current is used in the converter control loop. Make Kelvin
OSC
FB(Pin16):FeedbackAmplifierInput. Feedbackisusually
sensed via a third winding and enabled during the flyback
period.Thispinalsosinksadditionalcurrenttocompensate
for load current variation as set by the R
Thevenin equivalent resistance of the feedback divider at
roughly 3k.
connections to the sense resistor R
to reduce noise
SENSE
pin. Keep the
CMP
problems.SENSE–connectstotheGNDside.Atmaximum
current (V at its maximum voltage) SENSE pins have
CMP
100mV threshold. The signal is blanked (ignored) during
the minimum turn-on time.
V
(Pin 17): Frequency Compensation Control. V
is
CMP
CMP
used for frequency compensation of the switcher control
loop. Itistheoutputofthefeedbackamplifierandtheinput
tothecurrentcomparator. Switcherfrequencycompensa-
tion components are normally placed on this pin to GND.
The voltage on this pin is proportional to the peak primary
switch current. The feedback amplifier output is enabled
during the synchronous switch on time.
C
(Pin 21): Load Compensation Capacitive Control.
CMP
Connect a capacitor from C
to GND in order to reduce
CMP
the effects of parasitic resistances in the feedback sens-
ing path. A 0.1μF ceramic capacitor suffices for most
applications. Short this pin to GND in less demanding
applications.
R
(Pin 22): Load Compensation Resistive Control.
CMP
UVLO (Pin 18): Undervoltage Lockout. A resistive divider
Connect a resistor from R
to GND in order to com-
CMP
from V to this pin sets an undervoltage lockout based
IN
pensate for parasitic resistances in the feedback sensing
path. In less demanding applications, this resistor is not
needed and this pin can be left open. See Applications
Information for details.
upon V level (not V ). When the UVLO pin is below its
IN
CC
threshold,thegatedrivesaredisabled,butthepartdrawsits
normal quiescent current from V . The V undervoltage
CC
CC
lockout supersedes this function so V must be great
CC
42681fa
10
LTC4268-1
PIN FUNCTIONS
PGDLY (Pin 23): Primary Gate Delay Control. Connect an
external programming resistor (R
can start operation. High impedance indicates power is
) to set delay from
good. PWRGD is referenced to V
and is low imped-
PGDLY
NEG
synchronous gate turn-off to primary gate turn-on. See
Applications Information for details.
ance during inrush and in the event of a thermal overload.
PWRGD is clamped to 14V above V
.
NEG
PG (Pin 24): Primary Gate Drive. PG is the gate drive pin
for the primary side MOSFET Switch. Large dynamic cur-
rents flow during voltage transitions. See the Applications
Information for details.
PWRGD (Pin 30): Active Low Power Good Output, Open-
Drain. Signals to the DC/DC converter that the LTC4268-1
MOSFET is on and that the converter can start operation.
Low impedance indicates power is good. PWRGD is ref-
erenced to V
and is high impedance during detec-
PORTN
NC (Pin 25): No internal connection.
tion, classification and in the event of a thermal overload.
PWRGD h as no internal clamps.
V
(Pins 26, 27, 28): System Negative rail. Tie to the
NEG
GND pin to supply power to the flyback controller through
NC (Pin 31): No internal connection.
the internal power MOSFET. V is high impedance until
NEG
the input voltage rises above the UVLO turn-on threshold.
V
(Pin32):Positivepowerinput. Tietotheinputport
PORTP
The output is then connected to V through a cur-
power return through the input diode bridge.
PORTN
rent-limited internal MOSFET switch. Pins 26, 27 and 28
GND (Pin 33): Ground. This is the negative rail connection
must be electrically tied together.
for both signal ground and gate driver grounds. This pin
PWRGD (Pin 29): Active High Power Good Output,
Open-Collector. Signals to the flyback controller that the
LTC4268-1 MOSFET is on and that the flyback controller
shouldbeconnectedtoV .Carefulattentionmustbepaid
NEG
to layout. See the Applications Information for details.
42681fa
11
LTC4268-1
BLOCK DIAGRAM
CLASSIFICATION
CURRENT LOAD
V
SHDN
1
PORTP
NC
32
31
30
1.237V
+
–
16k 25k
2
3
NC
R
CLASS
PWRGD
I
LIM_EN
CONTROL
CIRCUITS
4
INPUT
CURRENT
LIMIT
PWRGD
1400mA
750mA
300mA
29
V
V
V
PORTN
PORTN
PORTN
+
5
6
7
14V
V
V
V
NEG
–
28
27
26
NEG
NEG
BOLD LINE INDICATES
HIGH CURRENT PATH
V
CC
10
CLAMPS
V
CC
UVLO
20V
0.7
+
–
+
–
FB
16
17
1.3
ERROR AMP
–
+
1.237V
REFERENCE
(V
V
15.3V
CMP
3V
)
FB
INTERNAL
REGULATOR
S
R
Q
Q
COLLAPSE DETECT
–
–
+
+
UVLO
+
UVLO
–
SFST
1V
18
14
19
CURRENT
COMPARATOR
OVERCURRENT
FAULT
I
UVLO
–
+
–
TSD
–
SENSE
CURRENT
SENSE AMP
+
CURRENT TRIP
+
SENSE
SLOPE COMPENSATION
ENABLE
20
21
R
CMPF
50k
OSC
15
OSCILLATOR
C
CMP
SET
+
–
SYNC
13
11
23
12
LOAD
COMPENSATION
t
ON
LOGIC
BLOCK
R
CMP
PGDLY
ENDLY
TO FB
22
24
V
CC
GATE DRIVE
PGATE
SGATE
PG
+
3V
–
V
CC
GATE DRIVE
SG
9
GND
33
42681 BD
42681fa
12
LTC4268-1
APPLICATIONS INFORMATION
OVERVIEW
One of the basic architectural decisions associated with
a high power PoE system is whether to deliver power
using four conductors (2-pair) or all eight conductors
(4-pair). Each method provides advantages and the
system vendor needs to decide which method best suits
their application.
Power over Ethernet (PoE) continues to gain popularity
as an increasing number of products are taking advantage
of having DC power and high speed data available from a
single RJ45 connector. As PoE is becoming established in
themarketplace,PoweredDevice(PD)equipmentvendors
are running into the 12.95W power limit established by
the IEEE 802.3af standard. To solve this problem and
expand the application of PoE, the LTC4268-1 breaks
the power barrier by allowing custom PoE applications
to deliver up to 35W for power hungry PoE applications
such as dual band access points, RFID readers and PTZ
security cameras.
2-pair power is used today in 802.3af systems (see
Figure 1A). One pair of conductors is used to deliver the
current and a second pair is used for the return while two
conductor pairs are not powered. This architecture offers
the simplest implementation method but suffers from
higher cable loss than an equivalent 4-pair system.
4-pair power delivers current to the PD via two conductor
pairs in parallel (Figure 1B). This lowers the cable resis-
tance but raises the issue of current balance between each
conductorpair.Differencesinresistanceofthetransformer,
cableandconnectorsalongwithdifferencesindiodebridge
forward voltage in the PD can cause an imbalance in the
currents flowing through each pair. The 4-pair system in
Figure 1B solves this problem by using two independent
DC/DCconvertersinthePD. Usingthisarchitecturesolves
the balancing issue and allows the PD to be driven by two
independent PSEs, for example an Endpoint PSE and a
Midspan PSE. Contact Linear Technology applications
support for detailed information on implementing 2-pair
and 4-pair PoE systems.
The LTC4268-1 is designed to be a complete solution
for PD applications with power requirements up to 35W.
The LTC4268-1 interfaces with custom Power Sourcing
Equipment (PSE) using a high efficiency flyback topol-
ogy for maximum power delivery without the need for
optoisolator feedback. Off-the-shelf high power PSEs are
available today from a variety of vendors for use with the
LTC4268-1 to allow quick implementation of a custom
system.Alternately,thesystemvendorcanchoosetobuild
their own high power PSE. Linear Technology provides
complete application information for high power PSE
solutions delivering up to 35W for 2-pair systems and as
much as 70W when used in 4-pair systems.
PSE
PD
RJ45
4
RJ45
CAT 5
4
5
5
SPARE PAIR
GND
DF1501S
0.1μF
100V
0.1μF
1k
1
1
DGND BYP
AGND
DETECT
SMAJ58A
58V
Tx
Rx
Tx
3.3V
V
DD
2
3
2
3
DATA PAIR
DATA PAIR
CMPD3003
1/4
LTC4259A-1
0.47μF
100V
Rx
0.1μF
V
EE
SENSE GATE OUT
6
6
+
OUT
SMAJ58A
58V
10k
LTC4268-1
TYP APP
V
0.25Ω
–54V
7
8
7
IRLR3410
–
S1B
8
DF1501S
SPARE PAIR
42681 F01a
Figure 1A. 2-Pair High Power PoE System Diagram
42681fa
13
LTC4268-1
APPLICATIONS INFORMATION
The LTC4268-1 is specifically designed to implement
the high power PD front end and switching regulator for
power-hungry PoE applications that must operate beyond
the power limits of IEEE 802.3af. The LTC4268-1 uses
a precision, dual current limit that keeps inrush below
IEEE 803.2af levels to ensure interoperability with any
PSE.Afterinrushiscomplete,theLTC4268-1inputcurrent
classificationmethodstomaintaincomplianceandincludes
anextendedprogrammableClass5rangeforuseincustom
PoE applications. The LTC4268-1 features both active-
high and active-low power good signaling for simplified
interfacetotheconverter. TheSHDNpinontheLTC4268-1
can be used to provide a seamless interface for external
walladaptersorotherauxiliarypoweroptions.TheI
LIM_EN
limit switches to the I
level, using an onboard,
pin provides the option to remove the high current limit,
I .TheLTC4268-1includesanonboardsignature
LIMIT_HIGH
resistor, precision UVLO, thermal overload protection and
is available in a thermally-enhanced 32-lead 7mm × 4mm
DFN package for superior high current performance.
LIMIT_HIGH
750mA power MOSFET. This allows a PD (supplied by a
custom PSE) to deliver power above the IEEE 802.3af
12.95W maximum, sending up to 35W to the PD load. The
LTC4268-1 uses established IEEE 802.3af detection and
PSE
RJ45
PD
GND
RJ45
0.1μF
0.1μF
CAT5
1
1
DGND BYP
AGND
SMAJ58A
Tx1
Rx1
Tx1
0.1μF
DF1501S
3.3V
V
DD
AUTO
DETECT
2
3
2
3
CMPD3003
1k
0.47μF
1/4
LTC4259A
LTC4268-1
TYP APP
Rx1
V
SENSE GATE OUT
10k
EE
6
4
6
+
–
–
+
SMAJ58A
S1B
+
0.25Ω
V
–54V
OUT
IRLR3410
–
0.1μF
SMAJ58A
GND
0.1μF
4
AGND
Tx2
Rx2
Tx2
LTC4268-1
TYP APP
DETECT
5
7
5
7
CMPD3003
1k
0.47μF
1/4
LTC4259A
DF1501S
Rx2
V
EE
SENSE GATE OUT
10k
8
8
SMAJ58A
S1B
0.25Ω
42681 F01b
–54V
IRLR3410
Figure 1B. 4-Pair High Power PoE Gigabit Ethernet
42681fa
14
LTC4268-1
APPLICATIONS INFORMATION
OPERATION
thresholds,theLTC4268-1extendstwodiodedropsbelow
the IEEE 802.3af specifications. The LTC4268-1 threshold
points support the use of either traditional or Schottky
diode bridges.
Note: Please refer to the simplified application circuit
(Figure 2) for voltage naming conventions used in this
datasheet.
The LTC4268-1 high power PD interface controller and
switchingregulatorhasseveralmodesofoperationdepend-
DETECTION
During detection, the PSE will apply a voltage in the range
of –2.8V to –10V on the cable and look for a 25k signature
resistor. This identifies the device at the end of the cable
as a PD. With the PSE voltage in the detection range, the
LTC4268-1 presents an internal 25k resistor between the
ing on the applied V
voltage as shown in Figure 3 and
PORT
summarized in Table 1. These various modes satisfy the
requirementsdefinedintheIEEE802.3afspecification.The
input voltage is applied to the V
pin with reference
PORTN
to the V
pin and is always negative.
PORTP
V
and V
pins. This precision, temperature-
PORTP
PORTN
compensated resistor provides the proper characteristics
to alert the PSE that a PD is present and requests power
to be applied.
SERIES DIODES
The IEEE 802.3af-defined operating modes for a PD refer-
ence the input voltage at the RJ45 connector on the PD.
In this datasheet port voltage is normally referenced to
the pins of the LTC4268-1. Note that the voltage ranges
specified in the LTC4268-1 Electrical Specifications are
referenced with respect to the IC pins.
Table 1. LTC4268-1 Operational Mode as a Function
of VPORT Voltage
V
PORT
MODE OF OPERATION
0V to –1.4V
Inactive
–1.5V to –10.1V
–10.3V to –12.4V
25k Signature Resistor Detection
The PD must be able to handle power received in either
polarity. For this reason, it is common to install diode
bridges between the RJ45 connector and the LTC4268-1
(Figure 4). The diode bridges introduce an offset that
affects the threshold points for each range of operation.
The LTC4268-1 meets the IEEE 802.3af-defined operating
modesbycompensatingforthediodedropsinthethreshold
points. For the signature, classification, and the UVLO
Classification Load Current Ramps Up from 0%
to 100%
–12.5V to UVLO*
UVLO* to –57V
Classification Load Current Active
Power Applied to PD Load
*UVLO includes hysteresis.
Rising input threshold ≅ –38.9V
Falling input threshold ≅ –30.6V
RJ45
+
1
TX
16 T1
15
1
2
•
+
+
~
~
+
–
–
TX
14
11
3
6
•
2
3
+
V
V
V
OUT
TO PHY
RX
PORT
IN
10
9
7
8
–
RX
6
V
PORTP
V
CC
+
–
SPARE
PG
LTC4268-1
4
5
7
8
~
~
+
–
GND
SPARE
V
V
NEG
PORTN
PD FRONT END
SWITCHING REGULATOR
ISOLATED OUTPUT
42681 F02
Figure 2. Simplified Application Circuit with Voltage Naming Conventions
42681fa
15
LTC4268-1
APPLICATIONS INFORMATION
The IEEE 802.3af specification requires the PSE to use
a ΔV/ΔI measurement technique to keep the DC offset
voltage of the diode bridge from affecting the signature
resistance measurement. However, the diode resistance
appears in series with the signature resistor and must be
included in the overall signature resistance of the PD.
The LTC4268-1 compensates for the two series diodes in
the signature path by offsetting the internal resistance so
that a PD built with the LTC4268-1 meets the IEEE 802.3af
specification.
DETECTION V1
TIME
DETECTION V2
–10
–20
–30
–40
–50
CLASSIFICATION
UVLO
TURN-OFF
UVLO
TURN-ON
TIME
C1
T = R
LOAD
–10
UVLO
OFF
UVLO
ON
UVLO
OFF
–20
–30
–40
I
LIMIT_LOW
C1
dV
dt
=
–50
TIME
–10
–20
–30
–40
–50
POWER
BAD
POWER
GOOD
POWER
BAD
PWRGD TRACKS
IN
V
20
10
POWER
BAD
POWER
GOOD
POWER
BAD
TIME
LOAD, I
I
LIMIT_HIGH
LOAD
(UP TO I
)
LIMIT_HIGH
I
LIMIT_LOW
I
CLASS
CLASSIFICATION
TIME
DETECTION I
2
DETECTION I
1
V1 – 2 DIODE DROPS
25kΩ
V2 – 2 DIODE DROPS
25kΩ
I
1
=
I
2
=
I
I
DEPENDENT ON R
SELECTION
CLASS
CLASS
= 300mA, I
= 750mA
LIMIT_LOW
LIMIT_HIGH
V
IN
I
=
LOAD
R
LOAD
LTC4268-1
R
I
LOAD
C1
IN
R
V
PORTP
CLASS
PSE
V
PORT
V
IN
+
R
PWRGD
PWRGD
CLASS
V
V
NEG
PORTN
42681 F03
Figure 3. VIN Voltage, PWRGD, PWRGD and PD Current as a Function of Port Voltage
42681fa
16
LTC4268-1
APPLICATIONS INFORMATION
In some designs that include an auxiliary power option,
such as an external wall adapter, it is necessary to control
whether or not the PD is detected by a PSE. With the
LTC4268-1, the 25k signature resistor can be enabled or
disabled with the SHDN pin (Figure 5). Taking the SHDN
pin high will reduce the signature resistor to 10k which is
an invalid signature per the IEEE 802.3af specifications.
This will prevent a PSE from detecting and powering the
PD. This invalid signature is present in the PSE probing
range of –2.8V to –10V. When the input rises above –10V,
the signature resistor reverts to 25k to minimize power
dissipation in the LTC4268-1. To disable the signature,
tie SHDN to VPORTP. Alternately, the SHDN pin can be
CLASSIFICATION
Once the PSE has detected a PD, the PSE may option-
ally classify the PD. Classification provides a method for
more efficient allocation of power by allowing the PSE
to identify lower-power PDs and assign the appropriate
power level to these devices. For each class, there is an
associated load current that the PD asserts onto the line
during classification probing. The PSE measures the PD
load current in order to assign the proper PD classifica-
tion. Class 0 is included in the IEEE 802.3af specification
to cover PDs that do not support classification. Class 1-3
partition PDs into three distinct power ranges as shown
in Table 2. Class 4 was reserved by the IEEE 802.3af
committee for future use and has been reassigned as a
high power indicator by IEEE 802.3at. The new Class 5
driven high with respect to V
. When SHDN is high,
PORTN
all functions are disabled. For normal operation tie SHDN
to V
.
PORTN
RJ45
1
+
T1
TX
BR1
–
TX
2
3
+
–
TO PHY
RX
RX
POWERED
DEVICE (PD)
INTERFACE
6
V
PORTP
+
–
AS DEFINED
SPARE
BR2
4
5
BY IEEE 802.3af
LTC4268-1
0.1μF
100V
D3
V
PORTN
7
8
42681 F04
SPARE
Figure 4. PD Front End Using Diode Bridges on Main and Spare Inputs
LTC4268-1
SHDN
V
PORTP
25k SIGNATURE
RESISTOR
TO
PSE
16k
V
PORTN
42681 F05
SIGNATURE DISABLE
Figure 5. 25k Signature Resistor with Disable
42681fa
17
LTC4268-1
APPLICATIONS INFORMATION
defined here is available for system vendors to implement
a unique classification for use in closed systems and is
not defined or supported by the IEEE 802.3af. With the
extendedclassificationrangeavailableintheLTC4268-1,it
ispossibleforsystemdesignerstodefinemultipleclasses
using load currents between 40mA and 75mA.
the signature and classification ranges up to UVLO turn
on as shown in Figure 6b. The positive I-V slope avoids
areas of negative resistance and helps prevent the PSE
from power cycling or getting “stuck” during signature
or classification probing. In the event a PSE overshoots
beyond the classification voltage range, the available load
currentaidsinreturningthePDbackintotheclassification
voltage range. (The PD input may otherwise be “trapped”
by a reverse-biased diode bridge and the voltage held by
the 0.1μF capacitor.) By gently ramping the classification
current on and maintaining a positive I-V slope until UVLO
turn-on, the LTC4268-1 provides a well behaved load,
assuring interoperability with any PSE.
During classification, the PSE presents a fixed voltage
between–15.5Vand–20.5VtothePD(Figure6a).Withthe
input voltage in this range, the LTC4268-1 asserts a load
current from the V
pin through the R
resistor.
PORTP
CLASS
The magnitude of the load current is set with the selection
of the R
resistor. The resistor value associated with
CLASS
each class is shown in Table 2.
Table 2. Summary of IEEE 802.3af Power Classifications and
LTC4268-1 RCLASS Resistor Selection
CURRENT PATH
MAXIMUM
NOMINAL
LTC4268-1
RCLASS
PSE
POWER LEVELS CLASSIFICATION
LTC4268-1
PROBING
AT INPUT OF PD LOAD CURRENT RESISTOR
VOLTAGE
SOURCE
–15.5V TO –20.5V
V
PORTP
R
CLASS
CLASS
USAGE
Default
(W)
(mA)
(Ω, 1%)
Open
124
CONSTANT
LOAD
CURRENT
INTERNAL
TO LTC4268-1
0
1
2
3
4
5
0.44 to 12.95
0.44 to 3.84
3.84 to 6.49
6.49 to 12.95
<5
R
CLASS
Optional
Optional
Optional
10.5
18.5
28
V
PORTN
42681 F06a
69.8
V
45.3
PSE CURRENT MONITOR
Reserved by IEEE. See Apps
Undefined by IEEE. See Apps
40
30.9
PSE
PD
56
22.1
Figure 6a. PSE Probing PD During Classification
A substantial amount of power is dissipated in the
LTC4268-1 during classification. The IEEE 802.3af
specificationlimitstheclassificationtimeto75msinorder
avoid excessive heating. The LTC4268-1 is designed to
handle the power dissipation during the probe period.
If the PSE probing exceeds 75ms, the LTC4268-1 may
overheat. In this situation, the thermal protection circuit
will engage and disable the classification current source,
protecting the LTC4268-1 from damage. When the die
cools, classification is automatically resumed.
–20
–30
0
–40
–10
Classification presents a challenging stability problem
for the PSE due to the wide range of loads possible. The
LTC4268-1hasbeendesignedtoavoidPSEinteroperability
problems by maintaining a positive I-V slope throughout
V
(V)
PORT
42681 F06b
Figure 6b. LTC4268-1 Positive I-V Slope
42681fa
18
LTC4268-1
APPLICATIONS INFORMATION
UNDERVOLTAGE LOCKOUT
INPUT CURRENT LIMIT
IEEE802.3afspecifiesamaximuminrushcurrentandalso
specifies a minimum load capacitor between the V
TheIEEE802.3afspecificationdictatesamaximumturn-on
voltage of 42V and a minimum turn-off voltage of 30V for
the PD. In addition, the PD must maintain large on-off
hysteresis to prevent current-resistance (I-R) drops in the
wiring between the PSE and the PD from causing start-up
oscillation. The LTC4268-1 incorporates an undervoltage
lockout (UVLO) circuit that monitors line voltage at
PORTP
and V
pins. To control turn-on surge currents in the
NEG
systemtheLTC4268-1integratesadualcurrentlimitcircuit
using an onboard power MOSFET and sense resistor to
provideacompleteinrushcontrolcircuitwithoutadditional
external components. At turn-on, the LTC4268-1 will limit
V
to determine when to apply power to the PD load
the inrush current to I
, allowing the load capaci-
LIMIT_LOW
PORTN
(Figure 7). Before power is applied to the load, the V
tor to ramp up to the line voltage in a controlled manner
withoutinterferencefromthePSEcurrentlimit.Bykeeping
the PD current limit below the PSE current limit, PD power
up characteristics are well controlled and independent of
PSE behavior. This ensures interoperability regardless of
PSE output characteristics.
NEG
pin is high impedance and there is no charge on capacitor
C1. When the input voltage rises above the UVLO turn-on
threshold, the LTC4268-1 removes the classification load
current and turns on the internal power MOSFET. C1
charges up under LTC4268-1 inrush current limit control
and the V
pin transitions from 0V to V
as shown
NEG
PORTN
After load capacitor C1 is charged up, the LTC4268-1
in Figure 3. The LTC4268-1 includes a hysteretic UVLO
circuit on V that keeps power applied to the load
switches to the high input current limit, I . This
LIMIT_HIGH
PORTN
allows the LTC4268-1 to deliver up to 35W to the PD load
for high power applications. To maintain compatibility
with IEEE 802.3af power levels, it is necessary for the PD
designertoensurethePDsteady-statepowerconsumption
remains below the limits shown in Table 2. The LTC4268-1
maintains the high input current limit until the port voltage
drops below the UVLO turn-off threshold.
until the magnitude of the input voltage falls below the
UVLO turn-off threshold. Once V falls below UVLO
PORTN
turn-off, the internal power MOSFET disconnects V
NEG
from V
and the classification current is re-enabled.
PORTN
C1 will discharge through the PD circuitry and the V
pin will go to a high impedance state.
NEG
+
C1
LTC4268-1
V
PORTP
5μF
MIN
TO
PSE
V
IN
UNDERVOLTAGE
LOCKOUT
CIRCUIT
V
V
NEG
PORTN
42681 F07
CURRENT-LIMITED
TURN ON
V
LTC4268-1
PORT
VOLTAGE
0V TO UVLO*
>UVLO*
POWER MOSFET
OFF
ON
*UVLO INCLUDES HYSTERESIS
RISING INPUT THRESHOLD –38.9V
FALLING INPUT THRESHOLD –30.6V
Figure 7. LTC4268-1 Undervoltage Lockout
42681fa
19
LTC4268-1
APPLICATIONS INFORMATION
During the inrush event as C1 is being charged, a large
amount of power is dissipated in the MOSFET. The
LTC4268-1 is designed to accept this load and is thermally
protected to avoid damage to the onboard power MOSFET.
If a thermal overload does occur, the power MOSFET turns
off, allowing the die to cool. Once the die has returned to
asafetemperature, theLTC4268-1automaticallyswitches
Table 3. Current Limit as a Function of ILIM_EN
INRUSH CURRENT
OPERATING INPUT
CURRENT LIMIT
STATE OF I
LIMIT
LIM_EN
Floating
Tied to V
I
I
I
LIMIT_LOW
LIMIT_LOW
LIMT_HIGH
I
PORTN
LIMIT_DISA
POWER GOOD
to I
, and load capacitor C1 charging resumes.
LIMIT_LOW
The LTC4268-1 includes complementary power good
outputs (Figure 8) to simplify connection to any DC/DC
converter. Power Good is asserted at the end of the inrush
event when load capacitor C1 is fully charged and the
DC/DC converter can safely begin operation. The power
good signal stays active during normal operation and is
de-asserted at power off when the port drops below the
UVLO threshold or in the case of a thermal overload event.
For PD designs that use a large load capacitor and also
consume a lot of power, it is important to delay activation
of the DC/DC converter with the power good signal. If
the converter is not disabled during the current-limited
turn-on sequence, the DC/DC converter will rob current
intended for charging up the load capacitor and create a
slow rising input, possibly causing the LTC4268-1 to go
into thermal shutdown.
The LTC4268-1 has the option of disabling the normal
operating input current limit, I , for custom
LIMIT_HIGH
high power PoE applications. To disable the current limit,
connect I to V . To protect the LTC4268-1
LIM_EN
PORTN
from damage when the normal current limit is disabled, a
safeguardcurrentlimit,I keepsthecurrentbelow
LIMIT_DISA
destructive levels, typically 1.4A. Note that continuous
operation at or near the safeguard current limit will rapidly
overheat the LTC4268-1, engaging the thermal protection
circuit. For normal operations, float the I
pin. The
LIM_EN
inrush current limit
LTC4268-1 maintains the I
LIMIT_LOW
for charging the load capacitor regardless of the state of
I
. The operation of the I
pin is summarized
LIM_EN
in Table 3.
LIM_EN
LTC4268-1
30 PWRGD
UVLO
THERMAL SD
CONTROL
CIRCUIT
INRUSH COMPLETE
AND NOT IN THERMAL SHUTDOWN
POWER
POWER
NOT
GOOD
29 PWRGD
REF
GOOD
V
5
28
V
PORTN
NEG
V
< UVLO OFF
PORT
OR THERMAL SHUTDOWN
V
V
6
7
27
26
V
V
PORTN
NEG
NEG
PORTN
42681 F08
BOLD LINE INDICATES HIGH CURRENT PATH
Figure 8. LTC4268-1 Power Good Functional and State Diagram
42681fa
20
LTC4268-1
APPLICATIONS INFORMATION
The active high PWRGD pin features an internal,
example, if the PD input voltage steps from –37V to –57V,
the instantaneous power dissipated by the LTC4268-1 can
be as high as 16W. The LTC4268-1 protects itself from
damage by monitoring die temperature. If the die exceeds
the overtemperature trip point, the power MOSFET and
classification transistors are disabled until the part cools
down. Once the die cools below the overtemperature
trip point, all functions are enabled automatically. During
classification, excessive heating of the LTC4268-1 can
occur if the PSE violates the 75ms probing time limit.
In addition, the IEEE 802.3af specification requires a PD
to withstand application of any voltage from 0V to 57V
indefinitely. To protect the LTC4268-1 in these situations,
the thermal protection circuitry disables the classification
circuit and the input current if the die temperature exceeds
the overtemperature trip point. When the die cools down,
classification and input current are enabled.
open-collector output referenced to V . During inrush,
NEG
theactivehighPWRGDpinbecomesvalidwhenC1reaches
–4V and pulls low until the load capacitor is fully charged.
Atthatpoint,PWRGDbecomeshighimpedance,indicating
the switching regulator may begin running. The active
high PWRGD pin interfaces directly to the UVLO pin of
the LTC4268-1 with the aid of an external pull-up resistor
to Vcc. The PWRGD pin includes an internal 14V clamp to
V
. During a power supply ramp down event, PWRGD
NEG
becomeslowimpedancewhenV
dropsbelowthe30V
PORT
PD UVLO turn-off threshold, then goes high impedance
whentheV voltagesfalltowithinthedetectionvoltage
PORT
range. Figure 11 shows a typical connection scheme for
the active high PWRGD pin.
The LTC4268-1 also includes an active low PWRGD pin
for system level use. PWRGD is referenced to the V
PORTN
pin and when active will be near the V
potential. The
OncetheLTC4268-1haschargeduptheloadcapacitorand
thePDispoweredandrunning,therewillbesomeresidual
heatingduetotheDCloadcurrentofthePDflowingthrough
the internal MOSFET. In some high current applications,
the LTC4268-1 power dissipation may be significant. The
LTC4268-1 uses a thermally enhanced DFN package that
includes an exposed pad which should be soldered to the
GND plane for heatsinking on the printed circuit board.
PORTN
negative rail (GND) of the internal switching regulator will
typically be referenced to V
and care must be taken to
NEG
ensure that the difference in potential of the PWRGD pin
does not cause a problem for the switcher.
THERMAL PROTECTION
The LTC4268-1 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
At turn-on, before load capacitor C1 has charged up, the
instantaneous power dissipated by the LTC4268-1 can be
as high as 20W. As the load capacitor charges, the power
dissipation in the LTC4268-1 will decrease until it reaches
a steady-state value dependent on the DC load current.
The LTC4268-1 can also experience device heating after
turn-on if the PD experiences a fast input voltage rise. For
MAXIMUM AMBIENT TEMPERATURE
The LTC4268-1 I
pin allows the PD designer to
LIM_EN
disablethenormaloperatingcurrentlimit.Withthenormal
current limit disabled, it is possible to pass currents
as high as 1.4A through the LTC4268-1. In this mode,
significant package heating may occur. Depending on the
current, voltage, ambient temperature, and waveform
characteristics, the LTC4268-1 may shut down. To avoid
42681fa
21
LTC4268-1
APPLICATIONS INFORMATION
nuisancetripsofthethermalshutdown,itmaybenecessary
to limit the maximum ambient temperature. Limiting the
die temperature to 125°C will keep the LTC4268-1 from
hitting thermal shutdown. For DC loads the maximum
ambient temperature can be calculated as:
reduces the perceived inductance and can interfere with
data transmission. Transformers specifically designed for
highcurrentapplicationsarerequired.Transformervendors
suchasBelFuse, Coilcraft, Halo, Pulse, andTyco(Table 4)
can provide assistance with selection of an appropriate
T
= 125 – θ • PWR (°C)
MAX
JA
Table 4. Power over Ethernet Transformer Vendors
where T
is the maximum ambient operating tempera-
VENDOR
CONTACT INFORMATION
MAX
ture, θ is the junction-to-ambient thermal resistance
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
JA
(49°C/W), and PWR is the power dissipation for the
LTC4268-1 in Watts (I
2
• R ).
PD
ON
Coilcraft Inc.
1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
Halo Electronics
Pulse Engineering
Tyco Electronics
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
Nodes on an Ethernet network commonly interface to
the outside world via an isolation transformer (Figure 9).
For powered devices, the isolation transformer must
include a center tap on the media (cable) side. Proper
termination is required around the transformer to provide
correct impedance matching and to avoid radiated and
conductedemissions.Forhighpowerapplicationsbeyond
IEEE 802.3af limits, the increased current levels increase
the current imbalance in the magnetics. This imbalance
www.haloelectronics.com
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
www.pulseeng.com
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
www.circuitprotection.com
RJ45
+
1
TX
16 T1
15
1
2
BR1
HD01
–
TX
14
11
3
6
2
3
+
TO PHY
RX
10
9
7
8
–
RX
6
PULSE H2019
V
PORTP
V
IN
+
–
SPARE
+
4
5
7
8
BR2
HD01
C1
LTC4268-1
C14
0.1μF
100V
D3
SMAJ58A
TVS
SPARE
V
V
NEG
PORTN
42681 F09
Figure 9. PD Front-End Isolation Transformer, Diode Bridges, Capacitors and TVS
42681fa
22
LTC4268-1
APPLICATIONS INFORMATION
isolation transformer and proper termination methods.
These vendors have transformers specifically designed
for use in high power PD applications.
The input diode bridge of a PD can consume over 4% of
the available power in some applications. Schottky diodes
can be used in order to reduce power loss. The LTC4268-1
is designed to work with both standard and Schottky
diode bridges while maintaining proper threshold points
for IEEE 802.3af compliance.
IEEE 802.3af allows power wiring in either of two
configurations on the TX/RX wires, and power can be
applied to the PD via the spare wire pair in the RJ45
connector. The PD is required to accept power in either
polarity on both the data and spare inputs; therefore it is
common to install diode bridges on both inputs in order
toaccommodatethedifferentwiringconfigurations.Figure
9 demonstrates an implementation of the diode bridges
to minimize heating. The IEEE 802.3af specification also
mandatesthattheleakagebackthroughtheunusedbridge
be less than 28μA when the PD is powered with 57V.
Auxiliary Power Source
In some applications, it may be necessary to power the PD
from an auxiliary power source such as a wall adapter. The
auxiliary power can be injected into the PD at several loca-
tions and various trade-offs exist. Figure 10 demonstrates
four methods of connecting external power to a PD.
Option 1 in Figure 10 inserts power before the LTC4268-1
interface controller. In this configuration, it is necessary
for the wall adapter to exceed the LTC4268-1 UVLO turn-
on requirement. This option provides input current limit
for the adapter, provides a valid power good signal and
simplifies power priority issues. As long as the adapter
applies power to the PD before the PSE, it will take priority
and the PSE will not power up the PD because the external
power source will corrupt the 25k signature. If the PSE
is already powering the PD, the adapter power will be in
parallel with the PSE. In this case, priority will be given to
the higher supply voltage. If the adapter voltage is higher,
the PSE may remove the port voltage since no current will
be drawn from the PSE. On the other hand, if the adapter
voltage is lower, the PSE will continue to supply power to
the PD and the adapter will not be used. Proper operation
will occur in either scenario.
ThePDmaybeconfiguredtohandle2-pairor4-pairpower
delivery over the Ethernet cable. In a 2-pair power delivery
system, one of the two pairs is delivering power to the
PD – either the main pair or the spare pair, but not both.
In a 4-pair system, both the main and spare pairs deliver
power to the PD simultaneously (see Figure 1). In either
case, a diode bridge is needed on the front end to accept
power in either polarity. Contact LTC applications for more
information about implementing a 4-pair PoE system.
The IEEE standard includes an AC impedance requirement
inordertoimplementtheACdisconnectfunction.Capacitor
C14 in Figure 9 is used to meet this AC impedance
requirement. A 0.1μF capacitor is recommended for this
application.
The LTC4268-1 has several different modes of operation
based on the voltage present between the V
PORTP
in a PD design subtracts from the input voltage and will
affect the transition point between modes.
and
PORTN
Option 2 applies power directly to the DC/DC converter.
In this configuration the adapter voltage does not need to
exceed the LTC4268-1 turn-on UVLO requirement and can
be selected based solely on the PD load requirements. It
V
pins. The forward voltage drop of the input diodes
42681fa
23
LTC4268-1
APPLICATIONS INFORMATION
OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4268-1
RJ45
1
+
T1
TX
D3
SMAJ58A
TVS
~
~
+
–
–
C14
0.1μF
100V
TX
+
2
3
+
–
C1
TO PHY
RX
BR1
BR2
RX
V
IN
6
V
PORTP
• 42V ≤ V
≤ 57V
WW
+
–
SPARE
4
5
7
8
~
~
+
–
• NO POWER PRIORITY ISSUES
LTC4268-1
• LTC4268-1 CURRENT LIMITS FOR BOTH PoE AND V
WW
SPARE
V
V
PORTN NEG
+
D8
S1B
ISOLATED
WALL
TRANSFORMER
V
WW
–
OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4268-1 WITH SIGNATURE DISABLED
RJ45
1
+
T1
TX
D3
SMAJ58A
TVS
~
~
+
–
–
C14
0.1μF
100V
TX
+
2
3
+
C1
TO PHY
RX
BR1
BR2
–
RX
V
IN
6
V
4.7k
PORTP
+
–
SPARE
BSS63
4
5
7
8
~
~
+
–
LTC4268-1
D9
100k
SHDN
V
S1B
SPARE
V
PORTN NEG
• V
ANY VOLTAGE BASED ON PD LOAD
WW
+
V
D10
S1B
ISOLATED
WALL
TRANSFORMER
• REQUIRES EXTRA DIODE
• SEE APPS REGARDING POWER PRIORITY
WW
–
OPTION 3: AUXILIARY POWER APPLIED TO LTC4268-1 AND PD LOAD
RJ45
1
+
T1
TX
D3
SMAJ58A
~
~
+
–
–
TVS
+
C14
0.1μF
100V
TX
2
3
+
C1
TO PHY
RX
BR1
BR2
–
RX
V
IN
6
V
PORTP
• 42V ≤ V
≤ 57V
WW
+
–
SPARE
4
5
7
8
• NO POWER PRIORITY ISSUES
• NO LTC4268-1 CURRENT LIMITS FOR V
~
~
+
–
LTC4268-1
WW
SPARE
V
V
PORTN NEG
+
D10
S1B
ISOLATED
WALL
TRANSFORMER
V
WW
–
OPTION 4: AUXILIARY POWER APPLIED TO ISOLATED LOAD
RJ45
1
+
T1
TX
D3
SMAJ58A
TVS
C14
0.1μF
100V
+
C1
~
~
+
–
–
TX
ISOLATED DC/DC CONVERTER
2
3
+
TO PHY
RX
BR1
BR2
–
DRIVE
LOAD
RX
6
V
PORTP
PG
+
–
SPARE
4
5
7
8
~
~
+
–
LTC4268-1
• V
WW
ANY VOLTAGE BASED ON PD LOAD
• SEE APPS REGARDING POWER PRIORITY
• BEST ISOLATION
SHDN GND
SPARE
V
V
PORTN NEG
+
V
ISOLATED
WALL
TRANSFORMER
WW
–
Figure 10. Interfacing Auxiliary Power Source to the PD
42681fa
24
LTC4268-1
APPLICATIONS INFORMATION
is necessary to include diode D9 to prevent the adapter
from applying power to the LTC4268-1. Power priority
issues require more intervention. If the adapter voltage
is below the PSE voltage, then the priority will be given
to the PSE power. The PD will draw power from the PSE
whiletheadapterwillremainunused. Thisconfigurationis
acceptable in a typical PoE system. However, if the adapter
voltage is higher than the PSE voltage, the PD will draw
power from the adapter. In this situation, it is necessary to
address the issue of power cycling that may occur if a PSE
is present. The PSE will detect the PD and apply power. If
the PD is being powered by the adapter, then the PD will
not meet the minimum load requirement and the PSE may
subsequently remove power. The PSE will again detect the
PD and power cycling will start. With an adapter voltage
above the PSE voltage, it is necessary to either disable the
signature as shown in option 2, or install a minimum load
on the output of the LTC4268-1 to prevent power cycling.
same power priority issues as option 2 and the signature
should be disabled or a minimum load should be installed.
Showninoption4isonemethodtodisabletothesignature
while maintaining isolation.
If employing options 1 through 3, it is necessary to ensure
that the end-user cannot access the terminals of the aux-
iliary power jack on the PD since this would compromise
IEEE 802.3af isolation requirements and may violate local
safety codes. Using option 4 along with an isolated power
supply addresses the isolation issue and it is no longer
necessary to protect the end-user from the power jack.
The above power cycling scenarios have assumed the
PSE is using DC disconnect methods. For a PSE using
AC disconnect, a PD with less than minimum load will
continue to be powered.
Walladaptershavebeenknowntogeneratevoltagespikes
outside their expected operating range. Care should be
takentoensurenodamageoccurstotheLTC4268-1orany
support circuitry from extraneous spikes at the auxiliary
power interface.
A 3k, 1W resistor connected between V
will present the required minimum load.
and V
PORTP
NEG
Option 3 applies power directly to the DC/DC converter
bypassing the LTC4268-1 and omitting diode D9. With
the diode omitted, the adapter voltage is applied to the
LTC4268-1 in addition to the DC/DC converter. For this
reason, it is necessary to ensure that the adapter maintain
the voltage between 42V and 57V to keep the LTC4268-1
in its normal operating range. The third option has the
advantageofcorruptingthe25ksignatureresistancewhen
the external voltage exceeds the PSE voltage and thereby
solving the power priority issue.
Classification Resistor Selection (R
)
CLASS
The IEEE 802.3af specification allows classifying PDs into
four distinct classes with class 4 being reserved for future
use (Table 2). The LTC4268-1 supports all IEEE classes
and implements an additional Class 5 for use in custom
PoE applications. An external resistor connected from
R
to V
(Figure 6) sets the value of the load
CLASS
PORTN
current. The designer should determine which class the
PD is to advertise and then select the appropriate value of
Option 4 bypasses the entire PD interface and injects
power at the output of the low voltage power supply. If
the adapter output is below the low voltage output there
are no power priority issues. However, if the adapter is
above the internal supply, then option 4 suffers from the
R
CLASS
from Table 2. If a unique load current is required,
the value of R
can be calculated as:
CLASS
R
CLASS
= 1.237V/(I
– I
)
LOAD
IN_CLASS
42681fa
25
LTC4268-1
APPLICATIONS INFORMATION
IN_CLASS
I
is the LTC4268-1 IC supply current during
on voltages if necessary by connecting the UVLO pin to
an external resistive divider between V and V
classification given in the electrical specifications. The
resistor must be 1% or better to avoid degrading
.
PORTN
PORTP
R
The UVLO pin also includes a bias current allowing imple-
mentation of hysteresis. When UVLO is below 1.24V, gate
drivers are disabled and the converter sits idle. When the
pin rises above the lockout threshold a small current is
sourcedoutoftheUVLOpin,increasingthepinvoltageand
thus creating hysteresis. As the pin voltage drops below
this threshold, the current is disabled, further dropping
the UVLO pin voltage. If not used, the UVLO pin can be
CLASS
the overall accuracy of the classification circuit. Resis-
tor power dissipation will be 100mW maximum and is
transient so heating is typically not a concern. In order
to maintain loop stability, the layout should minimize
capacitance at the R
node. The classification circuit
CLASS
can be disabled by floating the R
pin. The R
pin
CLASS
CLASS
should not be shorted to V
as this would force the
PORTN
LTC4268-1 classification circuit to attempt to source very
large currents. In this case, the LTC4268-1 will quickly go
into thermal shutdown.
disabled by tying to V .
CC
Shutdown Interface
To disable the 25k signature resistor, connect SHDN to
Power Good Interface
the V
pin. Alternately, the SHDN pin can be driven
PORTP
highwithrespecttoV
The LTC4268-1 provides complimentary power good
signals to simplify the DC/DC converter interface. Using
the power good signal to delay converter operation until
the load capacitor is fully charged is recommended as this
will help ensure trouble free start up.
. Examplesofinterfacecircuits
PORTN
that disable the signature and all LTC4268-1 functions are
shown in Figure 10, options 2 and 4. Note that the SHDN
input resistance is relatively large and the threshold volt-
age is fairly low. Because of high voltages present on the
printedcircuitboard,leakagecurrentsfromtheV
pin
PORTP
The active high PWRGD pin is controlled by an open
collector transistor referenced to V
low PWRGD pin is controlled by a high voltage, open-
drain MOSFET referenced to V . The PWRGD pin is
couldinadvertentlypullSHDNhigh.Toensuretrouble-free
while the active
NEG
operation,usehighvoltagelayouttechniquesinthevicinity
of SHDN. If unused, connect SHDN directly to V
.
PORTN
PORTN
designed to interface directly to the UVLO pin with the aid
of a pull-up resistor to Vcc. An example interface circuit
is shown in Figure 11.
Load Capacitor
TheIEEE802.3afspecificationrequiresthatthePDmaintain
a minimum load capacitance of 5μF. It is permissible to
have a much larger load capacitor and the LTC4268-1 can
charge very large load capacitors before thermal issues
become a problem. However, the load capacitor must not
be too large or the PD design may violate IEEE 802.3af
requirements. If the load capacitor is too large, there can
beaproblemwithinadvertentpowershutdownbythePSE.
For example, if the PSE is running at –57V (IEEE 802.3af
maximum allowed) and the PD is detected and powered
up, the load capacitor will be charged to nearly –57V. If
for some reason the PSE voltage is suddenly reduced to
Port Voltage Lockout
PoE applications require the PD interface to turn on below
42V and turn off above 30V. The LTC4268-1 includes an
internalportvoltagelockoutcircuittoimplementthisbasic
chip on/off control. Additionally, the LTC4268-1 includes
an enable/lockout function for the DC/DC converter that is
controlled by the UVLO pin and is intended to be driven by
PWRGD to ensure proper startup. (Refer to Power Good
Interface.) Users have the ability to implement higher turn
42681fa
26
LTC4268-1
APPLICATIONS INFORMATION
–44V (IEEE 802.3af minimum allowed), the input bridge
will reverse bias and the PD power will be supplied by the
load capacitor. Depending on the size of the load capacitor
and the DC load of the PD, the PD will not draw any power
from the PSE for a period of time. If this period of time
exceeds the IEEE 802.3af 300ms disconnect delay, the
PSE will remove power from the PD. For this reason, it
is necessary to evaluate the load current and capacitance
to ensure that inadvertent shutdown cannot occur. Refer
also to Thermal Protection in this data sheet for further
discussion on load capacitor selection.
SWITCHING REGULATOR OVERVIEW
TheLTC4268-1includesacurrentmodeconverterdesigned
specificallyforuseinanisolatedflybacktopologyemploying
synchronous rectification. The LTC4268-1 operation is
similar to traditional current mode switchers. The major
difference is that output voltage feedback is derived via
sensing the output voltage through the transformer. This
precludes the need of an optoisolator in isolated designs
greatly improving dynamic response and reliability. The
LTC4268-1hasauniquefeedbackamplifierthatsamplesa
transformerwindingvoltageduringtheflybackperiodand
uses that voltage to control output voltage. The internal
blocks are similar to many current mode controllers.
The differences lie in the feedback amplifier and load
compensation circuitry. The logic block also contains
circuitry to control the special dynamic requirements of
flyback control. For more information on the basics of
current mode switcher/controllers and isolated flyback
converters see Application Note 19.
MAINTAIN POWER SIGNATURE
In an IEEE 802.3af system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25k in parallel with 0.05μF. If either the DC current
is less than 10mA or the AC impedance is above 26.25k,
the PSE may disconnect power. The DC current must be
less than 5mA and the AC impedance must be above 2M
to guarantee power will be removed. The PD application
circuits shown in this data sheet present the required AC
impedance necessary to maintain power.
Feedback Amplifier—Pseudo DC Theory
ForthefollowingdiscussionrefertothesimplifiedFlyback
Amplifier diagram(Figure 12A). When the primary side
MOSFET switch MP turns off, its drain voltage rises above
the V
rail. Flyback occurs when the primary MOSFET
PORTP
IEEE 802.3at Interoperability
is off and the synchronous secondary MOSFET is on.
Duringflybackthevoltageonnondriventransformerpinsis
determinedbythesecondaryvoltage.Theamplitudeofthis
flyback pulse as seen on the third winding is given as:
In anticipation of the IEEE 802.3at standard release, the
LTC4268-1canbecombinedwithasimpleexternalcircuitto
befullyinteroperablewithanIEEE802.3at-compliantPSE.
For more information, please contact Linear Technology’s
Application Engineering.
VOUT +ISEC • ESR+R
(
)
DS(ON)
VFLBK
=
NSF
ACTIVE-HIGH ENABLE
R
= on resistance of the synchronous MOSFET
DS(ON)
MS
4k
V
PORTP
V
CC
TO
PSE
I
= transformer secondary current
SEC
LTC4268-1
100k
ESR = impedance of secondary circuit capacitor, winding
and traces
PWRGD
–54V
V
UVLO
PORTN
N = transformer effective secondary-to-flyback winding
42681 F11
SF
turns ratio (i.e., N /N
)
S
FLBK
Figure 11. Power Good Interface Example
42681fa
27
LTC4268-1
APPLICATIONS INFORMATION
point. The regulation voltage at the FB pin is nearly equal
The flyback voltage is scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
amplifier compares the voltage to the internal bandgap
reference.Thefeedbackampisactuallyatransconductance
to the bandgap reference V because of the high gain in
FB
the overall loop. The relationship between V
and V
FLBK
FB
is expressed as:
amplifier whose output is connected to V
only during
CMP
R1+R2
VFLBK
=
• VFB
a period in the flyback time. An external capacitor on
the V pin integrates the net feedback amp current to
R2
CMP
provide the control voltage to set the current mode trip
T1
V
FLBK
FLYBACK
LTC4268-1 FEEDBACK AMP
R1
R2
•
•
FB
16
–
V
CMP
1V
17
V
IN
V
FB
C
+
+
C
VC
ISOLATED
OUTPUT
1.237V
–
+
PRIMARY
SECONDARY
OUT
•
MP
COLLAPSE
DETECT
MS
R
S
ENABLE
Q
42681 F12a
Figure 12a. LTC4268-1 Switching Regulator Feedback Amplifier
V
FLBK
0.8 • V
PRIMARY SIDE
MOSFET DRAIN
VOLTAGE
FLBK
V
IN
PG VOLTAGE
SG VOLTAGE
42681 F12b
t
MIN ENABLE
PG DELAY
ON(MIN)
ENABLE
DELAY
FEEDBACK
AMPLIFIER
ENABLED
Figure 12b. LTC4268-1 Switching Regulator Timing Diagram
42681fa
28
LTC4268-1
APPLICATIONS INFORMATION
Combining this with the previous V
expression yields
output voltage. Some time is also required for internal
settling of the feedback amplifier circuitry. In order to
maintain immunity to these phenomena, a fixed delay is
introduced between the switch turn-off command and the
enabling of the feedback amplifier. This is termed “enable
delay.” In certain cases where the leakage spike is not
sufficiently settled by the end of the enable delay period,
regulation error may result. See Applications Information
for further details.
FLBK
an expression for V
in terms of the internal reference,
OUT
programming resistors and secondary resistances:
R1+R2
⎛
⎞
⎠
VOUT
=
• VFB •NSF −I • ESR+R
(
)
⎜
⎝
⎟
SEC
DS(ON)
R2
The effect of nonzero secondary output impedance is
discussedinfurtherdetail;seeLoadCompensationTheory.
The practical aspects of applying this equation for V
are found in the Applications Information.
OUT
Collapse Detect
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
Feedback Amplifier Dynamic Theory
So far, this has been a pseudo-DC treatment of flyback
feedback amplifier operation. But the flyback signal is a
pulse, not a DC level. Provision is made to turn on the
flyback amplifier only when the flyback pulse is present
using the enable signal as shown in the timing diagram
(Figure 12b).
voltage (FB) to a fixed reference, nominally 80% of V .
FB
When the flyback waveform drops below this level, the
feedback amplifier is disabled.
Minimum Enable Time
The feedback amplifier, once enabled, stays on for a fixed
minimum time period termed “minimum enable time.”
This prevents lockup, especially when the output voltage
is abnormally low; e.g., during start-up. The minimum
Minimum Output Switch On Time (t
)
ON(MIN)
The LTC4268-1 affects output voltage regulation via
flyback pulse action. If the output switch is not turned on,
there is no flyback pulse and output voltage information
is not available. This causes irregular loop response and
startup/latch-up problems. The solution is to require the
primary switch to be on for an absolute minimum time per
each oscillator cycle. To accomplish this the current limit
enable time period ensures that the V
node is able to
CMP
“pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is set internally.
feedbackisblankedeachcyclefort
.Iftheoutputload
ON(MIN)
Effects of Variable Enable Period
is less than that developed under these conditions, forced
continuous operation normally occurs. See Applications
Information for further details.
The feedback amplifier is enabled during only a portion of
thecycletime.Thiscanvaryfromthefixedminimumenable
time described to a maximum of roughly the “off” switch
time minus the enable delay time. Certain parameters of
feedbackampbehavioraredirectlyaffectedbythevariable
enable period. These include effective transconductance
Enable Delay Time (ENDLY)
The flyback pulse appears when the primary side switch
shutsoff.However,ittakesafinitetimeuntilthetransformer
primary side voltage waveform represents the output
voltage. This is partly due to rise time on the primary
side MOSFET drain node but, more importantly, is due
to transformer leakage inductance. The latter causes a
voltage spike on the primary side, not directly related to
and V
node slew rate.
CMP
Load Compensation Theory
The LTC4268-1 uses the flyback pulse to obtain
information about the isolated output voltage. An error
42681fa
29
LTC4268-1
APPLICATIONS INFORMATION
source is caused by transformer secondary current flow
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relatively constant. In these cases the external FB resistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function. Figure 13 shows the block diagram of the load
compensation function. Switch current is converted to a
voltagebytheexternalsenseresistor,averagedandlowpass
through the synchronous MOSFET R
and real life
DS(ON)
nonzero impedances of the transformer secondary and
output capacitor. This was represented previously by the
expression“I •(ESR+R
).”However,itisgenerally
DS(ON)
SEC
more useful to convert this expression to effective output
impedance. Because the secondary current only flows
during the off portion of the duty cycle (DC), the effective
outputimpedanceequalsthelumpedsecondaryimpedance
divided by off time DC.
filtered by the internal 50k resistor R
and the external
CMPF
capacitor on C . This voltage is impressed across the
CMP
Since the off time duty cycle is equal to 1 – DC then:
external R
resistor by op amp A1 and transistor Q3
CMP
ESR+RDS(ON)
producingacurrentatthecollectorofQ3thatissubtracted
from the FB node. This effectively increases the voltage
requiredatthetopoftheR1/R2feedbackdividertoachieve
equilibrium.
RS(OUT)
=
1−DC
where:
R
= effective supply output impedance
The average primary side switch current increases to
maintain output voltage regulation as output loading
S(OUT)
DC = duty cycle
increases. TheincreaseinaveragecurrentincreasesR
CMP
R
and ESR are as defined previously
DS(ON)
resistor current which affects a corresponding increase
in sensed output voltage, compensating for the IR drops.
Assuming relatively fixed power supply efficiency, Eff,
power balance gives:
P
V
= Eff • P
IN
OUT
V
T1
FLBK
• I
= Eff • V • I
IN IN
OUT OUT
R1
R2
•
•
Average primary side current is expressed in terms of
output current as follow:
FB
16
Q1 Q2
V
FB
V
PORTP
LOAD
COMP I
IIN =K1•IOUT
where:
•
MP
+
VOUT
R
C
K1=
CMPF
50k
+
Q3
A1
SENSE
20
V •Eff
IN
–
So the effective change in V
target is:
OUT
22
R
21
R
SENSE
RSENSE
RCMP
CMP
CMP
ΔVOUT =K1•
•R1•NSF
42681 F13
thus:
ΔVOUT
ΔIOUT
RSENSE
RCMP
Figure 13. Load Compensation Diagram
=K1•
•R1•NSF
42681fa
30
LTC4268-1
APPLICATIONS INFORMATION
where:
For instance, if we wanted a 48V to 5V converter at 50%
DC then:
K1 = dimensionless variable related to V ,
IN
V
and efficiency as explained above
5 1−0.5
• =
1
9.6
OUT
NDEAL
=
48 0.5
R
= external sense resistor
SENSE
Nominal output impedance cancellation is obtained by
equating this expression with R
In general, better performance is obtained with a lower
turns ratio. A DC of 45.5% yields a 1:8 ratio. Note the
use of the external feedback resistive divider ratio to set
output voltage provides the user additional freedom in
selecting a suitable transformer turns ratio. Turns ratios
that are the simple ratios of small integers; e.g., 1:1, 2:1,
3:2 help facilitate transformer construction and improve
performance. When building a supply with multiple
outputs derived through a multiple winding transformer,
lower duty cycle can improve cross regulation by keeping
the synchronous rectifier on longer, and thus, keep
secondary windings coupled longer. For a multiple output
transformer, the turns ratio between output windings is
critical and affects the accuracy of the voltages. The ratio
:
S(OUT)
ESR+RDS(ON)
1−DC
RSENSE
RCMP
K1•
•R1•NSF =
Solving for R
gives:
CMP
RSENSE • 1−DC
ESR+RDS(ON)
(
)
•R1•NSF
RCMP =K1•
Thepracticalaspectsofapplyingthisequationtodetermine
an appropriate value for the R
Applications Information.
resistor are found in the
CMP
between two output voltages is set with the formula V
OUT2
Transformer Design
= V
• N21 where N21 is the turns ratio between the
OUT1
Transformerdesign/specificationisthemostcriticalpartof
a successful application of the LTC4268-1. The following
sections provide basic information about designing the
transformer and potential tradeoffs. If you need help, the
LTC Applications group is available to assist in the choice
and/or design of the transformer.
two windings. Also keep the secondary MOSFET R
DS(ON)
small to improve cross regulation. The feedback winding
usually provides both the feedback voltage and power for
the LTC4268-1. Set the turns ratio between the output and
feedback winding to provide a rectified voltage that under
worst-case conditions is greater than the 11V maximum
V
turn-off voltage.
CC
Turns Ratios
VOUT
NSF >
The design of the transformer starts with determining
dutycycle(DC). DCimpactsthecurrentandvoltagestress
on the power switches, input and output capacitor RMS
currents and transformer utilization (size vs power). The
ideal turns ratio is:
11+ VF
where:
VF =Diode Forward Voltage
5
1
For our example: NSF >
=
VOUT
1−DC
DC
11+0.7 2.34
NDEAL
=
•
V
1
We will choose
3
IN
Avoid extreme duty cycles as they, in general, increase
current stresses. A reasonable target for duty cycle is
50% at nominal input voltage.
42681fa
31
LTC4268-1
APPLICATIONS INFORMATION
Leakage Inductance
leakage spike is the control point, and the trailing edge of
theleakagespiketriggersthecollapsedetectcircuitry.This
typically reduces the output voltage abruptly to a fraction,
roughly one-third to two-thirds of its correct value. Once
load current is reduced sufficiently, the system snaps
back to normal operation. When using transformers with
considerableleakageinductance,exercisethisworst-case
check for potential bistability:
Transformer leakage inductance (on either the primary or
secondary) causes a spike after the primary side switch
turn-off. This is increasingly prominent at higher load
currents, where more stored energy is dissipated. Higher
flyback voltage may break down the MOSFET switch if it
has too low a BV
rating. One solution to reducing this
DSS
spike is to use a snubber circuit to suppress the voltage
excursion. However, suppressing the voltage extends the
flyback pulse width. If the flyback pulse extends beyond
theenabledelaytime,outputvoltageregulationisaffected.
Thefeedbacksystemhasadeliberatelylimitedinputrange,
roughly 50mVreferredtotheFBnode.Thisrejectshigher
voltage leakage spikes because once a leakage spike is
several volts in amplitude; a further increase in amplitude
has little effect on the feedback system. Therefore, it is
advisable to arrange the snubber circuit to clamp at as
highavoltageaspossible,observingMOSFETbreakdown,
such that leakage spike duration is as short as possible.
ApplicationNote19providesagoodreferenceonsnubber
design.
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
lowvalue,thesystemhasaproblem.Thisisusuallyevident
bysimultaneouslyviewingtheprimarysideMOSFETdrain
voltage to observe firsthand the leakage spike behavior.
A final note—the susceptibility of the system to bistable
behavior is somewhat a function of the load current/
voltage characteristics. A load with resistive—i.e., I = V/R
behavior—is the most apt to be bistable. Capacitive loads
2
As a rough guide, leakage inductance of several percent
(of mutual inductance) or less may require a snubber, but
exhibit little to no regulation error due to leakage spike
behavior. Inductances from several percent up to perhaps
ten percent cause increasing regulation error.
that exhibit I = V /R behavior are less susceptible.
Secondary Leakage Inductance
Leakage inductance on the secondary forms an inductive
divider on the transformer secondary, reducing the size
of the flyback pulse. This increases the output voltage
target by a similar percentage. Note that unlike leakage
spike behavior; this phenomenon is independent of load.
Since the secondary leakage inductance is a constant
percentage of mutual inductance (within manufacturing
variations), the solution is to adjust the feedback resistive
divider ratio to compensate.
Avoid double digit percentage leakage inductances. There
isapotentialforabruptlossofcontrolathighloadcurrent.
Thiscuriousconditionpotentiallyoccurswhentheleakage
spikebecomessuchalargeportionoftheflybackwaveform
that the processing circuitry is fooled into thinking that
the leakage spike itself is the real flyback signal! It then
reverts to a potentially stable state whereby the top of the
42681fa
32
LTC4268-1
APPLICATIONS INFORMATION
Winding Resistance Effects
where:
Primary or secondary winding resistance acts to reduce
overallefficiency(P /P ).Secondarywindingresistance
OUT IN
f
is the oscillator frequency
OSC
increaseseffectiveoutputimpedance,degradingloadregu-
lation.Loadcompensationcanmitigatethistosomeextent
but a good design keeps parasitic resistances low.
DC
is the DC at maximum input voltage
MIN
X
is ripple current ratio at maximum input voltage
MAX
Using common high power PoE values a 48V (41V < V
IN
=
Bifilar Winding
< 57V) to 5V/5.3A Converter with 90% efficiency, P
OUT
A bifilar or similar winding is a good way to minimize
troublesome leakage inductances. Bifilar windings also
improve coupling coefficients and thus improve cross
regulation in multiple winding transformers. However,
tight coupling usually increases primary-to-secondary
capacitance and limits the primary-to-secondary
breakdown voltage, so it isn’t always practical.
26.5W and P = 29.5W Using X = 0.4 N = 1/8 and f
IN
OSC
= 200kHz:
1
1
DCMIN
=
=
= 41.2%
N• V
1 57
IN(MAX)
1+ •
1+
8 5
VOUT
2
57V •0.412
(
)
LP =
= 260μH
Primary Inductance
200kHz •0.4•26.5W
The transformer primary inductance, L , is selected
P
Optimization might show that a more efficient solution
is obtained at higher peak current but lower inductance
and the associated winding series resistance. A simple
spreadsheet program is useful for looking at tradeoffs.
based on the peak-to-peak ripple current ratio (X) in the
transformer relative to its maximum value.
As a general rule, keep X in the range of 20% to 40%
(i.e., X = 0.2 to 0.4). Higher values of ripple will increase
conduction losses, while lower values will require larger
cores.
Transformer Core Selection
OnceL isknown,thetypeoftransformerisselected.High
P
efficiency converters use ferrite cores to minimize core
loss. Actualcorelossisindependentofcoresizeforafixed
inductance, but decreases as inductance increases. Since
increasedinductanceisaccomplishedthroughmoreturns
of wire, copper losses increase. Thus transformer design
balancescoreandcopperlosses.Rememberthatincreased
winding resistance will degrade cross regulation and
increase the amount of load compensation required.
Ripplecurrentandpercentagerippleislargestatminimum
duty cycle; in other words, at the highest input voltage.
P
L is calculated from:
2
V
IN(MAX) •DCMIN
V
IN(MAX) •DCMIN 2 •Eff
(
)
(
)
LP =
=
fOSC •XMAX •P
fOSC •XMAX •POUT
IN
42681fa
33
LTC4268-1
APPLICATIONS INFORMATION
The main design goals for core selection are reducing
copper losses and preventing saturation. Ferrite core
material saturates hard, rapidly reducing inductance
when the peak design current is exceeded. This results
in an abrupt increase in inductor ripple current and,
consequently, output voltage ripple. Do not allow the core
to saturate! The maximum peak primary current occurs
feedback resistors:
⎛
⎜
⎞
⎡
⎣
⎤
⎦
VOUT +ISEC • ESR+R
(
)
DS(ON)
⎟
R1=R2
−1
VFB •NSF
⎜
⎝
⎟
⎠
Continuing the example, if ESR + R
3.32k, then:
= 8mΩ, R2 =
DS(ON)
at minimum V :
IN
5+5.3•0.008
1.237•1/3
⎛
⎞
⎠
P
XMIN
2
⎛
⎞
IN
R1= 3.32k
−1 = 37.28k
IPK =
• 1+
⎜
⎝
⎟
⎜
⎝
⎟
⎠
V
IN(MIN) •DCMAX
now:
choose 37.4k.
1
1
It is recommended that the Thevenin impedance of the
resistive divider (R1||R2) is roughly 3k for bias current
cancellation and other reasons.
DCMAX
=
=
= 49.4%
N• V
1 41
1+ •
8 5
IN MIN
(
)
1+
VOUT
2
2
Current Sense Resistor Considerations
V
IN(MIN) •DCMAX
(
)
41•49.4%
(
)
XMIN
=
=
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistordirectlyaboveanunbrokengroundplaneconnected
with wide and short traces keeps stray resistance and
inductance low.
fOSC •LP •P
200kHz •260μH•29.5W
IN
= 0.267
Using the example numbers leads to:
29.5W
41•0.494
0.267
2
⎛
⎞
IPK =
• 1+
=1.65A
⎜
⎟
⎠
⎝
Multiple Outputs
ThedualsensepinsallowforafullKelvinconnection.Make
sure that SENSE+ and SENSE– are isolated and connect
close to the sense resistor.
One advantage that the flyback topology offers is that
additionaloutputvoltagescanbeobtainedsimplybyadding
windings. Designing a transformer for such a situation is
beyondthescopeofthisdocument.Formultiplewindings,
realize that the flyback winding signal is a combination of
activityonallthesecondarywindings.Thusloadregulation
is affected by each winding’s load. Take care to minimize
cross regulation effects.
Peakcurrentoccursat100mVofsensevoltageV
. So
SENSE
the nominal sense resistor is V /I . For example, a
SENSE PK
peakswitchcurrentof10Arequiresanominalsenseresistor
of 0.010Ω Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
Setting Feedback Resistive Divider
Size R
SENSE
using worst-case conditions, minimum L ,
P
SENSE
TheexpressionforV developedintheOperationsection
OUT
V
and maximum V . Continuing the example, let us
IN
is rearranged to yield the following expression for the
42681fa
34
LTC4268-1
APPLICATIONS INFORMATION
300
200
assumethatourworst-caseconditionsyieldanI of40%
PK
above nominal so I = 2.3A. If there is a 10% tolerance
PK
on R
and minimum V
110% = 88mV/2.3A and nominal R
to the nearest available lower value, 33mΩ.
= 88mV, then R
SENSE
•
SENSE
SENSE
SENSE
= 35mΩ. Round
100
50
Selecting the Load Compensation Resistor
The expression for R
section as:
was derived in the Operation
CMP
30
100
(pF)
200
RSENSE • 1−DC
ESR+RDS(ON)
(
)
•R1•NSF
C
OSC
RCMP =K1•
42681 F02
Figure 14. fOSC vs OSC Capacitor Values
Continuing the example:
2. Temporarily ground the C
pin to disable the load
CMP
⎛
⎞
VOUT
5
compensation function. Measure output voltage while
K1=
DC=
=
= 0.116
⎜
⎟
V •Eff
48•90%
⎝
⎠
sweeping output current over the expected range.
Approximate the voltage variation as a straight line.
IN
1
N•V
1
=
= 45.5%
1 48
1+ •
8 5
ΔV /ΔI
= R
.
IN(NOM)
OUT OUT
S(OUT)
1+
VOUT
3. Calculate a value for the K1 constant based on V , V
and the measured efficiency.
IN OUT
If ESR+RDS(ON) = 8mΩ
4. Compute:
33mΩ• 1−0.455
(
)
1
3
RCMP = 0.116•
= 3.25k
•37.4kΩ•
8mΩ
RSENSE
RS(OUT)
RCMP =K1•
•R1•NSF
This value for R
is a good starting point, but empirical
CMP
5. Verify this result by connecting a resistor of this value
from the R pin to ground.
methodsarerequiredforproducingthebestresults.Thisis
becauseseveraloftherequiredinputvariablesaredifficult
to estimate precisely. For instance, the ESR term above
includesthatofthetransformersecondary,butitseffective
ESRvaluedependsonhighfrequencybehavior,notsimply
DC winding resistance. Similarly, K1 appears as a simple
CMP
6.DisconnectthegroundshorttoC
andconnecta0.1μF
CMP
filter capacitor to ground. Measure the output impedance
= ΔV /ΔI with the new compensation in
R
S(OUT)
OUT OUT
place. R
should have decreased significantly. Fine
S(OUT)
ratio of V to V
times efficiency, but theoretically
IN
OUT
tuning is accomplished experimentally by slightly altering
estimating efficiency is not a simple calculation.
R
CMP
. A revised estimate for R
is:
CMP
RS(OUT)CMP
RS(OUT)
The suggested empirical method is as follows:
⎛
⎞
R′CMP =RCMP • 1+
1. Build a prototype of the desired supply including the
actual secondary components.
⎜
⎟
⎝
⎠
42681fa
35
LTC4268-1
APPLICATIONS INFORMATION
Minimum Output Switch On Time (t
)
where R′
is the new value for the load compensation
ON(MIN)
CMP
resistor. R
is the output impedance with R
S(OUT)CMP
CMP
Minimumontimeistheprogrammableperiodduringwhich
current limit is blanked (ignored) after the turn on of the
primarysideswitch.Thisimprovesregulatorperformance
by eliminating false tripping on the leading edge spike in
the switch, especially at light loads. This spike is due to
boththegate/sourcechargingcurrentandthedischargeof
drain capacitance. The isolated flyback sensing requires a
pulse to sense the output. Minimum on time ensures that
the output switch is always on a minimum time and that
there is always a signal to close the loop. The LTC4268-1
does not employ cycle skipping at light loads. Therefore,
minimumontimealongwithsynchronousrectificationsets
the switch over to forced continuous mode operation.
in place and R
compensation (from step 2).
is the output impedance with no load
S(OUT)
Setting Frequency
The switching frequency of the LTC4268-1 is set by an
external capacitor connected between the OSC pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz.Figure14showsthenominalrelationshipbetween
external capacitance and switching frequency. Place the
capacitor as close as possible to the IC and minimize OSC
trace length and area to minimize stray capacitance and
potential noise pickup.
The t
resistor is set with the following equation
ON(MIN)
You can synchronize the oscillator frequency to an
external frequency. This is done with a signal on the SYNC
pin. Set the LTC4268-1 frequency 10% slower than the
desired external frequency using the OSC pin capacitor,
then use a pulse on the SYNC pin of amplitude greater
than 2V and with the desired frequency. The rising edge
of the SYNC signal initiates an OSC capacitor discharge
forcing primary MOSFET off (PG voltage goes low). If
the oscillator frequency is much different from the sync
frequency, problems may occur with slope compensation
and system stability. Keep the sync pulse width greater
than 500ns.
tON(MIN) ns −104
( )
RtON(MIN) kΩ =
(
)
1.063
Keep R
greater than 70k. A good starting value
tON(MIN)
is 160k.
Enable Delay Time (ENDLY)
Enable delay time provides a programmable delay between
turn-off of the primary gate drive node and the subsequent
enabling of the feedback amplifier. As discussed earlier, this
delay allows the feedback amplifier to ignore the leakage
inductancevoltagespikeontheprimaryside.Theworst-case
leakage spike pulse width is at maximum load conditions.
So set the enable delay time at these conditions.
Selecting Timing Resistors
There are three internal “one-shot” times that are
programmed by external application resistors: minimum
on time, enable delay time and primary MOSFET turn-on
delay. These are all part of the isolated flyback control
technique, and their functions are previously outlined in
theTheoryofOperationsection.Thefollowinginformation
should help in selecting and/or optimizing these timing
values.
While the typical applications for this part use forced
continuous operation, it is conceivable that a secondary
side controller might cause discontinuous operation at
light loads. Under such conditions the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
42681fa
36
LTC4268-1
APPLICATIONS INFORMATION
theactualsecondaryoutputvoltage.Theenabledelaytime
should be made long enough to ignore the “irrelevant”
portion of the flyback waveform at light loads.
spike in the transformer. This spike will cause additional
component stress and a loss in regulator efficiency.
The primary gate delay resistor is set with the following
equation:
EventhoughtheLTC4268-1hasarobustgatedrive,thegate
transition time slows with very large MOSFETs. Increase
delay time as required when using such MOSFETs.
tPGDLY ns +47
( )
RPGDLY kΩ =
(
)
9.01
The enable delay resistor is set with the following
equation:
A good starting point is 27k.
tENDLY ns −30
( )
Soft Start Function
RENDLY kΩ =
(
)
2.616
TheLTC4268-1containsanoptionalsoft-startfunctionthat
isenabledbyconnectinganexternalcapacitorbetweenthe
SFSTpinandground.Internalcircuitrypreventsthecontrol
Keep R
56k.
greater than 40k. A good starting point is
ENDLY
voltage at the V
pin from exceeding that on the SFST
CMP
Primary Gate Delay Time (PGDLY)
pin. There is an initial pull-up circuit to quickly bring the
SFST voltage to approximately 0.8V. From there it charges
to approximately 2.8V with a 20μA current source.
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of
the primary side MOSFET. Correct setting eliminates
overlap between the primary side switch and secondary
side synchronous switch(es) and the subsequent current
The SFST node is discharged to 0.8V when a fault occurs.
AfaultoccurswhenV istoolow(undervoltagelockout),
CC
current sense voltage is greater than 200mV or the IC’s
thermal (over temperature) shutdown is tripped. When
SFST discharges, the V
node voltage is also pulled low
CMP
V
IN
to below the minimum current voltage. Once discharged
and the fault removed, the SFST charges up again. In this
manner, switch currents are reduced and the stresses in
the converter are reduced during fault conditions.
R
TR
•
•
V
IN
+
C
TR
I
VCC
•
The time it takes to fully charge soft-start is:
V
CC
LTC4268-1 PG
GND
C
SFST •1.4V
20μA
tss =
= 70kΩ•CSFST μF
( )
Converter Start-Up
V
THRESHOLD
ON
V
I
VCC
The standard topology for the LTC4268-1 utilizes a third
transformer winding on the primary side that provides
both feedback information and local V power for the
VCC
0
CC
V
PG
LTC4268-1 (see Figure 15). This power “bootstrapping”
improves converter efficiency but is not inherently self-
starting.Start-upisaffectedwithanexternal“tricklecharge”
42681 F15
Figure 15. Typical Power Bootstrapping
resistor and the LTC4268-1’s internal V undervoltage
CC
lockout circuit. The V undervoltage lockout has wide
CC
hysteresis to facilitate start-up.
42681fa
37
LTC4268-1
APPLICATIONS INFORMATION
V
Make C large enough to avoid the relaxation oscillatory
CMP
TR
17
behavior described above. This is complicated to deter-
mine theoretically as it depends on the particulars of the
secondary circuit and load behavior. Empirical testing is
recommended. Note that the use of the optional soft-start
function lengthens the power-up timing and requires a
C
R
VCMP
VCMP2
C
VCMP
42681 F16
Figure 16. VCMP Compensation Network
correspondingly larger value for C .
TR
Inoperation, the“tricklecharge”resistorR isconnected
TR
The LTC4268-1 has an internal clamp on V of approxi-
CC
to V and supplies a small current, typically on the order
IN
mately 20V. This provides some protection for the part
of 1mA to charge C . Initially the LTC4268-1 is off and
TR
in the event that the switcher is off (UVLO low) and the
draws only its start-up current. When C reaches the V
TR
CC
V
node is pulled high. If R is sized correctly the part
CC TR
should never attain this clamp voltage.
turn-onthresholdvoltagetheLTC4268-1turnsonabruptly
and draws its normal supply current.
Control Loop Compensation
Switching action commences and the converter begins to
deliver power to the output. Initially the output voltage is
Loop frequency compensation is performed by connect-
ing a capacitor network from the output of the feedback
low and the flyback voltage is also low, so C supplies
TR
most of the LTC4268-1 current (only a fraction comes
amplifier (V
pin) to ground as shown in Figure 16.
CMP
from R .) V voltage continues to drop until after some
Becauseofthesamplingbehaviorofthefeedbackamplifier,
TR
CC
time, typically tens of milliseconds, the output voltage
compensation is different from traditional current mode
controllers. Normally only C
approaches its desired value. The flyback winding then
is required. R
can
VCMP
VCMP
providestheLTC4268-1supplycurrentandtheV voltage
beusedtoadda“zero”butthephasemarginimprovement
traditionallyofferedbythisextraresistorisusuallyalready
accomplishedbythenonzerosecondarycircuitimpedance.
CC
stabilizes.
IfC isundersized,V reachestheV turn-offthreshold
TR
CC
CC
C
can be used to add an additional high frequency
VCMP2
before stabilization and the LTC4268-1 turns off. The V
CC
pole and is usually sized at 0.1 times C
.
VCMP
node then begins to charge back up via R to the turn-on
TR
threshold, where the part again turns on. Depending upon
the circuit, this may result in either several on-off cycles
beforeproperoperationisreached,orpermanentrelaxation
In further contrast to traditional current mode switchers,
pinrippleisgenerallynotanissuewiththeLTC4268-1.
V
CMP
The dynamic nature of the clamped feedback amplifier
oscillation at the V node.
forms an effective track/hold type response, whereby the
CC
V
voltage changes during the flyback pulse, but is then
CMP
R
is selected to yield a worst-case minimum charging
TR
“held” during the subsequent “switch on” portion of the
next cycle. This action naturally holds the V voltage
currentgreaterthanthemaximumratedLTC4268-1start-up
current, andaworst-casemaximumchargingcurrentless
than the minimum rated LTC4268-1 supply current.
CMP
stableduringthecurrentcomparatorsenseaction(current
mode switching).
V
IN(MIN) − VCC(ON_MAX)
Application Note 19 provides a method for empirically
tweaking frequency compensation. Basically it involves
introducing a load current step and monitoring the
response.
RTR(MAX)
and
RTR(MIN)
<
ICC(ST _MAX)
VIN(MAX) − VCC(ON_MIN)
>
ICC(MIN)
42681fa
38
LTC4268-1
APPLICATIONS INFORMATION
Slope Compensation
Short-Circuit Conditions
TheLTC4268-1incorporatescurrentslopecompensation.
Slope compensation is required to ensure current loop
stabilitywhentheDCisgreaterthan50%.Insomeswitching
regulators,slopecompensationreducesthemaximumpeak
current at higher duty cycles. The LTC4268-1 eliminates
this problem by having circuitry that compensates for
the slope compensation so that maximum current sense
voltage is constant across all duty cycles.
Loss of current limit is possible under certain conditions
such as an output short circuit. If the duty cycle exhibited
by the minimum on time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is
ISC • RSEC +RDS(ON)
(
)
Minimum Load Considerations
DCMIN = tON(MIN) • fOSC
<
V •NSP
At light loads, the LTC4268-1 derived regulator goes into
forced continuous conduction mode. The primary side
switch always turns on for a short time as set by the
IN
where:
t
t
resistor. If this produces more power than the
is the primary side switch minimum on time
is the short-circuit output current
ON(MIN)
ON(MIN)
loadrequires, powerwillflowbackintotheprimaryduring
the “off” period when the synchronization switch is on.
This does not produce any inherently adverse problems,
although light load efficiency is reduced.
I
SC
N
N
is the secondary-to-primary turns ratio (N
)
(Other variables as previously defined)
/
SEC
SP
PRI
Maximum Load Considerations
Trouble is typically encountered only in applications with a
relatively high product of input voltage times secondary to
primaryturnsratioand/orarelativelylongminimumswitch
on time. Additionally, several real world effects such as
transformer leakage inductance, AC winding losses, and
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
design evaluates the switcher for short-circuit protection
and adds any additional circuitry to prevent destruction
for these losses.
The current mode control uses the V
and amplified sense resistor voltage as inputs to the
current comparator. When the amplified sense voltage
node voltage
CMP
exceeds the V
is turned off.
node voltage, the primary side switch
CMP
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
V
reaches its 2.56V clamp. At clamp, the primary side
CMP
MOSFET will turn off at the rated 100mV V
level. This
SENSE
repeatsonthenextcycle.Itispossibleforthepeakprimary
switch currents as referred across R to exceed the
Output Voltage Error Sources
SENSE
The LTC4268-1’s feedback sensing introduces additional
minor sources of errors. The following is a summary
list.
max 100mV rating because of the minimum switch on
time blanking. If the voltage on V exceeds 205mV
SENSE
after the minimum turn-on time, the SFST capacitor is
discharged, causing the discharge of the V capacitor.
CMP
• Theinternalbandgapvoltagereferencesetsthereference
voltage for the feedback amplifier. The specifications
detail its variation.
This then reduces the peak current on the next cycle and
will reduce overall stress in the primary switch.
42681fa
39
LTC4268-1
APPLICATIONS INFORMATION
For the primary-side power MOSFET, the peak current
is:
MILLER EFFECT
V
GS
P
XMIN
2
⎛
⎞
a
b
IN
IPK(PRI)
=
• 1+
⎜
⎝
⎟
⎠
42681 F17
Q
Q
B
A
V
IN(MIN) •DCMAX
GATE CHARGE (Q )
G
whereX ispeak-to-peakcurrentratioasdefinedearlier.
Figure 17. Gate Charge Curve
MIN
For each secondary-side power MOSFET, the peak current
• The external feedback resistive divider ratio directly
affects regulated voltage. Use 1% components.
• Leakage inductance on the transformer secondary
reduces the effective secondary-to-feedback winding
turns ratio (NS/NF) from its ideal value. This increases
the output voltage target by a similar percentage. Since
secondary leakage inductance is constant from part to
part (within a tolerance) adjust the feedback resistor
ratio to compensate.
is:
IOUT
1−DCMAX
XMIN
2
⎛
⎞
IPK(SEC)
=
• 1+
⎜
⎝
⎟
⎠
Selectaprimary-sidepowerMOSFETwithaBV
than:
greater
DSS
VOUT(MAX)
LLKG
CP
BVDSS ≥IPK
+ V
+
IN(MAX)
NSP
• The transformer secondary current flows through the
impedances of the winding resistance, synchronous
where N reflects the turns ratio of that secondary-to
SP
MOSFET R
and output capacitor ESR. The DC
DS(ON)
primary winding. L
is the primary-side leakage induc-
LKG
equivalent current for these errors is higher than the
load current because conduction occurs only during
the converter’s “off” time. So divide the load current
by (1 – DC).
tanceandC istheprimary-sidecapacitance(mostlyfrom
P
the drain capacitance (C ) of the primary-side power
OSS
MOSFET). A snubber may be added to reduce the leakage
inductance as discussed.
Iftheoutputloadcurrentisrelativelyconstant,thefeedback
resistive divider is used to compensate for these losses.
Otherwise,usetheLTC4268-1loadcompensationcircuitry.
(See Load Compensation.) If multiple output windings are
used, theflybackwindingwillhaveasignalthatrepresents
an amalgamation of all these windings impedances. Take
carethatyouexamineworst-caseloadingconditionswhen
tweaking the voltages.
Foreachsecondary-sidepowerMOSFET,theBV should
DSS
be greater than:
BV
≥ V
+ V
• N
DSS
OUT
IN(MAX) SP
Choose the primary side MOSFET R
at the nominal
DS(ON)
gate drive voltage (7.5V). The secondary side MOSFET
gate drive voltage depends on the gate drive method.
Primary side power MOSFET RMS current is given by:
Power MOSFET Selection
P
IN
ThepowerMOSFETsareselectedprimarilyonthecriteriaof
IRMS(PRI)
=
V
DCMAX
“on”resistanceR
,inputcapacitance,drain-to-source
DSS
IN(MIN)
DS(ON)
breakdown voltage (BV ), maximum gate voltage (V )
GS
and maximum drain current (ID
).
(MAX)
42681fa
40
LTC4268-1
APPLICATIONS INFORMATION
For each secondary-side power MOSFET RMS current is
given by:
(1 + δ) is generally given for a MOSFET in the form of a
normalizedR
vstemperaturecurve.Ifyoudon’thavea
DS(ON)
curve, use δ = 0.005/°C • ΔT for low voltage MOSFETs.
IOUT
1−DCMAX
IRMS(SEC)
=
The secondary-side power MOSFETs typically operate
at substantially lower V , so you can neglect transition
DS
losses. The dissipation is calculated using:
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high V , a
2
DS
P
= I
• R
(1 + δ)
DIS(SEC)
RMS(SEC)
DS(ON)
transitionpowerlosstermisincludedforaccuracy.C
MILLER
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
is the most critical parameter in determining the transition
loss, but is not directly specified on the data sheets.
T = T + P • θ
JA
J
A
DIS
C
is calculated from the gate charge curve included
MILLER
on most MOSFET data sheets (Figure 17).
whereT istheambienttemperatureandθ istheMOSFET
A
JA
junction to ambient thermal resistance.
The flat portion of the curve is the result of the Miller (gate
to-drain)capacitanceasthedrainvoltagedrops.TheMiller
capacitance is computed as:
Once you have T iterate your calculations recomputing
J
δ and power dissipations until convergence.
QB −QA
CMILLER
=
Gate Drive Node Consideration
VDS
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves efficiency
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The curve is done for a given V . The Miller capacitance
DS
for different V voltages are estimated by multiplying the
DS
MILLER
the curve specified V .
computed C
by the ratio of the application V to
DS
DS
WithC
determined,calculatetheprimary-sidepower
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and poorer efficiency.
MILLER
MOSFET power dissipation:
PD(PRI) =IRMS(PRI)2 •RDS(ON) 1+δ +
(
)
P
CMILLER
V
•
IN(MAX) •RDR
DCMIN
•
• fOSC
IN(MAX)
TheLTC4268-1gatedriveswillclampthemaxgatevoltage
to roughly 7.5V, so you can safely use MOSFETs with
VGATE(MAX) − VTH
maximum V of 10V and larger.
where:
GS
R
is the gate driver resistance (≈10Ω)
is the MOSFET gate threshold voltage
is the operating frequency
DR
Synchronous Gate Drive
V
TH
There are several different ways to drive the synchronous
gateMOSFET.Fullconverterisolationrequiresthesynchro-
nousgatedrivetobeisolated.Thisisusuallyaccomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary as shown in the
application on the front page of this data sheet.
f
OSC
V
= 7.5V for this part
GATE(MAX)
42681fa
41
LTC4268-1
APPLICATIONS INFORMATION
L1
0.1μH
V
OUT
I
PRI
PRIMARY
CURRENT
FROM
SECONDARY
WINDING
+
+
C1
C
C
OUT
OUT2
R
47μF
LOAD
470μF
1μF
s3
42681 F19
Figure 19.
SECONDARY
CURRENT
I
PRI
N
Keepinputcapacitorseriesresistance(ESR)andinductance
(ESL) small, as they affect electromagnetic interference
suppression. In some instances, high ESR can also
produce stability problems because flyback converters
exhibit a negative input resistance characteristic. Refer
to Application Note 19 for more information. The output
capacitorissizedtohandletheripplecurrentandtoensure
acceptable output voltage ripple.
RINGING
ΔV
COUT
DUE TO ESL
OUTPUT VOLTAGE
RIPPLE WAVEFORM
ΔV
ESR
42681 F18
Figure 18. Typical Flyback Converter Waveforms
However,otherschemesarepossible.Therearegatedrivers
and secondary side synchronous controllers available
that provide the buffer function as well as additional
features.
The output capacitor should have an RMS current rating
greater than:
DCMAX
IRMS(SEC) =IOUT
1−DCMAX
Capacitor Selection
In a flyback converter, the input and output current flows
in pulses, placing severe demands on the input and output
filter capacitors. The input and output filter capacitors
are selected based on RMS current ratings and ripple
voltage.
Continuing the example:
49.4%
1−49.4%
IRMS(SEC) = 5.3A
= 5.24A
This is calculated for each output in a multiple winding
application.
Select an input capacitor with a ripple current rating
greater than:
ESRandESLalongwithbulkcapacitancedirectlyaffectthe
output voltage ripple. The waveforms for a typical flyback
converter are illustrated in Figure 18.
P
1−DCMAX
DCMAX
IN
IRMS(PRI)
=
V
IN(MIN)
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose
of simplicity we will choose 2% for the maximum output
Continuing the example:
29.5W 1−49.4%
IRMS(PRI)
=
= 0.728A
41V
49.4%
42681fa
42
LTC4268-1
APPLICATIONS INFORMATION
ripple, divided equally between the ESR step and the
charging/discharging ΔV. This percentage ripple changes,
depending on the requirements of the application. You
can modify the equations below. For a 1% contribution
to the total ripple voltage, the ESR of the output capacitor
is determined by:
The design of the filter is beyond the scope of this data
sheet. However, as a starting point, use these general
guidelines. Start with a C
1/4 the size of the nonfilter
OUT
solution. Make C1 1/4 of C
to make the second filter
OUT
pole independent of C . C1 may be best implemented
OUT
with multiple ceramic capacitors. Make L1 smaller than
the output inductance of the transformer. In general, a
0.1μH filter inductor is sufficient. Add a small ceramic
VOUT • 1−DC
(
)
MAX
ESRCOUT ≤1%•
IOUT
capacitor (C
) for high frequency noise on V . For
OUT2
OUT
those interested in more details refer to “Second-Stage
LC Filter Design,” Ridley, Switching Power Magazine, July
2000 p8-10.
The other 1% is due to the bulk C component, so use:
IOUT
1%• VOUT • fOSC
COUT
≥
Circuit simulation is a way to optimize output capacitance
and filters, just make sure to include the component
parasitic. LTC SwitcherCADTM is a terrific free circuit
simulation tool that is available at www.linear.com. Final
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
significantly impact ripple. Refer to the PC Board Layout
section for more details.
In many applications the output capacitor is created from
multiple capacitors to achieve desired voltage ripple,
reliability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfies the required bulk C.
Continuing our example, the output capacitor needs:
5V • 1−49.4%
(
)
= 4mΩ
ELECTRO STATIC DISCHARGE AND SURGE
PROTECTION
ESRCOUT ≤1%•
5.3A
1%•5•200kHz
5.3A
= 600μF
The LTC4268-1 is specified to operate with an absolute
maximum voltage of –90V and is designed to tolerate
brief over-voltage events. However, the pins that interface
COUT
≥
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
to the outside world (primarily V
and V
)
PORTN
PORTP
can routinely see peak voltages in excess of 10kV. To
protect the LTC4268-1, it is highly recommended that the
SMAJ58Aunidirectional58Vtransientvoltagesuppressor
be installed between the diode bridge and the LTC4268-1
(D3 in Figure 4).
Most capacitor ripple current ratings are based on 2000
hour life. This makes it advisable to derate the capacitor
or to choose a capacitor rated at a higher temperature
than required.
One way to reduce cost and improve output ripple is to
use a simple LC filter. Figure 19 shows an example of the
filter.
42681fa
43
LTC4268-1
APPLICATIONS INFORMATION
ISOLATION
In order to minimize switching noise and improve output
load regulation, connect the GND pin of the LTC4268-1
The802.3standardrequiresEthernetportstobeelectrically
isolatedfromallotherconductorsthatareuseraccessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
common methods to meet the isolation requirement. If
there will be any user accessible connection to the PD,
then an isolated DC/DC converter is necessary to meet
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electricalconnectionstotheLTC4268-1orsupportcircuitry
other than the RJ-45 port.
directly to the ground terminal of the V decoupling
CC
capacitor,thebottomterminalofthecurrentsenseresistor
and the ground terminal of the input capacitor, using a
ground plane with multiple vias. Place the V capacitor
CC
immediately adjacent to the V and GND pins on the IC
CC
package. This capacitor carries high di/dt MOSFET gate
drive currents. Use a low ESR ceramic capacitor. Take care
inPCBlayouttokeepthetracesthatconducthighswitching
currents short, wide and with minimal overall loop area.
Thesearetypicallythetracesassociatedwiththeswitches.
This reduces the parasitic inductance and also minimizes
magneticfieldradiation.Figure20outlinesthecriticalpaths.
Keep electric field radiation low by minimizing the length
andareaoftraces(keepstraycapacitanceslow). Thedrain
of the primary side MOSFET is the worst offender in this
category. Always use a ground plane under the switcher
circuitry to prevent coupling between PCB planes. Check
LAYOUT CONSIDERATIONS FOR THE LTC4268-1
The LTC4268-1’s PD front end is relatively immune to
layout problems. Excessive parasitic capacitance on the
that the maximum BV
ratings of the MOSFETs are not
R
CLASS
pin should be avoided. Include a PCB heat sink
DSS
exceeded due to inductive ringing. This is done by viewing
the MOSFET node voltages with an oscilloscope. If it is
breaking down either choose a higher voltage device, add
a snubber or specify an avalanche-rated MOSFET.
to which the exposed pad on the bottom of the package
can be soldered. This heatsink should be electrically
connected to GND. For optimum thermal performance,
make the heat sink as large as possible. Voltages in a
PD can be as large as –57V for PoE applications, so
high voltage layout techniques should be employed. The
SHDN pin should be separated from other high voltage
Place the small-signal components away from high
frequency switching nodes. This allows the use of a
pseudo-Kelvinconnectionforthesignalground,wherehigh
di/dt gate driver currents flow out of the IC ground pin in
pins, like V
, V , to avoid the possibility of leakage
PORTP OUT
shutting down the LTC4268-1. If not used, tie SHDN to
one direction (to the bottom plate of the V decoupling
CC
V
V
.TheloadcapacitorconnectedbetweenV
and
PORTN
PORTP
capacitor) and small-signal currents flow in the other
direction. Keep the trace from the feedback divider tap
to the FB pin short to preclude inadvertent pickup. For
applications with multiple switching power converters
connected to the same input supply, make sure that the
input filter capacitor for the LTC4268-1 is not shared with
other converters. AC input current from another converter
could cause substantial input voltage ripple and this could
interferewiththeLTC4268-1operation. AfewinchesofPC
of the LTC4268-1 can store significant energy when
OUT
fully charged. The design of a PD must ensure that this
energy is not inadvertently dissipated in the LTC4268-1.
Thepolarity-protectiondiodespreventanaccidentalshort
on the cable from causing damage. However if, V
is shorted to V
PORTN
inside the PD while capacitor C1
PORTP
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4268-1.
traceorwire(L≅100nH)betweentheC oftheLTC4268-1
IN
and the actual source V is sufficient to prevent current
IN
sharing problems.
42681fa
44
LTC4268-1
APPLICATIONS INFORMATION
T1
•
•
V
CC
V
IN
C
VCC
GATE
TURN-ON
V
CC
•
+
+
PG
C
MP
VIN
GATE
TURN-OFF
OUT
R
SENSE
+
V
C
CC
OUT
GATE
C
R
TURN-ON
Q4
Q3
V
CC
T2
SG
MS
•
•
GATE
TURN-OFF
42681 F20
Figure 20. Layout Critical High Current Paths
42681fa
45
LTC4268-1
TYPICAL APPLICATION
42681fa
46
LTC4268-1
PACKAGE DESCRIPTION
DKD Package
32-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1734 Rev Ø)
0.70 0.05
4.50 0.05
6.43 0.05
2.65 0.05
3.10 0.05
PACKAGE
OUTLINE
0.23 0.05
0.40 BSC
6.00 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
7.00 0.10
17
32
R = 0.05
TYP
6.43 0.10
2.65 0.10
4.00 0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
16
1
0.20 0.05
0.40 BSC
0.75 0.05
6.00 REF
(DKD32) QFN 1106 REV Ø
BOTTOM VIEW—EXPOSED PAD
0.200 REF
NOTE:
0.00 – 0.05
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
42681fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
47
LTC4268-1
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT®1952
Single Switch Synchronous Forward Counter
Current Mode Flyback DC/DC Controller in ThinSOTTM
Synchronous Controller, Programmable Volt-Sec Clamp, Low Start Current
LTC3803-3
300kHz Constant Frequency, Adjustable Slope Compensation, Optimized
for High Input Voltage Applications
LTC3805
LTC3825
Adjustable Frequency Current Mode Flyback Controller Slope Comp Overcurrent Protect, Internal/External Clock
Isolate No-Opto Synchronous Flyback Controller with
Wide Input Supply Range
Adjustable Switching Frequency, Programmable Undervoltage Lockout,
Accurate Regulation without Trim, Synchronous for High Efficiency
LTC4257-1
LTC4258
IEEE 802.3af PD Interface Controller
100V 400mA Internal Switch, Programmable Classification Dual
Current Limit
Quad IEEE 802.3af Power over Ethernet Controller
Quad IEEE 802.3af Power over Ethernet Controller
Single IEEE 802.3af Power over Ethernet Controller
High Power Single PSE Controller
DC Disconnect Only, IEEE-Compliant PD Detection and Classification,
2
Autonomous Operation or I C Control
LTC4259A-1
LTC4263
AC or DC Disconnect IEEE-Compliant PD Detection and Classification,
2
Autonomous Operation or I C Control
AC or DC Disconnect IEEE-Compliant PD Detection and Classification,
2
Autonomous Operation or I C Control
LTC4263-1
LTC4264
Internal Switch, Autonomous Operation, 30W
High Power PD Interface Controller with 750mA
Current Limit
750mA Internal Switch, Programmable Classification Current to 75mA.
Precision Dual Current Limit with Disable.
LTC4267
IEEE 802.3af PD Interface with an Integrated Switching 100V 400mA Internal Switch, Programmable Classification, 200kHz
Regulator
Constant Frequency PWM, Interface and Switcher Optimized for IEEE-
Compliant PD System
LTC4267-3
IEEE 802.3af PD Interface with an Integrated Switching 100V 400mA Internal Switch, Programmable Classification, 300kHz
Regulator
Constant Frequency PWM, Interface and Switcher Optimized for IEEE-
Compliant PD System
ThinSOT are trademarks of Linear Technology Corporation.
42681fa
LT 0108 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
48
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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