LTC4269IDKD-1-PBF [Linear]
IEEE 802.3at PD with Synchronous No-Opto Flyback Controller; IEEE 802.3at标准的PD与同步无光电反激式控制器
| 型号： | LTC4269IDKD-1-PBF |
| 厂家： | 
Linear |
| 描述： | IEEE 802.3at PD with Synchronous No-Opto Flyback Controller |
| 文件： | 总44页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4269-1
IEEE 802.3at PD with
Synchronous No-Opto
Flyback Controller
FEATURES
DESCRIPTION
The LTC®4269-1 is an integrated Powered Device (PD)
controller and switching regulator intended for high
power IEEE 802.3at and 802.3af applications. The
LTC4269-1 is targeted for high efficiency, single and
multioutput applications from 10W to 25W. By support-
ing both 1-event and 2-event classifications, as defined
by the IEEE, the LTC4269-1 can be used in a wide range
of product configurations.
n
25.5W IEEE 802.3at Compliant (Type 2) PD
n
Integrated State-of-the-Art Synchronous Flyback
Controller
– Isolated Power Supply Efficiency >92%
– 88% Efficiency Including Diode Bridge and
Hot Swap™ FET
n
Flexible Integrated Auxiliary Power Support
n
Superior EMI Performance
n
Robust 100V 0.7Ω (Typ) Integrated Hot Swap MOSFET
The LTC4269-1 synchronous, current mode, flyback con-
trollergeneratesmultiplesupplyrailsinasingleconversion
stepprovidingforthehighestsystemefficiencywhilemain-
taining tight regulation across all outputs. The LTC4269-1
includes Linear Technology’s patented No-Opto feedback
topology to provide full IEEE 802.3 isolation without the
need of an opto-isolator circuit. A true soft-start function
allows graceful ramp-up of all output voltages.
n
IEEE 802.3at High Power Available Indicator
n
Integrated Signature Resistor and Programmable
Class Current
n
Undervoltage, Overvoltage and Thermal Protection
n
Short-Circuit Protection with Auto-Restart
n
Programmable Soft-Start and Switching Frequency
n
Complementary Power Good Indicators
n
Thermally Enhanced 7mm × 4mm DFN Package
All Linear Technology PD solutions include a shutdown
pin to provide flexible auxiliary power options. The
LTC4269-1 can accommodate adaptor voltages from 18V
to 60V and supports both PoE or aux dominance options.
The LTC4269-1 is available in a space saving 32-pin DFN
package.
APPLICATIONS
n
VoIP Phones with Advanced Display Options
n
Dual-Radio Wireless Access Points
n
PTZ Security Cameras
RFID Readers
Industrial Controls
n
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents, including
5841643.
n
TYPICAL APPLICATION
25W High Efficiency PD Solution
•
•
0.18μH
47μF
5V
5A
10μH
V
IN
39k
+
+
100μF
•
2.2μF
10μF
383k
14k
27.4k
10μF
~ +
~ –
54V FROM
DATA PAIR
TO MICRO
CONTROLLER
3.01k
+
–
FB
V
PG SENSE
PWRGD UVLO
T2P
CC
~ +
~ –
54V FROM
SPARE PAIR
V
PORTP
33mΩ
10nF
R
CLASS
SENSE
30.9ꢀ
LTC4269-1
0.1μF
SHDN
PORTN
SG
CMP
2.2nF
V
V
1μF
V
SYNC GND OSC PGDLY
t
ENDLY
100k
R
CMP
C
NEG
ON
CMP
•
•
12k
38.3k 1.21k
33pF
0.1μF
42691 TA01a
42691fb
1
LTC4269-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Pins with Respect to V
PORTN
SHDN
1
2
32 V
PORTP
V
V
V
Voltage......................................... –0.3V to 100V
PORTP
T2P
31 NC
Voltage......................................... –0.3V to V
NEG
NEG
PORTP
R
3
30 PWRGD
29 PWRGD
28 NC
CLASS
NC
Pull-Up Current ..................................................1A
SHDN....................................................... –0.3V to 100V
4
V
V
5
PORTN
R
R
, Voltage............................................ –0.3V to 7V
Source Current...........................................50mA
CLASS
CLASS
6
27
26
V
V
PORTN
NC
NEG
NEG
7
PWRGD Voltage (Note 3)
NC
SG
8
25 NC
33
Low Impedance Source ......V
–0.3V to V
+11V
NEG
NEG
9
24 PG
Sink Current.........................................................5mA
PWRGD, T2P Voltage............................... –0.3V to 100V
PWRGD, T2P Sink Current.....................................10mA
Pins with Respect to GND
V
10
11
23 PGDLY
CC
ON
t
22
21
R
CMP
CMP
ENDLY 12
SYNC 13
SFST 14
OSC 15
FB 16
C
+
20 SENSE
19 SENSE
18 UVLO
–
V
(Note 3)
CC
Low Impedance Source ....................... –0.3V to +18V
Sink Current.......................................................30mA
SENSE , SENSE Voltage........................ –0.5V to +0.5V
UVLO, SYNC Voltage...................................–0.3V to V
FB Current.............................................................. 2mA
17
V
CMP
–
+
DKD32 PACKAGE
32-LEAD (7mm × 4mm) PLASTIC DFN
CC
T
= 125°C, θ = 34°C/W, θ = 2°C/W
JA JC
JMAX
GND, EXPOSED PAD (PIN 33) MUST BE SOLDERED TO A
HEAT SINKING PLANE THAT IS CONNECTED TO V
V
Current ......................................................... 1mA
NEG
CMP
Operating Ambient Temperature Range
LTC4269C-1 ................................................. 0°C to 70°C
LTC4269I-1 ..............................................–40°C to 85°C
ORDER INFORMATION
LEAD FREE FINISH
LTC4269CDKD-1#PBF
LTC4269IDKD-1#PBF
TAPE AND REEL
LTC4269CDKD-1#TRPBF 42691
LTC4269IDKD-1#TRPBF 42691
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
32-Lead (7mm × 4mm) Plastic DFN
32-Lead (7mm × 4mm) Plastic DFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
42691fb
2
LTC4269-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Interface Controller (Note 4)
Operating Input Voltage
Signature Range
Classification Range
ON Voltage
At V
(Note 5)
60
9.8
21
V
V
V
V
V
V
PORTP
l
l
l
l
1.5
12.5
37.2
OFF Voltage
30.0
Overvoltage Lockout
71
l
l
l
ON/OFF Hysteresis Window
Signature/Class Hysteresis Window
Reset Threshold
4.1
1.4
V
V
V
State Machine Reset for 2-Event Classification
2.57
5.40
Supply Current
l
l
Supply Current at 57V
Class 0 Current
Measured at V
Pin
1.35
0.40
mA
mA
PORTP
V
= 17.5V, No R
Resistor
CLASS
PORTP
Signature
l
l
l
Signature Resistance
Invalid Signature Resistance, SHDN Invoked
1.5V ≤ V
1.5V ≤ V
≤ 9.8V (Note 6)
23.25
26
11
11
kꢀ
kꢀ
kꢀ
PORTP
≤ 9.8V, V
= 3V (Note 6)
PORTP
SHDN
Invalid Signature Resistance During Mark Event (Notes 6, 7)
Classification
l
l
Class Accuracy
10mA < I
< 40mA, 12.5V < V
< 21V
PORTP
3.5
1
%
CLASS
(Notes 8, 9)
Classification Stability Time
V
Pin Step to 17.5V, R
= 30.9, I Within
CLASS
ms
PORTP
CLASS
3.5% of Ideal Value (Notes 8, 9)
Normal Operation
l
l
l
Inrush Current
V
= 54V, V
= 3V
NEG
60
100
0.7
180
1.0
1
mA
ꢀ
PORTP
Power FET On-Resistance
Power FET Leakage Current at V
Digital Interface
Tested at 600mA into V , V
= 54V
NEG PORTP
V
= SHDN = V = 57V
NEG
μA
NEG
PORTP
l
l
l
l
SHDN Input High Level Voltage
SHDN Input Low Level Voltage
SHDN Input Resistance
3
V
V
0.45
0.15
V
= 9.8V, SHDN = 9.65V
= 54V. For T2P, Must Complete
100
kꢀ
V
PORTP
PWRGD, T2P Output Low Voltage
Tested at 1mA, V
2-Event Classification to See Active Low
PORTP
l
l
PWRGD, T2P Leakage Current
Pin Voltage Pulled 57V, V = V
= 0V
PORTN
1
μA
V
PORTP
PWRGD Output Low Voltage
Tested at 0.5mA, V
= 52V, V
= 48V, Output
0.4
PORTP
NEG
Voltage Is with Respect to V
NEG
l
l
PWRGD Clamp Voltage
PWRGD Leakage Current
Tested at 2mA, V
= 0V, Voltage with Respect to V
12
16.5
1
V
NEG
NEG
V
= 11V, V
= 0V, Voltage with Respect to V
μA
PWRGD
NEG
NEG
42691fb
3
LTC4269-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PWM Controller (Note 10)
Power Supply
l
●
●
●
●
●
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
Turn-On Voltage, V
Turn-Off Voltage, V
Hysteresis
14
8
15.3
9.7
16
11
V
V
CC(ON)
CC(OFF)
V
V
V
V
– V
4
5.6
6.5
V
CC(ON)
CC(OFF)
Shunt Clamp
= 0V, I
= 15mA
VCC
19.5
4
20.5
6.4
V
UVLO
CMP
Supply Current (I
Start-Up Current
)
= Open (Note 11)
10
mA
μA
CC
= 10V
180
400
CC
Feedback Amplifier
Feedback Regulation Voltage (V
●
)
FB
1.220
1.237
200
1.251
V
nA
Feedback Pin Input Bias Current
R
CMP
Open
●
●
Feedback Amplifier Transconductance
Feedback Amplifier Source or Sink Current
Feedback Amplifier Clamp Voltage
ΔI = 10μA
700
25
1000
55
1400
90
μmho
μA
C
V
FB
V
FB
= 0.9V
= 1.4V
2.56
0.84
V
V
●
Reference Voltage Line Regulation
Feedback Amplifier Voltage Gain
Soft-Start Charging Current
12V ≤ V ≤ 18V
0.005
1400
20
0.02
25
%/V
V/V
μA
CC
V
CMP
V
SFST
V
SFST
= 1.2V to 1.7V
= 1.5V
16
Soft-Start Discharge Current
= 1.5V, V
= 0V
0.8
1.3
mA
V
UVLO
Control Pin Threshold (V
)
Duty Cycle = Min
1
CMP
Gate Outputs
●
●
●
PG, SG Output High Level
PG, SG Output Low Level
6.6
7.4
0.01
1.6
11
8
V
V
0.05
2.3
PG, SG Output Shutdown Strength
PG Rise Time
V
C
C
C
= 0V; I , I = 20mA
V
UVLO
PG SG
= 1nF
ns
ns
ns
PG
SG
SG Rise Time
= 1nF
15
PG, SG Fall Time
, C = 1nF
PG SG
10
Current Amplifier
+
●
●
●
Switch Current Limit at Maximum V
V
V
C
88
98
110
230
mV
V/V
mV
CMP
SENSE
ΔV
/ΔV
0.07
206
SENSE
CMP
+
Sense Voltage Overcurrent Fault Voltage
, V
< 1V
SFST
SENSE
Timing
Switching Frequency (f
)
= 100pF
OSC
84
33
100
110
200
kHz
pF
ns
ns
ns
%
OSC
Oscillator Capacitor Value (C
Minimum Switch On Time (t
)
(Note 12)
OSC
)
200
265
200
88
ON(MIN)
Flyback Enable Delay Time (t
)
ENDLY
PG Turn-On Delay Time (t
)
PGDLY
●
●
Maximum Switch Duty Cycle
SYNC Pin Threshold
85
1.53
40
2.1
V
SYNC Pin Input Resistance
kꢀ
42691fb
4
LTC4269-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Load Compensation
Load Compensation to V
+
Offset Voltage
V
V
with V = 0V
SENSE
+
1
mV
μA
SENSE
RCMP
Feedback Pin Load Compensation Current
= 20mV, V = 1.230V
20
SENSE
FB
UVLO Function
●
UVLO Pin Threshold (V
)
1.215
1.240
1.265
V
UVLO
UVLO Pin Bias Current
V
UVLO
V
UVLO
= 1.2V
= 1.3V
–0.25
–4.50
0
–3.4
0.25
–2.50
μA
μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: An invalid signature after the 1st classification event is mandated
by the IEEE802.3at standard. See the Applications Information section.
Note 8: Class accuracy is with respect to the ideal current defined as
1.237/R
and does not include variations in R
resistance.
CLASS
CLASS
Note 2: Pins with 100V absolute maximum guaranteed for T ≥ 0°C,
otherwise 90V.
Note 3: Active high PWRGD internal clamp self-regulates to 14V with
Note 9: This parameter is assured by design and wafer level testing.
–
Note 10: V = 14V; PG, SG Open; V
= 1.5V, V
= 0V, R
= 1k,
CC
CMP
SENSE
CMP
R
= 90k, R
= 27.4k, R
= 90k, unless otherwise specified. All
tON
PGDLY
ENDLY
respect to V . V has internal 19.5V clamp with respect to GND.
NEG CC
voltages are with respect to GND.
Note 4: All voltages are with respect to V
pin unless otherwise noted.
PORTN
Note 11: Supply current does not include gate charge current to the
Note 5: Input voltage specifications are defined with respect to LTC4269-1
pins and meet IEEE 802.3af/at specifications when the input diode bridge
is included.
MOSFETs. See the Applications Information section.
Note 12: Component value range guaranteed by design.
Note 6: Signature resistance is measured via the ΔV/ΔI method with the
minimum ΔV of 1V. The LTC4269-1 signature resistance accounts for the
additional series resistance in the input diode bridge.
42691fb
5
LTC4269-1
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Input Voltage
25k Detection Range
Input Current vs Input Voltage
Input Current vs Input Voltage
50
40
30
20
0.5
0.4
0.3
0.2
11.0
10.5
T
= 25°C
CLASS 1 OPERATION
T
= 25°C
A
A
CLASS 4
CLASS 3
CLASS 2
CLASS 1
CLASS 0
85°C
–40°C
10.0
9.5
10
0
0.1
0
0
20
30
40
50
60
10
0
4
6
8
10
2
12
14
16
18
20
22
V
VOLTAGE (V)
V
VOLTAGE (V)
V
VOLTAGE (V)
PORTP
PORTP
PORTP
(RISING)
42691 G01
42691 G03
42691 G02
Signature Resistance
vs Input Voltage
Class Operation vs Time
On-Resistance vs Temperature
28
27
$V V2 – V1
RESISTANCE =
DIODES: HD01
=
T
= 25°C
V
A
PORTP
$I
I – I
2 1
VOLTAGE
10V/DIV
1.0
0.8
0.6
0.4
0.2
T
= 25°C
A
IEEE UPPER LIMIT
LTC4269-1 + 2 DIODES
26
25
24
CLASS
CURRENT
10mA/DIV
LTC4269-1 ONLY
IEEE LOWER LIMIT
23
22
42691 G05
TIME (10μs/DIV)
–50
0
25
50
75
100
–25
V1:
V2:
1
2
3
4
5
6
7
8
9
10
JUNCTION TEMPERATURE (°C)
V
VOLTAGE (V)
PORTP
42691 G04
42691 G06
PWRGD, T2P Output Low Voltage
Active High PWRGD
vs Current
Output Low Voltage vs Current
Inrush Current vs Input Voltage
1.0
0.8
0.6
0.4
0.2
0
0.8
115
110
105
T
= 25°C
T
= 25°C
PORTP
A
A
V
– V
= 4V
NEG
0.6
0.4
0.2
0
100
95
90
85
0
2
4
6
8
10
1
2
0
0.5
1.5
40
45
50
55
60
CURRENT (mA)
V
VOLTAGE (V)
CURRENT (mA)
PORTP
42691 G07
42691 G08
42691 G09
42691fb
6
LTC4269-1
TYPICAL PERFORMANCE CHARACTERISTICS
VCC(ON) and VCC(OFF)
vs Temperature
VCC Start-Up Current
vs Temperature
V
CC Current vs Temperature
10
9
16
15
14
13
12
11
10
9
300
250
200
150
V
CC(ON)
DYNAMIC CURRENT C = 1nF,
PG
C
SG
= 1nF, f
= 100kHz
OSC
8
7
6
STATIC PART CURRENT
= 14V
100
50
0
V
CC(OFF)
5
4
V
CC
3
8
–25
0
50
75 100 125
50
TEMPERATURE (°C)
100 125
–50
25
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
TEMPERATURE (°C)
42691 G10
42691 G12
42691 G11
SENSE Fault Voltage
vs Temperature
Oscillator Frequency
vs Temperature
SENSE Voltage vs Temperature
110
108
106
104
102
100
98
110
108
106
104
102
100
98
220
215
210
205
200
195
190
185
180
+
FB = 1.1V
+
SENSE = V
WITH V
C
= 100pF
OSC
SENSE
SENSE
–
SENSE = V
SENSE
= 0V
–
WITH V
= 0V
SENSE
96
96
94
94
92
92
90
90
–50
0
25
50
75 100 125
50
TEMPERATURE (°C)
125
–25
–50 –25
0
25
50
75 100 125
–50
0
25
75 100
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
42691 G13
42691 G14
42691 G15
Feedback Pin Input Bias
vs Temperature
VFB vs Temperature
VFB Reset vs Temperature
1.240
1.239
1.238
1.237
1.236
1.235
1.234
1.233
1.232
1.231
1.230
300
250
200
150
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
R
CMP
OPEN
100
50
0
–50
0
25
50
75 100 125
–25
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–25
0
50
75 100 125
–50
25
TEMPERATURE (°C)
TEMPERATURE (°C)
42691 G16
42691 G17
42691 G18
42691fb
7
LTC4269-1
TYPICAL PERFORMANCE CHARACTERISTICS
Feedback Amplifier Output
Current vs VFB
Feedback Amplifier Source and
Sink Current vs Temperature
Feedback Amplifier gm
vs Temperature
70
50
70
65
60
55
1100
1050
1000
950
SOURCE CURRENT
125°C
V
FB
= 1.1V
25°C
–40°C
SINK
30
CURRENT
V
= 1.4V
FB
10
–10
–30
–50
–70
50
45
40
900
0.9
1
1.1
1.2
(V)
1.3
1.4
1.5
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
V
FB
42691 G19
42691 G20
42691 G21
Feedback Amplifier Voltage Gain
vs Temperature
UVLO vs Temperature
IUVLO Hysteresis vs Temperature
1700
1650
1600
1550
1500
1450
1400
1350
1300
1250
1200
1150
1100
1.250
1.245
1.240
1.235
3.7
3.6
3.5
3.4
3.3
3.2
3.1
1.230
1.225
1.220
3.0
–25
0
50
75 100 125
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50
25
–50 –25
0
25
75
–50 –25
0
25
75
TEMPERATURE (°C)
42691 G22
42691 G23
42691 G24
PG, SG Rise and Fall Times
vs Load Capacitance
Soft-Start Charge Current
vs Temperature
VCC Clamp Voltage
vs Temperature
80
70
60
50
40
30
20
10
0
21.5
21.0
20.5
20.0
19.5
19.0
23
22
21
20
19
18
17
16
15
T
= 25°C
I
CC
= 10mA
A
FALL TIME
RISE TIME
–25
0
50
75 100 125
0
1
2
3
4
5
6
7
8
9
10
–50
25
50
TEMPERATURE (°C)
125
–50 –25
0
25
75 100
CAPACITANCE (nF)
TEMPERATURE (°C)
42691 G26
42691 G25
42691 G27
42691fb
8
LTC4269-1
TYPICAL PERFORMANCE CHARACTERISTICS
Enable Delay Time
vs Temperature
Minimum PG On-Time
vs Temperature
PG Delay Time vs Temperature
340
330
320
310
300
290
280
270
260
325
305
285
265
300
250
R
= 158k
R
ENDLY
= 90k
tON(MIN)
R
R
= 27.4k
= 16.9k
PGDLY
PGDLY
200
150
100
245
225
205
50
0
–25
0
50
75 100 125
50
TEMPERATURE (°C)
100 125
–50
25
–50 –25
0
25
75
–50 –25
0
25
75
50
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
42691 G28
42691 G30
42691 G29
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary
power application. Drive SHDN high to disable LTC4269-1
operation and corrupt the signature resistance. If unused,
increases significantly during turn-on causing a benign
relaxation oscillation action on the VCC pin if the part does
not start normally.
tie SHDN to V
.
PORTN
t
(Pin 11): Pin for external programming resistor to
ON
T2P(Pin2):Type2PSEIndicator,Open-Drain.Lowimped-
ance indicates the presence of a Type 2 PSE.
set the minimum time that the primary switch is on for
each cycle. Minimum turn-on facilitates the isolated feed-
back method. See the Applications Information section
for details.
R
(Pin 3): Class Select Input. Connect a resistor
CLASS
between R
and V
to set the classification load
CLASS
PORTN
current (see Table 2).
ENDLY (Pin 12): Pin for external programming resistor to
set enable delay time. The enable delay time disables the
feedback amplifier for a fixed time after the turn-off of the
primary-side MOSFET. This allows the leakage inductance
voltage spike to be ignored for flyback voltage sensing.
See the Applications Information section for details.
NC (Pins 4, 7, 8, 25, 28, 31): No Connect.
V
(Pins 5, 6): Input Voltage, Negative Rail. Pin 5 and
PORTN
Pin 6 must be electrically tied together at the package.
SG (Pin 9): Synchronous Gate Drive Output. This pin
provides an output signal for a secondary-side synchro-
nous rectifier. Large dynamic currents may flow during
voltage transitions. See the Applications Information
section for details.
SYNC (Pin 13): External Sync Input. This pin is used to
synchronize the internal oscillator with an external clock.
The positive edge of the clock causes the oscillator to
dischargecausingPGtogolow(off)andSGhigh(on).The
sync threshold is typically 1.5V. Tie to ground if unused.
See the Applications Information section for details.
VCC (Pin 10): Supply Voltage Pin. Bypass this pin to
GND with a 4.7μF, or more, capacitor. This pin has a 19.5V
clamp to ground. VCC has an undervoltage lockout func-
tion that turns the part on when VCC is approximately
15.3V and off at 9.7V. In a conventional trickle-charge
bootstrapped configuration, the VCC supply current
SFST (Pin 14): Soft-Start. This pin, in conjunction with a
capacitor (C
) to GND, controls the ramp-up of peak
SFST
primary current through the sense resistor. It is also used
to control converter inrush at start-up. The SFST clamps
42691fb
9
LTC4269-1
PIN FUNCTIONS
the V
voltage and thus limits peak current until soft-
current is used in the converter control loop. Make Kelvin
CMP
start is complete. The ramp time is approximately 70ms
per μF of capacitance. Leave SFST open if not using the
soft-start function.
connections to the sense resistor R
to reduce noise
SENSE
–
problems.SENSE connectstotheGNDside.Atmaximum
current (V
at its maximum voltage) SENSE pins have
CMP
100mV threshold. The signal is blanked (ignored) during
OSC (Pin 15): Oscillator. This pin, in conjunction with an
the minimum turn-on time.
external capacitor (C ) to GND, defines the controller
OSC
C
(Pin 21): Load Compensation Capacitive Control.
oscillator frequency. The frequency is approximately
CMP
Connect a capacitor from C
to GND in order to reduce
100kHz • 100/C
(pF).
CMP
OSC
the effects of parasitic resistances in the feedback sensing
path. A 0.1μF ceramic capacitor suffices for most applica-
tions. Short this pin to GND when load compensation is
not needed.
FB(Pin16):FeedbackAmplifierInput. Feedbackisusually
sensed via a third winding and enabled during the flyback
period.Thispinalsosinksadditionalcurrenttocompensate
for load current variation as set by the R
pin. Keep the
CMP
R
(Pin 22): Load Compensation Resistive Control.
Thevenin equivalent resistance of the feedback divider at
roughly 3k.
CMP
Connect a resistor from R
to GND in order to com-
CMP
pensate for parasitic resistances in the feedback sensing
path. In less demanding applications, this resistor is not
needed and this pin can be left open. See the Applications
Information section for details.
V
(Pin 17): Frequency Compensation Control. V
CMP
CMP
is used for frequency compensation of the switcher con-
trol loop. It is the output of the feedback amplifier and
the input to the current comparator. Switcher frequency
compensation components are placed on this pin to GND.
The voltage on this pin is proportional to the peak primary
switch current. The feedback amplifier output is enabled
during the synchronous switch on time.
PGDLY (Pin 23): Primary Gate Delay Control. Connect an
external programming resistor (R
) to set delay from
PGDLY
synchronous gate turn-off to primary gate turn-on. See
the Applications Information section for details.
PG (Pin 24): Primary Gate Drive. PG is the gate drive pin
for the primary-side MOSFET switch. Large dynamic cur-
rents flow during voltage transitions. See the Applications
Information section for details.
UVLO (Pin 18): Undervoltage Lockout. A resistive divider
fromV
tothispinsetsanundervoltagelockoutbased
PORTP
upon V
level (not V ). When the UVLO pin is below
PORTP
CC
its threshold, the gate drives are disabled, but the part
draws its normal quiescent current from V . The V
V
(Pins 26, 27): System Negative Rail. Connects V
NEG
CC
CC
CC
NEG
undervoltage lockout supersedes this function, so V
to V
through an internal power MOSFET. Pin 26 and
PORTN
must be great enough to start the part.
Pin 27 must be electrically tied together at the package.
The bias current on this pin has hysteresis such that the
biascurrentissourcedwhenUVLOthresholdisexceeded.
Thisintroducesahysteresisatthepinequivalenttothebias
current change times the impedance of the upper divider
resistor. The user can control the amount of hysteresis
by adjusting the impedance of the divider. Tie the UVLO
PWRGD (Pin 29): Power Good Output, Open-Collector.
High impedence signals power-up completion. PWRGD
is referenced to V
and features a 14V clamp.
NEG
PWRGD (Pin 30): Complementary Power Good Output,
Open-Drain.Lowimpedancesignalspower-upcompletion.
PWRGD is referenced to V
.
PORTN
pin to V if not using this function. See the Applications
CC
V
(Pin 32): Positive Power Input. Tie to the input
Information section for details. This pin is used for the
UVLOfunctionoftheswitchingregulator. ThePDinterface
section has an internal UVLO.
PORTP
port power through the input diode bridge.
Exposed Pad (Pin 33): Ground. This is the negative rail
connectionforbothsignalgroundandgatedrivergrounds
of the flyback controller. This pin should be connected to
–
+
SENSE , SENSE (Pins 19, 20): Current Sense Inputs.
These pins are used to measure primary-side switch cur-
rent through an external sense resistor. Peak primary-side
V
.
NEG
42691fb
10
LTC4269-1
BLOCK DIAGRAM
CLASSIFICATION
CURRENT LOAD
V
SHDN
1
PORTP
NC
32
31
30
1.237V
+
–
16k 25k
T2P
2
R
CLASS
3
PWRGD
PWRGD
CONTROL
CIRCUITS
4
5
NC
29
V
V
PORTN
PORTN
14V
V
NEG
6
7
27
26
V
NEG
BOLD LINE INDICATES
HIGH CURRENT PATH
NC
NC
8
V
CC
CLAMPS
10
V
CC
UVLO
20V
0.7
1.3
+
–
+
FB
16
17
ERROR AMP
–
+
–
1.237V
REFERENCE
(V
V
15.3V
CMP
3V
)
FB
INTERNAL
REGULATOR
S
R
Q
Q
COLLAPSE DETECT
–
–
+
+
–
UVLO
+
UVLO
SFST
1V
18
14
19
CURRENT
COMPARATOR
OVERCURRENT
FAULT
I
UVLO
–
+
–
TSD
–
SENSE
CURRENT
SENSE AMP
+
CURRENT TRIP
+
SENSE
SLOPE COMPENSATION
ENABLE
20
21
R
CMPF
50k
OSC
15
OSCILLATOR
C
CMP
SET
+
–
SYNC
13
11
23
12
LOAD
COMPENSATION
t
ON
LOGIC
BLOCK
R
CMP
PG
PGDLY
ENDLY
TO FB
22
24
V
CC
GATE DRIVE
PGATE
SGATE
+
NC
NC
25
28
3V
–
V
CC
GATE DRIVE
SG
9
GND
33
(EXPOSED PAD)
42691 BD
42691fb
11
LTC4269-1
APPLICATIONS INFORMATION
OVERVIEW
50
40
30
20
10
Power over Ethernet (PoE) continues to gain popularity
as more products are taking advantage of having DC
power and high speed data available from a single RJ45
connector. As PoE continues to grow in the marketplace,
Powered Device (PD) equipment vendors are running into
the 12.95W power limit established by the IEEE 802.3af
standard.
ON
OFF
CLASSIFICATION
DETECTION V2
TIME
DETECTION V1
50
40
30
20
10
dV
dt
INRUSH
C1
=
The IEE802.3at standard establishes a higher power
allocation for Power over Ethernet while maintaining
backwards compatibility with the existing IEEE 802.3af
systems. Power sourcing equipment (PSE) and powered
devices are distinguished as Type 1 complying with the
IEEE 802.3af/IEEE 802.3at power levels, or Type 2 com-
plying with the IEEE 802.3at power levels. The maximum
available power of a Type 2 PD is 25.5W.
OFF
ON
OFF
T = R
C1
LOAD
TIME
TIME
–10
–20
–30
–40
–50
POWER
BAD
POWER
BAD
POWER
GOOD
PWRGD
PWRGD
TRACKS
TRACKS
V
V
PORTP
PORTP
The IEEE 802.3at standard also establishes a new method
ofacquiringpowerclassificationfromaPDandcommuni-
cating the presence of a Type 2 PSE. A Type 2 PSE has the
option of acquiring PD power classification by performing
2-event classification (layer 1) or by communicating with
the PD over the data line (layer 2). In turn, a Type 2 PD
must be able to recognize both layers of communications
and identify a Type 2 PSE.
PWRGD TRACKS
V
PORTN
20
10
POWER
BAD
POWER
GOOD
POWER
BAD
IN DETECTION
RANGE
TIME
LOAD, I
LOAD
The LTC4269-1 is specifically designed to support the
front end of a PD that must operate under the IEEE 802.3at
standard. In particular, the LTC4269-1 provides the T2P
indicator bit which recognizes 2-event classification.
This indicator bit may be used to alert the LTC4269-1
output load that a Type 2 PSE is present. With an internal
signature resistor, classification circuitry, inrush control,
and thermal shutdown, the LTC4269-1 is a complete PD
Interface solution capable of supporting in the next gen-
eration PD applications.
INRUSH
CLASSIFICATION
TIME
DETECTION I
2
DETECTION I
V1 – 2 DIODE DROPS
1
V2 – 2 DIODE DROPS
25kΩ
SELECTION
CLASS
I
I
=
I
=
1
2
25kΩ
DEPENDENT ON R
CLASS
INRUSH = 100mA
V
R
PORTP
I
=
LOAD
LOAD
MODES OF OPERATION
LTC4269-1
R
I
LOAD
IN
R
V
PORTP
CLASS
The LTC4269-1 has several modes of operation depend-
ing on the input voltage applied between the V
PSE
R
PWRGD
C1
CLASS
and
PORTP
PWRGD
V
pins. Figure 1 presents an illustration of voltage
V
V
NEG
PORTN
PORTN
42691 F01
andcurrentwaveformstheLTC4269-1mayencounterwith
the various modes of operation summarized in Table 1.
Figure 1. VNEG, PWRGD, PWRGD and PD
Current as a Function of Input Voltage
42691fb
12
LTC4269-1
APPLICATIONS INFORMATION
Table 1. LTC4269-1 Modes of Operation as a Function
of Input Voltage
The input diode bridge introduces a voltage drop that
affects the range for each mode of operation. The
LTC4269-1 compensates for these voltage drops so that a
PD built with the LTC4269-1 meets the IEEE 802.3af/IEEE
802.3at-established voltage ranges. Note the Electrical
Characteristics are referenced with respect to the
LTC4269- 1 package pins.
V
–V
(V) LTC4269-1 MODES OF OPERATION
PORTP PORTN
0V to 1.4V
Inactive (Reset After 1st Classification Event)
1.5V to 9.8V
(5.4V to 9.8V)
25k Signature Resistor Detection Before 1st
Classification Event (Mark, 11k Signature
Corrupt After 1st Classification Event)
12.5V to ON/OFF*
ON/OFF* to 60V
>71V
Classification Load Current Active
Inrush and Power Applied To PD Load
DETECTION
Overvoltage Lockout,
Classification and Hot Swap Are Disabled
During detection, the PSE looks for a 25k signature resis-
tor which identifies the device as a PD. The PSE will apply
two voltages in the range of 2.8V to 10V and measures
the corresponding currents. Figure 1 shows the detection
voltagesV1andV2andthecorrespondingPDcurrent.The
PSE calculates the signature resistance using the ΔV/ΔI
measurement technique.
*ON/OFF includes hysteresis. Rising input threshold, 37.2V Max.
Falling input threshold, 30V Min.
These modes satisfy the requirements defined in the
IEEE 802.3af/IEEE 802.3at specification.
INPUT DIODE BRIDGE
The LTC4269-1 presents its precision, temperature-com-
In the IEEE 802.3af/IEEE 802.3at standard, the modes of
operation reference the input voltage at the PD’s RJ45
connector. Since the PD must handle power received in
either polarity from either the data or the spare pair, input
diode bridges BR1 and BR2 are connected between the
RJ45 connector and the LTC4269-1 (Figure 2).
pensated 25k resistor between the V
and V
PORTP
PORTN
pins, alerting the PSE that a PD is present and requests
power to be applied. The LTC4269-1 signature resistor
also compensates for the additional series resistance
introduced by the input diode bridge. Thus a PD built
with the LTC4269-1 conforms to the IEEE 802.3af/IEEE
802.3at specifications.
RJ45
+
1
T1
TX
BR1
–
TX
2
3
+
TO PHY
RX
–
RX
POWERED
DEVICE
(PD)
6
V
PORTP
+
SPARE
INPUT
BR2
4
5
LTC4269-1
0.1μF
100V
D3
V
PORTN
7
8
42691 F02
–
SPARE
Figure 2. PD Front End Using Diode Bridges on Main and Spare Inputs
42691fb
13
LTC4269-1
APPLICATIONS INFORMATION
SIGNATURE CORRUPT OPTION
Table 2. Summary of Power Classifications and LTC4269-1
RCLASS Resistor Selection
In some designs that include an auxiliary power option,
it is necessary to prevent a PD from being detected by a
PSE.TheLTC4269-1signatureresistancecanbecorrupted
with the SHDN pin (Figure 3). Taking the SHDN pin high
will reduce the signature resistor below 11k which is an
invalid signature per the IEEE 802.3af/IEEE 802.3at speci-
fication, and alerts the PSE not to apply power. Invoking
the SHDN pin also ceases operation for classification and
disconnects the LTC4269-1 load from the PD input. If this
CLASS
USAGE
MAXIMUM
NOMINAL
LTC4269-1
POWER LEVELS CLASSIFICATION
R
CLASS
AT INPUT OF PD LOAD CURRENT RESISTOR
(W)
(mA)
< 0.4
10.5
18.5
28
(Ω, 1%)
Open
124
0
1
2
3
4
Type 1
Type 1
Type 1
Type 1
Type 2
0.44 to 12.95
0.44 to 3.84
3.84 to 6.49
6.49 to 12.95
12.95 to 25.5
69.8
45.3
40
30.9
feature is not used, connect SHDN to V
.
PORTN
2-EVENT CLASSIFICATION AND THE T2P PIN
A Type 2 PSE may declare the availability of high power
by performing a 2-event classification (layer 1) or by
communicating over the high speed data line (layer 2). A
Type 2 PD must recognize both layers of communication.
Since layer 2 communication takes place directly between
the PSE and the LTC4269-1 load, the LTC4269-1 concerns
itself only with recognizing 2-event classification.
LTC4269-1
V
PORTP
25k SIGNATURE
RESISTOR
TO
PSE
16k
SHDN
V
PORTN
42691 F03
SIGNATURE DISABLE
In 2-event classification, a Type 2 PSE probes for power
classification twice. Figure 4 presents an example of a
2-event classification. The 1st classification event occurs
when the PSE presents an input voltage between 15.5V
to 20.5V and the LTC4269-1 presents a class 4 load cur-
rent. The PSE then drops the input voltage into the mark
voltage range of 7V to 10V, signaling the 1st mark event.
The PD in the mark voltage range presents a load current
between 0.25mA to 4mA.
Figure 3. 25k Signature Resistor with Disable
CLASSIFICATION
Classification provides a method for more efficient power
allocation by allowing the PSE to identify a PD power clas-
sification. Class 0 is included in the IEEE specification for
PDsthatdonotsupportclassification. Class1-3partitions
PDs into three distinct power ranges. Class 4 includes the
new power range under IEEE802.3at (see Table 2).
The PSE repeats this sequence, signaling the 2nd Clas-
sification and 2nd mark event occurrence. This alerts the
LTC4269-1 that a Type 2 PSE is present. The Type 2 PSE
then applies power to the PD and the LTC4269-1 charges
up the reservoir capacitor C1 with a controlled inrush cur-
rent.WhenC1isfullycharged,andtheLTC4269-1declares
power good, the T2P pin presents an active low signal, or
During classification probing, the PSE presents a fixed
voltage between 15.5V and 20.5V to the PD (Figure 1).
The LTC4269-1 asserts a load current representing the
PD power classification. The classification load current
low impedance output with respect to V
. The T2P
PORTN
outputbecomesinactivewhentheLTC4269-1inputvoltage
falls below undervoltage lockout threshold.
is programmed with a resistor R
from Table 2.
that is chosen
CLASS
42691fb
14
LTC4269-1
APPLICATIONS INFORMATION
SIGNATURE CORRUPT DURING MARK
50
As a member of the IEEE 802.3at working group, Linear
Technology noted that it is possible for a Type 2 PD to
receiveafalseindicationofa2-eventclassificationifaPSE
portispre-chargedtoavoltageabovethedetectionvoltage
range before the first detection cycle. The IEEE working
group modified the standard to prevent this possibility by
requiring a Type 2 PD to corrupt the signature resistance
duringthemarkevent, alertingthePSEnottoapplypower.
The LTC4269-1 conforms to this standard by corrupting
the signature resistance. This also discharges the port
before the PSE begins the next detection cycle.
40
1st CLASS
30
2nd CLASS
ON
OFF
20
10
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
INRUSH
LOAD, I
LOAD
1st CLASS
2nd CLASS
40mA
TIME
PD STABILITY DURING CLASSIFICATION
DETECTION V1
DETECTION V2
1st MARK 2nd MARK
Classificationpresentsachallengingstabilityproblemdue
to the wide range of possible classification load current.
The onset of the classification load current introduces a
voltage drop across the cable and increases the forward
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classification with the
onset and removal of the classification load current.
50
40
30
20
10
dV
dt
INRUSH
C1
=
OFF
ON
OFF
T = R
C1
LOAD
TIME
TIME
The LTC4269-1 prevents this oscillation by introducing a
voltagehysteresiswindowbetweenthedetectionandclas-
sification ranges. The hysteresis window accommodates
the voltage changes a PD encounters at the onset of the
classification load current, thus providing a trouble-free
transition between detection and classification modes.
–10
–20
–30
–40
–50
TRACKS
V
PORTN
TheLTC4269-1alsomaintainsapositiveI-Vslopethrough-
out the classification range up to the on-voltage. In the
event a PSE overshoots beyond the classification voltage
range, the available load current aids in returning the PD
back into the classification voltage range. (The PD input
may otherwise be “trapped” by a reverse-biased diode
bridge and the voltage held by the 0.1ꢁF capacitor).
INRUSH = 100mA
R
= 30.9Ω
CLASS
V
R
PORTN
I
=
LOAD
LOAD
LTC4269-1
R
I
IN
LOAD
R
V
CLASS PORTP
PSE
R
C1
CLASS
T2P
V
V
NEG
PORTN
42691 F04
INRUSH CURRENT
Once the PSE detects and optionally classifies the PD,
the PSE then applies powers on the PD. When the
LTC4269-1 input voltage rises above the on-voltage
Figure 4. VNEG, T2P and PD Current
as a Result of 2-Event Classification
threshold, LTC4269-1 connects V
the internal power MOSFET.
to V
through
NEG
PORTN
42691fb
15
LTC4269-1
APPLICATIONS INFORMATION
To control the power-on surge currents in the system, the
LTC4269-1 provides a fixed inrush current, allowing C1 to
ramp up to the line voltage in a controlled manner.
doesnotfallbelowtheOFFthreshold.WhentheLTC4269-1
input voltage falls below the OFF threshold, the PD load
is disconnected, and classification mode resumes. C1
discharges through the LTC4269-1 circuitry.
The LTC4269-1 keeps the PD inrush current below the
PSE current limit to provide a well controlled power-up
characteristic that is independent of the PSE behavior.
This ensures a PD using the LTC4269-1 interoperability
with any PSE.
COMPLEMENTARY POWER GOOD
When LTC4269-1 fully charges the load capacitor (C1),
power good is declared and the LTC4269-1 load can safely
beginoperation. TheLTC4269-1providescomplementary
power good signals that remain active during normal op-
eration and are de-asserted when the input voltage falls
below the OFF threshold, when the input voltage exceeds
the overvoltage lockout (OVLO) threshold, or in the event
of a thermal shutdown (see Figure 6).
TURN-ON/ TURN-OFF THRESHOLD
The IEEE 802.3af/at specification for the PD dictates a
maximum turn-on voltage of 42V and a minimum turn-off
voltage of 30V. This specification provides an adequate
voltage to begin PD operation, and to discontinue PD op-
eration when the input voltage is too low. In addition, this
specification allows PD designs to incorporate an ON/OFF
hysteresis window to prevent start-up oscillations.
The PWRGD pin features an open collector output refer-
enced to V
which can interface directly with the UVLO
NEG
pin. When power good is declared and active, the PWRGD
pin is high impedance with respect to V . An internal
NEG
TheLTC4269-1featuresanON/OFFhysteresiswindow(see
Figure 5) that conforms with the IEEE 802.3af/at specifica-
tion and accommodates the voltage drop in the cable and
input diode bridge at the onset of the inrush current.
14V clamp limits the PWRGD pin voltage. Connecting the
PWRGD pin to the UVLO prevents the DC/DC converter
LTC4269-1
30 PWRGD
OVLO
ON/OFF
TSD
OnceC1isfullycharged,theLTC4269-1turnsonisinternal
MOSFET and passes power to the PD load. The LTC4269-1
continuestopowerthePDloadaslongastheinputvoltage
CONTROL
CIRCUIT
29 PWRGD
V
V
5
6
27
26
V
V
PORTN
NEG
C1
+
LTC4269-1
PD
LOAD
V
PORTP
5μF
MIN
NEG
TO
PSE
PORTN
ON/OFF AND
OVERVOLTAGE
LOCKOUT
BOLD LINE INDICATES HIGH CURRENT PATH
INRUSH COMPLETE
CIRCUIT
V
V
PORTN
NEG
42691 F05
ON < V
< OVLO
PORTP
AND NOT IN THERMAL SHUTDOWN
CURRENT-LIMITED
TURN ON
V
– V
LTC4269-1
POWER MOSFET
PORTP
PORTN
VOLTAGE
0V TO ON*
>ON*
OFF
ON
OFF
OFF
POWER
POWER
GOOD
NOT
GOOD
<OFF*
>OVLO
*INCLUDES ON/OFF HYSTERESIS
ON THRESHOLD 36.1V
OFF THRESHOLD 30.7V
OVLO THRESHOLD 71.0V
V
< OFF
PORTP
> OVLO
V
PORTP
OR THERMAL SHUTDOWN
42691 F06
Figure 5. LTC4269-1 ON/OFF and Overvoltage Lockout
Figure 6. LTC4269-1 Power Good Functional and State Diagram
42691fb
16
LTC4269-1
APPLICATIONS INFORMATION
from commencing operation before the PD interface
completely charges the reservoir capacitor, C1.
operations and power good becomes inactive. Normal
operation resumes when the junction temperature falls
below the overtemperature threshold and when C1 is
charged up.
The active low PWRGD pin connects to an internal, open-
drainMOSFETreferencedtoV
andmaybeusedasan
PORTN
indicator bit when power good is declared and active. The
EXTERNAL INTERFACE AND COMPONENT SELECTION
Transformer
PWRGD pin is low impedance with respect to V
.
PORTN
PWRGD PIN WHEN SHDN IS INVOKED
Nodes on an Ethernet network commonly interface to the
outside world via an isolation transformer. For PDs, the
isolation transformer must also include a center tap on
the RJ45 connector side (see Figure 7).
InPDapplicationswhereanauxiliarypowersupplyinvokes
the SHDN feature, the PWRGD pin becomes high imped-
ance. This prevents the PWRGD pin that is connected to
the UVLO pin from interfering with the DC/DC converter
operations when powered by an auxiliary power supply.
The increased current levels in a Type 2 PD over a Type 1
increase the current imbalance in the magnetics which
can interfere with data transmission. In addition, proper
termination is also required around the transformer to
providecorrectimpedancematchingandtoavoidradiated
and conducted emissions. Transformer vendors such as
Bel Fuse, Coilcraft, Halo, Pulse, and Tyco (Table 4) can
assist in selecting an appropriate isolation transformer
and proper termination methods.
OVERVOLTAGE LOCKOUT
The LTC4269-1 includes an overvoltage lockout (OVLO)
feature (Figure 6) which protects the LTC4269-1 and its
load from an overvoltage event. If the input voltage ex-
ceeds the OVLO threshold, the LTC4269-1 discontinues
PD operation. Normal operations resume when the input
voltage falls below the OVLO threshold and when C1 is
charged up.
Table 4. Power over Ethernet Transformer Vendors
VENDOR
CONTACT INFORMATION
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel: 201-432-0463
www.belfuse.com
THERMAL PROTECTION
TheIEEE802.3af/atspecificationrequiresaPDtowithstand
any applied voltage from 0V to 57V indefinitely. However,
there are several possible scenarios where a PD may
encounter excessive heating.
Coilcraft Inc.
1102 Silver Lake Road
Gary, IL 60013
Tel: 847-639-6400
www.coilcraft.com
During classification, excessive heating may occur if the
PSEexceedsthe75msprobingtimelimit.Atturn-on,when
the load capacitor begins to charge, the instantaneous
power dissipated by the PD interface can be large before
it reaches the line voltage. And if the PD experiences a
fast input positive voltage step in its operational mode
(for example, from 37V to 57V), the instantaneous power
dissipated by the PD Interface can be large.
Halo Electronics
PCA Electronics
Pulse Engineering
Tyco Electronics
1861 Landings Drive
Mountain View, CA 94043
Tel: 650-903-3800
www.haloelectronics.com
16799 Schoenborn Street
North Hills, CA 91343
Tel: 818-892-0761
www.pca.com
12220 World Trade Drive
San Diego, CA 92128
Tel: 858-674-8100
The LTC4269-1 includes a thermal protection feature
which protects the LTC4269-1 from excessive heating.
If the LTC4269-1 junction temperature exceeds the over-
temperature threshold, the LTC4269-1 discontinues PD
www.pulseeng.com
308 Constitution Drive
Menlo Park, CA 94025-1164
Tel: 800-227-7040
www.circuitprotection.com
42691fb
17
LTC4269-1
APPLICATIONS INFORMATION
Input Diode Bridge
bridge cannot generate more than 2.8V across a 100k
resistor when a PD is powered with 57V.
Figure 2 shows how two diode bridges are typically con-
nected in a PD application. One bridge is dedicated to the
data pair while the other bridge is dedicated to the spare
pair. The LTC4269-1 supports the use of either silicon or
Schottkyinputdiodebridges.However,therearetrade-offs
in the choice of diode bridges.
Sharing Input Diode Bridges
At higher temperatures, a PD design may be forced to
consider larger bridges in a bigger package because the
maximum operating current for the input diode bridge is
drastically derated. The larger package may not be accept-
able in some space-limited environments.
An input diode bridge must be rated above the maximum
current the PD application will encounter at the tempera-
ture the PD will operate. Diode bridge vendors typically
call out the operating current at room temperature, but
derate the maximum current with increasing temperature.
Consultthediodebridgevendorsfortheoperatingcurrent
derating curve.
One solution to consider is to reconnect the diode bridges
so that only one of the four diodes conducts current in
each package. This configuration extends the maximum
operating current while maintaining a smaller package
profile. Figure 7 shows how to reconnect the two diode
bridges. Consult the diode bridge vendors for the derating
curve when only one of four diodes is in operation.
Asilicondiodebridgecanconsumeover4%oftheavailable
power in some PD applications. Using Schottky diodes can
help reduce the power loss with a lower forward voltage.
Input Capacitor
A Schottky bridge may not be suitable for some high
temperature PD application. The leakage current has a
voltagedependencythatcanreducetheperceivedsignature
resistance. In addition, the IEEE 802.3af/at specification
mandates the leakage back-feeding through the unused
The IEEE 802.3af/at standard includes an impedance
requirement in order to implement the AC disconnect
function. A 0.1μF capacitor (C14 in Figure 7) is used to
meet this AC impedance requirement.
RJ45
+
1
TX
14 T1
12
1
3
BR1
HD01
–
TX
13
10
2
5
2
3
+
TO PHY
RX
11
9
4
6
–
RX
6
COILCRAFT
ETHI - 230LD
V
PORTP
+
–
SPARE
SPARE
4
5
7
8
BR2
HD01
C1
LTC4269-1
C14
0.1μF
100V
D3
SMAJ58A
TVS
V
V
NEG
PORTN
42691 F07
Figure 7. PD Front-End with Isolation Transformer, Diode Bridges,
Capacitors, and a Transient Voltage Suppressor (TVS).
42691fb
18
LTC4269-1
APPLICATIONS INFORMATION
Transient Voltage Suppressor
T2P Interface
The LTC4269-1 specifies an absolute maximum voltage of
100V and is designed to tolerate brief overvoltage events.
However, the pins that interface to the outside world can
routinely see excessive peak voltages. To protect the
LTC4269-1, install a transient voltage suppressor (D3)
between the input diode bridge and the LTC4269-1 as
shown in Figure 7.
When a 2-event classification sequence successfully
completes, the LTC4269-1 recognizes this sequence,
and provides an indicator bit, declaring the presence of
a Type 2 PSE. The open-drain output provides the option
to use this signal to communicate to the LTC4269-1 load,
or to leave the pin unconnected.
Figure 8 shows two interface options using the T2P
pin and the opto-isolator. The T2P pin is active low and
connects to an opto-isolator to communicate across the
Classification Resistor (R
)
CLASS
The R
resistor sets the classification load current,
DC/DC converter isolation barrier. The pull-up resistor R
CLASS
P
corresponding to the PD power classification. Select the
value of R from Table 2 and connect the resistor
is sized according to the requirements of the opto-isola-
tor operating current, the pull-down capability of the T2P
CLASS
+
+
between the R
and V
CLASS
pins as shown in Figure
pin, and the choice of V . V for example can come from
CLASS
PORTN
4, or float the R
pin if the classification load cur-
the PoE supply rail (which the LTC4269-1 V
is tied
PORTP
rent is not required. The resistor tolerance must be 1%
or better to avoid degrading the overall accuracy of the
classification circuit.
to), or from the voltage source that supplies power to
the DC/DC converter. Option 1 has the advantage of not
drawing power unless T2P is declared active.
Load Capacitor
+
The IEEE 802.3af/at specification requires that the PD
maintains a minimum load capacitance of 5ꢁF and does
not specify a maximum load capacitor. However, if the
load capacitor is too large, there may be a problem with
inadvertent power shutdown by the PSE.
V
V
PORTP
R
P
TO
PSE
LTC4269-1
TO PD LOAD
V
–54V
T2P
PORTN
ThisoccurswhenthePSEvoltagedropsquickly. Theinput
diode bridge reverses bias, and the PD load momentarily
powers off the load capacitor. If the PD does not draw
power within the PSE’s 300ms disconnection delay, the
PSE may remove power from the PD. Thus, it is necessary
to evaluate the load current and capacitance to ensure that
an inadvertent shutdown cannot occur.
OPTION 1: SERIES CONFIGURATION FOR ACTIVE LOW/LOW IMPEDANCE OUTPUT
+
V
V
PORTP
R
P
LTC4269-1
T2P
TO
PSE
The load capacitor can store significant energy when fully
charged.ThePDdesignmustensurethatthisenergyisnot
inadvertently dissipated in the LTC4269-1. For example,
TO PD LOAD
V
V
NEG
–54V
PORTN
42691 F08
if the V
pin shorts to V
while the capacitor
PORTP
PORTN
OPTION 2: SHUNT CONFIGURATION FOR ACTIVE HIGH/OPEN COLLECTOR OUTPUT
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4269-1.
Figure 8. T2P Interface Examples
42691fb
19
LTC4269-1
APPLICATIONS INFORMATION
Shutdown Interface
providesaseamlesstransitionfromPoEtoauxiliarypower
when auxiliary power is applied, however, the removal of
auxiliary power to PoE power is not seamless.
To corrupt the signature resistance, the SHDN pin can be
driven high with respect to V
. If unused, connect
PORTN
SHDN directly to V
.
Contact Linear Technology applications support for detail
information on implementing a custom auxiliary power
supply.
PORTN
Auxiliary Power Source
In some applications, it is desirable to power the PD from
an auxiliary power source such as a wall adapter.
IEEE 802.3at SYSTEM POWER-UP REQUIREMENT
Auxiliary power can be injected into an LTC4269-1-based
Under the IEEE 802.3at standard, a PD must operate
under 12.95W in accordance with IEEE 802.3at standard
until it recognizes a Type 2 PSE. Initializing PD operation
in 12.95W mode eliminates interoperability issue in case
a Type 2 PD connects to a Type 1 PSE. Once the PD rec-
ognizes a Type 2 PSE, the IEEE 802.3at standard requires
the PD to wait 80ms in 12.95W operation before 25.5W
operation can commence.
PD at the input of the LTC4269-1 V
, at V , or even
PORTN
NEG
the power supply output. In addition, some PD application
may desire auxiliary supply dominance or may be con-
figured for PoE dominance. Furthermore, PD applications
may also opt for a seamless transition — that is, without
power disruption — between PoE and auxiliary power.
The most common auxiliary power option injects power at
V . Figure 9 presents an example of this application. In
NEG
MAINTAIN POWER SIGNATURE
thisexample, theauxiliaryportinjects48Vontothelinevia
diode D1. The components surrounding the SHDN pin are
selectedsothattheLTC4269-1doesnotdisconnectpower
to the output until the auxiliary supply exceeds 36V.
In an IEEE 802.3af/at system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
requirepower.TheMPSrequiresthePDtoperiodicallydraw
at least 10mA and also have an AC impedance less than
26.25k in parallel with 0.05ꢁF. If one of these conditions
is not met, the PSE may disconnect power to the PD.
This configuration is an auxiliary-dominant configuration.
Thatis,theauxiliarypowersourcesuppliesthepowereven
if PoE power is already present. This configuration also
RJ45
+
1
TX
T1
TVS
+
–
–
0.1μF
TX
C1
2
3
100V
+
TO PHY
RX
BR1
BR2
–
RX
6
36V
V
100k
10k
PORTP
+
–
SPARE
LTC4269-1
SHDN
GND
+
–
4
5
7
8
10k
SPARE
V
V
NEG
PORTN
+
ISOLATED
WALL
TRANSFORMER
D1
–
42691 F09
Figure 9. Auxiliary Power Dominant PD Interface Example
42691fb
20
LTC4269-1
APPLICATIONS INFORMATION
SWITCHING REGULATOR OVERVIEW
amplifier whose output is connected to V
only during
CMP
a period in the flyback time. An external capacitor on
the V pin integrates the net feedback amp current to
TheLTC4269-1includesacurrentmodeconverterdesigned
specificallyforuseinanisolatedflybacktopologyemploying
synchronous rectification. The LTC4269-1 operation is
similar to traditional current mode switchers. The major
difference is that output voltage feedback is derived via
sensing the output voltage through the transformer. This
precludes the need of an opto-isolator in isolated designs,
thus greatly improving dynamic response and reliability.
The LTC4269-1 has a unique feedback amplifier that
samples a transformer winding voltage during the flyback
period and uses that voltage to control output voltage.
The internal blocks are similar to many current mode
controllers.Thedifferenceslieinthefeedbackamplifierand
load compensation circuitry. The logic block also contains
circuitry to control the special dynamic requirements of
flyback control. For more information on the basics of
current mode switcher/controllers and isolated flyback
converters see Application Note 19.
CMP
provide the control voltage to set the current mode trip
point. The regulation voltage at the FB pin is nearly equal
to the bandgap reference V because of the high gain in
FB
the overall loop. The relationship between V
and V
FLBK
FB
is expressed as:
R1+R2
R2
V
=
• V
FB
FLBK
Combining this with the previous V
expression yields
FLBK
an expression for V
in terms of the internal reference,
OUT
programming resistors and secondary resistances:
R1+R2
R2
⎛
⎞
VOUT
=
• V •N
−I • ESR+R
(
)
⎜
⎝
⎟
⎠
FB
SF
SEC
DS(ON)
The effect of nonzero secondary output impedance is
discussed in further detail (see Load Compensation
Theory).Thepracticalaspectsofapplyingthisequationfor
Feedback Amplifier—Pseudo DC Theory
V
are found in subsequent sections of the Applications
OUT
Information.
For the following discussion, refer to the simplified
Switching Regulator Feedback Amplifier diagram (Figure
10A).Whentheprimary-sideMOSFETswitchMPturnsoff,
Feedback Amplifier Dynamic Theory
itsdrainvoltagerisesabovetheV
rail.Flybackoccurs
PORTP
So far, this has been a pseudo-DC treatment of flyback
feedback amplifier operation. But the flyback signal is a
pulse, not a DC level. Provision is made to turn on the
flyback amplifier only when the flyback pulse is present,
using the enable signal as shown in the timing diagram
(Figure 10b).
when the primary MOSFET is off and the synchronous
secondary MOSFET is on. During flyback the voltage on
nondriventransformerpinsisdeterminedbythesecondary
voltage. The amplitude of this flyback pulse, as seen on
the third winding, is given as:
VOUT +ISEC • ESR+R
(
)
DS(ON)
V
=
Minimum Output Switch On Time (t
)
ON(MIN)
FLBK
NSF
The LTC4269-1 affects output voltage regulation via
flyback pulse action. If the output switch is not turned on,
there is no flyback pulse and output voltage information
is not available. This causes irregular loop response and
start-up/latchup problems. The solution is to require the
primary switch to be on for an absolute minimum time per
each oscillator cycle. To accomplish this the current limit
R
= on-resistance of the synchronous MOSFET MS
DS(ON)
I
= transformer secondary current
SEC
ESR = impedance of secondary circuit capacitor, winding
and traces
N = transformer effective secondary-to-flyback winding
SF
turns ratio (i.e., N /N
)
S
FLBK
feedbackisblankedeachcyclefort
.Iftheoutputload
ON(MIN)
is less than that developed under these conditions, forced
continuous operation normally occurs. See subsequent
discussions in the Applications Information section for
The flyback voltage is scaled by an external resistive
divider R1/R2 and presented at the FB pin. The feedback
amplifier compares the voltage to the internal bandgap
reference.Thefeedbackampisactuallyatransconductance
further details.
42691fb
21
LTC4269-1
APPLICATIONS INFORMATION
T1
V
FLBK
FLYBACK
LTC4269-1 FEEDBACK AMP
R1
R2
•
•
FB
16
–
V
CMP
1V
17
V
IN
V
FB
C
+
+
C
VCMP
ISOLATED
OUTPUT
1.237V
–
+
PRIMARY
SECONDARY
MS
OUT
•
MP
COLLAPSE
DETECT
R
S
ENABLE
Q
42691 F10a
Figure 10a. LTC4269-1 Switching Regulator Feedback Amplifier
V
FLBK
0.8 • V
PRIMARY-SIDE
MOSFET DRAIN
VOLTAGE
FLBK
V
IN
PG VOLTAGE
SG VOLTAGE
42691 F10b
t
MIN ENABLE
PG DELAY
ON(MIN)
ENABLE
DELAY
FEEDBACK
AMPLIFIER
ENABLED
Figure 10b. LTC4269-1 Switching Regulator Timing Diagram
42691fb
22
LTC4269-1
APPLICATIONS INFORMATION
Enable Delay Time (ENDLY)
Load Compensation Theory
The flyback pulse appears when the primary-side switch
shutsoff.However,ittakesafinitetimeuntilthetransformer
primary-side voltage waveform represents the output
voltage. This is partly due to rise time on the primary-
side MOSFET drain node, but, more importantly, is due
to transformer leakage inductance. The latter causes a
voltage spike on the primary side, not directly related to
output voltage. Some time is also required for internal
settling of the feedback amplifier circuitry. In order to
maintain immunity to these phenomena, a fixed delay is
introduced between the switch turn-off command and the
enabling of the feedback amplifier. This is termed “enable
delay.” In certain cases where the leakage spike is not
sufficiently settled by the end of the enable delay period,
regulation error may result. See the subsequent sections
for further details.
The LTC4269-1 uses the flyback pulse to obtain
information about the isolated output voltage. An error
source is caused by transformer secondary current flow
through the synchronous MOSFET R
and real life
DS(ON)
nonzero impedances of the transformer secondary and
output capacitor. This was represented previously by the
expression, I •(ESR+R
). However, itisgenerally
SEC
DS(ON)
more useful to convert this expression to effective output
impedance. Because the secondary current only flows
during the off portion of the duty cycle (DC), the effective
outputimpedanceequalsthelumpedsecondaryimpedance
divided by off time DC.
Since the off-time duty cycle is equal to 1 – DC, then:
ESR+RDS(ON)
RS(OUT)
=
1−DC
Collapse Detect
where:
Once the feedback amplifier is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the flyback
R
= effective supply output impedance
S(OUT)
DC = duty cycle
and ESR are as defined previously
voltage (FB) to a fixed reference, nominally 80% of V .
FB
R
DS(ON)
When the flyback waveform drops below this level, the
feedback amplifier is disabled.
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relativelyconstant.Inthesecases,theexternalFBresistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function. Figure 11 shows the block diagram of the load
compensation function. Switch current is converted to a
voltagebytheexternalsenseresistor,averagedandlowpass
Minimum Enable Time
The feedback amplifier, once enabled, stays on for a fixed
minimum time period, termed “minimum enable time.”
This prevents lockup, especially when the output voltage
is abnormally low, e.g., during start-up. The minimum
enable time period ensures that the V
node is able to
CMP
“pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is set internally.
filtered by the internal 50k resistor R
capacitor on C . This voltage is impressed across the
external R
and the external
CMPF
CMP
resistor by op amp A1 and transistor Q3
CMP
producingacurrentatthecollectorofQ3thatissubtracted
from the FB node. This effectively increases the voltage
requiredatthetopoftheR1/R2feedbackdividertoachieve
equilibrium.
Effects of Variable Enable Period
The feedback amplifier is enabled during only a portion of
thecycletime.Thiscanvaryfromthefixedminimumenable
time described to a maximum of roughly the off switch
time minus the enable delay time. Certain parameters of
feedbackampbehavioraredirectlyaffectedbythevariable
enable period. These include effective transconductance
The average primary-side switch current increases to
maintain output voltage regulation as output loading
increases. TheincreaseinaveragecurrentincreasesR
CMP
and V
node slew rate.
resistor current which affects a corresponding increase
CMP
42691fb
23
LTC4269-1
APPLICATIONS INFORMATION
in sensed output voltage, compensating for the IR drops.
Assuming relatively fixed power supply efficiency, Eff,
power balance gives:
Nominal output impedance cancellation is obtained by
equating this expression with R
:
S(OUT)
ESR+RDS(ON)
1−DC
RSENSE
RCMP
K1•
•R1•NSF =
P
V
= Eff • P
IN
OUT
• I
= Eff • V • I
IN IN
OUT OUT
Solving for R
gives:
CMP
Average primary-side current is expressed in terms of
output current as follows:
RSENSE • 1−DC
ESR+RDS(ON)
(
)
•R1•NSF
RCMP =K1•
IIN =K1•IOUT
where:
Thepracticalaspectsofapplyingthisequationtodetermine
an appropriate value for the R resistor are discussed
subsequently in the Applications Information section.
VOUT
CMP
K1=
V •Eff
IN
So, the effective change in V
target is:
Transformer Design
OUT
RSENSE
RCMP
Transformerdesign/specificationisthemostcriticalpartof
a successful application of the LTC4269-1. The following
sections provide basic information about designing the
transformer and potential trade-offs. If you need help, the
LTC Applications group is available to assist in the choice
and/or design of the transformer.
ΔVOUT =K1•
•R1•NSF • ΔIOUT
thus:
ΔVOUT
ΔIOUT
RSENSE
RCMP
=K1•
•R1•NSF
Turns Ratios
where:
K1 = dimensionless variable related to V , V
ficiency, as previously explained
The design of the transformer starts with determining
dutycycle(DC). DCimpactsthecurrentandvoltagestress
on the power switches, input and output capacitor RMS
currents and transformer utilization (size vs power). The
ideal turns ratio is:
and ef-
IN OUT
R
= external sense resistor
SENSE
V
FLBK
VOUT
1−DC
DC
NIDEAL
=
•
R1
FB
•
•
V
IN
16
Q1 Q2
V
FB
V
IN
Avoid extreme duty cycles, as they generally increase cur-
rent stresses. A reasonable target for duty cycle is 50%
at nominal input voltage.
R2
LOAD
COMP I
•
MP
+
R
CMPF
50k
+
Q3
A1
SENSE
20
For instance, if we wanted a 48V to 5V converter at 50%
DC then:
–
5 1− 0.5
• =
1
9.6
NIDEAL
=
22
R
21
C
R
SENSE
CMP
CMP
48 0.5
42691 F11
In general, better performance is obtained with a lower
turns ratio. A DC of 45.5% yields a 1:8 ratio.
Figure 11. Load Compensation Diagram
42691fb
24
LTC4269-1
APPLICATIONS INFORMATION
Note the use of the external feedback resistive divider
ratio to set output voltage provides the user additional
freedom in selecting a suitable transformer turns ratio.
Turns ratios that are the simple ratios of small integers;
e.g., 1:1, 2:1, 3:2 help facilitate transformer construction
and improve performance.
pulse extends beyond the enable delay time, output
voltage regulation is affected. The feedback system has a
deliberately limited input range, roughly 50mV referred
to the FB node. This rejects higher voltage leakage spikes
because once a leakage spike is several volts in amplitude,
a further increase in amplitude has little effect on the
feedback system. Therefore, it is advisable to arrange the
clamp circuit to clamp at as high a voltage as possible,
observing MOSFET breakdown, such that leakage spike
duration is as short as possible. Application Note 19
provides a good reference on clamp design.
When building a supply with multiple outputs derived
through a multiple winding transformer, lower duty cycle
can improve cross regulation by keeping the synchronous
rectifier on longer, and thus, keep secondary windings
coupledlonger.Foramultipleoutputtransformer,theturns
ratio between output windings is critical and affects the
accuracy of the voltages. The ratio between two output
As a rough guide, leakage inductance of several percent
(of mutual inductance) or less may require a clamp, but
exhibit little to no regulation error due to leakage spike
behavior.Inductancesfromseveralpercentupto,perhaps,
ten percent, cause increasing regulation error.
voltagesissetwiththeformulaV
=V
•N21where
OUT2
OUT1
N21 is the turns ratio between the two windings. Also
keep the secondary MOSFET R
cross regulation.
small to improve
DS(ON)
Avoid double digit percentage leakage inductances. There
isapotentialforabruptlossofcontrolathighloadcurrent.
Thiscuriousconditionpotentiallyoccurswhentheleakage
spikebecomessuchalargeportionoftheflybackwaveform
thattheprocessingcircuitryisfooledintothinkingthatthe
leakage spike itself is the real flyback signal!
The feedback winding usually provides both the feedback
voltage and power for the LTC4269-1. Set the turns ratio
between the output and feedback winding to provide a
rectifiedvoltagethatunderworst-caseconditionsisgreater
than the 11V maximum V turn-off voltage.
CC
VOUT
NSF >
It then reverts to a potentially stable state whereby the
top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This typically reduces the output voltage
abruptly to a fraction, roughly one-third to two-thirds of
its correct value.
11+ VF
where:
V =Diode Forward Voltage
F
5
1
For our example: NSF >
=
11+ 0.7 2.34
Onceloadcurrentisreducedsufficiently,thesystemsnaps
back to normal operation. When using transformers with
considerableleakageinductance,exercisethisworst-case
check for potential bistability:
1
We will choose
3
Leakage Inductance
1. Operate the prototype supply at maximum expected
load current.
Transformer leakage inductance (on either the primary or
secondary) causes a spike after the primary-side switch
turn-off. This is increasingly prominent at higher load
currents, where more stored energy is dissipated. Higher
flyback voltage may break down the MOSFET switch if it
2. Temporarily short-circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
lowvalue,thesystemhasaproblem.Thisisusuallyevident
bysimultaneouslyviewingtheprimary-sideMOSFETdrain
voltage to observe firsthand the leakage spike behavior.
has too low a BV
rating.
DSS
Onesolutiontoreducingthisspikeistouseaclampcircuit
to suppress the voltage excursion. However, suppressing
the voltage extends the flyback pulse width. If the flyback
42691fb
25
LTC4269-1
APPLICATIONS INFORMATION
A final note—the susceptibility of the system to bistable
behavior is somewhat a function of the load current/
voltage characteristics. A load with resistive—i.e., I = V/R
behavior—is the most apt to be bistable. Capacitive loads
Ripplecurrentandpercentagerippleislargestatminimum
duty cycle; in other words, at the highest input voltage.
P
L is calculated from the following equation.
2
V
IN(MAX) •DCMIN
V
IN(MAX) •DCMIN 2 •Eff
2
that exhibit I = V /R behavior are less susceptible.
(
)
(
)
LP =
=
fOSC • XMAX •P
fOSC • XMAX •POUT
IN
Secondary Leakage Inductance
where:
Leakage inductance on the secondary forms an inductive
divider on the transformer secondary, reducing the size
of the flyback pulse. This increases the output voltage
target by a similar percentage. Note that unlike leakage
spike behavior, this phenomenon is independent of load.
Since the secondary leakage inductance is a constant
percentage of mutual inductance (within manufacturing
variations), the solution is to adjust the feedback resistive
divider ratio to compensate.
f
is the oscillator frequency
OSC
DC
is the DC at maximum input voltage
MIN
X
is ripple current ratio at maximum input voltage
MAX
Using common high power PoE values, a 48V (41V < V
IN
< 57V) to 5V/5.3A converter with 90% efficiency, P
=
OUT
26.5W and P = 29.5W. Using X = 0.4 N = 1/8 and f
IN
OSC
= 200kHz:
Winding Resistance Effects
1
1
DCMIN
=
=
= 41.2%
N• V
1 57
Primary or secondary winding resistance acts to reduce
IN(MAX)
1+ •
1+
overallefficiency(P /P ).Secondarywindingresistance
8 5
VOUT
OUT IN
increaseseffectiveoutputimpedance,degradingloadregu-
lation.Loadcompensationcanmitigatethistosomeextent
but a good design keeps parasitic resistances low.
2
57V •0.412
200kHz •0.4•26.5W
(
)
LP =
= 260µH
Optimization might show that a more efficient solution
is obtained at higher peak current but lower inductance
and the associated winding series resistance. A simple
spreadsheet program is useful for looking at trade-offs.
Bifilar Winding
A bifilar, or similar winding, is a good way to minimize
troublesome leakage inductances. Bifilar windings also
improve coupling coefficients, and thus improve cross
regulation in multiple winding transformers. However,
tight coupling usually increases primary-to-secondary
capacitance and limits the primary-to-secondary
breakdown voltage, so is not always practical.
Transformer Core Selection
OnceL isknown,thetypeoftransformerisselected.High
P
efficiency converters use ferrite cores to minimize core
loss. Actualcorelossisindependentofcoresizeforafixed
inductance, but decreases as inductance increases. Since
increasedinductanceisaccomplishedthroughmoreturns
of wire, copper losses increase. Thus, transformer design
balancescoreandcopperlosses.Rememberthatincreased
winding resistance will degrade cross regulation and
increase the amount of load compensation required.
Primary Inductance
The transformer primary inductance, L , is selected
P
based on the peak-to-peak ripple current ratio (X) in the
transformer relative to its maximum value. As a general
rule, keep X in the range of 20% to 40% (i.e., X = 0.2 to
0.4).Highervaluesofripplewillincreaseconductionlosses,
while lower values will require larger cores.
The main design goals for core selection are reducing
copper losses and preventing saturation. Ferrite core
material saturates hard, rapidly reducing inductance
when the peak design current is exceeded. This results
42691fb
26
LTC4269-1
APPLICATIONS INFORMATION
in an abrupt increase in inductor ripple current and,
consequently, output voltage ripple. Do not allow the core
to saturate! The maximum peak primary current occurs
Continuing the example, if ESR + R
3.32k, then:
= 8mΩ, R2 =
DS(ON)
5+ 5.3•0.008
1.237 •1/ 3
⎛
⎞
at minimum V :
R1= 3.32k
−1 = 37.28k
⎟
IN
⎜
⎝
⎠
P
XMIN
2
⎛
⎞
IN
IPK =
• 1+
⎜
⎟
⎠
⎝
choose 37.4k.
V
IN(MIN) •DCMAX
It is recommended that the Thevenin impedance of the
resistive divider (R1||R2) is roughly 3k for bias current
cancellation and other reasons.
now:
1
1
DCMAX
=
=
= 49.4%
N• V
1 41
1+ •
8 5
IN MIN
(
)
1+
VOUT
Current Sense Resistor Considerations
2
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistordirectlyaboveanunbrokengroundplaneconnected
with wide and short traces keeps stray resistance and
inductance low.
2
V
IN(MIN) •DCMAX
(
)
41• 49.4%
(
)
XMIN
=
=
fOSC •LP •P
200kHz •260µH•29.5W
IN
= 0.267
Using the example numbers leads to:
29.5W
41•0.494
0.267
2
⎛
⎞
IPK =
• 1+
=1.65A
⎜
⎟
⎠
⎝
ThedualsensepinsallowforafullKelvinconnection.Make
sure that SENSE+ and SENSE– are isolated and connect
close to the sense resistor.
Multiple Outputs
One advantage that the flyback topology offers is that
additionaloutputvoltagescanbeobtainedsimplybyadding
windings. Designing a transformer for such a situation is
beyondthescopeofthisdocument.Formultiplewindings,
realize that the flyback winding signal is a combination of
activityonallthesecondarywindings.Thusloadregulation
is affected by each winding’s load. Take care to minimize
cross regulation effects.
Peakcurrentoccursat100mVofsensevoltageV
. So
SENSE
/I . For example, a
the nominal sense resistor is V
SENSE PK
peakswitchcurrentof10Arequiresanominalsenseresistor
of 0.010Ω Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
Size R
SENSE
using worst-case conditions, minimum L ,
P
SENSE
Setting Feedback Resistive Divider
V
and maximum V . Continuing the example, let us
IN
assumethatourworst-caseconditionsyieldanI of40%
TheexpressionforV developedintheOperationsection
PK
OUT
above nominal, so I = 2.3A. If there is a 10% tolerance
is rearranged to yield the following expression for the
PK
on R
and minimum V
= 88mV, then R
SENSE
•
feedback resistors:
SENSE
SENSE
SENSE
= 35mΩ. Round
110% = 88mV/2.3A and nominal R
⎛
⎜
⎞
⎡
⎣
⎤
⎦
VOUT +ISEC • ESR+R
to the nearest available lower value, 33mΩ.
(
)
DS(ON)
⎟
−1
R1=R2
VFB •NSF
⎜
⎝
⎟
⎠
42691fb
27
LTC4269-1
APPLICATIONS INFORMATION
Selecting the Load Compensation Resistor
4. Compute:
RCMP =K1•
The expression for R
section as:
was derived in the Operation
RSENSE
RS(OUT)
CMP
•R1•NSF
RSENSE • 1−DC
ESR+RDS(ON)
(
)
•R1•NSF
RCMP =K1•
5. Verify this result by connecting a resistor of this value
from the R pin to ground.
CMP
Continuing the example:
6.DisconnectthegroundshorttoC
andconnecta0.1μF
CMP
filter capacitor to ground. Measure the output imped-
anceR =ΔV /ΔI withthenewcompensation
⎛
⎜
⎝
⎞
⎟
⎠
VOUT
5
K1=
=
= 0.116
S(OUT)
in place. R
OUT OUT
should have decreased significantly.
V •Eff
48 •90%
IN
S(OUT)
Fine tuning is accomplished experimentally by slightly
altering R . A revised estimate for R is:
1
1
DC=
=
= 45.5%
N•V
1 48
1+ •
8 5
CMP
CMP
IN(NOM)
1+
VOUT
⎛
⎞
⎟
RS(OUT)CMP
RC′ MP =RCMP • 1+
⎜
If ESR+RDS(ON) = 8mΩ
RS(OUT)
⎝
⎠
33mΩ • 1− 0.455
(
1
3
)
RCMP = 0.116 •
= 3.25k
•37.4kΩ •
where R′ is the new value for the load compensation
CMP
resistor. R
8mΩ
is the output impedance with R
CMP
S(OUT)CMP
in place and R
is the output impedance with no
S(OUT)
load compensation (from step 2).
This value for R
is a good starting point, but empirical
CMP
methods are required for producing the best results.
This is because several of the required input variables
are difficult to estimate precisely. For instance, the ESR
term above includes that of the transformer secondary,
but its effective ESR value depends on high frequency
behavior, not simply DC winding resistance. Similarly, K1
Setting Frequency
The switching frequency of the LTC4269-1 is set by an
external capacitor connected between the OSC pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz.Figure12showsthenominalrelationshipbetween
external capacitance and switching frequency. Place the
capacitor as close as possible to the IC and minimize OSC
appears as a simple ratio of V to V
times efficiency,
IN
OUT
but theoretically estimating efficiency is not a simple
calculation.
300
The suggested empirical method is as follows:
1. Build a prototype of the desired supply including the
actual secondary components.
200
2. Temporarily ground the C
pin to disable the load
CMP
compensation function. Measure output voltage while
sweeping output current over the expected range.
Approximate the voltage variation as a straight line.
100
50
ΔV /ΔI
= R
.
OUT OUT
S(OUT)
30
100
(pF)
200
3. Calculate a value for the K1 constant based on V , V
IN OUT
C
OSC
42691 F12
and the measured efficiency.
Figure 12. fOSC vs OSC Capacitor Values
42691fb
28
LTC4269-1
APPLICATIONS INFORMATION
trace length and area to minimize stray capacitance and
potential noise pick-up.
The t
resistor is set with the following equation
ON(MIN)
tON(MIN) ns −104
(
)
RtON(MIN) kΩ =
(
)
You can synchronize the oscillator frequency to an
external frequency. This is done with a signal on the SYNC
pin. Set the LTC4269-1 frequency 10% slower than the
desired external frequency using the OSC pin capacitor,
then use a pulse on the SYNC pin of amplitude greater
than 2V and with the desired frequency. The rising edge
of the SYNC signal initiates an OSC capacitor discharge
forcing primary MOSFET off (PG voltage goes low). If
the oscillator frequency is much different from the sync
frequency, problems may occur with slope compensation
and system stability. Also, keep the sync pulse width
greater than 500ns.
1.063
Keep R
is 160k.
greater than 70k. A good starting value
tON(MIN)
Enable Delay Time (ENDLY)
Enabledelaytimeprovidesaprogrammabledelaybetween
turn-offoftheprimarygatedrivenodeandthesubsequent
enabling of the feedback amplifier. As discussed earlier,
this delay allows the feedback amplifier to ignore the
leakage inductance voltage spike on the primary side.
The worst-case leakage spike pulse width is at maximum
load conditions. So, set the enable delay time at these
conditions.
Selecting Timing Resistors
There are three internal “one-shot” times that are
programmed by external application resistors: minimum
on-time, enable delay time and primary MOSFET turn-on
delay. These are all part of the isolated flyback control
technique, and their functions are previously outlined in
theTheoryofOperationsection.Thefollowinginformation
should help in selecting and/or optimizing these timing
values.
While the typical applications for this part use forced
continuous operation, it is conceivable that a secondary-
side controller might cause discontinuous operation at
light loads. Under such conditions, the amount of energy
stored in the transformer is small. The flyback waveform
becomes “lazy” and some time elapses before it indicates
theactualsecondaryoutputvoltage.Theenabledelaytime
should be made long enough to ignore the “irrelevant”
portion of the flyback waveform at light loads.
Minimum Output Switch On-Time (t
)
ON(MIN)
EventhoughtheLTC4269-1hasarobustgatedrive,thegate
transition time slows with very large MOSFETs. Increase
delay time as required when using such MOSFETs.
Minimumon-timeistheprogrammableperiodduringwhich
current limit is blanked (ignored) after the turn-on of the
primary-sideswitch.Thisimprovesregulatorperformance
by eliminating false tripping on the leading edge spike in
the switch, especially at light loads. This spike is due to
both the gate/source charging current and the discharge
ofdraincapacitance.Theisolatedflybacksensingrequires
a pulse to sense the output. Minimum on-time ensures
that the output switch is always on a minimum time and
that there is always a signal to close the loop.
The enable delay resistor is set with the following
equation:
tENDLY ns − 30
(
)
RENDLY kΩ =
(
)
2.616
Keep R
56k.
greater than 40k. A good starting point is
ENDLY
The LTC4269-1 does not employ cycle skipping at light
loads. Therefore, minimum on-time along with synchro-
nousrectificationsetstheswitchovertoforcedcontinuous
mode operation.
42691fb
29
LTC4269-1
APPLICATIONS INFORMATION
Primary Gate Delay Time (PGDLY)
Switcher’s UVLO Pin Function
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of the
primary-side MOSFET. Correct setting eliminates overlap
betweentheprimary-sideswitchandsecondary-sidesyn-
chronous switch(es) and the subsequent current spike in
thetransformer.Thisspikewillcauseadditionalcomponent
stress and a loss in regulator efficiency.
The UVLO pin provides a user programming undervoltage
lockout. This is typically used to provide undervoltage
lockout based on V . The gate drivers are disabled when
IN
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
dropping the voltage on UVLO. In this manner, hysteresis
is produced.
The primary gate delay resistor is set with the following
equation:
tPGDLY ns + 47
(
)
RPGDLY kΩ =
(
)
9.01
A good starting point is 15k.
Soft-Start Function
Referring to Figure 13, the voltage hysteresis at V is
IN
equal to the change in bias current times R . The design
A
TheLTC4269-1containsanoptionalsoft-startfunctionthat
isenabledbyconnectinganexternalcapacitorbetweenthe
SFSTpinandground.Internalcircuitrypreventsthecontrol
procedure is to select the desired V referred voltage
IN
hysteresis, V
. Then:
UVHYS
voltage at the V
pin from exceeding that on the SFST
VUVHYS
IUVLO
CMP
RA =
pin. There is an initial pull-up circuit to quickly bring the
SFST voltage to approximately 0.8V. From there it charges
to approximately 2.8V with a 20μA current source.
where:
The SFST node is discharged to 0.8V when a fault occurs.
I
= I
– I
is approximately 3.4μA
UVLO
UVLOL
UVLOH
AfaultoccurswhenV istoolow(undervoltagelockout),
CC
R is then selected with the desired turn-on voltage:
B
current sense voltage is greater than 200mV or the IC’s
thermal (overtemperature) shutdown is tripped. When
RA
RB =
SFST discharges, the V
node voltage is also pulled low
CMP
V
⎛
⎝
⎞
IN(ON)
to below the minimum current voltage. Once discharged
and the fault removed, the SFST charges up again. In this
manner, switch currents are reduced and the stresses in
the converter are reduced during fault conditions.
–1
⎜
⎟
⎠
V
UVLO
V
IN
The time it takes to fully charge soft-start is:
I
I
UVLO
UVLO
R
A1
A2
CSFST •1.4V
V
V
IN
IN
tSS
=
= 70kΩ •CSFST µF
(
)
R
R
20µA
R
R
A
B
A
B
C
UVLO
UVLO
UVLO
UVLO
LTC4969-1
B
LTC4969-1
R
R
42691 F13
(13a) UV Turning On
(13b) UV Turning Off
(13c) UV Filtering
Figure 13. UVLO Pin Function and Recommended Filtering
42691fb
30
LTC4269-1
APPLICATIONS INFORMATION
If we wanted a V -referred trip point of 36V, with 1.8V
IfC isundersized,V reachestheV turn-offthreshold
TR CC CC
IN
(5%) of hysteresis (on at 36V, off at 34.2V):
before stabilization and the LTC4269-1 turns off. The V
CC
node then begins to charge back up via R to the turn-on
TR
1.8V
3.4µA
RA =
RB =
= 529k, use 523k
threshold, where the part again turns on. Depending upon
the circuit, this may result in either several on-off cycles
beforeproperoperationisreached,orpermanentrelaxation
523k
=18.5k, use 18.7k
oscillation at the V node.
36V
1.23V
⎛
⎞
CC
–1
⎜
⎝
⎟
⎠
V
IN
Even with good board layout, board noise may cause
problems with UVLO. You can filter the divider but keep
large capacitance off the UVLO node because it will slow
the hysteresis produced from the change in bias current.
Figure 13c shows an alternate method of filtering by split-
R
TR
•
•
V
IN
+
C
TR
I
VCC
•
V
CC
ting the R resistor with the capacitor. The split should put
LTC4269-1 PG
GND
A
more of the resistance on the UVLO side.
Converter Start-Up
V
THRESHOLD
CC(ON)
The standard topology for the LTC4269-1 utilizes a third
transformer winding on the primary side that provides
V
I
VCC
VCC
0
both feedback information and local V power for the
CC
LTC4269-1 (see Figure 14). This power bootstrapping
improves converter efficiency but is not inherently self-
starting.Start-upisaffectedwithanexternal“tricklecharge”
V
PG
42691 F14
Figure 14. Typical Power Bootstrapping
resistor and the LTC4269-1’s internal V undervoltage
CC
lockout circuit. The V undervoltage lockout has wide
CC
R
is selected to yield a worst-case minimum charging
TR
hysteresis to facilitate start-up.
currentgreaterthanthemaximumratedLTC4269-1start-up
current, andaworst-casemaximumchargingcurrentless
than the minimum rated LTC4269-1 supply current.
In operation, the trickle charge resistor, R , is connected
TR
to V and supplies a small current, typically on the order
IN
of 1mA to charge C . Initially the LTC4269-1 is off and
TR
V
IN(MIN) − VCC(ON_MAX)
RTR(MAX)
<
draws only its start-up current. When C reaches the V
TR
CC
ICC(ST _MAX)
turn-onthresholdvoltagetheLTC4269-1turnsonabruptly
and draws its normal supply current.
and
V
IN(MAX) − VCC(ON_MIN)
Switching action commences and the converter begins to
deliver power to the output. Initially the output voltage is
RTR(MIN)
>
ICC(MIN)
low and the flyback voltage is also low, so C supplies
TR
most of the LTC4269-1 current (only a fraction comes
Make C large enough to avoid the relaxation oscillatory
TR
from R .) V voltage continues to drop until, after
TR
CC
behavior described above. This is complicated to deter-
mine theoretically as it depends on the particulars of the
secondary circuit and load behavior. Empirical testing is
recommended. Note that the use of the optional soft-start
function lengthens the power-up timing and requires a
some time (typically tens of milliseconds) the output
voltage approaches its desired value. The flyback winding
then provides the LTC4269-1 supply current and the V
voltage stabilizes.
CC
correspondingly larger value for C .
TR
42691fb
31
LTC4269-1
APPLICATIONS INFORMATION
The LTC4269-1 has an internal clamp on V of approxi-
Slope Compensation
CC
mately 19.5V. This provides some protection for the part
TheLTC4269-1incorporatescurrentslopecompensation.
Slope compensation is required to ensure current loop
stabilitywhentheDCisgreaterthan50%.Insomeswitching
regulators,slopecompensationreducesthemaximumpeak
current at higher duty cycles. The LTC4269-1 eliminates
this problem by having circuitry that compensates for
the slope compensation so that maximum current sense
voltage is constant across all duty cycles.
in the event that the switcher is off (UVLO low) and the
V
node is pulled high. If R is sized correctly, the part
TR
CC
should never attain this clamp voltage.
Control Loop Compensation
Loop frequency compensation is performed by connect-
ing a capacitor network from the output of the feedback
amplifier (V
pin) to ground as shown in Figure 15.
CMP
Becauseofthesamplingbehaviorofthefeedbackamplifier,
Minimum Load Considerations
compensation is different from traditional current mode
controllers. Normally only C
At light loads, the LTC4269-1 derived regulator goes into
forced continuous conduction mode. The primary-side
switch always turns on for a short time as set by the
is required. R
can
VCMP
VCMP
be used to add a zero, but the phase margin improvement
traditionallyofferedbythisextraresistorisusuallyalready
accomplishedbythenonzerosecondarycircuitimpedance.
t
resistor. If this produces more power than the
ON(MIN)
load requires, power will flow back into the primary dur-
ing the off period when the synchronization switch is on.
This does not produce any inherently adverse problems,
although light load efficiency is reduced.
C
can be used to add an additional high frequency
VCMP2
pole and is usually sized at 0.1 times C
.
VCMP
V
CMP
17
Maximum Load Considerations
C
R
VCMP
VCMP2
The current mode control uses the V
node voltage
CMP
C
VCMP
and amplified sense resistor voltage as inputs to the
current comparator. When the amplified sense voltage
42691 F15
exceeds the V
is turned off.
node voltage, the primary-side switch
CMP
Figure 15. VCMP Compensation Network
In normal use, the peak switch current increases while
FB is below the internal reference. This continues until
In further contrast to traditional current mode switchers,
CMP
V
pinrippleisgenerallynotanissuewiththeLTC4269-1.
V
reaches its 2.56V clamp. At clamp, the primary-side
CMP
The dynamic nature of the clamped feedback amplifier
forms an effective track/hold type response, whereby the
MOSFET will turn off at the rated 100mV V
repeats on the next cycle.
level. This
SENSE
V
voltage changes during the flyback pulse, but is then
CMP
held during the subsequent switch-on portion of the next
cycle. This action naturally holds the V voltage stable
It is possible for the peak primary switch currents as
referred across R to exceed the max 100mV rating
CMP
SENSE
duringthecurrentcomparatorsenseaction(currentmode
because of the minimum switch on time blanking. If the
switching).
voltage on V exceeds 205mV after the minimum
SENSE
turn-on time, the SFST capacitor is discharged, causing
Application Note 19 provides a method for empirically
tweaking frequency compensation. Basically, it involves
introducing a load current step and monitoring the
response.
the discharge of the V capacitor. This then reduces
CMP
the peak current on the next cycle and will reduce overall
stress in the primary switch.
42691fb
32
LTC4269-1
APPLICATIONS INFORMATION
Short-Circuit Conditions
• The transformer secondary current flows through the
impedances of the winding resistance, synchronous
Loss of current limit is possible under certain conditions
such as an output short-circuit. If the duty cycle exhibited
by the minimum on-time is greater than the ratio of
secondary winding voltage (referred-to-primary) divided
by input voltage, then peak current is not controlled at
the nominal value. It ratchets up cycle-by-cycle to some
higher level. Expressed mathematically, the requirement
to maintain short-circuit control is
MOSFET R
and output capacitor ESR. The DC
DS(ON)
equivalent current for these errors is higher than the
load current because conduction occurs only during
the converter’s off-time. So, divide the load current by
(1 – DC).
Iftheoutputloadcurrentisrelativelyconstant,thefeedback
resistive divider is used to compensate for these losses.
Otherwise,usetheLTC4269-1loadcompensationcircuitry
(see Load Compensation). If multiple output windings are
used, theflybackwindingwillhaveasignalthatrepresents
an amalgamation of all these windings impedances. Take
carethatyouexamineworst-caseloadingconditionswhen
tweaking the voltages.
I • RSEC +RDS(ON)
(
)
SC
DCMIN = tON(MIN) • fOSC
where:
<
V •N
IN
SP
t
is the primary-side switch minimum on-time
ON(MIN)
I
is the short-circuit output current
SC
Power MOSFET Selection
N
is the secondary-to-primary turns ratio (N /N
)
SP
SEC PRI
ThepowerMOSFETsareselectedprimarilyonthecriteriaof
(other variables as previously defined)
on-resistanceR
,inputcapacitance,drain-to-source
DS(ON)
Trouble is typically encountered only in applications with
a relatively high product of input voltage times secondary
to primary turns ratio and/or a relatively long minimum
switchontime.Additionally,severalrealworldeffectssuch
astransformerleakageinductance,ACwindinglossesand
output switch voltage drop combine to make this simple
theoretical calculation a conservative estimate. Prudent
design evaluates the switcher for short-circuit protection
and adds any additional circuitry to prevent destruction.
breakdown voltage (BV ), maximum gate voltage (V )
DSS
GS
and maximum drain current (ID
).
(MAX)
For the primary-side power MOSFET, the peak current is:
P
XMIN
2
⎛
⎞
IN
IPK(PRI)
=
• 1+
⎜
⎟
⎠
⎝
V
IN(MIN) •DCMAX
where XMIN is peak-to-peak current ratio as defined
earlier.
For each secondary-side power MOSFET, the peak cur-
rent is:
Output Voltage Error Sources
The LTC4269-1’s feedback sensing introduces additional
minor sources of errors. The following is a summary list:
IOUT
1−DCMAX
XMIN
2
⎛
⎞
IPK(SEC)
=
• 1+
⎜
⎟
⎠
⎝
• Theinternalbandgapvoltagereferencesetsthereference
voltage for the feedback amplifier. The specifications
detail its variation.
Select a primary-side power MOSFET with a BVDSS
greater than:
• The external feedback resistive divider ratio directly
affects regulated voltage. Use 1% components.
• Leakage inductance on the transformer secondary
reduces the effective secondary-to-feedback winding
turns ratio (NS/NF) from its ideal value. This increases
the output voltage target by a similar percentage. Since
secondary leakage inductance is constant from part to
part (within a tolerance) adjust the feedback resistor
ratio to compensate.
VOUT(MAX)
LLKG
CP
BVDSS ≥IPK
+ V
+
IN(MAX)
NSP
where NSP reflects the turns ratio of that secondary-to
primary winding. LLKG is the primary-side leakage induc-
tanceandCPistheprimary-sidecapacitance(mostlyfrom
the drain capacitance (COSS) of the primary-side power
MOSFET). A clamp may be added to reduce the leakage
inductance as discussed.
42691fb
33
LTC4269-1
APPLICATIONS INFORMATION
Foreachsecondary-sidepowerMOSFET,theBV should
WithC
determined,calculatetheprimary-sidepower
DSS
MILLER
be greater than:
MOSFET power dissipation:
PD(PRI) =IRMS(PRI)2 •RDS(ON) 1+ δ +
BV
≥ V
+ V
• N
IN(MAX) SP
DSS
OUT
(
)
Choose the primary-side MOSFET R
gatedrivevoltage(7.5V).Thesecondary-sideMOSFETgate
drive voltage depends on the gate drive method.
at the nominal
DS(ON)
P
CMILLER
V
•
IN(MAX) •RDR
DCMIN
•
• fOSC
IN(MAX)
VGATE(MAX) − VTH
Primary-side power MOSFET RMS current is given by:
where:
P
R
is the gate driver resistance (≈10Ω)
is the MOSFET gate threshold voltage
is the operating frequency
IN
DR
IRMS(PRI)
=
V
DCMAX
IN(MIN)
V
TH
f
OSC
For each secondary-side power MOSFET RMS current is
given by:
V
= 7.5V for this part
GATE(MAX)
(1 + δ) is generally given for a MOSFET in the form of a
IOUT
1−DCMAX
IRMS(SEC)
=
normalized R
vs temperature curve. If you don’t
DS(ON)
have a curve, use δ = 0.005/°C • ΔT for low voltage
MOSFETs.
Calculate MOSFET power dissipation next. Because the
The secondary-side power MOSFETs typically operate
primary-side power MOSFET operates at high V , a
DS
MILLER
at substantially lower V , so you can neglect transition
transitionpowerlosstermisincludedforaccuracy.C
DS
losses. The dissipation is calculated using:
is the most critical parameter in determining the transition
loss, but is not directly specified on the data sheets.
2
P
= I
• R
(1 + δ)
DIS(SEC)
RMS(SEC)
DS(ON)
C
is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 16).
MILLER
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
T = T + P • θ
JA
J
A
DIS
MILLER EFFECT
V
GS
whereT istheambienttemperatureandθ istheMOSFET
A
JA
junction to ambient thermal resistance.
a
b
42691 F16
Q
Q
B
A
Once you have T iterate your calculations recomputing
J
GATE CHARGE (Q )
G
δ and power dissipations until convergence.
Figure 16. Gate Charge Curve
Gate Drive Node Consideration
The flat portion of the curve is the result of the Miller (gate
to-drain)capacitanceasthedrainvoltagedrops.TheMiller
capacitance is computed as:
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves efficiency,
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
QB −QA
CMILLER
=
VDS
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
The curve is done for a given V . The Miller capacitance
DS
for different V voltages are estimated by multiplying the
DS
MILLER
the curve specified V .
computed C
by the ratio of the application V to
DS
and poorer efficiency.
DS
42691fb
34
LTC4269-1
APPLICATIONS INFORMATION
TheLTC4269-1gatedriveswillclampthemaxgatevoltage
capacitor should have an RMS current rating greater
than:
to roughly 7.5V, so you can safely use MOSFETs with
maximum V of 10V and larger.
GS
DCMAX
IRMS(SEC) =IOUT
Synchronous Gate Drive
1−DCMAX
There are several different ways to drive the synchronous
gateMOSFET.Fullconverterisolationrequiresthesynchro-
nousgatedrivetobeisolated.Thisisusuallyaccomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary, as shown in the
application on the front page of this data sheet.
Continuing the example:
49.4%
1− 49.4%
IRMS(SEC) = 5.3A
= 5.24A
This is calculated for each output in a multiple winding
application.
However,otherschemesarepossible.Therearegatedrivers
and secondary-side synchronous controllers available
that provide the buffer function as well as additional
features.
ESRandESLalongwithbulkcapacitancedirectlyaffectthe
output voltage ripple. The waveforms for a typical flyback
converter are illustrated in Figure 17.
Capacitor Selection
I
PRI
PRIMARY
CURRENT
In a flyback converter, the input and output current flows
in pulses, placing severe demands on the input and output
filter capacitors. The input and output filter capacitors
are selected based on RMS current ratings and ripple
voltage.
I
PRI
N
SECONDARY
CURRENT
RINGING
DUE TO ESL
ΔV
COUT
Select an input capacitor with a ripple current rating
greater than:
OUTPUT VOLTAGE
RIPPLE WAVEFORM
ΔV
ESR
42691 F17
P
1−DCMAX
DCMAX
IN
IRMS(PRI)
=
Figure 17. Typical Flyback Converter Waveforms
V
IN(MIN)
The maximum acceptable ripple voltage (expressed as a
percentage of the output voltage) is used to establish a
starting point for the capacitor values. For the purpose
of simplicity, we will choose 2% for the maximum output
ripple, divided equally between the ESR step and the
charging/discharging ΔV. This percentage ripple changes,
dependingontherequirementsoftheapplication. Youcan
modify the following equations.
Continuing the example:
29.5W 1− 49.4%
IRMS(PRI)
=
= 0.728A
41V
49.4%
Keepinputcapacitorseriesresistance(ESR)andinductance
(ESL) small, as they affect electromagnetic interference
suppression. In some instances, high ESR can also
produce stability problems because flyback converters
exhibit a negative input resistance characteristic. Refer
to Application Note 19 for more information.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor is determined by:
VOUT • 1−DC
(
)
MAX
The output capacitor is sized to handle the ripple current
andtoensureacceptableoutputvoltageripple. Theoutput
ESRCOUT ≤1%•
IOUT
42691fb
35
LTC4269-1
APPLICATIONS INFORMATION
The other 1% is due to the bulk C component, so use:
IOUT
optimization of output ripple must be done on a dedicated
PC board. Parasitic inductance due to poor layout can
significantly impact ripple. Refer to the PC Board Layout
section for more details.
COUT
≥
1%• VOUT • fOSC
In many applications, the output capacitor is created from
multiple capacitors to achieve desired voltage ripple,
reliability and cost goals. For example, a low ESR ceramic
capacitor can minimize the ESR step, while an electrolytic
capacitor satisfies the required bulk C.
ELECTRO STATIC DISCHARGE AND SURGE
PROTECTION
The LTC4269-1 is specified to operate with an absolute
maximum voltage of –100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
Continuing our example, the output capacitor needs:
to the outside world (primarily V
and V
)
PORTN
PORTP
5V • 1− 49.4%
(
)
can routinely see peak voltages in excess of 10kV. To
protect the LTC4269-1, it is highly recommended that the
SMAJ58Aunidirectional58Vtransientvoltagesuppressor
be installed between the diode bridge and the LTC4269-1
(D3 in Figure 2).
ESRCOUT ≤1%•
5.3A
1%•5•200kHz
= 4mΩ
5.3A
COUT
≥
= 600µF
These electrical characteristics require paralleling several
low ESR capacitors possibly of mixed type.
ISOLATION
Onewaytoreducecostandimproveoutputrippleistousea
simple LC filter. Figure 18 shows an example of the filter.
The802.3standardrequiresEthernetportstobeelectrically
isolatedfromallotherconductorsthatareuseraccessible.
This includes the metal chassis, other connectors and
any auxiliary power connection. For PDs, there are two
common methods to meet the isolation requirement. If
there will be any user accessible connection to the PD,
then an isolated DC/DC converter is necessary to meet
the isolation requirements. If user connections can be
avoided, then it is possible to meet the safety requirement
by completely enclosing the PD in an insulated housing.
In all PD applications, there should be no user accessible
electricalconnectionstotheLTC4269-1orsupportcircuitry
other than the RJ-45 port.
L1, 0.1μH
V
OUT
FROM
SECONDARY
WINDING
+
+
C1
47μF
s3
C
C
OUT2
1μF
OUT
R
LOAD
470μF
42691 F18
Figure 18.
The design of the filter is beyond the scope of this data
sheet. However, as a starting point, use these general
guidelines. Start with a C
1/4 the size of the nonfilter
OUT
OUT
solution. Make C1 1/4 of C
to make the second filter
pole independent of C . C1 may be best implemented
OUT
with multiple ceramic capacitors. Make L1 smaller than
the output inductance of the transformer. In general, a
0.1μH filter inductor is sufficient. Add a small ceramic
LAYOUT CONSIDERATIONS FOR THE LTC4269-1
The LTC4269-1’s PD front end is relatively immune to
layout problems. Excessive parasitic capacitance on the
capacitor (C
) for high frequency noise on V . For
OUT2
OUT
R
CLASS
pin should be avoided. Include a PCB heat sink
those interested in more details refer to “Second-Stage
LC Filter Design,” Ridley, Switching Power Magazine, July
2000 p8-10.
to which the exposed pad on the bottom of the package
can be soldered. This heat sink should be electrically
connected to GND. For optimum thermal performance,
make the heat sink as large as possible. Voltages in a
PD can be as large as 57V for PoE applications, so high
voltage layout techniques should be employed. The SHDN
Circuit simulation is a way to optimize output capacitance
and filters, just make sure to include the component
parasitic. LTC SwitcherCADTM is a terrific free circuit
simulation tool that is available at www.linear.com. Final
SwitcherCAD is a trademark of Linear Technology Corporation.
42691fb
36
LTC4269-1
APPLICATIONS INFORMATION
pin should be separated from other high voltage pins, like
Keep electric field radiation low by minimizing the length
andareaoftraces(keepstraycapacitanceslow). Thedrain
of the primary-side MOSFET is the worst offender in this
category. Always use a ground plane under the switcher
circuitry to prevent coupling between PCB planes.
V
, V , to avoid the possibility of leakage currents
PORTP NEG
shutting down the LTC4269-1. If not used, tie SHDN to
V
V
.TheloadcapacitorconnectedbetweenV
and
PORTN
PORTP
of the LTC4269-1 can store significant energy when
NEG
fully charged. The design of a PD must ensure that this
energy is not inadvertently dissipated in the LTC4269-1.
Thepolarity-protectiondiodespreventanaccidentalshort
Check that the maximum BV
ratings of the MOSFETs
DSS
are not exceeded due to inductive ringing. This is done by
viewingtheMOSFETnodevoltageswithanoscilloscope.If
it is breaking down, either choose a higher voltage device,
add a snubber or specify an avalanche-rated MOSFET.
on the cable from causing damage. However if, V
PORTN
is shorted to V
inside the PD while capacitor C1
PORTP
is charged, current will flow through the parasitic body
diode of the internal MOSFET and may cause permanent
damage to the LTC4269-1.
Placethesmall-signalcomponentsawayfromhighfrequen-
cy switching nodes. This allows the use of a pseudo-Kelvin
connection for the signal ground, where high di/dt gate
drivercurrentsflowoutoftheICgroundpininonedirection
In order to minimize switching noise and improve output
load regulation, connect the GND pin of the LTC4269-1
(to the bottom plate of the V decoupling capacitor) and
CC
directly to the ground terminal of the V decoupling
CC
small-signal currents flow in the other direction.
capacitor,thebottomterminalofthecurrentsenseresistor
and the ground terminal of the input capacitor, using a
Keep the trace from the feedback divider tap to the FB pin
short to preclude inadvertent pick-up.
ground plane with multiple vias. Place the V capacitor
CC
immediately adjacent to the V and GND pins on the IC
CC
Forapplicationswithmultipleswitchingpowerconverters
connected to the same input supply, make sure that the
input filter capacitor for the LTC4269-1 is not shared with
other converters. AC input current from another converter
could cause substantial input voltage ripple which could
interferewiththeLTC4269-1operation. AfewinchesofPC
package. This capacitor carries high di/dt MOSFET gate
drive currents. Use a low ESR ceramic capacitor.
TakecareinPCBlayouttokeepthetracesthatconducthigh
switching currents short, wide and with minimal overall
loop area. These are typically the traces associated with
the switches. This reduces the parasitic inductance and
alsominimizesmagneticfieldradiation. Figure19outlines
the critical paths.
traceorwire(L≅100nH)betweentheC oftheLTC4269-1
IN
and the actual source V , is sufficient to prevent current
IN
sharing problems.
T1
V
CC
V
IN
•
•
C
VCC
GATE
TURN-ON
V
•
CC
PG
+
C
VIN
MP
OUT
GATE
TURN-OFF
+
R
SENSE
+
C
OUT
GATE
C
R
Q4
Q3
V
CC
TURN-ON
T2
V
MS
CC
SG
•
•
GATE
TURN-OFF
42691 F19
Figure 19. Layout Critical High Current Paths
42691fb
37
LTC4269-1
TYPICAL APPLICATIONS
42691fb
38
LTC4269-1
TYPICAL APPLICATIONS
PoE-Based 5V, 5A Power Supply
0.18μH
5V
T1
•
•
5A
+
C1
47μF
100μF
•
V
PORTP
10μH
+
48V AUXILLIARY
POWER
+
39k
–
150ꢀ
22pF
2.2μF
10μF
B1100 s 8 PLCS
107k
+
36V
BAS21
54V FROM
DATA PAIR
1μF
10μF
PDZ36B
10k
27.4k
20ꢀ
383k
BSS63LT1
5.1ꢀ
1.5nF
FDS8880
S1B
14.0k
BAS21
3.01k
FDS2582
33mꢀ
2.2nF
2kV
UVLO
PWRGD
FB
V
PG
SENSE
CC
+
V
PORTP
SHDN
–
R
CLASS
SENSE
MMBT3906 MMBT3904
SMAJ58A
LTC4269-1
30.9ꢀ
24k
54V FROM
SPARE PAIR
SG
0.1μF
100V
100ꢀ
1μF
V
PORTN
15ꢀ
2.2nF
V
V
SYNC GND
OSC PGDLY
33pF
t
ENDLY
R
C
CMP
NEG
ON
CMP
CMP
T2
•
•
T1: PCA ELECTRONICS, EPC3409G-LF
OR
PULSE, PA2369NL
0.1μF
100k
10k
3.3nF
BAT54
10k
12k
38.3k
1.2k
1nF
T2: PULSE, PE-68386NL
C1: PSLB20J107M(45)
42691 TA03a
Efficiency
Regulation
92
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
42V
PORT
90
88
86
84
82
80
78
76
74
72
50V
PORT
50V
PORT
42V
PORT
PORT
57V
57V
PORT
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
42691 TA03b
42691 TA03c
42691fb
39
LTC4269-1
TYPICAL APPLICATIONS
PoE-Based 12V, 2A Power Supply
T1
•
•
0.33μH
10μF
12V
2A
V
PORTP
10μH
+
+
C1
47μF
48V AUXILLIARY
POWER
•
+
20k
–
150ꢀ
47pF
2.2μF
10μF
B1100 s 8 PLCS
107k
+
36V
PDZ36B
BAS21
54V FROM
DATA PAIR
1μF
22μF
10k
29.4k
20ꢀ
383k
BSS63LT1
15ꢀ
470pF
FDS3572
S1B
14.0k
BAS21
3.01k
FDS2582
33mꢀ
2.2nF
2kV
UVLO
PWRGD
FB
PG
SENSE
V
CC
+
V
PORTP
SHDN
–
R
CLASS
SENSE
MMBT3906 MMBT3904
SMAJ58A
LTC4269-1
30.9ꢀ
24k
54V FROM
SPARE PAIR
SG
0.1μF
100V
100ꢀ
1μF
V
PORTN
15ꢀ
2.2nF
V
V
NEG
SYNC GND
OSC PGDLY
33pF
t
ENDLY
R
C
CMP
ON
CMP
CMP
T2
•
•
T1: PCA ELECTRONICS, EPC3410G-LF
OR
PULSE, PA2467NL
0.1μF
100k
10k
4.7nF
BAT54
10k
12k
38.3k
2.2k
1nF
T2: PULSE, PE-68386NL
C1: PSLDIC476MH
42691 TA04a
Efficiency
Regulation
93
91
89
12.5
12.4
12.3
12.2
12.1
12.0
11.9
11.8
11.7
11.6
11.5
57V
IN
42V
IN
87
85
83
81
79
77
75
73
50V
IN
48V
IN
42V
IN
57V
IN
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.2 0.38 0.56 0.74 0.92 1.1 1.3 1.5 1.6 1.8
LOAD CURRENT (A)
2
LOAD CURRENT (A)
42691 TA04b
42691 TA04c
42691fb
40
LTC4269-1
TYPICAL APPLICATIONS
PoE-Based 3.3V, 7A Power Supply
0.18μH
3.3V
T1
•
•
7A
+
C1
47μF
100μF
•
V
PORTP
10μH
+
48V AUXILLIARY
POWER
+
20k
–
150ꢀ
22pF
2.2μF
10μF
B1100 s 8 PLCS
107k
+
36V
BAS21
54V FROM
DATA PAIR
1μF
22μF
PDZ36B
10k
B0540W
29.4k
20ꢀ
383k
BSS63LT1
5.1ꢀ
2.2nF
FDS8670
S1B
14.0k
BAS21
3.01k
FDS2582
33mꢀ
47ꢀ
2.2nF
2kV
UVLO
PWRGD
FB
V
PG
SENSE
CC
+
V
PORTP
SHDN
–
R
CLASS
SENSE
MMBT3906 MMBT3904
SMAJ58A
LTC4269-1
30.9ꢀ
24k
54V FROM
SPARE PAIR
1μF
16V
SG
0.1μF
100V
100ꢀ
1μF
V
PORTN
15ꢀ
2.2nF
V
V
SYNC GND
OSC PGDLY
33pF
t
ENDLY
R
C
CMP
NEG
ON
CMP
CMP
T2
•
•
T1: PCA ELECTRONICS, EPC3408G-LF
OR
PULSE, PA2466NL
0.1μF
100k
5.1k
6.8nF
BAT54
10k
12k
38.3k
1k
2.2nF
T2: PULSE, PE-68386NL
C1: PSLB20J107M(25)
42691 TA05a
Efficiency
Regulation
91
90
89
88
87
86
85
3.45
3.42
3.39
3.36
3.33
3.30
3.27
3.24
3.21
3.18
3.15
37V
IN
50V
IN
42V
57V
48V
IN
IN
IN
57V
IN
84
83
82
81
0.7 1.4 2.1 2.8 3.5 4.2 4.9 5.6 6.3 7.0
0.7 1.4 2.1 2.8 3.5 4.2 4.9 5.6 6.3 7.0
LOAD CURRENT (A)
LOAD CURRENT (A)
42691 TA05b
42691 TA05c
42691fb
41
LTC4269-1
PACKAGE DESCRIPTION
DKD Package
32-Lead Plastic DFN (7mm × 4mm)
(Reference LTC DWG # 05-08-1734 Rev A)
0.70 0.05
4.50 0.05
6.43 0.05
2.65 0.05
3.10 0.05
PACKAGE
OUTLINE
0.20 0.05
0.40 BSC
6.00 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
7.00 0.10
17
32
R = 0.05
TYP
0.40 0.10
6.43 0.10
2.65 0.10
4.00 0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
16
1
0.20 0.05
0.40 BSC
6.00 REF
BOTTOM VIEW—EXPOSED PAD
0.75 0.05
(DKD32) QFN 0707 REV A
0.200 REF
NOTE:
0.00 – 0.05
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
42691fb
42
LTC4269-1
REVISION HISTORY (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
1, 39-41
B
04/10 Connected PWRGD Pin to UVLO Pin in Typical Application Circuit Drawings
Added Text Clarifying Connecting PWRGD Pin to UVLO Pin in Complementary Power Good Section of the
Applications Information Section
16, 17
42691fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
43
LTC4269-1
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT®1952
Single Switch Synchronous Forward Counter
Current Mode Flyback DC/DC Controller in ThinSOTTM
Synchronous Controller, Programmable Volt-Sec Clamp, Low Start Current
LTC3803-3
300kHz Constant-Frequency, Adjustable Slope Compensation, Optimized
for High Input Voltage Applications
LTC3805
LTC3825
Adjustable Frequency Current Mode Flyback Controller Slope Comp, Overcurrent Protect, Internal/External Clock
Isolated No-Opto Synchronous Flyback Controller with Adjustable Switching Frequency, Programmable Undervoltage Lockout,
Wide Input Supply Range
Accurate Regulation without Trim, Synchronous for High Efficiency
LTC4257-1
LTC4258
IEEE 802.3af PD Interface Controller
100V 400mA Internal Switch, Programmable Classification, Dual
Current Limit
Quad IEEE 802.3af Power over Ethernet Controller
Quad IEEE 802.3af Power over Ethernet Controller
Single IEEE 802.3af Power over Ethernet Controller
High Power Single PSE Controller
DC Disconnect Only, IEEE-Compliant PD Detection and Classification,
2
Autonomous Operation or I C Control
LTC4259A-1
LTC4263
AC or DC Disconnect, IEEE-Compliant PD Detection and Classification,
2
Autonomous Operation or I C Control
AC or DC Disconnect, IEEE-Compliant PD Detection and Classification,
Autonomous Operation
LTC4263-1
LTC4264
Internal Switch, Autonomous Operation, 30W
High Power PD Interface Controller with 750mA
Current Limit
750mA Internal Switch, Programmable Classification Current to 75mA.
Precision Dual Current Limit with Disable.
LTC4265
LTC4266
IEEE 802.3at High Power PD Interface Controller with
2-Event Classification
2-Event Classification Recognition, 100mA Inrush Current, Single-Class
Programming Resistor, Full Compliance to 802.3at
IEEE 802.3at Quad PSE Controller
Supports IEEE 802.3at Type 1 and Type 2 PDs, 0.34ꢀ Channel Resistance,
Advanced Power Management, High Reliability 4-Point PD Detection,
Legacy Capacitance Detect
LTC4267-1
LTC4267-3
LTC4268-1
LTC4269-2
IEEE 802.3af PD Interface with an Integrated
Switching Regulator
100V 400mA Internal Switch, Programmable Classification, 200kHz
Constant-Frequency PWM, Optimized for IEEE-Compliant PD System
IEEE 802.3af PD Interface with an Integrated
Switching Regulator
100V 400mA Internal Switch, Programmable Classification, 300kHz
Constant-Frequency PWM, Optimized for IEEE-Compliant PD System
High Power PD with Synchronous No-Opto Flyback
Controller
IEEE 802.3af Compliant, 750mA Hot Swap FET, 92% Power Supply
Efficiency, Flexible Aux Support, Superior EMI
IEEE 802.3af/IEEE 802.3at PD with Synchronous
Forward Controller
2-Event Classification Recognition, 94% Power Supply Efficiency, Flexible
Aux Support, Superior EMI, 100kHz to 500kHz
ThinSOT is a trademark of Linear Technology Corporation.
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LT 0410 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
44
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© LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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