LTC4310-1 [Linear]
Hot-Swappable I2C Isolators; 可热插拔的I2C隔离器
| 型号： | LTC4310-1 |
| 厂家： | 
Linear |
| 描述： | Hot-Swappable I2C Isolators |
| 文件： | 总20页 (文件大小：812K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4310-1/LTC4310-2
Hot-Swappable
2
I C Isolators
FeaTures
DescripTion
2
2
The LTC®4310 provides bidirectional I C communications
n
Bidirectional I C Communication Between Two
2
Isolated Buses
between two I C buses whose grounds are isolated from
2
n
Full Isolation with Inexpensive Ethernet
Transformers or Capacitors
one another. Each LTC4310 encodes I C bus logic states
intosignalsthataretransmittedacrossanisolationbarrier
to another LTC4310. The receiving LTC4310 decodes the
n
n
Low Voltage Level Shifting
2
2
I C Maximum Operating Frequency:
transmissionanddrivesitsl Cbustotheappropriatelogic
100kHz for LTC4310-1
state.Theisolationbarriercanbebridgedbyaninexpensive
Ethernet,orothertransformer,toachievecommunications
across voltage differences reaching thousands of volts, or
it can be bridged by capacitors for lower voltage isolation.
400kHz for LTC4310-2
2
n
n
n
n
n
n
n
n
I C Specification Compliant V , V
OL IL
±±kꢀ Human ꢁody ꢂodel ESD Protection
2
Rise Time Accelerators
The LTC4310-1 is intended for use in 100kHz I C systems.
The LTC4310-2 is intended for 400kHz I C systems.
2
SDA, SCL Hot-Swapping
ꢀery Low Shutdown Current
Rise time accelerators provide strong pull-up currents on
SCL and SDA rising edges to meet rise time specifications
for heavily loaded systems. Data and clock Hot Swap™
circuitry prevent data corruption when a card is inserted
into or removed from a live bus. When a bus is stuck low
for 37ms, the LTC4310 turns off its pull-down devices and
generatesuptosixteenclocksandaSTOPbitinanattempt
to free the bus. Driving EN low sets the LTC4310 in a very
low current shutdown mode to conserve power.
Stuck ꢁus Disconnect and Recovery
Thermal Shutdown
10-Lead ꢂSOP and 3mm × 3mm DFN Packages
applicaTions
2
n
Isolated I C, Sꢂꢁus and Pꢂꢁus Interfaces
n
Isolated Power Supplies
n
Positive-to-Negative Rail Communications
n
Power-over-Ethernet
L, LT, LTC, LTꢂ, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Typical applicaTion
LTC4310 Operating Through
20kV/µs Common Mode Transient
1500V Isolated I2C System
10/100Base-TX
ISOLATED
3.3V
ETHERNET TRANSFORMER
5V
0.01µF
0.01µF
3.3k
V
TXP
RXP
V
CC
CC
SCL
SDA
0V
2V/DIV
3.3k
3.3k
3.3k
0.01µF
LTC4310-1
LTC4310-1
500V/
DIV
SDA
SCL
TXN
RXP
RXN SDA
SDA1
SCL1
SDA2
SCL2
20kV/µs
0V
TXP
SCL
431012 TA01b
EN
EN
2µs/DIV
0.01µF
READY
READY
GND RXN
TXN GND
431012 TA01a
EPF8119S
431012f
ꢀ
LTC4310-1/LTC4310-2
absoluTe MaxiMuM raTings (Notes 1, 4)
Input Supply ꢀoltage (ꢀ ) .......................... –0.3ꢀ to 6ꢀ
Operating Ambient Temperature Range
CC
Input and ꢁidirectional Pin ꢀoltages
LTC4310C ................................................ 0°C to 70°C
LTC4310I.............................................. –40°C to 8±°C
Storage Temperature Range
SCL, SDA, EN, RXP, RXN.......................... –0.3ꢀ to 6ꢀ
Output ꢀoltages
ꢀ READY..................................................... –0.3ꢀ to 6ꢀ
DD ..................................................... –6±°C to 12±°C
ꢂS..................................................... –6±°C to 1±0°C
Lead Temperature (Soldering, 10 sec)
TXP, TXN ......................–0.3ꢀ to ꢀ + 0.3ꢀ (6ꢀ ꢂax)
CC
ꢂaximum Sink Current (SDA, SCL, READY)..........30mA
ꢂS Package...................................................... 300°C
pin conFiguraTion
TOP VIEW
TOP VIEW
EN
SDA
1
2
3
4
5
10 RXN
EN
SDA
1
2
3
4
5
10 RXN
9
8
7
6
RXP
11
GND
9
8
7
6
RXP
SCL
V
CC
SCL
V
CC
TXP
TXN
READY
GND
TXP
TXN
READY
GND
MS PACKAGE
10-LEAD PLASTIC MSOP
= 1±0°C, θ = 120°C/W
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
T
JꢂAX
JA
T
= 12±°C, θ = 43°C/W
JA
JꢂAX
EXPOSED PAD (PIN 11) PCꢁ CONNECTION TO GROUND IS OPTIONAL
orDer inForMaTion
LEAD FREE FINISH
LTC4310CDD-1#PꢁF
LTC4310IDD-1#PꢁF
LTC4310CꢂS-1#PꢁF
LTC4310IꢂS-1#PꢁF
LTC4310CDD-2#PꢁF
LTC4310IDD-2#PꢁF
LTC4310CꢂS-2#PꢁF
LTC4310IꢂS-2#PꢁF
TAPE AND REEL
PART MARKING*
LFCH
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC4310CDD-1#TRPꢁF
LTC4310IDD-1#TRPꢁF
LTC4310CꢂS-1#TRPꢁF
LTC4310IꢂS-1#TRPꢁF
LTC4310CDD-2#TRPꢁF
LTC4310IDD-2#TRPꢁF
LTC4310CꢂS-2#TRPꢁF
LTC4310IꢂS-2#TRPꢁF
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic ꢂSOP
LFCH
–40°C to 8±°C
0°C to 70°C
LTFCG
LTFCG
10-Lead Plastic ꢂSOP
–40°C to 8±°C
0°C to 70°C
LFCK
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic ꢂSOP
LFCK
–40°C to 8±°C
0°C to 70°C
LTFCJ
LTFCJ
10-Lead Plastic ꢂSOP
–40°C to 8±°C
Consult LTC ꢂarketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
431012f
ꢁ
LTC4310-1/LTC4310-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
ꢀ
Input Supply Range
3
±.±
ꢀ
CC
l
l
I
Input Supply Current, LTC4310-1
Input Supply Current, LTC4310-2
EN = ꢀ = ±.±ꢀ, SDA = SCL = ꢀ
6.±
7
8
8.±
mA
mA
CC
CC
SDA,SCL(OL)
SDA,SCL(OL)
EN = ꢀ = ±.±ꢀ, SDA = SCL = ꢀ
CC
l
l
I
Shutdown Input Supply Current
EN = 0ꢀ, ꢀ = ±.±ꢀ
0.1
2.4
±10
2.7
µA
ꢀ
CC(SD)
CC
ꢀ
Input Supply Undervoltage Lockout
Rising Threshold ꢀoltage
2.1
90
CCH(UꢀL)
l
ꢀ
Input Supply Undervoltage Lockout
Hysteresis
190
270
mꢀ
CC(UꢀL, HYST)
2
I C Interface
l
l
ꢀ
ꢀ
SDA, SCL Logic Low Output ꢀoltage
I
= 4mA, ±00µA; ꢀ = 3ꢀ, ±.±ꢀ
310
3±0
380
mꢀ
ꢀ
SDA,SCL(OL)
SDA,SCL(IL,R)
(SDA,SCL)
CC
SDA, SCL Controlled Rising Edge Rate
Turn-Off Threshold ꢀoltage
ꢀ
= 3ꢀ, ±.±ꢀ (Note ±)
0.3 • ꢀ
0.3± • ꢀ
0.4 • ꢀ
0.± • ꢀ
±±
CC
CC
CC
CC
l
l
ꢀ
SDA, SCL Logic Low Falling Input
Threshold ꢀoltage
ꢀ
= 3ꢀ
0.4 • ꢀ
0.4± • ꢀ
0
ꢀ
SDA,SCL(IL,F)
CC
CC
CC
CC
I
SDA, SCL Input Current
SCL, SDA = ꢀ = 0ꢀ, ±.±ꢀ
µA
SDA,SCL(OH)
CC
2
I C Interface Timing
l
l
dꢀ/dt
ꢁus Line Controlled Rising Edge Rate, 0.3±ꢀ < ꢀ
< 0.3± • ꢀ , ꢀ = 3ꢀ
0.8
1.±
1.16
2.14
1.4
2.6
ꢀ/µs
ꢀ/µs
RISE
ꢁUS
ꢁUS
CC CC
LTC4310-1
0.3±ꢀ < ꢀ
< 0.3± • ꢀ , ꢀ = ±.±ꢀ
CC CC
l
l
ꢁus Line Controlled Rising Edge Rate, 0.3±ꢀ < ꢀ
< 0.3± • ꢀ , ꢀ = 3ꢀ
2
3.9
3
±.4
3.9
6.9
ꢀ/µs
ꢀ/µs
ꢁUS
ꢁUS
CC CC
LTC4310-2
0.3±ꢀ < ꢀ
< 0.3± • ꢀ , ꢀ = ±.±ꢀ
CC CC
l
t
f
SDA, SCL High-to-Low Propagation
Delay
ꢀ
= ±.±ꢀ (Note 3)
CC
170
270
ns
PHL(SDA,SCL)
SCL(ꢂAX)
l
l
ꢂaximum SCL Clock Frequency
LTC4310-1
LTC4310-2
100
400
kHz
kHz
C
SCL, SDA Input Capacitance
SCL, SDA = ꢀ (Note 2)
10
pF
IN
CC
Rise Time Accelerators
l
l
ꢀ
SDA, SCL Rise Time Accelerator
Activation Threshold ꢀoltage
ꢀ
ꢀ
= 3ꢀ (Note ±)
= 3ꢀ
0.32 • ꢀ
2
0.4± • ꢀ
6
0.± • ꢀ
CC
ꢀ
ꢁOOST
CC
CC
CC
CC
I
SDA, SCL Rise Time Accelerator
Current
mA
ꢁOOST
READY Open-Drain Output
l
l
ꢀ
READY Output Low ꢀoltage
READY Off-Current
I
= 4mA
±0
400
±10
mꢀ
µA
READY(OL)
READY(OH)
READY
I
READY= ꢀ = ±.±ꢀ, EN = 0ꢀ
0.1
CC
Connection Control
l
l
l
l
l
l
ꢀ
ꢀ
EN Rising Threshold ꢀoltage
EN Falling Threshold ꢀoltage
EN Input Current
0.6 • ꢀ
0.3 • ꢀ
0.1
0.9 • ꢀ
CC
ꢀ
ꢀ
EN,RISE
EN,FALL
EN(OH)
CC
0.1 • ꢀ
CC
CC
I
t
t
t
EN = ꢀ = ±.±ꢀ
±10
1±±
µA
µs
µs
ms
CC
ꢁus Idle Time
7±
700
27
11±
IDLE
Start-Up Filter Time
900
1200
47
UꢀLO,EN_FILT
STUCK
SDA, SCL ꢁus Stuck Low Disconnect
37
431012f
ꢂ
LTC4310-1/LTC4310-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
t
ꢂaximum Time ꢁetween TXP, TXN
Transmit Events
0.8±
1.1±
1.4±
ms
ꢂAX(TX)
t
ꢂaximum Time ꢁetween RXP, RXN
Receive Events
3.4
4.6
±.8
ms
ꢂAX(RX)
Transmit Outputs
l
l
l
l
l
ꢀ
TXP, TXN Single-Ended Output Low
TXP, TXN Single-Ended Output High
TXP, TXN Output Rise Time
I
= 100µA, ꢀ = 3ꢀ
1.±
1.2±
1
±
1.±2
3
mꢀ
ꢀ
TX(OL)
SINK
CC
ꢀ
1±kΩ to GND on TXP, TXN; ꢀ = 3ꢀ, ±.±ꢀ
0.9±
31.±
TX(OH)
CC
t
t
t
C
C
ꢀ
, C
TXP TXN
= 20pF
= 20pF
ns
ns
ns
R(TX)
TXP, TXN Output Fall Time
, C
TXP TXN
1
3
F(TX)
TXP, TXN ꢂinimum Transmission
Pulse Width
= 3ꢀ, ±.±ꢀ
CC
3±
39
PWꢂIN(TX)
Receive Inputs
l
l
l
ꢀ
RXP, RXN Differential High Level
Threshold
RXP, RXN Pins; ꢀ = 3ꢀ, ±.±ꢀ
0.3
30
13
0.±
0.87±
ꢀ
ns
RX(TH)
CC
t
RXP, RXN ꢂinimum Received Pulse
Width
ꢀ
= 3ꢀ, ±.±ꢀ
CC
PWꢂIN(RX)
R
RXP, RXN Differential Input Resistance
16.±
20
kΩ
RX(IN)
Note 1: Stresses beyond those listed under Absolute ꢂaximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
ꢂaximum Rating condition for extended periods may affect device
reliability and lifetime.
receive a message on the RXP and RXN pins, plus the time the LTC4310
requires to process the message and pass the low to the data and clock
buffers, plus the time required by the buffers to drive their bus pins below
0.± • ꢀ .
CC
Note 2. Guaranteed by design, not tested in production.
Note 4. All currents into pins are positive, all voltages are referenced to
GND unless otherwise specified.
Note 5. Internal control circuitry prevents the rise time accelerators from
activating until the rising edge rate control circuitry is off.
Note 3. SDA, SCL high-to-low propagation delay is measured from the
beginning of a new received message telling the LTC4310 to drive its SDA,
SCL pins from high to low, to when the SDA, SCL lines have fallen below
0.± • ꢀ . It includes approximately 87ns required for an LTC4310 to
CC
431012f
ꢃ
LTC4310-1/LTC4310-2
Typical perForMance characTerisTics
SDA, SCL Controlled Rising Edge
Rate vs Temperature, LTC4310-1
ICC vs Temperature, LTC4310-1
5.0
4.8
4.6
4.4
4.2
4.0
2.0
1.8
1.6
1.4
1.2
SDA = 0V
SCL = V
V
= 5V
CC
V
= 5V
CC
CC
V
= 3.3V
CC
V
= 3.3V
50
CC
0
25
50
75 100 125
–50 –25
0
25
75 100 125
–50 –25
TEMPERATURE (°C)
TEMPERATURE (°C)
431012 G01
431012 G02
SDA, SCL Controlled Rising Edge
Rate vs Temperature, LTC4310-2
SDA, SCL Rise Time Accelerator
Pull-Up Current vs Temperature
5.5
5.0
4.5
4.0
3.5
3.0
2.5
11
10
9
V
= 5V
CC
V
= 5V
CC
8
7
V
= 3.3V
CC
V
= 3.3V
50
CC
6
5
0
25
50
75 100 125
–50 –25
0
25
75 100 125
–50 –25
TEMPERATURE (°C)
TEMPERATURE (°C)
431012 G03
431012 G04
SDA, SCL Rise Time Accelerator
Pull-Up Current vs Bus Capacitance
SDA,SCL Falling Propagation
Delay vs Temperature
12
10
8
220
200
180
160
140
120
0
T
= 25°C
A
V
= 5V
CC
V
= 3.3V
CC
6
V
= 3.3V
CC
V
= 5V
4
CC
2
0
200 300 400 500 600 700 800
0
25
50
75 100 125
0
100
–50 –25
BUS CAPACITANCE (pF)
TEMPERATURE (°C)
431012 G06
431012 G05
431012f
ꢄ
LTC4310-1/LTC4310-2
pin FuncTions
EN (Pin 1): Device Enable Input. Pulling EN up to ꢀ
sets the device in normal operation mode, allowing bus
information to be sent and received across the barrier.
Grounding EN disables communication across the bar-
rier and debiases all internal circuitry, setting the device
TXN (Pin 6): Negative Transmit Output. Tie TXN to the
negative side of the transformer primary winding or to the
RXN pin of another LTC4310 through a ceramic capacitor.
See the Applications Information section for guidance in
selecting the capacitor value. Do not leave open.
CC
in a very low current shutdown mode. Connect to ꢀ if
unused.
CC
TXP (Pin 7): Positive Transmit Output. Tie TXP to the
positive side of the transformer primary winding or to the
RXP pin of another LTC4310 through a ceramic capacitor.
See the Applications Information section for guidance in
selecting the capacitor value. Do not leave open.
SDA (Pin 2): Serial ꢁus Data Input/Output. This is the
bidirectional data line for the two-wire bus. An external
pull-up resistor or current source from SDA to a supply
voltagegreaterthanorequaltotheꢀ voltageisrequired.
CC
V
(Pin 8): Device Power Supply Input. Connect a by-
CC
See the Applications Information section for guidance
on selecting the resistor or current source value. Do not
leave open.
pass capacitor of at least 0.01µF directly between ꢀ
CC
and GND.
RXP (Pin 9): Positive Receive Input. Tie RXP to the posi-
tive side of the transformer secondary winding or to the
TXP pin of another LTC4310 through a ceramic capacitor.
See the Applications Information section for guidance in
selecting the capacitor value. Do not leave open.
SCL (Pin 3): Serial ꢁus Clock Input/Output. This is the
bidirectional clock line for the two-wire bus. An external
pull-up resistor or current source from SCL to a supply
voltagegreaterthanorequaltotheꢀ voltageisrequired.
CC
See the Applications Information section for guidance
on selecting the resistor or current source value. Do not
leave open.
RXN(Pin10):NegativeReceiveInput.TieRXNtothenega-
tive side of the transformer secondary winding or to the
TXN pin of another LTC4310 through a ceramic capacitor.
See the Applications Information section for guidance in
selecting the capacitor value. Do not leave open.
READY(Pin4):DeviceReceivingIndicatorOutput.READY
is an open-drain digital output that pulls low when the
LTC4310 is driving its SDA and SCL pins with the logic
state information it is receiving on its RXP and RXN pins.
Exposed Pad (Pin 11) DFN Package Only: The exposed
pad may be left open or connected to device ground.
Connect this pin to ꢀ with a 10k resistor. This pin can
CC
be left open or tied to GND if unused.
GND (Pin 5): Device Ground.
431012f
ꢅ
LTC4310-1/LTC4310-2
FuncTional DiagraM
0.45 • V
+
–
CC
LOGIC
1.25V
+
–
0.45 • V
0.35 • V
V
FALLING V
RISING V
CC
CC
TXP
7
CC
IL
8
I
BOOST
1.25V
+
–
IL
TXN
6
SDA
2
RX
0.35V
–
+
LOGIC
RISE RATE
LIMITER
dV/dt
0.5V
RXP
RISE
+
–
+
–
9
+
–
150µA
V
CC
–
+
0.45 • V
+
–
CC
RXN
LOGIC
10
+
–
I
0.5V
BOOST
RXP
RXN
STOP BIT
AND BUS IDLE
DETECTORS
+
–
0.45 • V
0.35 • V
FALLING V
RISING V
CC
CC
IL
SCL
3
+
–
IL
SCL
SDA
RX
STUCK BUS
TIMERS
0.35V
–
+
RISE RATE
LIMITER
dV/dt
RISE
+
–
READY
4
5
150µA
EN
1
GND
t
SD
UVLO
V
+
–
CC
2.4V/2.21V
POR CIRCUITRY
431012 FD
431012f
ꢆ
LTC4310-1/LTC4310-2
operaTion (LTC4310 refers to both LTC4310-1 and LTC4310-2)
The LTC4310 provides fully bidirectional communications
bus rise rate to dꢀ/dt
via the rise rate limiter circuitry.
RISE
2
between two I C or Sꢂꢁus buses whose grounds are
It also transmits a high to the other LTC4310. If the SDA
rise rate falls below the threshold, it is assumed that an-
other pull-down on the bus has turned on and is pulling
SDA low, and a command to pull the far side low is sent
across the isolation barrier.
isolated from one another. Clock stretching, clock syn-
chronization, arbitration and data acknowledging all work
seamlessly across the barrier, regardless of the locations
of the master(s) and slave(s).
Referring to the application circuit shown in Figure 1, an
LTC4310 is located on each side of the isolation barrier.
Each LTC4310 contains logic detection circuitry that can
differentiate externally driven SDA and SCL logic signals
from its own output signals. Each LTC4310 converts the
logic state of the externally driven signals into a sequence
ofpulsesthatarethentransmittedacrosstheisolationbar-
rierviaanEthernettransformer(orcouplingcapacitorsfor
low isolation voltage applications) to the other LTC4310.
Each LTC4310 also receives and decodes corresponding
pulses from the other LTC4310 and drives its SDA and
SCL pins accordingly.
When SDA rises above 0.3± • ꢀ , the rise rate limiter
CC
circuitryisdeactivated. WhenSDArisesabove0.4± • ꢀ ,
CC
the rise time accelerator current I
is activated, which
provides a strong, slew-limited pull-up current to reduce
ꢁOOST
system rise time.
The LTC4310 contains power-on reset (POR) circuitry that
sets the data and clock pins in a high impedance state and
deactivates the transmit and receive circuitry until the EN
voltage is high, the device is not in thermal shutdown
and the ꢀ voltage is above the 2.4ꢀ UꢀLO threshold
CC
voltage. The LTC4310 enters thermal shutdown when the
die temperature exceeds 1±0°C. Grounding EN sets the
LTC4310 in a near-zero current mode.
TransmissionsoccurontheTXPandTXNpinsinasequence
of 1.2±ꢀ pulses. The LTC4310 receives messages on its
RXP and RXN pins. Signals having less than ±00mꢀ dif-
ferential voltages are rejected to provide noise immunity
against common-mode transients.
AftertheLTC4310exitsPOR,STOPbitandbusidledetector
circuitry monitors the logic state of its own SDA and SCL
2
bus and of the other I C bus in the system via RXP and
RXN. When a STOP bit or bus idle occurs simultaneously
2
When the LTC4310 receives a message to drive SDA low,
it regulates SDA to 0.3±ꢀ. If an external device pulls SDA
below 0.3±ꢀ during this time, the LTC4310 detects this
condition and immediately transmits a LOW to the other
LTC4310.
on both I C buses, the LTC4310 activates its SDA and SCL
drivers, logicdetectioncircuitryandrisetimeaccelerators
and drives READY low.
The stuck bus timer and recovery circuitry disable the
SDA and SCL driver, logic detection circuitry and rise
time accelerators if the bus is low for 37ms. A stuck bus
also causes READY to be released high. If the stuck bus
When an external pull-down device drives SDA below
0.4± • ꢀ from a logic high, TXP and TXN transmit a
CC
2
message across the isolation barrier instructing the other
releases high, the I C driver and accelerator circuitry are
LTC4310 to drive its SDA line low.
reactivated when a STOP bit or bus idle occurs simultane-
2
ously on both I C buses, as previously described.
When the external pull-down device turns off and SDA is
rising between 0ꢀ and 0.3± • ꢀ , the LTC4310 limits the
CC
431012f
ꢇ
LTC4310-1/LTC4310-2
operaTion
IS0LATED
3.3V
5V
C1
10/100Base-TX
ETHERNET
TRANSFORMER
C4
R3
10k
R4
0.01µF
0.01µF
10k
READY
TXP
READY
RXP
1
16
15
R1
R2
R5
R6
7.5k 7.5k
7.5k 7.5k
LTC4310-1
LTC4310-1
C3
V
V
CC
CC
0.01µF
EN
EN
SDA
SCL
C
= 40pF
BUS
C
= 80pF
BUS
3
6
14
11
SDA
SCL
TXN
RXP
RXN
TXP
SCL1
SCL2
. . .
SLAVE#4
µP
SLAVE
SLAVE#1
7
C2
0.01µF
8
9
GND RXN
TXN GND
431012 F01
EPF8119S
Figure 1. The LTC4310-1 in a Transformer Isolated Application
431012f
ꢈ
LTC4310-1/LTC4310-2
applicaTions inForMaTion
SDA, SCL Bus Pull-Up Resistor Value Selection
When the SDA (or SCL) bus is rising between 0ꢀ and
reduce the bus rise time. When the bus has risen
above 0.4± • ꢀ , the LTC4310 turns on a strong,
CC
slew-limited pull-up current, I
, to help even
ꢁOOST
0.3± • ꢀ , the LTC4310 controls the bus rise rate to
CC
heavily loaded buses meet the rise time specifica-
tions. See the Typical Performance Characteris-
tics section for the rise time accelerator pull-up
current as a function of temperature and bus
capacitance. When either the bus has risen above
(0.3±•ꢀ )/900nsfortheLTC4310-1andto(0.3±•ꢀ )/
CC
CC
300ns for the LTC4310-2. Users must quantify their
parasitic bus capacitance, C , and choose a bus pull-
ꢁUS
up resistor, R , based on their bus pull-up supply
ꢁUS
voltage and maximum bus switching frequency to en-
sure that each bus rises faster than the controlled rise
rate. For bus frequencies up to 100kHz, choose the
LTC4310-1andrefertoFigure2forthemaximumpull-up
resistance to use. For bus frequencies between 100kHz
and 400kHz, choose the LTC4310-2 and refer to Figure 3
for the maximum pull-up resistance to use. ꢁe sure to
include worst-case resistor tolerance when selecting
resistor value.
(ꢀ – 1ꢀ) or 300ns after the pull-up current has
CC
turned on (whichever comes first), the LTC4310
deactivates its pull-up current to deter fighting
with the subsequent falling edge. Users must
ensure that the bus pull-up supply voltage ꢀ
≥
ꢁUS
ꢀ , so that the accelerators do not overdrive the
CC
SDA, SCL bus and source current into ꢀ . The rise
ꢁUS
time accelerators are deactivated during start-up,
thermal shutdown, shutdown and after disconnec-
tion due to a stuck bus or failure to receive a transmis-
sion within 4.6ms.
Rise Time Accelerators
The LTC4310’s rise time accelerator circuitry on the
SDA and SCL lines turns on during rising edges to
18
16
14
12
18
16
14
V
= 5V
CC
12
10
8
V
= 5V
CC
V
= 3.3V
CC
10
8
V
= 3.3V
CC
6
6
4
4
2
2
0
0
1
10
100
1000
1
10
100
1000
C
(pF)
C
(pF)
BUS(MAX)
BUS(MAX)
431012 F03
431012 F02
Figure 2. Maximum SDA,SCL Bus Pull-Up Resistor Value as a
Function of Parasitic Bus Capacitance for the LTC4310-1
Figure 3. Maximum SDA,SCL Bus Pull-Up Resistor Value as
a Function of Parasitic Bus Capacitance for the LTC4310-2
431012f
ꢀ0
LTC4310-1/LTC4310-2
applicaTions inForMaTion
Bus Rising Edge Waveform
Start-Up, Data and Clock Hot Swap Circuitry
The LTC4310 contains power-on reset (POR) circuitry that
sets the data and clock pins in a high impedance state and
deactivates the transmit circuitry until the EN voltage is
When all external pull-downs on SCL1 (Figure 1) turn off,
the SCL1 rising waveform will resemble that shown in
Figure 4. The LTC4310-1 senses that SCL1 is rising and
transmits a message to the other LTC4310-1 to release
SCL2 high. During the transmission, the first LTC4310-1
also drives SCL1 to 0.3±ꢀ, so that when the transmission
is complete, both buses will rise simultaneously from
high, the device is not in thermal shutdown and the ꢀ
CC
voltage is above 2.4ꢀ. After the LTC4310 exits the POR
state, it activates its transmit circuitry and communicates
its SDA, SCL logic states across the barrier to the other
LTC4310 via its TXP and TXN pins.
0.3±ꢀ at a rate of (0.3± • ꢀ )/900ns. This functionality
CC
minimizestheeffectiveskewbetweenthetwobuses.When
The receive circuitry remains deactivated for an additional
900µsaftertheLTC4310exitsPOR.The900µsfiltertimeis
required for the LTC4310 to charge its RXP and RXN pins
totheirDCbiasvoltage,assuminga0.01µFcommon-mode
noise filtering capacitor at the center-tap of the secondary
side of the external transformer. When the filter time has
elapsed, the LTC4310 activates its receive circuitry and
decodes the messages it receives on its RXP and RXN
SCL1 reaches 0.3± • ꢀ , the LTC4310-1 deactivates its
CC
rise rate regulation circuitry. The bus then rises with a
time constant of (R
at which point the I
• C ) until it reaches 0.4± • ꢀ ,
ꢁUS
ꢁUS CC
rise time accelerator pull-up
ꢁOOST
current is activated.
Figure ± shows SCL1 and SCL2 for an entire 100kHz
switchingcycle. ꢁecausetheLTC4310-1regulatesthebus
2
pins, registering the logic state of the remote I C bus.
rise rate to (0.3± • ꢀ )/900ns, the ±ꢀ bus signal rises
CC
Whenboththelocalandremotetwo-wirebusesare“quiet”
(i.e., no data transactions are occurring on either bus), the
LTC4310 then drives its READY pin low to indicate that it
more quickly than the 3.3ꢀ bus signal. ꢁoth buses reach
(0.3± • ꢀ ) in approximately 900ns, so the effective skew
CC
betweenthebusesisnearlyzero.TheLTC4310-2functions
the same as the LTC4310-1, except the controlled rise rate
2
has linked the logic state of the local I C bus with the logic
2
state of the remote I C bus. This means that the LTC4310
is limited to (0.3± • ꢀ )/300ns.
CC
will now drive its SDA and SCL pins to the logic state of the
2
remote I C bus, as specified by the messages it receives
on RXP and RXN. The LTC4310 considers a two-wire bus
SCL2
RISE TIME
ACCELERATOR
ACTIVE
SCL1
1V/DIV
1V/DIV
BUS RC
CC
SCL1 SET TO 0.35V
DURING TX
0.35 • V
dV/dt =
900 ns
431012 F04
431012 F05
200ns/DIV
2µs/DIV
Figure 5. 100kHz SCL Waveforms for
Application Circuit Shown in Figure 1
Figure 4. SCL1 Rising Waveform of SCL1
for Application Circuit Shown in Figure 1
431012f
ꢀꢀ
LTC4310-1/LTC4310-2
applicaTions inForMaTion
quiet if it has been idle high for at least 11±µs, or if a STOP
bit has occurred and both data and clock have remained
high since the STOP bit. This functionality makes the
LTC4310 ideal for hot-swapping cards into and out of a
pleted, the LTC4310 drives its SDA and SCL lines to the
logic state dictated by the decoded RXP and RXN signals.
The LTC4310 rejects RXP and RXN signals having less
than±00mꢀmagnitudetoprovidenoiseimmunityagainst
common-modetransients.Theparasiticcapacitancesofthe
LTC4310’s RXP and RXN pins and their associated board
traces form a capacitive divider with the transmit/receive
coupling capacitors, as shown in Figure 6. To guarantee
robustcommunications,minimizetheparasiticcapacitance
CPAR by minimizing the trace length from the coupling
capacitors to the RXP and RXN pins and choose coupling
capacitor values, CRXP and CRXN, that are at least ten
times larger than CPAR.
2
live I C system. The threshold voltages for the STOP bit
and bus idle comparators are 0.± • ꢀ .
CC
Stuck Bus Disconnect and Recovery
An internal timer runs whenever SDA, SCL or both are low.
The timer is only reset when both SDA and SCL are high. If
thetimerdoesnotresetwithin37ms,theLTC4310assumes
the bus is stuck low. Accordingly, it ceases driving its SDA
and SCL pins and transmits a special message across the
barrier to inform the other LTC4310. Upon receiving this
message, the other LTC4310 also ceases driving its SDA
and SCL pins. At least 40µs after determining the bus
is stuck low, the LTC4310 generates up to sixteen clock
cycles on SCL in an attempt to make the slave release
the SDA line. The LTC4310 stops issuing clocks when the
SDA line releases high, or after sixteen cycles, whichever
comes first. Once the clock pulses have completed, the
LTC4310 issues a STOP bit on SDA and SCL to reset all
devices on the bus.
CRXP
≥47pF
LTC4310
RXP
CPAR1
4.7pF
CRXN
≥47pF
RXN
CPAR2
4.7pF
GND
431012 F06
Figure 6. Parasitic Trace and Pin Capacitances
Form a Capacitive Divider with CRXP and CRXN
.
The LTC4310 reactivates its amplifiers and rise time ac-
celerators when the bus releases high and a STOP bit or
bus idle occurs on both the local and isolated buses, as
previously described in the Start-Up, Data and Clock Hot
Swap Circuitry section. The stuck bus disconnect and re-
covery circuitry is disabled when the LTC4310 is in UꢀLO,
thermal shutdown and low current shutdown.
Ensure CRXP, CRXN ≥ 10 • CPAR
If the LTC4310 has not received a message in 4.6ms, it
assumes there is a communication problem and ceases
driving its SDA and SCL pins. It also transmits a special
message to the other LTC4310 to inform it that it is no
longer driving its SDA and SCL bus. Upon receiving this
message,theotherLTC4310alsoceasesdrivingitsSDAand
SCL pins. Once the communication problem is resolved,
both LTC4310’s reactivate their amplifiers and rise time
accelerators after a STOP bit or bus idle has occurred on
both buses, as previously described in the Start-Up, Data
and Clock Hot Swap Circuitry section.
Transmit and Receive Circuitry
Transmissions occur on the TXP and TXN pins whenever
the externally driven SDA or SCL logic state changes – in
other words, transmissions are event driven. In addition,
if SDA and SCL do not change state for 1.1±ms, the
LTC4310retransmitsthelogicstate.TheTXPandTXNpins
are driven in a pseudo differential fashion. ꢁoth pins are
driven to ground when inactive and are driven to 1.2±ꢀ
(typical)inmatchedsetsofalternating3±nspulsestosend
information across the barrier to the other LTC4310.
Thermal Shutdown
If the die temperature of the LTC4310 exceeds 1±0°C, the
LTC4310 enters a thermal shutdown mode. It sets TXP
and TXN to a high impedance state, ceases driving SDA
and SCL, and ignores the signals on RXP and RXN. When
the temperature drops back below 130°C, the LTC4310
The LTC4310 receives and decodes the pulses sent by the
other LTC4310 on its RXP and RXN pins. Assuming the
start-up sequence previously described has been com-
goes through the POR sequence previously described.
431012f
ꢀꢁ
LTC4310-1/LTC4310-2
applicaTions inForMaTion
Once a STOP bit or bus idle occurs on both the local and
isolated buses, the LTC4310 reactivates its buffers and
rise time accelerators.
differ up to 1±00ꢀ. An EPF8119S Ethernet transformer is
used to bridge the isolation barrier. The left I C bus con-
2
nects to the LTC4310-1 and two other devices, resulting
in a bus parasitic capacitance of 40pF in this example
READY Digital Output
set-up. Referring to the ꢀ = 3.3ꢀ curve in Figure 2,
CC
7.±k pull-up resistors are chosen for R1 and R2. The right
The READY pin provides a digital output flag that pulls
low to indicate that the LTC4310 is driving its SDA and
SCL pins with the logic state information it is receiving on
its RXP and RXN pins from the other LTC4310. READY is
drivenbyanN-channelꢂOSFETopen-drainpull-downthat
is capable of sinking 4mA while holding 0.4ꢀ maximum.
The pull-down turns off whenever the LTC4310 is not
driving its SDA and SCL pins—during start-up, thermal
shutdown, low current shutdown and after disconnection
due to a stuck bus or failure to receive a transmission
within 4.6ms. Connect a resistor to the bus pull-up supply
to provide the pull-up.
2
I C bus connects to another LTC4310-1 and four slave
devices, resulting in a bus parasitic capacitance of 80pF.
Referring to the ꢀ = ±ꢀ curve in Figure 2, 7.±k pull-up
CC
resistors are also chosen for R± and R6. Standard ±%
resistors are used.
Sudden changes in the ground differential across the
isolation barrier can be effectively resisted by tying the
center tap of the receive side of the transformer to the
local ground through a 0.01µF capacitor, as shown by
capacitors C2 and C3.
Figure 7 shows the same application as Figure 1, but with
each LTC4310-1 replaced by an LTC4310-2, so that the
bus can switch at frequencies up to 400kHz. To meet the
requirements shown in the curves of Figure 3, R1 and R2
arechangedfrom7.±kto4.3k, andR±andR6arechanged
from 7.±k to 3.3k.
Design Example: High Voltage Isolation Using an
Inexpensive Ethernet Transformer
2
Figure 1 shows the LTC4310-1 providing I C communi-
cations between two buses whose ground voltages can
IS0LATED
5V
3.3V
10/100Base-TX
C1
C4
0.01µF
R3
10k
R4
ETHERNET
0.01µF
10k
TRANSFORMER
READY
TXP
READY
RXP
1
16
15
R1
R2
R5
R6
4.3k 4.3k
3.3k 3.3k
LTC4310-2
LTC4310-2
C3
0.01µF
V
EN
V
CC
CC
EN
SDA
SCL
C
= 40pF
BUS
C
= 80pF
BUS
3
6
14
11
SDA
SCL
TXN
RXP
RXN
TXP
SCL1
SCL2
. . .
SLAVE#4
µP
SLAVE
SLAVE#1
7
C2
0.01µF
8
9
GND RXN
TXN GND
431012 F07
EPF8119S
Figure 7. The LTC4310-2 in a 400kHz Application
431012f
ꢀꢂ
LTC4310-1/LTC4310-2
applicaTions inForMaTion
TYPICAL APPLICATIONS
2
municatewiththeisolatedI Cbus.ꢁecausetheLTC4310-1
contains a STOP bit and bus idle detection circuitry, there
is no danger of connecting in the middle of a message
when the microprocessor asynchronously reenables the
LTC4310-1.
2
Figure 8 shows the LTC4310-1 providing I C communica-
2
tionsbetweenanI Cbusreferencedtosystemgroundand
an I C bus using –±ꢀ for its ground reference. Ceramic
2
couplingcapacitors,C1-C±,areusedtobridgetheisolation
barrier. This circuit is recommended for ground isolation
voltageslessthan100ꢀandislimitedbythevoltagerating
of C1-C±. Higher voltage ceramic capacitors may be used
to achieve higher isolation voltages. ꢁecause the LTC4310
uses a pseudo-differential transmit scheme, capacitor C±
must be connected between ground and –±ꢀ to provide a
return path for the transmitted current.
Figure10showstheLTC4310-1inatwo-wirebusHotSwap
application. Using a staggered connector, make EN the
shortestlengthpintoensurethatthetransientsassociated
with hot swapping have settled before the LTC4310-1 can
be enabled. After connection is complete, a master on the
backplane may drive EN high to bring the LTC4310-1 out
of shutdown mode and into normal operation. Due to its
STOP bit and bus idle detection circuitry, the LTC4310-1’s
driver circuitry is not activated until transactions on both
buses are complete.
Figure 9 shows the LTC4310-1 in an application circuit
using its zero current shutdown mode. A microprocessor
only activates the left LTC4310-1 when it needs to com-
3.3V
C6
C7
0.01µF 0.01µF
–5V
R1
5.1k
R2
R3
R4
10k
R5
10k
R6
10k
C1
5.1k 10k
V
V
CC
CC
TXP
LTC4310-1
RXP
LTC4310-1
C2
C4
SDA
SCL
TXN
RXP
RXN
RXN
TXP
TXN
SDA
C
= 100pF
C
= 30pF
BUS
BUS
C3
SCL
READY
EN
READY
EN
GND
GND
C5
–5V
431012 F08
C1 TO C5 = 47pF, 100V
Figure 8. Low Voltage I2C Isolation Between a Ground Referenced Bus and a –5V Referenced Bus
431012f
ꢀꢃ
LTC4310-1/LTC4310-2
applicaTions inForMaTion
5V
C6
C7
0.01µF 0.01µF
–5V
R1
3.3k
R2
R3
R4
10k
R5
R6
3.3k 10k
C1
C2
C3
C4
5.1k
5.1k
V
V
CC
CC
TXP
LTC4310-1
RXP
LTC4310-1
EN
SDA
SCL
TXN
RXP
RXN
RXN
TXP
TXN
READY
C
= 200pF
C
= 150pF
BUS
BUS
SDA
SCL
µP
READY
EN
. . .
SLAVE#1
SLAVE#N
OFF ON
GND
GND
C5
–5V
431012 F09
C1 TO C5 = 47pF, 100V
Figure 9. The LTC4310-1 in a Zero Current Shutdown Application
BACKPLANE
CONNECTOR
CARD
CONNECTOR
I/O PERIPHERAL CARD
BACKPLANE
5V
3.3V
C6
C7
0.01µF 0.01µF
R1
2k
R2
2k
R3
10k
R4
R5
R6
C1
C2
C3
C4
6.8k 6.8k
10k
V
V
CC
CC
TXP
LTC4310-1
RXP
LTC4310-1
SDA
SCL
SDA
SCL
TXN
RXP
RXN
RXN
TXP
TXN
SDA
SDA2
SCL2
READY2
EN2
C
= 400pF
C
= 50pF
BUS
BUS
SCL
READY
EN
READY
EN
READY
EN
R7
100k
GND
GND
C5
431012 F10
C1 TO C5 = 47pF, 100V
Figure 10. The LTC4310-1 in an I2C Hot-Swapping Application
431012f
ꢀꢄ
LTC4310-1/LTC4310-2
applicaTions inForMaTion
LTC4310 Compatibility with Other LTC Bus Buffers
of Figure 2, and the bus pull-up resistors connected to the
LTC4310-2 meet the requirements of Figure 3. However,
the bus switching frequency is limited by the rise rate
regulationcircuitryoftheLTC4310-1.Inaddition,significant
skew is introduced on the rising edges due to the large
difference in the controlled rise rates of the two buses. For
this reason, it is recommended to use two LTC4310-1’s
2
The LTC4310 cannot be used on the same I C bus with the
LTC4300A-1, LTC4303 or LTC4307. During rising edges,
the rise time accelerators of these buffers turn on before
the LTC4310 disables its rise rate regulation circuitry,
resulting in nonmonotonic bus edges.
2
The LTC4310-1 is compatible with the LTC4301 and
LTC4301L.ItisalsocompatiblewiththeLTC4302,LTC4304,
LTC430±andLTC4306,providedthattherisetimeaccelera-
tors of these buffers are permanently disabled. All of the
previously mentioned buffers are incompatible with the
LTC4310-2 because the compensation networks of these
buffers cause the bus to rise more slowly than (0.3± •
in Sꢂꢁus and standard mode I C applications and to use
2
two LTC4310-2’s in fast mode I C applications.
2
The LTC4310-1 cannot be used on the same physical I C
bus with the LTC4310-2, because the LTC4310-1’s rise
rate regulation circuitry controls the bus rise rate to (0.3±
• ꢀ )/900ns, therefore the LTC4310-2 would not be able
CC
to control the bus rise rate.
ꢀ )/300ns, therefore the LTC4310-2 would not be able
CC
to control the bus rise rate.
Using the LTC4310-1 at Frequencies Above 100kHz
LTC4310-1 Compatibility with LTC4310-2
Userswhoimplementcustomtwo-wirebusesmayusethe
LTC4310-1atbusfrequenciesabove100kHzprovidedthat
all other devices on the bus can tolerate the approximately
1µsbusrisetimesresultingfromtheLTC4310-1’sbusrise
rate regulation circuitry.
In a typical application such as shown in Figure 1, an
LTC4310-1 can be used on one bus and an LTC4310-2 can
be used on the other, provided that the bus pull-up resis-
tors connected to the LTC4310-1 meet the requirements
431012f
ꢀꢅ
LTC4310-1/LTC4310-2
Typical applicaTions
Transformer Selection Guide
are inexpensive and work very well in this application for
isolation voltages up to 1±00ꢀ. For applications requiring
4000ꢀisolation,theWürthElectronicsꢂidcom749014012
transformer is recommended.
As shown in Figure 1, a transformer passes transmit and
receive signals between the two LTC4310’s. The transmit
signals have 1.2±ꢀ magnitude and 3±ns pulse width. The
receive circuitry has an equivalent input impedance of
16.±kΩ and can receive differential signals ranging from
0.87±ꢀ to 1.±±ꢀ. To meet these requirements, choose a
transformer having a magnetizing inductance ranging
from ±0µH to 3±0µH, a 1:1 turns ratio and a maximum
insertionlossof–1.±dꢁ. Foroptimalcommonmodenoise
rejection,chooseacenter-tappedtransformerandconnect
the center tap on the receiving side to local ground using a
0.01µF capacitor. Ringing at the LTC4310’s RXP and RXN
pins can effectively be damped by inserting ±0Ω series
resistors between each LTC4310’s TXP and TXN pins and
the corresponding transformer primary windings.
RF Radiated Emissions
The LTC4310 evaluation board passes CISPR22 Class ꢁ
requirements for radiated emissions. The results of
CISPR22testingareshownintheevaluationboardmanual.
To reduce radiated emission levels further, enclose the
LTC4310 application circuit in a shielded enclosure.
Common Mode Transient Immunity
The LTC4310 has high immunity to common mode tran-
sients. This is tested by applying a square voltage pulse
having very fast edges between the isolated grounds. The
LTC4310 passes 20kꢀ/us edges without corruption of the
Table1showsarecommendedlistoftransformers foruse
with the LTC4310. 10/100ꢁaseTX Ethernet transformers
2
I C bus logic states.
Table 1. LTC4310 Recommended Transformers
ISOLATION
FORM FACTOR (mm)
TURNS
RATIO
CENTER
TAP
OPERATING
MANUFACTURER
PART NUMBER
VOLTAGE
x
10.41
10.2
9.4
y
z
TEMPERATURE
PCA Electronics
EPF8119S
1±00ꢀ
1±00ꢀ
1±00ꢀ
1±00ꢀ
4000ꢀ
12.4±
12.7
±.84
±.96
±.08
±.33
10.8±
1:1
1:1
1:1
1:1
1:1
Yes
Yes
Yes
Yes
Yes
0°C TO 70°C
–40°C TO 8±°C
0°C TO 70°C
–40°C TO 8±°C
0°C TO 70°C
RꢂS
RꢂS
RꢂS
RꢂS
RꢂS
EPF8119SE
E±017
Pulse
12.7
Würth Electronics
ꢂidcom
000-7090-37R-LF1
749014012
9.4
12.9±
24.±±
17
431012f
ꢀꢆ
LTC4310-1/LTC4310-2
package DescripTion
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 0±-08-1699)
R = 0.115
TYP
6
0.38 0.10
10
0.675 0.05
3.50 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
PACKAGE
OUTLINE
TOP MARK
(SEE NOTE 6)
(DD) DFN 1103
5
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
0.25 0.05
0.50
BSC
2.38 0.10
(2 SIDES)
2.38 0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
431012f
ꢀꢇ
LTC4310-1/LTC4310-2
package DescripTion
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 0±-08-1661 Rev E)
0.889 0.ꢀꢁ7
(.035 .005)
5.ꢁ3
(.ꢁ0ꢂ)
MIN
3.ꢁ0 – 3.45
(.ꢀꢁꢂ – .ꢀ3ꢂ)
3.00 0.ꢀ0ꢁ
(.ꢀꢀ8 .004)
(NOTE 3)
(.0ꢀ97)
0.497 0.07ꢂ
(.0ꢀ9ꢂ .003)
REF
0.50
0.305 0.038
(.0ꢀꢁ0 .00ꢀ5)
TYP
ꢀ0 9
8
7 ꢂ
BSC
RECOMMENDED SOLDER PAD LAYOUT
3.00 0.ꢀ0ꢁ
(.ꢀꢀ8 .004)
(NOTE 4)
4.90 0.ꢀ5ꢁ
(.ꢀ93 .00ꢂ)
DETAIL “A”
0.ꢁ54
(.0ꢀ0)
0° – ꢂ° TYP
GAUGE PLANE
ꢀ
ꢁ
3
4 5
0.53 0.ꢀ5ꢁ
(.0ꢁꢀ .00ꢂ)
0.8ꢂ
(.034)
REF
ꢀ.ꢀ0
(.043)
MAX
DETAIL “A”
0.ꢀ8
(.007)
SEATING
PLANE
0.ꢀ7 – 0.ꢁ7
(.007 – .0ꢀꢀ)
TYP
0.ꢀ0ꢀꢂ 0.0508
(.004 .00ꢁ)
0.50
(.0ꢀ97)
BSC
MSOP (MS) 0307 REV E
NOTE:
ꢀ. DIMENSIONS IN MILLIMETER/(INCH)
ꢁ. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.ꢀ0ꢁmm (.004") MAX
431012f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢀꢈ
LTC4310-1/LTC4310-2
Typical applicaTion
Breaking Ground Loops Using Capacitors
3.3V
5V
C6
0.01µF
C7
0.01µF
R1
5.1k
R2
R3
R4
10k
R5
10k
R6
10k
5.1k 10k
C1
V
V
CC
CC
TXP
LTC4310-1
RXP
LTC4310-1
C2
C4
SDA
SCL
TXN
RXP
RXN
RXN
TXP
TXN
SDA
C
= 100pF
C
= 20pF
BUS
BUS
C3
SCL
READY
EN
READY
EN
GND
GND
C5
431012 TA02
C1 TO C5 = 47pF, 100V
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTC4300A-1/LTC4300A-2/ Hot-Swappable 2-Wire ꢁus ꢁuffers
LTC4300A-3
LTC4300A–1: ꢁus ꢁuffer with READY and ENAꢁLE,
LTC4300A–2: Dual Supply ꢁus ꢁuffer with ꢀ
LTC4300A–3: Dual Supply ꢁus ꢁuffer with ꢀ
and ACC,
CC2
CC2
and ENAꢁLE
LTC4301
Supply Independent Hot-Swappable 2-Wire
ꢁus ꢁuffer
Supply Independent
LTC4302-1/LTC4302-2
LTC4303/LTC4304
Addressable 2-Wire ꢁus ꢁuffer
Address Expansion, GPIO, Software Controlled
2
Hot-Swappable 2-Wire ꢁus ꢁuffer with Stuck
ꢁus Recovery
Provides Automatic Clocking to Free Stuck I C ꢁusses
LTC430±/LTC4306
LTC4307
2- or 4-Channel, 2-Wire ꢁus ꢂultiplexers
with Capacitance ꢁuffering
Two or Four Selectable Downstream ꢁusses, Stuck ꢁus Disconnect, Rise Time
Accelerators, Fault Reporting, ±10kꢀ Hꢁꢂ ESD Tolerance
Low Offset Hot-Swappable 2-Wire ꢁus ꢁuffer 60mꢀ ꢁuffer Offset, 30ms Stuck ꢁus Disconnect and Recovery, Rise Time
with Stuck ꢁus Recovery
Accelerators, ±±kꢀ Hꢁꢂ ESD Tolerance
LTC4307-1
LTC4308
High Definition ꢂultimedia Interface (HDꢂI)
Level Shifting
2-Wire ꢁus ꢁuffer, 60mꢀ ꢁuffer Offset, 3.3ꢀ to ±ꢀ Level Shifting, ±±kꢀ Hꢁꢂ
ESD Tolerance
Low ꢀoltage Level Shifting Hot-Swappable
2-Wire ꢁus ꢁuffer with Stuck ꢁus Recovery
–200mꢀ Offset In-Out/+300mꢀ Offset Out-In, 0.9ꢀ to ±.±ꢀ Level Shifting,
30ms Stuck ꢁus Disconnect and Recovery, Output Side Rise Time
Accelerators, ±6kꢀ Hꢁꢂ ESD Tolerance
LTC4309
LTC4311
Level Shifting Low Offset Hot-Swappable
2-Wire ꢁus ꢁuffer with Stuck ꢁus Recovery
60mꢀ ꢁuffer Offset, 30ms Stuck ꢁus Disconnect and Recovery, Rise Time
Accelerators, 1.8ꢀ to ±ꢀ Level Shifting, ±±kꢀ Hꢁꢂ ESD Tolerance
2
I C/Sꢂꢁus Rise Time Accelerator
Strong Slew Limited Current Source, Wide 1.6ꢀ to ±.±ꢀ Supply Range, Auto
Detect Low Power Standby, Low <±µA Supply Shutdown Current, ±8kꢀ Hꢁꢂ
ESD Tolerance
431012f
LT 0410 • PRINTED IN USA
Linear Technology Corporation
1630 ꢂcCarthy ꢁlvd., ꢂilpitas, CA 9±03±-7417
ꢁ0
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0±07 www.linear.com
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