LTC4313-3_技术文档

LTC4313-1/LTC4313-2/

LTC4313-3

2-Wire Bus Buffers with

High Noise Margin

FeaTures

DescripTion

n

Bidirectional Buffer Increases Fanout

The LTC^®4313 is a hot swappable 2-wire bus buffer

that provides bidirectional buffering while maintain-

ing a low offset voltage and high noise margin up to

n

High Noise Margin with V = 0.3•V

IL

CC

2

n

Compatible with Non-Compliant I C Devices That

0.3 • V . The high noise margin allows the LTC4313 to be

Drive a High V

CC

OL

interoperablewithdevicesthatdriveahighV (>0.4V)and

Strong (LTC4313-1) and 2.5mA (LTC4313-2)

OL

allows multiple LTC4313s to be cascaded. The LTC4313-1

andLTC4313-2supportleveltranslationbetween3.3Vand

5V busses. In addition to these voltages, the LTC4313-3

also supports level translation to 1.5V, 1.8V and 2.5V.

Rise Time Accelerator Current

n

Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses

Prevents SDA and SCL Corruption During Live Board

Insertion and Removal from Backplane

Stuck Bus Disconnect and Recovery

n

Duringinsertion,theSDAandSCLlinesarepre-chargedto

1Vtominimizebusdisturbances.Connectionisestablished

between the input and output after ENABLE is asserted

high and a stop bit or bus idle condition has been detected

on the SDA and SCL pins.

2

Compatible with I C, I C Fast Mode and SMBus

±4kV Human Body Model ESD Ruggedness

High Impedance SDA, SCL Pins When Unpowered

8-Lead MSOP and 8-Lead (3mm × 3mm) DFN

Packages

If both data and clock are not simultaneously high at least

once in 45ms, the input is disconnected from the output.

Up to 16 clock pulses are subsequently generated to free

thestuckbus.Risetimeaccelerators(RTAs)providepull-up

currents on SDA and SCL rising edges to meet rise time

specifications in heavily loaded systems. The RTAs are

configured as slew limited switches in the LTC4313-1 and

2.5mA current sources in the LTC4313-2. The LTC4313-3

does not have RTAs.

applicaTions

n

Capacitance Buffers/Bus Extender

n

Live Board Insertion

n

Telecommunications Systems Including ATCA

Level Translation

PMBus

Servers

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents, including 6356140, 6650174,

7032051, 7478286.

Typical applicaTion

400kHz Operation

3.3V

5V

R

= 2.7kΩ, C

BUS_OUT

= 50pF

BUS_IN

= 1.3kΩ, C

= 100pF

BUS_OUT

0.01µF

V

CC

2.7k 2.7k

10k 1.3k 1.3k

SCLOUT

ENABLE

LTC4313-1

SCLIN

READY

SCL2

SCL1

SDA1

SCLOUT

SDAOUT

SCLIN

SDAIN

SDA2

GND

4313123 TA01b

4313123 TA01a

500ns/DIV

4313123f

1

LTC4313-1/LTC4313-2/

LTC4313-3

absoluTe MaxiMuM raTings

(Notes 1, 2)

Supply Voltage V ...................................... –0.3V to 6V

Input Voltage ENABLE.................................. –0.3V to 6V

Input/Output Voltages SDAIN, SDAOUT,

SCLIN, SCLOUT ........................................... –0.3V to 6V

Output Voltage READY................................. –0.3V to 6V

Output Sink Current READY...................................50mA

Operating Ambient Temperature Range

CC

LTC4313C ................................................ 0°C to 70°C

LTC4313I.............................................. –40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

MS Package...................................................... 300°C

pin conFiguraTion

TOP VIEW

ENABLE

SCLOUT

SCLIN

GND

1

2

3

4

8

7

6

5

V

CC

ENABLE 1

SCLOUT 2

8 V

CC

SDAOUT

SDAIN

7 SDAOUT

6 SDAIN

5 READY

9

SCLIN

GND

3

4

READY

MS8 PACKAGE

8-LEAD PLASTIC MSOP

DD8 PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

T

= 150°C, θ = 163°C/W

JA

JMAX

T

= 150°C, θ = 39.7°C/W

JA

JMAX

EXPOSED PAD (PIN 9) PCB CONNECTION TO GND IS OPTIONAL

orDer inForMaTion

LEAD FREE FINISH

LTC4313CDD-1#PBF

LTC4313IDD-1#PBF

LTC4313CMS8-1#PBF

LTC4313IMS8-1#PBF

LTC4313CDD-2#PBF

LTC4313IDD-2#PBF

LTC4313CMS8-2#PBF

LTC4313IMS8-2#PBF

LTC4313CDD-3#PBF

LTC4313IDD-3#PBF

LTC4313CMS8-3#PBF

LTC4313IMS8-3#PBF

TAPE AND REEL

PART MARKING*

LFYZ

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC4313CDD-1#TRPBF

LTC4313IDD-1#TRPBF

8-Lead (3mm × 3mm) Plastic DFN

8-Lead Plastic MSOP

LFYZ

–40°C to 85°C

0°C to 70°C

LTC4313CMS8-1#TRPBF LTFYZ

LTC4313IMS8-1#TRPBF LTFYZ

8-Lead Plastic MSOP

–40°C to 85°C

0°C to 70°C

LTC4313CDD-2#TRPBF

LTC4313IDD-2#TRPBF

LFZB

8-Lead (3mm × 3mm) Plastic DFN

8-Lead Plastic MSOP

–40°C to 85°C

0°C to 70°C

LTC4313CMS8-2#TRPBF LTFZC

LTC4313IMS8-2#TRPBF LTFZC

8-Lead Plastic MSOP

–40°C to 85°C

0°C to 70°C

LTC4313CDD-3#TRPBF

LTC4313IDD-3#TRPBF

LGDD

8-Lead (3mm × 3mm) Plastic DFN

8-Lead Plastic MSOP

–40°C to 85°C

0°C to 70°C

LTC4313CMS8-3#TRPBF LTGDF

LTC4313IMS8-3#TRPBF LTGDF

8-Lead Plastic MSOP

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

4313123f

2

LTC4313-1/LTC4313-2/

LTC4313-3

elecTrical characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 3.3V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply/Start-Up

l

V

Input Supply Voltage

2-Wire Bus Supply Voltage

2.9

1.4

6

5.5

10

V

CC

LTC4313-1, LTC4313-2

LTC4313-3

DD,BUS

I

Input Supply Current

V

= V = 5.5V, V = 0V

SDAIN,SCLIN

8.1

mA

CC

ENABLE

CC

(Note 3)

l

V

= 0V, V = 5.5V,

SDAIN,SCLIN

2.5

3.5

4.5

mA

CC(DISABLED)

ENABLE

CC

= 0V

V

UVLO Threshold

V

Rising

CC

2.55

2.7

200

1

2.85

V

mV

V

TH_UVLO

CC_UVLO(HYST)

PRE

CC

UVLO Threshold Hysteresis Voltage

Precharge Voltage

l

SDA, SCL Pins Open

0.8

1.2

Buffers

l

V

Buffer Offset Voltage

I

= 4mA, Driven V = 50mV

SDA,SCL

100

15

50

190

60

120

60

0.33•V

50

280

120

180

115

0.36•V

mV

V

mV

µA

pF

OS(SAT)

OS

OL

= 500µA, Driven V

= 50mV

SDA,SCL

Buffer Offset Voltage

= 4mA, Driven V

= 200mV

SDA,SCL

= 500µA, Driven V

= 2.9V, 3.3V, 5.5V

= 200mV

15

SDA,SCL

Buffer Input Logic Low Voltage

V

0.3•V

IL, FALLING

CC

∆V

V

Hysteresis Voltage

IL

IL(HYST)

l

I

Input Leakage Current

Input Capacitance

SDA, SCL Pins = 5.5V, V = 5.5V, 0V

SDA, SCL Pins (Note 4)

10

LEAK

CC

C

IN

Rise Time Accelerators (LTC4313-1 and LTC4313-2 Only)

l

dV/dt

V

Minimum Slew Rate Requirement

SDA, SCL Pins, V = 5V

0.1

0.38•V

0.05•V

0.2

0.41•V

0.07•V

0.4

0.44•V

V/µs

V

mV

(RTA)

RTA(TH)

CC

Rise Time Accelerator DC Threshold Voltage

Buffers Off to Accelerator On Voltage

Rise Time Accelerator Pull-Up Current

V

CC

= 5V

CC

∆V

SDA, SCL Pins, V = 5V

ACC

CC

I

SDA, SCL Pins, V = 5V (Note 5)

RTA

CC

l

LTC4313-1

LTC4313-2

15

1.5

25

2.5

40

3.5

mA

Enable/Control

l

V

I

ENABLE Threshold Voltage

ENABLE Leakage Current

READY Output Low Voltage

READY Off Leakage Current

1

1.4

0.1

1.8

10

0.4

5

V

µA

V

EN(TH)

LEAK

V

= 5.5V

ENABLE

V

I

= 3mA, V = 5V

READY(OL)

READY CC

I

V

CC

= V

= 5V

0.1

45

µA

READY(OH)

READY

Stuck Low Timeout Circuitry

l

t

Bus Stuck Low Timer

35

55

ms

TIMEOUT

2

I C Interface Timing

2

f

t

I C Frequency Max

SCL, SDA Fall Delay

400

kHz

ns

SCL(MAX)

PDHL

V

= 5V, C

= 100pF,

130

95

250

300

175

CC

DD,BUS

BUS

R

= 10kΩ (Note 4)

BUS

t

SCL, SDA Fall Times

Bus Idle Time

V

= V

BUS

= 5V, C

BUS

20

55

ns

µs

f

CC

DD,BUS

R

= 10kΩ (Note 4)

l

IDLE

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive and all voltages are referenced to

GND unless otherwise indicated.

Note 4: Guaranteed by design and not tested.

Note 5: Measured in a special DC mode with V

= V

+ 1V.

RTA(TH)

SDA,SCL

The transient I

during rising edges for the LTC4313-1 will depend on

RTA

the bus loading condition and the slew rate of the bus. The LTC4313-1’s

internal slew rate control circuitry limits the maximum bus rise rate to

75V/µs by controlling the transient I

.

RTA

Note 3: Test performed with SDA, SCL buffers active.

4313123f

3

LTC4313-1/LTC4313-2/

LTC4313-3

Typical perForMance characTerisTics ^T_A^{= 25°C, V}_CC= 3.3V unless otherwise noted.

I_CCEnabled Current

vs Supply Voltage

I_CCDisabled Current

vs Supply Voltage

Buffer DC I_OLvs Temperature

9.0

8.5

8.0

7.5

7.0

6.5

6.0

4.0

3.5

3.0

2.5

2.0

12

11

10

9

V

= 0V

V

= 0V

SDAIN,SCLIN

ENABLE

= 5.5V

V

= 0V

ENABLE

V

= 0.6V

SDA,SCL

8

V

= 0.4V

SDA,SCL

7

6

5

4

2

2.5

3

3.5

4

4.5

5

5.5

6

2

2.5

3

3.5

4

4.5

5

5.5

6

–50

–25

0

25

50

75

100

V

(V)

V

(V)

CC

TEMPERATURE (°C)

CC

4313213 G01

4313213 G02

4313213 G03

V_OSvs I_BUSfor Different Driven

Voltage Levels

t_F(70% to 30%)

LTC4313-1 I_RTAvs Temperature

vs Bus Capacitance

100

75

50

25

0

250

200

150

100

50

16

14

12

10

8

V

C

= V

DD,BUS

V

= V

DD,BUS

BUS

CC

SDA,SCL

CC

= 0.6 • V

R

= 10kΩ

DD,BUS

DRIVEN V

= 50mV

100mV

SDA,SCL

= 400pF, R

= 10kΩ

BUS

5V

≥200mV

3.3V

0

6

0

200

400

C

600

(pF)

800

1000

0

1

2

3

(mA)

4

5

–50

–25

0

25

50

75

100

I

TEMPERATURE (°C)

BUS

4313213 G06

4313213 G04

4313213 G05

LTC4313-1 Bus Rise Time

(40% to 70%) vs C_BUS

t_PDHL(50% to 50%)

vs Bus Capacitance

200

175

150

125

100

V

= V

DD,BUS

CC

V

= V

DD,BUS

BUS

CC

R

= 10kΩ

5V

75

50

25

3.3V

600

0

200

400

(pF)

600

800

0

200

400

C

800

1000

(pF)

C

BUS

4313213 G07

4313123 G08

4313123f

4

LTC4313-1/LTC4313-2/

LTC4313-3

pin FuncTions

ENABLE (Pin 1): Connection Enable Input. When driven

low, the ENABLE pin isolates SDAIN and SCLIN from

SDAOUT and SCLOUT, asserts READY low, disables

rise time accelerators and inhibits automatic clock and

stop bit generation during a stuck low fault condition.

When driven high, the ENABLE pin connects SDAIN and

SCLIN to SDAOUT and SCLOUT after a stop bit or bus idle

has been detected on both busses. Driving ENABLE high

also enables automatic clock generation during a stuck

low fault condition. During a stuck low fault condition, a

risingedgeontheENABLEpinforcesaconnectionbetween

SDAIN and SDAOUT and SCLIN and SCLOUT. When using

the LTC4313 in a Hot Swap™ application with staggered

connector pins, connect a 10k resistor between ENABLE

GND (Pin 4): Device Ground.

READY (Pin 5): Connection Ready Status Output. This

open drain N-channel MOSFET output pulls low when

the input and output sides are disconnected. READY is

pulled high when ENABLE is high and a connection has

been established between the input and output. Connect

a pull-up resistor, typically 10k from this pin to the bus

pull-up supply. Leave open or tie to GND if unused.

SDAIN (Pin 6): Serial Bus 1 Data Input/Output. Connect

this pin to the SDA line on the upstream bus. Connect an

externalpull-upresistororcurrentsourcebetweenthispin

and the bus supply. The bus supply needs to be ≥ V for

CC

the LTC4313-1 and LTC4313-2, but not for the LTC4313-3.

Refer to the Applications Information section for more

details. Do not leave open.

and GND to ensure correct functionality. Connect to V

if unused.

CC

SDAOUT (Pin 7): Serial Bus 2 Data Input/Output. Connect

this pin to the SDA bus segment where stuck low recovery

is desired. Connect an external pull-up resistor or current

sourcebetweenthispinandthebussupply.Thebussupply

SCLOUT(Pin2):SerialBus2ClockInput/Output. Connect

this pin to the SCL bus segment where stuck low recovery

is desired. Connect an external pull-up resistor or current

sourcebetweenthispinandthebussupply.Thebussupply

needs to be ≥ V for the LTC4313-1 and LTC4313-2, but

CC

not for the LTC4313-3. Refer to the Applications Informa-

tion section for more details. Do not leave open.

not for the LTC4313-3. Refer to the Applications Informa-

tion section for more details. Do not leave open.

V

(Pin 8): Power Supply Voltage. Power this pin from

SCLIN (Pin 3): Serial Bus 1 Clock Input/Output. Connect

this pin to the SCL line on the upstream bus. Connect

an external pull-up resistor or current source between

this pin and the bus supply. The bus supply needs to be

CC

a supply between 2.9V and 5.5V. Bypass with at least

0.01µF to GND.

Exposed Pad (Pin 9, DD8 Package Only): Exposed pad

may be left open or connected to device GND.

≥ V for the LTC4313-1 and LTC4313-2, but not for the

CC

LTC4313-3. Refer to the Applications Information section

for more details. Do not leave open.

4313123f

5

LTC4313-1/LTC4313-2/

LTC4313-3

block DiagraM

*

200k

*

V

CC

V

CC

PRECHARGE

I

RTA

PRECHARGE

CONNECT

PRECHARGE

CONNECT

SCLIN

SCLOUT

SLEW RATE

DETECTOR

0.2V/µs

SLEW RATE

DETECTOR

0.2V/µs

*

V

*

CC

CONNECT

I

RTA

SDAIN

SDAOUT

SLEW RATE

DETECTOR

0.2V/µs

SLEW RATE

DETECTOR

0.2V/µs

RTA_SCLOUT_EN

RTA_SCLIN_EN

RTA_SDAIN_EN

2

I C Hot Swap

LOGIC

+

–

+

–

V

= 0.33 • V

IL

CC

V

= 0.33 • V

IL

CC

45ms

TIMER

+

–

+

–

V

= 0.33 • V

CC

RTA_SDAOUT_EN

V

CC

+

READY

GND

95µs

TIMER

UVLO

2.7V/2.5V

–

CONNECT

PRECHARGE

CONNECT

ENABLE

+

–

1.4V/1.3V

4313123 BD

*INSIDE DASHED BOX APPLIES ONLY TO THE LTC4313-1 AND LTC4313-2.

4313123f

6

LTC4313-1/LTC4313-2/

LTC4313-3

operaTion

The LTC4313 is a high noise margin bus buffer which

providescapacitancebufferingforI Csignals.Capacitance

precharge circuit. RTAs for the LTC4313-1 and LTC4313-2

are also enabled at this time.

2

buffering is achieved by using back to back buffers on

the clock and data channels which isolate the SDAIN

and SCLIN capacitances from the SDAOUT and SCLOUT

capacitances respectively. All SDA and SCL pins are fully

bidirectional.ThehighnoisemarginallowstheLTC4313to

When a SDA/SCL pin is driven below the V level, the

IL

buffers are turned on and the logic low level is propagated

though the LTC4313 to the other side. A high occurs when

alldevicesontheinputandoutputsidesreleasehigh.Once

the bus voltages rise above the V level, the buffers are

IL

2

operate with non-compliant I C devices that drive a high

turned off. The RTAs are turned on at a slightly higher volt-

V , permits a number of LTC4313s to be connected in

OL

age. The RTAs accelerate the rising edges of the SDA/SCL

2

series and improves the reliability of I C communications

inputs and outputs up to a voltage of 0.9•V , provided

CC

inlargenoisysystems.Risetimeaccelerator(RTA)pull-up

that the busses on their own are rising at a minimum rate

of 0.4V/µs as determined by the slew rate detectors. The

RTAs are configured to operate in a strong slew limited

switch mode in the LTC4313-1 and in the current source

mode in the LTC4313-2.

currents (I ) turn on during rising edges to reduce bus

RTA

rise time for the LTC4313-1 and LTC4313-2. In a typical

application the input and output busses are pulled up to

V

CC

although this is not a requirement. If V

is not

DD,BUS

CC

tied to V , V

must be greater than V to prevent

CC DD,BUS

The LTC4313 detects a bus stuck low (fault) condition

when both clock and data busses are not simultaneously

high at least once in 45ms. When a stuck bus occurs, the

LTC4313 disconnects the input and output sides and after

waiting at least 40µs, generates up to sixteen 5.5kHz clock

pulses on the SCLOUT pin and a stop bit to attempt to free

the stuck bus. Should the stuck bus release high during

this period, automatic clock generation is terminated.

overdrive of the bus by the RTAs for the LTC4313-1 and

LTC4313-2. See the Applications Information section for

V

requirements for the LTC4313-3.

DD,BUS

When the LTC4313 first receives power on its V pin, it

CC

starts out in an undervoltage lockout mode (UVLO) until

its V exceeds 2.7V. The buffers and RTAs are disabled

CC

and the LTC4313 ignores the logic state of its clock and

data pins. During this time the precharge circuit forces a

nominal voltage of 1V on the SDA and SCL pins through

200k resistors.

Once the stuck bus recovers, connection is re-established

between the input and output after a stop bit or bus idle

conditionisdetected. TogglingENABLEafterafaultcondi-

tion has occurred forces a connection between the input

andoutput. Whenpoweringintoastucklowcondition, the

input and output sides remain disconnected even after the

LTC4313 has exited the UVLO mode as a stop bit or bus

idle condition is not detected on the stuck busses. After

the timeout period, a stuck low fault condition is detected

and the behavior is as described previously.

Once the LTC4313 exits UVLO and its ENABLE pin has

been asserted high, it monitors the clock and data pins

for a stop bit or a bus idle condition. When a combination

of either condition is detected simultaneously on the input

and output sides, the LTC4313 activates the connection

between SDAIN and SDAOUT, and SCLIN and SCLOUT,

respectively, asserts READY high and deactivates the

4313123f

7

LTC4313-1/LTC4313-2/

LTC4313-3

applicaTions inForMaTion

The LTC4313 provides capacitance buffering, data and

of 75V/µs. The current is therefore directly proportional

to the bus capacitance. The LTC4313-1 RTA is capable of

sourcing up to 40mA of current. Rise time acceleration

for the LTC4313-2 is provided by a 2.5mA current source.

clock Hot Swap capability and level translation. The high

noise margin of the LTC4313 permits interoperability with

2

I C devices that drive a high V permits series connec-

OL

2

tion of multiple LTC4313s and improves I C communica-

Figures 1 and 2 show the rising waveforms of heavily

loadedSDAINandSDAOUTbussesfortheLTC4313-1and

LTC4313-2 respectively. In both figures, during a rising

edge, the buffers are active and the input and output sides

are connected, until the bus voltages on both the input

tion reliability. The LTC4313 isolates backplane and card

capacitances and provides slew control of falling edges

whileleveltranslating3.3Vand5Vbusses.TheLTC4313-1

and LTC4313-2 also provide pull-up currents to accelerate

risingedges. Thesefeaturesareillustratedinthefollowing

subsections.

and output sides are greater than 0.3 • V . When each

CC

individual bus voltage rises above 0.41 • V , the RTA on

CC

that bus turns on. The effect of the acceleration strength

is shown in the waveforms in Figures 1 and 2 for identi-

cal bus loads. The RTAs of the LTC4313-1 and LTC4313-2

supply10mAand2.5mAofpull-upcurrentrespectivelyfor

the bus conditions shown in Figures 1 and 2. For identical

bus loads, the bus rises faster in Figure 1 compared to

Rise Time Accelerator (RTA) Pull-Up Current Strength

(LTC4313-1 and LTC4313-2)

Afteraninputandoutputconnectionhasbeenestablished,

the RTAs on both the input and output sides of the SDA

and SCL busses are activated. During positive bus transi-

tions of at least 0.4V/µs, the RTAs provide pull-up cur-

rents to reduce rise time. The RTAs allow users to choose

larger bus pull-up resistors to reduce power consumption

and improve logic low noise margins, design with bus

Figure 2 because of the higher I

.

RTA

The RTAs are internally disabled during power-up and dur-

ing a bus stuck low event. The RTAs when activated pull

the bus up to 0.9•V on the input and output sides of the

2

CC

capacitances outside of the I C specification or to oper-

SDA and SCL pins. In order to prevent bus overdrive by

ate at a higher clock frequency. The LTC4313-1 regulates

its RTA current to limit the bus rise rate to a maximum

the RTA, the bus supplies on the input and output sides

SDAOUT

SDAIN

2V/DIV

V

= V

= 5V

V

= V

= 5V

DD,BUS

CC

DD,BUS

CC

R

= 20k

R

= 20k

BUS

C

= C

= 200pF

C

= C = 200pF

OUT

IN

OUT

IN

4313123 F01

4313123 F02

1µs/DIV

Figure 1. Bus Rising Edge for the LTC4313-1. V_CC= V_DD,BUS= 5V

Figure 2. Bus Rising Edge for the LTC4313-2. V_CC= V_DD,BUS= 5V

4313123f

8

LTC4313-1/LTC4313-2/

LTC4313-3

applicaTions inForMaTion

of the LTC4313-1 and LTC4313-2 must be greater than

Input to Output Offset Voltage

or equal to 0.9•V . An example is shown in Figure 3

CC

While propagating a logic low voltage on its SDA and SCL

pins, the LTC4313 introduces a positive offset voltage

between the input and output. When a logic low voltage

≥200mV is driven on any of the LTC4313’s clock or data

pins, the LTC4313 regulates the voltage on the opposite

side to a slightly higher value. This is illustrated in Equa-

tion 3, which uses SDA as an example:

where the input bus voltage is greater than V . During a

CC

rising edge, the input bus rise rate will be accelerated by

the RTA up to a voltage of 2.97V after which the bus rise

rate will reduce to a value that is determined by the bus

current and bus capacitance. The RTA turn-off voltage is

less than the bus supply and the bus is not overdriven.

Pull-Up Resistor Value Selection

V_DD,BUS

To guarantee that the RTAs are activated during a rising

edge, the bus mustrise on its own with a positive slew rate

of at least 0.4V/µs. To achieve this, choose a maximum

V_SDAOUT= V_SDAIN+ 50mV + 15Ω •

(3)

R_BUS

In Equation 3, V

is the output bus supply voltage

DD,BUS

R

BUS

using the formula:

and R

is the SDAOUT bus pull-up resistance.

BUS

V

− V

RTA(TH)

(

)

For driven logic low voltages < 200mV Equation 3 does

not apply as the saturation voltage of the open collector

outputtransistorresultsinahigheroffset.Foradriveninput

logic low voltage below 220mV, the output is guaranteed

DD,BUS(MIN)

R

≤

BUS

V

(1)

0.4 • C

BUS

µs

R

is the pull-up resistor, V

is the minimum

DD,BUS(MIN)

BUS

to be below a V of 400mV for bus pull-up currents up to

OL

buspull-upsupplyvoltage,V

isthevoltageatwhich

RTA(TH)

4mA. See the Typical Performance Characteristicssection

for offset variation as a function of the driven logic low

voltage and bus pull-up current.

the RTA turns on and C

is the equivalent bus capaci-

BUS

tance. R

must also be large enough to guarantee that:

BUS

V

− 0.4V

(

)

DD,BUS(MAX)

R_BUS

≥

(2)

4mA

This criterion ensures that the maximum bus current is

less than 4mA.

5V

3.3V

C1

0.01µF

V

CC

R1

R2

R3

R4

R5

10k 10k

10k 10k 10k

LTC4313-1

ENABLE

READY

SCLOUT

SDAOUT

READY

SCL2

SCL1

SDA1

SCLIN

SDAIN

SDA2

GND

4313123 F03

Figure 3. Level Shift Application Where the SDAIN and SCLIN Bus Pull-Up

Supply Voltage Is Higher Than the Supply Voltage of the LTC4313

4313123f

9

LTC4313-1/LTC4313-2/

LTC4313-3

applicaTions inForMaTion

Falling Edge Characteristics

40µs the LTC4313 generates up to sixteen 5.5KHz clock

pulses on the SCLOUT pin. Should the stuck bus release

high during this period, clock generation is stopped and

a stop bit is generated. This process is shown in Figure 4

for the case where SDAOUT starts out stuck low and

then recovers. As seen from Figure 4, the LTC4313 pulls

READY low and breaks the connection between the input

and output sides, when a stuck low condition on SDA is

detected. Clock pulses are then issued on SCLOUT to at-

tempttounsticktheSDAOUTbus.WhenSDAOUTrecovers,

clock pulsing is stopped, a stop bit is generated on the

output and READY is released high. When powering up

into a stuck low condition, a connection is never made

between the input and the output, as a stop bit or bus

idle condition is never detected. After a timeout period of

45ms, the behavior is the same as described previously.

The LTC4313 introduces a propagation delay on falling

edges due to the finite response time and the finite current

sink capability of the buffers. In addition the LTC4313 also

slew limits the falling edge to an edge rate of 45V/µs (typ).

The slew limited falling edge eliminates fast transitions

on the busses and minimizes transmission line effects in

systems. RefertotheTypicalPerformanceCharacteristics

section for the propagation delay and fall times as a func-

tion of the bus capacitance.

Stuck Bus Disconnect and Recovery

During an output bus stuck low condition (SCLOUT and

SDAOUT have not been simultaneously high at least once

in 45ms), the LTC4313 attempts to unstick the bus by first

breakingtheconnectionbetweentheinputandoutput.After

READY

5V/DIV

AUTOMATIC CLOCKING

SCLOUT

5V/DIV

DISCONNECT

AT TIMEOUT

SDAIN

5V/DIV

RECOVERS HIGH

DRIVEN LOW

STOP BIT GENERATED

STUCK LOW > 45ms

SDAOUT

5V/DIV

4313123 F04

1ms/DIV

Figure 4. Bus Waveforms During SDAOUT

Stuck Low and Recovery Event

4313123f

10

LTC4313-1/LTC4313-2/

LTC4313-3

applicaTions inForMaTion

Live Insertion and Capacitance Buffering Application

ditionaltimefortransientsassociatedwithliveinsertionto

settle before the LTC4313 can be enabled. A 10k or lower

pull-downresistorfromENABLEtoGNDisrecommended.

Figure5illustratesanapplicationoftheLTC4313thattakes

advantage of the LTC4313’s Hot Swap, capacitance buffer-

ing and precharge features. If the I/O cards were plugged

directly into the backplane without LTC4313 buffers, all of

the backplane and card capacitances would directly add

together, making rise time requirements difficult to meet.

Placing an LTC4313 on the edge of each card isolates the

card capacitance from the backplane. For a given I/O card,

the LTC4313 drives the capacitance of everything on the

card and the devices on backplane must drive only the

small capacitance of the LTC4313 which is < 10pF.

If a connector is used where all pins are of equal length,

the benefit of the precharge circuit is lost. Also, the

ENABLE signal to the LTC4313 must be held low until all

the transients associated with card insertion into a live

system die out.

Level Translating to Voltages < 2.9V (LTC4313-3 Only)

The LTC4313-3 can be used for level translation to bus

voltages below 2.9V. Since the maximum buffer turn-on

and turn-off voltages are 0.36•V , the minimum bus

In Figure 5 a staggered connector is used to connect the

CC

supply voltage is determined by the following equation,

LTC4313 to the backplane. V and GND are the longest

CC

pins to ensure that the LTC4313 is powered and forcing

a 1V precharge voltage on the medium length SDA and

SCL pins before they contact the backplane. The 1V pre-

charge voltage is applied to the SDA and SCL pins through

200k resistors. Since cards are being plugged into a live

backplane whose SDA and SCL busses could be at any

0.36 • V_CC

V_DD,BUS(MIN)

≥

(4)

0.7

in order to meet the V = 0.7 • V

requirement and

DD,BUS

IH

not impact the high side noise margin. Users willing to live

with a lower logic high noise margin can level translate

down to 1.4V. An example of voltage level translation from

3.3V to 1.8V is illustrated in Figure 6, where a 3.3V input

voltage bus is translated to a 1.8V output voltage bus.

voltage between 0 and V , precharging the LTC4313’s

CC

SDA and SCL pins to 1V minimizes disturbances to the

backplane bus when cards are being plugged in. The low

(<10pF)inputcapacitanceoftheLTC4313alsocontributes

to minimizing bus disturbance as cards are being plugged

in. With ENABLE being the shortest pin and also pulled to

GND by a resistor, the staggered approach provides ad-

Tying V to 3.3V satisfies Equation 4. A similar voltage

CC

translation can also be performed going from a 3.3V bus

supply on the output side to a 1.8V input if the V pin of

CC

the LTC4313-3 is tied to the 3.3V output supply.

4313123f

11

LTC4313-1/LTC4313-2/

LTC4313-3

applicaTions inForMaTion

BACKPLANE

CARD

CONNECTOR CONNECTOR

I/O PERIPHERAL CARD 1

5V

C1

0.01µF

3.3V

C2

0.01µF

V

CC

R1

10k

R2

R3

R4

R5

10k 10k

LTC4313

READY

SCLIN

READY

SCL

CARD 1_SCL

CARD 1_SDA

SCLOUT

SDAOUT

SDAIN

ENABLE

SDA

ENABLE 1

R6

10k

GND

I/O PERIPHERAL CARD N

C3

0.01µF

C4

0.01µF

V

CC

R7

R8

10k 10k

LTC4313

READY

SCLIN

SCLOUT

SDAOUT

CARD N_SCL

CARD N_SDA

SDAIN

ENABLE

ENABLE N

R9

10k

GND

4313123 F05

Figure 5. LTC4313 in an I²C Hot Swap Application with a Staggered Connector

3.3V

1.8V

C1

0.01µF

R1

R2

R3

R4

R5

V

CC

10k 10k

10k 10k 10k

LTC4313-3

ENABLE

READY

SCLOUT

SDAOUT

READY

SCL2

SCLIN

SDAIN

SCL1

SDA1

SDA2

GND

4313123 F06

Figure 6. Voltage Level Translation from

3.3V to 1.8V Using the LTC4313-3

4313123f

12

LTC4313-1/LTC4313-2/

LTC4313-3

applicaTions inForMaTion

Telecommunications Systems

it is unpowered, minimize disturbances to the bus when

cards are being hot swapped. In Figure 7, the RTA of the

LTC4313-2 on the shelf manager supplies sufficient pull-

up current, allowing the 1µs rise time requirement to be

met on the heavily loaded backplane for loads well beyond

The LTC4313 has several features that make it an excellent

choiceforuseintelecommunicationsystemssuchasATCA.

ReferringtoFigures7and8, buffersareusedontheedges

of the field replaceable units (FRU) and shelf managers to

shield devices on these cards from the large backplane

capacitance. The input capacitance of the LTC4313 is less

than the 10pF maximum specification for buffers used in

bussed ATCA applications. The LTC4313 buffers can drive

capacitances >1nF, which is greater than the maximum

backplane capacitance of 690pF in bussed ATCA systems.

The precharge feature, low input capacitance and high

impedance of the SDA and SCL pins of the LTC4313 when

the 690pF maximum specification. The 0.33 • V turn-off

CC

voltage of the LTC4313’s buffers provides a large logic

low noise margin in these systems. In the bussed ATCA

application shown in Figure 7, the LTC4313s located on

the shelf managers #1 and #2 and on the FRUs, drive the

large backplane capacitance while the microcontrollers

2

on the shelf managers and the I C slave devices on the

FRUs drive the small input capacitance of the LTC4313-3.

FRU #1

SHELF MANAGER #1

BACKPLANE

3.3V

V

CC

R3

10k

R4

10k

R2

2.7k

R1

10k

IPMB-A

SCL

LTC4313-3

SCLIN SCLOUT

V

CC

SCLIN

LTC4313-2

ENABLE

SCLOUT

µP

2

I C

DEVICE

IPMB-B

3.3V

V

CC

IPMB-B DETAILS (NOT SHOWN) ARE IDENTICAL TO IPMB-A

LTC4313-3

SCLIN

SCLOUT

FRU #N

3.3V

V

CC

R6

10k

R5

10k

LTC4313-3

SCLIN SCLOUT

TO SHMC#2

2

I C

DEVICE

3.3V

SHELF MANAGER #2

IDENTICAL TO SHELF MANAGER #1

V

CC

IPMB-B

SCL

LTC4313-3

SCLIN SCLOUT

TO SHMC#2

4313123 F07

Figure 7. LTC4313s Used in a Bussed ATCA Application. Only the Clock Path is Shown for Simplicity

4313123f

13

LTC4313-1/LTC4313-2/

LTC4313-3

applicaTions inForMaTion

The LTC4313-2 on only one of the shelf managers is

enabled at any given time. The hot insertion logic on the

LTC4313-3 allows the FRUs to be plugged or unplugged

from a live backplane. The features mentioned previously

provide noise immunity and allow timing specifications to

be met for a wide range of backplane loading conditions.

the benefits provided by the LTC4313-2 in Figure 7 apply

to Figure 8 as well.

Cascading and Interoperability with Other LTC Buffers

2

and Non-Compliant I C Devices

MultipleLTC4313scanbecascadedortheLTC4313canbe

cascaded with other LTC bus buffers. Cascades often exist

In the 6 × 4 radial configuration shown in Figure 8, the

LTC4314s on the shelf managers and the LTC4313-2s on

the FRUs drive the large backplane capacitance while the

2

in large I C systems, where multiple I/O cards having bus

buffers connect to a common backplane bus. Two issues

need to be considered when using such cascades – the

additivenatureofthebufferlogiclowoffsetvoltagesandthe

impact of the RTA-buffer interaction on the noise margin.

2

I C slave devices on the FRUs only drive the small input

capacitance of the LTC4313-2s. The LTC4314s on only

one of the shelf managers are enabled at a given time. All

FRU #1

BACKPLANE

3.3V

SHELF MANAGER #1

3.3V

R1

10k

V

CC

V

R3

10k

R4

10k

R2

10k

CC

CC2

IPMB-A

SCL1

LTC4313-2

SCLIN SCLOUT

LTC4314#1

SCLIN SCLOUT1

ENABLE1A

ENABLE2A

ENABLE3A

ENABLE4A

ENABLE1 SCLOUT2

ENABLE2 SCLOUT3

ENABLE3 SCLOUT4

ENABLE4

µP

2

I C

DEVICE

3.3V

V

CC

ACC

3.3V

IPMB-B

SCL1

LTC4313-2

SCLIN SCLOUT

3.3V

V

CC2

LTC4314#6

R5

10k

CC

FRU #24

3.3V

SCLIN

ENABLE21A

ENABLE22A

ENABLE23A

ENABLE24A

ENABLE1 SCLOUT1

ENABLE2 SCLOUT2

ENABLE3 SCLOUT3

ENABLE4 SCLOUT4

ACC

V

CC

R6

10k

R7

10k

IPMB-A

SCL24

LTC4313-2

SCLIN SCLOUT

SCL1

3.3V

2

I C

IPMB-B

IPMB-B DETAILS (NOT SHOWN) ARE IDENTICAL TO IPMB-A

DEVICE

3.3V

SCL24

V

CC

IPMB-B

SCL24

LTC4313-2

SCLIN SCLOUT

IPMB-A(X24)

IPMB-B(X24)

SHELF MANAGER #2

IDENTICAL TO SHELF MANAGER #1

SCL1

4313123 F08

SCL24

Figure 8. LTC4313-2 Used in a Radially Connected Telecommunication System in a 6 × 4 Arrangement.

Only the Clock Path is Shown for Simplicity. The Data Pathway is Identical

4313123f

14

LTC4313-1/LTC4313-2/

LTC4313-3

applicaTions inForMaTion

First, when two or more buffers are connected in a cas-

cade configuration, if the sum of the offsets across the

cascade (refer to Equation 3 and the data sheets of the

corresponding buffers) plus the worst-case driven logic

low voltage exceeds the minimum buffer turn-off voltage,

signals will not be propagated across the cascade. The

maximumdrivenlogiclowvoltagemustbesetaccordingly,

for correct operation in such cascades.

number and turn-on voltage of other RTAs, whose current

mustbesunkbytheLTC4313buffers.Thesamearguments

apply for non-LTC buffer products whose RTA turn-on

voltage is less than 0.3•V .

CC

Interoperabilityisimprovedbyreducingtheinteractiontime

between the LTC4313 buffers and other RTAs by reducing

R1 and C . The following guidelines are recommended

B1

for single supply systems,

Second,noisemarginisaffectedbycascadingtheLTC4313

with buffers whose RTA turn-on voltage is lower than the

a. For 5V systems choose R1 < 20kΩ and C < 1nF. There

B1

are no other constraints.

LTC4313 buffer turn-off voltage. The V for the LTC4313

IL

b. For 3.3V systems, refer to Figures 11 and 12 for opera-

is set to 0.3 • V to achieve high noise margin provided

CC

tion with LTC4300As and LTC4307s. In the figures,

that the LTC4313 buffers do not contend with RTAs of

other products. To maximize logic low noise margin, dis-

able the RTAs of the other LTC buffers if possible and use

the RTAs of the LTC4313 in cascading applications. To

permit interoperability with other LTC buffers whose RTAs

cannot be disabled, the LTC4313 senses the RTA current

Number of LTC4300As or LTC4307s

M =

Number of LTC4313s

R1 and C must be chosen to be below the curves

B1

for a specific value of M. For M greater than the val-

and turns off its buffers below 0.3 • V . This eliminates

ues shown in the figures, non-idealities do not result.

CC

contention between the LTC4313 buffers and other RTAs,

R1 <20kΩ and C <1nF are still recommended.

B1

making the SDA/SCL waveforms monotonic.

2

The LTC4313 is interoperable with non-compliant I C

Figures 9 shows the LTC4313-1 operating on a bus shared

with LTC4300A and LTC4307 buffers. The correspond-

ing SCL waveforms are shown in Figure 10. The RTAs

on the LTC4300A and the LTC4307 cannot be disabled.

The backplane in Figure 9 has five I/O cards connected

to it. Each I/O card has a LTC bus buffer on its outside

edge for SDA/SCL Hot Swap onto the backplane. In this

example, there are three LTC4300As, one LTC4307 and

devices that drive a high V > 0.4V. Figure 13 shows the

OL

LTC4313-1inanapplicationwhereamicrocontrollercom-

municates through the LTC4313-1 with a non-compliant

2

I C device that drives a V of 0.6V. The LTC4313 buffers

OL

are active up to a bus voltage of 0.3•V which is 1.089V

in this case, yielding a noise margin of 0.489V.

CC

Repeater Application

2

one LTC4313-1. The SCL1 bus is driven by an I C master

Multiple LTC4313s can be cascaded in a repeater applica-

tion where a large 2-wire system is broken into smaller

sections as shown in Figure 14. The high noise margin

and low offset of the LTC4313 allows multiple devices

to be cascaded while still providing good system level

noise margin. In the repeater circuit shown in Figure 14 if

SCL1/SDA1 is driven externally to 200mV, SCL2/SDA2

is regulated to ~440mV worst-case by the cascade of

LTC4313-1s. The buffer turn-off voltage is 1.089V, yield-

ing a minimum logic low noise margin of ~650mV. In

Figure 14, use of the RTAs combined with an increased

level of buffering reduces transition times and permits

operation at a higher frequency.

(master not shown). When the SCL2 voltage crosses 0.6V

and 0.8V, the RTAs on the LTC4300A and LTC4307 turn on

respectivelyandsourcecurrentintoSCL2.TheLTC4313-1

detects this and turns off its buffers, releasing SCL1 and

SCL2 high. Contention between the LTC4313-1 buffers

and the LTC4300A and LTC4307 RTAs is prevented and

the SCL1, SCL2 and SCL3 waveforms in Figure 10 are

monotonic.Thelogiclownoisemarginisreducedbecause

the LTC4313-1 buffers turn off when the SCL1 voltage is

approximately 0.6V.

Generally, noise margin will be reduced if other RTAs turn

on at a voltage less than 0.3•V . The reduction in noise

CC

margin is a function of the number of LTC4313s and the

4313123f

15

LTC4313-1/LTC4313-2/

LTC4313-3

applicaTions inForMaTion

I/O CARD #2-4

I/O CARD #1

5V

3.3V

V

CC

R3

2.7k

LTC4300A

SCLIN SCLOUT

GND

C1

0.01µF

R1

5k

R2

2.7k

V

CC

SCL3

LTC4313-1

SCLIN SCLOUT

GND

SCL2

SCL1

* C

C

B2

B1

690pF

100pF

V

CC

R4

5k

LTC4307

SCLOUT

GND

SCL4

* PARASITIC BACKPLANE CAPACITANCE

SCLIN

BACKPLANE

4313123 F09

I/O CARD #5

Figure 9. The LTC4313-1 Operating in a Cascade with Other LTC Buffers

with Active RTAs. Only the Clock Pathway is Shown for Simplicity

SCL3

LTC4300A/

LTC4307

2V/DIV

RTAs

TURN ON

SCL2

SCL1

LTC4313

BUFFERS

TURN OFF

2V/DIV

LTC4313-1

RTA ON

4313123 F10

1µs/DIV

Figure 10. Corresponding SCL Switching Waveforms.

No Glitches Are Seen

4313123f

16

LTC4313-1/LTC4313-2/

LTC4313-3

applicaTions inForMaTion

1000

10000

100

1000

M = 1

M = 3

M = 2

10

100

0

2

4

6

8

10

0

2

4

6

8

10

R

BUS

(kΩ)

R

BUS

(kΩ)

4313123 F11

4313123 F12

Figure 11. Recommended Maximum R1 and C_B1Values for the

LTC4313 Operating with Multiple LTC4300As in a 3.3V System

Figure 12. Recommended Maximum R1 and C_B1Values for the

LTC4313 Operating with Multiple LTC4307s in a 3.3V System

3.3V

5V

C1

0.01µF

R1

R2

R3

10k

R4

R5

V

CC

10k 10k

LTC4313

DISCEN

ENABLE

READY

SCLIN

µP

SCLOUT

SDAOUT

SDAIN

GND

NON-COMPLIANT

4313123 F13

2

I C DEVICE

V

= 0.6V

OL

Figure 13. Communication with a Non-Compliant

I²C Device Using the LTC4313

3.3V

C1

0.01µF

R1

R2

R3

R4

R5

R6

R7

10k

R8

R9

V

CC

V

CC

10k 10k

LTC4313-1

LTC4313-3

LTC4313-1

ENABLE

READY

ENABLE

READY

ENABLE

READY

SCLIN

SDAIN

SCLOUT

SDAOUT

SCLIN

SDAIN

SCLOUT

SDAOUT

SCLIN

SDAIN

SCLOUT

SDAOUT

SCL2

SDA2

SCL1

SDA1

GND

4313123 F14

Figure 14. LTC4313-1s in a Repeater Application

4313123f

17

LTC4313-1/LTC4313-2/

LTC4313-3

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DD8 Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698 Rev C)

0.70 ±0.05

3.5 ±0.05

2.10 ±0.05 (2 SIDES)

1.65 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

0.50

BSC

2.38 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.125

0.40 ± 0.10

TYP

5

8

3.00 ±0.10

(4 SIDES)

1.65 ± 0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

(DD8) DFN 0509 REV C

4

1

0.25 ± 0.05

0.75 ±0.05

0.200 REF

0.50 BSC

2.38 ±0.10

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

4313123f

18

LTC4313-1/LTC4313-2/

LTC4313-3

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660 Rev F)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.52

(.0205)

REF

8

7 6 5

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

4.90 ± 0.152

(.193 ± .006)

0.889 ± 0.127

(.035 ± .005)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

GAUGE PLANE

5.23

(.206)

MIN

1

2

3

4

3.20 – 3.45

(.126 – .136)

0.53 ± 0.152

(.021 ± .006)

1.10

(.043)

MAX

0.86

(.034)

REF

DETAIL “A”

0.18

(.007)

0.65

(.0256)

BSC

0.42 ± 0.038

(.0165 ± .0015)

SEATING

PLANE

TYP

0.22 – 0.38

0.1016 ± 0.0508

RECOMMENDED SOLDER PAD LAYOUT

(.009 – .015)

(.004 ± .002)

0.65

(.0256)

BSC

TYP

NOTE:

MSOP (MS8) 0307 REV F

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

4313123f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LTC4313-1/LTC4313-2/

LTC4313-3

Typical applicaTion

Cascaded Application with Level Shifting and Operation with a Non-Compliant I²C Device

2.5V

3.3V

5V

R1

R2

R3

R4

C1

0.01µF

R5

R6

R7

V

CC

10k 10k

10k 10k 10k

ENABLE

LTC4313-3

ENABLE

READY

LTC4313-2

SCL1

SDA1

SCL2

SDA2

SCLIN

SDAIN

SCLIN

SDAIN

SCLOUT

SDAOUT

SCLOUT

SDAOUT

BACKPLANE OR

LONG CABLE RUN

GND

NON-COMPLIANT

2

I C DEVICE

= 0.6V

V

OL

4313123 TA02

relaTeD parTs

PART NUMBER DESCRIPTION

COMMENTS

LTC4300A-1/

LTC4300A-2/

LTC4300A-3

Hot Swappable 2-Wire Bus Buffers

-1: Bus Buffer with READY and ENABLE

-2: Dual Supply Buffer with ACC

-3: Dual Supply Buffer and ENABLE

LTC4302-1/

LTC4302-2

Addressable 2-Wire Bus Buffer

Address Expansion, GPIO, Software Controlled

2

LTC4303/

LTC4304

Hot Swappable 2-Wire Bus Buffer with Stuck Provides Automatic Clocking to Free Stuck I C Busses

Bus Recovery

LTC4305/

LTC4306

2- or 4-Channel, 2 Wire Bus Multiplexers

with Capacitance Buffering

Two or Four Software Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time

Accelerators, Fault Reporting, ±5kV HBM ESD

LTC4307

LTC4307-1

LTC4308

LTC4309

Low Offset Hot Swappable 2-Wire Bus

Buffer with Stuck Bus Recovery

60mV Bus Offset, Rise Time Accelerators, ±5kV HBM ESD

High Definition Multimedia Interface (HDMI) 60mV Buffer Offset, 3.3V to 5V Level Shifting, 30ms Stuck Bus Disconnect and Recovery,

Level Shifting 2-Wire Bus Buffer ±5kV HBM ESD

Low Voltage, Level Shifting Hot Swappable Bus Buffer with 1V Precharge, ENABLE and READY, 0.9V to 5.5V Level Translation, 30ms

2-Wire Bus Buffer with Stuck Bus Recovery Stuck Bus Disconnect and Recovery, Output Side Rise Time Accelerators, ±6kV HBM ESD

Low Offset Hot Swappable 2-Wire Bus

Buffer with Stuck Bus Recovery

60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time Accelerators,

±5kV HBM ESD, 1.8V to 5.5V Level Translation

2

LTC4310-1

LTC4310-2

Hot Swappable I C Isolators

Bidirectional I C Communication Between Two Isolated Busses, LTC4310-1: 100kHz Bus,

LTC4310-2: 400kHz Bus

2

LTC4311

Low Voltage I C/SMBus Accelerator

Rise Time Acceleration with ENABLE and ±8kV HBM ESD

LTC4312/

LTC4314

2- or 4-Channel, Hardware Selectable 2 Wire Two or Four Pin Selectable Downstream Busses, V Up to 0.3•V , Stuck Bus Disconnect,

IL CC

Bus Multiplexers with Capacitance Buffering Rise time Accelerators, 45ms Stuck Bus Disconnect and Recovery,

±4kV HBM ESD

LTC4315

High Noise Margin 2-Wire Bus Buffer

V = 0.3•V , Rise Time Accelerators, Stuck Bus Disconnect, 1V Precharge,

IL CC

ENABLE and READY Pins, ±4kV HBM ESD

4313123f

LT 1011 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

 LINEAR TECHNOLOGY CORPORATION 2011

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC4313-3
厂家：	Linear
描述：	2-Wire Bus Buffers with High Noise Margin
文件：	总20页 (文件大小：294K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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