LTC5800HWR-WHMA#PBF_技术文档

LTC5800-WHM

SmartMesh WirelessHART Node

Wireless Mote

neTwork FeaTures

DescripTion

SmartMesh WirelessHART wireless sensor networks

n

Complete Radio Transceiver, Embedded Processor,

and Networking Software for Forming a Self-Healing

Mesh Network

are self managing, low power networks built from

wireless nodes called motes. The LTC^®5800-WHM is the

WirelessHART Mote-on-Chip™ integrated circuit in the

Eterna^®* family of IEEE 802.15.4 System-on-Chip (SoC)

solutions, featuring a highly integrated, low power radio

designbyDustNetworks^®aswellasanARMCortex-M332-

bitmicroprocessorrunningDust’sembeddedSmartMesh

WirelessHART networking software.

n

Compliant to WirelessHART (IEC62591) Standard

SmartMesh^®Networks Incorporate:

n

Time Synchronized Network-Wide Scheduling

n

Per Transmission Frequency Hopping

n

Redundant Spatially Diverse Topologies

n

Network-Wide Reliability and Power Optimization

n

NIST Certiﬁed Security

The LTC5800-WHM SoC features an on-chip power am-

plifier (PA) and transceiver, requiring only power supply

decoupling, crystals, and antenna with matching circuitry

to create a complete wireless node.

n

SmartMesh Networks Deliver:

n

>99.999% Network Reliability Achieved in the

Most Challenging Dynamic RF Environments Often

Found in Industrial Applications

Sub 50µA Routing Nodes

n

WithDust’stime-synchronizedWirelessHARTnetworksall

motes in the network may route, source or terminate data

while providing many years of battery powered operation.

The SmartMesh WirelessHART software provided with

the LTC5800-WHM is fully tested and validated, and is

readily configured via a software Application Program-

ming Interface.

lTc5800-wHM FeaTures

n

Industry-Leading Low Power Radio Technology with:

n

4.5mA to Receive a Packet

n

5.4mA to Transmit at 0dBm

n

9.7mA to Transmit at 8dBm

SmartMesh WirelessHART motes deliver a highly flexible

networkwithprovenreliabilityandlowpowerperformance

in an easy-to-integrate platform.

n

PCB Module Versions Available (LTP™5901/LTP5902-

WHM) with RF Modular Certiﬁcations

n

2.4GHz, IEEE 802.15.4 System-on-Chip

L, LT, LTC, LTM, Linear Technology, the Linear logo, Dust, Dust Networks, SmartMesh and

Eterna are registered trademarks and LTP, the Dust Networks logo and Mote-on-Chip are

trademarks of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217, 7791419,

7881239, 7898322, 8222965.

n

72-Pin 10mm × 10mm QFN Package

* Eterna is Dust Networks’ low power radio SoC architecture.

Typical applicaTion

20MHz

EXPANDED VIEW

MANAGER

LTP5903-WHR

ANTENNA

LTC5800-WHM

ANTENNA

IN+

LTC2379-18 SPI

UART

ETHERNET

SENSOR

µCONTROLLER

IN–

HOST

APPLICATION

32kHz

MOTE

5800WHM TA01

5800whmfa

1

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

Table oF conTenTs

Network Features .......................................... 1

LTC5800-WHM Features .................................. 1

Typical Application ........................................ 1

Description.................................................. 1

SmartMesh Network Overview........................... 3

Absolute Maximum Ratings.............................. 4

Order Information.......................................... 4

Pin Configuration .......................................... 4

Recommended Operating Conditions................... 5

DC Characteristics......................................... 5

Radio Specifications ...................................... 5

Radio Receiver Characteristics.......................... 6

Radio Transmitter Characteristics....................... 6

Digital I/O Characteristics ................................ 7

Temperature Sensor Characteristics.................... 7

Analog Input Chain Characteristics ..................... 7

System Characteristics ................................... 8

UART AC Characteristics.................................. 8

TIMEn AC Characteristics................................10

Radio_Inhibit AC Characteristics.......................10

Flash AC Characteristics.................................11

Flash SPI Slave AC Characteristics ....................11

Electrical Characteristics................................12

Typical Performance Characteristics ..................13

Pin Functions..............................................17

Operation...................................................22

Power Supply..........................................................22

Supply Monitoring and Reset .................................23

Precision Timing.....................................................23

Application Time Synchronization ..........................23

Time References.....................................................23

Radio ......................................................................24

UARTs.....................................................................24

Autonomous MAC...................................................25

Security ..................................................................25

Temperature Sensor ...............................................26

Radio Inhibit ...........................................................26

Flash Programming ................................................26

FLASH Data Retention ............................................26

State Diagram.........................................................28

Applications Information ................................29

Regulatory and Standards Compliance...................29

Soldering Information.............................................29

Related Documentation..................................30

Package Description .....................................31

Typical Application .......................................32

Related Parts..............................................32

5800whmfa

2

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

sMarTMesH neTwork overview

ASmartMeshnetworkconsistsofaself-formingmulti-hop

mesh of nodes, known as motes, which collect and relay

data, and a network manager that monitors and manages

network performance and security, and exchanges data

with a host application.

The Network Manager uses health reports to continually

optimizethenetworktomaintain>99.999%datareliability

even in the most challenging RF environments.

The use of TSCH allows SmartMesh devices to sleep in

between scheduled communications and draw very little

power in this state. Motes are only active in time slots

where they are scheduled to transmit or receive, typically

resulting in a duty cycle of < 1%. The optimization soft-

ware in the Network Manager coordinates this schedule

automatically. When combined with the Eterna low power

radio, every mote in a SmartMesh network—even busy

routing ones—can run on batteries for years. By default,

all motes in a network are capable of routing traffic from

other motes, which simplifies installation by avoiding the

complexity of having distinct routers vs non-routing end

nodes. Motesmaybeconfiguredasnon-routingtofurther

reduce that particular mote’s power consumption and to

support a wide variety of network topologies.

SmartMesh networks communicate using a time slotted

channel hopping (TSCH) link layer, pioneered by Dust

Networks. In a TSCH network, all motes in the network

are synchronized to within less than a millisecond. Time

in the network is organized into time slots, which enables

collision-free packet exchange and per-transmission

channel-hopping. In a SmartMesh network, every device

has one or more parents (e.g. mote 3 has motes 1 and

2 as parents) that provide redundant paths to overcome

communicationsinterruptionduetointerference,physical

obstruction or multi-path fading. If a packet transmission

fails on one path, the next retransmission may try on a

different path and different RF channel.

A network begins to form when the network manager

instructs its on-board Access Point (AP) radio to begin

sendingadvertisements—packetsthatcontaininformation

that enables a device to synchronize to the network and

request to join. This message exchange is part of the secu-

rityhandshakethatestablishesencryptedcommunications

betweenthemanagerorapplication,andmote.Oncemotes

have joined the network, they maintain synchronization

through time corrections when a packet is acknowledged.

ALL NODES ARE ROUTERS.

THEY CAN TRANSMIT AND RECEIVE.

THIS NEW NODE CAN JOIN

ANYWHERE BECAUSE ALL

NODES CAN ROUTE.

HOST

APPLICATION

SNO 02

At the heart of SmartMesh motes and network manag-

ers is the Eterna IEEE 802.15.4e System-on-Chip (SoC),

featuring Dust Networks’ highly integrated, low power

radio design, plus an ARM Cortex-M3 32-bit micropro-

cessor running SmartMesh networking software. The

SmartMesh networking software comes fully compiled

yet is configurable via a rich set of Application Program-

ming Interfaces (APIs) which allows a host application

to interact with the network, e.g. to transfer information

to a device, to configure data publishing rates on one or

more motes, or to monitor network state or performance

metrics. Data publishing can be uniform or different for

each device, with motes being able to publish infrequently

NETWORK MANAGER

AP

Mote

1

Mote

2

Mote

3

SNO 01

An ongoing discovery process ensures that the network

continually discovers new paths as the RF conditions

change. In addition, each mote in the network tracks per-

formance statistics (e.g. quality of used paths, and lists of

potential paths) and periodically sends that information

to the network manager in packets called health reports.

or faster than once per second as needed.

5800whmfa

3

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

absoluTe MaxiMuM raTings

pin conFiguraTion

Pin functions shown in italics are currently not supported in software.

(Note 1)

Supply Voltage on VSUPPLY..................................4.20V

Input Voltage on AI_0/AI_1/AI_2/AI_3 Inputs ........1.80V

Voltage on Any Digital I/O Pin –0.3V to VSUPPLY + 0.3V

Input RF Level......................................................10dBm

Storage Temperature Range (Note 3)..... –55°C to 125°C

Junction Temperature (Note 3) ............................. 125°C

Operating Temperature Range

TOP VIEW

RADIO_INHIBIT 1

CAP_PA_1P 2

CAP_PA_1M 3

CAP_PA_2M 4

CAP_PA_2P 5

CAP_PA_3P 6

CAP_PA_3M 7

CAP_PA_4M 8

CAP_PA_4P 9

VDDPA 10

54 VPP

53 SPIS_SSn / SDA

52 SPIS_SCK / SCL

51 SPIS_MOSI / GPIO26 / UARTC1_RX

50 SPIS_MISO / 1_WIRE / UARTC1_TX

49 PWM0 / GPIO16

48 DP1 (GPIO20) / TIMER16_IN

47 SPIM_SS_0n / GPIO12

46 SPIM_SS_1n / GPIO13

45 IPCS_SSn / GPIO3

44 IPCS_SCK / GPIO4

43 SPIM_SCK / GPIO9

42 IPCS_MOSI / GPIO5

41 SPIM_MOSI / GPIO10

40 IPCS_MISO / GPIO6

39 SPIM_MISO / GPIO11

38 UARTCO_RX

LTC5800I.............................................–40°C to 85°C

LTC5800H.......................................... –55°C to 105°C

EXPOSED PAD

(GND)

LNA_EN / GPIO17 11

RADIO_TX / GPIO18 12

RADIO_TXn / GPIO19 13

ANTENNA 14

CAUTION: This part is sensitive to electrostatic discharge

(ESD). It is very important that proper ESD precautions be

observed when handling the LTC5800-WHM.

AI_0 15

AI_1 16

AI_3 17

AI_2 18

37 UARTCO_TX

WR PACKAGE

72-LEAD PLASTIC QFN

T

= 125°C, Ψ

= 0.2°C/W, Ψ = 0.6°C/W

JCbottom

JMAX

JCtop

EXPOSED PAD IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 85°C

–55°C to 105°C

LTC5800IWR-WHMA#PBF

LTC5800HWR-WHMA#PBF

LTC5800WR-WHMA

72-Lead (10mm × 10mm × 0.85mm) Plastic QFN

*The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

5800whmfa

4

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

recoMMenDeD operaTing conDiTions ^Thel denotes the specifications which apply over

the full operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

3.76

250

90

UNITS

V

l

VSUPPLY

Supply Voltage

Including Noise and Load Regulation

Requires Recommended RLC Filter, 50Hz to 2MHz

Non-condensing

2.1

Supply Noise

mV

Operating Relative Humidity

Temperature Ramp Rate

10

–8

% RH

°C/min

While Operating in Network

+8

Dc cHaracTerisTics ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

OPERATION/STATE

Reset

CONDITIONS

MIN

TYP

1.2

12

MAX

UNITS

µA

After Power-on Reset

Power-on Reset

During Power-on Reset, Maximum 750µs + VSUPPLY Rise Time

from 1V to 1.9V

mA

Doze

RAM On, ARM Cortex-M3, Flash, Radio, and Peripherals Off,

All Data and State Retained, 32.768kHz Reference Active

1.2

0.8

20

µA

Deep Sleep

RAM On, ARM Cortex-M3, Flash, Radio, and Peripherals Off,

All Data and State Retained, 32.768kHz Reference Inactive

In-Circuit Programming

RESETn and FLASH_P_ENn Asserted, IPCS_SCK at 8MHz

mA

Peak Operating Current

+8dBm

System Operating at 14.7MHz, Radio Transmitting, During Flash

Write. Maximum duration 4.33 ms.

30

26

mA

+0dBm

Active

ARM Cortex M3, RAM and Flash Operating, Radio and All Other

Peripherals Off. Clock Frequency of CPU and Peripherals Set to

7.3728MHz, VCORE = 1.2V

1.3

mA

Flash Write

Flash Erase

Single Bank Flash Write

3.7

2.5

mA

Single Bank Page or Mass Erase

Radio Tx

Current With Autonomous MAC Managing Radio Operation,

CPU Inactive. Clock Frequency of CPU and Peripherals Set to

7.3728MHz.

+0dBm (LTC5800I)

+0dBm (LTC5800H)

+8dBm (LTC5800I)

+8dBm (LTC5800H)

5.4

5.6

9.7

9.9

mA

Radio Rx

LTC5800I

LTC5800H

Current With Autonomous MAC Managing Radio Operation,

CPU Inactive. Clock Frequency of CPU and Peripherals Set to

7.3728MHz.

4.5

4.7

mA

raDio speciFicaTions ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

Frequency Band

2.4000

2.4835

GHz

Number of Channels

Channel Separation

Channel Center Frequency

Raw Data Rate

15

5

2405 + 5•(k-11)

250

MHz

kbps

V

Where k = 11 to 25, as Defined by IEEE.802.15.4

HBM Per JEDEC JESD22-A114F

Antenna Pin ESD Protection

1000

Range (Note 4)

Indoor

25°C, 50% RH, +2dBi Omni-Directional Antenna, Antenna 2m

Above Ground

100

300

1200

m

Outdoor

Free Space

5800whmfa

5

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

raDio receiver cHaracTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

–93

–95

0

MAX

UNITS

dBm

Receiver Sensitivity

Saturation

Packet Error Rate (PER) = 1% (Note 5)

PER = 50%

Maximum Input Level the Receiver Will

Properly Receive Packets

Adjacent Channel Rejection (High Side) Desired Signal at -82dBm, Adjacent Modulated Channel 5MHz

Above the Desired Signal, PER = 1% (Note 5)

22

19

40

36

42

–6

dBc

Adjacent Channel Rejection (Low Side) Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz

Below the Desired Signal, PER = 1% (Note 5)

Alternate Channel Rejection

(High Side)

Desired Signal at –82dBm, Alternate Modulated Channel 10MHz

Above the Desired Signal, PER = 1% (Note 5)

Alternate Channel Rejection (Low Side) Desired Signal at –82dBm, Alternate Modulated Channel 10MHz

Below the Desired Signal, PER = 1% (Note 5)

Second Alternate Channel Rejection

Desired Signal at –82dBm, Second Alternate Modulated Channel

Either 15MHz Above or Below, PER = 1% (Note 5)

Co-Channel Rejection

Desired Signal at –82dBm, Undesired Signal is an 802.15.4

Modulated Signal at the Same Frequency, PER = 1%

LO Feed Through

–55

50

dBm

ppm

dBm

Frequency Error Tolerance (Note 6)

Symbol Error Tolerance

50

Received Signal Strength Indicator

(RSSI) Input Range

–90 to –10

RSSI Accuracy

6

1

dB

RSSI Resolution

raDio TransMiTTer cHaracTerisTics ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Output Power

Delivered to a 50Ω Load

High Calibrated Setting

8

0

dBm

Low Calibrated Setting

Spurious Emissions

Conducted Measurement with a 50Ω Single-Ended Load,

+8dBm Output Power. All Measurements Made with Max

Hold. RF Implementation Per Eterna Reference Design

30MHz to 1000MHz

R

BW

R

BW

R

BW

R

BW

R

BW

= 120kHz, V = 100Hz

<–70

–45

–37

–49

–45

dBm

dBc

BW

1GHz to 12.75GHz

= 1MHz, V = 3MHz

BW

2.4GHz ISM Upper Band Edge (Peak)

2.4GHz ISM Upper Band Edge (Average)

2.4GHz ISM Lower Band Edge

= 1MHz, V = 3MHz

BW

= 1MHz, V = 10Hz

BW

= 100kHz, V = 100kHz

BW

Harmonic Emissions

2nd Harmonic

Conducted Measurement Delivered to a 50Ω Load,

Resolution Bandwidth = 1MHz, Video Bandwidth = 1MHz,

RF Implementation Per Eterna Reference Design

–50

–45

dBm

3rd Harmonic

5800whmfa

6

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

DigiTal i/o cHaracTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS (Note 7)

MIN

–0.3

TYP

MAX

0.6

UNITS

l

V

Low Level Input Voltage

High Level Input Voltage

Low Level Output Voltage

High Level Output Voltage

Input Leakage Current

V

IL

(Note 8)

VSUPPLY – 0.3

VSUPPLY + 0.3

0.4

IH

OL

Type 1, I

= 1.2mA

V

OL(MAX)

Type 2, Low Drive, I

= 2.2mA

= 4.5mA

0.4

V

OL(MAX)

Type 2, High Drive, I

0.4

V

OL(MAX)

V

Type 1, I

= –0.8mA

OH(MAX)

VSUPPLY – 0.3

VSUPPLY + 0.3

V

OH

Type 2, Low Drive, I

= –1.6mA

= –3.2mA

V

OH(MAX)

Type 2, High Drive, I

V

OH(MAX)

Input Driven to VSUPPLY or GND

50

nA

kΩ

Pull-Up/Pull-Down Resistance

TeMperaTure sensor cHaracTerisTics ^Thel denotes the specifications which apply over

the full operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER

Offset

CONDITIONS

MIN

TYP

MAX

UNITS

°C

Temperature Offset Error at 25°C

0.25

0.033

Slope Error

°C/°C

analog inpuT cHain cHaracTerisTics ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Variable Gain Amplifier

Gain

1

8

2

Gain Error

%

Offset-Digital to Analog Converter (DAC)

Full-Scale

1.80

4

V

Bits

mV

Resolution

DNL

Differential Non-Linearity

2.7

Analog to Digital Converter (ADC)

Full-Scale, Signal

Resolution

1.80

1.8

V

mV

LSB

µs

Offset

Mid-Scale

1.4

12

1

DNL

INL

Differential Non-Linearity

Integral Non-Linearity

Settling Time

Conversion Time

Current Consumption

1

10kΩ Source Impedance

10

20

µs

40

µA

Analog Inputs (Note 9)

Load

20

1

pF

kΩ

Series Input Resistance

5800whmfa

7

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

sysTeM cHaracTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

5

MAX

UNITS

µs

Doze to Active State Transition

Doze to Radio Tx or Rx

1.2

4

ms

Q

Charge to Sample RF Channel RSSI

Charge Consumed Starting from Doze State

and Completing an RSSI Measurement

µC

CCA

l

Largest Atomic Charge Operation

RESETn Pulse Width

Flash Erase, 21ms Max Duration

200

µC

µs

MAX

125

uarT ac cHaracTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

Permitted R Baud Rate Error

CONDITIONS

MIN

TYP

MAX

UNITS

l

Both Application Programming

Interface (API) and Command Line

Interface (CLI) UARTs

–2

2

%

X

l

Generated T Baud Rate Error

Both API and CLI UARTs

–1

0

1

2

%

X

t

Assertion of UART_RX_RTSn to Assertion of

UART_RX_CTSn, or Negation of UART_RX_

RTSn to Negation of UART_RX_CTSn

ms

RX_RTS to RX_CTS

l

t

Assertion of UART_RX_CTSn to Start of Byte

0

20

22

ms

CTS_R to RX

End of Packet (End of the Last Stop Bit) to

Negation of UART_RX_RTSn

EOP to RX_RTS

l

t

Assertion of UART_TX_RTSn to Assertion of

UART_TX_CTSn

0

22

ms

BEG_TX_RTS to TX_CTS

END_TX_RTS to TX_CTS

END_TX_CTS to TX_RTS

Negation of UART_TX_RTSn to Negation of

UART_TX_CTSn

Mode 2 Only

Mode 4 Only

Negation of UART_TX_CTSn to Negation of

UART_TX_RTSn

2

Bit Period

l

t

Assertion of UART_TX_CTSn to Start of Byte

0

2

1

Bit Period

TX_CTS to TX

End of Packet (End of the Last Stop Bit) to

Negation of UART_TX_RTSn

EOP to TX_RTS

l

t

Receive Inter-Byte Delay

100

ms

RX_INTERBYTE

RX_INTERPACKET

TX_INTERPACKET

TX to TX_CTS

Receive Inter-Packet Delay

20

1

Transmit Inter-Packet Delay

Bit Period

ns

Start of Byte to Negation of UART_TX_CTSn

0

5800whmfa

8

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

uarT ac cHaracTerisTics

t

EOP to RX_RTS

t

RX_INTERPACKET

UART_RX_RTSn

UART_RX_CTSn

UART_RX

t

RX_RTS to RX_CTS

t

RX_RTS to RX_CTS

t

RX_CTS to RX

BYTE 0

t

RX_INTERBYTE

BYTE 1

t

EOP to TX_RTS

t

TX_INTERPACKET

UART_TX_RTSn

UART_TX_CTSn

UART_TX

t

END_TX_CTS to TX_RTS

END_TX_RTS to TX_CTS

TX_RTS to TX_CTS

t

TX to TX_CTS

t

TX_CTS to TX

BYTE 0

BYTE 1

5800IPM F01

Figure 1. API UART Timing

5800whmfa

9

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

TiMeꢀ ac cHaracTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

125

0

TYP

MAX

UNITS

µs

l

t

TIMEn Signal Strobe Width

STROBE

Delay from Rising Edge of TIMEn to the Start

of Time Packet on API UART

100

ms

RESPONSE

l

t

Delay from End of Time Packet on API UART

to Falling Edge of Subsequent TIMEn

0

ns

TIME_HOLD

l

Timestamp Resolution (Note 10)

1

5

µs

Network-Wide Time Accuracy (Note 11)

t

STROBE

t

TIME_HOLD

TIMEn

t

RESPONSE

UART_TX

TIME INDICATION PAYLOAD

5800WHM F02

Figure 2. Timestamp Timing

raDio_inHibiT ac cHaracTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

t

Delay from Rising Edge of

20

ms

RADIO_OFF

RADIO_INHIBIT to Radio Disabled

t

Maximum RADIO_INHIBIT Strobe Width

2

s

RADIO_INHIBIT_STROBE

t

RADIO_INHIBIT_STROBE

RADIO_INHIBIT

t

RADIO_OFF

RADIO STATE

ACTIVE/OFF

OFF

ACTIVE/OFF

5800WHM F03

Figure 3. RADIO_INHIBIT Timing

5800whmfa

10

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

FlasH ac cHaracTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

21

UNITS

µs

l

t

Time to Write a 32-Bit Word (Note 12)

Time to Erase a 2kB Page (Note 12)

Time to Erase 256kB Flash Bank (Note 12)

Data Retention

WRITE

21

ms

PAGE_ERASE

MASS_ERASE

21

ms

25°C

85°C

105°C

100

20

8

Years

FlasH spi slave ac cHaracTerisTics ^Thel denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 13)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

t

Setup from Assertion of FLASH_P_ENn to

Assertion of RESETn

0

ns

FP_EN_to_RESET

Delay from the Assertion RESETn to the

First Falling Edge of IPCS_SSn

125

10

µs

FP_ENTER

Delay from the Completion of the Last

Flash SPI Slave Transaction to the

Negation of RESETn and FLASH_P_ENn

(Note 13)

FP_EXIT

l

t

IPCS_SSn Setup to the Leading Edge of

IPCS_SCK

15

ns

SSS

IPCS_SSn Hold from Trailing Edge of

IPCS_SCK

SSH

l

t

IPCS_SCK Period

300

15

5

ns

CK

IPCS_MOSI Data Setup

IPCS_MOSI Data Hold

IPCS_MISO Data Valid

IPCS_MISO Data Tri-State

DIS

DIH

DOV

OFF

–5

0

30

t

FP_EN_TO_RESET

FLASH_P_ENn

RESETn

t

FP_EXIT

FP_ENTER

t

SSH

SSS

IPCS_SSn

IPCS_SCK

t

CK

t

DIS

t

DIH

IPCS_MOSI

IPCS_MISO

t

DOV

t

OFF

5800IPM F04

Figure 4. Flash Programming Interface Timing

5800whmfa

11

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

elecTrical cHaracTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6: IEEE Std. 802.15.4-2006 requires transmitters to maintain a

frequency tolerance of better than 40ppm.

Note 7: Per-pin IO types are provided in the Pin Functions section.

Note 8: VIH maximum voltage input must respect the VSUPPLY maximum

Note 2: ESD (electrostatic discharge) sensitive device. ESD protection

devices are used extensively internal to Eterna. However, high electrostatic

discharge can damage or degrade the device. Use proper ESD handling

precautions.

Note 3: Extended storage at high temperature is discouraged, as this

negatively affects the data retention of Eterna’s calibration data. See the

FLASH Data Retention section for details.

voltage specification.

Note 9: The analog inputs to the ADC can be modeled as a series resistor

to a capacitor. At a minimum the entire circuit, including the source

impedance for the signal driving the analog input should be designed

to settle to within ¼ LSB within the sampling window to match the

performance of the ADC.

Note 10: See the SmartMesh WirelessHART API Guide for the

Note 4: Actual RF range is subject to a number of installation-specific

variables including, but not restricted to ambient temperature, relative

humidity, presence of active interference sources, line-of-sight obstacles,

and near-presence of objects (for example, trees, walls, signage, and so

on) that may induce multipath fading. As a result, range varies.

Note 5: As Specified by IEEE Std. 802.15.4-2006: Wireless Medium

Access Control (MAC) and Physical Layer (PHY) Specifications for

Low-Rate Wireless Personal Area Networks (LR-WPANs)

timeIndication notification definition.

Note 11: Network time accuracy is a statistical measure and varies over

the temperature range, reporting rate and the location of the device

relative to the manager in the network. See the Typical Performance

Characteristics section for a more detailed description.

Note 12: Code execution from flash banks being written or erased is

suspended until completion of the flash operation.

Note 13: Guaranteed by design. Not production tested.

http://standards.ieee.org/findstds/standard/802.15.4-2011.html

5800whmfa

12

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

Typical perForMance cHaracTerisTics

Networkmotestypicallyroutethroughatleasttwoparents

the traffic destined for the manager. The supply current

graphs shown in Figure 5 include a parameter called de-

scendants. In these graphs the term descendants is short

for traffic-weighted descendants and refers to an amount

of activity equivalent to the number of descendants if all

of the network traffic directed to the mote in question.

Generally the number of descendants of a parent is more,

typically 2x or more, than the number of traffic-weighted

descendants.Forexample,withreferencetoFigure6mote

P1 has 0.75 traffic-weighted descendants. To obtain this

value notice that mote D1 routes half its packets through

mote P1 adding 0.5 to the traffic-weighted descendant

value; the other half of D1’s traffic is routed through its

other parent, P2. Mote D2 routes half its packets through

mote D1 (the other half going through parent P3), which

weknowrouteshalfitspacketstomoteP1,addinganother

0.25 to the traffic-weighted descendant value for a total

traffic-weighted descendant value of 0.75.

was performed with the 1-hop mote inside a temperature

chamber. Timing errors due to temperature changes and

temperature differences both between the manager and

this mote and between this mote and its descendents

thereforepropagateddownthroughthenetwork. Thesyn-

chronizationofthe3-hopand5-hopmotestothemanager

was then affected by the temperature ramps even though

they were at room temperature. For 2°C/minute testing

the temperature chamber was cycled between –40°C and

85°C at this rate for 24 hours. For 8°C/minute testing, the

temperaturechamberwasrapidlycycledbetween85°Cand

45°C for 8 hours, followed by rapid cycling between –5°C

and 45°C for 8 hours, and lastly, rapid cycling between

–40°C and 15°C for 8 hours.

MANAGER

P1

As described in the Application Time Synchronization

section,Eternaprovidestwomechanismsforapplications

to maintain a time base across a network. The synchro-

nization performance plots that follow were generated

using the more precise TIMEn input. Publishing rate is

the rate a mote application sends upstream data. Syn-

chronization improves as the publishing rate increases.

Baseline synchronization performance is provided for a

network operating with a publishing rate of zero. Actual

performance for applications in network will improve

as publishing rates increase. All synchronization testing

P2

1 HOP

P3

2 HOP

D1

3 HOP

D2

5800WHM F06

Figure 6. Example Network Graph

120

100

80

60

40

20

0

10

9

8

7

6

5

4

3

2

1

0

250

5 HOPS

4 HOPS

3 HOPS

2 HOPS

1 HOP

5 DESCENDANTS

2 DESCENDANTS

1 DESCENDANTS

200

0 DESCENDANTS

2 DESCENDANTS 5sec REPORTING

5 DESCENDANTS 30sec REPORTING

2 DESCENDANTS 30sec REPORTING

0 DESCENDANTS 5sec REPORTING

0 DESCENDANTS 30sec REPORTING

150

100

50

0

60 80 100

TEMPERATURE (°C)

–60

0

30

25

30

–40 –20

0

20 40

5

10

15

20

25

0

5

10

15

20

REPORTING INTERVAL (sec)

5800WHM F05a

5800WHM F05b

5800WHM F05c

Figure 5

5800whmfa

13

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

Typical perForMance cHaracTerisTics

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, Room Temperature

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, Room Temperature

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, Room Temperature

35

30

25

20

15

10

5

18

16

14

12

10

8

12

10

8

µ = 0.1

σ = 35.0

N = 281490

µ = –0.7

σ = 63.0

N = 281492

µ = –0.8

σ = 110.7

N = 281493

6

4

2

0

–500

0

100

300

500

–500

0

100

300

500

–300

–100

–300

–100

–500

0

100

300

500

–300

–100

SYNCHRONIZATION ERROR (µs)

5800WHM G02

5800WHM G01

5800WHM G03

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, 2°C/Min

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, 2°C/Min

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, 2°C/Min

45

40

35

30

25

20

15

10

5

14

12

10

8

9

8

7

6

5

4

3

2

1

0

µ = 7.2

σ = 75.9

N = 92718

µ = 6

σ = 125.7

N = 92719

µ = 10.1

σ = 35.7

N = 92717

6

4

2

0

–500

0

100

300

500

–500

0

100

300

500

–500

0

100

300

–300

–100

–300

–100

–300

–100

SYNCHRONIZATION ERROR (µs)

5800WHM G04

5800WHM G05

5800WHM G06

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, 8°C/Min

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, 8°C/Min

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, 8°C/Min

8

7

6

5

4

3

2

1

0

14

12

10

8

45

40

35

30

25

20

15

10

5

µ = 10.7

σ = 136.8

N = 95167

µ = 10.9

σ = 81.5

N = 95165

µ = 15.3

σ = 39.4

N = 91114

6

4

2

0

–500

0

100

300

–500

0

100

300

500

–300

–100

–500

0

100

300

500

–300

–100

–300

–100

SYNCHRONIZATION ERROR (µs)

5800WHM G08

5800WHM G09

5800WHM G07

5800whmfa

14

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

Typical perForMance cHaracTerisTics

As described in the SmartMesh Network Overview sec-

tion, devices in network spend the vast majority of their

time inactive in their lowest power state (doze). On a

synchronous schedule a mote will wake to communicate

with another mote. Regularly occurring sequences which

wake, perform a significant function and return to sleep

are considered atomic. These operations are considered

atomic as the sequence of events can not be separated

into smaller events while performing a useful function.

For example, transmission of a packet over the radio is

an atomic operation. Atomic operations are characterized

in either charge or energy. In a time slot where a mote

successfully sends a packet, an atomic transmit includes

setuppriortosendingthemessage, sendingthemessage,

receiving the acknowledgment and the post processing

needed as a result of the message being sent. Similarly in

a time slot when a mote successfully receives a packet, an

atomic receive includes setup prior to listening, listening

untilthestartofthepackettransition, receivingthepacket,

sending the acknowledgement and post processing re-

quired due to the arrival of the packet.

To ensure reliability each mote in the network is provided

multiple time slots for each packet it nominally will send

and forward. The time slots are assigned to communicate

upstream, toward the manager, with at least two different

motes. When combined with frequency hopping this pro-

videstemporal,spatialandspectralredundancy.Giventhis

approach a mote will often listen for a message that it will

never receive, since the time slot is not being used by the

transmitting mote. It has already successfully transmitted

the packet. Since typically 3 time slots are scheduled for

every1packettobesentorforwarded, moteswillperform

moreoftheseatomic“idlelistens”thanatomictransmitor

atomic receive sequences. Examples of transmit, receive

and idle listen atomic operations are shown in Figure 7.

5800whmfa

15

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

Typical perForMance cHaracTerisTics

Atomic Operation – Idle Listen, 10ms Time Slot (15.1µC Total Charge at 3.6V), 25°C, LTC5800I

25

20

15

10

5

80

70

60

50

40

30

20

10

0

DOZE

IDLE RECEIVE

DOZE

POWER UP

CURRENT

0

CHARGE

0

–5

–2000

2000

4000

6000

8000

10000

12000

TIME (µs)

5800WHM F07a

Atomic Operation – Maximum Length Transmit with Acknowlege, 10ms Time Slot (39.2µC Total Charge at 3.6V), 25°C, LTC5800I

25

20

15

10

5

80

70

60

50

40

30

20

10

0

POST

MESSAGE

POWER UP

RECEIVE WITH AES

Tx ACKNOWLEDGE

DOZE

PROCESSING

CURRENT

0

CHARGE

0

–5

–2000

2000

4000

6000

8000

10000

12000

TIME (µs)

5800WHM F07b

Atomic Operation – Maximum Length Transmit with Acknowlege, 10ms Time Slot (55.9µC Total Charge at 3.6V), 25°C, LTC5800I

25

20

15

10

5

80

70

60

50

40

30

20

10

0

POST MESSAGE

PROCESSING

DOZE

POWER UP

PACKET TRANSMISSION

Rx ACKNOWLEDGE

DOZE

CURRENT

0

CHARGE

–5

–2000

0

2000

4000

6000

8000

10000

12000

TIME (µs)

5800WHM F07c

Figure 7

5800whmfa

16

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

pin FuncTions

Pin functions shown in italics are currently not supported in software.

The following table organizes the pins by functional

groups. For those I/O with multiple functions the alternate

functions are shown on the second and third line in their

respective row. The No column provides the pin number.

The second column lists the function. The Type column

lists the I/O type. The I/O column lists the direction of the

signal relative to Eterna. The Pull column shows which

signals have a fixed passive pull-up or pull-down. The

Description column provides a brief signal description.

NO POWER SUPPLY

TYPE

Power

Test

I/O

-

PULL DESCRIPTION

P

2

3

4

5

6

7

8

9

GND

-

Ground Connection, P = QFN Paddle

CAP_PA_1P

CAP_PA_1M

CAP_PA_2M

CAP_PA_2P

CAP_PA_3P

CAP_PA_3M

CAP_PA_4M

CAP_PA_4P

-

PA DC/DC Converter Capacitor 1 Plus Terminal

PA DC/DC Converter Capacitor 1 Minus Terminal

PA DC/DC Converter Capacitor 2 Minus Terminal

PA DC/DC Converter Capacitor 2 Plus Terminal

PA DC/DC Converter Capacitor 3 Plus Terminal

PA DC/DC Converter Capacitor 3 Minus Terminal

PA DC/DC Converter Capacitor 4 Minus Terminal

PA DC/DC Converter Capacitor 4 Plus Terminal

Internal Power Amplifier Power Supply, Bypass

Regulated Analog Supply, Bypass

-

10 VDDPA

-

30 VDDA

-

31 VCORE

-

Regulated Core Supply, Bypass

32 VOSC

-

Regulated Oscillator Supply, Bypass

54 VPP

-

Internal Regulator Test Port

56 VPRIME

Power

-

Internal Primary Power Supply, Bypass

57 CAP_PRIME_4P

58 CAP_PRIME_4M

59 CAP_PRIME_3M

60 CAP_PRIME_3P

61 CAP_PRIME_2P

62 CAP_PRIME_2M

63 CAP_PRIME_1M

64 CAP_PRIME_1P

65 VSUPPLY

-

Primary DC/DC Converter Capacitor 4 Plus Terminal

Primary DC/DC Converter Capacitor 4 Minus Terminal

Primary DC/DC Converter Capacitor 3 Minus Terminal

Primary DC/DC Converter Capacitor 3 Plus Terminal

Primary DC/DC Converter Capacitor 2 Plus Terminal

Primary DC/DC Converter Capacitor 2 Minus Terminal

Primary DC/DC Converter Capacitor 1 Minus Terminal

Primary DC/DC Converter Capacitor 1 Plus Terminal

Power Supply Input to Eterna

-

NO RADIO

TYPE

I/O

PULL DESCRIPTION

1

RADIO_INHIBIT

GPIO15

1 (Note 14)

I

-

Radio Inhibit

General Purpose Digital I/O

I/O

11 LNA_EN

GPIO17

1

-

O

-

External LNA Enable

I/O

General Purpose Digital I/O

12 RADIO_TX

GPIO18

O

I/O

-

Radio TX Active (External PA Enable/Switch Control)

General Purpose Digital I/O

13 RADIO_TXn

GPIO19

O

I/O

-

Radio TX Active (External PA Enable/Switch Control), Active Low

General Purpose Digital I/O

14 ANTENNA

-

Single-Ended Antenna Port, 50Ω

5800whmfa

17

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

pin FuncTions

Pin functions shown in italics are currently not supported in software.

NO ANALOG

15 AI_0

16 AI_1

17 AI_3

18 AI_2

TYPE

I/O

PULL DESCRIPTION

Analog

I

-

Analog Input 0

Analog Input 1

Analog Input 3

Analog Input 2

NO CRYSTALS

TYPE

I/O

O

I

PULL DESCRIPTION

19 OSC_32K_XOUT

20 OSC_32K_XIN

28 OSC_20M_XIN

29 OSC_20M_XOUT

Crystal

-

32 kHz Crystal Xout

32 kHz Crystal Xin

20 MHz Crystal Xin

20 MHz Crystal Xout

I

O

NO RESET

TYPE

I/O

PULL DESCRIPTION

22 RESETn

1

I

UP

Reset Input, Active Low

NO JTAG

23 TDI

TYPE

I/O

PULL DESCRIPTION

1

I

O

I

UP

-

JTAG Test Data In

24 TDO

25 TMS

26 TCK

JTAG Test Data Out

JTAG Test Mode Select

UP

I

DOWN JTAG Test Clock

NO GPIOS (NOTE 15)

TYPE

I/O

PULL DESCRIPTION

27 DP4 (GPIO23)

1

I/O

-

General Purpose Digital I/O

33 DP3 (GPIO22)

I/O

I

-

General Purpose Digital I/O

External Input to 8-Bit Timer/Counter

TIMER8_EXT

34 DP2 (GPIO21)

1

I/O

-

General Purpose Digital I/O

LPTIMER_EXT

I

External Input to Low Power Timer/Counter

36 DP0 (GPIO0)

SPIM_SS_2n

I/O

O

-

General Purpose Digital I/O

SPI Master Slave Select 2, Active Low

48 DP1 (GPIO20)

I/O

I

-

General purpose digital I/O

External Input to 16-Bit Timer/Counter

TIMER16_EXT

NO SPECIAL PURPOSE

TYPE

I/O

PULL DESCRIPTION

35 SLEEPn

GPIO14

1 (Note 14)

I

-

Deep Sleep, Active Low

General Purpose Digital I/O

I/O

49 PWM0

TIMER16_OUT

GPIO16

2

O

I/O

-

Pulse Width Modulator 0

16-Bit Timer/Counter Match Output/PWM Output

General Purpose Digital I/O

72 TIMEn

1 (Note 14)

I

-

Time Capture Request, Active Low

NO CLI

TYPE

I/O

O

PULL DESCRIPTION

37 UARTC0_TX

38 UARTC0_RX

2

1

-

CLI UART 0 Transmit

CLI UART 0 Receive

I

UP

5800whmfa

18

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

pin FuncTions

Pin functions shown in italics are currently not supported in software.

NO SPI MASTER

TYPE

I/O

PULL DESCRIPTION

39 SPIM_MISO

GPIO11

1

I

-

SPI Master (MISO) Master In Slave Out Port

General Purpose Digital I/O

I/O

41 SPIM_MOSI

GPIO10

2

1

O

-

SPI Master (MOSI) Master Out Slave In Port

General Purpose Digital I/O

I/O

43 SPIM_SCK

GPIO9

O

I/O

-

SPI Master (SCK) Serial Clock Port

General Purpose Digital I/O

46 SPIM_SS_1n

GPIO13

O

I/O

-

SPI Master Slave Select 1, Active Low

General Purpose Digital I/O

47 SPIM_SS_0n

GPIO12

O

I/O

-

SPI Master Slave Select 0, Active Low

General Purpose Digital I/O

NO IPCS SPI/FLASH PROGRAMMING (NOTE 16) TYPE

I/O

PULL DESCRIPTION

40 IPCS_MISO

TIMER16_OUT

GPIO6

2

1

O

-

SPI Flash Emulation (MISO) Master In Slave Out Port

16-Bit Timer/Counter Match Output/PWM Output

I/O

General Purpose Digital I/O

42 IPCS_MOSI

TIMER16_EXT

GPIO5

I

-

SPI Flash Emulation (MOSI) Master Out Slave In Port

External Input to 16-bit Timer/Counter

General Purpose Digital I/O

I/O

44 IPCS_SCK

TIMER8_EXT

GPIO4

I

-

SPI Flash Emulation (SCK) Serial Clock Port

External Input to 8-Bit Timer/Counter

General Purpose Digital I/O

I/O

45 IPCS_SSn

LPTIMER_EXT

GPIO3

I

-

SPI Flash Emulation Slave Select, Active Low

External Input to Low Power Timer/Counter

General Purpose Digital I/O

I/O

55 FLASH_P_ENn

I

UP

Flash Program Enable, Active Low

2

NO I C/1-WIRE/SPI SLAVE

TYPE

I/O

PULL DESCRIPTION

50 SPIS_MISO

UARTC1_TX

1_WIRE

2

O

I/O

-

SPI Slave (MISO) Master In Slave Out Port

CLI UART 1 Transmit

1 Wire Master

51 SPIS_MOSI

UARTC1_RX

GPIO26

1

I

-

SPI Slave (MOSI) Master Out Slave In Port

CLI UART 1 Receive

General Purpose Digital I/O

I/O

52 SPIS_SCK

SCL

2

I

-

SPI Slave (SCK) Serial Clock Port

I2C Serial Clock

I/O

53 SPIS_SSn

SDA

I

-

SPI Slave Select, Active Low

I2C Serial Data

I/O

NO API UART

TYPE

I/O

I

PULL DESCRIPTION

66 UART_RX_RTSn

67 UART_RX_CTSn

68 UART_RX

1 (Note 14)

-

UART Receive (RTS) Request to Send, Active Low

1

O

I

UART Receive (CTS) Clear to Send, Active Low

UART Receive

1 (Note 14)

69 UART_TX_RTSn

70 UART_TX_CTSn

71 UART_TX

1

O

I

UART Transmit (RTS) Request to Send, Active Low

UART Transmit (CTS) Clear to Send, Active Low

UART Transmit

1 (Note 14)

2

O

Note 14: These inputs are always enabled and must be driven or pulled to

a valid state to avoid leakage.

Note 16: Embedded programming over the IPCS SPI bus is only avaliable

when RESETn is asserted.

Note 15: See also pins 40, 42, 44, and 45 for additional GPIO ports.

5800whmfa

19

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

pin FuncTions

VSUPPLY: System and I/O Power Supply. Provides power

to the chip including the on-chip DC/DC converters. The

digital-interface I/O voltages are also set by this voltage.

Bypasswith2.2µFand0.1µFtoensuretheDC/DCconvert-

ers operate properly.

ANTENNA: Multiplexed Receiver Input and Transmitter

Output Pin. The impedance presented to the antenna

pin should be 50Ω, single-ended with respect to paddle

ground. To ensure regulatory compliance of the final

productpleaseseetheEternaIntegrationGuideforfiltering

requirements. The antenna pin must not have a DC path to

ground; AC blocking must be included if a DC-grounded

antenna is used.

VDDPA:PA-ConverterBypassPin. A0.47µFcapshouldbe

connected from VDDPA to ground with as short a trace as

feasible. Do not connect anything else to this pin.

LNA_ENABLE, RADIO_TX, RADIO_TXn: Control signals

generatedbytheautonomousMACsupportingtheintegra-

tionofanexternalLNA/PA.SeetheEternaExtendedRange

Reference Design for implementation details.

VDDA: Analog-Regulator Bypass Pin. A 0.1µF cap should

be connected from VDDA to ground with as short a trace

as feasible. Do not connect anything else to this pin.

VCORE:Core-RegulatorBypassPin. A56nFcapshouldbe

connected from VCORE to ground with as short a trace as

feasible. Do not connect anything else to this pin.

AI_0, AI_1, AI_2, AI_3: Analog Inputs. These pins are

multiplexed to the analog input chain. The analog input

chain, as shown in Figure 8, is software-configurable

and includes a variable-gain amplifier, an offset-DAC for

adjusting input range, and a 10b ADC. Valid input range

is between 0 to 1.8V.

VOSC:Oscillator-RegulatorBypassPin.A56nFcapshould

be connected from VOSC to ground with as short a trace

as feasible. Do not connect anything else to this pin.

VPP: Manufacturing Test port for internal regulator. Do

not connect anything to this pin.

ANALOG INPUT

10-BIT ADC

3-BIT

VGA

VPRIME: Primary-Converter Bypass Pin. A 0.22µF cap

shouldbeconnectedfromVPRIMEtogroundwithasshort

atraceasfeasible.Donotconnectanythingelsetothispin.

+

4-BIT DAC

5800WHM F08

VBGAP: Bandgap Reference Output. Used for testing and

calibration. Do not connect anything to this pin.

Figure 8. Analog Input Chain

CAP_PA_1P, CAP_PA_1M through CAP_PA_4P, CAP_

PA_4M: Dedicated Power-Amplifier DC/DC Converter

Capacitor Pins. These pins are used when the radio is

transmitting to efficiently convert VSUPPLY to the proper

voltage for the power amplifier. A 56nF cap should be con-

nected between each P and M pair. Trace length should

be as short as feasible.

OSC_32K_XOUT: Output Pin for the 32kHz Oscillator.

Connect to 32kHz quartz crystal. The OSC_32K_XOUT

and OSC_32K_XIN traces must be well-shielded from

other signals, both on the same PCB layer and lower PCB

layers, as shown in Figure 9.

OSC_32K_XIN: Input for the 32kHz Oscillator. Con-

nect to 32kHz quartz crystal.The OSC_32K_XOUT and

OSC_32K_XIN traces must be well-shielded from other

signals, both on the same PCB layer and lower PCB layers,

as shown in Figure 9.

CAP_PRIME_1P, CAP_PRIME_1M through CAP_

PRIME_4P, CAP_PRIME_4M: Primary DC/DC Converter

Capacitor Pins. These pins are used when the device is

awaketoefficientlyconvertVSUPPLYtothepropervoltage

for the three on-chip low-dropout regulators. A 56nF cap

should be connected between each P and M pair. Trace

length should be as short as feasible.

OSC_20M_XOUT: Output for the 20MHz Oscillator.

Connect only to a supported 20MHz quartz crystal. The

OSC_20M_XOUT and OSC_20M_XIN traces must be

well-shielded from other signals, both on the same PCB

layer and lower PCB layers, as shown in Figure 9. See the

Eterna Integration Guide for supported crystals.

5800whmfa

20

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

pin FuncTions

OSC_20M_XIN: Input for the 20MHz Oscillator. Connect

onlytoasupported20MHzquartzcrystal. TheOSC_20M_

XOUT and OSC_20M_XIN traces must be well-shielded

from other signals, both on the same PCB layer and lower

PCB layers, as shown in Figure 9.

RADIO_INHIBIT: RADIO_INHIBIT provide a mechanism

for an external device to temporarily disable radio opera-

tion. Failure to observe the timing requirements defined

in the Radio_Inhibit AC Characteristics table, may result

in unreliable network operation. In designs where the

RADIO_INHIBIT function is not needed the input must

either be tied, pulled or actively driven low to avoid excess

leakage.

RESETn:Theasynchronousresetsignalisinternallypulled

up. Resetting Eterna will result in the ARM Cortex M3

rebooting and loss of network connectivity. Use of this

signal for resetting Eterna is not recommended except

during power-on and in-circuit programming.

TMS, TCK, TDI, TDO: JTAG Port Supporting Software

Debug and Boundary Scan. An IEEE Std 1149.1b-1994

compliantBoundaryScanDefinitionLanguage(BDSL)file

for the WR QFN72 package can be found here.

SLEEPn: The SLEEPn function is not currently supported

in software. The SLEEPn input must either be tied, pulled

or actively driven high to avoid excess leakage.

UART_RX,UART_RX_RTSn,UART_RX_CTSn,UART_TX,

UART_TX_RTSn,UART_TX_CTSn:TheAPIUARTinterface

includes bi-directional wake up and flow control. Unused

inputsignalsmustbedrivenorpulledtotheirinactivestate.

TIMEn: Strobing the TIMEn input is the most accurate

method to acquire the network time maintained by Eterna.

Eternalatchesthenetworktimestampwithsub-microsec-

ond resolution on the rising edge of the TIMEn signal and

produces a packet on the API serial port containing the

timing information.

UARTC0_RX, UARTC0_TX: The CLI UART provides a

mechanism for monitoring, configuration and control of

Eterna during operation. For a complete description of the

supported commands see the SmartMesh WirelessHART

Mote CLI Guide.

Figure 9. PCB Top Metal Layer Shielding of Crystal Signals

FLASH_P_ENn, IPCS_SSn, IPCS_SCK, IPCS_MISO,

IPCS_SSn: The In-circuit Programming Control System

(IPCS)busenablesin-circuitprogrammingofEterna’sflash

memory. IPCS_SCK is a clock and should be terminated

appropriately for the driving source to prevent overshoot

and ringing.

5800whmfa

21

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

operaTion

The LTC5800 is the world’s most energy-efficient IEEE

802.15.4 compliant platform, enabling battery and en-

ergy harvested applications. With a powerful 32-bit ARM

Cortex™-M3,best-in-classradio,flash,RAMandpurpose-

built peripherals, Eterna provides a flexible, scalable and

robust networking solution for applications demanding

minimal energy consumption and data reliability in even

the most challenging RF environments.

POWER SUPPLY

Eterna is powered from a single pin, VSUPPLY, which

powers the I/O cells and is also used to generate internal

supplies.Eterna’stwoon-chipDC/DCconvertersminimize

energyconsumptionwhilethedeviceisawake.Toconserve

power the DC/DC converters are disabled when the device

isinlow-powerstate.Powersupplyconditioning,including

the two integrated DC/DC converters and three integrated

low-dropout regulators, provides excellent rejection of

supply noise. Eterna’s operating supply voltage range is

highenoughtosupportdirectconnectiontolithium-thionyl

Shown in Figure 10, Eterna integrates purpose-built

peripherals that excel in both low operating-energy con-

sumption and the ability to rapidly and precisely cycle

between operating and low-power states. Items in the

gray shaded region labeled "Analog Core” correspond to

the analog/RF components.

chloride (Li-SOCl ) sources and wide enough to support

battery operation over a broad temperature range.

2

32kHz

DIGITAL CORE

ANALOG CORE

32kHz, 20MHz

TIMERS

SCHED

VOLTAGE REFERENCE

PRIMARY

CORE REGULATOR

DC/DC

SRAM

72kB

CONVERTER

CLOCK REGULATOR

PMU/

RELAXATION

CLOCK

FLASH

ANALOG REGULATOR

OSCILLATOR

CONTROL

512kB

PA

DC/DC

CONVERTER

PoR

FLASH

CONTROLLER

20MHz

802.15.4

MOD

LPF

DAC

AES

PA

CODE

802.15.4

FRAMING

DMA

PLL

AUTO

MAC

802.15.4

DEMOD

SYSTEM

BPF

PPF

LNA

ADC

LIMITER

AGC

RSSI

BAT

LOAD

IPCS

SPI

SLAVE

CLI

UART

(2 PIN)

API

UART

(6 PIN)

10-BIT

ADC

CTRL

VGA

PTAT

4-BIT

DAC

5800WHM F10

Figure 10. Eterna Block Diagram

5800whmfa

22

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

operaTion

SUPPLY MONITORING AND RESET

The use of TIMEn has the advantage of being more accu-

rate. The value of the timestamp is captured in hardware

relative to the rising edge of TIMEn. If an API request is

used,duetopacketprocessing,thevalueofthetimestamp

may be captured several milliseconds after receipt of the

packet. See the TIMEn AC Characteristics section for the

TIMEn function’s definition and specifications.

Eterna integrates a Power-on reset (PoR) circuit. As the

RESETn input pin is nominally configured with an internal

pull-up resistor, no connection is required. For a graceful

shutdown, the software and the networking layers should

be cleanly halted via API commands prior to assertion

of the RESETn pin. See the SmartMesh WirelessHART

Mote API Guide for details on the disconnect and reset

commands. Eternaincludesasoftbrown-outmonitorthat

fully protects the flash from corruption in the event that

power is removed while writing to flash. Integrated flash

supervisoryfunctionality,inconjunctionwithafaulttolerant

file system, yields a robust nonvolatile storage solution.

TIME REFERENCES

Eterna includes three clock sources: an internal relaxation

oscillator,alowpoweroscillatordesignedfora32.768kHz

crystal, and the radio reference oscillator designed for a

20MHz crystal.

Relaxation Oscillator

PRECISION TIMING

The relaxation oscillator is the primary clock source for

Eterna, providing the clock for the CPU, memory subsys-

tems, and all peripherals. The internal relaxation oscillator

is dynamically calibrated to 7.3728MHz. The internal re-

laxation oscillator typically starts up in a few μs, providing

anexpedient,low-energymethodfordutycyclingbetween

active and low power states. Quick start-up from the doze

state,definedintheStateDiagramsection,allowsEternato

wakeupandreceivedataovertheUARTandSPIinterfaces

by simply detecting activity on the appropriate signals.

Eterna’s unique low power dedicated timing hardware and

timingalgorithmsprovidesasignificantimprovementover

competing 802.15.4 product offerings. This functionality

providestimingprecisiontwotothreeordersofmagnitude

better than any other low-power solution available at the

timeofpublication.Improvedtimingaccuracyallowsmotes

to minimize the amount of radio listening time required

to ensure packet reception thereby lowering even further

the power consumed by SmartMesh networks. Eterna’s

patented timing hardware and timing algorithms provide

superior performance over rapid temperature changes,

further differentiating Eterna’s reliability when compared

with other wireless products. In addition, precise timing

enablesnetworkstoreducespectraldeadtime, increasing

total network throughput.

32.768kHz Crystal

Once Eterna is powered up and the 32.768kHz crystal

source has begun oscillating, the 32.768kHz crystal re-

mains operational while in the Active state, and is used as

thetimingbasiswheninDozestate. SeetheStateDiagram

section, for a description of Eterna’s operational states.

APPLICATION TIME SYNCHRONIꢀATION

In addition to coordinating time slots across the network,

which is transparent to the user, Eterna’s timing manage-

mentisusedtosupporttwomechanismstosharenetwork

time. Having an accurate, shared, network-wide time base

enables events to be accurately time stamped or tasks to

be performed in a synchronized fashion across a network.

Eterna will send a time packet through its serial interface

when one of the following occurs:

20MHz Crystal

The 20MHz crystal source provides a frequency reference

for the radio, and is automatically enabled and disabled by

Eterna as needed. Eterna requires specific characterized

20MHz crystal references. See the the Eterna Integration

Guideforacompletelistofthecurrentlysupported20MHz

crystals.

n

Eterna receives an API request to read time

n

The TIMEn signal is asserted

5800whmfa

23

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

operaTion

RADIO

In the Figures accompanying the protocol descriptions,

signals driven by the companion processor are drawn

in black and signals driven by Eterna are drawn in blue.

Eterna includes the lowest-power commercially available

2.4GHz IEEE 802.15.4 radio by a substantial margin.

(Please refer to the Radio Specifications section for

powerconsumptionnumbers.).Eterna’sintegratedpower

amplifier is calibrated and temperature-compensated to

consistentlyprovidepoweratalimitsuitableforworldwide

radio certifications. Additionally, Eterna uniquely includes

a hardware-based autonomous MAC that handles precise

sequencing of peripherals, including the transmitter, the

receiver, and advanced encryption standard (AES) pe-

ripherals.Thehardware-basedautonomousmediaaccess

controller (MAC) minimizes CPU activity, thereby further

decreasing power consumption.

UART Mode 2

UART Mode 2 provides the most energy-efficient method

for operating Eterna’s API UART. UART Mode 2 requires

the use of all six UART signals, but does not require

adherence to the minimum inter-packet delay as defined

in the UART AC Characteristics section. UART Mode 2

incorporates edge-sensitive flow control, at either 9600

or 115200 baud. Packets are HDLC encoded with one

stop bit and no parity bit. The flow control signals for

Eterna’s API receive path are shown in Figure 11. Trans-

fers are initiated by the companion processor asserting

UART_RX_RTSn. Eterna then responds by enabling the

UART and asserting UART_RX_CTSn. After detecting the

assertion of UART_RX_CTSn the companion processor

sends the entire packet. Following the transmission of

the final byte in the packet, the companion processor

negates UART_RX_RTSn and waits until the negation of

UART_RX_CTSnbeforeassertingUART_RX_RTSnagain.

UARTS

The principal network interface is through the application

programming interface (API) UART. A command-line

interface (CLI) is also provided for support of test and

debug functions. Both UARTs sense activity continuously,

consuming virtually no power until data is transferred and

automatically returning to their lowest power state after

the conclusion of a transfer. The definition for packet

encoding on the API UART interface can be found in the

SmartMesh WirelessHART Mote API Guide and the CLI

command definitions can be found in the SmartMesh

WirelessHART Mote CLI Guide.

The flow control signals for Eterna’s API transmit path

are shown in Figure 12. Transfers are initiated by Eterna

asserting UART_TX_RTSn. The companion processor

responds by asserting UART_TX_CTSn when ready to

receive data. After detecting the falling edge of UART_

TX_CTSn Eterna sends the entire packet. Following

the transmission of the final byte in the packet Eterna

negates UART_TX_RTSn and waits until the negation of

UART_TX_CTSn before asserting UART_TX_RTSn again.

The companion processor may negate UART_TX_CTSn

any time after the first byte is transferred provided the

timeout from UART_TX_RTSn to UART_TX_CTSn,

API UART Protocols

The API UART supports multiple modes with the goal of

supporting a wide range of companion multipoint control

units (MCUs) while reducing power consumption of the

system. Asageneralrule, higherserialdataratestranslate

intolowerenergyconsumptionforbothendpoints.TheAPI

UARTreceiveprotocolincludestwoadditionalsignalsinad-

ditiontoUART_RX:UART_RX_RTSnandUART_RX_CTSn.

The transmit half of the API UART protocol includes two

additionalsignalsinadditiontoUART_TX:UART_TX_RTSn

and UART_TX_CTSn. The two supported protocols are

referred to as UART Mode 2 and UART Mode 4. Mode

setting is controlled via the Fuse Table.

t

is met.

END_TX_RTS to TX_CTS

UART_RX_RTSn

UART_RX_CTSn

UART_RX

BYTE 0

BYTE 1

5800WHM F11

Figure 11. UART Mode 2 Receive Flow Control

5800whmfa

24

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

operaTion

packet.Afterdetectingalogic‘0’onUART_TX_CTSnEterna

sends the entire packet. Following the transmission of the

final byte in the packet Eterna negates UART_TX_RTSn

and waits for a minimum period defined in the UART AC

Characteristics section before asserting UART_TX_RTSn

again.

UART_TX_RTSn

UART_TX_CTSn

UART_TX

BYTE 0

BYTE 1

5800WHM F12

Figure 12. UART Mode 2 Transmit Flow Control

For details on the timing of the UART protocol, see the

UART AC Characteristics section.

UART_TX_RTSn

CLI UART

UART_TX_CTSn

UART_TX

The command line interface (CLI) UART port is a two

wire protocol (TX and RX) that operates at a fixed 9600

baud rate with one stop bit and no parity. The CLI UART

interfaceisintendedtosupportcommandlineinstructions

and response activity.

BYTE 0

BYTE 1

5800WHM F13

Figure 13. UART Mode 4 Transmit Flow Control

UART Mode 4

UART Mode 4 incorporates level-sensitive flow control

on the TX channel and requires no flow control on the

RX channel, supporting both 9600 and 115200 baud.

The use of level-sensitive flow control signals enables

data rates above 9600 baud with the option of using a

reduced set of the flow control signals; however, Mode

4 has specific limitations. First, The use of the RX flow

control signals (UART_RX_RTSn and UART_RX_CTSn)

for Mode 4 are optional provided the use is limited to the

industrial temperature range (–40°C to 85°C); otherwise,

the flow control is mandatory. If RX flow control signals

are not used, UART_RX_RTSn should be tied to VSUPPLY

(inactive)andUART_RX_CTSnshouldbeleftunconnected.

Second, unless the companion processor is always ready

toreceiveapacket, thecompanionprocessormustnegate

UART_TX_CTSn prior to the end of the current packet.

Failure to negate UART_TX_CTSn prior to the end of a

packet may result in back to back packets. Third , the

AUTONOMOUS MAC

Eterna was designed as a system solution to provide a

reliable, ultralow power, and secure network. A reliable

network capable of dynamically optimizing operation

over changing environments requires solutions that are

far too complex to completely support through hardware

acceleration alone. As described in the Precision Timing

section,propertimemanagementisessentialforoptimizing

a solution that is both low power and reliable. To address

theserequirementsEternaincludestheAutonomousMAC,

which incorporates a co-processor for controlling all of

the time-critical radio operations. The Autonomous MAC

provides two benefits: first, preventing variable software

latency from affecting network timing and second, greatly

reducing system power consumption by allowing the CPU

to remain inactive during the majority of the radio activity.

The Autonomous MAC, provides software-independent

timing control of the radio and radio-related functions,

resultinginsuperiorreliabilityandexceptionallylowpower.

companion processor must wait at least t

RX_RTS to RX_CTS

betweentransmittingpacketsonUART_RX.SeetheUART

AC Characteristics section for complete timing specifica-

tions. Packets are HDLC encoded with one stop bit and

no parity bit. The flow control signals for the TX channel

are shown in Figure 13. Transfers are initiated by Eterna

asserting UART_TX_RTSn. The UART_TX_CTSn signal

may be actively driven by the companion processor when

ready to receive a packet or UART_TX_CTSn may be tied

lowifthecompanionprocessorisalwaysreadytoreceivea

SECURITY

Network security is an often overlooked component of

a complete network solution. Proper implementation

of security protocols is significant in terms of both en

gineering effort and market value in an OEM product.

Eterna system solutions provide a FIPS-140 compliant

-

5800whmfa

25

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

operaTion

encryption scheme that includes authentication and en-

cryptionattheMACandnetworklayerswithseparatekeys

for each mote. This not only yields end-to-end security,

but if a mote is somehow compromised, communication

from other motes is still secure. A mechanism for secure

key exchange allows keys to be kept fresh. To prevent

physical attacks, Eterna includes hardware support for

electronically locking devices, thereby preventing access

to Eterna’s flash and RAM memory and thus the keys and

code stored therein. This lock-out feature also provides

a means to securely unlock a device should support of a

product require access. For details see the Board Specific

Configuration Guide.

images are loaded via the In-Circuit Programming Control

System (IPCS) SPI interface. Sequencing of RESETn and

FLASH_P_ENn, as described in the Flash SPI Slave AC

Characteristics section, places Eterna in a state emulating

aserialflash tosupportin-circuitprogramming.Hardware

and software for supporting development and production

programming of devices is described in the Eterna Serial

Programmer Guide. The serial protocol, SPI, and tim-

ing parameters are described in the Flash SPI Slave AC

Characteristics section.

FLASH DATA RETENTION

Eterna contains internal flash (non-volatile memory) to

store calibration results, unique ID, configuration settings

and software images. Flash retention over the operating

temperature range. See the Electrical Characteristics and

Absolute Maximum Ratings sections.

TEMPERATURE SENSOR

Eterna includes a calibrated temperature sensor on chip.

The temperature readings are available locally through

Eterna’s serial API, in addition to being available via the

network manager. The performance characteristics of the

temperaturesensorcanbefoundintheTypicalPerformance

Characteristics section.

Non destructive storage above the operating temperature

range of –55°C to 105°C is possible; however, this may

result in a degradation of retention characteristics.

Thedegradationinflashretentionfortemperatures>105°C

can be approximated by calculating the dimensionless

acceleration factor using the following equation.

RADIO INHIBIT

The RADIO_INHIBIT input enables an external control-

ler to temporarily disable the radio software drivers (for

example, to take a sensor reading that is susceptible to

radio interference). When RADIO_INHIBIT is asserted

the software radio drivers will disallow radio operations

includingclearchannelassessment,packettransmissions,

or packet receptions. If the current timeslot is active when

RADIO_INHIBIT is asserted the radio will be disabled after

the present operation completes. The Radio Inhibit func-

tion is not enabled by default and must be enabled by the

FuseTable. SeetheBoardSpecificConfigurationGuidefor

details on creating a Fuse Table. For details on the timing

associated with RADIO_INHIBIT see the Radio_Inhibit AC

Characteristics section.

⎡

⎢

⎤

⎥

⎦

⎛

⎜

⎝

⎞

⎟

⎠

⎛

⎞

⎟

⎠

Ea

k

1

•

−

⎜

AF = e^⎣⎝

T

+273

T

+273

USE

STRESS

where:

AF = acceleration factor

Ea = activation energy = 0.6eV

–5

k = 8.625 • 10 eV/°K

T

= is the specified temperature retention in °C

= actual storage temperature in °C

USE

STRESS

Example: Calculate the effect on retention when storing

at a temperature of 125°C.

T

= 125°C

STRESS

FLASH PROGRAMMING

= 85°C

USE

Thisproductisprovidedwithoutsoftwareprogrammedinto

the device. OEMs will need to program software images

duringdevelopmentandmanufacturing.Eterna’ssoftware

AF = 7.1

5800whmfa

26

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

operaTion

POWER-ON

RESET

VSUPPLY > PoR

RESETn LOW AND

FLASH_P_ENn LOW

LOAD FUSE

SETTINGS

SET RESETn HIGH AND

FLASH_P_ENn HIGH

FOR 125µs, THEN

SERIAL FLASH

EMULATION

SET RESETn LOW

RESETn LOW AND

FLASH_P_ENn HIGH

RESETn HIGH

AND

FLASH_P_ENn

HIGH

RESET

DEASSERT

RESETn

BOOT

START-UP

ASSERT RESETn ASSERT RESETn

ASSERT RESETn

CPU AND

PERIPHERALS

INACTIVE

CPU

ACTIVE

DEEP SLEEP

DOZE

CPU

INACTIVE

LOW POWER SLEEP

COMMAND

HW OR PMU EVENT

OPERATION

INACTIVE

5800WHM F14

Figure 14. Eterna State Diagram

5800whmfa

27

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

operaTion

So the overall retention of the flash would be degraded

by a factor of 7.1, reducing data retention from 20 years

at 85°C to 2.8 years at 125°C.

FLASH_P_ENnpinisnotassertedbutRESETnis asserted,

Eterna automatically reduces its energy consumption to

a minimum until RESETn is released. Once RESETn is

de-asserted, Eterna goes through a boot sequence, and

then enters the active state.

STATE DIAGRAM

In order to provide capabilities and flexibility in addition

to ultra low power, Eterna operates in various states, as

shown in Figure 14. State transitions shown in red are

not recommended.

Serial Flash Emulation

When both RESETn and FLASH_P_ENn are asserted,

Eterna disables normal operation and enters a mode to

emulate the operation of a serial flash. In this mode, its

flash can be programmed.

Fuse Table

Operation

Eterna’s Fuse Table is a 2kB page in flash that contains

two data structures. One structure supports hardware

configuration immediately following power-on reset or

the assertion of RESETn. The second structure supports

configuration of software board support parameters.

Fuse Tables are generated via the Fuse Table application

described in the Board Specific Configuration Guide.

HardwareconfigurationofI/Oimmediatelyfollowingpower-

on reset provides a method to minimize leakage due to

floating nets prior to software configuration. I/O leakage

can contribute hundreds of microamperes of leakage

per input, potentially stressing current limited supplies.

Examples of software board support parameters include

setting of UART modes, clock sources and trim values.

Fuse Tables are loaded into flash using the same software

and in-circuit programmer used to load software images

as described in the Eterna Serial Programmer Guide.

Once Eterna has completed start-up, Eterna transitions to

the operational group of states (active/CPU active, active/

CPU inactive, and doze). There, Eterna cycles between the

various states, automatically selecting the lowest pos-

sible power state while fulfilling the demands of network

operation.

Active State

In the active state, Eterna’s relaxation oscillator is running

and peripherals are enabled as needed. The ARM Cortex-

M3cyclesbetweenCPU-activeandCPU-inactive(referred

to in the ARM Cortex-M3 literature as sleep now mode).

Eterna’s extensive use of DMA and intelligent peripherals

that independently move Eterna between active state and

doze state minimizes the time the CPU is active, signifi-

cantly reducing Eterna’s energy consumption.

Start-Up

Doze State

Start-up occurs asaresult ofeither crossingthepower-on

reset threshold or asserting RESETn. After the comple-

tion of power-on reset or the falling edge of an internally

synchronized RESETn, Eterna loads its Fuse Table which,

as described in the previous section, includes configuring

I/O direction. In this state, Eterna checks the state of the

FLASH_P_ENn and RESETn pins and enters the serial

flash emulation mode if both signals are asserted. If the

The doze state consumes orders of magnitude less cur-

rent than the active state and is entered when all of the

peripherals and the CPU are inactive. In the doze state

Eterna’s full state is retained, timing is maintained, and

Eterna is configured to detect, wake, and rapidly respond

to activity on I/Os (such as UART signals and the TIMEn

pin). In the doze state the 32.768kHz oscillator and as-

sociated timers are active.

5800whmfa

28

For more information www.linear.com/LTC5800-WHM

LTC5800-WHM

applicaTions inForMaTion

REGULATORY AND STANDARDS COMPLIANCE

This product has been specifically designed to utilize

RoHS-compliant materials and to eliminate or reduce the

use of restricted materials to comply with 2002/95/EC.

Radio Certification

Eterna is suitable for systems targeting compliance with

worldwide radio frequency regulations: ETSI EN 300 328

and EN 300 440 class 2 (Europe), FCC CFR47 Part 15

(US), and ARIB STD-T66 (Japan). Application Program-

ming Interfaces (APIs) supporting regulatory testing are

provided on both the API and CLI UART interfaces. The

Eterna Certification User Guide provides:

The RoHS-compliant design features include:

n

RoHS-compliant solder for solder joints

n

RoHS-compliant base metal alloys

n

RoHS-compliant precious metal plating

n

RoHS-compliant cable assemblies and connector

choices

n

Reference information required for certification

n

Lead-free QFN package

n

Test plans for common regulatory test cases

n

Halogen-free mold compound

n

Example CLI calls

n

RoHS-compliant and 245°C re-flow compatible

n

Sample manual language and example label

Note: Customers may elect to use certain types of lead-

free solder alloys in accordance with the European Com-

munity directive 2002/95/EC. Depending on the type of

solder paste chosen, a corresponding process change to

optimize reflow temperatures may be required.

Compliance to Restriction of Hazardous Substances

(RoHS)

RestrictionofHazardousSubstances(RoHS)isadirective

that places maximum concentration limits on the use of

+6

cadmium (Cd), lead (Pb), hexavalent chromium (Cr ),

SOLDERING INFORMATION

mercury (Hg), Polybrominated Biphenyl (PBB), and Poly-

brominated Diphenyl Ethers (PBDE). Linear Technology is

committed to meeting the requirements of the European

Community directive 2002/95/EC.

EternaissuitableforbotheutecticPbSnandRoHS-6reflow.

The maximum reflow soldering temperature is 260°C. A

moredetaileddescriptionoflayoutrecommendations, as-

sembly procedures and design considerations is included

in the Eterna Integration Guide.


型号：	LTC5800HWR-WHMA#PBF
厂家：	Linear
描述：	LTC5800-WHM - SmartMesh WirelessHART Mote-on-Chip; Package: QFN; Pins: 72; Temperature Range: -40°C to 125°C 无线电信电信集成电路
文件：	总32页 (文件大小：1027K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC5800HWR-WHMA#PBF [Linear]

相关型号：

LTC5800IWR-IPMA#PBF

LTC5800IWR-IPRB#PBF

LTC5800IWR-WHMA#PBF

LTC5800WR

LTC5836E

LTC5836G

LTC5836HR

LTC5836P

LTC5836R

LTC5836Y

LTC5837E

LTC5837G