LTC6241IDD#PBF [Linear]
LTC6241 - Dual 18MHz, Low Noise, Rail-to-Rail Output, CMOS Op Amp; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LTC6241IDD#PBF |
| 厂家： | 
Linear |
| 描述： | LTC6241 - Dual 18MHz, Low Noise, Rail-to-Rail Output, CMOS Op Amp; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C |
| 文件： | 总20页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2450-1
Easy-to-Use, Ultra-Tiny
16-Bit ΔΣ ADC
FEATURES
DESCRIPTION
The LTC®2450-1 is a low power, ultra-tiny 16-bit analog-
to-digital converter designed for space constrained ap-
plications requiring 16-bit performance. The LTC2450-1
uses a single 2.7V to 5.5V supply, accepts a single-ended
analog input voltage, and communicates through an SPI
interface. It includes an integrated oscillator that does
not require any external components. The delta-sigma
modulator converter core provides single-cycle settling
time for multiplexed applications. The converter is avail-
able in a 6-pin, 2mm × 2mm DFN package. The LTC2450-1
implements a proprietary input sampling scheme that
reducestheaverageinputsamplingcurrentseveralorders
of magnitude.
n
GND to V Single-Ended Input Range
CC
n
n
n
n
n
n
60 Conversions Per Second
0.02LSB RMS Noise
16-Bits, No Missing Codes
0.5mV Offset Error
4LSB Full-Scale Error
Single Conversion Settling Time for Multiplexed
Applications
Single Cycle Operation with Auto Shutdown
350μA Supply Current
50nA Sleep Current
Internal Oscillator—No External Components
Required
Single Supply, 2.7V to 5.5V Operation
SPI Interface
Ultra-Tiny, 2mm × 2mm DFN Package
n
n
n
n
n
n
n
The LTC2450-1 is capable of up to 60 conversions per
second and, due to the very large oversampling ratio, has
extremelyrelaxedantialiasingrequirements.Theconverter
uses its power supply voltage as the reference voltage and
the single-ended, rail-to-rail input voltage range extends
APPLICATIONS
n
from GND to V .
System Monitoring
Environmental Monitoring
CC
n
Following a conversion, the LTC2450-1 can automatically
enter a sleep mode and reduce its power to less than
500nA. At an output rate of 1Hz, the LTC2450-1 consumes
an average of less than 25μW from a 2.7V supply.
n
Direct Temperature Measurements
n
Instrumentation
n
Industrial Process Control
n
Data Acquisition
n
Embedded ADC Upgrades
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Easy Drive
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents including 6208279, 6411242, 7088280, 7164378.
TYPICAL APPLICATION
Integral Nonlinearity
3.0
2.5
2.0
2.7 TO 5.5V
1.5
10μF
0.1μF
1.0
0.5
V
0
CC
CS
CLOSE TO
CHIP
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
1k
SCK
SDO
3-WIRE SPI
INTERFACE
LTC2450-1
GND
V
IN
SENSE
0.1μF
24501 TA01
0
1.0
1.5
2.0
2.5
3.0
0.5
INPUT VOLTAGE (V)
24501 G02
24501fb
1
LTC2450-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
TOP VIEW
Supply Voltage (V ) ................................... –0.3V to 6V
CC
Analog Input Voltage (V )............–0.3V to (V + 0.3V)
IN
CC
6
5
4
SCK
SDO
CS
V
1
2
3
CC
Digital Input Voltage......................–0.3V to (V + 0.3V)
CC
7
V
IN
Digital Output Voltage ...................–0.3V to (V + 0.3V)
CC
GND
Operating Temperature Range
LTC2450C-1............................................. 0°C to 70°C
LTC2450I-1 .......................................... –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
DC PACKAGE
6-LEAD (2mm × 2mm) PLASTIC DFN
T
JMAX
= 125°C, θ = 102°C/W
JA
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
LTC2450CDC-1#TRMPBF
LTC2450IDC-1#TRMPBF
TAPE AND REEL
PART MARKING*
LCTR
LCTR
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
LTC2450CDC-1#TRPBF
LTC2450IDC-1#TRPBF
6-Lead (2mm × 2mm) Plastic DFN
6-Lead (2mm × 2mm) Plastic DFN
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The l denotes the specifications which apply over the full operating
ELECTRICAL CHARACTERISTICS
temperature range, otherwise specifications are at TA = 25°C. (Note 2)
PARAMETER
CONDITIONS
(Note 3)
MIN
TYP
MAX
UNITS
Bits
l
l
l
Resolution (No missing codes)
Integral Nonlinearity
Offset Error
16
(Note 4)
2
10
2
LSB
0.5
mV
Offset Error Drift
Gain Error
0.02
0.01
0.02
1.4
LSB/°C
% of FS
LSB/°C
l
0.02
Gain Error Drift
Transition Noise
μV
RMS
The l denotes the specifications which apply over the full operating temperature range,otherwise
ANALOG INPUT
specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
C
Input Voltage Range
IN Sampling Capacitance
IN DC Leakage Current
0
V
CC
IN
IN
0.35
pF
l
l
I
(V )
V
IN
V
IN
= GND (Note 5)
–10
–10
1
1
10
10
nA
nA
DC_LEAK IN
= V (Note 5)
CC
I
Input Sampling Current (Note 9)
50
nA
CONV
24501fb
2
LTC2450-1
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range,otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
Supply Voltage
2.7
5.5
V
CC
I
Supply Current
Conversion
Sleep
CC
l
l
CS = GND (Note 6)
350
0.05
600
0.5
μA
μA
CS = V (Note 6)
CC
The l denotes the specifications which apply over the full
DIGITAL INPUTS AND DIGITAL OUTPUTS
operating temperature range,otherwise specifications are at TA = 25°C. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
– 0.3
TYP
MAX
UNITS
V
l
l
l
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
CC
0.3
10
V
I
–10
μA
pF
V
IN
C
V
V
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage Current
10
IN
l
l
l
I = –800μA
O
V
– 0.5
CC
OH
OL
I = –1.6mA
O
0.4
10
V
I
–10
μA
OZ
The l denotes the specifications which apply over the full operating temperature
TIMING CHARACTERISTICS
range,otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
21
UNITS
ms
MHz
ns
l
l
l
l
l
l
l
l
t
f
t
t
t
t
t
t
Conversion Time
14
16.6
CONV
SCK
lSCK
hSCK
1
SCK Frequency Range
SCK Low Period
2
250
250
0
SCK High Period
ns
CS Falling Edge to SDO Low Z
CS Rising Edge to SDO High Z
CS Falling Edge to SCK Falling Edge
SCK Falling Edge to SDO Valid
(Notes 7, 8)
(Notes 7, 8)
100
100
ns
0
ns
2
100
0
ns
3
(Note 7)
100
ns
KQ
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: CS = V . A positive current is flowing into the DUT pin.
CC
Note 6: SCK = V or GND. SDO is high impedance.
CC
Note 7: See Figure 3.
Note 8: See Figure 4.
Note 9: Input sampling current is the average input current drawn from
the input sampling network while the LTC2450-1 is actively sampling the
input.
Note 2: All voltage values are with respect to GND. V = 2.7V to 5.5V
CC
unless otherwise specified.
Note 3: Guaranteed by design, not subject to test.
Note 4: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band. Guaranteed by design, test correlation and 3 point transfer curve
measurement.
24501fb
3
LTC2450-1
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
Integral Nonlinearity
Maximum INL vs Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
3.0
2.5
2.0
2.0
1.5
1.5
1.0
1.0
0.5
0.5
0
0
V
= 5V
= 3V
CC
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
V
= 4.1V
CC
V
CC
–50
25
50
TEMPERATURE (°C)
75
100
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT VOLTAGE (V)
0.5
–25
0
0
1.0
1.5
2.0
2.5
3.0
0.5
INPUT VOLTAGE (V)
24501 G01
24501 G03
24501 G02
Offset Error vs Temperature
Gain Error vs Temperature
Transition Noise vs Temperature
7
6
5
4
3
2
1
0
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.50
0.75
0.25
0
5
4
V
= 4.1V
CC
V
= 2.7V
CC
3
V
= 5V
CC
V
= 5.5V
V
= 2.7V
CC
CC
V
= 4.1V
CC
2
V
= 5.5V
CC
V
= 3V
CC
1
0
V
= 4.1V
25
CC
–1
50
TEMPERATURE (°C)
100
–50 –25
0
25
75
70 90
–50
10 30
50
–50
0
50
75
100
–30 –10
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
24501 G04
24501 G06
24501 G05
Conversion Mode Power Supply
Current vs Temperature
Transition Noise vs Output Code
500
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.50
0.75
0.25
0
T
= 25°C
A
V
= 5V
CC
400
300
200
100
0
V
= 3V
CC
V
= 4.1V
CC
V
= 5V
= 3V
CC
V
CC
0
0.40
0.60
0.80
1.00
–45 –25 –5
15
35
55
75
95
0.20
OUTPUT CODE (NORMALIZED TO FULL SCALE)
TEMPERATURE (°C)
24501 G07
24501 G08
24501fb
4
LTC2450-1
TYPICAL PERFORMANCE CHARACTERISTICS
Average Supply Power
vs Temperature, VCC = 3V
Sleep Mode Power Supply
Current vs Temperature
250
200
150
100
50
10000
1000
100
60 Hz OUTPUT SAMPLE RATE
10 Hz OUTPUT SAMPLE RATE
V
= 5V
CC
V
= 4.1V
CC
1 Hz OUTPUT SAMPLE RATE
V
= 3V
CC
0
10
–45 –25 –5
15
35
55
75
95
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
24501 G09
24501 G10
Conversion Period vs
Temperature
22
21
20
19
18
17
16
V
= 5.5V, 4.1V, 2.7V
CC
15
35
TEMPERATURE (°C)
75
95
–45 –25
–5
15
55
24501 G11
24501fb
5
LTC2450-1
PIN FUNCTIONS
V
(Pin 1): Positive Supply Voltage and Converter Refer-
SDO (Pin 5): Three-State Serial Data Output. SDO is used
for serial data output during the DATA OUTPUT state and
can be used to monitor the conversion status.
CC
ence Voltage. Bypass to GND (Pin 3) with a 10μF capacitor
in parallel with a low series inductance 0.1μF capacitor
located as close to the part as possible.
SCK(Pin6):SerialClockInput.SCKsynchronizestheserial
data output. While digital data is available (the ADC is not
in CONVERT state) and CS is LOW (ADC is not in SLEEP
state) a new data bit is produced at the SDO output pin
following every falling edge applied to the SCK pin.
V (Pin 2): Analog Input Voltage.
IN
GND (Pin 3): Ground. Connect to a ground plane through
a low impedance connection.
CS (Pin 4): Chip Select (Active LOW) Digital Input. A
LOW on this pin enables the SDO digital output. A HIGH
on this pin places the SDO output pin in a high imped-
ance state.
Exposed Pad (Pin 7): Ground. The Exposed Pad must be
soldered to the same point as Pin 3.
FUNCTIONAL BLOCK DIAGRAM
V
CC
CS
V
CC
SPI
REF +
SDO
INTERFACE
SCK
16 BIT ΔΣ
A/D
CONVERTER
V
IN
INTERNAL
OSCILLATOR
REF –
GND
24501 BD
Figure 1. Functional Block Diagram
24501fb
6
LTC2450-1
APPLICATIONS INFORMATION
While in the SLEEP state, whenever the chip select in-
put is pulled high (CS = HIGH), the LTC2450-1’s power
supply current is reduced to less than 500nA. When the
chip select input is pulled low (CS = LOW), and SCK is
maintained at a HIGH logic level, the LTC2450-1 will return
to a normal power consumption level. During the SLEEP
state, the result of the last conversion is held indefinitely
in a static register.
CONVERTER OPERATION
Converter Operation Cycle
The LTC2450-1 is a low power, delta-sigma analog-to-
digital converter with a simple 3-wire interface (see
Figure 1). Its operation is composed of three successive
states: CONVERT, SLEEP and DATA OUTPUT. The operat-
ing cycle begins with the CONVERT state, is followed
by the SLEEP state, and ends with the DATA OUTPUT
state (see Figure 2). The 3-wire interface consists of
serial data output (SDO), serial clock input (SCK), and the
active low chip select input (CS).
Upon entering the DATA OUTPUT state, SDO outputs the
most significant bit (D15) of the conversion result. During
this state, the ADC shifts the conversion result serially
through the SDO output pin under the control of the SCK
input pin. There is no latency in generating this data and
the result corresponds to the last completed conversion.
A new bit of data appears at the SDO pin following each
falling edge detected at the SCK input pin. The user can
reliably latch this data on every rising edge of the external
serial clock signal driving the SCK pin (see Figure 3).
TheCONVERTstatedurationisdeterminedbytheLTC2450-
1 conversion time (nominally 16.6 milliseconds). Once
started, this operation can not be aborted except by a low
power supply condition (V < 2.1V) which generates an
internal power-on reset signal.
CC
After the completion of a conversion, the LTC2450-1
enters the SLEEP state and remains there until both the
chip select and clock inputs are low (CS = SCK = LOW).
Following this condition the ADC transitions into the DATA
OUTPUT state.
The DATA OUTPUT state concludes in one of two different
ways.First,theDATAOUTPUTstateoperationiscompleted
once all 16 data bits have been shifted out and the clock
th
then goes low. This corresponds to the 16 falling edge
of SCK. Second, the DATA OUTPUT state can be aborted
at any time by a LOW-to-HIGH transition on the CS input.
Following either one of these two actions, the LTC2450-1
will enter the CONVERT state and initiate a new conver-
sion cycle.
POWER-ON RESET
CONVERT
SLEEP
Power-Up Sequence
When the power supply voltage V applied to the con-
CC
SCK = LOW
verter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
NO
AND
CS = LOW?
YES
WhenV risesabovethiscriticalthreshold, theconverter
CC
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2450-1 starts
a conversion cycle and follows the succession of states
described in Figure 2. The first conversion result fol-
lowing POR is accurate within the specifications of the
DATA OUTPUT
16TH FALLING
NO
YES
EDGE OF SCK
OR
24501 F02
CS = HIGH?
device if the power supply voltage V is restored within
CC
the operating range (2.7V to 5.5V) before the end of the
POR time interval.
Figure 2. LTC2450-1 State Transition Diagram
24501fb
7
LTC2450-1
APPLICATIONS INFORMATION
Input Voltage Range
Ease of Use
The ADC is capable of digitizing true rail-to-rail input sig-
nals. Ignoring offset and full-scale errors, the converter
will theoretically output an “all zero” digital result when
the input is at ground (a zero scale input) and an “all
The LTC2450-1 data output has no latency, filter settling
delay or redundant results associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog input voltages requires no special ac-
tions.
one” digital result when the input is at V (a full-scale
CC
input). In an under-range condition, for all input voltages
less than the voltage corresponding to output code 0, the
converterwillgeneratetheoutputcode0. Inanover-range
condition, for all input voltages greater than the voltage
corresponding to output code 65535 the converter will
generate the output code 65535.
The LTC2450-1 includes a proprietary input sampling
scheme that reduces the average input current several
orders of magnitude as compared to traditional delta
sigma architectures. This allows external filter networks
to interface directly to the LTC2450-1. Since the average
input sampling current is 50nA, an external RC lowpass
filter using a 1kΩ and 0.1μF results in <1LSB error.
Output Data Format
The LTC2450-1 generates a 16-bit direct binary encoded
result. It is provided, MSB first, as a 16-bit serial stream
through the SDO output pin under the control of the SCK
input pin (see Figure 3).
Reference Voltage Range
The converter uses the power supply voltage (V ) as the
CC
positive reference voltage (see Figure 1). Thus, the refer-
ence range is the same as the power supply range, which
extends from 2.7V to 5.5V. The LTC2450-1’s internal noise
level is extremely low so the output peak-to-peak noise
remains well below 1LSB for any reference voltage within
this range. Thus the converter resolution remains at 1LSB
independent of the reference voltage. INL, offset, and full-
scale errors vary with the reference voltage as indicated
by the Typical Performance Characteristics graphs. These
error terms will decrease with an increase in the reference
voltage (as the LSB size in μV increases).
During the data output operation the CS input pin must
be pulled low (CS = LOW). The data output process starts
with the most significant bit of the result being present
at the SDO output pin (SDO = D15) once CS goes low.
A new data bit appears at the SDO output pin following
every falling edge detected at the SCK input pin. The
output data can be reliably latched by the user using the
rising edge of SCK.
t
3
t
2
t
1
CS
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
1
D
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
MSB
LSB
SDO
SCK
24501 F03
t
t
t
hSCK
KQ
lSCK
Figure 3. Data Output Timing
24501fb
8
LTC2450-1
APPLICATIONS INFORMATION
Conversion Status Monitor
Serial Interface Operation Modes
The following are a few of the more common interface
operation examples. Many more valid control and serial
dataoutputoperationsequencescanbeconstructedbased
upon the above description of the function of the three
digital interface pins.
For certain applications, the user may wish to monitor
the LTC2450-1 conversion status. This can be achieved
by holding SCK HIGH during the conversion cycle. In
this condition, whenever the CS input pin is pulled low
(CS = LOW), the SDO output pin will provide an indication
of the conversion status. SDO = HIGH is an indication of
a conversion cycle in progress while SDO = LOW is an
indication of a completed conversion cycle. An example
of such a sequence is shown in Figure 4.
The modes of operation can be summarized as follows:
1) TheLTC2450-1functionswithSCKidlehigh(commonly
known as CPOL = 1) or idle low (commonly known as
CPOL = 0).
Conversionstatusmonitoring,whilepossible,isnotrequired
for LTC2450-1 as its conversion time is fixed and equal at
approximately 16.6ms (21ms maximum). Therefore, ex-
ternal timing can be used to determine the completion of a
conversion cycle.
2) After the 16th bit is read, the user can choose one of
two ways to begin a new conversion. First, one can
pull CS high (CS = ↑). Second, one can use a high-low
transition on SCK (SCK = ↓).
3) At any time during the Data Output state, pulling CS
high (CS = ↑) causes the part to leave the I/O state,
abort the output and begin a new conversion.
SERIAL INTERFACE
TheLTC2450-1transmitstheconversionresultandreceives
the start of conversion command through a synchronous
3-wire interface. This interface can be used during the
CONVERT and SLEEP states to assess the conversion
status and during the DATA OUTPUT state to read the
conversion result, and to trigger a new conversion.
4) When SCK = HIGH, it is possible to monitor the conver-
sion status by pulling CS low and watching for SDO
to go low. This feature is available only in the idle-high
(CPOL = 1) mode.
t
t
2
1
CS
SDO
SCK = HI
CONVERT
SLEEP
24501 F04
Figure 4. Conversion Status Monitoring Mode
24501fb
9
LTC2450-1
APPLICATIONS INFORMATION
Serial Clock Idle-High (CPOL = 1) Examples
the falling edge of the serial clock (SCK). A 17th clock
pulse is used to trigger a new conversion cycle.
In Figure 5, following a conversion cycle the LTC2450-1
automatically enters the low power sleep mode. The user
can monitor the conversion status at convenient intervals
using CS and SDO.
Serial Clock Idle-Low (CPOL = 0) Examples
In Figure 7, following a conversion cycle the LTC2450-1
automatically enters the low power sleep state. The user
determines data availability (and the end of conversion)
based upon external timing. The user then pulls CS low
(CS = ↓) and uses 16 clock cycles to transfer the result.
Followingthe16thrisingedgeoftheclock,CSispulledhigh
(CS = ↑), which triggers a new conversion.
CS is pulled LOW while SCK is HIGH to test whether or not
the chip is in the CONVERT state. While in the CONVERT
state, SDO is HIGH while CS is LOW. In the SLEEP state,
SDO is LOW while CS is LOW. These tests are not required
operationalstepsbutmaybeusefulforsomeapplications.
Whenthedataisavailable, theuserapplies16clockcycles
to transfer the result. The CS rising edge is then used to
initiate a new conversion.
ThetimingdiagraminFigure8isidenticaltothatofFigure 7,
except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
and the CS signal is subsequently pulled high.
The operation example of Figure 6 is identical to that of
Figure 5, except the new conversion cycle is triggered by
CS
SD0
D
15
D
D
D
D
D
1
D
0
14
13
12
2
SCK
clk
clk
clk
clk
4
clk
clk
16
1
2
3
15
CONVERT
SLEEP
LOW I
DATA OUTPUT
CONVERT
24501 F05
CC
Figure 5. Idle-High (CPOL = 1) Serial Clock Operation Example.
The Rising Edge of CS Starts a New Conversion
CS
SD0
SCK
D
1
D
D
D
D
2
D
D
0
15
14
13
12
1
clk
clk
clk
clk
4
clk
clk
clk
17
2
3
15
16
CONVERT
SLEEP
LOW I
DATA OUTPUT
CONVERT
24501 F06
CC
Figure 6. Idle-High (CPOL = 1) Clock Operation Example.
A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
24501fb
10
LTC2450-1
APPLICATIONS INFORMATION
CS
SD0
D
D
14
D
13
D
12
D
2
D
D
0
15
1
SCK
clk
1
clk
2
clk
3
clk clk
clk
clk
16
4
14
15
CONVERT
SLEEP
LOW I
DATA OUTPUT
CONVERT
24501 F07
CC
Figure 7. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
CS
SD0
D
D
14
D
13
D
12
D
D
1
D
0
15
2
SCK
clk
1
clk
clk
3
clk
4
clk
14
clk
15
clk
16
2
CONVERT
SLEEP
LOW I
DATA OUTPUT
CONVERT
24501 F08
CC
Figure 8. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
Examples of Aborting Cycle using CS
conversion operation can be triggered by pulling CS low
and then high. When CS is pulled low (CS = LOW), SDO
will output the most significant bit (D15) of the result of
the just completed conversion. While a low logic level is
maintained at SCK pin and CS is subsequently pulled high
(CS = HIGH) the remaining 15 bits of the result (D14:D0)
are discarded and a new conversion cycle starts.
For some applications the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2450-1 is in
thedataoutputstate,aCSrisingedgeclearstheremaining
databitsfrommemory,abortstheoutputcycleandtriggers
a new conversion. Figure 9 shows an example of aborting
an I/O with idle-high (CPOL = 1) and Figure 10 shows an
example of aborting an I/O with idle-low (CPOL = 0).
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal tran-
sitions on SCK can potentially create noise on the ADC
during the conversion, and thus may negatively influence
the conversion accuracy.
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 11. If SCK is maintained at a LOW
logic level, after the end of a conversion cycle, a new
24501fb
11
LTC2450-1
APPLICATIONS INFORMATION
CS
SD0
SCK
D
D
D
13
15
14
clk
clk
clk
clk
4
1
2
3
CONVERT
SLEEP
LOW I
DATA OUTPUT
CONVERT
24501 F09
CC
Figure 9. Idle-High (CPOL = 1) Clock and Aborted I/O Example
CS
SD0
D
D
D
13
15
14
SCK
clk
1
clk
clk
3
2
CONVERT
SLEEP
LOW I
DATA OUTPUT
CONVERT
24501 F10
CC
Figure 10. Idle-Low (CPOL = 0) Clock and Aborted I/O Example
CS
SD0
D
15
SCK = LOW
CONVERT
SLEEP
LOW I
DATA OUTPUT
CONVERT
24501 F11
CC
Figure 11. Idle-Low (CPOL = 0) Clock and Minimum Data Output Length Example
24501fb
12
LTC2450-1
APPLICATIONS INFORMATION
2-Wire Operation
status cannot be monitored at the SDO output. Following
a conversion cycle, the LTC2450-1 bypasses the SLEEP
state and immediately enters the DATA OUTPUT state. At
this moment the SDO pin outputs the most significant bit
(D15) of the conversion result. The user must use external
timing in order to determine the end of conversion and
resultavailability.Subsequently16clockpulsesareapplied
to SCK in order to serially shift the 16-bit result. The 16th
clock falling edge triggers a new conversion cycle.
The 2-wire operation modes, while reducing the number
of required control signals, should be used only if the
LTC2450-1 low power sleep capability is not required. In
additiontheoptiontoabortserialdatatransfersisnolonger
available. Hardwire CS to GND for 2-wire operation.
Figure 12 shows a 2-wire operation sequence which uses
anidle-high(CPOL=1)serialclocksignal. Theconversion
status can be monitored at the SDO output. Following a
conversion cycle, the ADC enters SLEEP state and the
SDO output transitions from HIGH to LOW. Subsequently
16 clock pulses are applied to the SCK input in order
to serially shift the 16 bit result. Finally, the 17th clock
pulse is applied to the SCK input in order to trigger a new
conversion cycle.
PRESERVING THE CONVERTER ACCURACY
The LTC2450-1 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line and frequency
perturbations. Nevertheless, in order to preserve the
very high accuracy capability of this part, some simple
precautions are desirable.
Figure 13 shows a 2-wire operation sequence which uses
an idle-low (CPOL = 0) serial clock signal. The conversion
CS = LOW
D
D
D
D
4
D
D
D
0
15
14
13
12
2
1
SD0
SCK
clk
clk
clk
clk
clk
clk
clk
17
1
2
3
15
16
CONVERT
SLEEP
DATA OUTPUT
CONVERT
24501 F12
Figure 12. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example
CS = LOW
SD0
D
D
14
D
D
D
D
D
0
15
13
12
2
1
SCK
clk
clk
clk
clk clk
4
clk
clk
16
1
2
3
14
15
CONVERT
DATA OUTPUT
CONVERT
24501 F13
Figure 13. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example
24501fb
13
LTC2450-1
APPLICATIONS INFORMATION
Digital Signal Levels
and to limit potential undershoot to less than 0.3V below
GND and overshoot to less than 0.3V above V .
CC
The LTC2450-1’s digital interface is easy to use. Its digital
inputs (SCK and CS) accept standard CMOS logic levels
and the internal hysteresis receivers can tolerate edge
rates as slow as 100μs. However, some considerations
are required to take advantage of the exceptional accuracy
and low supply current of this converter.
Noisy external circuitry can potentially impact the output
under 2-wire operation. In particular, it is possible to get
the LTC2450-1 into an unknown state if an SCK pulse is
missed or noise triggers an extra SCK pulse. In this situ-
ation, it is impossible to distinguish SDO = 1 (indicating
conversion in progress) from valid “1” data bits. As such,
CPOL = 1 is recommended for the 2-wire mode. The user
should look for SDO = 0 before reading data, and look
for SDO = 1 after reading data. If SDO does not return a
“0” within the maximum conversion time (or return a “1”
after a full data read), generate 16 SCK pulses to force a
new conversion.
The digital output signal SDO is less of a concern because
it is not active during the conversion cycle.
While a digital input signal is in the range 0.5V to V
CC
–0.5V, the CMOS input receiver may draw additional
current from the power supply. Due to the nature of CMOS
logic,aslowtransitionwithinthisvoltagerangemaycause
an increase in the power supply current drawn by the
converter, particularly in the low power operation mode
within the SLEEP state. Thus, for low power consumption
it is highly desirable to provide relatively fast edges for the
two digital input pins SCK and CS, and to keep the digital
Driving V and GND
CC
The V and GND pins of the LTC2450-1 converter are
CC
directly connected to the positive and negative reference
voltages, respectively. A simplified equivalent circuit is
shown in Figure 14.
input logic levels at V or GND.
CC
At the same time, during the CONVERT state, undershoot
and/or overshoot of fast digital signals connected to the
LTC2450-1 pins may affect the conversion result. Under-
shoot and overshoot can occur because of an impedance
mismatch at the converter pin combined with very fast
transitiontimes.Thisproblembecomesparticularlydifficult
when shared control lines are used and multiple reflec-
tions may occur. The solution is to carefully terminate all
transmissionlinesclosetotheircharacteristicimpedance.
Parallel termination is seldom an acceptable option in low
power systems so a series resistor between 27Ω and 56Ω
placed near the driver may eliminate this problem. The
actual resistor value depends upon the trace impedance
andconnectiontopology.Analternatesolutionistoreduce
the edge rate of the control signals, keeping in mind the
concerns regarding slow edges mentioned above.
The power supply current passing through the parasitic
layout resistance associated with these common pins will
modifytheADCreferencevoltageandthusnegativelyaffect
the converter accuracy. It is thus important to keep the
V
and GND lines quiet, and to connect these supplies
CC
through very low impedance traces.
In relation to the V and GND pins, the LTC2450-1 com-
CC
bines internal high frequency decoupling with damping
R
R
(TYP)
SW
15k
V
CC
I
LEAK
V
CC
(TYP)
15k
SW
I
I
V
V
LEAK
LEAK
CC
V
IN
C
(TYP)
EQ
Particular attention should be given to configurations in
which a continuous clock signal is applied to SCK pin dur-
ing the CONVERT state. While LTC2450-1 will ignore this
signalfromalogicpointofviewthesignaledgesmaycreate
unexpected errors depending upon the relation between
its frequency and the internal oscillator frequency. In such
a situation it is beneficial to use edge rates of about 10ns
0.35pF
CC
R
SW
(TYP)
I
LEAK
15k
24501 F14
GND
INTERNAL SWITCHING FREQUENCY = 4 MHz
Figure 14. LTC2450-1 Analog Pins Equivalent Circuit
24501fb
14
LTC2450-1
APPLICATIONS INFORMATION
elementswhichreducetheADCperformancesensitivityto
PCBlayoutandexternalcomponents.Nevertheless,thevery
highaccuracyofthisconverterisbestpreservedbycareful
low and high frequency power supply decoupling.
layout C
has typical values between 2pF and 15pF. In
PAR
addition, the equivalent circuit of Figure 15 includes the
converter equivalent internal resistor R and sampling
capacitor C .
SW
EQ
A 0.1μF, high quality, ceramic capacitor in parallel with a
10μF ceramic capacitor should be connected between the
CC
Therearesomeimmediatetrade-offsinR andC without
S
IN
needing a full circuit analysis. Increasing R and C can
S
IN
V
and GND pins, as close as possible to the package.
give the following benefits:
1) Due to the LTC2450-1’s input sampling algorithm, the
input current drawn by V during the conversion cycle
The 0.1μF capacitor should be placed closest to the ADC
package. It is also desirable to avoid any via in the circuit
IN
path starting from the converter V pin, passing through
CC
is 50nA. A high R • C attenuates the high frequency
S
IN
these two decoupling capacitors and returning to the
converter GND pin. The area encompassed by this circuit
path, as well as the path length, should be minimized.
components of the input current, and R values up to
S
1kΩ result in <1LSB error.
2) The bandwidth from V is reduced at V .This band-
SIG
IN
Very low impedance ground and power planes and star
width reduction isolates the ADC from high frequency
signals, and as such provides simple antialiasing and
input noise reduction.
connections at both V and GND pins are preferable. The
CC
V pinshouldhavetwodistinctconnections:thefirsttothe
CC
decoupling capacitors described above and the second to
the power supply voltage. The GND pin should have three
distinctconnections:thefirsttothedecouplingcapacitors
described above, the second to the ground return for the
input signal source and the third to the ground return for
the power supply voltage source.
3) Noise generated by the ADC is attenuated before it goes
back to the signal source.
4) A large C gives a better AC ground at V , helping
IN
IN
reduce reflections back to the signal source.
5) Increasing R protects the ADC by limiting the current
S
during an outside-the-rails fault condition. R can be
Driving V
S
IN
easily sized such as to protect against even extreme
The V input drive requirements can be best analyzed
IN
fault conditions.
using the equivalent circuit of Figure 15. The input signal
There is a limit to how large R • C should be for a given
V
is connected to the ADC input pin V through an
S
IN
SIG
IN
application. Increasing R beyond a given point increases
equivalent source resistance R . This resistor includes
S
S
the voltage drop across R due to the input current, to
both the actual generator source resistance and any
S
the point that significant measurement errors exist. Ad-
ditionally, for some applications, increasing the R • C
additional optional resistor connected to the V pin. An
IN
optional input capacitor C is also connected to the ADC
S
IN
IN
product too much may unacceptably attenuate the signal
at frequencies of interest.
V pin. This capacitor is placed in parallel with the ADC
IN
inputparasiticcapacitanceC .DependinguponthePCB
PAR
V
CC
R
SW
15k
V
I
R
S
CC
(TYP)
LEAK
V
IN
C
I
EQ
LEAK
V
+
SIG
I
CONV
C
C
PAR
0.35pF
(TYP)
IN
–
24501 F15
Figure 15. LTC2450-1 Input Drive Equivalent Circuit
24501fb
15
LTC2450-1
APPLICATIONS INFORMATION
For most applications, it is desirable to implement C as
longer than the time periods between actual conversions,
then one can consider the input current to be reduced
correspondingly.
IN
a high quality 0.1μF ceramic capacitor and R ≤ 1k. This
S
capacitor should be located as close as possible to the
actualV packagepin.Furthermoretheareaencompassed
IN
These considerations need to be balanced out by the input
by this circuit path as well as the path length should be
signal bandwidth. The 3dB bandwidth ≅ 1/(2π • R • C ).
S
IN
minimized.
Finally, if the recommended choice for C is unacceptable
IN
In the case of a 2-wire sensor which is not remotely
fortheuser’sspecificapplication,analternatestrategyisto
grounded, it is desirable to split R and place series
S
eliminateC andminimizeC andR .Inpracticalterms,
IN
PAR
S
resistors in the ADC input line as well as in the sensor
ground return line which should be tied to the ADC GND
pin using a star connection topology.
thisconfigurationcorrespondstoalowimpedancesensor
directly connected to the ADC through minimum length
traces. Actual applications include current measurements
through low value sense resistors, temperature measure-
ments, low impedance voltage source monitoring and so
Figure 16 shows the measured LTC2450-1 INL vs
Input Voltage as a function of R value with an input
S
capacitor C = 0.1μF.
on. The resultant INL vs V is shown in Figure 17. The
IN
IN
measurements of Figure 17 include a C
capacitor cor-
PAR
In some cases, R can be increased above these guide-
S
responding to a minimum size layout pad and a minimum
width input trace of about 1 inch length.
lines. The input current is zero while the ADC is either in
sleep or I/O modes. Thus, if the time constant of the input
R-C circuit τ = R • C is of the same order magnitude or
S
IN
8
6
4
2
16
12
8
4
0
–2
–4
–6
–8
0
–4
–8
–12
–16
1
2
4
0
5
3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
24501 F16
24501 F17
Figure 16. Measured INL vs Input Voltage,
CIN = 0.1μF, VCC = 5V, TA = 25°C
Figure 17. Measured INL vs VIN, CIN = 0, VCC = 5V, TA = 25°C
24501fb
16
LTC2450-1
APPLICATIONS INFORMATION
Signal Bandwidth and Noise Equivalent Input
noise contribution of the external drive circuit would be
Bandwidth
V = n • √π/2 • F . Then, the total system noise level can
n
i
i
2
be estimated as the square root of the sum of (V ) and
1
n
The LTC2450-1 includes a sinc type digital filter with the
2
the square of the LTC2450-1 noise floor (≈2μV ).
first notch located at f = 60Hz. As such the 3dB input
0
signal bandwidth is 26.54Hz. The calculated LTC2450-1
input signal attenuation with frequency at low frequencies
is shown in Figure 18.
Aliasing
The LTC2450-1 signal acquisition circuit is a sampled
data system and as such suffers from input signal alias-
ing. As can be seen from Figure 19, due to the very high
over-sample ratios the high frequency input signal attenu-
ation is reasonably good. Nevertheless a continuous time
antialiasing filter connected at the input will preserve
the converter accuracy when the input signal includes
undesirable high frequency components. The antialias-
The LTC2450-1 input signal attenuation with frequency
over a wide frequency range is shown in Figure 19.
The converter noise level is about 1.4μV
and can be
RMS
modeled by a white noise source connected at the input
of a noise free converter.
ForasimplesystemnoiseanalysistheV drivecircuitcan
IN
ing function can be accomplished using the R and C
S
IN
S
be modeled as a single pole equivalent circuit character-
components shown in Figure 15 sized such that τ = R
ized by a pole location F and a noise spectral density n .
i
i
• C > 450ns.
IN
If the converter has an unlimited bandwidth or at least
a bandwidth substantially larger than F , then the total
i
0
–20
–40
–60
–80
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–100
0
0
60 120 180 240 300 360 420 480 540 600
INPUT SIGNAL FREQUENCY (Hz)
24501 F18
5.0
7.5
10.0 12.5 15.0
2.5
INPUT SIGNAL FREQUENCY (MHz)
24501 F19
Figure 18. Input Signal Attenuation vs Frequency
(Low Frequencies)
Figure 19. Input Signal Attenuation vs Frequency
24501fb
17
LTC2450-1
TYPICAL APPLICATION
Thermistor Measurement
5V
V
CC
10k
CS
SCK
SDO
V
LTC2450-1
GND
IN
THERMISTOR
1k TO 10k
100nF
24501 TA02
24501fb
18
LTC2450-1
PACKAGE DESCRIPTION
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703)
0.675 ±0.05
2.50 ±0.05
0.61 ±0.05
1.15 ±0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
1.42 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
0.56 ± 0.05
(2 SIDES)
0.38 ± 0.05
4
6
2.00 ±0.10
(4 SIDES)
PIN 1 BAR
PIN 1
TOP MARK
CHAMFER OF
(SEE NOTE 6)
EXPOSED PAD
(DC6) DFN 1103
3
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
1.37 ±0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
24501fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2450-1
TYPICAL APPLICATIONS
Easy Active Input
Easy Passive Input
PRECONDITIONED SENSOR
WITH VOLTAGE OUTPUT
V+
1k
R
S
< 10k
V
LTC2450-1
OUT
LTC2450-1
GND
100nF
100nF
24501 TA04
24501 TA05
RELATED PARTS
PART NUMBER
LT®1236A-5
DESCRIPTION
COMMENTS
Precision Bandgap Reference, 5V
0.05% Maximum, 5ppm/°C Drift
0.04% Maximum, 3ppm/°C Drift
LT1461
Micropower Series Reference, 2.5V
LTC1860/LTC1861
LTC1860L/LTC1861L
LTC1864/LTC1865
LTC1864L/LTC1865L
LTC2440
12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP
12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC
16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP
16-bit, 3V, 1-/2-Channel 150ksps SAR ADC
24-Bit No Latency ΔΣTM ADC
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages
450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages
200nV
Noise, 8kHz Output Rate, 15ppm INL
RMS
LTC2450
Ultra Tiny, Easy to use 16-Bit ΔΣ ADC with Automatic Offset
Calibration and 30Hz Output Rate
Pin Compatible with the LTC2450-1
LTC2480
LTC2481
LTC2482
LTC2483
LTC2484
LTC2485
16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA,
Easy Drive Input Current Cancellation, 600nV
Tiny 10-Lead DFN Package
Noise,
Noise,
Noise,
Noise,
Noise,
Noise,
RMS
RMS
RMS
RMS
RMS
RMS
Temperature Sensor, SPI
16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA,
Easy Drive Input Current Cancellation, 600nV
Tiny 10-Lead DFN Package
2
Temperature Sensor, I C
16-Bit, Differential Input, No Latency ΔΣ ADC, SPI
Easy Drive Input Current Cancellation, 600nV
Tiny 10-Lead DFN Package
2
16-Bit, Differential Input, No Latency ΔΣ ADC, I C
Easy Drive Input Current Cancellation, 600nV
Tiny 10-Lead DFN Package
24-Bit, Differential Input, No Latency ΔΣ ADC, SPI
Easy Drive Input Current Cancellation, 600nV
Tiny 10-Lead DFN Package
2
24-Bit, Differential Input, No Latency ΔΣ ADC, I C
Easy Drive Input Current Cancellation, 600nV
Tiny 10-Lead DFN Package
LTC6241
LT6660
Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp
550nV Noise, 125μV Offset Maximum
P-P
Micropower References in 2mm × 2mm DFN Package, 2.5V,
3V, 3.3V, 5V
20ppm/°C Maximum Drift, 0.2% Maximum
No Latency ΔΣ is a trademark of Linear Technololgy Corporation.
24501fb
LT 0907 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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