LTC6242HVIDHC [Linear]
Dual/Quad 18MHz, Low Noise, Rail-to-Rail, CMOS Op Amps; 双/四路18MHz时,低噪声,轨至轨, CMOS运算放大器型号: | LTC6242HVIDHC |
厂家: | Linear |
描述: | Dual/Quad 18MHz, Low Noise, Rail-to-Rail, CMOS Op Amps |
文件: | 总24页 (文件大小:491K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC6241/LTC6242
Dual/Quad 18MHz, Low
Noise, Rail-to-Rail,
CMOS Op Amps
U
DESCRIPTIO
FEATURES
The LTC®6241/LTC6242 are dual and quad low noise,
low offset, rail-to-rail output, unity gain stable CMOS op
amps that feature 1pA of input bias current. The 0.1Hz to
■
0.1Hz to 10Hz Noise: 550nV
P-P
■
Input Bias Current: 1pA (Typ at 25°C)
Low Offset Voltage: 125µV Max
Low Offset Drift: 2.5µV/°C Max
Voltage Gain: 124dB Typ
■
■
■
■
■
■
10Hz noise of only 550nV , along with an offset of just
P-P
125µV make them uncommon among traditional CMOS
op amps. Additionally, noise is guaranteed to be less
than 10nV/√Hz at 1kHz. An 18MHz gain bandwidth, and
10V/µs slew rate, along with the wide supply range and
low input capacitance, make them perfect for use as fast
signal processing amplifiers.
Gain Bandwidth Product: 18MHz
Output Swings Rail-to-Rail
Supply Operation:
2.8V to 6V LTC6241/LTC6242
2.8V to 5.5V LTC6241HV/LTC6242HV
Low Input Capacitance
Dual LTC6241 in 8-Pin SO and Tiny DFN Packages
Quad LTC6242 in 16-Pin SSOP and 5mm × 3mm
DFN Packages
■
■
■
These op amps have an output stage that swings within
30mV of either supply rail to maximize the signal dynamic
rangeinlowsupplyapplications.Theinputcommonmode
range extends to the negative supply. They are fully speci-
fiedon3Vand5V, andanHVversionguaranteesoperation
on supplies up to 5.5V.
U
APPLICATIO S
■
The LTC6241 is available in the 8-pin SO, and for compact
designs it is packaged in the tiny dual fine pitch leadless
(DFN) package. The LTC6242 is available in the 16-Pin
SSOP as well as the 5mm × 3mm DFN package.
Photo Diode Amplifiers
■
Charge Coupled Amplifiers
■
Low Noise Signal Processing
Active Filters
Medical Instrumentation
■
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
High Impedance Transducer Amplifier
U
TYPICAL APPLICATIO
Low Noise Single-Ended Input to Differential Output Amplifier
Noise Voltage vs Frequency
60
C3
10pF
T
V
V
= 25°C
A
S
=
2.5V
= 0V
50
40
30
20
10
0
CM
C4
10pF
R4
4.99k
C1
10pF
+2.5V
1/2
R1
200k
R3
4.99k
V
–
IN
+
–
V
V
OUT
OUT
LTC6241
+
–
–2.5V
1/2
LTC6241
+
R2
200k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
6241 TA01b
C2
10pF
6241 TA01a
62412f
1
LTC6241/LTC6242
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
+
–
Total Supply Voltage (V to V )
Specified Temperature Range (Note 4) .... –40°C to 85°C
Junction Temperature ........................................... 150°C
DHC, DD Package ............................................. 125°C
Storage Temperature Range....................–65ºC to 150°C
DHC, DD Package ...............................–65ºC to 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
LTC6241/LTC6242 ..................................................7V
LTC6241HV/LTC6242HV.......................................12V
Input Voltage.......................... (V + 0.3V) to (V – 0.3V)
Input Current........................................................ 10mA
Output Short Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range (Note 3) ... –40°C to 85°C
+
–
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
DD PART
MARKING*
TOP VIEW
LTC6241CDD
LTC6241HVCDD
LTC6241IDD
LBPD
LBRR
LBPD
LBRR
TOP VIEW
+
OUT A
–IN A
+IN A
1
2
3
4
8
7
6
5
V
+
OUT A
–IN A
+IN A
1
2
3
4
8
7
6
5
V
OUT B
–IN B
+IN B
A
OUT B
–IN B
+IN B
A
LTC6241HVIDD
B
–
V
B
–
ORDER PART
NUMBER
S8 PART
MARKING
V
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
= 125°C, θ = 43°C/W
UNDERSIDE METAL CONNECTED TO V
(PCB CONNECTION OPTIONAL)
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
JA
LTC6241CS8
LTC6241HVCS8
LTC6241IS8
6241
T
= 150°C, θ = 190°C/W
JMAX
JA
–
6241HV
6241I
LTC6241HVIS8
241HVI
ORDER PART
NUMBER
DHC PART
MARKING*
TOP VIEW
TOP VIEW
OUT A
–IN A
+IN A
1
2
3
4
5
6
7
8
16 OUT D
15 –IN D
OUT A
–IN A
+IN A
1
2
3
4
5
6
7
8
16
OUT D
LTC6242CDHC
LTC6242HVCDHC
LTC6242IDHC
6242
A
B
D
C
15 –IN D
A
B
D
C
6242HV
6242
14 +IN D
–
14
13
+IN D
+
V
13 V
+
–
V
V
17
LTC6242HVIDHC
6242HV
+IN B
–IN B
OUT B
NC
12 +IN C
11 –IN C
10 OUT C
+IN B
–IN B
OUT B
NC
12 +IN C
11
10
9
–IN C
OUT C
NC
ORDER PART
NUMBER
GN PART
MARKING
9
NC
LTC6242CGN
LTC6242HVCGN
LTC6242IGN
6242
DHC16 PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
= 125°C, θ = 43°C/W
GN PACKAGE
16-LEAD PLASTIC SSOP
= 150°C, θ = 135°C/W
6242HV
6242I
T
JMAX
JA
T
JMAX
JA
–
UNDERSIDE METAL CONNECTED TO V
LTC6242HVIGN
242HVI
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
62412f
2
LTC6241/LTC6242
U
AVAILABLE OPTIO S
PART NUMBER
AMPS/PACKAGE
SPECIFIED TEMP RANGE
0°C to 70°C
SPECIFIED SUPPLY VOLTAGE
3V, 5V
PACKAGE
SO-8
DD
PART MARKING
6241
LTC6241CS8
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
LTC6241CDD
0°C to 70°C
3V, 5V
LBPD
LTC6241HVCS8
LTC6241HVCDD
LTC6241IS8
0°C to 70°C
3V, 5V, 5V
3V, 5V, 5V
3V, 5V
SO-8
DD
6241HV
LBRR
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
0°C to 70°C
SO-8
DD
6241I
LTC6241IDD
3V, 5V
LBPD
LTC6241HVIS8
LTC6241HVIDD
LTC6242CGN
3V, 5V, 5V
3V, 5V, 5V
3V, 5V
SO-8
DD
241HVI
LBRR
GN
6242
LTC6242CDHC
LTC6242HVCGN
LTC6242HVCDHC
LTC6242IGN
0°C to 70°C
3V, 5V
DHC
GN
6242
0°C to 70°C
3V, 5V, 5V
3V, 5V, 5V
3V, 5V
6242HV
6242HV
6242I
0°C to 70°C
DHC
GN
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
–40°C to 85°C
LTC6242IDHC
LTC6242HVIGN
LTC6242HVIDHC
3V, 5V
DHC
GN
6242
3V, 5V, 5V
3V, 5V, 5V
242HVI
6242HV
DHC
ELECTRICAL CHARACTERISTICS (LTC6241/LTC6241HV, LTC6242/LTC6242HV) The
●
denotes the
specifications which apply over the specified temperature range, otherwise specifications are at T = 25°C. V = 5V, 0V, V = 2.5V
A
S
CM
unless otherwise noted.
SYMBOL PARAMETER
Input Offset Voltage (Note 5)
CONDITIONS
MIN
TYP
MAX
UNITS
V
SO-Package
0°C to 70°C
–40°C to 85°C
40
125
250
300
µV
µV
µV
OS
●
●
GN Package
0°C to 70°C
–40°C to 85°C
50
100
40
150
275
300
µV
µV
µV
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
550
650
725
µV
µV
µV
●
●
V
Match Channel-to-Channel (Note 6) SO-8 Package
160
300
375
µV
µV
µV
OS
●
●
0°C to 70°C
–40°C to 85°C
GN Package
0°C to 70°C
–40°C to 85°C
50
185
325
400
µV
µV
µV
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
150
650
700
750
µV
µV
µV
●
●
●
TC V
Input Offset Voltage Drift (Note 7)
Input Bias Current (Notes 5, 8)
0.7
1
2.5
µV/°C
OS
I
pA
pA
B
●
75
62412f
3
LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6241/LTC6241HV, LTC6242/LTC6242HV) The
unless otherwise noted.
●
denotes the
specifications which apply over the specified temperature range, otherwise specifications are at T = 25°C. V = 5V, 0V, V = 2.5V
A
S
CM
MAX
75
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
UNITS
I
Input Offset Current (Notes 5, 8)
0.5
pA
pA
OS
●
Input Noise Voltage
0.1Hz to 10Hz
f = 1kHz
550
7
nV
P-P
e
n
Input Noise Voltage Density
Input Noise Current Density (Note 9)
Input Resistance
10
nV/√Hz
fA/√Hz
Ω
i
0.56
n
12
R
Common Mode
10
IN
IN
C
Input Capacitance
Differential Mode
Common Mode
f = 100kHz (See Typical Characteristic
Curves)
0.5
3
pF
pF
●
●
V
Input Voltage Range
Guaranteed by CMRR
0
3.5
V
CM
CMRR
Common Mode Rejection
0V ≤ V ≤ 3.5V
80
105
95
dB
CM
CMRR Match
Channel-to-Channel (Note 6)
●
76
dB
A
VOL
Large Signal Voltage Gain
V = 1V to 4V
O
R = 10k to V /2
425
300
200
1600
V/mV
V/mV
V/mV
L
S
●
●
0°C to 70°C
–40°C to 85°C
V = 1.5V to 3.5V
O
R = 1k to V /2
90
60
50
215
V/mV
V/mV
V/mV
L
S
●
●
0°C to 70°C
–40°C to 85°C
●
●
●
V
V
Output Voltage Swing Low (Note 10)
Output Voltage Swing High (Note 10)
Power Supply Rejection
No Load
SINK
SINK
7
30
75
mV
mV
mV
OL
I
I
= 1mA
= 5mA
40
190
325
●
●
●
No Load
SOURCE
SOURCE
11
45
190
30
75
325
mV
mV
mV
OH
I
I
= 1mA
= 5mA
●
PSRR
V = 2.8V to 6V, V = 0.2V
S
80
104
100
dB
CM
PSRR Match
Channel-to-Channel (Note 6)
●
●
●
74
2.8
15
dB
V
Minimum Supply Voltage (Note 11)
Short-Circuit Current
I
I
30
mA
SC
Supply Current per Amplifier
1.8
2.2
2.3
2.4
mA
mA
mA
S
●
●
0°C to 70°C
–40°C to 85°C
●
●
●
GBW
SR
Gain Bandwidth Product
Slew Rate (Note 12)
Frequency = 20kHz, R = 1kΩ
13
5
18
10
MHz
V/µs
MHz
ns
L
A = –2, R = 1kΩ
V
L
FPBW
Full Power Bandwidth (Note 13)
Settling Time
V
OUT
= 3V , R = 1kΩ
0.53
1.06
1100
P-P
L
t
s
V = 2V, A = –1, R = 1kΩ, 0.1%
STEP V L
62412f
4
LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6241/LTC6241HV, LTC6242/LTC6242HV) The
●
denotes the
specifications which apply over the specified temperature range, otherwise specifications are at T = 25°C. V = 3V, 0V, V = 1.5V
A
S
CM
unless otherwise noted.
SYMBOL PARAMETER
Input Offset Voltage (Note 5)
CONDITIONS
MIN
TYP
MAX
UNITS
V
SO-8 Package
0°C to 70°C
–40°C to 85°C
40
175
275
325
µV
µV
µV
OS
●
●
GN Package
0°C to 70°C
–40°C to 85°C
60
100
40
200
275
325
µV
µV
µV
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
550
650
725
µV
µV
µV
●
●
V
Match Channel-to-Channel (Note 6) SO-8 Package
200
325
400
µV
µV
µV
OS
●
●
0°C to 70°C
–40°C to 85°C
GN Package
0°C to 70°C
–40°C to 85°C
60
225
325
400
µV
µV
µV
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
150
650
700
750
µV
µV
µV
●
●
I
I
Input Bias Current (Notes 5, 8)
Input Offset Current (Notes 5, 8)
1
pA
pA
B
●
75
0.5
pA
pA
OS
●
●
●
75
V
Input Voltage Range
Guaranteed by CMRR
0
1.5
V
CM
CMRR
Common Mode Rejection
0V ≤ V ≤ 1.5V
78
100
95
dB
CM
CMRR Match
Channel-to-Channel (Note 6)
●
76
dB
A
VOL
Large Signal Voltage Gain
V = 1V to 2V
O
R = 10k to V /2
140
100
75
600
V/mV
V/mV
V/mV
L
S
●
●
0°C to 70°C
–40°C to 85°C
●
●
V
V
Output Voltage Swing Low (Note 10)
Output Voltage Swing High (Note 10)
Power Supply Rejection
No Load
SINK
3
30
mV
mV
OL
I
= 1mA
65
110
●
●
No Load
= 1mA
4
70
30
120
mV
mV
OH
I
SOURCE
●
PSRR
V = 2.8V to 6V, V = 0.2V
S
80
104
100
dB
CM
PSRR Match
Channel-to-Channel (Note 6)
●
●
●
74
2.8
3
dB
V
Minimum Supply Voltage (Note 11)
Short-Circuit Current
I
I
6
mA
SC
S
Supply Current per Amplifier
1.4
1.7
1.8
1.9
mA
mA
mA
●
●
0°C to 70°C
–40°C to 85°C
●
GBW
Gain Bandwidth Product
Frequency = 20kHz, R = 1kΩ
12
17
MHz
L
62412f
5
LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6241HV/LTC6242HV) The
●
denotes the specifications which apply over
CM
the specified temperature range, otherwise specifications are at T = 25°C. V = 5V, 0V, V = 0V unless otherwise noted.
A
S
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage (Note 5)
SO-8 Package
0°C to 70°C
–40°C to 85°C
50
175
275
325
µV
µV
µV
OS
●
●
GN Package
0°C to 70°C
–40°C to 85°C
60
100
50
200
275
325
µV
µV
µV
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
550
650
725
µV
µV
µV
●
●
V
Match Channel-to-Channel (Note 6) SO-8 Package
200
325
400
µV
µV
µV
OS
●
●
0°C to 70°C
–40°C to 85°C
GN Package
0°C to 70°C
–40°C to 85°C
60
225
325
400
µV
µV
µV
●
●
DD, DHC Packages
0°C to 70°C
–40°C to 85°C
150
650
700
750
µV
µV
µV
●
●
●
●
●
TC V
Input Offset Voltage Drift (Note 7)
Input Bias Current (Notes 5, 8)
0.7
1
2.5
75
75
µV/°C
OS
I
pA
pA
B
I
OS
Input Offset Current (Notes 5, 8)
0.5
pA
pA
Input Noise Voltage
0.1Hz to 10Hz
f = 1kHz
550
7
nV
P-P
e
n
Input Noise Voltage Density
Input Noise Current Density (Note 9)
Input Resistance
10
nV/√Hz
fA/√Hz
Ω
i
0.56
n
12
R
Common Mode
10
IN
IN
C
Input Capacitance
Differential Mode
Common Mode
f = 100kHz (See Typical Characteristic
Curves)
0.5
3
pF
pF
●
●
V
Input Voltage Range
Guaranteed by CMRR
–5
83
3.5
V
CM
CMRR
Common Mode Rejection
–5V ≤ V ≤ 3.5V
105
95
dB
CM
CMRR Match
Channel-to-Channel (Note 6)
76
dB
●
A
VOL
Large Signal Voltage Gain
V = –3.5V to 3.5V
O
R = 10k
775
600
500
2700
V/mV
V/mV
V/mV
L
●
●
0°C to 70°C
–40°C to 85°C
R = 1k
150
90
75
360
V/mV
V/mV
V/mV
L
●
●
0°C to 70°C
–40°C to 85°C
●
●
●
V
V
Output Voltage Swing Low (Note 10)
Output Voltage Swing High (Note 10)
No Load
15
45
30
75
mV
mV
mV
OL
I
I
= 1mA
SINK
SINK
= 10mA
360
550
●
●
●
No Load
15
45
360
30
75
550
mV
mV
mV
OH
I
I
= 1mA
SOURCE
SOURCE
= 10mA
62412f
6
LTC6241/LTC6242
ELECTRICAL CHARACTERISTICS (LTC6241HV/LTC6242HV) The
●
denotes the specifications which apply over
CM
the specified temperature range, otherwise specifications are at T = 25°C. V = 5V, 0V, V = 0V unless otherwise noted.
A
S
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
PSRR
Power Supply Rejection
V = 2.8V to 11V, V = 0.2V
85
110
dB
S
CM
PSRR Match
●
●
●
Channel-to-Channel (Note 6)
82
2.8
15
106
dB
V
Minimum Supply Voltage (Note 11)
Short-Circuit Current
I
I
35
mA
SC
S
Supply Current per Amplifier
2.5
3.2
3.3
3.7
mA
mA
mA
●
●
0°C to 70°C
–40°C to 85°C
●
●
●
GBW
SR
Gain Bandwidth Product
Slew Rate (Note 12)
Frequency = 20kHz, R = 1kΩ
13
5.5
18
10
MHz
V/µs
MHz
ns
L
A = –2, R = 1kΩ
V
L
FPBW
Full Power Bandwidth (Note 13)
Settling Time
V
OUT
= 3V , R = 1kΩ
0.58
1.06
900
P-P
L
t
s
V = 2V, A = –1, R = 1kΩ, 0.1%
STEP V L
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
is calculated between the matching sides in µV/V. The result is converted
to dB.
Note 2: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 7: This parameter is not 100% tested.
Note 8: This specification is limited by high speed automated test
capability. See Typical Characteristics curves for actual typical
Note 3: All versions of the LTC6241/LTC6242 are guaranteed functional
over the temperature range of –40°C and 85°C.
performance.
1/2
Note 9: Current noise is calculated from the formula: i = (2qI )
n
B
–19
Note 4: The LTC6241C/LTC6241HVC, LTC6242C/LTC6242HVC are
guaranteed to meet specified performance from 0°C to 70°C. They are
designed, characterized and expected to meet specified performance from
–40°C to 85°C, but are not tested or QA sampled at these temperatures.
The LTC6241I/LTC6241HVI, LTC6242I/LTC6242HVI are guaranteed to meet
specified performance from –40°C to 85°C.
where q = 1.6 × 10 coulomb. The noise of source resistors up to
50GΩ dominates the contribution of current noise. See also Typical
Characteristics curve Noise Current vs Frequency.
Note 10: Output voltage swings are measured between the output and
power supply rails.
Note 11: Minimum supply voltage is guaranteed by the power supply
Note 5: ESD (Electrostatic Discharge) sensitive device. ESD protection
devices are used extensively internal to the LTC6241/LTC6242; however,
high electrostatic discharge can damage or degrade the device. Use proper
ESD handling precautions.
rejection ratio test.
Note 12: Slew rate is measured in a gain of –2 with R = 1k and R
= 500Ω. On the LTC6241/LTC6242, V is 1V and V
measured between –1V and +1V. On the LTC6241HV/LTC6242HV, V is
F
G
slew rate is
IN
OUT
IN
Note 6: Matching parameters are the difference between the two amplifiers
A and D and between B and C of the LTC6242; between the two amplifiers
of the LTC6241. CMRR and PSRR match are defined as follows: CMRR
and PSRR are measured in µV/V on the matched amplifiers. The difference
2V and V
slew rate is measured between –2V and +2V.
OUT
Note 13: Full-power bandwidth is calculated from the slew rate:
FPBW = SR/2πV .
P
62412f
7
LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
V
Temperature Coefficient
OS
V
Distribution
V
OS
Distribution
Distribution
OS
90
80
70
60
50
40
30
20
10
120
100
80
60
40
20
0
16
14
12
10
8
V
=
2.5V
V
=
2.5V
V = 2.5V
S
S
S
SO-8 PACKAGE
DD PACKAGE
2 LOTS
–55°C TO 125°C
6
4
2
0
0
–70 –50 –30 –10 10
30
50
70
–350 –250 –150 –50 50 150 250 350
–1.0 –0.6 –0.2 0.2 0.6 1.0 1.4 1.8
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
DISTRIBUTION (µV/°C)
6241 G01
6241 G02
6241 G03
Offset Voltage vs Input Common
Mode Voltage
Input Bias Current vs Common
Mode Voltage
Supply Current vs Supply Voltage
300
250
200
150
100
50
1000
100
10
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V, 0V
V
= 5V, 0V
S
S
T
= 25°C
A
T = 125°C
A
T
= 125°C
= 25°C
A
T
= –55°C
A
T
A
T
= 125°C
A
0
–50
–100
–150
–200
–250
–300
T
= –55°C
T
= 85°C
A
A
T
= 25°C
A
1
8
12
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
INPUT COMMON MODE VOLTAGE (V)
0
2
4
6
10
–0.5
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
COMMON MODE VOLTAGE (V)
TOTAL SUPPLY VOLTAGE (V)
6241 G06
6241 G05
6241 G04
Input Bias Current vs
Output Saturation Voltage vs
Load Current (Output Low)
Common Mode Voltage
Input Bias Current vs Temperature
10
1
1000
100
10
700
600
500
400
300
200
100
0
V
= 5V, 0V
V
= V /2
S
V
= 5V, 0V
S
CM
S
T
= 25°C
A
T
= 125°C
A
T
= 25°C
A
T
= 125°C
A
V = 10V
S
0.1
T
= –55°C
A
V
= 5V
S
–100
–200
–300
–400
0.01
0.001
T
= 85°C
A
1
25 35 45 55 65 75 85 95 105 115 125
–0.8 –0.6 –0.4 –0.2
0
0.2 0.4 0.6 0.8 1.0
0.1
1
10
100
TEMPERATURE (°C)
COMMON MODE VOLTAGE (V)
LOAD CURRENT (mA)
6241 G08
6241 G07
6241 G09
62412f
8
LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output Saturation Voltage vs
Load Current (Output High)
Gain Bandwidth and Phase
Margin vs Temperature
Open Loop Gain vs Frequency
10
1
70
60
50
40
30
80
120
100
80
V
= 5V, 0V
C
= 5pF
= 1k
C
= 5pF
= 1k
CM
S
L
L
L
L
PHASE
V
=
5V
70
60
50
40
30
20
10
0
R
R
S
V
= V /2
S
T
= 25°C
A
60
PHASE MARGIN
V
= 5V
S
V
=
1.5V
GAIN
40
S
T
= 125°C
A
V
=
1.5V
5V
S
40
30
20
10
0
20
T
= –55°C
A
0
V
=
S
0.1
V
=
5V
–20
–40
–60
–80
S
GAIN BANDWIDTH
V =
1.5V
S
V
=
1.5V
S
–10
–20
0.01
–55 –35 –15
5
25 45 65 85 105 125
10k
100k
1M
FREQUENCY (Hz)
10M
100M
0.1
1
10
100
TEMPERATURE (°C)
LOAD CURRENT (mA)
6241 G12
6241 G13
6241 G10
Gain Bandwidth and Phase
Margin vs Supply Voltage
Slew Rate vs Temperature
Output Impedance vs Frequency
20
18
16
14
12
10
8
10k
70
A
= –2
T = 25°C
A
V = 2.5V
S
T
= 25°C
= 5pF
= 1k
V
F
A
L
L
R
= 1k, R = 500Ω
C
G
60
50
40
CONDITIONS: SEE NOTE 12
R
1k
100
10
PHASE MARGIN
V
=
S
5V FALLING
5V RISING
S
A
= 10
V
A = 2
V
V
=
=
2.5V FALLING
2.5V RISING
S
30
20
10
0
V
=
1
A
= 1
V
V
S
GAIN BANDWIDTH
0.10
0.01
6
4
–55 –35 –15
5
25 45 65 85 105 125
0
2
4
6
8
10
12
10k
100k
1M
10M
TEMPERATURE (°C)
TOTAL SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
6241 G15
6241 G14
6241 G16
Common Mode Rejection Ratio vs
Frequency
Power Supply Rejection Ratio vs
Frequency
Channel Separation vs Frequency
0
–10
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
T
= 25°C
= 2.5V
T
V
A
= 25°C
T
= 25°C
= 2.5V
A
S
A
S
V
A
S
V
=
2.5V
V
= 1
–20
–30
–40
–50
POSITIVE SUPPLY
–60
–70
–80
–90
NEGATIVE SUPPLY
–100
–110
–120
–10
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6241 G19
6241 G18
6241 G17
62412f
9
LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output Short Circuit Current vs
Power Supply Voltage
Input Capacitance vs Frequency
Minimum Supply Voltage
50
40
16
14
12
10
8
100
80
V
= 1.5V
V
= V /2
S
S
CM
T
= –55°C
A
SINKING
30
60
C
CM
T
T
= 125°C
= 125°C
A
A
20
40
T
A
= 25°C
A
10
20
T
= 25°C
0
0
A
C
DM
–10
–20
–30
–40
–50
–20
–40
–60
–80
–100
T
= –55°C
6
4
T
= 125°C
A
SOURCING
T
= –55°C
A
2
0
1k
10k
100k
1M
10M
100M
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
1
2
3
4
5
6
7
8
9
10
POWER SUPPLY VOLTAGE ( V)
FREQUENCY (Hz)
TOTAL SUPPLY VOLTAGE (V)
6241 G22
6241 G20
6241 G21
Open Loop Gain
Open Loop Gain
Open Loop Gain
120
100
80
60
40
20
0
120
100
80
100
80
T
= 25°C
T
= 25°C
T = 25°C
A
A
S
A
S
V
= 3V, 0V
V
= 5V, 0V
V = 5V
S
60
40
60
R
= 10k
= 1k
R
= 100k
L
L
R
= 10k
= 1k
L
20
40
R
= 10k
L
R
L
0
R
L
20
–20
–40
–60
0
–20
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
–5 –4 –3 –2 –1
0
1
2
3
4
5
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
6241 G23
6241 G24
6241 G25
Noise Voltage vs Frequency
Offset Voltage vs Output Current
Warm-Up Drift vs Time
60
50
40
30
20
10
0
500
400
25
20
15
10
5
T
A
= 25°C
2.5V
= 0V
V
=
5V
T = 25°C
A
S
V
V
=
S
CM
300
T
= 125°C
V
S
=
5V
A
S
200
T
= 25°C
100
A
V
=
2.5V
0
T
= –55°C
A
–100
–200
–300
–400
–500
V
=
1.5V
0
S
–5
1
10
100
1k
10k
100k
–50 –40 –30 –20 –10
0
10 20 30 40 50
0
5
10 15 20 25 30 35 40 45 50 55 60
FREQUENCY (Hz)
OUTPUT CURRENT (mA)
TIME AFTER POWER UP (s)
6241 G28
6241 G26
6241 G27
62412f
10
LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Series Output Resistance and
Overshoot vs Capacitive Load
0.1Hz to 10Hz Voltage Noise
Noise Current vs Frequency
1000
100
10
60
V
= 5V, 0V
T
V
V
= 25°C
75pF
S
A
S
=
2.5V
= 0V
50
CM
1k
1k
R
–
+
S
40
30
20
10
0
C
L
R
= 10Ω
S
R
= 50Ω
S
1
V
A
=
= –1
2.5V
S
V
0.1
10
100
CAPACITIVE LOAD (pF)
1000
100
1k
10k
100k
TIME (1s/DIV)
FREQUENCY (Hz)
6241 G11
6241 G42
6241 G29
Series Output Resistance and
Overshoot vs Capacitive Load
Settling Time vs Output Step
(Non-Inverting)
60
50
40
30
20
10
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
75pF
T
V
A
= 25°C
A
S
V
=
5V
= 1
V
–
+
500Ω
OUT
1k
R
–
+
S
V
IN
1k
C
L
1mV
R
= 10Ω
S
R
= 50Ω
S
1mV
10mV
–4 –3 –2 –1
10mV
3
V
A
=
= –2
2.5V
S
V
10
100
CAPACITIVE LOAD (pF)
1000
0
1
2
4
OUTPUT STEP (V)
6241 G31
6241 G30
Maximum Undistorted Output
Signal vs Frequency
Settling Time vs Output Step
(Inverting)
10
9
8
7
6
5
4
3
2
1
3.0
2.5
2.0
1.5
1.0
0.5
0
T
V
A
= 25°C
A
S
V
=
5V
1k
= –1
1k
–
+
V
IN
A
= –1
V
V
OUT 1k
A
= +2
V
1mV
1mV
10mV
T
= 25°C
A
S
10mV
V
=
5V
HD , HD < –40dBc
2
3
10k
100k
1M
10M
–4 –3 –2 –1
0
1
2
3
4
FREQUENCY (Hz)
OUTPUT STEP (V)
6241 G33
6241 G32
62412f
11
LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Distortion vs Frequency
Distortion vs Frequency
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
V
A
V
=
2.5V
V
A
V
=
5V
S
V
S
V
= 1
= 1
= 2V
= 2V
OUT
P-P
OUT
P-P
R
= 1k, 2ND
L
R
= 1k, 2ND
L
R
= 1k, 3RD
L
R
= 1k, 3RD
L
10k
100k
1M
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
6241 G34
6241 G35
Distortion vs Frequency
Distortion vs Frequency
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
V
A
V
=
2.5V
V
A
V
=
5V
S
V
S
V
= 2
= 2
= 2V
= 2V
OUT
P-P
OUT
P-P
R
= 1k, 2ND
L
R
= 1k, 2ND
L
R
= 1k, 3RD
L
R
= 1k, 3RD
1M
L
10k
100k
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
6241 G36
6241 G37
62412f
12
LTC6241/LTC6242
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Small Signal Response
Large Signal Response
0V
0V
6241 G38
6241 G39
V
A
=
2.5V
V
A
=
5V
S
V
L
S
V
L
= 1
= 1
R
= ∞
R
= ∞
Large Signal Response
Output Overdrive Recovery
0V
V
IN
0V
(1V/DIV)
0V
V
OUT
(2V/DIV)
6241 G40
6241 G41
V
A
= 2.5V
= –1
= 1k
V
A
=
2.5V
500ns/DIV
S
V
L
S
V
L
= 3
R
R
= ∞
62412f
13
LTC6241/LTC6242
U
W U U
APPLICATIO S I FOR ATIO
Amplifier Characteristics
The amplifier input bias current is the leakage current of
these ESD diodes. This leakage is a function of the tem-
perature and common mode voltage of the amplifier, as
shown in the Typical Performance Curves.
Figure 1 is a simplified schematic of the LTC6241, which
has a pair of low noise input transistors M1 and M2. A
simple folded cascode Q1, Q2 and R1, R2 allow the input
stage to swing to the negative rail, while performing level
shift to the Differential Drive Generator. Low offset voltage
is accomplished by laser trimming the input stage.
Noise
The LTC6241 exhibits exceptionally low 1/f noise in the
0.1Hz to 10Hz region. This 550nV noise allows these
P-P
Capacitor C1 reduces the unity cross frequency and im-
proves the frequency stability without degrading the gain
bandwidth of the amplifier. Capacitor Cm sets the overall
amplifier gain bandwidth. The differential drive generator
supplies signals to transistors M3 and M4 that swing the
output from rail-to-rail.
op amps to be used in a wide variety of high impedance
low frequency applications, where Zero-Drift amplifiers
might be inappropriate due to their charge injection.
In the frequency region above 1kHz the LTC6241 also
show good noise voltage performance. In this frequency
region, noise can easily be dominated by the total source
resistance of the particular application. Specifically, these
amplifiers exhibit the noise of a 3.1kΩ resistor, meaning it
is desirable to keep the source and feedback resistance at
The photo of Figure 2 shows the output response to an
input overdrive with the amplifier connected as a voltage
follower. If the negative going input signal is less than
–
a diode drop below V , no phase inversion occurs. For
or below this value, i.e. R + R ||R ≤ 3.1kΩ. Above this
S
G
FB
–
input signals greater than a diode drop below V , limit the
totalsourceimpedance,thenoisevoltageisnotdominated
current to 3mA with a series resistor R to avoid phase
S
by the amplifier.
inversion.
Noise current can be estimated from the expression i =
n
–19
√2qI , where q = 1.6 • 10 coulombs. Equating √4kTRΔf
andR√2qI Δfshowsthatforsourceresistorsbelow50GΩ
ESD
B
B
The LTC6241 has reverse-biased ESD protection diodes
on all input and outputs as shown in Figure 1. If these
pins are forced beyond either supply, unlimited current
will flow through these diodes. If the current is transient
and limited to one hundred milliamps or less, no damage
to the device will occur.
the amplifier noise is dominated by the source resistance.
See the Typical Characteristics curve Noise Current vs
Frequency.
V
=
DD
+2.5V
+
V
I
TAIL
M3
CM
–
V
+
V
+
V
V
=
SS
–2.5V
DESD1
+
DESD2
DESD4
DESD5
DIFFERENTIAL
DRIVE
GENERATOR
V
O
V
M1
M2
IN
V
OUT
AND V OF FOLLOWER WITH LARGE INPUT OVERDRIVE
IN
–
V
IN
DESD6
C1
+2.5V
–
–
V
R
S
DESD3
V
Q1
Q2
+
BIAS
M4
1/2
LTC6241
–
V
+
V
V
OUT
V
IN
–
R1
R2
–2.5V
–
V
6241 F02
6241 F01
Figure 2. Unity Gain Follower Test Circuit
Figure 1. Simplified Schematic
62412f
14
LTC6241/LTC6242
U
W U U
APPLICATIO S I FOR ATIO
Proprietary design techniques are used to obtain simul-
taneous low 1/f noise and low input capacitance. Low
input capacitance is important when the amplifier is used
with high source and feedback resistors. High frequency
Half the Noise
The circuit shown in Figure 3 can be used to achieve even
lower noise voltage. By paralleling 4 amplifiers the noise
voltage can be lowered by √4, or half as much noise. The
√ comes about from an RMS summing of uncorrelated
noise sources. This circuit maintains extremely high input
resistance, and has a 250Ω output resistance. For lower
output resistance, a buffer amplifier can be added without
influencing the noise.
noise from the amplifier tail current source, I
in Fig-
TAIL
ure 1, couples through the input capacitance and appears
across these large source and feedback resistors. As an
example, the photodiode amplifier of Figure 11 on the last
page of this data sheet shows the noise results from the
LTC6241 and the results of a competitive CMOS amplifier.
The LTC6241 output is the ideal noise of a 1MΩ resistor
at room temperature, 130nV√Hz.
Stability
The good noise performance of these op amps can be at-
tributedtolargeinputdevicesinthedifferentialpair.Above
several hundred kilohertz, the input capacitance rises and
can cause amplifier stability problems if left unchecked.
+2.5
+
1k
1/4
LTC6242
When the feedback around the op amp is resistive (R ), a
–
F
pole will be created with R , the source resistance, source
F
–2.5
capacitance (R , C ), and the amplifier input capacitance.
S
S
1k
In low gain configurations and with R and R in even
10Ω
F
S
the kilohm range (Figure 4), this pole can create excess
phase shift and possibly oscillation. A small capacitor C
F
+
in parallel with R eliminates this problem.
1k
F
1/4
LTC6242
–
Low Noise Single-Ended Input to Differential Output
Amplifier
V
V
O
IN
1k
The circuit on the first page of the data sheet is a low noise
single-ended input to differential output amplifier, with a
200k input impedance. The very low input bias current
of the LTC6241 allows for these large input and feedback
resistors. The 200k resistors, R1 and R2, along with C1
and C2 set the –3dB bandwidth to 80kHz. Capacitor C3 is
used to cancel effects of input capacitance, while C4 adds
10Ω
10Ω
10Ω
+
1k
1/4
LTC6242
–
1k
C
F
R
F
+
1k
1/4
LTC6242
–
+
C
–
IN
OUTPUT
R
C
S
S
6241 F04
1k
Figure 4. Compensating Input Capacitance
6241 F03
Figure 3. Parallel Amplifier Lowers Noise by 2x
62412f
15
LTC6241/LTC6242
U
W U U
APPLICATIO S I FOR ATIO
gain of the difference amplifier is one. An LTC6910-2 PGA
amplifies the difference amplifier output with inverting
gains of –1, –2, –4, –8, –16, –32 and –64. The second
LTC6241 op amp is used as an integrator to set the DC
phase lead to compensate the phase lag of the second
amplifier. The op amp’s good input offset voltage match
andlowinputbiascurrentmeansthatthetypicaldifferential
output voltage is less than 40µV. A noise spectrum plot of
the differential output is shown in Figure 5.
output voltage equal to the LT6650 reference voltage V
.
REF
The integrator drives the PGA analog ground to provide
a feedback loop, in addition to blocking any DC voltage
through the PGA. The reference voltage of the LT6650
140
V
T
=
2.5V
S
A
= 25°C
120
100
80
60
40
20
0
–3dB BW = 80kHz
+
can be set to a voltage from 400mV to V – 350mV with
resistors R5 and R6. If R6 is 20k or less, the error due
to the LT6650 op amp bias current is negligible. The low
voltage offset and drift of the LTC6241 integrator will not
contribute any significant error to the LT6650 reference
voltage. The LT6650 V
voltage has a maximum error
REF
+
R3
V
G2 G1 G0
0
10 20 30 40 50 60 70 80 90 100
0.1µF
FREQUENCY (kHz)
C1
8
7
6
5
R1
6241 F05
V1
LTC6910-2
OUT AGND IN
–
Figure 5. Differential Output Noise
V
4
+
1
2
3
1/2
LTC6241
Achieving Low Input Bias Current
V
OUT
–
100Ω
R7
R2
C2
R4
C3
The DD package is leadless and makes contact to the PCB
beneath the package. Solder flux used during the attach-
ment of the part to the PCB can create leakage current
paths and can degrade the input bias current performance
ofthepart. Allinputsaresusceptiblebecausethebackside
paddle is connected to V internally. As the input voltage
changes or if V changes, a leakage path can be formed
and alter the observed input bias current. For lowest bias
current, use the LTC6241 in the SO-8 and provide a guard
ring around the inputs that are tied to a potential near the
input voltage.
V2
+
V
R1 = R2 = R3 = R4
0.1µF
R5
–
+
1/2
LTC6241
–
1000pF
–
R6
20k
1
5
4
LT6650
V
REF
2
1µF
1µF
1k
3
+
V
A Digitally Programmable AC Difference Amplifier
DIGITAL INPUTS GAIN
G2 G1 GO
V
V
= (V1 – V2) GAIN + V
REF
OUT
The LTC6241 configured as a difference amplifier, can
be combined with a programmable gain amplifier (PGA)
to obtain a low noise high speed programmable differ-
ence amplifier. Figure 6 shows the LTC6241 based as a
single-supply AC amplifier. One LTC6241 op amp is used
at the circuit’s input as a standard four resistor difference
amplifier. The low bias current and current noise of the
LTC6241allowtheuseofhighvaluedinputresistors, 100k
or greater. Resistors R1, R2, R3 and R4 are equal and the
R5
R6
⎛
⎞
⎠
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
= 0.4•
+ 1
⎟
REF
⎜
⎝
–1
–2
R5 =10k • 5• V – 2 R6 = 20k
(
)
REF
–4
–3d BANDWIDTH =
1
f
– f
LOW
(
)
HIGH
–8
–16
–32
–64
GAIN
f
=
f
=
HIGH
LOW
2• π •R3•C1
2 • π •R7 •C3
6241 F06
Figure 6. Wideband Difference Amplifier with High
Input Impedance and Digitally Programmable Gain
62412f
16
LTC6241/LTC6242
U
W U U
APPLICATIO S I FOR ATIO
of 2% with 1% resistors. The upper –3dB frequency of
the amplifier is set by resistor R3 and capacitor C1 and
is limited by the bandwidth of the PGA when operated at
a gain of 64. Capacitor C2 is equal to C1 and is added to
maintain good common mode rejection at high frequency.
The lower –3dB frequency is set by the integrator resistor
R7, capacitor C3, and the gain setting of the LTC6910-2
PGA. This lower –3dB zero frequency is multiplied by the
PGA gain. The rail-to-rail output of the LTC6910-2 PGA
allows for a maximum output peak-to-peak voltage equal
40nVpp Noise, 0.05µV/°C Drift, Chopped FET
Amplifier
Figure 7’s circuit combines the 5V rail-to-rail performance
of the LTC6241 with a pair of extremely low noise JFETs
configured in a chopper based carrier modulation scheme
to achieve an extraordinarily low noise and low DC drift.
The performance of this circuit is suited for the demand-
ing transducer signal conditioning situations such as high
resolution scales and magnetic search coils.
The LTC1799’s output is divided down to form a 2-phase
925Hz square wave clock. This frequency, harmonically
unrelatedto60Hz,providesexcellentimmunitytoharmonic
beating or mixing effects which could cause instabilities.
S1 and S2 receive complementary drive, causing A1 to
see a chopped version of the input voltage. A1’s square
wave output is synchronously demodulated by S3 and
S4. Because these switches are synchronously driven
with the input chopper, proper amplitude and polarity
information is presented to A2, the DC output amplifier.
This stage integrates the square wave into a DC voltage,
providing the output. The output is divided down (R2 and
R1) and fed back to the input chopper where it serves as
a zero signal reference. Gain, in this case 1000, is set by
the R1-R2 ratio. Because A1 is AC coupled, its DC offset
and drift do not affect the overall circuit offset, resulting
in the extremely low offset and drift noted. The JFETs
have an input RC damper that minimizes offset voltage
contribution due to parasitic switch behavior, resulting in
the 1µV offset specification.
to twice the V voltage. At the maximum gain setting of
REF
64, the maximum peak-to-peak difference between inputs
V1 and V2 is equal to twice V divided by 64.
REF
Example Design: Design a programmable gain AC differ-
ence amplifier, with a bandwidth 10Hz to 100kHz, an input
impedance equal or greater than 100kΩ, and an output
DC reference equal to 1V.
a. Select input resistors R1, R2, R3 and R4 equal to
100k.
b. If the upper –3dB frequency is 100kHz then C1 = 1/(2π
• R2 • f3dB) = 1/(6.28 • 100kΩ • 100kHz) = 15pF (to
the nearest 5% value) and C2 = C1 = 15pF.
c. Select R7 equal to one 1M and set the lower –3dB
frequency to 10Hz at the highest PGA gain of 64, then
C3 = Gain/(2π • R7 • f3dB) = 64/(6.28 • 100kΩ • 10Hz)
= 1uF. Lower gains settings will give a lower f3dB.
d. Calculate the value of R5 to set the LT6650 reference
equal to 1V;
The noise measured over a 50 second interval, in Figure 8,
is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is at-
tributed to the input JFET’s die size and current density.
V
= 0.4(R5/R6 + 1), so R5 = R6(2.5V
– 1). For
REF
REF
R6 = 20kΩ, R5 = 30kΩ
With V = 1V the maximum input difference voltage
is equal to 2V/64 = 31.2mV.
REF
62412f
17
LTC6241/LTC6242
U
W U U
APPLICATIO S I FOR ATIO
5V
–5V
+
–
TO LTC201 V PIN
TO LTC201 V PIN
1µF
1µF
+
5V
5V
18.5kHz
+
V
74C90 ÷ 10
74C74 ÷ 2
DIV
OUT
5V
LTC1799
R
SET
Q
Q
925Hz
54.2k*
TO
Ø1
TO
Ø2
5V
Ø1
POINTS POINTS
8
898Ω**
898Ω**
3k
6
7
INPUT
Ø2
S1
S2
0.01µF
1µF
1
–
LSK389
1µF
11
10
A1
3
2
9
LTC6241HV
S3
S4
240k
499Ω**
–5V
Ø2
–
+
10M
10k
A2
OUTPUT
LTC6241HV
14
15
16
Ø1
+
R2
10k
1µF
* = 0.1% METAL FILM RESISTOR
** = 1% METAL FILM RESISTOR
NOISE = 40nV 0.1Hz TO 10Hz
P-P
R1
OFFSET = 1µV
DRIFT = 0.05µV/°C
R2
10Ω
= LTC201 QUAD
=
+1
GAIN
10
= LSK389
= LINEAR INTEGRATED SYSTEMS
FREMONT, CA
9
OPEN-LOOP GAIN = 10
= 500pA
I
6241 F07
BIAS
Figure 7. Ultra Low Noise Chopper Amplifier
VERT = 20nV/DIV
HORIZ = 5s/DIV
6241 F08
Figure 8. Noise in a 0.1Hz to 10Hz Bandwidth
62412f
18
LTC6241/LTC6242
U
W U U
APPLICATIO S I FOR ATIO
Low Noise Shock Sensor Amplifiers
accelerometerswherethecablelengthmayvary.Difficulties
with the circuit are inaccuracy of the gain setting with the
small capacitor, and low frequency cutoff due to the bias
resistor working into the small feedback capacitor.
Figures 9 and 10 show the LTC6241 realizing two different
approachestoamplifyingsignalsfromacapacitivesensor.
The sensor in both cases is a 770pF piezoelectric shock
sensor accelerometer, which generates charge under
physical acceleration.
Figure 10 shows a non-inverting amplifier approach. This
approach has many advantages. First of all, the gain is set
accurately with resistors rather than with a small capaci-
tor. Second, the low frequency cutoff is dictated by the
bias resistor working into the large 770pF sensor, rather
than into a small feedback capacitor, for lower frequency
response. Third, the non-inverting topology can be paral-
leled and summed (as shown) for scalable reductions in
voltage noise. The only drawback to this circuit is that the
parasiticcapacitanceattheinputreducesthegainslightly.
This circuit is favored in cases where parasitic input
capacitances such as traces and cables will be relatively
small and invariant.
Figure 9 shows the classical “charge amplifier” approach.
TheLTC6241isintheinvertingconfigurationsothesensor
looks into a virtual ground. All of the charge generated
by the sensor is forced across the feedback capacitor
by the op amp action. Because the feedback capacitor
is 100 times smaller than the sensor, it will be forced to
100 times what would have been the sensor’s open circuit
voltage. So the circuit gain is 100. The benefit of this ap-
proach is that the signal gain of the circuit is independent
of any cable capacitance introduced between the sensor
and the amplifier. Hence this circuit is favored for remote
+
V
S
+
1/2
LTC6241HV
SHOCK SENSOR
MURATA-ERIE
PKGS-00LD
770pF
–
+
1k
1k
1/2
LTC6241
100Ω
10k
SHOCK SENSOR
MURATA-ERIE
PKGS-00LD
770pF
V
OUT
–
C
7.7pF
V
= 110mV/g
OUT
f
1G
+
BIAS RESISTOR
1/2
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
LTC6241HV
MAIN
R
1G
GAIN-SETTING
ELEMENT IS A
CAPACITOR
f
–
V
V
= 110mV/g
CABLE HAS
UNKNOWN C
OUT
=
S
1.4V to 5.5V
–
V
S
BW = 0.2Hz to 10kHz
BIAS RESISTOR
VISHAY-TECHNO
CRHV2512AF1007G
(OR EQUIVALENT)
100Ω
10k
6241 F09
6241 F10
Figure 9. Classical Inverting Charge Amplifier
Figure 10. Low Noise Non-Inverting Shock Sensor Amplifier
62412f
19
LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
0.65 0.05
3.50 0.05
1.65 0.05
2.20 0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
4.40 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
0.40 0.10
5.00 0.10
(2 SIDES)
9
16
R = 0.20
TYP
3.00 0.10 1.65 0.10
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1
NOTCH
(DHC16) DFN 1103
8
1
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
4.40 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
62412f
20
LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 .005
.150 – .165
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 .004
(0.38 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
62412f
21
LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 0.10
TYP
5
8
0.675 0.05
3.5 0.05
2.15 0.05 (2 SIDES)
1.65 0.05
3.00 0.10
(4 SIDES)
1.65 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD8) DFN 1203
4
1
0.25 0.05
0.75 0.05
0.200 REF
0.25 0.05
0.50 BSC
0.50
BSC
2.38 0.05
(2 SIDES)
2.38 0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
62412f
22
LTC6241/LTC6242
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 .005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.160 .005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 .005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
62412f
InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC6241/LTC6242
U
TYPICAL APPLICATIO
1MΩ TIA
150kHz 3RD ORDER BUTTERWORTH FILTER
+1.5V
R1
R2
1.69k
R3
2k
C2
+
866Ω
1500pF
1/2
LTC6241
+
1/2
LTC6241
–
C1
1500pF
C3
180pF
R
F
1MΩ
–
SFH213FA
OR EQUIVALENT
(≤4pF)
–1.5V
6241 TA02a
C
F
–1.5V
1pF
Figure 11. Ultralow Noise 1MΩ 150kHz Photodiode Amplifier
LTC6241 Output Noise Spectrum. 1MΩ Resistor Noise
Competition Output Noise Spectrum. Op Amp Noise Dominates;
Performance Compromised
Dominates; Ideal Performance
0V
0V
1kHz
10kHz/DIV
101kHz
1kHz
10kHz/DIV
101kHz
6241 TA02b
6241 TA02c
RELATED PARTS
PART NUMBER
LTC1151
DESCRIPTION
15V Zero-Drift Op Amp
COMMENTS
Dual High Voltage Operation 18V
6nV/√Hz Noise, 15V Operation
2.7 Volt Operation, SOT-23
LT1792
Low Noise Precision JFET Op Amp
Zero-Drift Op Amp
LTC2050
LTC2051/LTC2052
LTC2054/LTC2055
Dual/Quad Zero-Drift Op Amp
Single/Dual Zero-Drift Op Amp
Dual/Quad Version of LTC2050 in MS8/GN16 Packages
Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages
62412f
LT/TP 0605 500 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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