LTC6404-4 [Linear]
2.7GHz, 5V, Low Noise,Rail-to-Rail Input Differential Amplifier/Driver; 2.7GHz频率， 5V ，低噪声，轨至轨输入差分放大器/驱动器
| 型号： | LTC6404-4 |
| 厂家： | 
Linear |
| 描述： | 2.7GHz, 5V, Low Noise,Rail-to-Rail Input Differential Amplifier/Driver |
| 文件： | 总26页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6405
2.7GHz, 5V, Low Noise,
Rail-to-Rail Input Differential
Amplifier/Driver
Features
Description
The LTC®6405 is a very low noise, low distortion, fully
differential input/output amplifier optimized for 5V, single
supplyoperation.TheLTC6405inputcommonmoderange
is rail-to-rail, while the output common mode voltage is
independently adjustable by applying a voltage on the
n
Low Noise: 1.6nV/√Hz RTI
n
Low Power: 18mA at 5V
n
Low Distortion (HD2/HD3):
–82dBc/–65dBc at 50MHz, 2V
–97dBc/–91dBc at 25MHz, 2V
P-P
P-P
n
Rail-to-Rail Differential Input
V
pin. This makes the LTC6405 ideal for level shifting
OCM
n
4.5V to 5.25V Supply Voltage Range
Fully Differential Input and Output
signalswithawidecommonmoderangefordriving12-bit
to 16-bit single supply, differential input ADCs.
n
n
n
n
n
n
Adjustable Output Common Mode Voltage
A2.7GHzgain-bandwidthproductresultsin65dBlinearity
for 50MHz input signals. The LTC6405 is unity gain stable
andtheclosed-loopbandwidthextendsfromDCto800MHz.
The output voltage swing extends from near-ground to
4V, to be compatible with a wide range of ADC converter
input requirements. The LTC6405 draws only 18mA, and
has a hardware shutdown feature which reduces current
consumption to 400µA.
800MHz –3dB Bandwidth with A = 1
V
Gain-Bandwidth Product: 2.7GHz
Low Power Shutdown
Available in 8-Lead MSOP and 16-Lead
3mm × 3mm × 0.75mm QFN Packages
applications
n
Differential Input ADC Driver
TheLTC6405isavailableinacompact3mm×3mm16-pin
leadlessQFNpackage,aswellasan8-leadMSOPpackage,
and operates over a –40°C to 85°C temperature range.
n
Single-Ended to Differential Conversion
n
Level-Shifting Ground-Referenced Signals
n
Level-Shifting V -Referenced Signals
CC
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
High-Linearity Direct Conversion Receivers
typical application
Single-Ended Input to Differential Output
with Common Mode Level Shifting
Input Noise Density vs Input
Common Mode Voltage
4
3
2
1
0
4
3
2
1
0
2V
P-P
V
= 5V
S
1.8pF
NOISE MEASURED AT f = 1MHz
0V
V
S
50Ω
196Ω
200Ω
0.1µF
i
n
5V
61.9Ω
SIGNAL
GENERATOR
1V
1V
P-P
e
n
2.5V
2.5V
+
V
OCM
LTC6405UD
0.01µF
221Ω
–
P-P
200Ω
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
INPUT COMMON MODE VOLTAGE (V)
1.8pF
6405 TA01b
6405 TA01
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For more information www.linear.com/6405
LTC6405
absolute MaxiMuM ratings (Note 1)
+
–
Total Supply Voltage (V to V )................................5.5V
Specified Temperature Range (Note 5)
Input Current
LTC6405I.............................................–40°C to 85°C
LTC6405C................................................ 0°C to 70°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
(+IN, –IN, V
, SHDN, V ) (Note 2) ............ 10mA
TIP
OCM
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range
(Note 4) ...............................................–40°C to 85°C
pin conFiguration
TOP VIEW
16 15 14 13
–
TOP VIEW
SHDN
1
2
3
4
12
11
10
9
V
V
V
V
–IN 1
8 +IN
9
+
+
+
–
V
V
2
3
4
7 SHDN
OCM
17
+
–
–
V
6 V
V
+OUT
5 –OUT
V
OCM
MS8E PACKAGE
8-LEAD PLASTIC MSOP
5
6
7
8
T
= 150°C, θ = 40°C/W, θ = 10°C/W
JA JC
JMAX
–
EXPOSED PAD (PIN 9) IS V , MUST BE SOLDERED TO PCB
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
T
= 150°C, θ = 68°C/W, θ = 4.2°C/W
JA JC
JMAX
–
EXPOSED PAD (PIN 17) IS V , MUST BE SOLDERED TO PCB
orDer inForMation
LEAD FREE FINISH
LTC6405CMS8E#PBF
LTC6405IMS8E#PBF
LTC6405CUD#PBF
LTC6405IUD#PBF
TAPE AND REEL
PART MARKING*
LTDKN
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6405CMS8E#TRPBF
LTC6405IMS8E#TRPBF
LTC6405CUD#TRPBF
LTC6405IUD#TRPBF
8-Lead Plastic MSOP
0°C to 70°C
LTDKN
8-Lead Plastic MSOP
–40°C to 85°C
0°C to 70°C
LDKP
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
LDKP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
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LTC6405
The l denotes the specifications which apply over the full
Dc electrical characteristics
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 2.5V, VSHDN = open,
circuit component values in Figure 1 used, unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2.
VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
V
Differential Offset Voltage (Input Referred)
V
V
V
= 5V (Note 12)
= 2.5V
= 0V (Note 12)
1
0.5
1
7
3.5
7
mV
mV
mV
OSDIFF
ICM
ICM
ICM
l
l
l
∆V
/∆T
OSDIFF
Differential Offset Voltage Drift (Input Referred)
Input Bias Current (Note 6)
V
V
V
= 5V (Note 12)
= 2.5V
1.5
1
µV/°C
µV/°C
µV/°C
ICM
ICM
ICM
= 0V (Note 12)
3
I
I
V
V
V
= 5V
= 2.5V
= 0V
8
µA
µA
µA
B
ICM
ICM
ICM
l
l
–24
–7
–14
Input Offset Current (Note 6)
Input Resistance
V
V
V
= 5V
= 2.5V
= 0V
0.5
0.5
0.5
µA
µA
µA
OS
ICM
ICM
ICM
4
R
Common Mode
Differential Mode
230
3.5
kΩ
kΩ
IN
C
Input Capacitance
Differential
1
pF
IN
e
Differential Input Referred Noise Voltage Density
f = 1MHz, Not Including R /R
1.6
nV/√Hz
n
I
F
Noise
i
Input Noise Current Density
f = 1MHz, Not Including R /R
2.4
9.5
pA/√Hz
nV/√Hz
n
I
F
Noise
e
Input Referred Common Mode Output Noise Voltage f = 1MHz
Density
nVOCM
–
+
l
l
V
(Note 7) Input Signal Common Mode Range
Op-Amp Inputs
V
V
V
ICMR
CMRRI
(Note 8)
Input Common Mode Rejection Ratio
(Input Referred) ∆V /∆V
V
ICM
from 0V to 5V
50
50
50
55
75
75
75
70
dB
ICM
OSDIFF
l
l
l
CMRRIO
(Note 8)
Output Common Mode Rejection Ratio
(Input Referred) ∆V /∆V
V
OCM
from 0.5V to 3.9V
dB
dB
dB
OCM
OSDIFF
PSRR
(Note 9)
Differential Power Supply Rejection
(∆V /∆V
V = 4.5V to 5.25V
S
)
OSDIFF
S
PSRRCM
(Note 9)
Output Common Mode Power Supply Rejection
(∆V /∆V
V = 4.5V to 5.25V
S
)
OSCM
S
l
l
G
Common Mode Gain (∆V
/∆V
)
V
V
from 0.5V to 3.9V
from 0.5V to 3.9V
1
V/V
%
CM
OUTCM
OCM
OCM
∆G
Common Mode Gain Error 100 • (G – 1)
0.25
0.8
CM
CM
OCM
BAL
Output Balance (∆V
/∆V
)
∆V
= 2V
OUTDIFF
OUTCM
OUTDIFF
l
l
Single-Ended Input
Differential Input
–60
–65
–40
–40
dB
dB
l
l
l
V
Common Mode Offset Voltage (V
– V )
OCM
6
15
mV
µV/°C
V
OSCM
OUTCM
∆V
/∆T
Common Mode Offset Voltage Drift
20
OSCM
V
Output Signal Common Mode Range
0.5
3.9
OUTCMR
(Note 7)
(Voltage Range for the V
Pin)
OCM
l
l
R
Input Resistance, V
Pin
13
19
25
kΩ
V
INVOCM
OCM
V
V
Self-Biased Voltage at the V
Pin
V
= Open
OCM
2.35
2.5
2.65
OCM
OCM
l
l
Output Voltage, High, +OUT/–OUT Pins
I = 0
3.9
3.85
4
3.95
V
V
OUT
L
I = –5mA
L
l
l
Output Voltage, Low, +OUT/–OUT Pins
I = 0
L
0.3
0.42
0.45
0.54
V
V
L
I = 5mA
l
I
Output Short-Circuit Current, +OUT/–OUT Pins
(Note 10)
40
60
mA
6405fb
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SC
For more information www.linear.com/6405
LTC6405
Dc electrical characteristics The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 2.5V, VSHDN = open,
circuit component values in Figure 1 used, unless otherwise noted. VS is defined as (V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2.
VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
dB
V
A
V
Large-Signal Open Loop Voltage Gain
Supply Voltage Range
Supply Current
90
VOL
S
l
l
l
l
l
l
4.5
5.25
23
1
I
I
18
0.4
50
mA
mA
kΩ
V
S
Supply Current in Shutdown
SHDN Pull-Up Resistor
SHDN Input Logic Low
SHDN Input Logic High
Turn-On Time
V
V
= 0V
SHDN
SHDN
SHDN
R
= 0V to 0.5V
30
70
SHDN
IL
V
V
1.25
1.8
2
2.55
V
IH
t
t
200
50
ns
ON
OFF
Turn-Off Time
ns
ac electrical characteristics The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, VCM = VOCM = VICM = 2.5V, VSHDN = open,
RLOAD = 400Ω, circuit component values in Figure 2 used, unless otherwise noted. VS is defined as (V+ – V–). VICM is defined as (V+IN
+ V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT).
SYMBOL
SR
PARAMETER
CONDITIONS
MIN
TYP
690
2.7
MAX
UNITS
V/µS
GHz
Slew Rate
Differential Output
GBW
Gain-Bandwidth Product
–3dB Frequency (See Figure 2)
f
= 27MHz
TEST
f
QFN Package
MSOP Package
500
400
800
750
MHz
MHz
–3dB
50MHz Distortion
Differential Input, V
(Note 13)
V
V
V
= 2.5V, V = 5V
OCM S
2nd Harmonic
3rd Harmonic
= 2V
–80
–64
dBc
dBc
OUTDIFF
P-P
l
–53
= 2.5V, V = 5V, R
= 800Ω
= 800Ω,
OCM
S
LOAD
2nd Harmonic
3rd Harmonic
–82
–66
dBc
dBc
= 2.5V, V = 5V, R
OCM
I
S
LOAD
R = R = 499Ω
F
2nd Harmonic
3rd Harmonic
–82
–64
dBc
dBc
50MHz Distortion
Single-Ended Input, V
(Note 13)
V
= 2.5V, V = 5V, R
= 800Ω,
OCM
I
S
LOAD
= 2V
R = R = 499Ω
OUTDIFF
P-P
F
2nd Harmonic
–72
–77
dBc
dBc
3rd Harmonic
3rd-Order IMD at 49.5MHz, 50.5MHz
V
R
= 2V Envelope,
–63
dBc
OUTDIFF
LOAD
P-P
= 800Ω
Equivalent OIP3 at 50MHz (Note 11)
Settling Time
R
= 800Ω
35.5
dBm
LOAD
t
V
OUTDIFF
= 2V Step
S
1% Settling
6
11
ns
ns
0.1% Settling
NF
Noise Figure at 50MHz
Shunt-Terminated to 50Ω, R = 50Ω
IN
14.4
7.5
dB
dB
S
Z
= 200Ω (R = 100Ω, R = 300Ω)
I F
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For more information www.linear.com/6405
LTC6405
electrical characteristics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 8: Input CMRR is defined as the ratio of the change in the input
common mode voltage at the pins +IN or –IN to the change in differential
input referred voltage offset. Output CMRR is defined as the ratio of
the change in the voltage at the V
pin to the change in differential
OCM
Note 2: Input pins (+IN, –IN, V
, SHDN and V ) are protected by
input referred voltage offset. This specification is strongly dependent on
feedback ratio matching between the two outputs and their respective
inputs, and it is difficult to measure actual amplifier performance. (See
the “Effects of Resistor Pair Mismatch” in the Applications Information
section of this data sheet.) For a better indicator of actual amplifier
performance independent of feedback component matching, refer to the
PSRR specification.
Note 9: Differential Power Supply Rejection (PSRR) is defined as the
ratio of the change in supply voltage to the change in differential input
referred voltage offset. Common mode power supply rejection (PSRRCM)
is defined as the ratio of the change in supply voltage to the change in the
OCM
TIP
steering diodes to either supply. If the inputs should exceed either supply
voltage, the input current should be limited to less than 10mA. In addition,
the inputs +IN, –IN are protected by a pair of back-to-back diodes. If the
differential input voltage exceeds 1.4V, the input current should be limited
to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indefinitely.
Note 4: The LTC6405C/LTC6405I are guaranteed functional over the
operating temperature range –40°C to 85°C.
Note 5: The LTC6405C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6405C is designed, characterized, and expected
to meet specified performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures. The LTC6405I is guaranteed to meet
specified performance from –40°C to 85°C.
common mode offset, V
– V
.
OUTCM
OCM
Note 10: Extended operation with the output shorted may cause the
junction temperature to exceed the 150°C limit.
Note 11: Because the LTC6405 is a feedback amplifier with low output
impedance, a resistive load is not required when driving an ADC.
Therefore, typical output power can be very small in many applications. In
order to compare the LTC6405 with “RF style” amplifiers that require 50Ω
load, the output voltage swing is converted to dBm as if the outputs were
Note 6: Input bias current is defined as the average of the input currents
flowing into the inputs (–IN, and +IN). Input Offset current is defined as
+
–
the difference between the input currents (I = I – I ).
OS
B
B
driving a 50Ω load. For example, 2V output swing is equal to 10dBm
P-P
Note 7: Input common mode range is tested using the test circuit of Figure
1 by taking 3 measurements of differential gain with a 1VDC differential
using this convention.
Note 12: Includes offset/drift induced by feedback resistors mismatch. See
the Applications Information section for more details.
output with V
differential gain has not deviated from the V
= 0V; V
= 2.5V; V
= 5V, verifying that the
ICM
ICM
ICM
= 2.5V case by more than
ICM
0.5%, and that the common mode offset (V
) has not deviated from
Note 13: QFN package only—refer to datasheet curves for MSOP package
numbers.
OSCM
the common mode offset at V
= 2.5V by more than 35mV.
ICM
The voltage range for the output common mode range is tested using the
test circuit of Figure 1 by applying a voltage on the V pin and testing at
OCM
both V
= 2.5V and at the Electrical Characteristics table limits to verify
OCM
that the common mode offset (V
) has not deviated by more than
OSCM
20mV from the V
= 2.5V case.
OCM
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LTC6405
typical perForMance characteristics
Differential Input Referred
Differential Input Referred Offset
Voltage vs Temperature
Offset Voltage vs Input Common
Mode Voltage
Common Mode Offset Voltage
vs Temperature
1.0
0.8
1.0
0.8
9
8
7
6
5
4
3
2
V
V
V
= 5V
V
V
= 5V
OCM
0.1% FEEDBACK NETWORK
RESISTORS REPRESENT-
S
S
V
V
V
= 5V
= 2.5V
OCM
= 2.5V
ICM
S
= 2.5V
= 2.5V
= 2.5V
OCM
ICM
R = R = 200Ω ATIVE UNIT
I
F
0.6
0.6
FIVE REPRESENTATIVE UNITS
R = R = 200Ω
I
F
0.4
0.4
FIVE REPRESENTATIVE UNITS
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
T
T
T
T
T
= –40°C
= 0°C
= 25°C
= 70°C
= 85°C
A
A
A
A
A
1
1.5
2
2.5
3
5
–50
–25
25
50
75
100
0
0.5
3.5
4
4.5
–50
–25
25
50
75
100
0
0
INPUT COMMON MODE VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
6405 G02
6405 G01
6405 G03
Shutdown Supply Current
vs Supply Voltage
Supply Current vs Supply Voltage
Supply Current vs SHDN Voltage
20
15
10
5
20
15
10
5
600
500
400
300
200
100
0
–
V
SHDN
= OPEN
V = 5V
S
V
SHDN
= V
T
= –40°C
T
T
T
T
T
= –40°C
A
A
A
A
A
A
A
A
A
A
T
T
T
T
= 0°C
= 0°C
= 25°C
= 70°C
= 85°C
= 25°C
= 70°C
= 85°C
T
T
T
T
T
= –40°C
= 0°C
= 25°C
= 70°C
= 85°C
A
A
A
A
A
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.5
1
1.5
SUPPLY VOLTAGE (V)
2
2.5
3
3.5
4
4.5
5
5.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5.5
5
0
SHDN VOLTAGE (V)
SUPPLY VOLTAGE (V)
6405 G05
6405 G04
6405 G06
6405fb
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LTC6405
typical perForMance characteristics
Input Noise Density vs Input
Common Mode Voltage
Differential Slew Rate
vs Temperature
Input Noise Density vs Frequency
100
10
1
100
10
1
4
3
2
1
0
4
3
2
1
0
720
700
680
660
640
620
600
V
V
= 5V
ICM
V
= 5V
V = 5V
S
S
S
= 2.5V
NOISE MEASURED AT f = 1MHz
i
n
e
n
i
n
e
n
100
1k
10k
100k
1M
10M
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
–50
–25
25
50
75
100
0
FREQUENCY (Hz)
INPUT COMMON MODE VOLTAGE (V)
TEMPERATURE (°C)
6405 G07
6405 G08
6405 G09
Differential Output Impedance
vs Frequency
CMRR vs Frequency
Differential PSRR vs Frequency
90
80
70
60
50
40
30
20
10
1000
100
10
V
S
= 5V
V
= 5V
F
S
I
R = R = 200Ω
80
70
60
50
40
30
20
1
V
V
= 5V
OCM
S
0.1
0.01
= 2.5V
R = R = 200Ω, C = 1.8pF
I
F
F
0.1% FEEDBACK NETWORK RESISTORS
1
10
100
1000 2000
1
10
100
1000 2000
1
10
100
1000 2000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
6405 G11
6405 G12
6405 G10
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LTC6405
typical perForMance characteristics (QFN Package)
Overdriven Output
Transient Response
Small Signal Step Response
Large Signal Step Response
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
+OUT
–OUT
+OUT
–OUT
–OUT
+OUT
6405 G13
6405 G14
6405 G15
10ns/DIV
10ns/DIV
100ns/DIV
V
= 5V
LOAD
= 2V , DIFFERENTIAL
V
V
= 5V
R =R = 200Ω
I F
V
V
= 5V
OCM
LOAD
S
S
S
R
V
= 400Ω
P-P
=V
= 2.5V C = 1.8pF
F
= 2.5V
OCM ICM
R
=400Ω
C = 0pF
L
R
= 400Ω TO GROUND PER OUTPUT
IN
LOAD
Frequency Response
vs Closed Loop Gain
Frequency Response
vs Load Capacitance
Frequency Response vs Input
Common Mode Voltage
50
40
10
5
30
20
C
C
C
= 0pF
= 2pF
= 3pF
L
L
L
L
L
A
= 100
V
30
0
A
= 20
C = 4.7pF
V
10
A
= 10
C
= 10pF
V
20
–5
V
V
V
V
V
V
= 0V
A
= 5
ICM
ICM
ICM
ICM
ICM
ICM
V
0
= 0.5V
= 1.25V
= 2.5V
= 4V
A
A
= 2
= 1
10
–10
–15
–20
–25
–30
–35
–40
V
V
–10
–20
–30
–40
–50
–60
0
V
V
= 5V
–10
–20
–30
–40
–50
S
= 5V
= V
= 2.5V
ICM
OCM
LOAD
R
= 400Ω
V
V
= 5V
R = R = 200Ω, C = 1.8pF
S
I
F
F
V
= 5V
= V
LOAD
= 2.5V
S
OCM
CAPACITOR VALUES ARE FROM EACH
OUTPUT TO GROUND.
NO SERIES RESISTORS ARE USED.
OCM
LOAD
V
= 2.5V
ICM
R
I
= 400Ω
R
= 400Ω
R = R = 200Ω, C = 1.8pF
F
F
1
10
100
1000 2000
1
10
100
1000 2000
1
10
100
1000 2000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
6405 G18
6405 G17
A
(V/V) R (Ω) R (Ω) C (pF)
V
I
F
F
1
2
5
10
20
100
200
200
200
200
200
200
200
400
1k
2k
4k
1.8
1.5
0.6
0.2
0
20k
0
6405 G16
6405fb
8
For more information www.linear.com/6405
LTC6405
typical perForMance characteristics (QFN Package)
Harmonic Distortion
vs Input Common Mode Voltage
Harmonic Distortion
vs Input Amplitude
Harmonic Distortion vs Frequency
–40
–50
–60
–70
–80
–90
–100
–30
–40
–40
–50
–60
–70
–80
–90
–100
V
V
V
f
= 5V
V
V
V
= 5V
V
V
V
f
= 5V
R
=800Ω
LOAD
S
S
S
= V
= 2.5V
ICM
= V
= 2.5V
= 2.5V
V
= 2V
P-P
OCM
TIP
= 50MHz
OCM
TIP
LOAD
ICM
OCM
TIP
= 50MHz
OUTDIFF
= OPEN (2.8V)
= OPEN (2.8V)
= OPEN (2.8V) DIFFERENTIAL INPUTS
R
= 800Ω, V
= 2V
–50
IN
R
I
OUTDIFF
P-P
IN
R = R = 200Ω
I
F
HD3
= 800Ω
DIFFERENTIAL INPUTS
LOAD
–60
R = R = 200Ω
DIFFERENTIAL INPUTS
F
–70
HD3
R = R = 499Ω
I
F
HD3
HD2
R = R = 499Ω
I
F
–80
HD3
HD2
R = R = 499Ω
I
F
–90
R = R = 200Ω
I
F
–100
–110
–120
HD2
R =R = 200Ω
R = R = 200Ω
I
F
HD2
I
F
R = R = 499Ω
I
F
1
10
100
–4
–2
0
2
4
6
8
10
(2V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5
5
(0.4V
)
)
FREQUENCY (MHz)
P-P
INPUT AMPLITUDE (dBm)
P-P
INPUT COMMON MODE VOLTAGE (V)
6405 G21
6405 G20
6405 G19
Harmonic Distortion
vs Input Common Mode Voltage
Harmonic Distortion
vs Input Amplitude
Harmonic Distortion vs Frequency
–30
–40
–40
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
V
V
V
= 5V
=V
= 2.35V
R
V
= 800Ω
OUTDIFF
SINGLE-ENDED INPUT
V
V
V
= 5V
S
S
OCM
TIP
LOAD
= 2.5V
= 2V
= V
= 2.5V
ICM
ICM
P-P
OCM
TIP
= 2.35V
f
= 50MHz
IN
–50
HD2
R
= 800Ω
LOAD
R = R = 499Ω
SINGLE-ENDED INPUT
I
F
–60
–70
HD2
HD3
HD3
–80
–90
V
V
V
f
= 5V
R
= 800Ω
LOAD
HD2, R = R = 200Ω
S
I
I
I
I
F
F
F
F
= 2.5V R = R = 499Ω
HD2, R = R = 499Ω
OCM
TIP
I
F
–100
–110
= 2.35V
V
= 2V
OUTDIFF P-P
HD3, R = R = 200Ω
= 50MHz SINGLE-ENDED INPUT
HD3, R = R = 499Ω
IN
1
10
FREQUENCY (MHz)
100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
–4
(0.4V
–2
0
2
4
6
8
10
(2V
)
)
INPUT COMMON MODE VOLTAGE (V)
P-P
INPUT AMPLITUDE (dBm)
P-P
6405 G22
6405 G23
6405 G24
Intermodulation Distortion
vs Input Common Mode Voltage
Intermodulation Distortion
vs Frequency
Intermodulation Distortion
vs Input Amplitude
–40
–50
–60
–70
–80
–90
–100
–30
–40
–40
–50
–60
–70
–80
–90
–100
V
V
V
f
= 5V
V
V
V
= 5V
= V
= OPEN (2.8V)
= 800Ω
S
S
OCM
= V
= 2.5V
ICM
= 2.5V
ICM
OCM
= OPEN (2.8V)
TIP
TIP
= 50MHz
R
LOAD
IN
–50
R
= 800Ω
R = R = 200Ω
LOAD
I
F
R = R = 200Ω
2 TONES, 1MHz TONE SPACING,
I
F
–60
2 TONES, 1MHz TONE SPACING
DIFFERENTIAL INPUTS
2V COMPOSITE
P-P
DIFFERENTIAL INPUTS
V
V
V
f
= 5V
= 2.5V
S
OCM
TIP
IN
R
–70
= OPEN (2.8V)
–80
= 50MHz
=800Ω
LOAD
–90
R = R = 200Ω
I
F
2TONES,1MHz TONE SPACING,
–100
–110
2V COMPOSITE
P-P
DIFFERENTIAL INPUTS
–4
(0.4V
–2
0
2
4
6
8
10
(2V
1
10
FREQUENCY (MHz)
100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
)
)
P-P
INPUT AMPLITUDE (dBm)
P-P
INPUT COMMON MODE VOLTAGE (V)
6405 G25
6405 G27
6405 G26
6405fb
9
For more information www.linear.com/6405
LTC6405
typical perForMance characteristics (MSOP Package)
Frequency Response
Harmonic Distortion
vs Input Amplitude
vs Load Capacitance
Harmonic Distortion vs Frequency
–30
–40
30
20
–40
–50
–60
–70
–80
–90
–100
V
V
V
= 5V
V
V
V
f
= 5V
S
S
=V
=2.5V
ICM
C
= 10pF
= V
= 2.5V
ICM
OCM
TIP
LOAD
L
OCM
TIP
= 50MHz
= OPEN (2.8V)
= OPEN (2.8V)
R
I
= 800Ω
IN
R
I
–50
10
R = R = 300Ω
= 800Ω
F
LOAD
V
= 2V
P-P
R = R = 300Ω
DIFFERENTIAL INPUTS
OUTDIFF
F
–60
0
DIFFERENTIAL INPUTS
HD2
HD3
C
= 0pF
L
–70
–10
–20
–30
–40
–50
V
V
= 5V
S
–80
= V
= 2.5V
ICM
OCM
LOAD
HD3
R
= 400Ω
–90
R = R = 300Ω, C = 1pF
I
F
F
HD2
CAPACITOR VALUES ARE FROM EACH
OUTPUT TO GROUND.
NO SERIES RESISTORS ARE USED.
–100
–110
1
10
100
1
10
100
1000 2000
–4
(0.4V
–2
0
2
4
6
8
10
)
(2V
)
FREQUENCY (MHz)
FREQUENCY (MHz)
P-P
INPUT AMPLITUDE (dBm)
P-P
6405 G29
6405 G28
6405 G30
Harmonic Distortion
vs Input Amplitude
Harmonic Distortion vs Frequency
–30
–40
–40
–50
–60
–70
–80
–90
–100
V
V
V
= 5V
V
V
V
IN
R
= 5V
R = R = 300Ω
I F
S
S
=V
= 2.5V
= V
= 2.5V SINGLE-ENDED INPUT
ICM
OCM
TIP
LOAD
ICM
OCM
TIP
= 50MHz
= OPEN (2.8V)
= OPEN (2.8V)
R
I
= 800Ω
f
–50
HD2
HD3
R = R = 300Ω
= 800Ω
F
LOAD
V
= 2V
P-P
OUTDIFF
–60
SINGLE-ENDED INPUT
–70
–80
HD2
HD3
–90
–100
–110
1
10
FREQUENCY (MHz)
100
–4
P-P
–2
0
2
4
6
8
10
(2V
(0.4V
)
)
INPUT AMPLITUDE (dBm)
P-P
6405 G31
6405 G32
6405fb
10
For more information www.linear.com/6405
LTC6405
pin Functions (MSOP/QFN)
V
(Pin 2/Pin 4): Output Common Mode Reference
circuit current limiting of 60mA. Each amplifier output
is designed to drive a load capacitance of 5pF. Larger
capacitive loads should be decoupled with at least 15Ω
resistors from each output.
OCM
Voltage. The voltage on V
sets the output common
OCM
mode voltage level (which is defined as the average of the
voltages on the +OUT and –OUT pins). The V voltage
OCM
isinternallysetbyaresistivedividerbetweenthesupplies,
V
(Pin 5) QFN Only: This pin can normally be left float-
TIP
developing a default voltage potential of 2.5V with a 5V
ing. It determines which pair of input transistors (NPN or
supply. The V
pin can be over-driven by an external
OCM
PNP or both) is sensing the input signal. The V pin is
TIP
voltage capable of driving the 19kΩ Thevenin equivalent
impedance presented by the pin. The V pin should be
set by an internal resistive divider between the supplies,
OCM
developing a default 2.8V voltage with a 5V supply. V
TIP
bypassedwithahighqualityceramicbypasscapacitorofat
least0.01µF, tominimizecommonmodenoisefrombeing
converted to differential noise by impedance mismatches
both externally and internally to the IC.
has a Thevenin equivalent resistance of approximately
17k and can be over-driven by an external voltage. The
V
pin should be bypassed with a high quality ceramic
TIP
bypass capacitor of at least 0.01µF. See the Applications
+
V (Pin 3/Pins 2, 10, 11):
Information section for more details.
–
V (Pin 6/Pins 3, 9, 12):
SHDN (Pin 7/Pin 1): When SHDN is floating or directly
+
tied to V , the LTC6405 is in the normal (active) operating
Power Supply Pins. It is critical that close attention be
paid to supply bypassing. For single supply applications,
itisrecommendedthatahighquality0.1µFsurfacemount
ceramicbypasscapacitorbeplacedbetweenV andV with
direct short connections. In addition, V should be tied
directly to a low impedance ground plane with minimal
routing.Fordual(split)powersupplies,itisrecommended
that additional high quality, 0.1µF ceramic capacitors are
used to bypass V to ground and V to ground, again
with minimal routing. For driving large loads (<200Ω),
additional bypass capacitance may be needed for optimal
performance.Keepinmindthatsmallgeometry(e.g.,0603
orsmaller)surfacemountceramiccapacitorshaveamuch
higher self resonant frequency than do leaded capacitors,
and perform best in high speed applications.
–
mode.WhentheSHDNpinisconnectedtoV ,theLTC6405
enters into a low power shutdown state with Hi-Z outputs.
+
–
+IN,–IN(Pins8,1/Pins15,6):NoninvertingandInverting
Input Pins of the Amplifier, Respectively. For best perfor-
mance, it is highly recommended that stray capacitance
be kept to an absolute minimum by keeping printed circuit
connections as short as possible.
–
+
–
+OUTF, –OUTF (Pins 8, 13) QFN Only: Filtered Output
Pins. These pins have a series RC network (R = 50Ω,
C = 3.75pF) connected between the filtered and unfiltered
outputs. See the Applications Information section for
more details.
NC (Pin 16) QFN Only: No Connection. This pin is not
connected internally.
+OUT, –OUT (Pins 4, 5/Pins 7, 14): Unfiltered Output
Pins. Besides driving the feedback network, each pin
can drive an additional 50Ω to ground with typical short
–
Exposed Pad (Pin 9/Pin 17): Tie the bottom pad to V .
If split supplies are used, DO NOT tie the pad to ground.
6405fb
11
For more information www.linear.com/6405
LTC6405
block DiagraMs
LTC6405 Block Diagram/Pinout in MSOP Package
8
7
6
5
–
+IN
SHDN
V
–OUT
–
V
+
+
V
V
V
37k
37k
+
–
–
–
V
+
V
+
–IN
V
OCM
V
+OUT
6405 BD01
1
2
3
4
LTC6405 Block Diagram/Pinout in QFN Package
16
15
14
13
NC
+IN
–OUT
–OUTF
1.25pF
–
SHDN
V
V
1
12
–
–
+
+
V
V
V
V
50Ω
+
+
V
+
–
+
+
2
11
V
V
V
V
37k
37k
+
–
1.25pF
–
+
+
V
V
V
V
V
V
50Ω
3
4
10
30k
38k
V
–
–
–
OCM
V
9
1.25pF
+OUTF
–
V
–IN
+OUT
TIP
5
6
7
8
6405 BD02
6405fb
12
For more information www.linear.com/6405
LTC6405
applications inForMation
Functional Description
modenoise(likepowersupplynoise).TheLTC6405canbe
usedasasingleendedinputtodifferentialoutputamplifier,
or as a differential input to differential output amplifier.
The LTC6405 is a small outline, wideband, low noise, and
low distortion fully-differential amplifier with accurate
output phase balancing. The LTC6405 is optimized to
drive low voltage, single-supply, differential input analog-
to-digitalconverters(ADCs). TheLTC6405inputcommon
mode range is rail-to-rail, while the output common mode
voltage is independently adjustable by applying a voltage
The LTC6405 output common mode voltage, defined as
the average of the two output voltages, is independent of
theinputcommonmodevoltage, andisadjustedbyapply-
ing a voltage on the V
pin. If the pin is left open, there
OCM
is an internal resistive voltage divider, which develops a
on the V
pin. The output voltage swing extends from
potential of 2.5V (if the supply is 5V). It is recommended
that a high quality ceramic cap is used to bypass the V
OCM
near-ground to 4V, to be compatible with a wide range of
ADCconverterinputrequirements.ThismakestheLTC6405
ideal for level shifting signals with a wide common mode
range for driving 12-bit to 16-bit single supply, differential
input ADCs. The differential output allows for twice the
signal swing in low voltage systems when compared to
single-ended output amplifiers. The balanced differential
nature of the amplifier also provides even-order harmonic
distortion cancellation, and less susceptibility to common
OCM
pin to a low impedance ground plane. The LTC6405’s
internal common mode feedback path forces accurate
output phase balancing to reduce even order harmonics,
and centers each individual output about the potential set
by the V
pin.
OCM
V+OUT + V–OUT
VOUTCM = VOCM
=
2
C
F
R
I
V
+IN
V
–OUT
V
R
–OUTF
F
+
–
16
15
14
13
NC
+IN
–OUT
–OUTF
V
INP
LTC6405
SHDN
–
R
V
–
BAL
1.25pF
V
100k
SHDN
12
V
1
2
SHDN
0.1µF
–
50Ω
–
+
+
V
V
V
V
V
+
11
V
+
0.1µF
V
1.25pF
50Ω
OUTCM
+
+
V
V
0.1µF
V
OCM
–
+
V
V
V
V
CM
–
–
–
3
4
10
V
V
–
–
0.1µF
0.1µF
V
–
V
1.25pF
R
BAL
V
OCM
100k
–
V
9
VOCM
0.1µF
0.01µF
V
–IN
+OUT
+OUTF
TIP
+
–
5
6
7
8
6405 F01
V
INM
0.01µF
V
+OUTF
R
R
I
F
V
–IN
V
+OUT
DEFAULT VALUES
PACKAGE
R
I
R
C
F
F
C
F
MSOP*
QFN
300Ω
200Ω
300Ω
200Ω
1.0pF
1.8pF
(R , R : 0.1% RESISTORS)
I
F
*TO OPTIMIZE THE HIGH FREQUENCY PERFORMANCE FOR THE PIN CONFIGURATION OF THE LTC6405
IN THE SMALL MSOP PACKAGE, A FEEDBACK RESISTANCE OF AT LEAST 300Ω IS RECOMMENDED.
Figure 1. DC Test Circuit
6405fb
13
For more information www.linear.com/6405
LTC6405
applications inForMation
Theoutputs(+OUTand–OUT)oftheLTC6405arecapable
of swinging from close-to-ground to typically 1V below
IC. The LTC6405 also has clamping diodes to either power
supply on the V , V and SHDN pins and if driven to
OCM TIP
+
V . They can source or sink up to approximately 60mA of
voltages which exceed either supply, they too, should be
current. Each output is designed to directly drive up to 5pF
to ground. Higher load capacitances should be decoupled
with at least 15Ω of series resistance from each output.
current limited to under 10mA.
SHDN Pin
The SHDN pin is a CMOS logic input with a 50k internal
pull-up resistor. If the pin is driven low, the LTC6405 pow-
ers down with Hi-Z outputs. If the pin is left unconnected
or driven high, the part is in normal active operation.
Some care should be taken to control leakage currents
at this pin to prevent inadvertently putting the LTC6405
into shutdown. The turn-on and turn-off time between the
shutdown and active states are typically less than 1µs.
Input Pin Protection
The LTC6405 input stage is protected against differential
input voltages which exceed 1.4V by two pairs of series
diodes connected back to back between +IN and –IN. In
addition, the input pins have clamping diodes to either
powersupply. Iftheinputpinsareover-driven, thecurrent
should be limited to under 10mA to prevent damage to the
C
F
0.1µF
0.1µF
100Ω
R
I
V
+IN
R
F
V
V
R
–OUTF
–OUT
T
16
15
14
13
NC
+IN
–OUT
–OUTF
LTC6405
–
SHDN
V
1.25pF
–
V
MINI-CIRCUITS
TCM4-19
MINI-CIRCUITS
TCM4-19
SHDN
12
50Ω
V
1
2
SHDN
0.1µF
–
50Ω
–
+
+
V
V
V
V
V
V
+
–
+
11
V
+
0.1µF
50Ω
V
1.25pF
50Ω
IN
+
+
V
V
V
0.1µF
OCM
–
+
V
V
V
–
–
–
3
4
10
V
V
–
–
0.1µF
0.1µF
0.1µF
V
–
1.25pF
V
OCM
5
–
V
9
VOCM
0.01µF
R
CHOSEN SO
T
–IN
+OUT
+OUTF
V
TIP
THAT R ||R = 100Ω
6
7
8
T
I
0.01µF
V
+OUTF
R
0.1µF
0.1µF
T
R
I
R
F
V
100Ω
+OUT
V
–IN
6405 F02
DEFAULT VALUES
PACKAGE
R
I
R
F
C
F
C
F
MSOP*
QFN
300Ω
200Ω
300Ω
200Ω
1.0pF
1.8pF
(R , R : 0.1% RESISTORS)
I
F
*TO OPTIMIZE THE HIGH FREQUENCY PERFORMANCE FOR THE PIN CONFIGURATION OF THE LTC6405
IN THE SMALL MSOP PACKAGE, A FEEDBACK RESISTANCE OF AT LEAST 300Ω IS RECOMMENDED.
Figure 2. AC Test Circuit (–3dB BW Testing)
6405fb
14
For more information www.linear.com/6405
LTC6405
applications inForMation
General Amplifier Applications
∆b is defined as the difference in feedback factors:
RI2 RI1
RI2 + RF2 RI1+ RF1
As levels of integration have increased and correspond-
ingly, system supply voltages decreased, there has been
a need for ADCs to process signals differentially in order
to maintain good signal to noise ratios. These ADCs are
typically supplied from a single supply voltage which
can be as low as 3V, and will have an optimal common
mode input range of 1.25V or 1.5V. The LTC6405 makes
interfacing to these ADCs easy, by providing both single-
ended to differential conversion as well as common mode
∆b =
–
V
isdefinedastheaverageofthetwoinputvoltagesV
INP
INM
ICM
and V
(also called the input common mode voltage):
1
2
V
= • V + V
(
)
ICM
INP
INM
and V
is defined as the difference of the input voltages:
INDIFF
level shifting. The gain to V
from V
and V is:
INM INP
OUTDIFF
V
INDIFF
= V – V
INP INM
RF
RI
VOUTDIFF = V+OUT – V–OUT
≈
• VINP – V
(
)
V
V
is defined as the average of the two output voltages
INM
OCM
and V
:
+OUT
–OUT
Note from the above equation, the differential output volt-
age (V – V ) is completely independent of input
and output common mode voltages, or the voltage at the
commonmodepin.ThismakestheLTC6405ideallysuited
forpre-amplification,levelshiftingandconversionofsingle
ended signals to differential output signals in preparation
for driving differential input ADCs.∆
V+OUT + V−OUT
VOCM
=
+OUT
–OUT
2
When the feedback ratios mismatch (∆b), common mode
to differential conversion occurs.
Setting the differential input to zero (V
gree of common mode to differential conversion is given
by the equation:
= 0), the de-
INDIFF
Effects of Resistor Pair Mismatch
∆b
bAVG
Figure 3 shows a circuit diagram which takes into consid-
eration that real world resistors will not match perfectly.
Assuming infinite open loop gain, the differential output
relationship is given by the equation:
VOUTDIFF = V+OUT – V–OUT ≈ VICM – VOCM
•
(
)
R
R
I2
F2
V
+IN
V
–OUT
+
–
RF
RI
VOUTDIFF = V+OUT – V–OUT
≅
•V
+
V
INP
INDIFF
+
V
V
VOCM
OCM
∆b
bAVG
∆b
bAVG
•V
–
•VOCM
ICM
–
–
+
V
INM
R
R
F1
I1
V
–IN
where:
R is the average of R , and R , and R is the average
V
+OUT
6405 F03
F
F1
F2
I
of R , and R .
I1
I2
Figure 3. Real-World Application with
Feedback Resistor Pair Mismatch
b
is defined as the average feedback factor from the
AVG
outputs to their respective inputs:
RI1
RI2
RI2 + R
1
bAVG = •
2
+
R + R
F2
I1
F1
6405fb
15
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LTC6405
applications inForMation
In general, the degree of feedback pair mismatch is a
sourceofcommonmodetodifferentialconversionofboth
signalsandnoise.Using1%resistorsorbetterwillmitigate
most problems, and will provide about 34dB worst case of
commonmoderejection.Using0.1%resistorswillprovide
about 54dB of common mode rejection. A low impedance
ground plane should be used as a reference for both the
thebalanceddifferentialcase.Theinputimpedancelooking
into either input is:
RI
RINP = RINM
=
RF
1
1– •
2
R + R
I
F
input signal source and the V
pin. Bypassing the V
Inputsignalsourceswithnon-zerooutputimpedancescan
alsocausefeedbackimbalancebetweenthepairoffeedback
networks. For the best performance, it is recommended
that the input source output impedance be compensated
for. Ifinputimpedancematchingisrequiredbythesource,
a termination resistor R1 should be chosen (see Figure 4):
OCM
OCM
with a high quality 0.1µF ceramic capacitor to this ground
planewillfurtherhelppreventcommonmodesignalsfrom
being converted to differential signals.
There may be concern on how feedback factor mismatch
affects distortion. Feedback factor mismatch from using
1%resistorsorbetter,hasanegligibleeffectondistortion.
However,insinglesupplylevelshiftingapplicationswhere
there is a voltage difference between the input common
mode voltage and the output common mode voltage,
resistor mismatch can make the apparent voltage offset
of the amplifier appear worse than specified.
RINM •RS
R1=
RINM –RS
According to Figure 4, the input impedance looking into
R
INM
R
R
R
F
S
I
The apparent input referred offset induced by feedback
factor mismatch is derived from the above equation:
R1
V
S
–
+
–
V
≈ (V
– V
) • ∆b
OCM
OSDIFF(APPARENT)
ICM
R1 CHOSEN SO THAT R1 || R
R2 CHOSEN TO BALANCE R1 || R
= R
S
S
+
INM
Using the LTC6405 in a single supply application on a
single5Vsupplywith1%resistors, andtheinputcommon
R
R
F
I
6405 F04
mode grounded, with the V
pin biased at 2.5V, the
OCM
R2 = R || R1
S
worst case DC offset can induce 25mV of apparent offset
voltage. With 0.1% resistors, the worst case apparent
offset reduces to 2.5mV.
Figure 4. Optimal Compensation for Signal Source Impedance
Input Impedance and Loading Effects
thedifferentialamp(R )reflectsthesingleendedsource
INM
The input impedance looking into the V or V
of Figure 1 depends on whether or not the sources V
input
INM
INP
case, thus:
INP
RI
and V
are fully differential or not. For balanced input
INM
RINM
=
sources(V =–V ),theinputimpedanceseenateither
RF
1
1– •
2
INP
INM
input is simply:
R + R
I
F
R
= R = R
INM I
INP
R2 is chosen to equal R1 || R :
S
For single ended inputs, because of the signal imbalance
at the input, the input impedance actually increases over
R1•RS
R2=
R1+ RS
6405fb
16
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LTC6405
applications inForMation
Input Common Mode Voltage Range
Manipulating the Rail-to-Rail Input Stage with V
TIP
The LTC6405’s input common mode voltage (V ) is
To achieverail-to-railinputoperation,theLTC6405features
anNPNinputstageinparallelwithaPNPinputstage.When
ICM
defined as the average of the two input voltages, V , and
+IN
+
V
. At the inputs to the actual op amp, the range extends
the input common mode voltage is near V , the NPNs are
–IN
–
+
from V to V . This makes it easy to interface to a wide
rangeofcommonmodesignals,fromgroundreferencedto
active while the PNPs are off. When the input common
–
mode is near V , the PNPs are active while the NPNs are
V
CC
referencedsignals. Moreover, duetoexternalresistive
off. At some range in the middle, both input stages are
active. This ‘hand-off’ operation happens automatically.
divideractionofthegainandfeedbackresistors,theeffective
range of signals that can be processed is even wider. The
input common mode range at the op amp inputs depends
In the QFN package, a special pin, V , is made available
TIP
that can be used to manipulate the ‘hand-off’ operation
on the circuit configuration (gain), V
and V (refer to
OCM
CM
between the NPN and PNP input stages. By default, the
Figure 5). For fully differential input applications, where
V
pin is internally biased by an internal resistive divider
TIP
V
INP
= –V , the common mode input is approximately:
INM
between the supplies, developing a default 2.8V voltage
V+IN + V–IN
RI
R + R
with a 5V supply. If desired, V can be over-driven by
TIP
V
=
≈ VOCM
•
+
ICM
an external voltage (the Thevenin equivalent resistance is
2
I
F
approximately 17k).
RF
–
VCM
•
If V is pulled closer to V , the range over which the NPN
TIP
R + R
I
F
inputpairremainsactiveisincreased, whiletherangeover
which the PNP input pair is active is reduced. In applica-
tions where the input common mode does not come close
R
R
F
I
V
+IN
V
–OUT
+
–
to V , this mode can be used to further improve linearity
V
INP
beyond the specified performance (see Figure 6).
–
+
+
If V is pulled closer to V , the range over which the PNP
TIP
V
V
VOCM
OCM
inputpairremainsactiveisincreased, whiletherangeover
which the NPN input pair is active is reduced. In applica-
tions where the input common mode does not come close
+
–
V
CM
–
+
–
V
INM
+
R
R
F
I
to V , this mode can be used to further improve linearity
V
–IN
V
+OUT
6405 F05
beyond the specified performance.
Figure 5. Circuit for Common Mode Range
–30
V
V
= 5V
R = R = 499Ω
I F
OUTDIFF
SINGLE-ENDED INPUT
QFN PACKAGE
S
=V =2.5V V
= 2V
P-P
OCM ICM
–40
–50
R
= 800Ω
LOAD
With single ended inputs, there is an input signal compo-
nent to the input common mode voltage. Applying only
HD2
TIP
–60
V
= OPEN
V
INP
(setting V
to zero), the input common voltage is
INM
HD3
–70
approximately:
V
= OPEN
TIP
–80
HD2
TIP
V+IN + V–IN
RI
R + R
V
=1V
V
=
≈ VOCM
•
+
–90
ICM
2
I
F
HD3
TIP
–100
–110
V
=1V
RF
V
RF
R + R
INP
VCM
•
+
•
1
10
FREQUENCY (MHz)
100
R + R
2
I
I
F
F
6405 F06
Figure 6. Manipulating VTIP to Improve Harmonic Distortion
Use the equations above to check that the V
at the op
ICM
–
+
amp inputs is within range (V to V ).
6405fb
17
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LTC6405
applications inForMation
Output Common Mode Voltage Range
Output Filter Considerations and Use
The output common mode voltage is defined as the aver-
age of the two outputs:
Filtering at the output of the LTC6405 is often desired to
provide anti-aliasing or to improve signal to noise ratio.
To simplify this filtering, the LTC6405 in the QFN package
includes an additional pair of differential outputs (+OUTF
and –OUTF) which incorporate an internal lowpass RC
network with a –3dB bandwidth of 850MHz (Figure 7).
V+OUT + V–OUT
VOUTCM = VOCM
The V
=
2
pin sets this average by an internal common
OCM
modefeedbackloopwhichinternallyforcesV
=V
.
OUTCM
OCM
These pins each have an output resistance of 50Ω (toler-
ance 12%). Internal capacitances are 1.25pF (tolerance
Theoutputcommonmoderangeextendsfrom0.5Vabove
–
+
–
V to typically 1V below V . The V
voltage is internally
OCM
15%) to V on each filtered output, plus an additional
set by a resistive divider between the supplies, developing
a default voltage potential of 2.5V with a 5V supply.
1.25pF(tolerance 15%)capacitorconnectedbetweenthe
two filtered outputs. This resistor/capacitor combination
creates filtered outputs that look like a series 50Ω resistor
with a 3.75pF capacitor shunting each filtered output to
AC ground, providing a –3dB bandwidth of 850MHz, and
a noise bandwidth of 1335MHz. The filter cutoff frequency
is easily modified with just a few external components. To
increase the cutoff frequency, simply add two equal value
resistors, one between +OUT and +OUTF and the other
between –OUT and –OUTF (Figure 8). These resistors, in
parallel with the internal 50Ω resistors, lower the overall
resistance and therefore increase filter bandwidth. For
example, to double the filter bandwidth, add two external
50Ω resistors to lower the series filter resistance to 25Ω.
The 3.75pF of capacitance remains unchanged, so filter
bandwidth doubles. Keep in mind, the series resistance
also serves to decouple the outputs from load capaci-
In single supply applications, where the LTC6405 is used
to interface to an ADC, the optimal common mode input
range to the ADC is often determined by the ADC’s refer-
ence. IftheADCmakesareferenceavailableforsettingthe
input common mode voltage, it can be directly tied to the
V
pin (as long as it is able to drive the 19kΩ Thevenin
OCM
equivalent input impedance presented by the V
pin).
OCM
The V
pin should be bypassed with a high quality
OCM
ceramic bypass capacitor of at least 0.01µF to filter any
common mode noise rather than being converted to dif-
ferential noise and to prevent common mode signals on
this pin from being inadvertently converted to differential
signals by impedance mismatches both externally and
internally to the IC.
49.9Ω
–OUTF
–OUTF
14
13
14
13
–OUT
50Ω
–OUTF
LTC6405
–OUT
50Ω
–OUTF
1.25pF
LTC6405
–
1.25pF
–
V
V
12
12
–
–
–
–
V
V
+
–
+
–
FILTERED OUTPUT
(1.7GHz)
FILTERED OUTPUT
1.25pF
V
1.25pF
V
50Ω
50Ω
–
–
1.25pF
1.25pF
V
V
9
9
+OUT
+OUTF
+OUT
+OUTF
7
8
7
8
6405 F08
6405 F07
+OUTF
49.9Ω
+OUTF
Figure 8. LTC6405 Filter Topology Modified for 2x Filter
Bandwidth (Two External Resistors)
Figure 7. LTC6405 Internal Filter Topology
6405fb
18
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LTC6405
applications inForMation
the amplifier and the feedback components is governed
by the equation:
tance. The outputs of the LTC6405 are designed to drive
5pF to ground, so care should be taken to not lower the
effective impedance between +OUT and +OUTF or –OUT
and –OUTF below 15Ω.
2
RF
RI
2
eni • 1+
+ 2• I •R
+
(
)
n
F
To decrease filter bandwidth, add two external capacitors,
one from +OUTF to ground, and the other from –OUTF to
ground. A single differential capacitor connected between
+OUTF and –OUTF can also be used, but since it is being
driven differentially it will appear at each filtered output
as a single-ended capacitance of twice the value. To halve
the filter bandwidth, for example, two 3.9pF capacitors
could be added (one from each filtered output to ground).
Alternatively, one1.8pFcapacitorcouldbeaddedbetween
thefilteredoutputs, whichalsohalvesthefilterbandwidth.
Combinations of capacitors could be used as well; a three
capacitor solution of 1.2pF from each filtered output to
groundplusa1.2pFcapacitorbetweenthefilteredoutputs
would also halve the filter bandwidth (Figure 9).
eno =
2
RF
2
2• enRI
•
+ 2•enRF
R
I
A plot of this equation, and a plot of the noise generated
by the feedback components for the LTC6405 is shown
in Figure 11.
2
2
e
nRF
e
nRI
R
I
R
F
+2
i
n
2
e
ncm
+
2
V
OCM
e
no
Noise Considerations
–
–2
i
n
The LTC6405’s input referred voltage noise is 1.6nV/√Hz.
Its input referred current noise is 2.4pA/√Hz. In addition
to the noise generated by the amplifier, the surrounding
feedback resistors also contribute noise. A noise model is
shown in Figure 10. The output noise generated by both
2
e
ni
R
2
2
e
nRF
e
nRI
R
F
I
6405 F10
Figure 10. Noise Model of the LTC6405
–OUTF
14
13
–OUT
50Ω
–OUTF
1.25pF
1.2pF
LTC6405
–
V
V
100
12
–
–
V
+
–
FILTERED OUTPUT
(425MHz)
1.2pF
1.25pF
V
TOTAL (AMPLIFIER AND
50Ω
FEEDBACK NETWORK)
OUTPUT NOISE
10
1
–
1.2pF
1.25pF
9
FEEDBACK NETWORK
NOISE ALONE
+OUT
+OUTF
7
8
6405 F09
+OUTF
Figure 9. LTC6405 Filter Topology Modified for 1/2x Filter
Bandwidth (Three External Capacitors)
0.1
10
100
1000
R = R (Ω)
10000
I
F
6405 F11
Figure 11. LTC6405 Output Spot Noise vs Spot Noise
Contributed by Feedback Network Alone
6405fb
19
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LTC6405
applications inForMation
TheLTC6405’sinputreferredvoltagenoisecontributesthe
equivalent noise of a 155Ω resistor. When the feedback
network is comprised of resistors whose values are less
than this, the LTC6405’s output noise is voltage noise
dominant (see Figure 11):
recommended that additional high quality, 0.1µF ceramic
+
–
capacitors are used to bypass V to ground and V to
ground, again with minimal routing. For driving large
loads (<200Ω), additional bypass capacitance may be
needed for optimal performance. Keep in mind that small
geometry (e.g., 0603) surface mount ceramic capacitors
haveamuchhigherselfresonantfrequencythandoleaded
capacitors, and perform best in high speed applications.
RF
RI
eno ≈ eni • 1+
Anystrayparasiticcapacitancestogroundatthesumming
junctions,+INand–IN,shouldbeminimized.Thisbecomes
especially true when the feedback resistor network uses
Feedback networks consisting of resistors with values
greater than about 200Ω will result in output noise which
is resistor noise and amplifier current noise dominant.
resistorvalues>500ΩincircuitswithR =R . Alwayskeep
F
I
in mind the differential nature of the LTC6405, and that it
is critical that the load impedances seen by both outputs
(stray or intended), should be as balanced and symmetric
as possible. This will help preserve the natural balance
of the LTC6405, which minimizes the generation of even
order harmonics, and improves the rejection of common
mode signals and noise.
RF
RI
2
eno ≈ 2 • I •R + 1+
• 4•k • T •RF
(
)
n
F
Lowerresistorvalues(<100Ω)alwaysresultinlowernoise
at the penalty of increased distortion due to increased
loading of the feedback network on the output. Higher
resistor values (but still less than <500Ω) will result in
higher output noise, but typically improved distortion due
to less loading on the output. The optimal feedback resis-
tance for the LTC6405 runs in between 100Ω to 500Ω.
It is highly recommended that the V
pin be bypassed
OCM
to ground with a high quality ceramic capacitor whose
value exceeds 0.01µF. This will help stabilize the common
mode feedbackloop aswell aspreventthermal noise from
the internal voltage divider and other external sources of
noise from being converted to differential noise due to
divider mismatches in the feedback networks. It is also
recommended that the resistive feedback networks be
comprised of 1% resistors (or better) to enhance the
output common mode rejection. This will also prevent
The differential filtered outputs +OUTF and –OUTF will
have a little higher noise than the unfiltered outputs (due
to the two 50Ω resistors which contribute 0.9nV/√Hz
each), but can provide superior signal-to-noise due to the
output noise filtering.
Layout Considerations
V
input referred common mode noise of the common
OCM
Because the LTC6405 is a very high speed amplifier, it is
sensitive to both stray capacitance and stray inductance.
In the QFN package, three pairs of power supply pins are
provided to keep the power supply inductance as low
as possible to prevent any degradation of amplifier 2nd
harmonic performance. It is critical that close attention be
paid to supply bypassing. For single supply applications
it is recommended that high quality 0.1µF surface mount
ceramic bypass capacitor be placed directly between each
mode amplifier path (which cannot be filtered) from being
converted to differential noise, degrading the differential
noise performance.
Feedback factor mismatch has a weak effect on distortion.
Using 1% or better resistors will limit any mismatch from
impacting amplifier linearity. However, in single supply
level shifting applications where there is a voltage differ-
ence between the input common mode voltage and the
output common mode voltage, resistor mismatch can
make the apparent voltage offset of the amplifier appear
worse than specified.
+
–
–
V and V pin with direct short connections. The V pins
should be tied directly to a low impedance ground plane
with minimal routing. For dual (split) power supplies, it is
6405fb
20
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LTC6405
applications inForMation
Interfacing the LTC6405 to A/D Converters
The capacitance of the filter network serves as a charge
reservoir to provide high frequency charging during the
sampling process, while the resistors of the filter network
are used to dampen and attenuate any charge kickback
from the ADC. The selection of the R-C time constant is
trialanderrorforagivenADC, butthefollowingguidelines
are recommended: Choosing too large of a resistor in the
decoupling network leaving insufficient settling time will
createavoltagedividerbetweenthedynamicinputimped-
ance of the ADC and the decoupling resistors. Choosing
too small of a resistor will possibly prevent the resistor
from properly dampening the load transient caused by
the sampling process, prolonging the time required for
settling. In 16-bit applications, this will typically require
a minimum of 11 R-C time constants. It is recommended
that the capacitor chosen have a high quality dielectric
(such as C0G multilayer ceramic).
Rail-to-rail input and fast settling time make the LTC6405
ideal for interfacing to low voltage, single supply, differ-
ential input ADCs. The sampling process of ADCs create
a sampling glitch caused by switching in the sampling
capacitorontheADCfrontendwhichmomentarily“shorts”
theoutputoftheamplifieraschargeistransferredbetween
the amplifier and the sampling capacitor. The amplifier
must recover and settle from this load transient before
this acquisition period ends for a valid representation of
the input signal. In general, the LTC6405 will settle much
more quickly from these periodic load impulses than from
a 2V input step, but it is a good idea to place an R-C filter
network between the differential outputs of the LTC6405
andtheinputoftheADCtohelpabsorbthechargeinjection
that comes out of the ADC from the sampling process.
1.8pF
V
, 2V
P-P
IN
200Ω
NC
200Ω
20Ω
16
15
14
13
+IN
–OUT
50Ω
–OUTF
LTC6405
SHDN
CONTROL
–
1.25pF
V
SHDN
12
1
2
–
+
+
V
V
V
D15
•
0.1µF
5V
+INA
–INA
11
5V
+
1.25pF
50Ω
•
4.7pF
4.7pF
+
4.7pF
0.1µF
V
LTC2208
GND V
V
D0
OCM
–
+
V
V
V
–
–
3
4
10
V
0.1µF
3.3V
1µF
V
CM
DD
–
V
–
1.25pF
1µF
V
OCM
9
0.1µF
V
–IN
+OUT
+OUTF
TIP
5
6
7
8
2.2µF
6405 F12
0.1µF
100Ω
200Ω
200Ω
20Ω
1.8pF
Figure 12. Interfacing the LTC6405 to an ADC
6405fb
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LTC6405
typical application
Attenuating and Level Shifting a Single-Ended 5V Signal to a
Differential 2VP-P Signal at a 1.25V Common Mode
C1, 2.7pF
2V DIFF OUTPUT
P-P
LEVEL-SHIFTED TO 1.25V
R3, 100Ω
3.3V
5V
R5
R1
511Ω
51.1Ω
– +
LTC6405
±5V SINE WAVE
(10V
R6
511Ω
R2
51.1Ω
LTC2207
)
V
P-P
IN
CENTERED AT 0V
+ –
6405 TA03
V
CM
= 1.25V
R4, 100Ω
2.2µF
C2, 2.7pF
6405fb
22
For more information www.linear.com/6405
LTC6405
package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev J)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074)
1
0.29
REF
1.88 ±0.102
(.074 ±.004)
1.68
(.066)
0.889 ±0.127
(.035 ±.005)
0.05 REF
DETAIL “B”
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
1.68 ±0.102
(.066 ±.004)
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
8
NO MEASUREMENT PURPOSE
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.65
(.0256)
BSC
0.52
(.0205)
REF
0.42 ±0.038
(.0165 ±.0015)
8
7 6 5
TYP
RECOMMENDED SOLDER PAD LAYOUT
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ±0.152
(.021 ±.006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ±0.0508
(.004 ±.002)
0.65
(.0256)
BSC
MSOP (MS8E) 0911 REV J
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
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23
For more information www.linear.com/6405
LTC6405
package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691 Rev Ø)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
1.45 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ±0.05
3.00 ±0.10
(4 SIDES)
15 16
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
1
2
1.45 ± 0.10
(4-SIDES)
(UD16) QFN 0904
0.200 REF
0.25 ±0.05
0.00 – 0.05
0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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24
For more information www.linear.com/6405
LTC6405
revision history (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
02/13 Changed operating voltage upper range from 5.5V to 5.25V
Changed voltage max spec from 0.4V to 0.45V
1, 3, 4
3
6405fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
25
LTC6405
typical application
DC-Coupled Level Shifting of Demodulator Output
5V
C5, 10pF
DIFF OUTPUT Z
130Ω| |2.5pF
DC LEVEL
1.5V
LT5575
5V
5V
R5, 324Ω
3.3V
C8
5pF
65Ω
5pF
4.7pF
DC LEVEL
3.8V
5V
R7
R9
65Ω
I
15nH
15nH
49.9Ω
10Ω
10dBm
+
–
–
C6
4.7pF
LTC2249
14-BIT ADC
R8
49.9Ω
R10
10Ω
LTC6405
RF IN
900MHz
–7dBm
+
5V
5V
V
CM
C1
4.7pF
C2
4.7pF
C7
4.7pF
4.7pF
3.9pF
6405 TA02
5pF
65Ω
5pF
V
= 1.5V
OCM
80MHz
SAMPLE
CLOCK
LO
OdBm
65Ω
Q
R6, 324Ω
IDENTICAL
Q CHANNEL
C4, 10pF
GAIN: 14dB
GAIN: 3dB
INPUT NF: 13dB
OIP3: 31dBm
INPUT NF: 11dB
OIP3: 44dBm AT 30MHz
relateD parts
PART NUMBER
DESCRIPTION
COMMENTS
A = 2V/V / A = 4V/V / A = 10V/V, NF = 12.3dB/14.5dB/
LT1993-2/LT1993-4/
LT1993-10
800MHz/900MHz/700MHz Low Distortion, Low Noise
Differential Amplifier/ADC Driver
V
V
V
12.7dB, OIP3 = 38dBm/40dBm/40dBm at 70MHz
LT1994
Low Noise, Low Distortion Fully differential Input/Output
Amplifier/Driver
Low Distortion, 2V , 1MHz: –94dBc, 13mA,
P-P
Low Noise: 3nV/
√Hz
LTC6400-8/LTC6400-14/ 1.8GHz Low Noise, Low Distortion, Differential ADC Driver
LTC6400-20/LTC6400-26
300MHz IF Amplifier, A = 20dB/26dB
V
LTC6401-8/LTC6401-14/ 1.3GHz Low Noise, Low Distortion, Differential ADC Driver
LTC6401-20/LTC6401-26
140MHz IF Amplifier, A = 20dB/26dB
V
LT6402-6/LT6402-12/
LT6402-20
300MHz/300MHz/300MHz Low Distortion, Low Noise
Differential Amplifier/ADC Driver
A = 6dB/A = 12dB/A = 20dB, NF = 18.6dB/15dB/12.4dB,
V V V
OIP3 = 49dBm/43dBm/51dBm at 20MHz
LTC6404-1/ LTC6404-2/ 600MHz Low Noise, Low Distortion, Differential ADC Driver
LTC6404-4
1.5nV/ Hz Noise, –90dBc Distortion at 10MHz
√
LTC6406
3GHz Low Noise, 3V, Rail-to-Rail Input Differential Amplifier/
Driver
1.6nV/√Hz Noise, –70dBc Distortion at 50MHz, 18mA, 3V Supply
LTC6411
Low Power Differential ADC Driver/Dual Selectable Gain
Amplifier
16mA Supply Current, IMD3 = –83dBC at 70MHz, A = 1, –1,
V
or 2
LT6600-2.5/LT6600-5/
LT6600-10/LT6600-20
Very Low Noise, Fully Differential Amplifier and 4th
Order Filter
2.5MHz/5MHz/10MHz/20MHz Integrated Filter, 3V Supply,
SO-8 Package
LTC6403-1
200MHz Low Noise, Low Power Differential ADC Driver
–95dBc Distortion at 3MHz, 10.8mA Supply Current
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LT 0213 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
26
(408)432-1900 FAX: (408) 434-0507 www.linear.com/6405
●
●
LINEAR TECHNOLOGY CORPORATION 2012
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