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LTC6802IG-2#PBF [Linear]

LTC6802-2 - Multicell Addressable Battery Stack Monitor; Package: SSOP; Pins: 44; Temperature Range: -40°C to 85°C;
LTC6802IG-2#PBF
型号： LTC6802IG-2#PBF
厂家： Linear    Linear
描述：

LTC6802-2 - Multicell Addressable Battery Stack Monitor; Package: SSOP; Pins: 44; Temperature Range: -40°C to 85°C

电池 光电二极管
文件： 总34页 (文件大小：854K)
中文：  中文翻译
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LTC6802-2  
Multicell Addressable  
Battery Stack Monitor  
FEATURES  
DESCRIPTION  
The LTC®6802-2 is a complete battery monitoring IC  
that includes a 12-bit ADC, a precision voltage reference,  
a high voltage input multiplexer and a serial interface.  
Each LTC6802-2 can measure 12 series connected bat-  
tery cells, with a total input voltage up to 60V. The voltage  
on all 12 input channels can be measured within 13ms.  
n
Qualified for Automotive Applications  
n
Measures Up to 12 Li-Ion Cells in Series (60V Max)  
n
Stackable Architecture Enables Monitoring High  
Voltage Battery Stacks  
n
Individually Addressable with 4-Bit Address  
n
0.25% Maximum Total Measurement Error  
n
13ms to Measure All Cells in a System  
Many LTC6802-2 devices can be stacked to measure  
the voltage of each cell in a long battery string. Each  
LTC6802-2 has an individually addressable serial inter-  
face, allowing up to 16 LTC6802-2 devices to interface to  
one control processor and operate simultaneously.  
n
Cell Balancing:  
n
On-Chip Passive Cell Balancing Switches  
n
Provision for Off-Chip Passive Balancing  
n
Two Thermistor Inputs Plus Onboard  
Temperature Sensor  
n
To minimize power, the LTC6802-2 offers a measure mode  
to monitor each cell for overvoltage and undervoltage  
conditions. A standby mode is also provided to reduce  
supply current to 50µA.  
1MHz Serial Interface with Packet Error Checking  
n
High EMI Immunity  
n
Delta-Sigma Converter with Built-In Noise Filter  
n
Open-Wire Connection Fault Detection  
Low Power Modes  
n
Each cell input has an associated MOSFET switch that can  
discharge any overcharged cell.  
n
44-Lead SSOP Package  
The related LTC6802-1 offers a serial interface that allows  
the serial ports of multiple LTC6802-1 devices to be daisy  
APPLICATIONS  
n
Electric and Hybrid Electric Vehicles  
chained without opto-couplers or isolators.  
n
High Power Portable Equipment  
All registered trademarks and trademarks are the property of their respective owners.  
n
Backup Battery Systems  
n
High Voltage Data Acquisition Systems  
TYPICAL APPLICATION  
Measurement Error Over  
Extended Temperature  
NEXT 12-CELL  
PACK ABOVE  
LTC6802-2  
DIE TEMP  
V+  
ꢒ.ꢓꢒ  
ꢔ RꢁꢋRꢁꢃꢁꢅꢆꢂꢆꢘꢙꢁ ꢄꢅꢘꢆꢃ  
ꢒ.ꢏꢐ  
+
ꢙ ꢚ ꢛꢓ.ꢏꢙ  
ꢃ
ꢍꢁꢜꢜ ꢙꢇꢜꢆꢂꢝꢁ ꢓ.ꢕꢙ  
ꢒ.ꢏꢒ  
ꢒ.ꢎꢐ  
SERIAL DATA  
REGISTERS  
AND  
CONTROL  
ꢒ.ꢎꢒ  
4-BIT  
ADDRESS  
ꢒ.ꢒꢐ  
12-CELL  
BATTERY  
STRING  
MUX  
ꢒ
ꢑꢒ.ꢒꢐ  
ꢑꢒ.ꢎꢒ  
ꢑꢒ.ꢎꢐ  
ꢑꢒ.ꢏꢒ  
ꢑꢒ.ꢏꢐ  
ꢑꢒ.ꢓꢒ  
+
+
12-BIT  
∆∑ ADC  
V–  
VOLTAGE  
REFERENCE  
ꢑꢐꢒ ꢑꢏꢐ  
ꢒ
ꢏꢐ  
ꢐꢒ  
ꢔꢐ ꢎꢒꢒ ꢎꢏꢐ  
EXTERNAL  
TEMP  
ꢆꢁꢀꢋꢁRꢂꢆꢄRꢁ ꢈꢌꢍꢊ  
NEXT 12-CELL  
PACK BELOW  
ꢕꢖꢒꢏꢏ ꢆꢂꢒꢎꢗ  
68022 TA01a  
100k  
100k NTC  
Rev. B  
1
Document Feedback  
For more information www.analog.com  
LTC6802-2  
ABSOLUTE MAXIMUM RATINGS  
PIN CONFIGURATION  
(Note 1)  
+
–
ꢊꢋꢌ ꢍꢎꢏꢐ  
Total Supply Voltage (V to V ).................................60V  
–
ꢠ
Input Voltage (Relative to V )  
ꢀ
ꢓꢘBꢎ  
ꢘꢗꢋ  
ꢘꢗꢎ  
ꢃꢃ  
ꢍ
ꢓꢀꢁ  
ꢘꢀꢁ  
ꢓꢀꢀ  
ꢘꢀꢀ  
ꢓꢀꢉ  
ꢘꢀꢉ  
ꢓꢈ  
ꢁ
ꢂ
ꢃꢂ  
ꢃꢁ  
ꢃꢀ  
ꢃꢉ  
ꢂꢈ  
ꢂꢇ  
ꢂꢆ  
ꢂꢅ  
ꢂꢄ  
ꢂꢃ  
ꢂꢂ  
ꢂꢁ  
ꢂꢀ  
ꢂꢉ  
ꢁꢈ  
ꢁꢇ  
ꢁꢆ  
ꢁꢅ  
ꢁꢄ  
ꢁꢃ  
ꢁꢂ  
C1 ............................................................ –0.3V to 9V  
+
+
C12 .......................................... V – 0.6V to V + 0.3V  
Cn (Note 5) ......................... –0.3V to Min (9 • n, 60V)  
Sn (Note 5) ......................... –0.3V to Min (9 • n, 60V)  
All Other Pins........................................... –0.3V to 7V  
Voltage Between Inputs  
ꢃ
ꢘꢓꢔꢎ  
ꢒꢂ  
ꢄ
ꢅ
ꢒꢁ  
ꢆ
ꢒꢀ  
ꢇ
ꢒꢉ  
Cn to Cn – 1............................................. –0.3V to 9V  
Sn to Cn – 1............................................. –0.3V to 9V  
C12 to C8............................................... –0.3V to 25V  
C8 to C4................................................. –0.3V to 25V  
ꢈ
ꢑꢌꢎꢋꢁ  
ꢑꢌꢎꢋꢀ  
ꢐꢗꢊB  
ꢚꢚB  
ꢊꢋꢘ  
ꢘꢈ  
ꢀꢉ  
ꢀꢀ  
ꢀꢁ  
ꢀꢂ  
ꢀꢃ  
ꢀꢄ  
ꢀꢅ  
ꢀꢆ  
ꢀꢇ  
ꢀꢈ  
ꢁꢉ  
ꢁꢀ  
ꢁꢁ  
ꢓꢇ  
ꢘꢇ  
ꢓꢆ  
–
C4 to V ................................................. –0.3V to 25V  
ꢘꢆ  
Operating Temperature Range .................–40°C to 85°C  
Specified Temperature Range ..................–40°C to 85°C  
Junction Temperature ........................................... 150°C  
Storage Temperature Range .................. –65°C to 150°C  
*n = 1 to 12  
ꢍ
Rꢏꢑ  
ꢓꢅ  
ꢍ
Rꢏꢡ  
ꢘꢅ  
ꢍ
ꢓꢄ  
ꢊꢏꢚꢌꢁ  
ꢍ
ꢘꢄ  
ꢊꢏꢚꢌꢀ  
ꢢꢓ  
ꢓꢃ  
ꢣ
ꢍ
ꢘꢃ  
ꢘꢀ  
ꢓꢀ  
ꢘꢁ  
ꢓꢂ  
ꢘꢂ  
ꢓꢁ  
ꢑ ꢌꢒꢓꢔꢒꢑꢏ  
ꢃꢃꢕꢖꢏꢒꢗ ꢌꢖꢒꢘꢊꢎꢓ ꢘꢘꢋꢌ  
ꢜ ꢀꢄꢉꢝꢓꢞ θ ꢜ ꢆꢉꢝꢓꢟꢐ  
ꢊ
ꢙꢚꢒꢛ  
ꢙꢒ  
ORDER INFORMATION  
TUBE  
TAPE AND REEL  
PART MARKING  
PACKAGE DESCRIPTION  
SPECIFID TEMPERATURE RANGE  
–40°C to 85°C  
LTC6802IG-2#PBF  
LTC6802IG-2#3ZZPBF  
LTC6802IG-2#TRPBF  
LTC6802G-2  
44-Lead Plastic SSOP  
44-Lead Plastic SSOP  
LTC6802IG-2#3ZZTRPBF LTC6802G-2  
–40°C to 85°C  
Contact the factory for parts specified with wider operating temperature ranges.  
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.  
Versions of the LTC6802-2 models are available with controlled manufacturing to support the quality and reliability requirements of automotive  
applications. These models are available with #WTRPBF, #WPBF or #ZZPBF suffix and are listed in ADI’s ARPL.  
Note that these automotive models may have specifications that differ from the commercial models; therefore designers should review the Electrical  
Characteristics section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact  
your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for  
these models.  
Rev. B  
2
For more information www.analog.com  
LTC6802-2  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted.  
SYMBOL PARAMETER  
DC Specifications  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
l
l
V
V
Measurement Resolution  
ADC Offset Voltage  
ADC Gain Error  
Quantization of the ADC  
(Note 2)  
1.5  
mV/Bit  
mV  
ACC  
–0.5  
0.5  
(Note 2)  
–0.12  
–0.22  
0.12  
0.22  
%
%
l
Total Measurement Error  
(Note 4)  
ERR  
V
= 0V  
0.8  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
CELL  
V
= 2.3V  
= 2.3V  
= 3.6V  
= 3.6V  
= 4.2V  
= 4.2V  
= 4.6V  
–2.8  
–5.1  
–4.3  
–7.9  
–5  
2.8  
5.1  
4.3  
7.9  
5
CELL  
CELL  
CELL  
CELL  
CELL  
CELL  
CELL  
TEMP  
TEMP  
TEMP  
l
l
l
V
V
V
V
V
V
V
V
V
–9.2  
9.2  
8
5
l
l
l
= 2.3V  
= 3.6V  
= 4.2V  
–5.1  
–7.9  
–9.2  
5.1  
7.9  
9.2  
V
V
Cell Voltage Range  
Full-Scale Voltage Range  
V
CELL  
CM  
l
l
l
l
Common Mode Voltage Range Measured Range of Inputs Cn for <0.25% Gain Error, n = 3 to 11  
3.7  
1.8  
1.2  
0
5 • n  
15  
10  
5
V
V
V
V
–
Relative to V  
Range of Input C3 for <1% Gain Error  
Range of Input C2 for <0.25% Gain Error  
Range of Input C1 for <0.25% Gain Error  
l
l
Overvoltage (OV) Detection Level  
Undervoltage (UV) Detection Level  
Die Temperature Measurement Error  
Reference Pin Voltage  
Programmed for 4.2V  
Programmed for 2.3V  
4.182  
2.290  
4.200  
2.300  
3
4.218  
2.310  
V
V
Error in Measurement at 125°C  
°C  
–
V
REF  
R
LOAD  
= 100k to V  
3.020  
3.015  
3.065  
3.065  
3.110  
3.115  
V
V
l
Reference Voltage Temperature  
Coefficient  
8
ppm/°C  
Reference Voltage Thermal Hysteresis  
Reference Voltage Long-Term Drift  
Regulator Pin Voltage  
25°C to 85°C and 25°C to –40°C  
100  
60  
ppm  
ppm/√kHr  
+
l
l
V
V
10 < V < 50, No Load  
4.5  
4.1  
5.0  
4.8  
5.5  
V
V
REG  
S
I
= 4mA  
LOAD  
l
Regulator Pin Short-Circuit Current Limit  
5
8
mA  
+
–
l
l
Supply Voltage, V Relative to V  
V
Specifications Met  
10  
4
50  
50  
V
V
ERR  
Timing Specifications Met  
I
Input Bias Current  
In/Out of Pins C1 Through C12  
When Measuring Cells  
B
l
l
–10  
10  
µA  
nA  
When Not Measuring Cells  
1
+
I
I
Supply Current, Active  
Current Into the V Pin When Measuring Voltages with  
0.8  
1.1  
1.2  
mA  
mA  
S
the ADC  
+
Supply Current, Monitor Mode  
Average Current Into the V Pin While Monitoring for  
M
UV and OV Conditions  
Continuous Monitoring (CDC = 2)  
Monitor Every 130ms (CDC = 5)  
Monitor Every 500ms (CDC = 6)  
Monitor Every 2 Seconds (CDC = 7)  
800  
225  
150  
100  
µA  
µA  
µA  
µA  
+
I
QS  
Supply Current, Idle  
Current Into the V Pin When Idle  
37.5  
32.5  
62.5  
82.5  
87.5  
µA  
µA  
l
All Serial Port Pins at Logic ‘1’  
Rev. B  
3
For more information www.analog.com  
LTC6802-2  
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. V+ = 43.2V, V– = 0V, unless otherwise noted.  
SYMBOL PARAMETER  
Discharge Switch On-Resistance  
CONDITIONS  
> 3V (Note 3)  
MIN  
TYP  
MAX  
20  
UNITS  
Ω
l
l
V
10  
CELL  
Temperature Range  
–40  
85  
°C  
Thermal Shutdown Temperature  
Thermal Shutdown Hysteresis  
145  
5
°C  
°C  
Timing Specifications  
l
l
t
Measurement Cycle Time  
Time Required to Measure 11 or 12 Cells  
Time Required to Measure Up to 10 Cells  
Time Required to Measure 1 Cell  
11  
9.2  
1
13  
11  
1.2  
16  
13.5  
1.5  
ms  
ms  
ms  
CYCLE  
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
SDI Valid to SCKI Rising Setup  
SDI Valid to SCKI Rising Hold  
SCKI Low  
10  
ns  
ns  
1
2
3
4
5
6
7
8
250  
400  
400  
400  
100  
100  
ns  
SCKI High  
ns  
CSBI Pulse Width  
ns  
SCKI Rising to CSBI Rising  
CSBI Falling to SCKI Rising  
SCKI Falling to SDO Valid  
Clock Frequency  
ns  
ns  
250  
1
ns  
MHz  
s
Watchdog Timer Time-Out Period  
1
2
2.5  
Digital I/O Specifications  
l
l
l
V
V
V
Digital Voltage Input High  
Digital Voltage Input Low  
Digital Voltage Output Low  
V
V
V
IH  
IL  
0.8  
0.3  
Sinking 500µA  
OL  
Note 1: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
Note 4: V  
refers to the voltage applied across the following pin  
CELL  
–
combinations: Cn to Cn – 1 for n = 2 to 12, C1 to V . V  
voltage applied from V  
Note 5: These absolute maximum ratings apply provided that the voltage  
refers to the  
TEMP  
–
or V  
to V  
TEMP1  
TEMP2  
Note 2: The ADC specifications are guaranteed by the total measurement  
between inputs do not exceed their absolute maximum ratings.  
error (V ) specification.  
ERR  
Note 3: Due to the contact resistance of the production tester, this  
specification is tested to relaxed limits. The 20Ω limit is guaranteed by  
design.  
Rev. B  
4
For more information www.analog.com  
LTC6802-2  
TYPICAL PERFORMANCE CHARACTERISTICS  
Cell Measurement Total  
Measurement Gain Error  
Hysteresis  
Cell Measurement Total  
Unadjusted Error  
Unadjusted Error vs Input  
Resistance  
ꢍꢎ  
ꢍꢏ  
ꢕꢎ  
ꢕꢏ  
ꢎ
ꢑꢊ  
ꢓ
ꢑꢊ  
ꢊ
ꢓ
ꢘ ꢗꢎꢙꢀ ꢓꢇ ꢍꢎꢙꢀ  
ꢅ
ꢅ
ꢅ
ꢅ
ꢚ ꢒꢔꢊꢛꢀ  
ꢚ ꢖꢗꢛꢀ  
ꢚ ꢓꢗꢛꢀ  
ꢚ ꢑꢖꢗꢛꢀ  
ꢂ
ꢆ
ꢆ
ꢆ
ꢆ
ꢕ
ꢒꢑꢊ  
ꢒꢓꢊ  
ꢒꢖꢊ  
ꢒꢔꢊ  
ꢒꢗꢊ  
ꢒꢕꢊ  
ꢒꢘꢊ  
ꢒꢙꢊ  
ꢔ
ꢖ
ꢊ
R
ꢏ
R
ꢏ
R
ꢏ
R
ꢏ
ꢚ ꢑꢛ  
ꢚ ꢓꢛ  
ꢚ ꢗꢛ  
ꢚ ꢑꢊꢛ  
ꢒꢖ  
ꢒꢔ  
ꢒꢕ  
ꢒꢓ  
ꢒꢑꢊ  
R
ꢜꢌ ꢏꢁRꢜꢁꢏ ꢝꢜꢅꢞ ꢀn ꢆꢌꢍ ꢀn ꢒ ꢑ  
ꢏ
ꢌꢄ ꢁꢟꢅꢁRꢌꢆꢂ ꢀꢆꢠꢆꢀꢜꢅꢆꢌꢀꢁ ꢄꢌ  
ꢀn ꢆꢌꢍ ꢀn ꢒ ꢑ  
ꢏ
ꢌꢍꢎꢏꢌꢍꢏꢏꢌꢕꢎꢏꢌꢕꢏꢏ ꢌꢎꢏ  
ꢏ
ꢎꢏ ꢕꢏꢏ ꢕꢎꢏ ꢍꢏꢏ  
ꢊ
ꢊ.ꢗ ꢑ.ꢊ ꢑ.ꢗ ꢖ.ꢊ ꢖ.ꢗ ꢘ.ꢊ ꢘ.ꢗ ꢔ.ꢊ ꢔ.ꢗ ꢗ.ꢊ  
ꢊ
ꢊ.ꢗ ꢑ.ꢊ ꢑ.ꢗ ꢓ.ꢊ ꢓ.ꢗ ꢖ.ꢊ ꢖ.ꢗ ꢔ.ꢊ ꢔ.ꢗ ꢗ.ꢊ  
ꢀꢁꢂꢃꢄꢅ ꢆꢃ ꢄꢂꢆꢃ ꢅRRꢇR ꢈꢉꢉꢊꢋ  
ꢀꢁꢂꢂ ꢃꢄꢂꢅꢆꢇꢁ ꢈꢃꢉ  
ꢀꢁꢂꢂ ꢃꢄꢂꢅꢆꢇꢁ ꢈꢃꢉ  
ꢖꢗꢏꢍꢍ ꢄꢍꢏ  
ꢕꢓꢊꢖꢖ ꢇꢊꢙ  
ꢕꢙꢊꢓꢓ ꢇꢑꢊ  
Measurement Gain Error  
Hysteresis  
Cell Measurement Common Mode  
Rejection  
ADC Normal Mode Rejection vs  
Frequency  
ꢍꢏ  
ꢕꢗ  
ꢕꢖ  
ꢕꢘ  
ꢕꢍ  
ꢕꢏ  
ꢗ
ꢀ
ꢁꢂꢀ  
ꢁꢅꢀ  
ꢁꢃꢀ  
ꢁꢆꢀ  
ꢁꢄꢀ  
ꢁꢇꢀ  
ꢁꢈꢀ  
ꢀ
ꢁꢂꢀ  
ꢁꢅꢀ  
ꢁꢃꢀ  
ꢁꢆꢀ  
ꢁꢄꢀ  
ꢁꢇꢀ  
ꢁꢈꢀ  
ꢓ
ꢙ ꢌꢘꢎꢚꢀ ꢓꢇ ꢍꢎꢚꢀ  
ꢞ ꢟ ꢄꢞ  
ꢎꢝꢐꢖꢍꢓ ꢠꢡꢠ  
ꢂ
ꢈꢅꢘB Rꢊꢔꢊꢎꢕꢖꢗꢍ  
ꢎꢗRRꢊꢢꢠꢗꢍꢣꢢ ꢕꢗ  
ꢤꢊꢢꢢ ꢕꢑꢥꢍ ꢂ Bꢖꢕ  
ꢥꢕ ꢥꢣꢎ ꢗꢌꢕꢠꢌꢕ  
ꢖ
ꢘ
ꢍ
ꢏ
ꢌꢍꢎꢏꢌꢍꢏꢏꢌꢕꢎꢏꢌꢕꢏꢏ ꢌꢎꢏ  
ꢏ
ꢎꢏ ꢕꢏꢏ ꢕꢎꢏ ꢍꢏꢏ  
ꢂꢀ  
ꢂꢀꢀ  
ꢂꢜ  
ꢂꢀꢜ ꢂꢀꢀꢜ  
ꢂꢝ  
ꢂꢀꢝ  
ꢂꢀ  
ꢂꢀꢀ  
ꢂꢜ  
ꢂꢀꢜ  
ꢂꢀꢀꢜ  
ꢀꢁꢂꢃꢄꢅ ꢆꢃ ꢄꢂꢆꢃ ꢅRRꢇR ꢈꢉꢉꢊꢋ  
ꢉRꢊꢋꢌꢊꢍꢎꢏ ꢐꢑꢒꢓ  
ꢉRꢊꢋꢌꢊꢍꢎꢏ ꢐꢑꢒꢓ  
ꢖꢗꢏꢍꢍ ꢄꢍꢕ  
ꢇꢚꢀꢅꢅ ꢛꢂꢄ  
ꢇꢚꢀꢅꢅ ꢛꢂꢆ  
ADC INL  
ADC DNL  
Cell Input Bias Current in Standby  
ꢑꢌ  
ꢋꢌ  
ꢒꢌ  
ꢓꢌ  
ꢔꢌ  
ꢌ
ꢋ.ꢈ  
ꢌ.ꢍ  
ꢌ.ꢈ  
ꢈ.ꢍ  
ꢈ.ꢐ  
ꢌ.ꢈ  
ꢈ.ꢏ  
ꢈ.ꢍ  
ꢈꢔ  
ꢈ.ꢎ  
ꢈ
ꢈ
ꢈꢔꢓ  
ꢑꢈ.ꢎ  
ꢑꢈ.ꢏ  
ꢑꢈ.ꢐ  
ꢑꢈ.ꢍ  
ꢑꢌ.ꢈ  
ꢎꢈ.ꢍ  
ꢎꢌ.ꢈ  
ꢎꢌ.ꢍ  
ꢎꢋ.ꢈ  
ꢈꢓ ꢀꢘ ꢈꢔꢔ  
ꢊꢔꢌ  
ꢊꢋꢌ ꢊꢓꢌ  
ꢌ
ꢓꢌ ꢋꢌ ꢖꢌ ꢕꢌ ꢔꢌꢌ ꢔꢓꢌ  
ꢈ
ꢌ
ꢋ
ꢓ
ꢏ
ꢍ
ꢈ
ꢌ
ꢎ
ꢔ
ꢏ
ꢓ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ  
ꢀꢁꢂꢃꢄ ꢅꢆꢇ  
ꢀꢁꢂꢃꢄ ꢅꢆꢇ  
ꢖꢕꢌꢓꢓ ꢗꢌꢒ  
ꢐꢑꢈꢋꢋ ꢒꢈꢍ  
ꢐꢍꢈꢎꢎ ꢒꢈꢐ  
Rev. B  
5
For more information www.analog.com  
LTC6802-2  
TYPICAL PERFORMANCE CHARACTERISTICS  
Cell Input Bias Current During  
Conversion  
Supply Current vs Supply Voltage  
Standby  
Supply Current vs Supply Voltage  
in CDC = 2  
ꢒꢍ  
ꢓꢍ  
ꢔꢍ  
ꢕꢍ  
ꢖꢍ  
ꢗꢍ  
ꢍ
ꢍ.ꢑꢍ  
ꢍ.ꢒꢓ  
ꢍ.ꢒꢍ  
ꢍ.ꢔꢓ  
ꢍ.ꢔꢍ  
ꢍ.ꢕꢓ  
ꢍ.ꢕꢍ  
ꢑ.ꢒꢌ  
ꢑ.ꢓꢔ  
ꢑ.ꢓꢌ  
ꢑ.ꢔꢔ  
ꢑ.ꢔꢌ  
ꢑ.ꢋꢔ  
ꢑ.ꢋꢌ  
ꢑ.ꢕꢔ  
ꢎꢜꢎ ꢚ ꢖ ꢋꢎꢆꢏꢇꢝꢏꢁꢆꢁꢀ  
ꢎꢊꢃꢃ ꢎꢆꢏꢅꢊRꢀꢝꢆꢏꢀꢌ  
ꢈꢁꢙꢙ ꢍꢎꢃꢅꢀ ꢚ ꢕ.ꢓꢛ  
ꢇ
ꢚ ꢒꢓꢛꢎ  
ꢈ
ꢇ
ꢚ ꢖꢓꢛꢎ  
ꢈ
ꢇ
ꢚ ꢞꢗꢍꢛꢎ  
ꢈ
ꢇ
ꢇ
ꢇ
ꢙ ꢚꢔꢍꢛꢐ  
ꢙ ꢖꢓꢛꢐ  
ꢙ ꢘꢓꢛꢐ  
ꢈ
ꢈ
ꢈ
ꢍ
ꢗꢍ  
ꢖꢍ  
ꢕꢍ  
ꢔꢍ  
ꢓꢍ  
ꢒꢍ  
ꢍ
ꢘꢍ  
ꢖꢍ  
ꢙꢍ  
ꢗꢍ  
ꢓꢍ  
ꢕꢍ  
ꢊꢋꢌ ꢊꢑꢌ  
ꢌ
ꢑꢌ ꢋꢌ ꢓꢌ ꢖꢌ ꢗꢌꢌ ꢗꢑꢌ  
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ  
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ  
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ  
ꢒꢘꢍꢖꢖ ꢉꢍꢗ  
ꢕꢒꢍꢖꢖ ꢉꢍꢖ  
ꢓꢖꢌꢑꢑ ꢘꢌꢋ  
External Temperature  
Internal Die Temperature  
Measurement vs Ambient  
Temperature  
Measurement Total Unadjusted  
Error vs Input  
VREF Output Voltage vs  
Temperature  
ꢓꢎ  
ꢕ
ꢀ
ꢂ
ꢏ.ꢌꢐꢌ  
ꢏ.ꢌꢑꢒ  
ꢏ.ꢌꢑꢑ  
ꢏ.ꢌꢑꢓ  
ꢏ.ꢌꢑꢔ  
ꢏ.ꢌꢑꢌ  
ꢏ.ꢌꢋꢒ  
ꢏ.ꢌꢋꢑ  
ꢜ
ꢗ
ꢢ ꢂꢅ.ꢃꢜ  
ꢅ
ꢃ
ꢎ
ꢆ
ꢔꢕ  
ꢄ
ꢁꢆ  
ꢁꢃ  
ꢁꢅ  
ꢁꢂ  
ꢁꢀ  
ꢔꢓꢎ  
ꢔꢓꢕ  
ꢔꢖꢎ  
ꢀ
ꢀ
ꢀ
ꢀ
ꢛ ꢔꢗꢎꢜꢝ  
ꢛ ꢖꢕꢜꢝ  
ꢛ ꢚꢕꢜꢝ  
ꢛ ꢓꢎꢕꢜꢝ  
ꢄ
ꢄ
ꢄ
ꢄ
ꢓꢊꢜꢉꢑꢊ ꢉꢋ ꢗꢌꢇꢋꢓBꢝ ꢍRꢉꢞR ꢌꢞ  
ꢈꢇꢟꢉꢋꢚ ꢓꢉꢊ ꢈꢊꢇꢗꢎRꢊꢈꢊꢋꢌꢗ  
ꢌꢞ ꢈꢉꢋꢉꢈꢉꢠꢊ ꢗꢊꢖꢔ ꢡꢊꢇꢌꢉꢋꢚ  
ꢋ RꢁꢃRꢁꢗꢁꢘꢀꢄꢀꢙꢍꢁ ꢅꢘꢙꢀꢗ  
ꢎ
ꢎ.ꢕ ꢓ.ꢎ ꢓ.ꢕ ꢖ.ꢎ ꢖ.ꢕ ꢘ.ꢎ ꢘ.ꢕ ꢗ.ꢎ ꢗ.ꢕ ꢕ.ꢎ  
ꢁꢀꢄ ꢁꢃꢀ  
ꢄ
ꢃꢀ  
ꢀꢄ  
ꢛꢀ ꢆꢄꢄ ꢆꢃꢀ  
ꢊꢋꢌ ꢊꢔꢋ  
ꢌ
ꢔꢋ  
ꢋꢌ  
ꢐꢋ ꢕꢌꢌ ꢕꢔꢋ  
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢃꢅꢀ ꢈꢉꢊꢀꢄꢋꢁ ꢌꢈꢍ  
ꢇꢈBꢉꢊꢋꢌ ꢌꢊꢈꢍꢊRꢇꢌꢎRꢊ ꢏꢐꢑꢒ  
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ  
ꢙꢚꢎꢖꢖ ꢋꢓꢘ  
ꢘꢙꢄꢃꢃ ꢚꢆꢃ  
ꢑꢒꢌꢔꢔ ꢖꢔꢔ  
VREF Load Regulation  
VREF Line Regulation  
VREG Load Regulation  
ꢐ.ꢍꢑ  
ꢐ.ꢍꢒ  
ꢐ.ꢍꢓ  
ꢐ.ꢍꢔ  
ꢐ.ꢍꢖ  
ꢐ.ꢍꢕ  
ꢏ.ꢍꢐꢑ  
ꢏ.ꢍꢐꢒ  
ꢏ.ꢍꢐꢍ  
ꢏ.ꢍꢓꢔ  
ꢏ.ꢍꢓꢓ  
ꢏ.ꢍꢓꢑ  
ꢏ.ꢍꢓꢒ  
ꢏ.ꢍꢓꢍ  
ꢐ.ꢑ  
ꢐ.ꢒ  
ꢐ.ꢍ  
ꢑ.ꢓ  
ꢑ.ꢔ  
ꢑ.ꢑ  
ꢑ.ꢒ  
ꢑ.ꢍ  
ꢛꢆ ꢊꢜꢇꢊRꢛꢈꢃ ꢃꢆꢈꢝ ꢆꢛ ꢅ ꢞ ꢙꢝꢙ ꢗ ꢒ  
Rꢊꢎ  
ꢋꢙꢆꢛꢇꢟꢛꢁꢆꢁꢀ ꢙꢊꢃꢃ ꢙꢆꢛꢅꢊRꢀꢟꢆꢛꢀꢌ  
ꢈ
ꢙ ꢓꢐꢚꢅ  
ꢙ ꢒꢐꢚꢅ  
ꢋ
ꢇ
ꢗ ꢒꢖꢘꢙ  
ꢗ ꢔꢖꢘꢙ  
ꢈ
ꢈ
ꢋ
ꢇ
ꢈ
ꢈ
ꢙ ꢛꢑꢍꢚꢅ  
ꢋ
ꢇ
ꢗ ꢚꢑꢍꢘꢙ  
ꢈ
ꢈ
ꢈ
ꢈ
ꢙ ꢚꢕꢍꢛꢃ  
ꢙ ꢘꢖꢛꢃ  
ꢙ ꢒꢖꢛꢃ  
ꢋ
ꢋ
ꢋ
ꢍ
ꢗꢍ  
ꢗꢍꢍ  
ꢗꢍꢍꢍ  
ꢍ
ꢕꢍ  
ꢒꢍ  
ꢏꢍ  
ꢑꢍ  
ꢖꢍ  
ꢓꢍ  
ꢍ
ꢕ
ꢒ
ꢖ
ꢑ
ꢐ
ꢔ
ꢗ
ꢓ
ꢘ
ꢕꢍ  
ꢀꢁꢂRꢃꢄꢅꢆ ꢃꢂRRꢇꢅꢈ ꢉꢊꢋꢌ  
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ  
ꢀꢁꢂꢂꢃꢄ ꢅꢁRRꢆꢇꢈ ꢉꢊꢋꢌ  
ꢔꢒꢍꢘꢘ ꢆꢍꢓ  
ꢓꢔꢍꢒꢒ ꢉꢍꢔ  
ꢔꢓꢍꢒꢒ ꢏꢕꢔ  
Rev. B  
6
For more information www.analog.com  
LTC6802-2  
TYPICAL PERFORMANCE CHARACTERISTICS  
Internal Discharge Resistance vs  
Cell Voltage  
VREG Line Regulation  
ꢍ.ꢍ  
ꢍ.ꢎ  
ꢏ.ꢍ  
ꢏ.ꢎ  
ꢐ.ꢍ  
ꢐ.ꢎ  
50  
T
T
T
T
= –45°C  
= 25°C  
= 85°C  
= 105°C  
A
A
A
A
45  
40  
35  
30  
25  
20  
15  
10  
5
ꢇ
ꢖ ꢔꢍꢗꢘ  
ꢈ
ꢇ
ꢖ ꢙꢏꢎꢗꢘ  
ꢈ
ꢇ
ꢖ ꢑꢍꢗꢘ  
ꢈ
ꢚꢆ ꢊꢛꢇꢊRꢚꢈꢃ ꢃꢆꢈꢜ ꢆꢚ ꢅ ꢝ ꢘꢜꢘ ꢖ ꢑ  
Rꢊꢉ  
ꢋꢘꢆꢚꢇꢞꢚꢁꢆꢁꢀ ꢘꢊꢃꢃ ꢘꢆꢚꢅꢊRꢀꢞꢆꢚꢀꢌ  
0
ꢍ
ꢒꢍ  
ꢑꢍ  
ꢐꢍ  
ꢏꢍ  
ꢍꢍ  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
ꢀꢁꢂꢂꢃꢄ ꢅꢆꢃꢇꢈꢉꢊ ꢋꢅꢌ  
CELL VOLTAGE (V)  
ꢓꢔꢎꢑꢑ ꢉꢒꢕ  
68022 G11  
Die Temperature Increase vs  
Discharge Current in Internal FET  
Cell Conversion Time  
ꢓꢐ  
ꢔꢓ  
ꢔꢐ  
ꢕꢓ  
ꢕꢐ  
ꢖꢓ  
ꢖꢐ  
ꢗꢓ  
ꢗꢐ  
ꢓ
ꢔꢕ.ꢖꢌ  
ꢔꢕ.ꢔꢗ  
ꢔꢕ.ꢔꢌ  
ꢔꢕ.ꢌꢗ  
ꢔꢕ.ꢌꢌ  
ꢔꢖ.ꢙꢗ  
ꢔꢖ.ꢙꢌ  
ꢔꢖ.ꢘꢗ  
ꢔꢖ.ꢘꢌ  
ꢅꢌꢌ ꢗꢖ ꢃꢇꢌꢌꢂ ꢅꢊ ꢕ.ꢙꢛ  
ꢛ
ꢜ ꢔꢕ.ꢖꢛ  
ꢜ ꢖꢓꢒꢃ  
ꢂ
ꢅ
ꢊ
ꢗꢖ ꢃꢇꢌꢌꢂ  
ꢀꢁꢂꢃꢄꢅRꢆꢁꢉꢆ  
ꢙ ꢃꢇꢌꢌꢂ  
ꢀꢁꢂꢃꢄꢅRꢆꢁꢉꢆ  
ꢗ ꢃꢇꢌꢌ  
ꢀꢁꢂꢃꢄꢅRꢆꢁꢉꢆ  
ꢐ
ꢐ
ꢗꢐ ꢖꢐ ꢕꢐ ꢔꢐ ꢓꢐ ꢙꢐ ꢚꢐ ꢘꢐ  
ꢀꢁꢂꢃꢄꢅRꢆꢇ ꢃꢈRRꢇꢉꢊ ꢋꢇR ꢃꢇꢌꢌ ꢍꢎꢅꢏ  
ꢊꢋꢌ ꢊꢖꢌ  
ꢌ
ꢖꢌ ꢋꢌ ꢚꢌ ꢘꢌ ꢔꢌꢌ ꢔꢖꢌ  
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ  
ꢙꢘꢐꢖꢖ ꢆꢗꢘ  
ꢚꢘꢌꢖꢖ ꢛꢔꢙ  
Rev. B  
7
For more information www.analog.com  
LTC6802-2  
PIN FUNCTIONS  
V+ (Pin 1): Tie Pin 1 to the most positive potential in  
VREF (Pin 30): 3.075V Voltage Reference Output. This pin  
+
the battery stack. V must be approximately the same  
should be bypassed with a 1µF capacitor. The VREF pin can  
–
potential as C12.  
drive a 100k resistive load connected to V . Larger loads  
should be buffered with an LT6003 op amp, or similar  
device.  
C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1  
(Pins 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24): C1  
through C12 are the inputs for monitoring battery cell  
voltages. Up to 12 cells can be monitored. The lowest  
V
(Pin 31): Linear Voltage Regulator Output. This pin  
REG  
should be bypassed with a 1µF capacitor. The VREG is  
–
potential is tied to the V pin. The next lowest potential is  
capable of sourcing up to 4mA to an external load. The  
V
tied to C1 and so forth. See the figures in the Applications  
Information section for more details on connecting bat-  
teries to the LTC6802-2.  
pin does not sink current.  
REG  
TOS (Pin 32): Top of Stack Input. The TOS pin can be tied  
–
to V  
or V for the LTC6802-2. The state of the TOS pin  
REG  
S12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1  
(Pins 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25): S1  
though S12 pins are used to balance battery cells. If one  
cell in a series becomes over charged, an S output can  
be used to discharge the cell. Each S output is an inter-  
nal N-channel MOSFET for discharging. See the Block  
Diagram. The NMOS has a maximum on-resistance of  
20Ω. An external resistor should be connected in series  
with the NMOS to dissipate heat outside of the LTC6802-2  
package. When using the internal MOSFETs to discharge  
cells, the die temperature should be monitored. See Power  
Dissipation and Thermal Shutdown in the Applications  
Information section.  
alters the operation of the SDO pin in the toggle polling  
mode. See the Serial Port description.  
MMB (Pin 33): Monitor Mode Input (Active Low). When  
MMB is low (same potential as V–), the LTC6802-2  
goes into monitor mode. See Modes of Operation in the  
Applications Information section.  
WDTB (Pin 34): Watchdog Timer Output (Active Low). If  
there is no activity on the SCKI pin for 2.5 seconds, the  
WDTB output is asserted. The WDTB pin is an open-drain  
NMOS output. When asserted it pulls the output down  
–
to V and resets the configuration register to its default  
state. See Watchdog Timer Circuit in the Applications  
Informationn section.  
The S pins also feature an internal 10k pull-up resistor. This  
allows the S pins to be used to drive the gates of external  
P-channel MOSFETs for higher discharge capability.  
GPIO1, GPIO2 (Pins 35, 36): General Purpose Input/  
Output. The operation of these pins depends on the state  
of the MMB pin.  
–
–
V (Pin 26): Connect V to the most negative potential in  
When MMB is high, the pins behave as traditional GPIOs.  
By writing a “0” to a GPIO configuration register bit, the  
the series of cells.  
–
NC (Pin 27): Pin 27 is internally connected to V through  
–
open drain output is activated and the pin is pulled to V .  
10Ω. Pin 27 can be left unconnected or connect Pin 27  
to Pin 26 on the PCB.  
By writing a logic “1” to the configuration register bit, the  
corresponding GPIO pin is high impedance. An external  
VTEMP1, VTEMP2 (Pins 28, 29): Temperature Sensor  
resistor is needed to pull the pin up to V  
.
REG  
Inputs. The ADC will measure the voltage on V  
with  
TEMPx  
By reading the configuration register locations GPIO1  
and GPIO2, the state of the pins can be determined. For  
example, if a “0” is written to register bit GPIO1, a “0”  
is always read back because the output NMOSFET pulls  
–
respect to V and store the result in the TMP register. The  
ADC measurements are relative to the V  
pin voltage.  
REF  
Therefore a simple thermistor and resistor combination  
connected to the V pin can be used to monitor tem-  
–
REF  
Pin 35 to V . If a “1” is written to register bit GPIO1, the  
perature. The V  
ADC inputs.  
inputs can also be general purpose  
TEMP  
pin becomes high impedance. Either a “1” or a “0” is read  
back, depending on the voltage present at Pin 35. The  
Rev. B  
8
For more information www.analog.com  
LTC6802-2  
PIN FUNCTIONS  
GPIOs make it possible to turn on/off circuitry around  
the LTC6802-2, or read logic values from a circuit around  
the LTC6802-2.  
SCKI (Pin 41): Serial Clock Input. The SCKI pin inter-  
faces to any logic gate (TTL levels). See Serial Port in the  
Applications Information section.  
When the MMB pin is low, the GPIO pins and the WDTB  
pin are treated as inputs that set the number of cells to  
be monitored. See Monitor Mode in the Applications  
Information section.  
SDI (Pin 42): Serial Data Input. The SDI pin interfaces  
to any logic gate (TTL levels). See Serial Port in the  
Applications Information section.  
SDO (Pin 43): Serial Data Output. The SDO pin is an  
NMOS open drain output and requires an external resis-  
tor pull-up. See Serial Port in the Applications Information  
section.  
A0, A1, A2, A3 (Pins 37, 38, 39, 40): Address Inputs.  
–
These pins are tied to V  
or V . The state of the address  
REG  
pins (VREG = 1, V– = 0) determines the LTC6802-2 address.  
See LTC6802-2 Address Commands in the Serial Port  
subsection of the Applications Information section.  
CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI  
pin interfaces to any logic gate (TTL levels). See Serial  
Port in the Applications Information section.  
BLOCK DIAGRAM  
1
+
V
C12  
2
V
REG  
REGULATOR  
31  
34  
10k  
S12  
3
WDTB  
WATCHDOG  
TIMER  
C11  
4
A3  
A2  
40  
39  
38  
37  
44  
43  
42  
41  
A1  
10k  
S3  
21  
A0  
12  
RESULTS  
REGISTER  
∆∑ A/D CONVERTER  
MUX  
CSBI  
SDO  
SDI  
SCKI  
AND  
C2  
22  
COMMUNICATIONS  
10k  
S2  
23  
C1  
24  
REFERENCE  
GPIO2  
GPIO1  
MMB  
TOS  
36  
35  
33  
32  
10k  
S1  
25  
CONTROL  
–
V
26  
10Ω  
NC  
27  
EXTERNAL  
TEMP  
DIE  
TEMP  
V
V
V
REF  
TEMP1  
TEMP2  
28  
29  
30  
68022 BD  
Rev. B  
9
For more information www.analog.com  
LTC6802-2  
TIMING DIAGRAM  
Timing Diagram of the Serial Interface  
ꢈ
ꢈ
ꢈ
ꢉ
ꢃ
ꢇ
ꢈ
ꢈ
ꢁ
ꢈ
ꢅ
ꢂ
ꢒꢓꢘꢏ  
ꢒꢀꢏ  
ꢆ
ꢀꢁ  
ꢀꢂ  
ꢀꢃ  
ꢀꢄ  
ꢀꢅ  
ꢀꢇ  
ꢀꢁ  
ꢈ
ꢊ
ꢓꢒBꢏ  
ꢈ
ꢋ
ꢆ
ꢀꢇ  
ꢀꢁ  
ꢀꢂ  
ꢀꢃ  
ꢀꢄ  
ꢀꢅ  
ꢀꢇ  
ꢀꢁ  
ꢒꢀꢐ  
ꢌRꢍꢎꢏꢐꢑꢒ ꢓꢐꢔꢔꢕꢖꢀ  
ꢓꢑRRꢍꢖꢗ ꢓꢐꢔꢔꢕꢖꢀ  
ꢉꢋꢄꢂꢂ ꢗꢀ  
OPERATION  
THEORY OF OPERATION  
the LTC6802-2 makes no decisions about turning on/off  
the internal MOSFETs. This is completely controlled by  
the host processor. The host processor writes values to a  
configuration register inside the LTC6802-2 to control the  
switches. The watchdog timer on the LTC6802-2 can be  
used to turn off the discharge switches if communication  
with the host processor is interrupted.  
The LTC6802-2 is a data acquisition IC capable of mea-  
suring the voltage of 12 series connected battery cells.  
An input multiplexer connects the batteries to a 12-bit  
delta-sigma analog to digital converter (ADC). An internal  
5ppm voltage reference combined with the ADC give the  
LTC6802-2 its outstanding measurement accuracy. The  
inherent benefits of the delta-sigma ADC vs other types  
of ADCs (e.g. successive approximation) are explained  
in Advantages of Delta-Sigma ADCs in the Applications  
Information section.  
OPEN-CONNECTION DETECTION  
When a cell input (C pin) is open, it affects 2-cell mea-  
surements. Figure 2 shows an open connection to C3,  
in an application without external filtering between the C  
pins and the cells. During normal ADC conversions (that  
is, using the STCVAD command), the LTC6802 will give  
near zero readings for B3 and B4 when C3 is open. The  
zero reading for B3 occurs because during the measure-  
ment of B3, the ADC input resistance will pull C3 to the  
C2 potential. Similarly, during the measurement of B4, the  
ADC input resistance pulls C3 to the C4 potential.  
Communication between the LTC6802-2 and a host pro-  
cessor is handled by a SPI compatible serial interface.  
Multiple LTC6802-2s can be connected to a single serial  
interface. This is shown in Figure 1. The LTC6802-2s are  
isolated from one another using digital isolators. A unique  
addressing scheme allows all LTC6802-2s to connect to  
the same serial port of the host processor. Further expla-  
nation of the LTC6802-2 can be found in the Serial Port  
section of the data sheet.  
Figure 3 shows an open connection at the same point  
in the cell stack as Figure 2, but this time there is an  
external filter network still connected to C3. Depending  
on the value of the capacitor remaining on C3, a normal  
measurement of B3 and B4 may not give near zero read-  
ings, since the C3 pin is not truly open. In fact, with a  
large external capacitance on C3, the C3 voltage will be  
The LTC6802-2 also contains circuitry to balance cell volt-  
ages. Internal MOSFETs can be used to discharge cells.  
These internal MOSFETs can also be used to control exter-  
nal balancing circuits. Figure 1 illustrates cell balancing by  
internal discharge. Figure 4 shows the S pin controlling  
an external balancing circuit. It is important to note that  
Rev. B  
10  
For more information www.analog.com  
LTC6802-2  
OPERATION  
ꢈꢕ ꢠꢐ ꢊꢃ ꢈꢕ ꢠꢘ  
ꢂ
BꢋꢊꢊꢄRꢎ  
ꢏꢃꢍꢈꢊꢈꢀꢄ  
ꢐꢑꢒꢀ  
ꢂ
ꢂ
ꢂ
ꢀꢁ  
ꢀꢆ  
ꢀꢁ  
ꢀꢆ  
ꢌꢊꢕꢙꢗꢒꢁꢟꢁ  
ꢌꢊꢕꢙꢗꢒꢁꢟꢁ  
ꢈꢕ ꢠꢗ  
ꢅ
ꢃꢄꢁ  
ꢃꢄꢆ  
ꢃꢄꢁ  
ꢃꢄꢆ  
ꢈꢕ ꢠꢁ  
ꢅ
ꢀ
ꢕꢍBꢈ  
ꢍꢇꢃ  
ꢍꢇꢈ  
ꢍꢕꢛꢈ  
ꢋꢐ  
ꢋꢁ  
ꢋꢆ  
ꢋꢒ  
ꢀ
ꢕꢍBꢈ  
ꢕꢆꢁ  
ꢍꢆꢁ  
ꢕꢆꢆ  
ꢍꢆꢆ  
ꢕꢆꢒ  
ꢍꢆꢒ  
ꢕꢖ  
ꢕꢆꢁ  
ꢍꢆꢁ  
ꢕꢆꢆ  
ꢍꢆꢆ  
ꢕꢆꢒ  
ꢍꢆꢒ  
ꢕꢖ  
ꢍꢖ  
ꢕꢗ  
ꢍꢗ  
ꢕꢘ  
ꢍꢘ  
ꢕꢙ  
ꢍꢙ  
ꢕꢑ  
ꢍꢑ  
ꢕꢚ  
ꢍꢚ  
ꢕꢐ  
ꢍꢇꢃ  
ꢍꢇꢈ  
ꢍꢕꢛꢈ  
ꢋꢐ  
ꢋꢁ  
ꢋꢆ  
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢂ
ꢂ
ꢂ
ꢂ
ꢀꢁ  
ꢀꢆ  
ꢀꢁ  
ꢀꢆ  
ꢋꢇꢇRꢄꢍꢍ ꢆ  
ꢋꢇꢇRꢄꢍꢍ ꢆꢑ  
ꢅ
ꢅ
ꢅ
ꢅ
ꢀꢁ  
ꢀꢆ  
ꢐꢀ  
ꢀꢁ  
ꢀꢆ  
ꢐꢀ  
ꢇꢈꢉꢈꢊꢋꢌ  
ꢈꢍꢃꢌꢋꢊꢃR  
ꢇꢈꢉꢈꢊꢋꢌ  
ꢈꢍꢃꢌꢋꢊꢃR  
ꢋꢒ  
ꢍꢖ  
ꢕꢗ  
ꢍꢗ  
ꢕꢘ  
ꢍꢘ  
ꢕꢙ  
ꢍꢙ  
ꢕꢑ  
ꢍꢑ  
ꢕꢚ  
ꢍꢚ  
ꢕꢐ  
ꢍꢐ  
ꢕꢁ  
ꢉꢏꢈꢃꢁ  
ꢉꢏꢈꢃꢆ  
ꢜꢇꢊB  
ꢓꢓB  
ꢊꢃꢍ  
ꢉꢏꢈꢃꢁ  
ꢉꢏꢈꢃꢆ  
ꢜꢇꢊB  
ꢓꢓB  
ꢊꢃꢍ  
ꢀ
ꢀ
Rꢄꢉ  
ꢀ
Rꢄꢝ  
Rꢄꢉ  
ꢀ
Rꢄꢝ  
ꢀ
ꢀ
ꢀ
ꢊꢄꢓꢏꢁ  
ꢊꢄꢓꢏꢁ  
ꢀ
ꢊꢄꢓꢏꢆ  
ꢞꢕ  
ꢀ
ꢊꢄꢓꢏꢆ  
ꢞꢕ  
ꢂ
ꢂ
ꢀ
ꢍꢆ  
ꢕꢆ  
ꢍꢁ  
ꢍꢆ  
ꢕꢆ  
ꢍꢁ  
ꢍꢐ  
ꢕꢁ  
ꢅ
ꢅ
ꢅ
ꢅ
ꢐꢀ  
ꢂ
ꢀꢁ  
ꢂ
ꢀꢆ  
ꢌꢊꢕꢙꢗꢒꢁꢟꢁ  
ꢈꢕ ꢠꢆ  
ꢃꢄꢁ  
ꢃꢄꢆ  
ꢓꢏꢔ  
ꢅ
ꢓꢃꢇꢔꢌꢄ  
ꢈꢃ  
ꢀ
ꢕꢍBꢈ  
ꢓꢈꢍꢃ  
ꢕꢍ  
ꢓꢃꢍꢈ  
ꢕꢌꢛ  
ꢕꢆꢁ  
ꢍꢆꢁ  
ꢕꢆꢆ  
ꢍꢆꢆ  
ꢕꢆꢒ  
ꢍꢆꢒ  
ꢕꢖ  
ꢍꢇꢃ  
ꢍꢇꢈ  
ꢍꢕꢛꢈ  
ꢋꢐ  
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
ꢂ
ꢂ
ꢀꢁ  
ꢀꢆ  
ꢋꢇꢇRꢄꢍꢍ ꢒ  
ꢅ
ꢅ
ꢀꢁ  
ꢀꢆ  
ꢐꢀ  
ꢋꢁ  
ꢋꢆ  
ꢋꢒ  
ꢇꢈꢉꢈꢊꢋꢌ  
ꢈꢍꢃꢌꢋꢊꢃR  
ꢍꢖ  
ꢕꢗ  
ꢍꢗ  
ꢕꢘ  
ꢍꢘ  
ꢕꢙ  
ꢍꢙ  
ꢕꢑ  
ꢍꢑ  
ꢕꢚ  
ꢍꢚ  
ꢕꢐ  
ꢍꢐ  
ꢕꢁ  
ꢉꢏꢈꢃꢁ  
ꢉꢏꢈꢃꢆ  
ꢜꢇꢊB  
ꢓꢓB  
ꢊꢃꢍ  
ꢀ
Rꢄꢉ  
ꢀ
Rꢄꢝ  
ꢀ
ꢀ
ꢊꢄꢓꢏꢁ  
ꢊꢄꢓꢏꢆ  
ꢞꢕ  
ꢂ
ꢀ
ꢍꢆ  
ꢕꢆ  
ꢍꢁ  
ꢅ
ꢅ
ꢙꢗꢒꢁꢁ ꢝꢒꢆ  
Figure 1. 96-Cell Battery Stack, Isolated Interface. In this Diagram the Battery Negative is Isolated from Module Ground.  
Opto-Couplers or Digital Isolators Allow Each IC to be Addressed Individually. This is a Simplified Schematic Showing  
the Basic Multi-IC Architecture  
charged midway between C2 and C4 after several cycles  
of measuring cells B3 and B4. Thus the measurements  
for B3 and B4 may indicate a valid cell voltage when in  
fact the exact state of B3 and B4 is unknown.  
turned on during all cell conversions. Referring again to  
Figure 3, with the STOWAD command, the C3 pin will be  
pulled down by the 100µA current source during the B3  
cell measurement AND during the B4 cell measurement.  
This will tend to decrease the B3 measurement result and  
increase the B4 measurement result relative to the normal  
STCVAD command. The biggest change is observed in the  
Rev. B  
To reliably detect an open connection, the command  
STOWAD is provided. With this command, two 100µA  
current sources are connected to the ADC inputs and  
11  
For more information www.analog.com  
LTC6802-2  
OPERATION  
ꢐꢑꢃꢍꢎꢊꢆꢒꢆ  
4. Issue a RDCV command and store all cell measure-  
ments into array CELLB(n).  
ꢃꢄ  
5. For each value of n from 1 to 11:  
Bꢄ ꢓ  
ꢃꢅ  
If CELLB(n + 1) – CELLA(n + 1) ≥ +200mV,  
then Cn is open, otherwise it is not open.  
Bꢅ ꢓ  
ꢀꢁꢂ  
ꢃꢆ  
ꢓ
ꢃꢇ  
The 200mV threshold is chosen to provide tolerance  
for errors in the measurement with the 100µA current  
source connected. Even without an open connection there  
is always some difference between a cell measured with  
and without the 100µA current source because of the IR  
drop across the finite resistance of the MUX switches. On  
the other hand, with capacitors larger then 0.1µF remain-  
ing on an otherwise open C pin, the 100µA current source  
may not be enough to move the open C pin 200mV with  
a single STOWAD command. If the STOWAD command  
is repeated several times, the large external capacitor will  
discharge enough to create a 200mV change in cell read-  
ings. To detect an open connection with larger then 0.1µF  
capacitance still on the pin, one must repeat step 3 a  
number of times before proceeding to step 4.  
ꢓ
ꢈꢉ  
ꢇꢊꢊꢋꢌ  
ꢍꢎꢊꢆꢆ ꢏꢊꢆ  
Figure 2. Open Connection  
ꢐꢑꢃꢎꢏꢋꢇꢒꢇ  
ꢓ
ꢓ
ꢃꢄ  
ꢃꢅ  
Bꢄ  
ꢃ
ꢃ
ꢆꢄ  
Bꢅ ꢓ  
ꢓ
ꢀꢁꢂ  
ꢃꢇ  
ꢆꢅ  
ꢃꢈ  
ꢉꢊ  
ꢓ
The algorithm above determines if the Cn pin is open  
based on measurements of the n + 1 cell. For example,  
in a 12-cell system, the algorithm finds opens on Pins C1  
through C11 by looking at the measurements of cells B2  
through B12. Therefore the algorithm can not be used to  
determine if the topmost C pin is open. Fortunately, an  
open wire from the battery to the top C pin usually means  
ꢈꢋꢋꢌꢍ  
ꢎꢏꢋꢇꢇ ꢆꢋꢅ  
Figure 3. Open Connection with RC Filtering  
+
B4 measurement when C3 is open. So, the best method to  
detect an open wire at input C3 is to look for an increase  
in the measurement of the cell connected between inputs  
C3 and C4 (cell B4).  
the V pin is also floating. When this happens, the read-  
ings for the top battery cell will always be 0V, indicating  
+
a failure. If the top C pin is open yet V is still connected,  
then the best way to detect an open connection to the top  
C pin is by comparing the sum of all cell measurements  
using the STCVAD command to an auxiliary measurement  
of the sum of all the cells, using a method similar to that  
shown in Figure 15. A significantly lower result for the  
calculated sum of all 12 cells suggests an open connec-  
tion to the top C pin, provided it was already determined  
that no other C pin is open.  
Thus the following algorithm can be used to detect an  
open connection to cell pin Cn:  
1. Issue a STCVAD command (ADC convert without  
100µA current sources).  
2. Issue a RDCV command and store all cell measure-  
ments into array CELLA(n).  
3. Issue a STOWAD command (ADC convert with 100µA  
current sources).  
Rev. B  
12  
For more information www.analog.com  
LTC6802-2  
OPERATION  
DISCHARGING DURING CELL MEASUREMENTS  
Cn  
The primary cell voltage A/D measurement commands  
(STCVAD and STOWAD) automatically turn off a cell’s  
discharge switch while its voltage is being measured.  
The discharge switches for the cell above and the cell  
below will also be turned off during the measurement.  
For example, discharge switches S4, S5, and S6 will be  
disabled while cell 5 is being measured.  
SI2351DS  
MM3Z12VT1  
3.3k  
+
15Ω  
1W  
VISHAY CRCW2512 SERIES  
Sn  
Cn – 1  
68022 F04  
Figure 4. External Discharge FET Connection (One Cell Shown)  
In some systems it may be desirable to allow discharg-  
ing to continue during cell voltage measurements. The  
cell voltage A/D conversion commands STCVDC and  
STOWDC allow any enabled discharge switches to remain  
on during cell voltage measurements. This feature allows  
the system to perform a self test to verify the discharge  
functionality and multiplexer operation.  
POWER DISSIPATION AND THERMAL SHUTDOWN  
The MOSFETs connected to the Pins S1 through S12  
can be used to discharge battery cells. An external resis-  
tor should be used to limit the power dissipated by  
the MOSFETs. The maximum power dissipation in the  
MOSFETs is limited by the amount of heat that can be  
tolerated by the LTC6802-2. Excessive heat results in  
elevated die temperatures. The electrical characteristics  
are guaranteed for die temperatures up to 85°C. Little  
or no degradation will be observed in the measurement  
accuracy for die temperatures up to 105°C. Damage may  
occur near 150°C, therefore the recommended maximum  
die temperature is 125°C.  
All discharge switches are automatically disabled during  
OV and UV comparison measurements.  
A/D CONVERTER DIGITAL SELF TEST  
Two self-test commands can be used to verify the func-  
tionality of the digital portions of the ADC. The self tests  
also verify the cell voltage registers and cell temperature  
registers. During these self tests a test signal is applied  
to the ADC. If the circuitry is working properly the cell  
voltage or cell temperature registers will contain identi-  
cal codes. For self test 1 the registers will contain 0x555.  
For self test 2, the registers will contain 0xAAA. The time  
required for the self-test function is the same as required  
to measure all cell voltages or all temperature sensors.  
Perform the self-test function with CDC[2:0] set to 1 in  
the configuration register.  
To protect the LTC6802-2 from damage due to overheat-  
ing, a thermal shutdown circuit is included. Overheating  
of the device can occur when dissipating significant power  
in the cell discharge switches. The problem is exacerbated  
+
–
when operating with a large voltage between V and V or  
when the thermal conductivity of the system is poor.  
If the temperature detected on the device goes above  
approximately 145°C, the configuration registers will be  
reset to default states, turning off all discharge switches  
and disabling A/D conversions. When a thermal shutdown  
has occurred, the THSD bit in the temperature register  
group will go high. The bit is cleared by performing a read  
of the temperature registers (RDTMP command).  
USING THE S PINS AS DIGITAL OUTPUTS OR  
GATE DRIVERS  
The S outputs include an internal 10k pull-up resistor.  
Therefore the S pins will behave as a digital output when  
loaded with a high impedance, e.g., the gate of an external  
MOSFET. For applications requiring high battery discharge  
currents, connect a discrete PMOS switch device and suit-  
able discharge resistor to the cell, and the gate terminal  
to the S output pin, as illustrated in Figure 4.  
Since thermal shutdown interrupts normal operation, the  
internal temperature monitor should be used to determine  
when the device temperature is approaching unacceptable  
levels.  
Rev. B  
13  
For more information www.analog.com  
LTC6802-2  
APPLICATIONS INFORMATION  
USING THE LTC6802-2 WITH LESS THAN 12 CELLS  
USING THE GENERAL PURPOSE INPUTS/OUTPUTS  
(GPIO1, GPIO2)  
The LTC6802-2 can typically be used with as few as 4  
cells. The minimum number of cells is governed by the  
supply voltage requirements of the LTC6802-2. The sum  
of the cell voltages must be 10V to guarantee that all  
electrical specifications are met.  
The LTC6802-2 has two general purpose digital inputs/  
outputs. By writing a GPIO configuration register bit to  
a logic low, the open-drain output can be activated. The  
GPIOs give the user the ability to turn on/off circuitry  
around the LTC6802-2. One example might be a circuit  
to verify the operation of the system.  
Figure 5 shows an example of the LTC6802-2 when used  
to monitor 7 cells. The lowest C inputs connect to the 7  
cells and the upper C inputs connect to V+. Other configu-  
rations, e.g., 9 cells, would be configured in the same way:  
the lowest C inputs connected to the battery cells and the  
When a GPIO configuration bit is written to a logic high,  
the corresponding GPIO pin may be used as an input.  
The read back value of that bit will be the logic level that  
appears at the GPIO pin.  
+
unused C inputs connected to V . The unused inputs will  
result in a reading of 0V for those channels.  
When the MMB pin is low, the GPIO pins and the WDTB  
pin are treated as inputs that set the number of cells to  
be monitored. See the Monitor Mode section.  
The ADC can also be commanded to measure a stack of  
cells by making 10 or 12 measurements, depending on  
the state of the CELL10 bit in the control register. Data  
from all 10 or 12 measurements must be downloaded  
when reading the conversion results. The ADC can be  
commanded to measure any individual cell voltage.  
WATCHDOG TIMER CIRCUIT  
The LTC6802-2 includes a watchdog timer circuit. If no  
activity is detected on the SCKI pin for 2.5 seconds, the  
WDTB open-drain output is asserted low. The WDTB pin  
remains low until an edge is detected on the SCKI pin.  
NEXT HIGHER GROUP OF 7 CELLS  
LTC6802-2  
+
V
C12  
S12  
C11  
S11  
C10  
S10  
C9  
S9  
C8  
S8  
C7  
When the watchdog timer circuit times out, the configura-  
tion bits are reset to their default (power-up) state.  
In the power-up state, the S outputs are off. Therefore,  
the watchdog timer provides a means to turn off cell dis-  
charging should communications to the MPU be inter  
-
rupted. The IC is in the minimum power standby mode  
after a time out. Note that externally pulling the WDTB pin  
low will not reset the configuration bits.  
+
S7  
C6  
S6  
C5  
S5  
The watchdog timer operation is disabled when MMB  
is low.  
+
+
When reading the configuration register, byte CFG0 bit 7  
will reflect the state of the WDTB pin.  
C4  
S4  
C3  
S3  
C2  
S2  
C1  
+
+
REVISION CODE  
+
The temperature register group contains a 3-bit revision  
code. If software detection of device revision is neces-  
sary, then contact the factory for details. Otherwise, the  
code can be ignored. In all cases, however, the values of  
all bits must be used when calculating the packet error  
code (PEC) CRC byte on data reads.  
+
S1  
−
V
68022 F05  
NEXT LOWER GROUP OF 7 CELLS  
Figure 5. Monitoring 7 Cells with the LTC6802-2  
Rev. B  
14  
For more information www.analog.com  
LTC6802-2  
APPLICATIONS INFORMATION  
MODES OF OPERATION  
and OV flag status for each cell can be determined using  
the Read Flag Register Group.  
The LTC6802-2 has three modes of operation: standby,  
measure and monitor. Standby mode is a power saving  
state where all circuits except the serial interface are  
turned off. In measure mode, the LTC6802-2 is used to  
measure cell voltages and store the results in memory.  
Measure mode will also monitor each cell voltage for  
overvoltage (OV) and undervoltage (UV) conditions. In  
monitor mode, the device will only monitor cells for UV  
and OV conditions. A signal is output on the SDO pin to  
indicate the UV/OV status. The serial interface is disabled.  
If fewer than 12 cells are connected to the LTC6802-2  
then it is necessary to mask the unused input channels.  
The MCxI bits in the configuration registers are used to  
mask channels. If the CELL10 bit is high, then the inputs  
for cells 11 and 12 are automatically masked.  
The LTC6802-2 can monitor UV and OV conditions con-  
tinuously. Alternatively, the duty cycle of the UV and OV  
comparisons can be reduced or turned off to lower the  
overall power consumption. The CDC bits are used to  
control the duty cycle.  
Standby Mode  
To initiate cell voltage measurements while in measure  
mode, a Start A/D Conversion and Poll Status command  
must be sent. After the command has been sent, the  
LTC6802-2 will send the A/D converter status using either  
the toggle polling or the level polling method, as described  
in the Serial Port section. If the CELL10 bit is high, then  
only the bottom 10 cell voltages will be measured, thereby  
reducing power consumption and measurement time. By  
default the CELL10 bit is low, enabling measurement of all  
12 cell voltages. During cell voltage measurement com-  
mands, UV and OV flag conditions, reflected in the flag  
register group, are also updated. When the measurements  
are complete, the part will go back to monitoring UV and  
OV conditions at the rate designated by the CDC bits.  
The LTC6802-2 defaults (powers up) to standby mode.  
Standby mode is the lowest possible supply current state.  
All circuits are turned off except the serial interface and  
the voltage regulator. The LTC6802-2 can be programmed  
for standby mode by setting configuration bits CDC[2:0]  
to 0. If the part is put into standby mode while ADC mea-  
surements are in progress, the measurements will be  
interrupted and the cell voltage registers will be in an  
indeterminate state. To exit standby mode, the CDC bits  
must be written to a value other than 0.  
Measure Mode  
The LTC6802-2 is in measure mode when the CDC bits  
are programmed with a value from 1 to 7. The IC moni-  
tors each cell voltage and produces an interrupt signal  
on the SDO pin indicating all cell voltages are within the  
UV and OV limits. There are two methods for indicating  
the UV/OV interrupt status: toggle polling (using a 1kHz  
output signal) and level polling (using a high or low output  
signal). The polling methods are described in the Serial  
Port section.  
Monitor Mode  
The LTC6802-2 can be used as a simple monitoring cir-  
cuit with no serial interface by pulling the MMB pin low.  
When in this mode, the interrupt status is indicated on the  
SDO pin using the toggle polling mode described in the  
Serial Port section. Unlike serial port polling commands,  
however, the toggling is independent of the state of the  
CSBI pin.  
The UV/OV limits are set by the VUV and VOV values in  
the configuration registers. When a cell voltage exceeds  
the UV/OV limits a bit is set in the flag register. The UV  
When the MMB pin is low, all the device configuration  
values are reset to the default states shown in Table 15  
Memory Bit Descriptions. When MMB is held low the VUV,  
VOV, and CDC register values are ignored. Instead VUV  
Rev. B  
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and VOV use factory-programmed setings. CDC is set  
to state 5. The number of cells to be monitored is set by  
the logic levels on the WDTB and GPIO pins, as shown  
in Table 1.  
Physical Layer  
On the LTC6802-2, four pins comprise the serial inter-  
face: CSBI, SCKI, SDI and SDO. The SDO and SDI may  
be tied together, if desired, to form a single, bidirectional  
port. Four address pins (A0 to A3) set the part address  
for address commands. The TOS pin designates the top  
device (logic high) for polling commands. All interface  
pins are voltage mode, with voltage levels sensed with  
Table 1. Monitor Mode Cell Selection  
WDTB  
GPIO2  
GPIO1  
CELL INPUTS MONITORED  
Cells 1 to 5  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Cells 1 to 6  
–
respect to the V supply. See Figure 1.  
Cells 1 to 7  
Cells 1 to 8  
Data Link Layer  
Cells 1 to 9  
Clock Phase And Polarity: The LTC6802-2 SPI compat-  
ible interface is configured to operate in a system using  
CPHA = 1 and CPOL = 1. Consequently, data on SDI must  
be stable during the rising edge of SCKI.  
Cells 1 to 10  
Cells 1 to 11  
Cells 1 to 12  
Data Transfers: Every byte consists of 8 bits. Bytes are  
transferred with the most significant bit (MSB) first. On a  
write, the data value on SDI is latched into the device on  
the rising edge of SCKI (Figure 6). Similarly, on a read,  
the data value output on SDO is valid during the rising  
edge of SCKI and transitions on the falling edge of SCKI  
(Figure 7).  
If MMB is low then brought high, all device configuration  
values are reset to the default states including the VUV,  
VOV, and CDC configuration bits.  
SERIAL PORT  
Overview  
CSBI must remain low for the entire duration of a com-  
mand sequence, including between a command byte and  
subsequent data. On a write command, data is latched in  
on the rising edge of CSBI.  
The LTC6802-2 has an SPI bus compatible serial port.  
Devices can be connected in parallel, using digital isola-  
tors. Multiple devices are uniquely identified by a part  
address determined by the A0 to A3 pins.  
After a polling command has been entered, the SDO out-  
put will immediately be driven by the polling state, with  
ꢀꢁBꢂ  
ꢁꢀꢃꢂ  
ꢊꢁB ꢆꢄꢋꢈꢋꢇ  
ꢅꢁB ꢆꢀꢅꢄꢇ  
Bꢂꢈꢉ ꢆꢀꢅꢄꢇ  
ꢊꢁB ꢆꢀꢅꢄꢇ  
ꢅꢁB ꢆꢄꢋꢈꢋꢇ  
ꢁꢄꢂ  
ꢉꢌꢍꢎꢎ ꢏꢍꢉ  
Figure 6. Transmission Format (Write)  
Rev. B  
16  
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APPLICATIONS INFORMATION  
ꢀꢁBꢂ  
ꢁꢀꢃꢂ  
ꢁꢄꢂ  
ꢆꢁB ꢇꢀꢆꢄꢈ  
Bꢂꢉꢊ ꢇꢀꢆꢄꢈ  
ꢋꢁB ꢇꢀꢆꢄꢈ  
ꢁꢄꢅ  
ꢋꢁB ꢇꢄꢌꢉꢌꢈ  
ꢆꢁB ꢇꢄꢌꢉꢌꢈ  
ꢊꢍꢎꢏꢏ ꢐꢎꢑ  
Figure 7. Transmission Format (Read)  
ꢀꢁBꢂ  
ꢁꢀꢃꢂ  
ꢁꢄꢂ  
ꢋꢁB ꢌꢀꢋꢄꢍ  
Bꢂꢈꢎ ꢌꢀꢋꢄꢍ  
ꢇꢁB ꢌꢀꢋꢄꢍ  
ꢁꢄꢅ  
ꢆꢅꢇꢇ ꢁꢈꢉꢈꢊ  
ꢎꢏꢐꢑꢑ ꢒꢐꢏ  
Figure 8. Transmission Format (Poll)  
the SCKI input ignored (Figure 8). See the Toggle Polling  
and Level Polling sections.  
data. Broadcast read commands should not be used in  
the parallel configuration.  
Network Layer  
Address Commands: An address command is one in  
which only the addressed device on the bus responds. The  
first byte of an address command consists of 4 bits with a  
value of 1000 and 4 address bits. The second byte is the  
command byte. See the Bus Protocols and Commands  
section.  
Broadcast Commands: A broadcast command is one to  
which all devices on the bus will respond, regardless of  
device address. See the Bus Protocols and Commands  
sections.  
With broadcast commands all devices can be sent com-  
mands simultaneously. This is useful for A/D conversion  
and polling commands. It can also be used with write  
commands when all parts are being written with the same  
PEC Byte: The packet error code (PEC) byte is a CRC  
value calculated for all of the bits in a register group in  
Rev. B  
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the order they are read, using the following characteristic  
polynomial:  
A/D conversion and will be high when no device is busy.  
Similarly, when polling for interrupt status, the output will  
be low when any device has an interrupt condition and will  
be high when none has an interrupt condition.  
8
2
x + x + x + 1  
On a read command, after sending the last byte of a reg-  
ister group, the device will shift out the calculated PEC,  
MSB first.  
Level polling—Address Polling: The addressed device  
drives the SDO line based on its state alone—pulled low  
for busy/in interrupt, released for not busy/not in interrupt.  
Toggle Polling: Toggle polling allows a robust determina-  
tion both of device states and of the integrity of the con-  
nections between the devices in a stack. Toggle polling  
is enabled when the LVLPL bit is low. After entering a  
polling command, the data out line will be driven by the  
slave devices based on their status. When polling for the  
A/D converter status, data out will be low when any device  
is busy performing an A/D conversion and will toggle at  
1kHz when no device is busy. Similarly, when polling for  
interrupt status, the output will be low when any device  
has an interrupt condition and will toggle at 1kHz when  
none has an interrupt condition.  
Level polling—Parallel Broadcast Polling: No part address  
is sent, so all devices respond simultaneously. If a device  
is busy/in interrupt, it will pull SDO low. If a device is not  
busy/not in interrupt, then it will release the SDO line. If  
any device is busy or in interrupt the SDO signal will be  
low. If all devices are not busy/not in interrupt, the SDO  
signal will be high.  
The master controller pulls CSBI high to exit polling.  
Polling Methods: For A/D conversions, three methods can  
be used to determine A/D completion. First, a controller  
can start an A/D conversion and wait for the specified  
conversion time to pass before reading the results. The  
second method is to hold CSBI low after an A/D start com-  
mand has been sent. The A/D conversion status will be  
output on SDO. A problem with the second method is that  
the controller is not free to do other serial communication  
while waiting for A/D conversions to complete. The third  
method overcomes this limitation. The controller can send  
an A/D start command, perform other tasks, and then  
send a Poll A/D Converter Status (PLADC) command to  
determine the status of the A/D conversions.  
Toggle Polling—Address Polling: The addressed device  
drives the SDO line based on its state alone—low for  
busy/in interrupt, toggling at 1kHz for not busy/not in  
interrupt.  
Toggle Polling—Parallel Broadcast Polling: No part  
address is sent, so all devices respond simultaneously.  
If a device is busy/in interrupt, it will pull SDO low. If a  
device is not busy/not in interrupt, then it will release the  
SDO line (TOS = 0) or attempt to toggle the SDO line at  
1kHz (TOS =1).  
For OV/UV interrupt status, the poll interrupt status  
(PLINT) command can be used to quickly determine  
whether any cell in a stack is in an overvoltage or under-  
voltage condition.  
The master controller pulls CSBI high to exit polling.  
Level polling: Level polling is enabled when the LVLPL  
bit is high. After entering a polling command, the data  
out line will be driven by the slave devices based on their  
status. When polling for the A/D converter status, data  
out will be low when any device is busy performing an  
Bus Protocols  
There are 6 different protocol formats, depicted in Table 3  
through Table 8. Table 2 is the key for reading the protocol  
diagrams.  
Rev. B  
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Table 2. Protocol Key  
PEC  
Packet error code (CRC-8)  
Master-to-slave  
N
Number of bits  
Slave-to-master  
…
Continuation of protocol  
Complete byte of data  
Table 3. Broadcast Poll Command  
8
Command  
Poll Data  
Table 4. Broadcast Read  
8
8
8
8
Command  
Data Byte Low  
…
…
Data Byte High  
PEC  
Table 5. Broadcast Write  
8
8
8
Command  
Data Byte Low  
Data Byte High  
Table 6. Address Poll Command  
4
4
8
1000  
Address  
Command  
Poll Data  
Table 7. Address Read  
4
4
8
8
8
8
1000  
Address  
Command  
Data Byte Low  
…
…
Data Byte High  
PEC  
Table 8. Address Write  
4
4
8
8
8
1000  
Address  
Command  
Data Byte Low  
Data Byte High  
Rev. B  
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Commands  
Table 9. Command Codes  
Write Configuration Register Group  
Read Configuration Register Group  
Read Cell Voltage Register Group  
Read Flag Register Group  
WRCFG  
RDCFG  
RDCV  
0x01  
0x02  
0x04  
0x06  
0x08  
RDFLG  
RDTMP  
STCVAD  
Read Temperature Register Group  
Start Cell Voltage A/D Conversions and Poll Status  
0x10 (all cell voltage inputs)  
0x11 (cell 1 only)  
0x12 (cell 2 only)  
…
0x1A (cell 10 only)  
0x1B (cell 11 only, if CELL10 bit=0)  
0x1C (cell 12 only, if CELL10 bit=0)  
0x1D (unused)  
0x1E (cell self test 1; all CV=0x555)  
0x1F (cell self test 2; all CV=0xAAA)  
Start Open-Wire A/D Conversions and Poll Status  
STOWAD  
0x20 (all cell voltage inputs)  
0x21 (cell 1 only)  
0x22 (cell 2 only)  
…
0x2A (cell 10 only)  
0x2B (cell 11 only, if CELL10 bit=0)  
0x2C (cell 12 only, if CELL10 bit=0)  
0x2D (unused)  
0x2E (cell self test 1; all CV=0x555)  
0x2F (cell self test 2; all CV=0xAAA)  
Start Temperature A/D Conversions and Poll Status  
STTMPAD  
0x30 (all temperature inputs)  
0x31 (external temp 1 only)  
0x32 (external temp 2 only)  
0x33 (internal temp only)  
0x34—0x3D (unused)  
0x3E (temp self test 1; all TMP=0x555)  
0x3F (temp self test 2; all TMP=0xAAA)  
Poll A/D Converter Status  
Poll Interrupt Status  
PLADC  
PLINT  
0x40  
0x50  
Start Cell Voltage A/D Conversions and Poll Status, with  
Discharge Permitted  
STCVDC  
0x60 (all cell voltage inputs)  
0x61 (cell 1 only)  
0x62 (cell 2 only)  
…
0x6A (cell 10 only)  
0x6B (cell 11 only, if CELL10 bit=0)  
0x6C (cell 12 only, if CELL10 bit=0)  
0x6D (unused)  
0x6E (cell self test 1; all CV=0x555)  
0x6F (cell self test 2; all CV=0xAAA)  
Start Open-Wire A/D Conversions and Poll Status, with  
Discharge Permitted  
STOWDC  
0x70 (all cell voltage inputs)  
0x71 (cell 1 only)  
0x72 (cell 2 only)  
…
0x7A (cell 10 only)  
0x7B (cell 11 only, if CELL10 bit=0)  
0x7C (cell 12 only, if CELL10 bit=0)  
0x7D (unused)  
0x7E (cell self test 1; all CV=0x555)  
0x7F (cell self test 2; all CV=0xAAA)  
Rev. B  
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Memory Map  
Table 10 through Table 15 show the memory map for the  
LTC6802-2. Table 15 gives bit descriptions.  
Table 10. Configuration (CFG) Register Group  
REGISTER  
CFGR0  
CFGR1  
CFGR2  
CFGR3  
CFGR4  
CFGR5  
RD/WR  
RD/WR  
RD/WR  
RD/WR  
RD/WR  
RD/WR  
RD/WR  
BIT 7  
WDT  
BIT 6  
GPIO2  
DCC7  
BIT 5  
GPIO1  
DCC6  
BIT 4  
LVLPL  
DCC5  
BIT 3  
CELL10  
DCC4  
BIT 2  
CDC[2]  
DCC3  
BIT 1  
CDC[1]  
DCC2  
BIT 0  
CDC[0]  
DCC1  
DCC8  
MC4I  
MC3I  
MC2I  
MC1I  
DCC12  
MC8I  
DCC11  
MC7I  
DCC10  
MC6I  
DCC9  
MC12I  
VUV[7]  
VOV[7]  
MC11I  
VUV[6]  
VOV[6]  
MC10I  
VUV[5]  
VOV[5]  
MC9I  
MC5I  
VUV[4]  
VOV[4]  
VUV[3]  
VOV[3]  
VUV[2]  
VOV[2]  
VUV[1]  
VOV[1]  
VUV[0]  
VOV[0]  
Table 11. Cell Voltage (CV) Register Group  
REGISTER  
CVR00  
CVR01  
CVR02  
CVR03  
CVR04  
CVR05  
CVR06  
CVR07  
CVR08  
CVR09  
CVR10  
CVR11  
CVR12  
CVR13  
CVR14  
CVR15*  
CVR16*  
CVR17*  
RD/WR  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
RD  
BIT 7  
C1V[7]  
BIT 6  
C1V[6]  
BIT 5  
C1V[5]  
C2V[1]  
C2V[9]  
C3V[5]  
C4V[1]  
C4V[9]  
C5V[5]  
C6V[1]  
C6V[9]  
C7V[5]  
C8V[1]  
C8V[9]  
C9V[5]  
C10V[1]  
C10V[9]  
C11V[5]  
C12V[1]  
C12V[9]  
BIT 4  
C1V[4]  
C2V[0]  
C2V[8]  
C3V[4]  
C4V[0]  
C4V[8]  
C5V[4]  
C6V[0]  
C6V[8]  
C7V[4]  
C8V[0]  
C8V[8]  
C9V[4]  
C10V[0]  
C10V[8]  
C11V[4]  
C12V[0]  
C12V[8]  
BIT 3  
C1V[3]  
C1V[11]  
C2V[7]  
C3V[3]  
C3V[11]  
C4V[7]  
C5V[3]  
C5V[11]  
C6V[7]  
C7V[3]  
C7V[11]  
C8V[7]  
C9V[3]  
C9V[11]  
C10V[7]  
C11V[3]  
C11V[11]  
C12V[7]  
BIT 2  
C1V[2]  
C1V[10]  
C2V[6]  
C3V[2]  
C3V[10]  
C4V[6]  
C5V[2]  
C5V[10]  
C6V[6]  
C7V[2]  
C7V[10]  
C8V[6]  
C9V[2]  
C9V[10]  
C10V[6]  
C11V[2]  
C11V[10]  
C12V[6]  
BIT 1  
C1V[1]  
C1V[9]  
C2V[5]  
C3V[1]  
C3V[9]  
C4V[5]  
C5V[1]  
C5V[9]  
C6V[5]  
C7V[1]  
C7V[9]  
C8V[5]  
C9V[1]  
C9V[9]  
C10V[5]  
C11V[1]  
C11V[9]  
C12V[5]  
BIT 0  
C1V[0]  
C1V[8]  
C2V[4]  
C3V[0]  
C3V[8]  
C4V[4]  
C5V[0]  
C5V[8]  
C6V[4]  
C7V[0]  
C7V[8]  
C8V[4]  
C9V[0]  
C9V[8]  
C10V[4]  
C11V[0]  
C11V[8]  
C12V[4]  
C2V[3]  
C2V[2]  
C2V[11]  
C3V[7]  
C2V[10]  
C3V[6]  
C4V[3]  
C4V[2]  
C4V[11]  
C5V[7]  
C4V[10]  
C5V[6]  
C6V[3]  
C6V[2]  
C6V[11]  
C7V[7]  
C6V[10]  
C7V[6]  
C8V[3]  
C8V[2]  
C8V[11]  
C9V[7]  
C8V[10]  
C9V[6]  
C10V[3]  
C10V[11]  
C11V[7]  
C12V[3]  
C12V[11]  
C10V[2]  
C10V[10]  
C11V[6]  
C12V[2]  
C12V[10]  
*Registers CVR15, CVR16, and CVR17 can only be read if the CELL10 bit in register CFGR0 is low.  
Rev. B  
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Table 12. Flag (FLG) Register Group  
REGISTER  
FLGR0  
RD/WR  
RD  
BIT 7  
C4OV  
BIT 6  
C4UV  
BIT 5  
C3OV  
BIT 4  
C3UV  
BIT 3  
C2OV  
C6OV  
C10OV  
BIT 2  
C2UV  
C6UV  
C10UV  
BIT 1  
C1OV  
C5OV  
C9OV  
BIT 0  
C1UV  
C5UV  
C9UV  
FLGR1  
RD  
C8OV  
C8UV  
C7OV  
C7UV  
FLGR2  
RD  
C12OV*  
C12UV*  
C11OV*  
C11UV*  
*Bits C11UV, C12UV, C11OV, and C12OV are always low if the CELL10 bit in register CFGR0 is high.  
Table 13. Temperature (TMP) Register Group  
REGISTER  
TMPR0  
TMPR1  
TMPR2  
TMPR3  
TMPR4  
RD/WR  
RD  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
ETMP1[7]  
ETMP2[3]  
ETMP2[11]  
ITMP[7]  
ETMP1[6]  
ETMP2[2]  
ETMP2[10]  
ITMP[6]  
ETMP1[5]  
ETMP2[1]  
ETMP2[9]  
ITMP[5]  
REV[0]  
ETMP1[4]  
ETMP2[0]  
ETMP2[8]  
ITMP[4]  
THSD  
ETMP1[3]  
ETMP1[11]  
ETMP2[7]  
ITMP[3]  
ETMP1[2]  
ETMP1[10]  
ETMP2[6]  
ITMP[2]  
ETMP1[1]  
ETMP1[9]  
ETMP2[5]  
ITMP[1]  
ITMP[9]  
ETMP1[0]  
ETMP1[8]  
ETMP2[4]  
ITMP[0]  
ITMP[8]  
RD  
RD  
RD  
RD  
REV[2]  
REV[1]  
ITMP[11]  
ITMP[10]  
Table 14. Packet Error Code (PEC)  
REGISTER  
RD/WR  
BIT 7  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
PEC  
RD  
PEC[7]  
PEC[6]  
PEC[5]  
PEC[4]  
PEC[3]  
PEC[2]  
PEC[1]  
PEC[0]  
Rev. B  
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Table 15. Memory Bit Descriptions  
NAME  
DESCRIPTION  
VALUES  
UV/OV COMPARATOR  
PERIOD  
V
POWERED DOWN  
CELL VOLTAGE  
MEASUREMENT TIME  
REF  
CDC  
BETWEEN MEASUREMENTS  
0
N/A (Comparator Off)  
Standby Mode  
Yes  
N/A  
(default)  
1
N/A (Comparator Off)  
13ms  
No  
No  
13ms  
13ms  
13ms  
13ms  
21ms  
21ms  
21ms  
2
CDC  
Comparator Duty Cycle  
3
130ms  
No  
4
500ms  
No  
5*  
6
130ms  
Yes  
Yes  
Yes  
500ms  
7
2000ms  
*when MMB pin is low, the CDC value is set to 5  
CELL10  
LVLPL  
10-Cell Mode  
0=12-cell mode (default); 1=10-cell mode  
Level Polling Mode  
0=toggle polling (default); 1=level polling  
Write: 0=GPIO1 pin pull down on; 1=GPIO1 pin pull down off (default)  
Read: 0=GPIO1 pin at logic ‘0’; 1=GPIO1 pin at logic ‘1’  
Write: 0=GPIO2 pin pull down on; 1=GPIO2 pin pull down off (default)  
Read: 0=GPIO2 pin at logic ‘0’; 1=GPIO2 pin at logic ‘1’  
Read Only: 0=WDTB pin at logic ‘0’; 1=WDTB pin at logic ‘1’  
GPIO1  
GPIO2  
GPIO1 Pin Control  
GPIO2 Pin Control  
WDT  
Watchdog Timer  
Discharge Cell x  
DCCx  
x=1..12 0=turn off shorting switch for cell ‘x’ (default); 1=turn on shorting switch  
Comparison voltage = VUV * 16 * 1.5mV  
VUV  
Undervoltage Comparison Voltage*  
(default VUV=0. When MMB pin is low a factory programmed comparison voltage is used)  
Comparison voltage = VOV * 16 * 1.5mV  
VOV  
Overvoltage Comparison Voltage*  
Mask Cell x Interrupts  
(default VOV=0. When MMB pin is low a factory programmed comparison voltage is used)  
x=1..12 0=enable interrupts for cell ‘x’ (default)  
1=turn off interrupts and clear flags for cell ‘x’  
MCxI  
x=1..12 12-bit ADC measurement value for cell ‘x’  
cell voltage for cell ‘x’ = CxV * 1.5mV  
CxV  
Cell x Voltage*  
reads as 0xFFF while A/D conversion in progress  
x=1..12 cell voltage compared to VUV comparison voltage  
0=cell ‘x’ not flagged for under voltage condition; 1=cell ‘x’ flagged  
CxUV  
Cell x Undervoltage Flag  
x=1..12 cell voltage compared to VOV comparison voltage  
0=cell ‘x’ not flagged for over voltage condition; 1=cell ‘x’ flagged  
CxOV  
Cell x Overvoltage Flag  
ETMPx  
External Temperature Measurement*  
Temperature measurement voltage = ETMPx * 1.5mV  
0= thermal shutdown has not occurred; 1=thermal shutdown has occurred  
Status cleared to ‘0’ on read of Thermal Register Group  
Device revision code  
THSD  
Thermal Shutdown Status  
REV  
ITMP  
PEC  
Revision Code  
Internal Temperature Measurement*  
Packet Error Code  
Temperature measurement voltage = ITMP * 1.5mV = 8mV * T(°K)  
CRC value for reads  
*Voltage determinations use the decimal value of the registers, 0 to 4095 for 12-bit and 0 to 255 for 8-bit registers.  
Rev. B  
23  
For more information www.analog.com  
LTC6802-2  
APPLICATIONS INFORMATION  
SERIAL COMMAND  
Example for LTC6802-2 (Addressable Configuration)  
Examples below use a configuration of three stacked  
devices: bottom (B), middle (M), and top (T)  
Write Configuration Registers (Broadcast Command)  
1. Pull CSBI low  
2. Send WRCFG command byte  
3. Send CFGR0 byte, then CFGR1, CFGR2, … CFGR5 (All devices on bus receive same data)  
4. Pull CSBI high; data latched into all devices on rising edge of CSBI  
Calculation of serial interface time for sequence above:  
Number of devices in stack= N  
Number of bytes in sequence = B = 1 command byte and 6 data bytes  
Serial port frequency per bit = F  
Time = (1/F) * B * 8 bits/byte = (1/F) * (1+6) * 8  
Time for 3 cell stacks example above, with 1MHz serial port = (1/1000000) * (1+6)*8 = 56us  
Read Cell Voltage Registers (Address Command)  
1. Pull CSBI low  
2. Send Address byte for bottom device  
3. Send RDCV command byte  
4. Read CVR00 byte of bottom device, then CVR01 (B), CVR02 (B), … CVR17 (B), and then PEC (B)  
5. Pull CSBI high  
6. Repeat steps 1-5 for middle device and top device  
Calculation of serial interface time for sequence above:  
Number of devices in stack= N  
Number of bytes in sequence = B = 1 address, 1 command, 18 register, and 1 PEC byte per device = 21*N  
Serial port frequency per bit = F  
Time = (1/F) * B * 8 bits/byte = (1/F) * (21*N) * 8  
Time for 3-cell stacks example above, with 1MHz serial port = (1/1000000) * (21*3)*8 = 504us  
Start Cell Voltage A/D Conversions and Poll Status (Broadcast Command with Toggle Polling)  
1. Pull CSBI low  
2. Send STCVAD command byte (all devices in stack start A/D conversions simultaneously)  
3. SDO output of all devices in parallel pulled low for approximately 12ms  
4. SDO output toggles at 1kHz rate, indicating conversions complete for all devices  
5. Pull CSBI high to exit polling  
Rev. B  
24  
For more information www.analog.com  
LTC6802-2  
APPLICATIONS INFORMATION  
Poll Interrupt Status (Level Polling)  
1. Pull CSBI low  
2. Send Address byte for bottom device  
3. Send PLINT command byte  
4. SDO output from bottom device pulled low if any device has an interrupt condition; otherwise, SDO high  
5. Pull CSBI high to exit polling  
6. Repeat steps 1-5 for middle device and top device  
FAULT PROTECTION  
Overview  
battery system during its useful lifespan. Table 16 shows  
the various situations that should be considered when  
planning protection circuitry. The first five scenarios are to  
be anticipated during production and appropriate protec-  
tion is included within the LTC6802-2 device itself.  
Care should always be taken when using high energy  
sources such as batteries. There are numerous ways  
that systems can be (mis-)configured that might affect a  
Table 16. LTC6802-2 Failure Mechanism Effect Analysis  
SCENARIO  
EFFECT  
DESIGN MITIGATION  
+
–
Cell input open circuit (random)  
Power-up sequence at IC inputs  
Clamp diodes at each pin to V and V (within IC) provide  
alternate power path.  
Cell input open circuit (random)  
Differential input voltage overstress  
Zener diodes across each cell voltage input pair (within IC)  
limits stress.  
+
+
–
Top cell input connection loss (V ) Power will come from highest connected cell input Clamp diodes at each pin to V and V (within IC) provide  
or via data port fault current alternate power path.  
+
–
Bottom cell input connection loss  
Power will come from lowest connected cell input Clamp diodes at each pin to V and V (within IC) provide  
or via data port fault current alternate power path.  
–
(V )  
+
–
Disconnection of a harness between Loss of supply connection to the IC  
a group of battery cells and the IC  
(in a system of stacked groups)  
Clamp diodes at each pin to V and V (within IC) provide  
an alternate power path if there are other devices (which can  
supply power) connected to the LTC6802-2.  
Data link disconnection between  
LTC6802-2 and the master.  
Loss of serial communication (no stress to ICs).  
The device will enter standby mode within 2 seconds of  
disconnect. Discharge switches are disabled in standby mode.  
Cell-pack integrity, break between  
stacked units  
No effect during charge or discharge  
Use digital isolators to isolate the LTC6802-2 serial port from  
other LTC6802-2 serial ports.  
Cell-pack integrity, break within  
stacked unit  
Cell input reverse overstress during discharge  
Add parallel Schottky diodes across each cell for load-path  
redundancy. Diode and connections must handle full operating  
current of stack, will limit stress on IC  
Cell-pack integrity, break within  
stacked unit  
Cell input positive overstress during charge  
Add SCR across each cell for charge-path redundancy. SCR  
and connections must handle full charging current of stack, will  
limit stress on IC by selection of trigger Zener  
Rev. B  
25  
For more information www.analog.com  
LTC6802-2  
APPLICATIONS INFORMATION  
Internal Protection Diodes  
of 30V snapping back to 25V. The forward voltage drop  
of all Zeners is 0.5V. Refer to this diagram in the event of  
unpredictable voltage clamping or current flow. Limiting  
the current flow at any pin to 10mA will prevent damage  
to the IC.  
Each pin of the LTC6802-2 has protection diodes to help  
prevent damage to the internal device structures caused  
by external application of voltages beyond the supply rails  
as shown in Figure 9.  
The diodes shown are conventional silicon diodes with a  
forward breakdown voltage of 0.5V. The unlabeled Zener  
diode structures have a reverse-breakdown characteristic  
which initially breaks down at 12V then snaps back to a 7V  
Cell-Voltage Filtering  
The LTC6802-2 employs a sampling system to perform its  
analog-to-digital conversions and provides a conversion  
result that is essentially an average over the 0.5ms con-  
version window, provided there isn’t noise aliasing with  
respect to the delta-sigma modulator rate of 512kHz. This  
indicates that a lowpass filter with useful attenuation at  
500kHz may be beneficial. Since the delta-sigma integra-  
tion bandwidth is about 1kHz, the filter corner need not  
be lower than this to assure accurate conversions.  
clamping potential. The Zener diodes labeled Z  
are  
CLAMP  
higher voltage devices with an initial reverse breakdown  
ꢜ
ꢆꢇꢈꢀꢁꢂꢃꢉꢃ  
ꢌ
ꢈꢋꢃ  
ꢊꢋꢃ  
ꢈꢋꢋ  
ꢊꢋꢋ  
ꢈꢋꢂ  
Series resistors of 100Ω may be inserted in the input  
paths without introducing meaningful measurement  
error, provided only external discharge switch FETs are  
being used. Shunt capacitors may be added from the cell  
ꢝ
ꢈꢆꢛꢑꢖ  
ꢊꢋꢂ  
ꢈꢅ  
–
inputs to V , creating RC filtering as shown in Figure 10.  
Note that this filtering is not compatible with use of the  
internal discharge switches to carry current since this  
would induce settling errors at the time of conversion  
as any activated switches temporarily open to provide  
Kelvin mode cell sensing. As a discharge switch opens,  
cell wiring resistance will also form a small voltage step  
(recovery of the small IR drop), so keeping the frequency  
cutoff of the filter relatively high will allow adequate set-  
tling prior to the actual conversion. A guard time of about  
60µs is provided in the ADC timing, so a 16kHz LP is  
optimal and offers about 30dB of noise rejection.  
ꢊꢅ  
ꢈꢁ  
ꢊꢁ  
ꢈꢚ  
ꢊꢚ  
ꢈꢀ  
ꢊꢀ  
ꢈꢙ  
ꢊꢙ  
ꢈꢘ  
ꢛꢗ  
ꢛꢃ  
ꢝ
ꢈꢆꢛꢑꢖ  
ꢛꢋ  
ꢛꢂ  
ꢈꢊBꢐ  
ꢊꢏꢒ  
ꢊꢏꢐ  
ꢊꢈꢔꢐ  
ꢊꢘ  
ꢈꢗ  
ꢊꢗ  
ꢈꢃ  
ꢊꢃ  
ꢈꢋ  
ꢊꢋ  
ꢌꢍ  
Cn  
100Ω  
100nF  
ꢌ
ꢑꢒꢏꢓ  
6.2V  
ꢕꢖꢐꢒꢃ  
ꢕꢖꢐꢒꢋ  
ꢎꢏꢇB  
ꢑꢑB  
ꢇꢒꢊ  
+
ꢝ
ꢈꢆꢛꢑꢖ  
Sn  
Cn – 1  
100Ω  
100nF  
68021 F10  
Figure 10. Adding RC Filtering to the Cell Inputs  
(One Cell Connection Shown)  
ꢀꢁꢂꢃꢃ ꢄꢂꢅ  
Figure 9. Internal Protection Diodes  
Rev. B  
26  
For more information www.analog.com  
LTC6802-2  
APPLICATIONS INFORMATION  
No resistor should be placed in series with the V– pin.  
Because the supply current flows from the V– pin, any  
resistance on this pin could generate a significant conver-  
sion error for CELL1.  
pin in this case. Probe loads up to about 1mA maximum  
are supported in this configuration. Since V  
is shut-  
REF  
down during the LTC6802-2 idle and shutdown modes,  
the thermistor drive is also shut off and thus power dis-  
sipation minimized. Since V  
remains always on, the  
REG  
buffer op amp (LT6000 shown) is selected for its ultralow  
power consumption (10µA).  
READING EXTERNAL TEMPERATURE PROBES  
Using Dedicated Inputs  
Expanding Probe Count  
The LTC6802-2 includes two channels of ADC input,  
The LTC6802-2 provides general purpose I/O pins, GPIO1  
and GPIO2, that may be used to control multiplexing of  
several temperature probes. Using just one of the GPIO  
pins, the sensor count can double to four as shown in  
Figure 13. Using both GPIO pins, up to eight sensor inputs  
can be supported.  
V
and V  
, that are intended to monitor therm-  
TEMP1  
TEMP2  
istors (tempco about –4%/°C generally) or diodes  
(–2.2mV/°C typical) located within the cell array. Sensors  
can be powered directly from V as shown in Figure 11  
REF  
(up to 60µA total).  
For sensors that require higher drive currents, a buffer  
op amp may be used as shown in Figure 11. Power for  
the sensor is actually sourced indirectly from the V  
LTC6802-2  
GPIO1  
SN74LVC1G3157  
OR SIMILAR DEVICE  
REG  
100k  
100k  
LTC6802-2  
100k  
NTC  
100k  
100k  
V
V
REG  
100k  
V
V
REG  
REF  
REF  
100k  
NTC  
V
V
TEMP2  
V
V
TEMP2  
TEMP1  
NC  
TEMP1  
NC  
100k  
NTC  
100k  
NTC  
1µF  
−
V
1µF  
−
V
100k  
NTC  
1µF  
100k  
NTC  
68022 F13  
68022 F11  
Figure 13. Expanding Sensor Count with Multiplexing  
Figure 11. Driving Thermistors Directly from VREF  
Using Diodes to Monitor Temperatures  
in Multiple Locations  
+
Another method of multiple sensor support is possible  
without the use of any GPIO pins. If the sensors are PN  
diodes and several used in parallel, then the hottest diode  
will produce the lowest forward voltage and effectively  
LT6000  
–
LTC6802-2  
establish the input signal to the V  
input(s). The hot-  
TEMP  
V
V
REG  
10k  
10k  
test diode will therefore dominate the readout from the  
VTEMP inputs that the diodes are connected to. In this  
scenario, the specific location or distribution of heat is  
not known, but such information may not be important  
in practice. Figure 14 shows the basic concept.  
REF  
V
V
TEMP2  
TEMP1  
NC  
10k  
NTC  
−
V
10k  
NTC  
In any of the sensor configurations shown, a full-scale  
cold readout would be an indication of a failed-open sen-  
sor connection to the LTC6802-2.  
68022 F12  
Figure 12. Buffering VREF for Higher Current Sensors  
Rev. B  
27  
For more information www.analog.com  
LTC6802-2  
APPLICATIONS INFORMATION  
200k  
of the total stack potential. This provides a redundant  
operational measurement of the cells in the event of a mal-  
function in the normal acquisition process, or as a faster  
means of monitoring the entire stack potential. Figure 15  
shows a means of providing both of these features. A  
resistor divider is used to provide a low voltage repre-  
sentation of the full stack potential (C12 to C0 voltage)  
with MOSFETs that decouple the divider current under  
unneeded conditions. Other MOSFETs, in conjunction with  
an op amp having a shutdown mode, form a voltage selec-  
tor that allows measurement of the normal cell1 potential  
(when GPIO1 is low) or a buffered MUX signal. When the  
MUX is active (GPIO1 is high), selection can be made  
between the reference (4.096V) or the full-stack voltage  
divider (GPOI2 set low will select the reference). During  
idle time when the LTC6802-2 WDTB signal goes low,  
the external circuitry goes into a power-down condition,  
reducing battery drain to a minimum. When not actively  
performing measurements, GPIO1 should be set low and  
GPIO2 should be set high to achieve the lowest power  
state for the configuration shown.  
LTC6802-2  
V
V
REG  
200k  
REF  
V
V
TEMP2  
TEMP1  
NC  
−
V
68022 F14  
Figure 14. Using Diode Sensors as Hot-Spot Detectors  
ADDING CALIBRATION AND  
FULL-STACK MEASUREMENTS  
By adding multiplexing hardware, additional signals can  
be digitized by the CELL1 ADC channel. One useful sig-  
nal to provide is a high accuracy voltage reference, such  
as from an LT®1461A-4 or LTC6652A-4.096. By periodic  
readings of this signal, host software can provide correc-  
tion of the LTC6802-2 readings to improve the accuracy  
over that of the internal LTC6802-2 reference, and/or vali-  
date ADC operation. Another useful signal is a measure  
TP0610K  
CELL12  
1M  
V
2.2M  
0 = REF_EN  
0 = CELL1  
GPIO2  
GPIO1  
WDTB  
ꢀꢁꢂꢃꢄꢅꢆ  
LT1461A-4  
DNC DNC  
1M  
1M  
10M  
1M  
1µF  
V
REG  
V
IN  
ꢀꢇ  
DNC  
4.096V  
2N7002  
V
OUT  
GND DNC  
LTC6802-2  
90.9k  
2N7002  
−
V
2.2µF  
C1  
150Ω  
100nF  
TP0610K  
+
TP0610K TP0610K  
V
CH0 CH1 SEL  
DD  
CELL1  
LT1636  
100Ω  
SD  
TC4W53FU  
COM INH  
–
V
V
SS  
EE  
1M  
68022 F15  
Figure 15. Providing Measurement of Calibration Reference and Full-Stack Voltage Through CELL1 Port  
Rev. B  
28  
For more information www.analog.com  
LTC6802-2  
APPLICATIONS INFORMATION  
PROVIDING HIGH SPEED OPTO-ISOLATION  
OF THE SPI DATA PORT  
PCB LAYOUT CONSIDERATIONS  
The V  
and V  
pins should be bypassed with a 1µF  
REF  
REG  
capacitor for best performance.  
Isolation techniques that are capable of supporting the  
1Mbps data rate of the LTC6802-2 require more power  
on the isolated (battery) side than can be furnished by  
The LTC6802-2 is capable of operation with as much as  
+
–
60V between V and V . Care should be taken on the PCB  
layout to maintain physical separation of traces at differ-  
ent potentials. The pinout of the LTC6802-2 was chosen  
to facilitate this physical separation. Figure 17 shows the  
the V  
output of the LTC6802-2. To keep battery drain  
REG  
minimal, this means that a DC/DC function must be imple-  
mented along with a suitable data isolation circuit, such  
as shown in Figure 16. Here an optimal Avago 4-channel  
(3/1 bidirectional) opto-coupler is used, with a simple  
isolated supply generated by an LTC1693-2 configured  
as a 200kHz oscillator. The DC/DC function provides an  
unregulated logic voltage (~4V) to the opto-coupler iso-  
lated side, from energy provided by host-furnished 5V.  
This circuit provides totally galvanic isolation between  
the batteries and the host processor, with an insulation  
rating of 560V continuous, 2500V transient. The Figure 16  
functionality is included in the LTC6802-2 demo board.  
–
DC voltage on each pin with respect to V when twelve  
3.6V battery cells are connected to the LTC6802-2. There  
is no more then 5.5V between any two adjacent pins.  
The package body is used to separate the highest voltage  
(43.5V) from the lowest voltage (0V).  
+5V_HOST  
330Ω  
100k  
CSBI  
3.57k  
3.57k  
3.57k  
100k  
CSBI  
SDO  
SDI  
SDI  
TP0610K  
100k  
SCKI  
330Ω  
TP0610K  
330Ω  
TP0610K  
SCKI  
V
REG  
SDO  
100nF  
4.99k  
249Ω  
LTC6802-2  
GND_HOST  
ACSL-6410  
ISOLATED V  
LOGIC  
1µF  
470pF  
20k  
BAT54S  
BAT54S  
6
V
IN1  
OUT1 GND1  
IN2  
CC1  
1µF  
1
•
•
33nF  
V
CC2  
10k  
4
3
ꢀꢁꢂꢃ GND2  
−
V
PE68386  
LTC1693-2  
68022 F16  
Figure 16. Providing an Isolated High-Speed Data Interface  
Rev. B  
29  
For more information www.analog.com  
LTC6802-2  
APPLICATIONS INFORMATION  
ꢜꢎꢂꢊꢈꢆꢄꢝꢄ  
ꢁ
ꢌꢍ.ꢄꢀ  
ꢌꢍ.ꢄꢀ  
ꢌꢍ.ꢄꢀ  
ꢍꢇ.ꢊꢀ  
ꢍꢇ.ꢊꢀ  
ꢍꢊꢀ  
ꢀ
ꢂꢅBꢐ  
ꢅꢑꢏ  
ꢅꢑꢐ  
ꢅꢂꢒꢐ  
ꢓꢍ  
ꢓꢄ  
ꢓꢃ  
ꢓꢆ  
ꢔꢕꢐꢏꢄ  
ꢔꢕꢐꢏꢃ  
ꢖꢑꢎB  
ꢗꢗB  
ꢎꢏꢅ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢆꢀ ꢎꢏ ꢋ.ꢋꢀ  
ꢋ.ꢋꢀ  
ꢍ.ꢃꢀ  
ꢃ.ꢋꢀ  
ꢃ.ꢋꢀ  
ꢆꢀ  
ꢆꢀ  
ꢍ.ꢊꢀ  
ꢍ.ꢊꢀ  
ꢉ.ꢄꢀ  
ꢂꢃꢄ  
ꢅꢃꢄ  
ꢂꢃꢃ  
ꢅꢃꢃ  
ꢂꢃꢆ  
ꢅꢃꢆ  
ꢂꢇ  
ꢅꢇ  
ꢂꢈ  
ꢅꢈ  
ꢂꢉ  
ꢅꢉ  
ꢂꢊ  
ꢅꢊ  
ꢂꢋ  
ꢅꢋ  
ꢂꢌ  
ꢅꢌ  
ꢂꢍ  
ꢍꢊꢀ  
ꢍꢄ.ꢌꢀ  
ꢍꢄ.ꢌꢀ  
ꢄꢈ.ꢈꢀ  
ꢄꢈ.ꢈꢀ  
ꢄꢋ.ꢄꢀ  
ꢄꢋ.ꢄꢀ  
ꢄꢃ.ꢊꢀ  
ꢄꢃ.ꢊꢀ  
ꢃꢈꢀ  
ꢀ
Rꢘꢔ  
ꢀ
Rꢘꢙ  
ꢀ
ꢀ
ꢎꢘꢗꢕꢄ  
ꢃꢈꢀ  
ꢎꢘꢗꢕꢃ  
ꢚꢂ  
ꢃꢌ.ꢌꢀ  
ꢃꢌ.ꢌꢀ  
ꢃꢆ.ꢈꢀ  
ꢃꢆ.ꢈꢀ  
ꢉ.ꢄꢀ  
ꢛ
ꢀ
ꢅꢃ  
ꢂꢃ  
ꢅꢄ  
ꢊꢈꢆꢄꢄ ꢙꢃꢉ  
ꢅꢍ  
ꢂꢄ  
Figure 17. Typical Pin Voltages for 12 3.6V Cells  
to measure several input channels a separate filter will be  
ADVANTAGES OF DELTA-SIGMA ADCS  
required for each channel. A low frequency filter cannot  
reside between a multiplexer and an ADC and achieve a  
high scan rate across multiple channels. Another conse-  
quence of filtering a SAR ADC is that any noise reduction  
gained by filtering the input cancels the benefit of having  
a high sample rate in the first place, since the filter will  
take many conversion cycles to settle.  
The LTC6802-2 employs a delta-sigma analog-to-digital  
converter for voltage measurement. The architecture of  
delta-sigma converters can vary considerably, but the  
common characteristic is that the input is sampled many  
times over the course of a conversion and then filtered  
or averaged to produce the digital output code. In con-  
trast, a SAR converter takes a single snapshot of the input  
voltage and then performs the conversion on this single  
sample. For measurements in a noisy environment, a  
delta-sigma converter provides distinct advantages over  
a SAR converter.  
For a given sample rate, a delta-sigma converter can  
achieve excellent noise rejection while settling completely  
in a single conversion—something that a filtered SAR  
converter cannot do. Noise rejection is particularly impor-  
tant in high voltage switching controllers, where switching  
noise will invariably be present in the measured voltage.  
Other advantages of delta sigma converters are that they  
are inherently monotonic, meaning they have no missing  
codes, and they have excellent DC specifications.  
While SAR converters can have high sample rates, the full-  
power bandwidth of a SAR converter is often greater than  
1MHz, which means the converter is sensitive to noise out  
to this frequency. And many SAR converters have much  
higher bandwidths—up to 50MHz and beyond. It is pos-  
sible to filter the input, but if the converter is multiplexed  
Rev. B  
30  
For more information www.analog.com  
LTC6802-2  
APPLICATIONS INFORMATION  
Converter Details  
is applied to the LTC6802-2 input, the increase in noise  
seen at the digital output will be the same as an ADC with  
a wide bandwidth (such as a SAR) preceded by a perfect  
1350Hz brickwall lowpass filter.  
The LTC6802-2’s ADC has a second-order delta-sigma  
modulator followed by a Sinc2, finite impulse response  
(FIR) digital filter. The front-end sample rate is 512ksps,  
which greatly reduces input filtering requirements. A  
simple 16kHz, 1-pole filter composed of a 100Ω resistor  
and a 0.1μF capacitor at each input will provide adequate  
filtering for most applications. These component values  
will not degrade the DC accuracy of the ADC.  
Thus if an analog filter is placed in front of a SAR converter  
to achieve the same noise rejection as the LTC6802-2  
ADC, the SAR will have a slower response to input sig-  
nals. For example, a step input applied to the input of the  
850Hz filter will take 1.55ms to settle to 12 bits of preci-  
sion, while the LTC6802-2 ADC settles in a single 1ms  
conversion cycle. This also means that very high sample  
rates do not provide any additional information because  
the analog filter limits the frequency response.  
Each conversion consists of two phases—an autozero  
phase and a measurement phase. The ADC is autozeroed  
at each conversion, greatly improving CMRR. The second  
half of the conversion is the actual measurement.  
While higher order active filters may provide some  
improvement, their complexity makes them impractical  
for high-channel count measurements as a single filter  
would be required for each input.  
Noise Rejection  
Figure 18 shows the frequency response of the ADC. The  
roll-off follows a Sinc2 response, with the first notch at  
4kHz. Also shown is the response of a 1-pole, 850Hz fil-  
ter (187μs time constant) which has the same integrated  
response to wideband noise as the LTC6802-2’s ADC,  
which is about 1350Hz. This means that if wideband noise  
Also note that the Sinc2 response has a 2nd order roll-off  
envelope, providing an additional benefit over a single-  
pole analog filter.  
ꢑꢒ  
ꢒ
ꢔꢑꢒ  
ꢔꢖꢒ  
ꢔꢗꢒ  
ꢔꢘꢒ  
ꢔꢙꢒ  
ꢔꢕꢒ  
ꢑꢒ  
ꢑꢒꢒ  
ꢑꢓ  
ꢑꢒꢓ  
ꢑꢒꢒꢓ  
ꢀRꢄꢋꢌꢄꢇꢍꢎ ꢈꢏꢐꢊ  
ꢕꢚꢒꢖꢖ ꢀꢑꢚ  
Figure 18. Noise Filtering of the LTC6802-2 ADC  
Rev. B  
31  
For more information www.analog.com  
LTC6802-2  
PACKAGE DESCRIPTION  
G Package  
44-Lead Plastic SSOP (5.3mm)  
ꢎReꢩeꢪeꢫꢬe ꢔꢑꢝ ꢡꢦꢀ ꢭ ꢅꢍꢮꢅꢆꢮꢇꢘꢍꢁ Rev ꢊꢏ  
ꢇꢌ.ꢍꢅ ꢋ ꢇꢗ.ꢇꢅꢖ  
ꢎ.ꢁꢕꢌ ꢋ .ꢍꢇꢚꢏ  
ꢇ.ꢌꢍ ꢅ.ꢇꢌ  
ꢍ.ꢗ ꢋ ꢍ.ꢘ  
ꢁꢅ ꢗꢆ  
ꢁꢁ ꢁꢗ ꢁꢌ ꢁꢇ ꢗꢕ ꢗꢘ ꢗꢚ ꢗꢍ ꢗꢁ ꢗꢗ ꢗꢌ ꢗꢇ ꢗꢅ ꢌꢕ ꢌꢆ ꢌꢘ ꢌꢚ ꢌꢍ ꢌꢁ ꢌꢗ  
ꢘ.ꢆ ꢋ ꢆ.ꢌ  
ꢘ.ꢁꢅ ꢋ ꢆ.ꢌꢅ  
ꢎ.ꢌꢕꢇ ꢋ .ꢗꢌꢗꢏ  
ꢅ.ꢍꢅ  
Bꢂꢝ  
ꢅ.ꢌꢍ ꢅ.ꢅꢍ  
ꢍ
ꢘ
ꢆ
Rꢈꢝꢃꢛꢛꢈꢓꢡꢈꢡ ꢂꢃꢔꢡꢈR ꢄꢊꢡ ꢔꢊꢟꢃꢢꢑ  
ꢊꢄꢄꢔꢟ ꢂꢃꢔꢡꢈR ꢛꢊꢂꢨ ꢑꢃ ꢊRꢈꢊꢂ ꢑꢠꢊꢑ ꢊRꢈ ꢓꢃꢑ ꢂꢃꢔꢡꢈRꢈꢡ  
ꢇ
ꢌ
ꢗ
ꢁ
ꢚ
ꢕ ꢇꢅ ꢇꢇ ꢇꢌ ꢇꢗ ꢇꢁ ꢇꢍ ꢇꢚ ꢇꢘ ꢇꢆ ꢇꢕ ꢌꢅ ꢌꢇ ꢌꢌ  
ꢌ.ꢅ  
ꢎ.ꢅꢘꢕꢏ  
ꢛꢊꢜ  
ꢍ.ꢅꢅ ꢋ ꢍ.ꢚꢅꢖ  
ꢎ.ꢇꢕꢘ ꢋ .ꢌꢌꢇꢏ  
ꢇ.ꢚꢍ ꢋ ꢇ.ꢆꢍ  
ꢎ.ꢅꢚꢍ ꢋ .ꢅꢘꢗꢏ  
ꢄꢊRꢑꢒꢓꢀ  
ꢅꢐ ꢋ ꢆꢐ  
ꢔꢒꢓꢈ  
ꢂꢈꢊꢑꢒꢓꢀ  
ꢄꢔꢊꢓꢈ  
ꢅ.ꢍꢅ  
ꢎ.ꢅꢇꢕꢚꢆꢏ  
Bꢂꢝ  
ꢅ.ꢇꢅ ꢋ ꢅ.ꢌꢍ  
ꢎ.ꢅꢅꢁ ꢋ .ꢅꢇꢅꢏ  
ꢅ.ꢍꢍ ꢋ ꢅ.ꢕꢍꢖꢖ  
ꢎ.ꢅꢌꢌ ꢋ .ꢅꢗꢘꢏ  
ꢇ.ꢌꢍ  
ꢎ.ꢅꢁꢕꢌꢏ  
Rꢈꢙ  
ꢅ.ꢅꢍ  
ꢎ.ꢅꢅꢌꢏ  
ꢛꢒꢓ  
ꢞ
ꢅ.ꢌꢅ ꢋ ꢅ.ꢗꢇꢍ  
ꢎ.ꢅꢅꢆ ꢋ .ꢅꢇꢌꢁꢏ  
ꢑꢟꢄ  
ꢀꢁꢁ ꢂꢂꢃꢄ ꢅꢆꢇꢁ Rꢈꢉ ꢊ  
ꢓꢃꢑꢈꢥ  
ꢇ.ꢡRꢊꢦꢒꢓꢀ ꢒꢂ ꢓꢃꢑ ꢊ ꢧꢈꢡꢈꢝ ꢃꢢꢑꢔꢒꢓꢈ  
ꢖꢡꢒꢛꢈꢓꢂꢒꢃꢓꢂ ꢡꢃ ꢓꢃꢑ ꢒꢓꢝꢔꢢꢡꢈ ꢛꢃꢔꢡ ꢙꢔꢊꢂꢠ ꢃR ꢄRꢃꢑRꢢꢂꢒꢃꢓꢂꢣ  
Bꢢꢑ ꢡꢃ ꢒꢓꢝꢔꢢꢡꢈ ꢛꢃꢔꢡ ꢛꢒꢂꢛꢊꢑꢝꢠ ꢊꢓꢡ ꢊRꢈ ꢛꢈꢊꢂꢢRꢈꢡ ꢊꢑ  
ꢑꢠꢈ ꢄꢊRꢑꢒꢓꢀ ꢔꢒꢓꢈ. ꢛꢃꢔꢡ ꢙꢔꢊꢂꢠ ꢂꢠꢊꢔꢔ ꢓꢃꢑ ꢈꢜꢝꢈꢈꢡ .ꢇꢍꢤꢤ ꢄꢈR ꢂꢒꢡꢈ  
ꢌ. ꢝꢃꢓꢑRꢃꢔꢔꢒꢓꢀ ꢡꢒꢛꢈꢓꢂꢒꢃꢓꢥ ꢛꢒꢔꢔꢒꢛꢈꢑꢈRꢂ  
ꢛꢒꢔꢔꢒꢛꢈꢑꢈRꢂ  
ꢗ. ꢡꢒꢛꢈꢓꢂꢒꢃꢓꢂ ꢊRꢈ ꢒꢓ  
ꢎꢒꢓꢝꢠꢈꢂꢏ  
ꢖꢖꢔꢈꢓꢀꢑꢠ ꢃꢙ ꢔꢈꢊꢡ ꢙꢃR ꢂꢃꢔꢡꢈRRꢒꢓꢀ ꢑꢃ ꢊ ꢂꢢBꢂꢑRꢊꢑꢈ  
ꢞ
ꢑꢠꢈ ꢛꢊꢜꢒꢛꢢꢛ ꢡꢒꢛꢈꢓꢂꢒꢃꢓ ꢡꢃꢈꢂ ꢓꢃꢑ ꢒꢓꢝꢔꢢꢡꢈ ꢡꢊꢛBꢊR ꢄRꢃꢑRꢢꢂꢒꢃꢓꢂ.  
ꢡꢊꢛBꢊR ꢄRꢃꢑRꢢꢂꢒꢃꢓꢂ ꢡꢃ ꢓꢃꢑ ꢈꢜꢝꢈꢈꢡ ꢅ.ꢇꢗꢤꢤ ꢄꢈR ꢂꢒꢡꢈ  
ꢁ. ꢡRꢊꢦꢒꢓꢀ ꢓꢃꢑ ꢑꢃ ꢂꢝꢊꢔꢈ  
ꢍ. ꢙꢃRꢛꢈꢡ ꢔꢈꢊꢡꢂ ꢂꢠꢊꢔꢔ Bꢈ ꢄꢔꢊꢓꢊR ꢦꢒꢑꢠ Rꢈꢂꢄꢈꢝꢑ ꢑꢃ  
ꢃꢓꢈ ꢊꢓꢃꢑꢠꢈR ꢦꢒꢑꢠꢒꢓ ꢅ.ꢅꢆꢤꢤ ꢊꢑ ꢂꢈꢊꢑꢒꢓꢀ ꢄꢔꢊꢓꢈ  
Rev. B  
32  
For more information www.analog.com  
LTC6802-2  
REVISION HISTORY  
REV  
DATE  
DESCRIPTION  
PAGE NUMBER  
A
01/10 Additions to Absolute Maximum Ratings  
Changes to Electrical Characteristics  
Change to Graph G10  
2
3, 4  
5
8, 9  
Text Changes to Pin Configuration  
Replaced Open-Connection Detection Section  
Edits to Figures 1, 9  
10, 11, 12  
11, 26  
Text Changes to Operation Section  
13  
Text Changes to Applications Information Section  
Edits to Tables 4, 5, 9, 10, 15, 16  
14, 25, 27  
19, 20, 21, 23  
2
B
06/19 Updated order information to include automotive versions  
Rev. B  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog  
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications  
33  
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
LTC6802-2  
TYPICAL APPLICATION  
Stacked Daisy-Chain SPI Bus for LTC6802-2  
V
BATT  
LTC6802-2  
IC #3  
V
REG  
1M  
1.8k  
2.2k  
2.2k  
2.2k  
WDT  
NDC7002N  
ALL NPN: CMPT8099  
ALL PNP: CMPT8599  
ALL PN: RS07J  
SDI  
SCKI  
CSBI  
ALL SCHOTTKY: CMD5H2-3  
SDO  
−
V
LTC6802-2  
IC #2  
V
REG  
100Ω  
2.2k  
2.2k  
2.2k  
SDI  
SCKI  
CSBI  
SDO  
−
V
LTC6802-2  
IC #1  
V
REG  
100Ω  
2.2k  
2.2k  
2.2k  
SDI  
SCKI  
CSBI  
SDO  
CS  
CK  
DI  
HOST µP  
500kbps MAX DATA RATE  
R12  
2.2k  
DO  
−
V
68022 TA02  
RELATED PARTS  
PART NUMBER  
DESCRIPTION  
COMMENTS  
LTC6802-1  
Multicell Battery Stack Monitor with Daisy Chained  
Serial Interface  
Functionality equivalent to LTC6802-2, Allows for Multiple Devices to be  
Daisy Chained  
Rev. B  
06/19  
www.analog.com  
34  
ANALOG DEVICES, INC. 2009-2019  

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