LTC6912CDE-2#TR [Linear]
LTC6912 - Dual Programmable Gain Amplifiers with Serial Digital Interface; Package: DFN; Pins: 12; Temperature Range: 0°C to 70°C;
| 型号： | LTC6912CDE-2#TR |
| 厂家： | 
Linear |
| 描述： | LTC6912 - Dual Programmable Gain Amplifiers with Serial Digital Interface; Package: DFN; Pins: 12; Temperature Range: 0°C to 70°C 放大器 |
| 文件： | 总24页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6912
Dual Programmable
Gain Amplifiers with
Serial Digital Interface
U
FEATURES
DESCRIPTIO
The LTC®6912 is a family of dual channel, low noise,
digitally programmable gain amplifiers (PGA) that are
easy to use and occupy very little PC board space. The
gains for both channels are independently programmable
using a 3-wire SPI interface to select voltage gains of 0, 1,
2, 5, 10, 20, 50, and 100V/V (LTC6912-1 ); and 0, 1, 2, 4,
8, 16, 32, and 64V/V (LTC6912-2). All gains are inverting.
■
2 Channels with Independent Gain Control
LTC6912-1: (0, 1, 2, 5, 10, 20, 50, and 100V/V)
LTC6912-2: (0, 1, 2, 4, 8, 16, 32, and 64V/V)
■
Offset Voltage = 2mV Max (–40°C to 85°C)
■
Channel-to-Channel Gain Matching of 0.1dB Max
3-Wire SPITM Interface
■
■
Extended Gain-Bandwidth at High Gains
■
Wired-OR Outputs Possible (2:1 Analog MUX
The LTC6912 family consists of 2 matched amplifiers with
rail-to-rail outputs. When operated with unity gain, they
will also process rail-to-rail input signals. A half-supply
reference generated internally at the AGND pin supports
single power supply applications. Operating from single
or split supplies from 2.7V to 10.5V total, the LTC6912-X
family is offered in tiny SSOP and DFN-12 Packages.
Function)
■
Low Power Hardware Shutdown (GN-16 Only,
2µA Max at 2.7V)
■
Rail-to-Rail Input Range
■
Rail-to-Rail Output Swing
■
Single or Dual Supply: 2.7V to 10.5V Total
■
Input Noise: 12.6nV/√Hz
■
Total System Dynamic Range to 115dB
■
16-Pin GN (SSOP) or 12-Pin DFN Package Options
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
APPLICATIO S
■
Data Acquisition Systems
■
Dynamic Gain Changing
■
Automatic Ranging Circuits
Automatic Gain Control
■
U
TYPICAL APPLICATIO
A Dual, Matched Low Noise PGA (16-Lead SSOP Package)
3V
0.1µF
LTC6912-2
Frequency Response
12
+
14
–
V
V
40
V
V
=
IN
±2.5V
GAIN OF 64
GAIN OF 32
GAIN OF 16
GAIN OF 8
GAIN OF 4
GAIN OF 2
GAIN OF 1
S
= 10mV
RMS
2
3
4
15
13
INA
OUT A
V
V
= GAIN • V
A
INA
OUTA
OUTB
INA
30
20
1µF
LTC6912-X
AGND
INB
OUT B
10
V
= GAIN • V
B
V
INB
INB
0
–10
CHB
SHDN
CHA
DGND
5
6
7
8
0.1
10
100
1000 10000
1
SHDN
CS/LD
DATA
CLK
10
FREQUENCY (kHz)
CS/LD
3-WIRE
SPI
INTERFACE
6912 TA01b
D
IN
9
D
OUT
6912 TA01a
6912fa
1
LTC6912
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
Specified Temperature Range (Note 3)
Total Supply Voltage (V+ to V–)............................... 11V
Input Current ...................................................... ±10mA
Operating Temperature Range (Note 2)
LTC6912C-1, LTC6912C-2 ..................–40°C to 85°C
LTC6912I-1, LTC6912I-2.....................–40°C to 85°C
LTC6912H-1, LTC6912H-2
LTC6912C-1, LTC6912C-2 ..................–40°C to 85°C
LTC6912I-1, LTC6912I-2.....................–40°C to 85°C
LTC6912H-1, LTC6912H-2
(GN-16 Only) .....................................–40°C to 125°C
Storage Temperature Range ..................–65°C to 150°C
UE Package ....................................... –65°C to 125°C
Lead Temperature (Soldering, 10sec)................... 300°C
(GN-16 Only) .....................................–40°C to 125°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
NC
INA
1
2
3
4
5
6
7
8
16 NC
INA
AGND
INB
1
2
3
4
5
6
12 OUTA
–
15 OUT A
–
11
V
AGND
INB
14
13
12
11
10
9
V
10 OUTB
+
13
OUT B
CS/LD
DIN
9
8
7
V
+
SHDN
CS/LD
V
DGND
DOUT
NC
CLK
D
DGND
IN
UE12 PACKAGE
CLK
D
OUT
12-LEAD (4mm × 3mm) PLASTIC DFN
–
EXPOSED PAD IS CONNECTED TO V (PIN 13),
GN PACKAGE
MUST BE SOLDERED TO PCB
16-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 160°C/W
TJMAX = 150°C, θJA = 120°C/W
ORDER PART
NUMBER
DFN PART*
MARKING
ORDER PART
NUMBER
GN PART
MARKING
LTC6912CGN-1
LTC6912IGN-1
LTC6912HGN-1
LTC6912CGN-2
LTC6912IGN-2
LTC6912HGN-2
69121
LTC6912CDE-1
LTC6912IDE-1
LTC6912CDE-2
LTC6912IDE-2
69121
69121
69122
69122
6912I1
6912H1
69122
6912I2
6912H2
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
6912fa
2
LTC6912
U
U
U
GAI SETTI GS A D PROPERTIES
Table 1. LTC6912-1 GAIN SETTINGS AND PROPERTIES
UPPER/LOWER
NIBBLE
NOMINAL
VOLTAGE GAIN
MAXIMUM LINEAR INPUT RANGE (V
)
P-P
Q7
Q3
Q6
Q2
Q5
Q1
Q4
Q0
Dual 5V
Supply
Single 5V
Supply
Single 3V
Supply
NOMINAL INPUT NOMINAL OUTPUT
IMPEDANCE (kΩ) IMPEDANCE (Ω)
Volts/Volt
dB
–120
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
X
X
0
–1
10
5
5
3
3
(Open)
0.4
0.7
10
10
–2
6
5
2.5
1
1.5
0.6
0.3
0.15
0.06
0.03
3
5
3.4
–5
14
2
2
3.4
–10
–20
–50
–100
0
20
1
0.5
0.25
0.1
0.05
5
1
3.4
26
0.5
1
6.4
34
0.2
1
1
15
40
0.1
10
30
–120
(Open)
(Open)
Not Used (Note 11)
Not Used
Table 2. LTC6912-2 GAIN SETTINGS AND PROPERTIES
UPPER/LOWER
NIBBLE
NOMINAL
VOLTAGE GAIN
MAXIMUM LINEAR INPUT RANGE (V
)
P-P
Q7
Q3
Q6
Q2
Q5
Q1
Q4
Q0
Dual 5V
Supply
Single 5V
Supply
Single 3V
Supply
NOMINAL INPUT NOMINAL OUTPUT
IMPEDANCE (kΩ) IMPEDANCE (Ω)
Volts/Volt
dB
–120
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
X
X
0
10
5
5
3
(Open)
10
0.4
0.7
–1
10
3
–2
6
5
2.5
1.5
5
3.4
–4
–8
12
2.5
1.25
0.625
0.3125
0.156
0.078
5
0.75
0.375
0.188
0.094
0.047
3
2.5
3.4
18.1
24.1
30.1
36.1
–120
1.25
0.625
1.25
1.25
1.25
1.25
(Open)
3.4
–16
–32
–64
0
6.4
0.3125
15
0.156
30
10
(Open)
Not Used (Note 11)
Not Used
6912fa
3
LTC6912
ELECTRICAL CHARACTERISTICS
otherwise noted.
The
●
denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 5V, AGND = 2.5V, Gain = 1, R = 10k to midsupply point, unless
A
S
L
C, I GRADES
H GRADE
TYP
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
Specifications for Both the LTC6912-1 and the LTC6912-2
Total Supply Voltage (V )
●
2.7
10.5
2.7
10.5
V
S
Supply Current per Channel
Both Amplifiers Active (Gain = 1)
V = 2.7V, V = V = V
●
●
●
1.75
2.0
2.25
2.75
3.0
3.5
1.75
2.0
2.25
3.0
3.25
3.75
mA
mA
mA
S
INA
INB
AGND
V = 5V, V = V = V
S
INA
INB
AGND
V = ±5V, V = V = 0V
S
INA
INB
Supply Current per Channel
(Software Shutdown)
Both Amplifiers Inactive (State 1000)
V = 2.7V, V = V = V
●
●
●
150
200
265
255
325
750
150
200
265
280
350
750
µA
µA
µA
S
INA
INB
AGND
V = 5V, V = V = V
S
INA
INB
AGND
V = ±5V, V = V = 0V
S
INA
INB
Total-Supply Current
(Hardware Shutdown,
GN-16 Package Only)
V = 2.7V, V
= 2.43V
= 4.5V
= 4.5V
●
●
●
0.3
3.6
20
2
10
50
0.3
3.6
20
5
10
50
µA
µA
µA
S
SHDN
V = 5V, V
S
SHDN
V = ±5V, V
S
SHDN
Output Voltage Swing LOW
(Note 4)
V = 2.7V, R = 10k Tied to Midsupply Point
●
●
12
60
30
110
12
50
35
125
mV
mV
S
L
V = 2.7V, R = 500Ω Tied to Midsupply Point
S
L
V = 5V, R = 10k Tied to Midsupply Point
●
●
20
100
40
170
20
90
45
190
mV
mV
S
L
V = 5V, R = 500Ω Tied to Midsupply Point
S
L
V = ±5V, R = 10k Tied to 0V
●
●
30
190
50
260
30
80
60
290
mV
mV
S
L
V = ±5V, R = 500Ω Tied to 0V
S
L
Output Voltage Swing HIGH
(Note 4)
V = 2.7V, R = 10k Tied to Midsupply Point
●
●
10
50
20
80
10
50
25
90
mV
mV
S
L
V = 2.7V, R = 500Ω Tied to Midsupply Point
S
L
V = 5V, R = 10k Tied to Midsupply Point
●
●
15
90
30
160
15
80
35
175
mV
mV
S
L
V = 5V, R = 500Ω Tied to Midsupply Point
S
L
V = ±5V, R = 10k Tied to 0V
●
●
20
180
40
250
20
180
45
270
mV
mV
S
L
V = ±5V, R = 500Ω Tied to 0V
S
L
Output Short-Circuit Current
(Note 5)
V = 2.7V
V = ±5V
S
●
●
±27
±35
±27
±35
mA
mA
S
AGND Open-Circuit Voltage
(GN-16 Package Only)
V = Single 5V Supply, V
V = Single 5V Supply, V
S
= 0.5V
= 4.5V
●
2.45
2.5
2.65
2.55
2.45
2.5
2.65
2.55
V
V
S
SHDN
SHDN
AGND (Common Mode)
Input Voltage Range
V = Single 2.7V Supply
●
●
●
0.55
0.75
–4.3
1.6
3.65
3.2
0.55
0.75
–4.3
1.6
3.65
3.2
V
V
V
S
V = Single 5V Supply
S
V = ±5V
S
AGND Rejection (i.e., Common
Mode Rejection or CMRR)
V = 2.7V, V
V = ±5V, V
S
= 1.1V to 1.6V
= –2.5V to 2.5V
●
●
55
55
80
75
50
50
80
75
dB
dB
S
AGND
AGND
Power Supply Rejection Ratio (PSRR) V =2.7V to ±5V
●
60
80
57
80
dB
S
Slew Rate
Gain = 1
V = 5V, V
= V = 1.1V to 3.9V
OUTB
12
16
12
16
V/µs
V/µs
S
OUTA
V = ±5V, V
S
= V
= ±1.4V
OUTA
OUTB
Gain = 10 (–1), Gain = 8 (–2)
V = 5V, V = V = 1.1V to 3.9V
20
26
20
26
V/µs
V/µs
S
OUTA
OUTB
V = ±5V, V
= V
= ±1.4V
S
OUTA
OUTB
Signal Attenuation at Gain = 0 Setting Gain = 0 (Digital Inputs 0000),
f = 200kHz
●
●
–120
–120
dB
Signal Attenuation in Software
Shutdown
(State = 1000)
–120
–120
dB
6912fa
4
LTC6912
ELECTRICAL CHARACTERISTICS
otherwise noted.
The
●
denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 5V, AGND = 2.5V, Gain = 1, R = 10k to midsupply point, unless
A
S
L
C, I GRADES
TYP
H GRADE
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Specifications for Both the LTC6912-1 and the LTC6912-2
SHDN Input High Voltage
(GN-16 Package Only)
V = Single 2.7V
●
●
●
2.43
4.5
4.5
2.43
4.5
4.5
V
V
V
S
V = Single 5V
S
V = ±5V
S
SHDN Input Low Voltage
(GN-16 Package Only)
V = Single 2.7V
●
●
●
0.27
0.5
0.5
0.27
0.5
0.5
V
V
V
S
V = Single 5V
S
V = ±5V
S
SHDN Pin 5, Input High Current
(GN-16 Package Only)
V = Single 2.7V
0.2
1
1
0.2
1
1
µA
µA
µA
S
V = Single 5V
S
V = ±5V
S
SHDN Pin 5, Input Low Current
(GN-16 Package Only)
V = Single 2.7V
0.2
1
1
0.2
1
1
µA
µA
µA
S
V = Single 5V
S
V = ±5V
S
Specifications for the LTC6912-1 ONLY
Voltage Gain (Note 6)
V = 2.7V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.07
–0.11
5.94
13.85
19.7
19.55
25.75
33.5
0
0.07
0.07
6.08
14.05
20.1
20.05
26.1
34.05
40.0
–0.08
–0.13
5.93
0
0.07
0.07
6.08
14.05
20.1
20.05
26.1
34.05
40.0
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = 2.7V, Gain = 1, R = 500Ω
–0.02
6.01
13.95
19.93
19.85
25.94
33.8
–0.02
6.01
13.95
19.93
19.85
25.94
33.8
S
L
V = 2.7V, Gain = 2, R = 10k
S
L
V = 2.7V, Gain = 5, R = 10k
13.8
S
L
V = 2.7V, Gain = 10, R =10k
19.65
19.35
25.65
33.40
39.0
S
L
V = 2.7V, Gain = 10, R = 500Ω
S
L
V = 2.7V, Gain = 20, R = 10k
S
L
V = 2.7V, Gain = 50, R = 10k
S
L
V = 2.7V, Gain = 100, R = 10k
39.2
37.3
39.6
38.9
39.6
38.9
S
L
V = 2.7V, Gain = 100, R = 500Ω
39.7
36.20
39.7
S
L
V = 5V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.08
–0.11
5.95
13.8
19.8
19.6
25.78
33.5
39.3
37.75
0.01
–0.01
6.02
13.96
19.94
19.87
25.94
33.84
39.7
0.08
0.07
6.09
14.1
20.1
20.1
26.08
34.1
40.1
39.85
–0.09
–0.13
5.94
13.78
19.75
19.45
25.75
33.4
0.01
–0.01
6.02
13.96
19.94
19.87
25.94
33.84
39.7
0.08
0.07
6.09
14.1
20.1
20.1
26.08
34.1
40.1
39.85
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = 5V, Gain = 1, R = 500Ω
S
L
V = 5V, Gain = 2, R = 10k
S
L
V = 5V, Gain = 5, R = 10k
S
L
V = 5V, Gain = 10, R = 10k
S
L
V = 5V, Gain = 10, R = 500Ω
S
L
V = 5V, Gain = 20, R = 10k
S
L
V = 5V, Gain = 50, R = 10k
S
L
V = 5V, Gain = 100, R = 10k
39.1
36.6
S
L
V = 5V, Gain = 100, R = 500Ω
39.2
39.2
S
L
V = ±5V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.06
–0.10
5.95
0.01
0
0.08
0.08
6.09
–0.07
–0.11
5.94
13.79
19.75
19.58
25.73
33.60
39.25
37.6
0.01
0
0.08
0.08
6.09
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = ±5V, Gain = 1, R = 500Ω
S
L
V = ±5V, Gain = 2, R = 10k
6.02
13.96
19.94
19.91
25.95
33.87
39.8
39.5
6.02
13.96
19.94
19.91
25.95
33.87
39.8
39.5
S
L
V = ±5V, Gain = 5, R = 10k
13.8
14.1
14.1
S
L
V = ±5V, Gain = 10, R = 10k
19.78
19.68
25.78
33.65
39.4
20.08
20.05
26.08
34.05
40.2
20.08
20.05
26.08
34.05
40.2
S
L
V = ±5V, Gain = 10, R = 500Ω
S
L
V = ±5V, Gain = 20, R = 10k
S
L
V = ±5V, Gain = 50, R = 10k
S
L
V = ±5V, Gain = 100, R = 10k
S
L
V = ±5V, Gain = 100, R = 500Ω
38.6
39.9
39.9
S
L
6912fa
5
LTC6912
ELECTRICAL CHARACTERISTICS
otherwise noted.
The
●
denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 5V, AGND = 2.5V, Gain = 1, R = 10k to midsupply point, unless
A
S
L
C, I GRADES
TYP
H GRADE
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Specifications for the LTC6912-1 ONLY
Channel-to-Channel
Voltage Gain Match
(Note 6)
V = 2.7V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.1
–0.1
–0.1
–0.15
–0.15
–0.15
–0.15
–0.15
–0.2
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.15
0.15
0.15
0.2
–0.1
–0.1
–0.1
–0.15
–0.15
–0.2
–0.15
–0.15
–0.2
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.2
0.15
0.15
0.2
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = 2.7V, Gain = 1, R = 500Ω
S
L
V = 2.7V, Gain = 2, R = 10k
S
L
V = 2.7V, Gain = 5, R = 10k
S
L
V = 2.7V, Gain = 10, R = 10k
S
L
V = 2.7V, Gain = 10, R = 500Ω
S
L
V = 2.7V, Gain = 20, R = 10k
S
L
V = 2.7V, Gain = 50, R = 10k
S
L
V = 2.7V, Gain = 100, R = 10k
S
L
V = 2.7V, Gain = 100, R = 500Ω
–1.0
1.0
–1.5
1.5
S
L
V = 5V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.1
–0.1
–0.1
–0.15
–0.15
–0.15
–0.15
–0.15
–0.2
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.15
0.15
0.15
0.2
–0.1
–0.1
–0.1
–0.15
–0.15
–0.15
–0.15
–0.15
–0.2
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.15
0.15
0.15
0.2
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = 5V, Gain = 1, R = 500Ω
S
L
V = 5V, Gain = 2, R = 10k
S
L
V = 5V, Gain = 5, R = 10k
S
L
V = 5V, Gain = 10, R = 10k
S
L
V = 5V, Gain = 10, R = 500Ω
S
L
V = 5V, Gain = 20, R = 10k
S
L
V = 5V, Gain = 50, R = 10k
S
L
V = 5V, Gain = 100, R = 10k
S
L
V = 5V, Gain = 100, R = 500Ω
–0.8
0.8
–1.2
1.2
S
L
V = ±5V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.1
–0.1
–0.1
–0.15
–0.15
–0.15
–0.15
–0.15
–0.2
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.15
0.15
0.15
0.2
–0.1
–0.1
–0.1
–0.15
–0.15
–0.15
–0.15
–0.15
–0.2
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.15
0.15
0.15
0.2
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = ±5V, Gain = 1, R = 500Ω
S
L
V = ±5V, Gain = 2, R = 10k
S
L
V = ±5V, Gain = 5, R = 10k
S
L
V = ±5V, Gain = 10, R = 10k
S
L
V = ±5V, Gain = 10, R = 500Ω
S
L
V = ±5V, Gain = 20, R = 10k
S
L
V = ±5V, Gain = 50, R = 10k
S
L
V = ±5V, Gain = 100, R = 10k
S
L
V = ±5V, Gain = 100, R = 500Ω
–0.6
0.6
–0.9
0.9
S
L
Gain Temperature Coefficient
(Note 6)
V = 5V, Gain = 1, R = OPEN
2
2
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
S
L
V = 5V, Gain = 2, R = OPEN
–1.5
–11
–30
–40
–70
–140
–1.5
–11
–30
–40
–70
–140
S
L
V = 5V, Gain = 5, R = OPEN
S
L
V = 5V, Gain = 10, R = OPEN
S
L
V = 5V, Gain = 20, R = OPEN
S
L
V = 5V, Gain = 50, R = OPEN
S
L
V = 5V, Gain = 100, R = OPEN
S
L
Channel-to-Channel Gain
Temperature Coefficient Match
(Gain Specified in dB’s)
(Note 6)
V = 5V, Gain = 1, R = OPEN
1
1
1
1
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
S
L
V = 5V, Gain = 2, R = OPEN
S
L
V = 5V, Gain = 5, R = OPEN
0.2
–1
–1
–3
–3
0.2
–1
–1
–3
–3
S
L
V = 5V, Gain = 10, R = OPEN
S
L
V = 5V, Gain = 20, R = OPEN
S
L
V = 5V, Gain = 50, R = OPEN
S
L
V = 5V, Gain = 100, R = OPEN
S
L
Channel-to-Channel Isolation
(Note 7)
f = 200kHz,
V = 5V, Gain = 1, R = 10k
113
108
89
113
108
89
dB
dB
dB
S
L
V = 5V, Gain = 10, R = 10k
S
L
V = 5V, Gain = 100, R = 10k
S
L
6912fa
6
LTC6912
ELECTRICAL CHARACTERISTICS
otherwise noted.
The
●
denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 5V, AGND = 2.5V, Gain = 1, R = 10k to midsupply point, unless
A
S
L
C, I SUFFIXES
TYP
H SUFFIX
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Specifications for the LTC6912-1 ONLY
Offset Voltage Magnitude
(Internal Op-Amp, Note 8)
Gain = 1
●
0.125
2
0.125
3.5
mV
Offset Voltage Magnitude
Referred to INA or INB Pins
(Note 8)
Gain = 1
Gain = 10
●
●
0.25
0.14
3.5
2
0.25
0.14
6.5
4
mV
mV
Input Offset Voltage Drift,
Internal Op Amp
6
10
µV/°C
DC Input Resistance at
INA or INB Pins (Note 9)
DC V or V = 0V
INA INB
Gain = 0
State = 8, Software Shutdown
Gain = 1
Gain = 2
Gain = 5
Gain > 5
●
●
●
●
●
●
>10
>10
10
5
2
1
>10
>10
10
5
2
1
MΩ
MΩ
kΩ
kΩ
kΩ
kΩ
DC Input Resistance Drift at
INA or INB Pins (Note 9)
Gain = 1
Gain = 2
Gain = 5
Gain = 10
Gain = 20
Gain = 50
Gain = 100
85
90
100
120
130
150
190
95
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
100
110
130
140
160
200
DC Input Resistance Match
Gain = 1
Gain = 2
Gain = 5
Gain > 5
●
●
●
●
10
5
5
10
5
5
Ω
Ω
Ω
Ω
R -R
INA INB
5
5
DC Small Signal Output Resistance DC V or V = 0V
INA
INB
at OUT A or OUT B Pins
Gain = 0
0.4
0.7
1.0
1.9
3.4
6.4
15
0.4
0.7
1.0
1.9
3.4
6.4
15
Ω
Ω
Gain = 1
Gain = 2
Gain = 5
Ω
Ω
Gain = 10
Gain = 20
Gain = 50
Gain = 100
Ω
Ω
Ω
30
>1
30
>1
Ω
State = 8, Software Shutdown
●
●
MΩ
Gain Bandwidth Product
Gain = 100
18
33
50
16
33
50
MHz
Wideband Noise
(Referred to Input)
f = 1kHz to 200kHz
Gain = 0 (Output Noise only)
Gain = 1
8.9
15.6
11.1
8.3
7.4
7.0
8.9
15.6
11.1
8.3
7.4
7.0
µV
µV
µV
µV
µV
µV
µV
µV
RMS
RMS
RMS
RMS
RMS
RMS
RMS
RMS
Gain = 2
Gain = 5
Gain = 10
Gain = 20
Gain = 50
Gain = 100
6.7
6.3
6.7
6.3
6912fa
7
LTC6912
ELECTRICAL CHARACTERISTICS
otherwise noted.
The
●
denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 5V, AGND = 2.5V, Gain = 1, R = 10k to midsupply point, unless
A
S
L
C, I GRADES
TYP
H GRADE
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Specifications for the LTC6912-1 ONLY
Voltage Noise Density
(Referred to Input)
f = 50kHz
Gain = 1
Gain = 2
Gain = 5
Gain = 10
Gain = 20
Gain = 50
Gain = 100
35.6
24.8
19.1
16.7
16
15.4
15.1
35.6
24.8
19.1
16.7
16
15.4
15.1
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Total Harmonic Distortion
Gain = 10, f = 10kHz, V
= 1V
–90
0.003
–90
0.003
dB
%
IN
OUT
RMS
Gain = 10, f = 100kHz,
–82
0.008
–82
0.008
dB
%
IN
V
= 1V
OUT
RMS
Specifications for the LTC6912-2 ONLY
Voltage Gain (Note 6)
V = 2.7V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.07
–0.11
5.94
11.9
17.8
17.65
23.8
29.7
35.4
0
0.07
0.07
6.08
12.12
18.15
18.15
24.25
30.2
–0.08
–0.13
5.93
11.88
17.75
17.50
23.75
29.65
35.15
33.40
0
0.07
0.07
6.08
12.12
18.15
18.15
24.25
30.2
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = 2.7V, Gain = 1, R = 500Ω
–0.02
6.01
–0.02
6.01
S
L
V = 2.7V, Gain = 2, R = 10k
S
L
V = 2.7V, Gain = 4, R = 10k
12.02
18.0
17.94
24.01
30.0
35.8
35.3
12.02
18.0
17.94
24.01
30.0
35.8
35.3
S
L
V = 2.7V, Gain = 8, R = 10k
S
L
V = 2.7V, Gain = 8, R = 500Ω
S
L
V = 2.7V, Gain = 16, R =10k
S
L
V = 2.7V, Gain = 32, R = 10k
S
L
V = 2.7V, Gain = 64, R = 10k
36.2
36.0
36.2
36.0
S
L
V = 2.7V, Gain = 64, R = 500Ω
34.15
S
L
V = 5V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.08
–0.1
5.95
11.85
17.85
17.65
23.85
29.70
35.5
0
0.08
0.08
6.09
12.15
18.15
18.15
24.15
30.2
36.25
36.0
–0.09
–0.12
5.94
11.83
17.83
17.50
23.80
29.65
35.40
33.8
0
0.08
0.08
6.09
12.15
18.15
18.15
24.15
30.2
36.25
36.0
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = 5V, Gain = 1, R = 500Ω
–0.01
6.02
–0.01
6.02
S
L
V = 5V, Gain = 2, R = 10k
S
L
V = 5V, Gain = 4, R = 10k
12.02
18.01
17.96
24.02
30.02
35.9
12.02
18.01
17.96
24.02
30.02
35.9
S
L
V = 5V, Gain = 8, R = 10k
S
L
V = 5V, Gain = 8, R = 500Ω
S
L
V = 5V, Gain = 16, R = 10k
S
L
V = 5V, Gain = 32, R = 10k
S
L
V = 5V, Gain = 64, R = 10k
S
L
V = 5V, Gain = 64, R = 500Ω
34.6
35.6
35.6
S
L
V = ±5V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.06
–0.1
5.95
0.01
0
0.08
0.08
6.09
12.15
18.15
18.15
24.15
30.2
36.20
36.10
–0.07
–0.11
5.94
11.88
17.83
17.73
23.82
29.8
0.01
0
0.08
0.08
6.09
12.15
18.15
18.15
24.15
30.20
36.20
36.10
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = ±5V, Gain = 1, R = 500Ω
S
L
V = ±5V, Gain = 2, R = 10k
6.02
12.03
18.02
17.99
24.03
30.0
36.0
35.8
6.02
12.03
18.02
17.99
24.03
30.0
36.0
35.8
S
L
V = ±5V, Gain = 4, R = 10k
11.9
S
L
V = ±5V, Gain = 8, R = 10k
17.85
17.80
23.85
29.85
35.65
35.15
S
L
V = ±5V, Gain = 8, R = 500Ω
S
L
V = ±5V, Gain = 16, R = 10k
S
L
V = ±5V, Gain = 32, R = 10k
S
L
V = ±5V, Gain = 64, R = 10k
35.55
34.45
S
L
V = ±5V, Gain = 64, R = 500Ω
S
L
6912fa
8
LTC6912
ELECTRICAL CHARACTERISTICS
otherwise noted.
The
●
denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 5V, AGND = 2.5V, Gain = 1, R = 10k to midsupply point, unless
A
S
L
C, I GRADES
TYP
H GRADE
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Specifications for the LTC6912-2 ONLY
Channel-to-Channel
Voltage Gain Match
(Note 6)
V = 2.7V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.1
–0.1
–0.1
–0.15
–0.15
–0.15
–0.15
–0.15
–0.2
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.15
0.15
0.15
0.2
–0.1
–0.1
–0.1
–0.15
–0.15
–0.2
–0.15
–0.15
–0.2
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.2
0.15
0.15
0.2
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = 2.7V, Gain = 1, R = 500Ω
S
L
V = 2.7V, Gain = 2, R = 10k
S
L
V = 2.7V, Gain = 4, R = 10k
S
L
V = 2.7V, Gain = 8, R = 10k
S
L
V = 2.7V, Gain = 8, R = 500Ω
S
L
V = 2.7V, Gain = 16, R = 10k
S
L
V = 2.7V, Gain = 32, R = 10k
S
L
V = 2.7V, Gain = 64, R = 10k
S
L
V = 2.7V, Gain = 64, R = 500Ω
–0.7
0.7
–1.0
1.0
S
L
V = 5V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.1
–0.1
–0.1
–0.15
–0.15
–0.15
–0.15
–0.15
–0.15
–0.6
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.15
0.15
0.15
0.15
0.6
–0.1
–0.1
–0.1
–0.15
–0.15
–0.15
–0.15
–0.15
–0.15
–0.8
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.15
0.15
0.15
0.15
0.8
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = 5V, Gain = 1, R = 500Ω
S
L
V = 5V, Gain = 2, R = 10k
S
L
V = 5V, Gain = 4, R = 10k
S
L
V = 5V, Gain = 8, R = 10k
S
L
V = 5V, Gain = 8, R = 500Ω
S
L
V = 5V, Gain = 16, R = 10k
S
L
V = 5V, Gain = 32, R = 10k
S
L
V = 5V, Gain = 64, R = 10k
S
L
V = 5V, Gain = 64, R = 500Ω
S
L
V = ±5V, Gain = 1, R = 10k
●
●
●
●
●
●
●
●
●
●
–0.1
–0.1
–0.1
–0.15
–0.15
–0.15
–0.15
–0.15
–0.15
–0.4
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.15
0.15
0.15
0.15
0.4
–0.1
–0.1
–0.1
–0.15
–0.15
–0.15
–0.15
–0.15
–0.15
–0.6
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
±0.02
0.1
0.1
0.1
0.15
0.15
0.15
0.15
0.15
0.15
0.6
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
S
L
V = ±5V, Gain = 1, R = 500Ω
S
L
V = ±5V, Gain = 2, R = 10k
S
L
V = ±5V, Gain = 4, R = 10k
S
L
V = ±5V, Gain = 8, R = 10k
S
L
V = ±5V, Gain = 8, R = 500Ω
S
L
V = ±5V, Gain = 16, R = 10k
S
L
V = ±5V, Gain = 32, R = 10k
S
L
V = ±5V, Gain = 64, R = 10k
S
L
V = ±5V, Gain = 64, R = 500Ω
S
L
Gain Temperature Coefficient
(Note 6)
V = 5V, Gain = 1, R = OPEN
2
–4
–10
–24
–30
–40
–120
2
–4
–10
–24
–30
–40
–120
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
S
L
V = 5V, Gain = 2, R = OPEN
S
L
V = 5V, Gain = 4, R = OPEN
S
L
V = 5V, Gain = 8, R = OPEN
S
L
V = 5V, Gain = 16, R = OPEN
S
L
V = 5V, Gain = 32, R = OPEN
S
L
V = 5V, Gain = 64, R = OPEN
S
L
Channel-to-Channel Gain
Temperature Coefficient Match
(Note 6)
V = 5V, Gain = 1, R = OPEN
0
–0.5
0
0
–0.5
0
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
S
L
V = 5V, Gain = 2, R = OPEN
S
L
V = 5V, Gain = 4, R = OPEN
S
L
V = 5V, Gain = 8, R = OPEN
0
0
S
L
V = 5V, Gain = 16, R = OPEN
–1
–4
–4
–1
–4
–4
S
L
V = 5V, Gain = 32, R = OPEN
S
L
V = 5V, Gain = 64, R = OPEN
S
L
Channel-to-Channel Isolation
(Note 7)
f = 200kHz,
V = 5V, Gain = 1, R = 10k
117
110
92
117
110
92
dB
dB
dB
S
L
V = 5V, Gain = 8, R = 10k
S
L
V = 5V, Gain = 64, R = 10k
S
L
Offset Voltage Magnitude
(Internal Op-Amp, Note 8)
Gain = 1
●
0.125
2
0.125
3.5
mV
6912fa
9
LTC6912
ELECTRICAL CHARACTERISTICS
otherwise noted.
The
●
denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 5V, AGND = 2.5V, Gain = 1, R = 10k to midsupply point, unless
A
S
L
C, I GRADES
TYP
H GRADE
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Specifications for the LTC6912-2 ONLY
Offset Voltage Magnitude
Referred to INA or INB Pins
(Note 8)
Gain = 1
Gain = 8
●
●
0.25
0.14
3.5
2
0.25
0.14
6.5
4
mV
mV
Input Offset Voltage Drift,
Internal Op Amp
6
10
µV/°C
DC Input Resistance at
INA or INB Pins (Note 9)
DC V or V = 0V
INA INB
Gain = 0
State = 8, Software Shutdown
Gain = 1
Gain = 2
Gain = 4
Gain > 4
●
●
●
●
●
●
>10
>10
10
5
2.5
>10
>10
10
5
2.5
MΩ
MΩ
kΩ
kΩ
kΩ
kΩ
1.25
1.25
DC Input Resistance Drift at
INA or INB Pins (Note 9)
Gain = 1
85
90
95
120
130
140
170
95
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
100
105
130
140
150
180
DC Input Resistance Match
Gain = 1
Gain = 2
Gain = 4
Gain > 4
●
●
●
●
10
5
5
10
5
5
Ω
Ω
Ω
Ω
R -R
INA INB
5
5
DC Small Signal Output Resistance DC V or V = 0V
INA
INB
at OUT A or OUT B Pins
Gain = 0
0.4
0.7
1.0
1.9
3.4
6.4
15
0.4
0.7
1.0
1.9
3.4
6.4
15
Ω
Ω
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Ω
Ω
Ω
Ω
Ω
30
>1
30
>1
Ω
State = 8, Software Shutdown
●
●
MΩ
Gain Bandwidth Product
Gain = 64
17
30
50
15
30
50
MHz
Wideband Noise
(Referred to Input)
f = 1kHz to 200kHz
Gain = 0 (Output Noise Only)
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
8.1
13.8
9.6
7.5
6.4
6.0
5.8
5.6
8.1
13.8
9.6
7.5
6.4
6.0
5.8
5.6
µV
µV
µV
µV
µV
µV
µV
µV
RMS
RMS
RMS
RMS
RMS
RMS
RMS
RMS
6912fa
10
LTC6912
ELECTRICAL CHARACTERISTICS
otherwise noted.
The
●
denotes the specifications that apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 5V, AGND = 2.5V, Gain = 1, R = 10k to midsupply point, unless
A
S
L
C, I GRADES
TYP
H GRADE
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
Specifications for the LTC6912-2 ONLY
Voltage Noise Density
(Referred to Input)
f = 50kHz
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
31.1
22.8
17
14.6
13.2
12.9
12.6
31.1
22.8
17
14.6
13.2
12.9
12.6
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Total Harmonic Distortion
Gain = 8, f = 10kHz, V
= 1V
RMS
–84
0.006
–84
0.006
dB
%
IN
OUT
Gain = 8, f = 100kHz, V
= 1V
RMS
–82
0.008
–82
0.008
dB
%
IN
OUT
U
U
SERIAL I TERFACE SPECIFICATIO S
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital I/O Logic Levels, All Digital I/O Voltage Referenced to DGND
V
V
V
V
Digital Input High Voltage
Digital Input Low Voltage
Digital Output High Voltage
Digital Output Low Voltage
●
●
●
●
2
V
V
V
V
IH
0.8
0.3
IL
+
Sourcing 500µA
Sinking 500µA
V – 0.3
OH
OL
+
–
Serial Interface Timing, V = 2.7V ~ 4.5V, V = 0V (Note 10)
t
t
t
t
t
t
t
t
t
D
D
Valid to CLK Setup
Valid to CLK Hold
●
●
●
●
●
●
●
●
●
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
7
8
9
IN
IN
CLK Low
100
100
60
CLK High
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
60
30
D
OUT
Output Delay
C = 15pF
L
125
CLK Low to CS/LD Low
0
+
–
Serial Interface Timing, V = 4.5V ~ 5.5V, V = 0V (Note 10)
t
t
t
t
t
t
t
t
t
D
D
Valid to CLK Setup
Valid to CLK Hold
●
●
●
●
●
●
●
●
●
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
7
8
9
IN
IN
CLK Low
50
50
40
40
20
CLK High
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
D
OUT
Output Delay
C = 15pF
L
85
CLK Low to CS/LD Low
0
6912fa
11
LTC6912
U
U
SERIAL I TERFACE SPECIFICATIO S
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Interface Timing, Dual ±4.5V ~ ±5.5V Supplies (Note 10)
t
t
t
t
t
t
t
t
t
D
D
Valid to CLK Setup
Valid to CLK Hold
●
●
●
●
●
●
●
●
●
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
7
8
9
IN
IN
CLK High
50
50
40
40
20
CLK Low
CS/LD Pulse Width
LSB CLK to CS/LD
CS/LD Low to CLK
D
OUT
Output Delay
C = 15pF
L
85
CLK Low to CS/LD Low
0
t
t
t
t
t
t
7
1
2
4
3
6
CLK
t
9
D7 • • • D4
D3
D2
D31
D0
D3
D
IN
t
5
CS/LD
t
8
D
D7 • • • D4
CURRENT BYTE
D4
D3
D2
D31
D0
D3
OUT
PREVIOUS BYTE
6912 TD
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 7: Channel-to-channel isolation is measured by applying a 200kHz
input signal to one channel so that its output varies 1V , and measuring
RMS
the output voltage RMS of the other channel relative to AGND with its
Note 2: The LTC6912-1C and LTC6912-1I are guaranteed functional over
the operating temperature range of –40°C to 85°C. The LTC6912-1H is
guaranteed functional over the operating temperature range of –40°C to
125°C.
input tied to AGND. Isolation is calculated:
10
Isolation = 20 • log (V
/V
) or
)
B
OUTA OUTB
10
Isolation = 20 • log (V
/V
OUTB OUTA
A
Note 3: The LTC6912-1C is guaranteed to meet specified performance
from 0°C to 70°C. The LTC6912-1C is designed, characterized and
expected to meet specified performance from – 40°C to 85°C but is not
tested or QA sampled at these temperatures. The LTC6912-1I is
guaranteed to meet specified performance from –40°C to 85°C. The
LTC6912-1H is guaranteed to meet specified performance from –40°C to
125°C.
Note 4: Output voltage swings are measured as differences between the
output and the respective supply rail.
Note 5: Extended operation with output shorted may cause junction
temperature to exceed the 150°C limit for GN package and 125°C for a
DFN package is not recommended.
High channel-to-channel isolation is strongly dependent on proper circuit
layout. See Applications Information.
Note 8: Offset voltage referred to the INA or INB input is (1 + 1/|GAIN|)
times the offset voltage of the internal op amp, where GAIN is the nominal
gain magnitude. The typical offset voltage values are for 25°C only. See
Applications Information.
Note 9: Input resistance can vary by approximately ±30% part-to-part at a
given gain setting.
Note 10: Guaranteed by design, not subject to test.
Note 11: States 13, 14 and 15 (binary 11xx) are not used. Programming a
channel to states 8 or higher will configure that particular channel into a
low power shutdown state. In addition, programming a channel into
state 15 (binary 1111) will cause that particular channel to draw up to
20mA of supply current and is not recommended.
Note 6: Gain is measured with a large signal DC test using an output
excursion between approximately 30% and 70% of supply voltage.
6912fa
12
LTC6912
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-1 –3dB Bandwidth vs
Gain Setting
LTC6912-1 Channel Gain
Matching vs Frequency
LTC6912-1 Frequency Response
6
1
50
40
30
20
10
0
0.10
0.05
V
V
=
IN
5V
V
=
IN
5V
= 10mV
RMS
V
= 10mV
RMS
S
S
IN
= 10mV
V
RMS
GAIN OF 100
GAIN OF 50
GAIN OF 100
GAIN OF 10
GAIN OF 1
V
= 5V
S
0
GAIN OF 20
GAIN OF 10
GAIN OF 5
–0.05
–0.10
–0.15
–0.20
V
= 2.7V
S
GAIN OF 2
GAIN OF 1
0.1
–10
1
10
100
1000
FREQUENCY (kHz)
10000
1
10
GAIN (V/V)
100
1
10
100
FREQUENCY (Hz)
1000
10000
6912 G01
6912 G02
6912 G03
LTC6912-1 Noise Density vs
Frequency
LTC6912-1 Channel Isolation vs
Frequency
LTC6912-1 Power Supply
Rejection vs Frequency
100
10
1
125
120
115
110
105
100
95
90
80
70
60
50
40
30
20
10
0
V
= 5V
V
V
=
OUT
5V
= 1V
S
S
GAIN = 1
RMS
GAIN OF 1
GAIN OF 1
GAIN OF 10
GAIN OF 100
+SUPPLY
–SUPPLY
GAIN OF 10
GAIN OF 100
90
V
=
2.5V
S
A
85
T
= 25°C
INPUT REFERRED
80
100
1000
1
10
FREQUENCY (kHz)
100
1
10
100
1000
10000
FREQUENCY (kHz)
FREQUENCY (kHz)
6912 G04
6912 G05
6912 G06
LTC6912-1 THD Plus Noise vs
Input Voltage
LTC6912-1 Distortion vs
Frequency with Light Loading
LTC6912-1 Distortion vs
Frequency with Heavy Loading
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–50
–55
–60
–65
–70
–75
–80
–85
–90
R
= 10k
2.5V
= 1V
L
GAIN OF 100
V
V
=
GAIN OF 100
S
OUT
(2.83)V
P-P
RMS
GAIN OF 10
GAIN OF 100
GAIN
OF 10
GAIN OF 1
GAIN OF 10
V
= 5V
= 10k
S
L
GAIN OF 1
150
R
= 500Ω
L
R
V
V
=
2.5V
= 1V
S
OUT
f
= 1kHz
BW = 22kHz
IN
GAIN OF 1
(2.83)V
150
RMS
P-P
0.001
0.01
0.1
1
)
10
0
50
100
FREQUENCY (kHz)
200
0
50
100
200
INPUT VOLTAGE (V
FREQUENCY (kHz)
P-P
6912 G07
6912 G08
6912 G09
6912fa
13
LTC6912
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-1 Hardware Shutdown
Total Supply Current vs
Temperature
LTC6912-1 Software Shutdown
Total Supply Current vs
Temperature
LTC6912-1 Total Supply Current
vs Temperature (Both Amplifiers
Active)
700
600
500
400
300
200
100
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
HARDWARE SHUTDOWN (GN-16 ONLY)
BOTH AMPLIFIERS IN
SOFTWARE SHUTDOWN
BOTH AMPLIFIERS
PROGRAMMED TO GAIN = 1
L
V
= 5V
S
V
S
= 5V
R
= 10k
R = 10k
L
V
= 5V
S
10
1
V
= 5V
S
V
S
= 5V
V
S
= 5V
V
= 2.7V
S
V
= 3V
S
V
= 2.7V
25
S
V
= 2.7V
25
S
0.1
50
100 125
–50 –25
0
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
50
75 100 125
–50 –25
0
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
6912 G10
6912 G11
6912 G12
LTC6912-1 Gain Shift vs
Temperature (Heavy Load)
LTC6912-1 Gain Shift vs
Temperature (Light Load)
LTC6912-2
Frequency Response
0.5
0
0.10
0.05
40
30
20
10
0
V
V
=
IN
5V
V
= 5V
GAIN OF 64
GAIN OF 32
GAIN OF 16
GAIN OF 8
GAIN OF 4
GAIN OF 2
GAIN OF 1
S
V
= 5V
S
L
S
L
= 10mV
R
= 10k
RMS
R
= 500Ω
GAIN OF 1
GAIN OF 1
0
GAIN OF 10
–0.05
–0.10
–0.15
–0.20
–0.25
GAIN OF 10
–0.5
–1.0
–1.5
GAIN OF 100
GAIN OF 100
–10
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
1
10
100
1000
FREQUENCY (kHz)
10000
6912 G14a
6912 G13
6912 G14
LTC6912-2 Channel Isolation vs
Frequency
LTC6912-2 Channel Gain
Matching vs Frequency
LTC6912-2 –3dB Bandwidth vs
Gain Setting
8.0
0.100
125
120
115
110
105
100
95
V
V
=
5V
= 10mV
V
IN
= 10mV
GAIN = 1
V
V
= 5V
S
OUT
S
RMS
V
V
=
5V
S
S
6.0
= 1V
IN
= 10kΩ
RMS
RMS
0.075
0.050
0.025
0
R
L
= 2.7V
4.0
GAIN = 8
GAIN OF 1
GAIN OF 8
2.0
–0.025
–0.050
–0.075
–0.100
GAIN = 64
GAIN OF 64
1.0
0.8
90
0.6
85
0.4
80
1
10
100
100
1000
1
10000
10
100
FREQUENCY (kHz)
1000
GAIN (V/V)
FREQUENCY (kHz)
6912 G16
6912 G17
6912 G15
6912fa
14
LTC6912
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-2 Distortion vs
Frequency with Light Loading
(R = 10k)
LTC6912-2 Power Supply
Rejection vs Frequency
LTC6912-2 Noise Density vs
Frequency
L
100
10
1
90
80
70
60
50
40
30
20
10
0
–50
–55
–60
–65
–70
–75
–80
–85
–90
V
= 5V
V
T
=
2.5V
V
V
=
OUT
2.5V
= 1V
S
S
A
S
GAIN = 1
= 25°C
(2.83V )
P-P
RMS
INPUT REFERRED
GAIN = 1
GAIN = 8
GAIN = 64
GAIN = 64
+SUPPLY
–SUPPLY
GAIN = 8
GAIN = 1
1
10
FREQUENCY (kHz)
100
0
50
100
FREQUENCY (kHz)
150
200
1
10000
10
100
1000
FREQUENCY (kHz)
6912 G19
6912 G20
6912 G18
LTC6912-2 Distortion vs
LTC6912-2 Hardware Shutdown
Total Supply Current vs
Temperature
Frequency with Heavy Loading
LTC6912-2 THD + Noise vs
Input Voltage
(R = 500Ω)
L
–30
–40
–50
–60
–70
–80
–90
–30
–40
–50
–60
–70
–80
–90
–100
HARDWARE SHUTDOWN (GN-16 ONLY)
V
V
=
OUT
2.5V
= 1V
S
(2.83V )
P-P
RMS
V
= 5V
S
GAIN = 64
10
1
GAIN = 64
GAIN = 8
V
S
= 5V
GAIN = 8
GAIN = 1
V
= 3V
S
GAIN = 1
V
= 2.7V
25
S
V
= 5V
= 10k
= 1kHz
S
L
R
f
IN
0.1
50
100 125
0
50
100
FREQUENCY (kHz)
150
200
0.001
0.01
0.1
1
10
–50 –25
0
75
INPUT VOLTAGE (V
)
P-P
TEMPERATURE (°C)
6912 G21
6912 G22
6912 G22A
LTC6912-2 Software Shutdown
Total Supply Current vs
Temperature
LTC6912-2 Total Supply Current
vs Temperature (Both Amplifiers
Active)
LTC6912-2 Gain Shift vs
Temperature (Light Load)
800
700
600
500
400
300
200
100
6.0
5.5
5.0
4.5
4.0
3.5
3.0
0.100
0.075
0.050
0.025
0
BOTH AMPLIFIERS
BOTH AMPLIFIERS
ACTIVE : GAIN = 1
V
= 5V
S
L
PROGRAMMED TO STATE = 8
R
= 10k
R
L
= 10k
R
= 10k
L
V
S
=
5V
V
S
= 5V
GAIN = 1
GAIN = 8
–0.025
–0.050
–0.075
–0.100
–0.125
–0.150
–0.175
–0.200
V
S
= 5V
V
S
= 5V
V
S
= 2.7V
V
S
= 2.7V
GAIN = 64
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
6912 G23
6912 G24
6912 G25
6912fa
15
LTC6912
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC6912-2 Gain Shift vs
Temperature (Heavy Load)
0.25
V
= 5V
= 500
S
L
R
GAIN = 1
0
–0.25
–0.50
–0.75
–1.00
GAIN = 8
GAIN = 64
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
6912 G26
U
U
U
PI FU CTIO S
INA, INB: Analog Inputs. The input signal to the A channel
amplifier of the LTC6912-X is the voltage difference be-
tweentheINApinandAGNDpin. Likewise, theinputsignal
to the B channel amplifier of the LTC6912-X is the voltage
difference between the INB pin and AGND pin. The INA (or
INB) pin connects internally to a digitally controlled resis-
tance whose other end is a current summing point at the
same potential as the AGND pin (Figure 1). At unity gain,
the value of this input resistance is approximately 10kΩ
and the INA (or INB) pin voltage range is rail-to-rail (V+ to
V–). At gain settings above unity, the input resistance falls.
The linear input range at INA and INB also falls inversely
proportional to the programmed gain. Tables 1 and 2
summarizethisbehavior.Thehighergainsaredesignedto
boost lower level signals with good noise performance. In
the “zero” gain state (state = 0), or in software shutdown
(state = 8) analog switches disconnect the INA or INB pin
internally and this pin presents a very high input resis-
tance. In the “zero” gain state (state = 0), the input may
vary from rail to rail but the output is insensitive to it and
is forced to the AGND potential. Circuitry driving the INA
and INB pins must consider the LTC6912-X’s input resis-
tance, its process variance, and the variation of this
resistancefromgainsettingtogainsetting.Signalsources
with significant output resistance may introduce a gain
error as the source’s output resistance and the LTC6912-
X’s input resistance forms a voltage divider. This is espe-
cially true at higher gain settings where the input resis-
tance is the lowest.
In single supply voltage applications, the LTC6912-X’s DC
ground reference for both input and output is AGND, not
V–. With increasing gains, the LTC6912-X’s input voltage
range for an unclipped output is no longer rail-to-rail but
diminishes inversely to gain, centered about the AGND
potential.
NC
1
2
16
NC
INA
INPUT R ARRAY
FEEDBACK R ARRAY
–
+
V
OUT A
15
14
MOS INPUT
100k
100k
+
OP AMP
–
V
3
4
AGND
INB
MOS INPUT
OP AMP
+
–
OUT B
13
–
V
+
12
11
V
INPUT R ARRAY
CHANNEL A
FEEDBACK R ARRAY
CHANNEL B
NC
LOWER
NIBBLE
UPPER
NIBBLE
8-BIT
LATCH
DGND
10
9
+
V
D
OUT
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
5
6
7
8
SHDN
CS/LD
DATA
CLK
8-BIT
SHIFT-REGISTER
6912 BD
Figure 1. GN-16 Block Diagram
6912fa
16
LTC6912
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AGND: Analog Ground. The AGND pin is at the midpoint of
an internal resistive voltage divider, developing a potential
halfway between the V+ and V– pins. In normal operation,
the AGND pin has an equivalent input resistance of nomi-
nally 50k (Figure 1). In order to reduce the quiescent
supply current in hardware shutdown (SHDN pin pulled to
V+, GN-16 only), the equivalent series resistance of this
pin significantly increases (to a value on the order of
800kΩ with 5V supplies, but is highly supply voltage,
temperature, and process dependent). AGND is the
noninverting input to both the internal channel A and
channel B amplifiers. This makes AGND the ground refer-
ence voltage for the INA, INB, OUTA, and OUTB pins.
Recommended analog ground plane connection depends
on how power is applied to the LTC6912-X (See Figures 2,
3, and 4). Single power supply applications typically use
V– for the system signal ground. The analog ground plane
in single-supply applications should therefore tie to V–,
andtheAGNDpinshouldbebypassedtothisgroundplane
by a high quality capacitor of at least 0.1µF (Figure 2). The
AGND pin provides an internal analog reference voltage at
half the V+ supply voltage. Dual supply applications with
symmetricalsupplies(suchas±5V)haveanaturalsystem
groundplanepotentialofzerovolts,inwhichtheAGNDpin
can be directly tied to, making the zero volt ground plane
the input and output reference voltage for the LTC6912-X
(Figure3). Finally, ifdualasymmetricalpowersuppliesare
used, the supply ground is still the natural ground plane
voltage. To maximize signal swing capability with an
asymmetricalsupply,however,itisoftendesirabletorefer
the LTC6912-X’s analog input and output to a voltage
equidistantfromthetwosupplyrailsV+ andV–.TheAGND
pin will provide such a potential when open-circuited and
bypassed with a capacitor (Figure 4). In noise sensitive
applications where AGND does not tie directly to a ground
plane, as in Figures 2 and 4, it is important to AC-bypass
the AGND pin. Otherwise channel to channel isolation is
degraded, and wideband noise will enter the signal path
from the thermal noise of the internal voltage divider
resistors which present a Thévenin equivalent resistance
of approximately 50kΩ. This noise can reduce SNR by at
least 15dB at high gain settings. An external capacitor
from AGND to the ground plane, whose impedance is well
below 50kΩ at frequencies of interest, will filter and
suppress this noise. A 0.1µF high quality capacitor is
effective for frequencies down to 1kHz. Larger capacitors
will extend this suppression to lower frequencies. This
issue does not arise in dual supply applications because
the AGND pin ties directly to ground. In applications
requiring an analog ground reference other than half the
total supply voltage, the user can override the built-in
analog ground reference by tying the AGND pin to a
referencevoltagewiththeAGNDvoltagerangespecifiedin
theElectricalCharacteristicsTable.TheAGNDpinwillload
the external reference with approximately 50kΩ returned
to the half-supply potential. AGND should still be capaci-
tively bypassed to a ground plane as noted above. Do not
connect the AGND pin to the V– pin.
ANALOG GROUND PLANE
ANALOG GROUND PLANE
+
V
REFERENCE
1
2
3
4
5
6
7
8
16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2
15
0.1µF
0.1µF
≥0.1µF
LTC6912-X
LTC6912-X
–
+
14 V
13
SINGLE-POINT
SYSTEM GND
0.1µF
SINGLE-POINT
SYSTEM GND
12 V
11
+
V
SERIAL
INTERFACE
10
SERIAL
INTERFACE
9
DIGITAL GROUND PLANE
DIGITAL GROUND PLANE
6912 F03
6912 F02
Figure 2. Single Supply Ground Plane Connection
Figure 3. Symmetrical Dual Supply Ground Plane Connection
6912fa
17
LTC6912
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ANALOG GROUND PLANE
16
DIN: TTL/CMOS Compatible Logic Serial Data Input. The
serial interface is synchronously loaded MSB first via DIN
on the rising edge of CLK with CS/LD asserted low.
+
–
V
+ V
2
REFERENCE
1
2
3
4
5
6
7
8
15
≥0.1µF
0.1µF
LTC6912-X
–
14 V
13
CLK: TTL/CMOS Compatible Logic Input. With CS/LD
asserted low, the clock synchronizes the loading of the
serial shift register on its rising and falling edges. Data is
shiftedinatDIN ontherisingedgeofCLKandisshiftedout
on DOUT on the falling edge of CLK.
0.1µF
SINGLE-POINT
SYSTEM GND
+
12 V
11
10
9
SERIAL
INTERFACE
DIGITAL GROUND PLANE
6912 F04
DOUT: TTL/CMOS Compatible Logic Output. The MSB of
the shift register contents is shifted out at DOUT on the
fallingedgeofCLK. TheoutputatDOUT swingsbetweenV+
and DGND, and is rated to drive approximately 15pF.
Figure 4. Asymmetrical Dual Supply Ground Plane Connection
SHDN (GN-16 ONLY): CMOS Compatible Logic Hardware
ShutdownInput.TheLTC6912-Xhastwoshutdownmodes.
One is a software shutdown state which can be software
programmed into either Channel A, Channel B, or both.
Thesoftwareshutdown, whenprogrammedtoaparticular
channel (state = 8), will disable that channel’s amplifier
and tri-state open its analog input and analog output. The
serial interface, however is still active. A hardware shut-
down occurs when the SHDN pin is pulled to the positive
rail. In this condition, both amplifiers and serial interface
are disabled. The SHDN pin is allowed to swing from V– to
10.5VaboveV–,regardlessofV+ solongasthelogiclevels
meettheminimumrequirementsspecifiedintheElectrical
Characteristics table. The SHDN pin is a high impedance
CMOS logic input, but has a small pull-down current
source (<10µA) which will force SHDN low if the logic
input is externally floated. On initial power up (with SHDN
open), or coming out of the hardware shutdown mode
(pulling SHDN to V–), both amplifiers are reset into the
power-onresetstate(softwareshutdownmode, state=8)
for both channels.
DGND:DigitalGround:TheDGNDpindefinesthepotential
from which LOGIC levels VIH and VIL for the 3-wire serial
digital interface are referenced. The recommended con-
nection of DGND depends on how power is applied to the
LTC6912 (See Figures 2, 3, and 4). (CAVEAT: Under no
conditions is DGND to exceed either supply pins V+ and
V–, which could result in damage to the IC if not current
limited.)
Single power supply applications typically use V– for the
systemsignalground.ThepreferredconnectionforDGND
is therefore V– (See Figure 2).
Dual supply applications with symmetrical supplies (such
as ±5V) have a natural system ground potential of zero
volts, in which the DGND pin can be tied to, making the
zero volt ground plane the logic reference (Figure 3).
Finally, if dual asymmetrical power supplies are used, the
system ground is still the natural ground plane voltage.
V–, V+: Power Supply Pins. The V+ and V– pins should be
bypassed with 0.1µF capacitors to an adequate analog
ground plane using the shortest possible wiring. Electri-
cally clean supplies and a low impedance ground are
important for the high dynamic range available from the
LTC6912 (see further details under the AGND pin descrip-
tion). Low noise linear power supplies are recommended.
Switching power supplies require special care to prevent
switching noise coupling into the signal path, reducing
dynamic range.
CS/LD: TTL/CMOS Compatible Logic Input. When this pin
is asserted low, the CLK pin is enabled, and the 8-bit shift
register serially shifts the shift register contents and
whatever data is present on the DIN pin into the shift
register on the rising edge of CLK. On the rising edge of
CS/LD, the contents of the shift register data are loaded
into the eight bit latch which configures the gain state of
both channel A and channel B amplifiers. A logic high on
CS/LD inhibits the CLK signal internally to the IC.
6912fa
18
LTC6912
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OUT A, OUT B: Analog Output. These pins are the output
of the A and B channel amplifiers respectively. Each
operational amplifier can swing rail-to-rail (V+ to V–) as
specified in the Electrical Characteristics table. For best
performance, loading the output as lightly as possible will
minimize signal distortion and gain error. The Electrical
Characteristics table shows performance at output cur-
rentsupto10mA, andthecurrentlimitswhichoccurwhen
the output is shorted midsupply at 2.7V and ±5V supplies.
Output current above 10mA is possible but current-limit-
ing circuitry will begin to affect amplifier performance at
approximately 20mA. Long-term operation above 20mA
output is not recommended. Do not exceed maximum
junction temperature of 150°C for a GN and 125°C for a
DFN package. The output will drive capacitive loads up to
50pF. Capacitances higher than 50pF should be isolated
by a series resistor (10Ω or higher).
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APPLICATIO S I FOR ATIO
Functional Description
Description of the 3-Wire SPI Interface
The LTC6912-X is a small outline, wideband, inverting
two-channel amplifier with voltage gains that are indepen-
dently programmable. Each delivers a choice of eight
voltage gains, configurable through a 3-wire serial digital
interface, which accepts TTL or CMOS logic levels (See
Figure 5). Tables 1 and 2 list the nominal gains for the
LTC6912-1 and LTC6912-2 respectively. Gain control
within the amplifier occurs by switching resistors from a
matched array in or out of a closed-loop op amp circuit
using MOS analog switches (Figure 1). The bandwidths of
the individual amplifiers depend on gain setting. The
Typical Performance Characteristics section shows mea-
sured frequency responses.
Gain control of each amplifier is independently program-
mable using the 3-wire SPI interface (see Figure 5). Logic
levels for the LTC6912 3-wire serial interface are TTL/
CMOS compatible. When CS/LD is low, the serial data on
DIN is shifted into an 8-bit shift-register on the rising edge
of the clock, with the MSB transferred first. Serial data on
DOUT isshiftedoutontheclock’sfallingedge.Arisingedge
on CS/LD will latch the shift-register’s contents into an 8-
bit D-latch and disable the clock internally on the IC. The
upper nibble of the D-latch (4 most significant bits),
configure the gain for the B-channel amplifier. The lower
nibble of the D-latch (4 least significant bits), configures
the gain for the A-channel amplifier. Tables 1 and 2 detail
thenominalgainsandrespectivegaincodes.Caremustbe
taken to ensure CLK is taken low before CS/LD is pulled
low to avoid an extra internal clock pulse to the input of the
8-bit shift-register (See Figure 5).
CHANNEL A
CHANNEL B
RESET
8-BIT LATCH
UPPER NIBBLE
LE
LOWER NIBBLE
DOUT is active in all states, therefore DOUT cannot be
“wire-OR’d” to other SPI outputs.
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
LSB MSB
D
IN
An LTC6912 may be daisy-chained with other LTC6912s
or other devices having serial interfaces by connecting the
DOUT to the DIN of the next chip while CLK and CS/LD
remain common to all chips in the daisy chain. The serial
data is clocked to all the chips then the CS/LD signal is
pulled high to update all of them simultaneously. Figure 6
showsanexampleoftwoLTC6912sinadaisychainedSPI
8-BIT
CLK
CS/LD
SHDN
SHIFT-REGISTER
D
OUT
RESET
6912 F05
Figure 5. Serial Digital Interface Block Diagram
6912fa
19
LTC6912
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APPLICATIO S I FOR ATIO
configuration. It is recommended the serial interface sig-
nals should remain idle in between data transfers in order
to minimize digital noise coupling into the analog path.
Timing Constraints
Settling time in the CMOS gain-control logic is typically
several nanoseconds and is faster than the analog signal
path. When the amplifier gain changes, the limiting timing
is analog. As with any programmable-gain amplifier, each
gain change causes an output transient as the amplifier’s
output moves, with finite speed, toward a differently
scaled version of the input signal. The LTC6912-X analog
path settles with a characteristic time constant or time
scale, τ, that is roughly the standard value for a first order
band limited response:
Power On Reset
On the initial application of power, the power on reset
state of both amplifiers is low power software shutdown
(state = 8) (see Tables 1 and 2). In this state, both analog
amplifiers are disabled and have their inputs and outputs
opened. This will facilitate the application of using the
device as a 2:1 analog MUX, in that the amplifier’s outputs
may be wired-OR together and the LTC6912 can alter-
nately select between A and B channels. Care must be
taken if the outputs are wired-OR’d to ensure the software
shutdown state (state = 8) is always programmed in one
of the two channels.
τ = 0.35/f–3dB
See the –3dB BW vs Gain Setting graph in the Typical
Performance Characteristics section.
ANALOG GROUND PLANE
1
2
3
4
5
6
7
8
16
1
2
3
4
5
6
7
8
16
SINGLE-POINT
SYSTEM GND
15
15
0.1µF
0.1µF
0.1µF
0.1µF
LTC6912-X
LTC6912-X
–
+
–
+
14 V
13
14 V
13
12 V
11
12 V
11
SHDN
SHDN
CS/LD
DATA
CLK
CS/LD
CS/LD
10
10
µP
D
D
DGND
DGND
IN
IN
9
9
D
OUT
D
OUT
DIGITAL GROUND PLANE
CLK
D15
D11
D10
D9
D8
D7
D3
D2
D1
D0
D
IN
CS/LD
6912 F06
Figure 6. Two LTC6912s (Four PGAs) in Daisy Chain Configuration
6912fa
20
LTC6912
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Offset Voltage vs Gain Setting
Note that operating the LTC6912 family in “zero” gain
mode (digital state 0000) open circuits both the INA and
INB pins and this demands some care if employed with a
series AC coupling input capacitor. When the chip enters
the zero gain mode, the opened INA or INB pin tends to
sample and freeze the voltage across the capacitor to the
value it held just before the zero gain state. This can place
the INA or INB pin at or near the DC potential of a supply
rail. (The INA or INB pin may also drift to a supply potential
in this state due to small leakage currents.) To prevent
driving the INA or INB pin outside the supply limit and
potentially damaging the chip, avoid AC input signals in
the zero gain state with an AC coupling capacitor. Also,
switching later to a non-zero gain value will cause a
transient pulse at the output of the LTC6912-1 (with a time
constantsetbythecapacitorvalueandthenewLTC6912-1
input resistance value). This occurs because the INA and
INB pins return to the AGND potential forcing transient
current sourced by the amplifier output to charge the AC
coupling capacitor to its proper DC blocking value.
The electrical tables list DC offset (error), VOS(OA), at the
inputs of the internal op amp (See Figure 1). The electrical
tables also show the resulting, gain dependent offset
voltage referred to the INA, or INB pins, VOS(IN). The two
measures are related through the feedback/input resistor
ratio, which equals the nominal gain-magnitude setting,
|GAIN|:
VOS(IN) = (1 + 1/|GAIN|) VOS(OA)
Offsetvoltagesatanygainsettingcanbeinferredfromthis
relationship. For example, an internal amplifier offset
V
OS(OA) of 1mV will appear referred to the INA, INB pins as
2mV at a gain setting of 1, or 1.5mV at a gain setting of 2.
At high gains, VOS(IN) approaches VOS(OA). (Offset voltage
is random and can have either polarity centered on 0V).
The MOS input circuitry of the internal op amp in Figure 1
draws negligible input currents (less than 10µA), so only
VOS(OA) and the GAIN affect the overall amplifier’s offset.
AC-Coupled Operation
SNR and Dynamic Range
Adding capacitors in series with the INA and INB pins
converts the LTC6912-X into a dual AC-coupled inverting
amplifier,suppressingtheinputsignal’sDClevel(andalso
adding the additional benefit of reducing the offset voltage
from the LTC6912-X’s amplifier itself). No further compo-
nents are required because the input of the LTC6912-X
biases itself correctly when a series capacitor is added.
The INA and INB analog input pins connect internally to a
resistor whose nominal value varies between 10kΩ and
1kΩ depending on the version of LTC6912 used (see the
rightmost column of Tables 1 and 2). Therefore, the low
frequency cutoff will vary with capacitor and gain setting.
If, for example, a low frequency corner of 1kHz (or lower)
on the LTC6912-1 is desired, use a series capacitor of
0.16µF or larger. 0.16µF has a reactance of 1kΩ at 1kHz,
giving a 1kHz lower –3dB frequency for gain settings of
10V/V through 100V/V. If the LTC6912-1 is operated at
lower gain settings with a 0.16µF capacitor, the higher
input resistance will reduce the lower corner frequency
downto100Hzatagainsettingof1V/V.Thesefrequencies
scale inversely with the value of input capacitor used.
The term “dynamic range” is much used (and abused)
with signal paths. Signal-to-noise (SNR) is an unambigu-
ous comparison of signal and noise levels, measured in
thesamewayandunderthesameoperatingconditions. In
avariablegainamplifier,however,furthercharacterization
is useful because both noise and maximum signal level in
the amplifier will vary with the gain setting, in general. In
the LTC6912-X, maximum output signal is independent of
gain (and is near the full power supply voltage, as detailed
in the swing sections of the Electrical Characteristics
table). The maximum input level falls with increasing gain,
and the input-referred noise falls as well (listed also in the
table). To summarize the useful signal range in such an
amplifier, we define dynamic range (DR) as the ratio of
maximum input (at unity gain) to minimum input-referred
noise (at maximum gain). This DR has a physical interpre-
tation as the range of signal levels that will experience an
SNR above unity V/V or 0dB. At a 10V total power supply,
DR in the LTC6912-X (gains 0V/V to 100V/V), the DR is
typically 115dB (the ratio of 9.9 VP-P, or 3.5VRMS, maxi-
mum input to the 6.3µVRMS high gain input noise). The
6912fa
21
LTC6912
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APPLICATIO S I FOR ATIO
SNR from an amplifier is the ratio of input level to input-
referred noise, and can be 108dB with the LTC6912 family
at unity gain.
decoupling from a clean, low inductance power source.
But several centimeters of wire (i.e., a few µH of induc-
tance) from the power supplies, unless decoupled by
substantial capacitance (>10µF) near the chip, can create
a parasitic high-Q LC resonant circuit in the hundreds of
kHz range in the chip’s supplies or ground reference. This
may impair circuit performance at those frequencies. A
compact, carefully laid out printed circuit board with a
good ground plane makes a significant difference in mini-
mizing distortion. Finally, equipment to measure perfor-
mance can itself introduce distortion or noise floors.
Checking for these limits with wired shorts from INA to
OUTA and INB to OUTB in place of the chip is a prudent
routine procedure.
Construction and Instrumentation Cautions
Electrically clean construction is important in applications
seeking the full dynamic range of the LTC6912 family of
dualamplifiers. ItisabsolutelycriticaltohaveAGNDeither
AC bypassed or wired directly using the shortest possible
wiring,toalowimpedancegroundreturnforbestchannel-
to-channel isolation. Short, direct wiring minimizes para-
sitic capacitance and inductance. High quality supply
bypass capacitors of 0.1µF near the chip provide good
U
TYPICAL APPLICATIO
Low Noise AC Amplifier with Programmable Gain and
Bandwidth
an integrating lowpass loop with capacitor C2 to set the
programmable upper corner frequency. The LT1884 also
supports rail-to-rail output swings over the total supply
voltage range of 2.7V to 10.5V. AC coupling through
capacitor C1 establishes a fixed low frequency corner of
1Hz, which can be adjusted by changing C1. Alternatively,
shorting C1 makes the amplifier DC coupled. If DC gain is
not needed, the AC coupling cap C1 serves to suppress
severalerrorsources:anyshiftinDClevels, lowfrequency
noise, and DC offset voltages (not including the LT1884’s
low internal offset).
Analogdataacquisitioncanexploitbandlimitingaswellas
gain to suppress unwanted signals or noise. Tailoring an
analog front end to both the level and bandwidth of each
source maximizes the resulting SNR. Figure 7 shows a
block diagram for a low noise amplifier with gain and
bandwidth independently programmable over a 100:1
range. Channels A and B of the LTC6912-1 are used to
independently control the gain and bandwidth respec-
tively over a 100:1 range. The LT1884 dual op amp forms
R2
15.8k
C2
1µF
R
GAIN
CONTROL
1M
BANDWIDTH
CONTROL
PGA
PGA
C1
R1
15.8k
10µF
V
GAINA
IN
–
R
INA
OUTA
GAINB
–
1/2 LT1884
INB
OUTB
V
1/2 LT1884
LTC6912-1
CHANNEL A
+
OUT
LTC6912-1
CHANNEL B
+
1/2 LT1884
6912 F07
R2
= GAINA
R1
1
1
R2
V
OUT
V
IN
–3dB BANDWIDTH RANGE IS FROM
TO ≤
2πR1C1
2π
(
)
C2
GAINB
Figure 7. Block Diagram of an AC Amplifier with Programmable Gain and Bandwidth
6912fa
22
LTC6912
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PACKAGE DESCRIPTIO
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695)
0.38 ± 0.10
4.00 ±0.10
(2 SIDES)
R = 0.115
TYP
7
12
0.65 ±0.05
R = 0.20
TYP
3.50 ±0.05
2.20 ±0.05 (2 SIDES)
1.70 ±0.05
3.00 ±0.10 1.70 ± 0.10
(2 SIDES)
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PIN 1
NOTCH
PACKAGE OUTLINE
(UE12/DE12) DFN 0603
6
0.25 ± 0.05
1
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
0.50
BSC
3.30 ±0.10
(2 SIDES)
3.30 ±0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ± .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
6912fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LTC6912
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TYPICAL APPLICATIO
A 2:1 PGA MUX
+
V
0.1µF
12
+
14
–
V
V
2
3
4
15
13
INA
OUT A
V
CHANNEL A
INPUT
OUT
(TO ADC)
1µF
LTC6912-X
AGND
INB
OUT B
CHANNEL B
INPUT
CHB
SHDN
CHA
DGND
5
6
7
8
SHDN
CS/LD
DATA
CLK
10
CS/LD
3-WIRE
SPI
INTERFACE
D
9
IN
D
OUT
6912 TA02
MUX OPERATION: IF THE LOWER NIBBLE (Q3, Q2, Q1, Q0) IS (1, 0, 0, 0) THEN OUTA IS IN
TRI-STATE AND THE UPPER NIBBLE (Q7, Q6, Q5, Q4) CONTROLS THE ACTIVE CHANNEL B.
IF THE UPPER NIBBLE IS (1, 0, 0, 0) THEN OUTB IS IN TRI-STATE
AND THE LOWER NIBBLE CONTROLS ACTIVE CHANNEL A.
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1228
100MHZ Gain Controlled Transconductance Amplifier
40Mhz Video Fader and Gain Controlled Amplifier
10kHz to 150kHz Digitally Controlled Filter and PGA
Differential Input, Continuous Analog Gain Control
LT1251/LT1256
LTC1564
Two Input, One Output, Continuous Analog Gain Control
Continuous Time, Low Noise 8th Order Filter and 4-Bit PGA
Single Programmable Gain Amplifier, 3-Bit Parallel Digital Interface
LTC6910-1/-2/-3
Digitally Controlled Programmable Gain Amplifier
in SOT-23
LTC6911-1/-2
LTC6915
Dual Digitally Controlled Programmable Gain Amplifier
in MSOP-10
Dual Programmable Gain Amplifiers, 3-Bit Parallel Digital Interface
Gains 0 - 4096V/V, 116dB CMRR
Zero Drift Instrumentation Amp
with Digitally Programmable Gain
6912fa
LT/LT 1005 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
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(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2004
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