LTC6990CS6-PBF [Linear]
TimerBlox: Voltage Controlled Silicon Oscillator; TimerBlox系列：压控硅振荡器
| 型号： | LTC6990CS6-PBF |
| 厂家： | 
Linear |
| 描述： | TimerBlox: Voltage Controlled Silicon Oscillator |
| 文件： | 总28页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Electrical Specifications Subject to Change
LTC6990
TimerBlox: Voltage
Controlled Silicon Oscillator
FEATURES
DESCRIPTION
The LTC®6990 is a precision silicon oscillator with a pro-
grammable frequency range of 488Hz to 2MHz. It can be
used as a fixed-frequency or voltage-controlled oscillator
(VCO). The LTC6990 is part of the TimerBlox™ family of
versatile silicon timing devices.
n
Fixed-Frequency or Voltage-Controlled Operation
– Fixed: Single Resistor Programs Frequency
with <2.2% Max Error
– VCO: Two Resistors Set VCO Center
Frequency and Tuning Range
n
Frequency Range: 488Hz to 2MHz
A single resistor, R , programs the LTC6990’s inter-
SET
n
2.25V to 5.5V Single Supply Operation
nal master oscillator frequency. The output frequency
n
72μA Supply Current at 100kHz
is determined by this master oscillator and an internal
n
500μs Start-Up Time
frequency divider, N , programmable to eight settings
DIV
n
VCO Bandwidth >300kHz at 1MHz
from 1 to 128.
n
CMOS Logic Output Sources/Sinks 20mA
n
50% Duty Cycle Square Wave Output
1MHz 50kΩ
NDIV RSET
fOUT
=
•
,NDIV = 1, 2, 4 …128
n
Output Enable (Selectable Low or Hi-Z When Disabled)
n
–40°C to 125°C Operating Temperature Range
Optionally,asecondresistorattheSETinputprovideslinear
voltage control of the output frequency and can be used
for frequency modulation. A narrow or wide VCO tuning
range can be configured by the appropriate selection of
the two resistors.
n
Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN Package
APPLICATIONS
n
Low Cost Precision Programmable Oscillator
n
Voltage-Controlled Oscillator
The LTC6990 includes an enable function that is synchro-
nizedwiththemasteroscillatortoensureclean,glitch-free
output pulses. The disabled output can be configured to
be high impedance or forced low.
n
High Vibration, High Acceleration Environments
n
Replacement for Fixed Crystal and Ceramic Oscillators
n
Portable and Battery-Powered Equipment
L, LT, LTC and LTM, Linear Technology and the Linear logo are registered trademarks of
Linear Technology Corporation. TimerBlox and ThinSOT are trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by U.S.
Patents including 6342817, 6614313.
The LTC6990 is available in the 6-lead SOT-23 (ThinSOT)
package or a 6-lead 2mm × 3mm DFN.
TYPICAL APPLICATION
Voltage Controlled Oscillator with 16:1 Frequency Range
VCO Transfer Function
1000
MHz
V
f
ꢀ 1MHz ꢁ V • 0.5
CTRL
+
OUT
V
750
500
250
0
OE
OUT
LTC6990
+
V
+
GND
V
C1
0.1μF
R
VCO
100k
V
SET
DIV
CTRL
6990 TA01a
R
SET
100k
0
0.5
1
1.5
2
V
CTRL
(V)
6990 TA01b
6990p
1
LTC6990
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V ) to GND ........................................6V
(Note 1)
+
Specified Temperature Range (Note 3)
Maximum Voltage on Any Pin
LTC6990C................................................ 0°C to 70°C
LTC6990I.............................................–40°C to 85°C
LTC6990H.......................................... –40°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10sec) ...................300°C
+
.............................(GND – 0.3V) ≤ V ≤ (V + 0.3V)
PIN
Operating Temperature Range (Note 2)
LTC6990C............................................–40°C to 85°C
LTC6990I.............................................–40°C to 85°C
LTC6990H.......................................... –40°C to 125°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
+
6
5
4
OUT
GND
OE
V
1
2
3
OE 1
GND 2
SET 3
6 OUT
7
DIV
SET
+
5 V
4 DIV
DCB PACKAGE
6-LEAD (2mm × 3mm) PLASTIC DFN
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
T
= 150°C, θ = 230°C/W
T
= 150°C, θ = 64°C/W
JA
JMAX
JA
JMAX
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL
ORDER INFORMATION
LEAD FREE FINISH
LTC6990CDCB#PBF
LTC6990IDCB#PBF
LTC6990HDCB#PBF
LTC6990CS6#PBF
LTC6990IS6#PBF
LTC6990HS6#PBF
TAPE AND REEL
PART MARKING*
LDWX
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
LTC6990CDCB#TRPBF
LTC6990IDCB#TRPBF
LTC6990HDCB#TRPBF
LTC6990CS6#TRPBF
LTC6990IS6#TRPBF
LTC6990HS6#TRPBF
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
LDWX
–40°C to 85°C
LDWX
–40°C to 125°C
0°C to 70°C
LTDWW
LTDWW
LTDWW
6-Lead Plastic TSOT-23
–40°C to 85°C
6-Lead Plastic TSOT-23
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
6990p
2
LTC6990
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, OE = V+, DIVCODE = 0 to 15
(NDIV = 1 to 128), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
f
Output Frequency
Recommended Range: R = 50k to 800k
0.488
0.488
1000
2000
kHz
kHz
OUT
SET
Extended Range: R = 25k to 800k
SET
Frequency Accuracy (Note 4)
Recommended Range
SET
0.8
1.5
2.2
%
%
Δf
OUT
l
R
= 50k to 800k
Extended Range
= 25k to 800k
2.4
3.2
%
%
l
l
R
SET
Frequency Drift Over Temperature
Frequency Drift Over Supply
0.005
%/°C
Δf /ΔT
OUT
+
+
+
l
l
V = 4.5V to 5.5V
0.23
0.06
0.55
0.16
%/V
%/V
Δf /ΔV
OUT
V = 2.25V to 4.5V
Period Jitter (Note 10)
N
N
= 1
= 2
0.38
%
DIV
DIV
P-P
0.22
0.027
%
P-P
%
%
RMS
N
DIV
= 128
0.022
0.004
%
RMS
P-P
l
l
Duty Cycle
N
DIV
N
DIV
= 1, R = 25k to 800k
47
48
50
50
53
52
%
%
SET
> 1, R = 25k to 800k
SET
BW
Frequency Modulation Bandwidth
0.4•f
kHz
μs
OUT
t
Frequency Change Settling Time
(Note 9)
t
= t /N
OUT DIV
6•t
MASTER
S
MASTER
Analog Inputs
l
l
V
Voltage at SET Pin
0.97
1.00
75
1.03
V
SET
V
V
V
Drift Over Temperature
Drift Over Supply
μV/°C
μV/V
Ω
ΔV /ΔT
SET
SET
SET
SET
+
–150
–7
ΔV /ΔV
SET
Droop with I
ΔV /ΔI
SET
SET
SET
l
l
R
SET
Frequency-Setting Resistor
Recommended Range
Extended Range
50
25
800
800
kΩ
kΩ
+
l
l
l
V
DIV Pin Voltage
0
V
V
%
DIV
+
+
DIV Pin Valid Code Range (Note 5) Deviation from Ideal V /V = (DIVCODE + 0.5)/16
1.5
10
ΔV /V
DIV
DIV
DIV Pin Input Current
nA
Power Supply
+
l
l
V
Operating Supply Voltage Range
2.25
5.5
V
V
Power-On Reset Voltage
Supply Current
R
= 25k to 800k
1.95
SET
+
+
l
l
I
R = ∞, N = 1, R = 50k
L
V = 5.5V
235
145
283
183
μA
μA
S
DIV
SET
V = 2.25V
+
+
l
l
R = ∞, N = 1 R = 800k
V = 5.5V
71
59
105
92
μA
μA
L
DIV
SET
V = 2.25V
+
+
l
l
R = ∞, N = 128, R = 50k
V = 5.5V
137
106
180
145
μA
μA
L
DIV
SET
V = 2.25V
+
+
l
l
R = ∞, N = 128, R = 800k
V = 5.5V
66
56
100
90
μA
μA
L
DIV
SET
V = 2.25V
6990p
3
LTC6990
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, OE = V+, DIVCODE = 0 to 15
(NDIV = 1 to 128), RSET = 25k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital I/O
OE Pin Input Capacitance
OE Pin Input Current
2.5
pF
nA
V
+
l
l
l
OE = 0V to V
10
+
V
V
High Level OE Pin Input Voltage
Low Level OE Pin Input Voltage
OUT Pin Hi-Z Leakage
(Note 6)
0.7•V
IH
+
(Note 6)
0.3•V
10
V
IL
+
OE = 0V, DIVCODE ≥ 8, OUT = 0V to V
μA
mA
I
Maximum Output Current
20
OUT(MAX)
+
l
l
V
High Level Output Voltage
(Note 7)
V = 5.5V
I
OH
I
OH
= –1mA
= –16mA
5.45
4.84
5.48
5.15
V
V
OH
+
l
l
V = 3.3V
I
OH
I
OH
= –1mA
= –10mA
3.24
2.75
3.27
2.99
V
V
+
l
l
V = 2.25V
I
OH
I
OH
= –1mA
= –8mA
2.17
1.58
2.21
1.88
V
V
+
l
l
V
OL
Low Level Output Voltage
(Note 7)
V = 5.5V
I
I
= 1mA
= 16mA
0.02
0.26
0.04
0.54
V
V
OL
OL
+
l
l
V = 3.3V
I
I
= 1mA
= 10mA
0.03
0.22
0.05
0.46
V
V
OL
OL
+
l
l
V = 2.25V
I
OL
I
OL
= 1mA
= 8mA
0.03
0.26
0.07
0.54
V
V
+
t
PD
Output Disable Propagation Delay V = 5.5V
17
26
44
ns
ns
ns
+
V = 3.3V
+
V = 2.25V
t
t
Output Enable Time
N
N
≤ 2, t
≥ 4, t
= 1/f
MASTER
t
to t
μs
μs
ENABLE
r
DIV
DIV
OUT
OUT
OUT DIV
PD
OUT
= t /N
t
to 2•t
PD MASTER
+
Output Rise Time (Note 8)
V = 5.5V
1.1
1.7
2.7
ns
ns
ns
+
V = 3.3V
+
V = 2.25V
+
t
f
Output Fall Time (Note 8)
V = 5.5V
1.0
1.6
2.4
ns
ns
ns
+
V = 3.3V
+
V = 2.25V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6990C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
Note 6: The OE pin has hysteresis to accommodate slow rising or falling
+
signals. The threshold voltages are proportional to V . Typical values can
+
be estimated at any supply voltage using V
≈ 0.55 • V + 185mV
OE(RISING)
+
and V
≈ 0.48 • V – 155mV.
OE(FALLING)
Note 3: The LTC6990C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6990C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6990I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6990H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Settling time is the amount of time required for the output to settle
Note 4: Frequency accuracy is defined as the deviation from the f
OUT
within 1% of the final frequency after a 0.5x or 2x change in I
.
SET
equation, assuming R is used to program the frequency.
SET
Note 10: Jitter is the ratio of the deviation of the period to the mean of the
period. This specification is based on characterization and is not 100%
tested.
6990p
4
LTC6990
V+ = 3.3V, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Frequency Error
Frequency Error vs RSET
vs Supply Voltage
Frequency Error vs Temperature
4
3
0.5
0.4
1.5
1.0
+
T
= 25°C
T = 25°C
A
V
= 3.3V
A
DIVCODE = 4
GUARANTEED MAX
OVER TEMPERATURE
0.3
2
R
= 800k
SET
0.2
0.5
1
TYPICAL MAX
90% OF UNITS
TYPICAL MIN
0.1
R
SET
= 50k
R
0
0
0.0
R
R
= 200k
= 50k
= 800k
SET
SET
SET
–0.1
–0.2
–0.3
–0.4
–0.5
–1
–2
–3
–4
–0.5
–1.0
–1.5
R
SET
= 267k
GUARANTEED MIN
OVER TEMPERATURE
10
100
1000
2
3
4
5
6
–50 –25
0
25
50
75 100 125
R
(kꢀ)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SET
6990 G01
6990 G02
6990 G03
VSET vs ISET
VSET vs Supply Voltage
VSET vs Temperature
1.003
1.002
1.001
1.000
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
1.003
1.002
1.001
1.000
+
V
T
= 3.3V
= 25°C
R
T
= 200k
R
= 200k
SET
SET
A
= 25°C
3 TYPICAL PARTS
A
0
10
20
(μA)
30
40
–50 –25
0
25
50
75 100 125
2
3
4
5
6
I
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SET
6990 G04
6990 G06
6990 G05
Typical VSET Distribution
Supply Current vs Supply Voltage
Supply Current vs Temperature
250
200
150
100
50
250
200
150
100
50
300
250
200
150
100
50
T
= 25°C
T
= 25°C
A
A
R
= 50k, ÷1
SET
5.5V, R
= 50k, ÷1
2 LOTS
SET
DFN AND SOT-23
1416 UNITS
R
SET
= 50k, ÷2
2.25V, R
5.5V, R
= 50k, ÷1
SET
R
SET
= 50k, ÷128
= 50k, ÷128
= 800k, ÷1
SET
5.5V, R
SET
R
R
= 800k, ÷1
SET
SET
= 800k, ÷128
2.25V, R
= 800k, ÷128
SET
0
0
0
2
3
4
5
6
–50 –25
0
25
50
75 100 125
0.986 0.994
1.002
(V)
1.010
1.018
SUPPLY VOLTAGE (V)
V
TEMPERATURE (°C)
SET
6990 G05
6990 G09
6990 G07
6990p
5
LTC6990
V+ = 3V, unless otherwise noted.
Supply Current vs Frequency, 2.5V
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Frequency, 5V
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
RECOMMENDED RANGE
EXTENDED RANGE
RECOMMENDED RANGE
EXTENDED RANGE
÷2
÷1
÷2
÷128
÷1
÷128
+
+
V
T
= 5V
= 25°C
V
T
= 2.5V
= 25°C
A
A
0
0
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
FREQUENCY (kHz)
FREQUENCY (kHz)
6990 G10
6990 G11
Peak-to-Peak Jitter vs Frequency
Supply Current vs OE Pin Voltage
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
200
175
150
125
100
75
T
= 25°C
= 5V
T
= 25°C
SET
A
A
+
V
R
= 800k
5V, OE RISING
PEAK-TO-PEAK PERIOD
DEVIATION MEASURED
OVER 30sec INTERVALS
DIVCODE = 7
5V, OE FALLING
3.3V, OE FALLING
÷1
3.3V,
OE RISING
÷2
÷4
÷128
50
0.1
1
10
100
1000
0
20
40
60
/V (%)
80
100
+
FREQUENCY (kHz)
V
OE
6990 G13
6990 G12
OE Threshold Voltage
vs Supply Voltage
Output Resistance
vs Supply Voltage
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
50
45
40
35
30
25
20
15
10
5
T
= 25°C
T
= 25°C
A
A
POSITIVE-GOING
OUTPUT SOURCING CURRENT
NEGATIVE-GOING
OUTPUT SINKING CURRENT
0
2
3
4
5
6
2
3
4
5
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6990 G14
6990 G16
6990p
6
LTC6990
V+ = 3V, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Rise and Fall Time
vs Supply Voltage
Output Disable Propagation Delay
(tPD) vs Supply Voltage
3.0
2.5
2.0
1.5
1.0
0.5
0
50
45
40
35
30
25
20
15
10
5
T
= 25°C
LOAD
T
= 25°C
LOAD
A
A
C
= 5pF
C
= 5pF
t
RISE
t
FALL
0
2
3
4
5
6
2
3
4
5
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6990 G16
6990 G17
Typical ISET Current Limit vs V+
Typical Output Waveform
1000
800
600
400
200
0
+
T
= 25°C
V
= 3.3V
A
SET PIN SHORTED TO GND
DIVCODE = 2
= 200k
R
SET
OE
2V/DIV
OUT
2V/DIV
6990 G19
20μs/DIV
2
3
4
5
6
SUPPLY VOLTAGE (V)
6990 G18
Frequency Modulation
Frequency Modulation
V
V
CTRL
CTRL
2V/DIV
2V/DIV
OUT
2V/DIV
OUT
2V/DIV
f
f
OUT
OUT
50kHz/DIV
50kHz/DIV
6990 G21
6990 G20
20μs/DIV
+
20μs/DIV
+
V
R
f
= 3.3V, DIVCODE = 0
V
R
f
= 3.3V, DIVCODE = 0
= 200k, R
= 464k
= 200k, R
= 464k
SET
VCO
SET
VCO
= 175kHz to 350kHz
= 175kHz to 350kHz
OUT
OUT
6990p
7
LTC6990
PIN FUNCTIONS (DCB/S6)
V (Pin1/Pin5):SupplyVoltage(2.25Vto5.5V).Thissup-
ply must be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1μF capacitor.
+
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the V voltage.
SET
DIV (Pin 2/Pin 4): Programmable Divider and Hi-Z Mode
+
+
Input. A V referenced A/D converter monitors the DIV
V
pin voltage (V ) to determine a 4-bit result (DIVCODE).
DIV
OE
OUT
LTC6990
+
V
DIV
may be generated by a resistor divider between V
+
V
and GND. Use 1% resistors to ensure an accurate result.
The DIV pin and resistors should be shielded from the
OUT pin or any other traces that have fast edges. Limit
the capacitance on the DIV pin to less than 100pF so that
+
GND
SET
V
C1
0.1μF
R1
R2
DIV
6990 PF
R
SET
V
settles quickly. The MSB of DIVCODE (Hi-Z) deter-
DIV
mines the behavior of the output when OE is driven low.
If Hi-Z = 0 the output is pulled low when disabled. If Hi-Z
= 1 the output is placed in a high impedance condition
when disabled.
OE (Pin 4/Pin 1): Output Enable. Drive high to enable the
output driver (Pin 6). Driving OE low disables the output
asynchronously, so that the output is immediately forced
low (Hi-Z = 0) or floated (Hi-Z = 1). When enabled, the
output may temporarily remain low to synchronize with
the internal oscillator in order to eliminate pulse slivers.
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (V ) is regulated to 1V above GND. The
SET
amount of current sourced from the SET pin (I ) pro-
SET
grams the master oscillator frequency. The I
current
SET
GND(Pin5/Pin2):Ground.Tietoalowinductanceground
plane for best performance.
range is 1.25μA to 40μA. The output oscillation will stop
if I drops below approximately 500nA. A resistor con-
SET
OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
nected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
50ppm/°C or better temperature coefficient. For lower ac-
curacy applications an inexpensive 1% thick film resistor
may be used.
+
fromGNDtoV withanoutputresistanceofapproximately
30ꢀ. When driving an LED or other low-impedance load a
series output resistor should be used to limit source/sink
current to 20mA.
6990p
8
LTC6990
(S6 Package Pin Numbers Shown)
BLOCK DIAGRAM
+
V
OE
1
5
R1
Hi-Z BIT
DIV
4-BIT A/D
CONVERTER
DIGITAL
FILTER
4
R2
Hi-Z WHEN
DISABLED
MASTER OSCILLATOR
VSET
1μs
OUT
tMASTER
ꢀ
•
MCLK
PROGRAMMABLE DIVIDER
÷1, 2, 4, 8, 16, 32, 64, 128
50k7 ISET
6
t
OUT
Hi-Z OUTPUT
UNTIL SETTLED
HALT OSCILLATOR
IF I
< 500nA
SET
I
SET
POR
+
–
+
–
1V
V
= 1V
SET
2
3
6990 BD
GND
SET
R
SET
6990p
9
LTC6990
OPERATION
The LTC6990 is built around a master oscillator with a
DIVCODE
1MHz maximum frequency. The oscillator is controlled
+
The DIV pin connects to an internal, V referenced 4-bit
by the SET pin current (I ) and voltage (V ), with a
SET
SET
A/D converter that monitors the DIV pin voltage (V ) to
DIV
1MHz • 50k conversion factor that is accurate to 0.8%
determine the DIVCODE value. DIVCODE programs two
under typical conditions.
settings on the LTC6990:
ISET
VSET
1
fMASTER
=
=1MHz • 50k •
1. DIVCODE determines the output frequency divider
tMASTER
setting, N
.
DIV
A feedback loop maintains V at 1V 30mV, leaving I
2. DIVCODE determines the state of the output when
disabled, via the Hi-Z bit.
SET
SET
as the primary means of controlling the output frequency.
The simplest way to generate I is to connect a resistor
+
SET
V
DIV
may be generated by a resistor divider between V
(R ) between SET and GND, such that I = V /R .
SET
SET
SET SET
and GND as shown in Figure 1.
The master oscillator equation reduces to:
1
1MHz •50k
RSET
2.25V TO 5.5V
fMASTER
=
=
tMASTER
+
V
LTC6990
R1
R2
From this equation it is clear that V drift will not affect
SET
DIV
theoutputfrequencywhenusingasingleprogramresistor
(R ). Error sources are limited to R tolerance and the
SET
SET
GND
inherent frequency accuracy Δf
of the LTC6990.
OUT
6990 F01
R
values between 50k and 800k (equivalent to I
SET
SET
between 1.25μA and 20μA) produce the best results,
Figure 1. Simple Technique for Setting DIVCODE
although R may be reduced to 25k (I = 40μA) with
reduced accuracy.
SET
SET
The LTC6990 includes a programmable frequency divider
which can further divide the frequency by 1, 2, 4, 8, 16,
32, 64 or 128 before driving the OUT pin. The divider ratio
N
is set by a resistor divider attached to the DIV pin.
DIV
ISET
VSET
1
tOUT
1MHz •50k
NDIV
fOUT
=
=
•
With R in place of V /I the equation reduces to:
SET
SET SET
1
1MHz •50k
fOUT
=
=
tOUT NDIV •RSET
6990p
10
LTC6990
OPERATION
Table 1. DIVCODE Programming
+
DIVCODE
Hi-Z
0
N
Recommended f
R1 (k)
Open
976
R2 (k)
Short
102
V
/V
DIV
DIV
OUT
0
1
1
62.5kHz to 1MHz
31.25kHz to 500kHz
15.63kHz to 250kHz
7.813kHz to 125kHz
3.906kHz to 62.5kHz
1.953kHz to 31.25kHz
976.6Hz to 15.63kHz
488.3Hz to 7.813kHz
488.3Hz to 7.813kHz
976.6Hz to 15.63kHz
1.953kHz to 31.25kHz
3.906kHz to 62.5kHz
7.813kHz to 125kHz
15.63kHz to 250kHz
31.25kHz to 500kHz
62.5kHz to 1MHz
≤ 0.03125 0.015
0.09375 0.015
0.15625 0.015
0.21875 0.015
0.28125 0.015
0.34375 0.015
0.40625 0.015
0.46875 0.015
0.53125 0.015
0.59375 0.015
0.65625 0.015
0.71875 0.015
0.78125 0.015
0.84375 0.015
0.90625 0.015
≥ 0.96875 0.015
0
2
4
8
2
0
976
182
3
0
1000
1000
1000
1000
1000
887
280
4
0
16
32
64
128
128
64
32
16
8
392
5
0
523
6
0
681
7
0
887
8
1
1000
1000
1000
1000
1000
976
9
1
681
10
11
12
13
14
15
1
523
1
392
1
280
1
4
182
1
2
102
976
1
1
Short
Open
Table 1 offers recommended 1% resistor values that ac-
curatelyproducethecorrectvoltagedivisionaswellasthe
column in Table 1 shows the ideal ratio of V
to the
DIV
supply voltage, which can also be calculated as:
correspondingN andHi-Zvaluesfortherecommended
DIV
VDIV
V+
DIVCODE + 0.5
resistor pairs. Other values may be used as long as:
=
1.5%
16
+
1. The V /V ratio is accurate to 1.5% (including resis-
DIV
Forexample,ifthesupplyis3.3VandthedesiredDIVCODE
tor tolerances and temperature effects)
is 4, V = 0.281 • 3.3V = 928mV 50mV.
DIV
2. The driving impedance (R1||R2) does not exceed
500kꢀ.
Figure2illustratestheinformationinTable1,showingthat
N
DIV
is symmetric around the DIVCODE midpoint.
If the voltage is generated by other means (i.e. the output
+
of a DAC) it must track the V supply voltage. The last
Hi-Z BIT = 0
Hi-Z BIT = 1
1000
0
15
1
14
13
100
2
3
12
11
4
10
1
5
10
6
9
7
8
RECOMMENDED RANGE
EXTENDED RANGE
0.1
+
+
0V
0.5•V
INCREASING V
V
DIV
6990 F02
Figure 2. Frequency Range and Hi-Z Bit vs DIVCODE
6990p
11
LTC6990
OPERATION
On start-up, the DIV pin A/D converter must determine the
correct DIVCODE before the output is enabled. If V is
notstable,itwillincreasethestart-uptimeastheconverter
waits for a stable result. Therefore, capacitance on the DIV
pin should be minimized so it will settle quickly. Less than
100pF will not affect performance.
Figure 3 illustrates the timing for the OE function when
Hi-Z = 0. When OE is low, the output is disabled and OUT
is held low. Bringing OE high enables the output after a
DIV
delay, t
, which synchronizes the enable to eliminate
ENABLE
sliver pulses and guarantee the correct width for the first
pulse. If N = 1 or 2 this delay will be no longer than
DIV
the output period, t . If N > 2 the delay is limited to
OUT
DIV
Output Enable
twicethe internalmasteroscillatorperiod(or2•t
).
MASTER
Forcing OE low will bring OUT low after a propagation
The OE pin controls the state of the LTC6990’s output as
seen on the OUT pin. Pulling the OE pin high enables the
oscillator output. Pulling it low disables the output. When
the output is disabled, it is either held low or placed in
a high impedance state as dictated by the Hi-Z bit value
(determinedbytheDIVCODEasdescribedearlier). Table2
summarizes the output control states.
delay, t . If the output is high when OE falls, the output
PD
pulse will be truncated.
As shown in Figure 4, setting Hi-Z = 1 places the output in
a high-impedance state when OE = 0. This feature allows
for“wired-OR”connectionsofmultipledevices.DrivingOE
high enables the output. The output will usually be forced
low during this time, although it is possible for OUT to
transition directly from high-impedance to a high output,
depending on the timing of the OE transition relative to
the internal oscillator. Once high, the first output pulse
will have the correct width (unless truncated by bringing
OE low again).
Table 2. Output States
OE Pin
Hi-Z
X
OUT
1
0
0
Enabled, Output is Active
Disabled, Output is Hi-Z
Disabled, Output is Held Low
1
0
OE
t
PD
t
PD
OUT
t
ENABLE
t
t
OUT
ENABLE
6990 F03
Figure 3. OE Timing Diagram (Hi-Z = 0)
OE
t
t
PD
t
t
PD
PD
PD
Hi-Z
OUT
t
ENABLE
t
t
OUT
ENABLE
6990 F04
Figure 4. OE Timing Diagram (Hi-Z = 1)
6990p
12
LTC6990
OPERATION
Changing DIVCODE After Start-Up
Start-Up Time
When power is first applied to the LTC6990 the power-on
reset (POR) circuit will initiate the start-up time, t
Following start-up, the A/D converter will continue
monitoring V for changes. Changes to DIVCODE will
.
START
DIV
be recognized slowly, as the LTC6990 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
The OUT pin is floated (high-impedance) during this time.
The typical value for t ranges from 0.5ms to 8ms
START
depending on the master oscillator frequency (indepen-
dent of N ):
DIV
tSTART(TYP) = 500 • tMASTER
tDIVCODE =16 •(ΔDIVCODE + 6)• tMASTER
The start-up time may be longer if the supply or DIV
pin voltages are not stable. For this reason, it is recom-
mended to minimize the capacitance on the DIV pin so it
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes. A
digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
+
will properly track V .
576μs
DIV
1V/DIV
+
V
1V/DIV
470μs
OUT
1V/DIV
OUT
1V/DIV
OUTPUT CONNECTED
TO 1.25V THROUGH 25k
TO SHOW Hi-Z
6990 F05
6990 F06
100μs/DIV
+
100μs/DIV
+
V
R
= 3.3V
V
= 2.5V
DIVCODE = 4
= 50k
= 200k
SET
R
SET
Figure 5. DIVCODE Change from 5 to 2
Figure 6. Typical Start-Up
6990p
13
LTC6990
APPLICATIONS INFORMATION
OE
Hi-Z
OUT
1/2 t
OUT
t
t
OUT
START
6990 F07
Figure 7. Start-Up Timing Diagram (OE = 1, NDIV = 1 or 2, Hi-Z = 0 or 1)
OE
Hi-Z
OUT
t
t
t
OUT
START
MASTER
6990 F08
Figure 8. Start-Up Timing Diagram (OE = 1, NDIV ≥ 4, Hi-Z = 0 or 1)
OE
Hi-Z
OUT
t
ENABLE
t
t
OUT
START
6990 F09
Figure 9. Start-Up Timing Diagram (OE = 0, NDIV = Any, Hi-Z = 0)
OE
t
PD
Hi-Z
OUT
t
ENABLE
REMAINS Hi-Z
UNTIL OE = 1
t
t
OUT
START
6990 F10
Figure 10. Start-Up Timing Diagram (OE = 0, NDIV = Any, Hi-Z = 1)
6990p
14
LTC6990
APPLICATIONS INFORMATION
Start-Up Behavior
Example: Design a 20kHz Oscillator with Minimum
Power Consumption
When first powered up, the output is high impedance. If
the output is enabled (OE = 1) at the end of the start-up
Step 1: Selecting the N Frequency Divider Value
DIV
time, the output will go low for one t
cycle (or half
MASTER
First, choose an N value that meets the requirements
DIV
a t
cycle if N < 4) before the first rising edge. If the
OUT
DIV
of Equation (1a).
output is disabled (OE = 0) at the end of the start-up time,
the output will drop to a low output if the Hi-Z bit = 0, or
simply remain floating if Hi-Z = 1.
3.125 ≤ N ≤ 50
DIV
PotentialsettingsforN include4,8,16,and32.N =4
DIV
DIV
is the best choice, as it minimizes supply current by using
Basic Fixed Frequency Operation
a large R resistor. Using Table 1, choose the R1 and R2
SET
The simplest and most accurate method to program the
LTC6990 for fixed frequency operation is to use a single
values to program DIVCODE to either 2 or 13, depending
on the desired behavior when the output is disabled.
resistor, R , between the SET and GND pins. The design
SET
procedureisasimpletwostepprocess.FirstselecttheN
Step 2: Select R
DIV
SET
value and then calculate the value for the R resistor.
SET
Calculate the correct value for R using Equation (1b).
SET
Step 1: Selecting the N Frequency Divider Value
1MHz • 50k
4•20kHz
DIV
RSET
=
= 625k
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the Hi-Z bit and the
Since 625k is not available as a standard 1% resistor,
substitute 619k if a 0.97% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
N
value. For a given output frequency, N should be
DIV
DIV
selected to be within the following range.
62.5kHz
fOUT
1MHz
fOUT
≤ NDIV
≤
(1a)
Frequency Modulated Operation (Voltage-Controlled
Oscillator)
To minimize supply current, choose the lowest N value
DIV
(generallyrecommended).Forfasterstart-upordecreased
Operating the LTC6990 as a voltage-controlled oscillator in
itssimplestformisachievedwithoneadditionalresistor.As
jitter,chooseahigherN setting.Alternatively,useTable1
DIV
as a guide to select the best N value for the given ap-
DIV
shown in Figure 11, voltage V
sources/sinks a current
CTRL
plication. After choosing the value for N , use Table 1 to
DIV
through R to vary the I current, which in turn modu-
VCO
SET
+
select the proper resistor divider or V /V ratio to apply
DIV
lates the output frequency as described in Equation (2).
to the DIV pin.
⎛
⎞
1MHz •50k
NDIV •RVCO
RVCO VCTRL
−
(2)
fOUT
=
• 1+
Step 2: Calculate and Select R
⎜
⎝
⎟
SET
RSET VSET
⎠
The final step is to calculate the correct value for R
using the following equation.
SET
+
V
OE
OUT
1MHz • 50k
NDIV • fOUT
+
LTC6990
V
RSET
=
(1b)
+
GND
V
C1
0.1μF
R1
Select the standard resistor value closest to the calculated
value.
R
VCO
V
CTRL
SET
DIV
R
6990 F08
R2
SET
Figure 11. Voltage Controlled Oscillator
6990p
15
LTC6990
APPLICATIONS INFORMATION
Equation(2)canbere-writtenasshownbelow, wheref
K
and f
are not device settings or resistor values
(0V)
is the
VCO
(0V)
themselves. However, beyond their utility for the resistor
calculations,theseparametersprovideausefulandintuitive
is the output frequency when V
= 0V, and K
CTRL
VCO
frequency gain. Note that the gain is negative (the output
way to look at the VCO application. The f
parameter is
frequency decreases as V
increases).
(0V)
CTRL
the output frequency when V
is at 0V. Viewed another
CTRL
fOUT = f(0V) – KVCO • VCTRL
way, it is the fixed output frequency when the R
and
VCO
1MHz •50k
R
resistorsareinparallel.K isactuallythefrequency
SET
VCO
f(0V)
=
gain of the circuit.
NDIV • RSET PRVCO
(
)
With K
can now be calculated.
and f
determined, the R and R values
VCO SET
VCO
(0V)
1MHz • 50k
KVCO
=
NDIV • VSET •RVCO
Step 3: Calculate and Select R
VCO
The design procedure for a VCO is a simple four step
process. First select the N value. Then calculate the
The next step is to calculate the correct value for R
using the following equation.
VCO
DIV
intermediate values K
and f . Next, calculate and
VCO
(0V)
select the R
resistor. Finally calculate and select the
VCO
resistor.
1MHz • 50k
NDIV • VSET •KVCO
RVCO
=
R
(3d)
SET
Step 1: Select the N Frequency Divider Value
DIV
Select the standard resistor value closest to the calculated
value.
For best accuracy, the master oscillator frequency should
fall between 62.5kHz and 1MHz. Since f
= N
•
MASTER
that meets the following
DIV
Step 4: Calculate and Select R
SET
f
, choose a value for N
OUT
DIV
conditions
The final step is to calculate the correct value for R
using the following equation:
SET
62.5kHz
fOUT(MIN)
1MHz
fOUT(MAX)
≤ NDIV
≤
(3a)
1MHz •50k
RSET
=
(3e)
NDIV • f(0V) − V •KVCO
(
)
SET
The 16:1 frequency range of the master oscillator and
the 2:1 divider step-size provides several overlapping fre-
quency spans to guarantee that any 8:1 modulation range
Select the standard resistor value closest to the calculated
value.
can be covered by a single N setting. R
allows the
DIV
VCO
Some applications require combinations of f
,
OUT(MIN)
that are not achiev-
gain to be tailored to the application, mapping the V
CTRL
f
, V
and V
OUT(MAX) CTRL(MIN)
CTRL(MAX)
voltage range to the modulation range.
able. These applications result in unrealistic or unrealiz-
able (e.g. negative value) resistors. These applications
Step 2: Calculate K
and f
(0V)
VCO
will require preconditioning of the V
scaling and/or level shifting to place the V
that yields realistic resistor values.
signal via range
CTRL
CTRL
K
and f
define the VCO’s transfer function and
(0V)
into a range
VCO
simplify the calculation of the the R
and R
resis-
VCO
SET
tors. Calculate these parameters using the following
equations.
Frequency Error in VCO Applications Due to V Error
SET
fOUT(MAX) − fOUT(MIN)
As stated earlier, f
= 0V, which is the same value as would be generated by
a single resistor between SET and GND with a value of
represents the frequency for V
CTRL
(0V)
KVCO
=
(3b)
(3c)
VCTRL(MAX) − VCTRL(MIN)
) + K • V
CTRL(MIN)
f
= f
R
|| R . Therefore, f
SET
= 0V).
is not affected by error or
(0V)
OUT(MAX
VCO
SET
drift in V
VCO
(0V)
(i.e. ΔV
adds no frequency error when
SET
V
CTRL
6990p
16
LTC6990
APPLICATIONS INFORMATION
The accuracy of K
does depend on V
because the
Example: Design a VCO with the Following Parameters
VCO
SET
output frequency is controlled by the ratio of V
to
is ap-
CTRL
f
f
= 100kHz at V
= 1V
CTRL(MIN)
OUT(MAX)
OUT(MIN)
V
. The frequency error (in Hertz) due to ΔV
SET
SET
= 10kHz at V
= 4V
proximated by:
CTRL(MAX)
ΔVSET
VSET
Step 1: Select the N Value
ΔfOUT ≅KVCO • VCTRL
•
DIV
First, choose an N
Equation (3a).
that meets the requirements of
DIV
As the equation indicates, the potential for error in output
frequency due to V error increases with K and is
is at its maximum. Recall that
is at its maximum, the output frequency is at
itsminimum. Withthemaximumabsolutefrequencyerror
(in Hertz) occurring at the lowest output frequency, the
relative frequency error (in percent) can be significant.
SET
VCO
6.25 ≤ N ≤ 10
DIV
at its largest when V
CTRL
The application’s desired frequency range is 10:1, which
when V
CTRL
isn’t always possible. However, in this case N = 8 meets
DIV
both requirements of Equation (3).
Step 2: Calculate K
and f
(0V)
VCO
V
is nominally 1.0V with a maximum error of 30mV
SET
Next,calculatetheintermediatevaluesK andf using
Equations (3b) and (3c).
VCO
(0V)
for at most a 3% error term. However, this 3% potential
error term is multiplied by both V and K . Wide fre-
CTRL
VCO
quencyrangeapplications(highK )canhavefrequency
100kHz −10kHz
4V −1V
f(0V) =100kHz + 30kHz/V •1V =130kHz
VCO
KVCO
=
= 30kHz/V
errors greater than 50% at the highest V
voltage
CTRL
(lowestf ). Forthisreasonthesimple, tworesistorVCO
OUT
circuit must be used with caution for applications where
the frequency range is greater than 4:1. Restricting the
range to 4:1 typically keeps the frequency error due to
Step 3: Calculate and Select R
VCO
V
variation below 10%.
The next step is to use Equation (3d) to calculate the cor-
rect value for R
SET
.
VCO
For wide frequency range applications, the non-inverting
VCO circuit shown in Figure 13 is preferred because the
maximum frequency error occurs when the frequency
is highest, keeping the relative error (in percent) much
smaller.
1MHz • 50k
8 •1V •30kHz/V
RVCO
=
= 208.333k
Select R
= 210k.
VCO
100
80
60
40
20
0
Step 4: Calculate and Select R
SET
The final step is to calculate the correct value for R
using Equation (3e).
SET
1MHz • 50k
8 • 130kHz −1V • 30kHz/V
RSET
=
= 62.5k
(
)
Select R = 61.9k
SET
Inthisdesignexample,withitswide10:1frequencyrange,
thepotentialoutputfrequencyerrorduetoV erroralone
SET
1
2
3
4
ranges from less than 1% when V
is at its minimum
CTRL
V
(V)
CTRL
6990 F12
up to 36% when V
is at its maximum. This error
CTRL
must be accounted for in the system design.
Figure 12. VCO Transfer Function
6990p
17
LTC6990
APPLICATIONS INFORMATION
Depending on the application’s requirements, the non-
inverting VCO circuit in Figure 13 may be preferred for
this wide of a frequency variation as its maximum inac-
the maximum absolute frequency error (in Hertz) now
occurring at the highest output frequency, the relative
frequency error (in percent) is greatly improved.
curacy due to V error is only 9% and can be reduced
SET
Additionally,bychoosingtheVCO’sspecificationsshrewdly,
to only 3% with a small change to the voltage tuning
the frequency error (in percent) due to V variation is
SET
range specification.
reduced to ΔV /V
= 3%. To realize this improve-
SET SET
ment, the design must abide by three conditions. First,
the V voltage must be positive throughout the range.
Reducing V Error Effects in VCO Applications
SET
IN
Figure 13 shows a VCO that reduces the effect of ΔV
Second, choose V
VCO SET
/V
≥ f
/f . Last, choose
MAX MIN
SET
MAX MIN
/R ≥ R4/R3.
by adding an op-amp to make V
dependent on V
.
R
CTRL
SET
This circuit also has a positive transfer function (the out-
Figure 13 shows a design similar to the previous design
example where the V voltage is now specified to be
put frequency increases as V increases). Furthermore,
IN
MIN
for positive V voltages, this circuit places the greatest
IN
0.4V. This satisfies the V
/V
≥ f
/f
condition
MAX MIN
MAX MIN
absolute frequency error at the highest output frequency.
Compared to the simple VCO circuit of Figure 11, the
absolute frequency error is unchanged. However, with
and the design assures that the output frequency error
due to V variation is only 3%.
SET
10kHz TO 100kHz
3V
f
OUT
OE
OUT
LTC6990
3V
+
GND
SET
V
C1
0.1μF
R1
1M
V
SET
DIVCODE = 3
DIV
DIV
(N = 8, Hi-Z = 0)
3V
6990 F13
R2
280k
R
VCO
+
V
CTRL
75k
1/2
R3
LTC6078
100k
0.4V TO 4V
R
SET
–
V
IN
¨
·
¸
¥
´
249k
RVCO
V
V
SET
1MHz • 50k7
NDIV •RVCO
R4
R3
IN
fOUT
R4
ꢀ
• ©
ꢂ
ꢁ1 •
¦
µ
R
R4
30.1k
§
¶
©
ª
¸
¹
SET
RVCO
IF
ꢀ
, THE EQUATION REDUCES TO:
R3 RSET
C4
33pF
V
VSET
1MHz • 50k7
NDIV •RSET
IN
fOUT
=
•
ꢀ V • 25kHz/V
IN
Figure 13. VCO with Reduced ΔVSET Sensitivity
6990p
18
LTC6990
APPLICATIONS INFORMATION
Eliminating V Error Effects with DAC Frequency
The oscillator will still function with reduced accuracy
in its extended range (see the Electrical Characteristics
section).
SET
Control
Many DACs allow for the use of an external reference.
If such a DAC is used to provide the V
voltage, the
The LTC6990 is designed to function normally for I
SET
CTRL
V
error is eliminated by buffering V and using it as
as low as 1.25μA. At approximately 500nA, the oscillator
SET
SET
the DAC’s reference voltage, as shown in Figure 14. The
DAC’s output voltage now tracks any V variation and
output will be frozen in its current state. For N = 1 or 2,
DIV
OUT will halt in a low state. But for larger divider ratios,
it could halt in a high or low state. This avoids introduc-
ing short pulses while modulating a very low frequency
output. Note that the output will not be disabled as when
OE is low (e.g. the output will not enter a high impedance
state if Hi-Z = 1).
SET
eliminates it as an error source. The SET pin cannot be
tied directly to the reference input of the DAC because
the current drawn by the DAC’s REF input would affect
the frequency.
I
Extremes (Master Oscillator Frequency Extremes)
SET
At the other extreme, the master oscillator frequency can
reach 2MHz for I = 40ꢁA (R = 25k). It is not recom-
PushingI outsideoftherecommended1.25μAto20μA
SET
SET
SET
range forces the master oscillator to operate outside of
mended to operate the master oscillator beyond 2MHz
because the accuracy of the DIV pin ADC will suffer.
the 62.5kHz to 1MHz range in which it is most accurate.
OE
OUT
LTC6990
+
V
+
GND
SET
V
C1
0.1μF
+
V
R1
DIV
+
1/2
LTC6078
6990 F14
R2
–
+
V
¥
´
RVCO
DIN
1MHz • 50k7
NDIV •RVCO
fOUT
ꢀ
•
1ꢂ
ꢁ
¦
µ
RSET 4096
§
¶
V
REF
CC
DIN = 0 to 4095
D
IN
R
VCO
V
OUT
CLK
μP
LTC1659
CS/LD
R
SET
GND
Figure 14. Digitally Controlled Oscillator with VSET Variation Eliminated
6990p
19
LTC6990
APPLICATIONS INFORMATION
Modulation Bandwidth and Settling Time
Power Supply Current
The LTC6990 will respond to changes in I up to a –3dB
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under any
condition using the following equation:
SET
bandwidth of 0.4 • f
(see Figure 15). This makes it easy
OUT
to stabilize a feedback loop around the LTC6990, since it
does not introduce a low-frequency pole.
IS(TYP) ≈ V+• fMASTER •7pF + V+• fOUT•(13pF +CLOAD
V+ V+
480kΩ 2•RLOAD
)
Settling time depends on the master oscillator frequency.
Following a 2x or 0.5x step change in I , the output
SET
+
+
+1.75•ISET + 50µA
frequency takes approximately six master clock cycles
(6 • t
) to settle to within 1% of the final value. An
MASTER
example is shown in Figure 16.
The equation is also valid for OE = 0 (output disabled),
with f
= 0Hz.
OUT
0
V
= 0.536V + 0.278V
MOD
=18.75kHz 10%
CTRL
• SIN(2π•f
•t)
V
CTRL
f
OUT
2V/DIV
–10
–20
–30
–40
OUT
–3dB AT 0.4•f
OUT
2V/DIV
f
OUT
50kHz/DIV
R
R
= 200k
= 464k
SET
VCO
DIVCODE = 4(÷16)
6990 F16
10μs/DIV
= 3.3V, DIVCODE = 0
+
V
R
0.1
1
10
= 200k, R
= 464k
SET
VCO
f
/f
(Hz/Hz)
MOD OUT
f
= 175kHz AND 350kHz
OUT
6990 F15
Figure 15. Modulation Frequency Response
Figure 16. Settling Time
6990p
20
LTC6990
APPLICATIONS INFORMATION
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1μF ceramic capacitor.
The LTC6990 is a 2.2% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. The most important use issues involve
adequate supply bypassing and proper PCB layout.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place R
as close as possible to the SET pin and
SET
Figure17showsexamplePCBlayoutsforboththeSOT-23
andDCBpackagesusing0603sizedpassivecomponents.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6990. These layouts are
a guide and need not be followed exactly.
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
+
1. Connect the bypass capacitor, C1, directly to the V and
4. Connect R directly to the GND pin. Using a long path
SET
GND pins using a low inductance path. The connection
from C1 to the V pin is easily done directly on the top
or vias to the ground plane will not have a significant
affect on accuracy, but the direct, short connection is
recommended and easy to apply.
+
layer. For the DCB package, C1’s connection to GND is
also simply done on the top layer. For the SOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that,C1’sGNDconnectioncanbeaccomplishedthrough
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
OE
OUT
LTC6990
+
+
GND
V
V
C1
0.1μF
R1
R2
SET
DIV
R
SET
+
+
V
+
C1
V
R1
C1
V
OUT
GND
OE
OE
OUT
+
DIV
SET
GND
SET
V
R2
DIV
R1
R
SET
R
R2
SET
DCB PACKAGE
TSOT-23 PACKAGE
6990 F17
Figure 17. Supply Bypassing and PCB Layout
6990p
21
LTC6990
TYPICAL APPLICATIONS
Programming NDIV Using an 8-Bit DAC
DIVCODE
DAC CODE
0
0
1
OE
OUT
LTC6990
24
2
40
2.25V TO 5.5V
3
56
+
GND
SET
V
4
72
C1
0.1μF
5
88
6
104
120
136
152
168
184
200
216
232
255
7
DIV
8
C2
0.1μF
9
R
V
CC
SET
SDI
10
11
12
13
14
15
619k
LTC2630-LZ8 SCK
μP
V
OUT
CS/LD
GND
6990 TA02
Full Range VCO with Any NDIV Setting (fMAX to fMIN for VIN = 0V to VSET
)
5V
R
VCO2
26.1k
OE
OUT
LTC6990
5V
+
R
VCO1
GND
SET
V
5V
D1
IN4148
C1
0.1μF
26.1k
–
+
V
IN
R1
R2
0V TO 1V
LT1490
DIV
6990 TA03
R
SET
826k
Full Range VCO with Any NDIV Setting (Positive Frequency Control, fMIN to fMAX for VIN = 0V to VSET
5V
R4
10k
OE
OUT
LTC6990
5V
+
R3
10k
GND
SET
V
5V
C1
0.1μF
–
+
V
IN
R
VCO
53.6k
R1
R2
0V TO 1V
LT1490
DIV
6990 TA04
R
SET1
412k
R
SET2
412k
6990p
22
LTC6990
TYPICAL APPLICATIONS
Speaker Alarm. Modulate Tone with RVCO within 500Hz to 8kHz Span
5V
8ꢀ
IN4004
5V
20k
2N2222
OE
OUT
LTC6990
50k
+
GND
SET
V
5V
1M
R
VCO
STEP
DIV
RAMP
6990 TA05
97.6k
887k
Overvoltage Detector/Alarm. Direct Drive of Piezo Alarm
24V
5V
R
A
787k
+
100k
R
B
LT6703-3
OE
OUT
LTC6990
10.7k
400mV
PIEZO ALARM
4kHz
–
+
GND
SET
V
5V
MURATA
PKM29-3A0
1M
¥
´
R
R
A
B
DIV
V
ꢀ 400mV 1ꢂ
ꢀ 30V
ALARM
¦
µ
§
¶
6990 TA06
392k
523k
Direct Piezo Alarm Driver. Adjust Frequency for Maximum Alarm Sound Pressure
(Maximum Annoyance for Best Effect)
5V
10k
ON
OE
OUT
LTC6990
OFF
PIEZO ALARM
MURATA
PKM29-340
f = 4kHz
+
GND
SET
V
5V
1M
DIV
6990 TA07
392k
523k
6990p
23
LTC6990
TYPICAL APPLICATIONS
Isolated V → F Converter. VIN Provided by Isolated Measurement Circuit.
5μs Rise/Fall Time of Isolator Limits fMAX to 60kHz
3.3V
5V
365ꢀ
MOC207M
OE
OUT
LTC6990
+
GND
SET
V
5V
1M
f
75k
OUT
412ꢀ
V
IN
DIV
0V TO 5V
6990 TA08
157k
523k
Quadrature Sine Wave Oscillator. Voltage Controlled Frequency Range
from 2Hz to 18kHz with 1VP-P Constant Output Amplitude
SINE
COSINE
2.5V
51.1k
5V
5.11k
N
S1A
BP
LP
124k
–
+
LTC1059 OR
1/2 LTC1060
–
+
–
CLOCK
5V
S
A/B
AGND
10k
50/100
OUT
LTC6990
OE
2.5V
2k
LT1004
–2.5V
+
+
1M
5V
V
V
GND
5V
R1
R
VCO
1M
267k
V
FREQ
ADJ
–
+
CC
DIV
SET
OUT
REF
R2
280k
R
SET
49.9k
6990 TA09
LTC1440
HYST
1.18V
0.1μF
4.12k
1M
6990p
24
LTC6990
TYPICAL APPLICATIONS
Temperature to Frequency Converter.
3% Linearity from –20°C (fOUT ≈ 20kHz) to 75°C (fOUT ≈ 25kHz)
5V
f
OE
OUT
LTC6990
OUT
+
GND
SET
V
5V
1M
60.4k
DIV
22k AT 25°C
B = 3964
6990 TA10
21.5k
523k
+
THERMISTOR: VISHAY NTHS120601N2202J
Full Range Temperature to Frequency Converter. 16kHz to 1kHz from –20°C to 80°C
5V
f
OE
OUT
LTC6990
OUT
10k
+
GND
SET
V
5V
5V
–
+
1M
100k
LT1490
DIV
22k AT 25°C
B = 3964
6990 TA11
10k
681k
+
26k
26k
THERMISTOR: VISHAY NTHS120601N2202J
Light to Frequency Converter. fOUT ≈ –1.4kHz per Microampere of Photo Diode Current, IPD
1000pF
5V
f
OE
OUT
LTC6990
OUT
24.9k
+
GND
V
5V
I
5V
PD
–
+
187k
222k
LT1677
SET
DIV
SFH213
6990 TA12
619k
1M
6990p
25
LTC6990
PACKAGE DESCRIPTION
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715)
0.70 p0.05
1.65 p0.05
3.55 p0.05
(2 SIDES)
2.15 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
1.35 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
2.00 p0.10
(2 SIDES)
0.40 p 0.10
R = 0.05
TYP
4
6
3.00 p0.10 1.65 p 0.10
(2 SIDES)
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R0.20 OR 0.25
s 45o CHAMFER
(DCB6) DFN 0405
3
1
0.25 p 0.05
0.50 BSC
0.75 p0.05
0.200 REF
1.35 p0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
6990p
26
LTC6990
PACKAGE DESCRIPTION
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.4 MIN
1.50 – 1.75
2.80 BSC
3.85 MAX 2.62 REF
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302 REV B
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
6990p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC6990
TYPICAL APPLICATION
Ultrasonic Frequency Sweep Generator
f
= 500kHz TO 31.25kHz
OUT
OE
OE
OUT
LTC6990
+
GND
V
2.25V TO 5.5V
C1
0.1μF
R1
976k
SET
DIV
6990 TA13
R2
102k
R
SET1
74HC125
C
49.9k
R
750k
SET
0.022μF
SET2
SWEEPS FROM 500kHz to 31.25kHz IN A
FEW MILLISECONDS (CONTROLLED BY C ).
SET
RELATED PARTS
PART NUMBER
LTC1799
DESCRIPTION
COMMENTS
1MHz to 33MHz ThinSOT Silicon Oscillator
1MHz to 20MHz ThinSOT Silicon Oscillator
Wide Frequency Range
Low Power, Wide Frequency Range
LTC6900
LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator
Micropower, I
= 35μA at 400kHz
SUPPLY
LTC6930
Fixed Frequency Oscillator, 32.768kHz to 8.192MHz
0.09% Accuracy, 110μs Start-Up Time, 105μA at 32kHz
6990p
LT 0510 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
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