LTC6991HS6PBF [Linear]
TimerBlox: Resettable, Low Frequency Oscillator; TimerBlox系列：可重置，低频振荡器
| 型号： | LTC6991HS6PBF |
| 厂家： | 
Linear |
| 描述： | TimerBlox: Resettable, Low Frequency Oscillator |
| 文件： | 总24页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6991
TimerBlox: Resettable, Low
Frequency Oscillator
FeaTures
DescripTion
The LTC®6991 is a silicon oscillator with a programmable
periodrangeof1.024msto9.54hours(29.1µHzto977Hz),
specifically intended for long duration timing events. The
LTC6991 is part of the TimerBlox™ family of versatile
silicon timing devices.
n
Period Range: 1ms to 9.5 Hours
n
Configured with 1 to 3 Resistors
n
<1.5% Maximum Frequency Error
n
Output Reset Function
n
2.25V to 5.5V Single Supply Operation
n
55µA to 80µA Supply Current
A single resistor, R , programs the LTC6991’s internal
SET
(2ms to 9.5hr Clock Period)
master oscillator frequency. The output clock period
n
500µs Start-Up Time
is determined by this master oscillator and an internal
n
CMOS Output Driver Sources/Sinks 20mA
frequency divider, N , programmable to eight settings
DIV
n
–40°C to 125°C Operating Temperature Range
21
from 1 to 2 .
n
Available in Low Profile (1mm) SOT-23 (ThinSOT™)
NDIV •RSET
and 2mm × 3mm DFN Packages
tOUT
=
•1.024ms, NDIV =1,8,64,...,221
50kΩ
applicaTions
In normal operation, the LTC6991 oscillates with a 50%
duty cycle. A reset function is provided to truncate the
pulse (reducing the duty cycle). The reset pin can also be
used to prevent the output from oscillating.
n
“Heartbeat” Timers
n
Watchdog Timers
n
Intervalometers
Periodic “Wake-Up” Call
High Vibration, High Acceleration Environments
Portable and Battery-Powered Equipment
n
The RST and OUT pins can be configured for active-low
or active-high operation using a polarity function.
n
n
POL BIT
RST PIN
OUTPUT STATE
Oscillating
0 (reset)
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT and TimerBlox are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
0
0
1
1
0
1
0
1
1 (reset)
Oscillating
The LTC6991 is available in the 6-lead SOT-23 (ThinSOT)
package or a 6-lead 2mm × 3mm DFN.
Clock Period Range over Eight Divider Settings
10Hr
Typical applicaTion
Low Frequency Pulse Generator
1Hr
10Min
1µs PULSE WIDTH
OUT
60 SECONDS
R
PW
1Min
2.26k
10Sec
RST
GND
SET
OUT
6991 TA01a
C
PW
LTC6991
1Sec
100ms
10ms
1ms
2.25V TO 5.5V
470pF
+
V
0.1µF
R1
1M
R
SET
715k
DIV
R2
392k
1.25
DIV PIN VOLTAGE, V (V)
0
0.625
1.875
2.5
6991 TA01b
t
≈ R • C ≈ 1µs
PW PW
DIV
PULSE
6991f
ꢀ
LTC6991
absoluTe MaxiMuM raTings (Note 1)
+
Supply Voltage (V ) to GND........................................6V
Specified Temperature Range (Note 3)
Maximum Voltage
LTC6991C ................................................ 0°C to 70°C
LTC6991I .............................................–40°C to 85°C
LTC6991H.......................................... –40°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
+
on Any Pin ................(GND – 0.3V) ≤ V ≤ (V + 0.3V)
PIN
Operating Temperature Range (Note 2)
LTC6991C ............................................–40°C to 85°C
LTC6991I .............................................–40°C to 85°C
LTC6991H.......................................... –40°C to 125°C
S6 Package...........................................................300°C
pin conFiguraTion
TOP VIEW
TOP VIEW
+
6
5
4
OUT
GND
RST
V
1
2
3
RST 1
GND 2
SET 3
6 OUT
7
DIV
SET
+
5 V
4 DIV
DCB PACKAGE
6-LEAD (2mm s 3mm) PLASTIC DFN
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
T
JMAX
= 150°C, θ = 192°C/W, θ = 51°C/W
T
= 150°C, θ = 64°C/W, θ = 10.6°C/W
JA
JC
JMAX
JA
JC
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL
orDer inForMaTion
LEAD FREE FINISH
LTC6991CDCB#PBF
LTC6991IDCB#PBF
LTC6991HDCB#PBF
LTC6991CS6#PBF
LTC6991IS6#PBF
LTC6991HS6#PBF
TAPE AND REEL
PART MARKING*
LDWZ
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
LTC6991CDCB#TRPBF
LTC6991IDCB#TRPBF
LTC6991HDCB#TRPBF
LTC6991CS6#TRPBF
LTC6991IS6#TRPBF
LTC6991HS6#TRPBF
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
LDWZ
–40°C to 85°C
LDWZ
–40°C to 125°C
0°C to 70°C
LTDWY
LTDWY
6-Lead Plastic TSOT-23
–40°C to 85°C
LTDWY
6-Lead Plastic TSOT-23
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
6991f
ꢁ
LTC6991
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
1.024m
29.1µ
TYP
MAX
34,360
977
UNITS
Seconds
Hz
t
f
Output Clock Period
Output Frequency
OUT
OUT
Frequency Accuracy (Note 4)
29.1µHz ≤ f
≤ 977Hz
0.8
1.5
2.2
%
%
∆f
OUT
OUT
l
l
Frequency Drift Over Temperature
Frequency Drift Over Supply
0.005
%/°C
∆f /∆T
OUT
+
l
l
V = 4.5V to 5.5V
0.23
0.06
0.55
0.16
%/V
%/V
+
V = 2.25V to 4.5V
Period Jitter (Note 10)
N
DIV
N
DIV
= 1
= 8
15
7
ppm
ppm
RMS
RMS
BW
Frequency Modulation Bandwidth
0.4 • f
Hz
OUT
t
Frequency Change Settling Time (Note 9)
1
Cycle
S
Analog Inputs
l
l
l
l
l
V
Voltage at SET Pin
0.97
1.00
75
1.03
800
V
µV/°C
kΩ
SET
V
Drift Over Temperature
∆V /∆T
SET
SET
R
Frequency-Setting Resistor
DIV Pin Voltage
50
0
SET
DIV
+
V
V
V
+
DIV Pin Valid Code Range (Note 5)
Deviation from Ideal
DIV
1.5
%
∆V /∆V
DIV
+
V
/V = (DIVCODE + 0.5)/16
l
DIV Pin Input Current
10
nA
Power Supply
+
l
l
V
Operating Supply Voltage Range
Power-On Reset Voltage
Supply Current
2.25
5.5
V
V
1.95
+
+
l
l
I
R = ∞, R = 50k
V = 5.5V
135
105
170
135
µA
µA
S
L
SET
V = 2.25V
+
+
l
l
R = ∞, R = 100k
V = 5.5V
100
80
130
105
µA
µA
L
SET
V = 2.25V
+
+
l
l
R = ∞, R = 800k
V = 5.5V
65
55
100
85
µA
µA
L
SET
V = 2.25V
6991f
ꢂ
LTC6991
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital I/O
RST Pin Input Capacitance
RST Pin Input Current
2.5
pF
nA
V
+
RST = 0V to V
(Note 6)
10
+
l
l
V
V
High Level RST Pin Input Voltage
Low Level RST Pin Input Voltage
Output Output Current
0.7 • V
IH
+
(Note 6)
+
0.3 • V
V
IL
I
V = 2.7V to 5.5V
20
mA
OUT(MAX)
+
l
l
V
High Level Output Voltage (Note 7)
V = 5.5V
I
I
= –1mA
5.45
4.84
5.48
5.15
V
V
OH
OUT
OUT
= –16mA
+
l
l
V = 3.3V
I
I
= –1mA
= –10mA
3.24
2.75
3.27
2.99
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= –1mA
= –8mA
2.17
1.58
2.21
1.88
V
V
OUT
OUT
+
l
l
V
OL
Low Level Output Voltage (Note 7)
Reset Propagation Delay
V = 5.5V
I
I
= 1mA
= 16mA
0.02
0.26
0.04
0.54
V
V
OUT
OUT
+
l
l
V = 3.3V
I
I
= 1mA
= 10mA
0.03
0.22
0.05
0.46
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= 1mA
= 8mA
0.03
0.26
0.07
0.54
V
V
OUT
OUT
+
t
V = 5.5V
16
24
40
ns
ns
ns
RST
+
V = 3.3V
+
V = 2.25V
+
t
t
Minimum Input Pulse Width
Output Rise Time (Note 8)
V = 3.3V
5
ns
WIDTH
r
+
V = 5.5V
1.1
1.7
2.7
ns
ns
ns
+
V = 3.3V
+
V = 2.25V
+
t
Output Fall Time (Note 8)
V = 5.5V
1.0
1.6
2.4
ns
ns
ns
f
+
V = 3.3V
+
V = 2.25V
Note 6: The RST pin has hysteresis to accommodate slow rising or falling
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
+
signals. The threshold voltages are proportional to V . Typical values can
+
be estimated at any supply voltage using V
≈ 0.55 • V + 185mV
RST(RISING)
+
and V
≈ 0.48 • V – 155mV.
RST(FALLING)
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 2: The LTC6991C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 3: The LTC6991C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6991C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6991I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6991H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 9: Settling time is the amount of time required for the output to settle
within 1% of the final frequency after a 0.5× or 2× change in I
.
SET
Note 10: Jitter is the ratio of the deviation of the period to the mean of the
period. This specification is based on characterization and is not 100%
tested.
Note 4: Frequency accuracy is defined as the deviation from the f
OUT
equation, assuming R is used to program the frequency.
SET
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
6991f
ꢃ
LTC6991
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Frequency Error vs Temperature
Frequency Error vs Temperature
Frequency Error vs Temperature
3
2
1
0
3
2
1
0
3
2
1
0
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MAX OVER TEMPERATURE
R
= 800k
R
= 50k
R
= 200k
SET
SET
SET
3 PARTS
3 PARTS
3 PARTS
–1
–2
–3
–1
–2
–3
–1
–2
–3
GUARANTEED MIN OVER TEMPERATURE
GUARANTEED MIN OVER TEMPERATURE
GUARANTEED MIN OVER TEMPERATURE
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
6991 G03
6991 G01
6991 G02
Frequency Error vs RSET
Frequency Drift vs Supply Voltage
Typical VSET Distribution
250
200
150
100
50
0.5
0.4
3
2
2 LOTS
DFN AND SOT-23
1274 UNITS
GUARANTEED MAX OVER TEMPERATURE
3 PARTS
0.3
0.2
1
0
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–1
–2
–3
+
REFERENCED TO V = 4.5V
R
SET
R
SET
R
SET
= 50k
= 200k
= 800k
GUARANTEED MIN OVER TEMPERATURE
0
4
6
0.98
0.988
0.996
V
1.004
(V)
1.012
1.02
0
200
400
(kΩ)
600
800
2
3
5
SUPPLY VOLTAGE (V)
R
SET
SET
6991 G06
6991 G04
6991 G05
VSET Drift vs ISET
VSET Drift vs Supply
VSET vs Temperature
1.0
0.8
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
1.0
0.8
3 PARTS
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
+
REFERENCED TO V = 4V
REFERENCED TO I
= 10µA
SET
0
10
(µA)
20
2
3
4
5
6
–50
–25
0
25
50
75 100 125
15
5
SUPPLY (V)
TEMPERATURE (°C)
I
SET
6991 G08
6991 G09
6992 G07
6991f
ꢄ
LTC6991
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Supply Current
vs RST Pin Voltage
Supply Current vs Supply Voltage
Supply Current vs Temperature
250
200
150
100
50
150
125
150
125
100
75
R
= 800k
SET
R
= 50k
SET
5V
5V
RST FALLING
RST RISING
5V, R
= 100k
SET
100
75
R
SET
= 100k
2.5V, R
= 100k
SET
R
R
= 200k
= 800k
SET
3.3V
3.3V
RST RISING
5V, R
= 800k
= 800k
SET
RST FALLING
SET
50
25
0
2.5V, R
50
25
0
SET
0
0
0.2
0.4
0.6
0.8
1.0
2
3
4
5
6
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
+
SUPPLY VOLTAGE (V)
V
/V (V/V)
RST
6991 G12
6991 G10
6991 G11
RST Threshold Voltage
vs Supply Voltage
Supply Current vs RSET
Typical ISET Current Limit vs V+
1000
800
600
400
200
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
150
125
SET PIN SHORTED TO GND
+
POSITIVE-GOING
V
= 5V
100
75
+
V
= 3.3V
= 2.5V
NEGATIVE-GOING
+
V
50
25
0
2
3
4
5
6
2
3
4
5
6
0
200
400
600
800
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
R
SET
(kΩ)
6991 G15
6991 G14
6991 G13
Reset Propagation Delay (tRST
vs Supply Voltage
)
Rise and Fall Time
vs Supply Voltage
50
45
40
35
3.0
2.5
2.0
1.5
1.0
0.5
0
C
= 5pF
C
= 5pF
LOAD
LOAD
30
25
20
15
10
5
t
RISE
t
FALL
0
2
3
4
5
6
2
3
4
5
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6991 G17
6991 G16
6991f
ꢅ
LTC6991
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Output Resistance
vs Supply Current
50
Typical Start-Up with POL = 1
45
40
+
V
35
30
25
20
15
10
5
1V/DIV
OUTPUT SOURCING CURRENT
1µs (t
) WIDE
MASTER
INITIAL PULSE
500µs
OUT
1V/DIV
OUTPUT SINKING CURRENT
0
+
6991 G19
2
3
4
5
6
V
= 2.5V
DIVCODE = 15
= 50k
250µs/DIV
SUPPLY VOLTAGE (V)
6991 G22
R
SET
pin FuncTions (DCB/S6)
V (Pin1/Pin5):SupplyVoltage(2.25Vto5.5V).Thissup-
ply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1µF capacitor.
+
50ppm/°C or better temperature coefficient. For lower ac-
curacy applications an inexpensive 1% thick film resistor
may be used.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
+
Input. A V referenced A/D converter monitors the DIV
pin voltage (V ) to determine a 4-bit result (DIVCODE).
DIV
+
V
may be generated by a resistor divider between V
regulating the V voltage.
DIV
SET
and GND. Use 1% resistors to ensure an accurate result.
The DIV pin and resistors should be shielded from the
OUT pin or any other traces that have fast edges. Limit
the capacitance on the DIV pin to less than 100pF so that
+
V
RST
OUT
LTC6991
+
V
+
GND
SET
V
V
settles quickly. The MSB of DIVCODE (POL) deter-
DIV
C1
0.1µF
R1
R2
mines the polarity of the RST and OUT pins. If POL = 0,
RST is active-high, and forces OUT low. If POL = 1, RST
is active-low and forces OUT high.
DIV
6991 PF
R
SET
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (V ) is regulated to 1V above GND. The
SET
RST (Pin 4/Pin 1): Output Reset. The behavior of the RST
pin is dependent on the polarity bit (POL). The POL bit is
configuredviatheDIVCODEsetting.WhenPOL=0,setting
RST high forces OUT low and setting RST low allows the
output to oscillate. When POL = 1, RST is active low. In
that case, setting RST low forces OUT high and setting
RST high allows the output to oscillate.
amount of current sourced from the SET pin (I ) pro-
SET
grams the master oscillator frequency. The I
current
SET
range is 1.25µA to 20µA. The output oscillation will stop
if I drops below approximately 500nA. A resistor con-
SET
nected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
6991f
ꢆ
LTC6991
pin FuncTions (DCB/S6)
GND(Pin5/Pin2):Ground.Tietoalowinductanceground
plane for best performance.
30Ω. When driving an LED or other low impedance load a
series output resistor should be used to limit source/sink
current to 20mA.
OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
+
fromGNDtoV withanoutputresistanceofapproximately
(S6 package pin numbers shown)
block DiagraM
5
+
V
R1
POL BIT
DIV
4-BIT A/D
CONVERTER
DIGITAL
FILTER
4
R2
OUT
OUTPUT
POLARITY
6
+
V
t
OUT
MASTER OSCILLATOR
D
Q
1µs
V
SET
FIXED
DIVIDER
÷ 1024
MCLK
=
t
=
PROGRAMMABLE
DIVIDER
MASTER
50kΩ
I
SET
R
÷1, 8, 64, 512
15 18 21
4096, 2 , 2 , 2
INPUT
POLARITY
HALT OSCILLATOR
IF I < 500nA
POR
SET
I
SET
+
–
+
–
1V
GND
V
SET
= 1V
RST
1
SET
3
2
6991 BD
I
SET
R
SET
6991f
ꢇ
LTC6991
operaTion
The LTC6991 is built around a master oscillator with a
DIVCODE
1MHz maximum frequency. The oscillator is controlled
+
TheDIVpinconnectstoaninternal,V referenced4-bitA/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6991:
by the SET pin current (I ) and voltage (V ), with a
SET
SET
1MHz • 50k conversion factor that is accurate to 0.8%
under typical conditions.
1. DIVCODE determines the output frequency divider set-
ISET
VSET
1
ting, N .
fMASTER
=
=1MHz •50kΩ•
DIV
tMASTER
2. DIVCODE determines the polarity of the RST and OUT
pins, via the POL bit.
A feedback loop maintains V at 1V 30mV, leaving I
SET
SET
+
as the primary means of controlling the output frequency.
The simplest way to generate I is to connect a resistor
V
may be generated by a resistor divider between V
DIV
SET
and GND as shown in Figure 1.
(R ) between SET and GND, such that I = V /R .
SET
SET
SET SET
2.25V TO 5.5V
The master oscillator equation reduces to:
+
V
1
1MHz •50kΩ
LTC6991
R1
R2
fMASTER
=
=
tMASTER
RSET
DIV
From this equation, it is clear that V drift will not affect
SET
GND
theoutputfrequencywhenusingasingleprogramresistor
6991 F01
(R ). Error sources are limited to R tolerance and the
SET
SET
Figure 1. Simple Technique for Setting DIVCODE
inherent frequency accuracy ∆f
of the LTC6991.
OUT
R
may range from 50k to 800k (equivalent to I
SET
SET
Table 1 offers recommended 1% resistor values that ac-
curatelyproducethecorrectvoltagedivisionaswellasthe
between 1.25µA and 20µA).
Before reaching the OUT pin, the oscillator frequency
passes through a fixed ÷1024 divider. The LTC6991 also
includes a programmable frequency divider which can
correspondingN andPOLvaluesfortherecommended
DIV
resistor pairs. Other values may be used as long as:
+
1. The V /V ratio is accurate to 1.5% (including resis-
DIV
15
further divide the frequency by 1, 8, 64, 512, 4096, 2 ,
tor tolerances and temperature effects)
18
21
2 or 2 . The divider ratio N is set by a resistor divider
DIV
2. The driving impedance (R1||R2) does not exceed
500kΩ.
attached to the DIV pin.
ISET
1MHz •50kΩ
fOUT
tOUT
=
=
•
, or
If the voltage is generated by other means (i.e., the output
1024•NDIV VSET
VSET
fOUT 50kΩ ISET
+
of a DAC) it must track the V supply voltage. The last
NDIV
1
column in Table 1 shows the ideal ratio of V
to the
DIV
=
•
•1.024ms
supply voltage, which can also be calculated as:
VDIV
V+
DIVCODE+0.5
with R in place of V /I the equation reduces to:
SET
SET SET
=
±1.5%
16
NDIV •RSET
tOUT
=
•1.024ms
Forexample,ifthesupplyis3.3VandthedesiredDIVCODE
50kΩ
is 4, V = 0.281 • 3.3V = 928mV 50mV.
DIV
Figure2illustratestheinformationinTable1,showingthat
N
is symmetric around the DIVCODE midpoint.
DIV
6991f
ꢈ
LTC6991
operaTion
Table 1. DIVCODE Programming
+
DIVCODE
POL
0
N
RECOMMENDED t
R1 (kΩ)
Open
976
R2 (kΩ)
Short
102
V
/V
DIV
DIV
OUT
0
1
1
1.024ms to 16.384ms
8.192ms to 131ms
65.5ms to 1.05sec
524ms to 8.39sec
4.19sec to 67.1sec
33.6sec to 537sec
268sec to 4,295sec
2,147sec to 34,360sec
2,147sec to 34,360sec
268sec to 4,295sec
33.6sec to 537sec
4.19sec to 67.1sec
524ms to 8.39sec
65.5ms to 1.05sec
8.192ms to 131ms
1.024ms to 16.384ms
≤0.03125 0.015
0.09375 0.015
0.15625 0.015
0.21875 0.015
0.28125 0.015
0.34375 0.015
0.40625 0.015
0.46875 0.015
0.53125 0.015
0.59375 0.015
0.65625 0.015
0.71875 0.015
0.78125 0.015
0.84375 0.015
0.90625 0.015
≥0.96875 0.015
0
8
2
0
64
512
976
182
3
0
1000
1000
1000
1000
1000
887
280
4
0
4,096
32,768
262,144
2,097,152
2,097,152
262,144
32,768
4,096
512
392
5
0
523
6
0
681
7
0
887
8
1
1000
1000
1000
1000
1000
976
9
1
681
10
11
12
13
14
15
1
523
1
392
1
280
1
64
182
1
8
102
976
1
1
Short
Open
POL BIT = 0
POL BIT = 1
10000
1000
100
10
7
8
6
9
5
10
11
4
12
3
1
2
13
0.1
1
14
0.01
0.001
0
15
+
+
0V
0.5•V
V
INCREASING V
DIV
6991 F02
Figure 2. Frequency Range and POL Bit vs DIVCODE
6991f
ꢀ0
LTC6991
operaTion
RST Pin and Polarity (POL) Bit
If POL = 0, the reset pin is active high and the output latch
is not inverted. Therefore, pulling the RST pin high will
reset the output latch and force the OUT pin low. Pulling
RST low will allow the output to oscillate, with the next
rising edge dependent on the internal oscillator.
The RST pin controls the state of the LTC6991’s output
as seen on the OUT pin. The active/inactive voltage levels
depend on the POL bit setting.
Table 2. Output States
If POL = 1, the reset pin is active low and the output latch
is inverted. Therefore, pulling the RST pin low will reset
the output latch and force the OUT pin high. Pulling RST
high will allow the output to oscillate, with the next falling
edge dependent on the internal oscillator.
POL BIT
RST PIN
OUTPUT STATE
Oscillating
0 (reset)
0
0
1
1
0
1
0
1
1 (reset)
Oscillating
Note that the master oscillator frequency and phase are
not affected by the RST pin; The LTC6991 continues to
oscillate, internally, even when RST is active. While the
reset function can block an output pulse, its exact place-
ment in time can only be changed by power cycling the
LTC6991.
Each period of the LTC6991’s internal oscillator clocks the
outputstatelatch(seeBlockDiagram).Theresetpin(RST)
can reset or hold off the output latch. The active state of
the reset pin is determined by the polarity function (POL).
Similarly, the output latch is followed by a buffer that can
invert the output. The output polarity is also controlled
by the POL bit.
t
WIDTH
RST
OUT
INTERNAL
OSCILLATOR
t
RST
6991 F03
t
OUT
Figure 3. RST Timing Diagram (POL = 0)
RST
OUT
t
RST
6991 F04
INTERNAL
OSCILLATOR
t
OUT
Figure 4. RST Timing Diagram (POL = 1)
6991f
ꢀꢀ
LTC6991
operaTion
Changing DIVCODE After Start-Up
start-up time may increase if the supply or DIV pin volt-
ages are not stable. For this reason, it is recommended to
minimize the capacitance on the DIV pin so it will properly
Following start-up, the A/D converter will continue
monitoring V for changes. The LTC6991 will respond
DIV
+
track V . Less than 100pF will not affect performance.
to DIVCODE changes in less than one cycle.
t
< 500 • t
< t
OUT
Start-Up Behavior
DIVCODE
MASTER
The output may have an inaccurate pulse width during the
frequency transition. But the transition will be glitch-free
and no high or low pulse can be shorter than the mas-
ter clock period. A digital filter is used to guarantee the
DIVCODEhassettledtoanewvaluebeforemakingchanges
to the output.
When first powered up, the output is held low. If the po-
larity is set for non-inversion (POL = 0) and the output is
enabled (RST = 0) at the end of the start-up time, OUT will
begin oscillating. If the output is being reset (RST = 1) at
the end of the start-up time, the first pulse will be skipped.
Subsequent pulses will also be skipped until RST = 0.
In inverted operation (POL = 1), the start-up sequence is
similar. However, the LTC6991 does not know the correct
DIVCODE setting when first powered up, so the output
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, t
. The OUT pin
defaults low. At the end of t
, the value of DIVCODE is
START
START
is held low during this time. The typical value for t
recognizedandOUTgoeshigh(inactive)becausePOL = 1.
If RST = 1 (inactive) then OUT will quickly fall after a single
START
ranges from 0.5ms to 8ms depending on the master oscil-
lator frequency (independent of N ):
t
cycle. If RST = 0 at the end of the start-up time,
DIV
MASTER
the output is held in reset and remains high.
t
= 500 • t
MASTER
START(TYP)
Figures7to10detailthefourpossiblestart-upsequences.
Duringstart-up,theDIVpinA/Dconvertermustdetermine
the correct DIVCODE before the output is enabled. The
+
V
1V/DIV
DIV
200mV/DIV
500µs
OUT
OUT
1V/DIV
1V/DIV
+
6991 F06
V
= 2.5V
250µs/DIV
DIVCODE = 0
= 50k
+
6991 F05
V
R
= 3.3V
= 200k
10ms/DIV
R
SET
SET
Figure 5. DIVCODE Change from 1 to 0
Figure 6. Typical Start-Up
6991f
ꢀꢁ
LTC6991
operaTion
RST
OUT
6991 F07
t
t
t
t
OUT
START
Figure 7. Start-Up Timing Diagram (RST = 0, POL = 0)
RST
OUT
6991 F08
OUTPUT DISABLED FOR
INTEGER MULTIPLE OF t
START
OUT
Figure 8. Start-Up Timing Diagram (RST = 1, POL = 0)
RST
OUT
6991 F09
OUTPUT DISABLED FOR
INTEGER MULTIPLE OF t
START
OUT
t
MASTER
Figure 9. Start-Up Timing Diagram (RST = 0, POL = 1)
RST
OUT
6991 F10
t
t
OUT
START
t
MASTER
Figure 10. Start-Up Timing Diagram (RST = 1, POL = 1)
6991f
ꢀꢂ
LTC6991
applicaTions inForMaTion
Basic Operation
Example: Design a 1Hz oscillator with minimum power
consumption and active-high reset input.
The simplest and most accurate method to program the
LTC6991 is to use a single resistor, R , between the SET
Step 1: Select the POL Bit Setting
SET
and GND pins. The design procedure is a 3-step process.
For noninverted (active-high) functionality, choose
POL = 0.
FirstselectthePOLbitsettingandN value,thencalculate
DIV
the value for the R resistor.
SET
Step 2: Select the N Frequency Divider Value
DIV
Step 1: Select the POL Bit Setting
Choose an N
value that meets the requirements of
DIV
TheLTC6991canoperateinnormal(active-high)orinverted
(active-low) modes, depending on the setting of the POL
bit. The best choice depends on the the application.
Equation (1), using t
= 1000ms:
OUT
61.04 ≤ N ≤ 976.6
DIV
Potential settings for N include 64 and 512. N = 64
DIV
DIV
Step 2: Select the N Frequency Divider Value
DIV
is the best choice, as it minimizes supply current by us-
ing a large R resistor. POL = 0 and N = 64 requires
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
SET
DIV
DIVCODE = 2. Using Table 1, choose R1 = 976k and
R2 = 182k values to program DIVCODE = 2.
N
value. For a given output clock period, N should
DIV
DIV
be selected to be within the following range.
Step 3: Select R
SET
tOUT
16.384ms
tOUT
1.024ms
≤NDIV
≤
(1)
Calculate the correct value for R using Equation (2).
SET
50k
1.024ms
1000ms
64
Tominimizesupplycurrent,choosethelowestN value
DIV
RSET
=
•
= 763k
(generally recommended). Alternatively, use Table 1
as a guide to select the best N
application.
value for the given
DIV
Since 763k is not available as a standard 1% resistor,
substitute 768k if a –0.7% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 576k + 187k to attain a more precise resistance.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
+
or V /V ratio to apply to the DIV pin.
DIV
The completed design is shown in Figure 11.
Step 3: Calculate and Select R
SET
The final step is to calculate the correct value for R
using the following equation.
SET
RST
RST
GND
SET
OUT
LTC6991
2.25V TO 5.5V
+
V
tOUT
50k
R1
976k
RSET
=
•
(2)
1.024ms NDIV
DIVCODE = 2
DIV
R
R2
SET
Select the standard resistor value closest to the calculated
value.
763k
182k
6991 F11
Figure 11. 1Hz Oscillator
6991f
ꢀꢃ
LTC6991
applicaTions inForMaTion
LTC6991 as “Wake-Up Timer”
input to filter start-up glitches from the system as it is
powered on.
The output latch reset function provided by the RST pin
allows the LTC6991 to enable a larger system at regular
intervals. The on-time can be controlled by the system.
Thisallowsthesystemtoshutitselfdownimmediatelyafter
performing its tasks, reducing power consumption.
If the LTC6991 is enabling a switching regulator that can
operate on supplies greater than 5.5V, it will be necessary
to limit the supply voltage provided to the LTC6991. If
the LTC6991 output is not heavily loaded, and if a large
R
resistor is used, the supply current will not be much
SET
Figure 12 shows an example using “black boxes” for a
switching regulator and the system being duty-cycled.
In some cases, an RC filter may be necessary at the RST
larger than 100µA, so a simple regulator circuit can be
constructed using a Zener diode.
3V TO 20V
V
REG
V
V
OUT
IN
t
OUT
R
SWITCHING
REGULATOR
SUPPLY
3570 SECONDS
4.99k
+
SHDN
V
OUT
1N4733A
5.1V
R1
1M
0.1µF
LTC6991
+
V
DIV
GND
R2
681k
SYSTEM
DONE
R
R
SET
FILT
665k
100k
SET
RST
C
FILT
6991 F12
0.1µF
THE SYSTEM CAN EXTEND t AS LONG AS NEEDED (UP TO 50% OF t
)
OUT
ON
t
ON
t
ON
t
ON
V
REG
DONE/RST
LTC6991 OUT
t
t
t
OUT
OUT
OUT
Figure 12. Powering Up a System Once an Hour
6991f
ꢀꢄ
LTC6991
applicaTions inForMaTion
Self-Resetting Circuits
OUT
R
PW
2.26k
TheRSTpinhashysteresistoaccommodateslow-changing
inputvoltages.Furthermore,thetrippointsareproportional
to the supply voltage (see Note 6 and the RST Threshold
Voltage vs Supply Voltage curve in Typical Performance
Characteristics). This allows an RC time constant at the
RST input to generate a delay that is nearly independent
of the supply voltage.
RST
GND
SET
OUT
C
PW
LTC6991
2.25V TO 5.5V
470pF
+
V
0.1µF
R1
1M
R
SET
715k
DIV
R2
392k
V
RST(RISING)
A simple application of this technique allows the LTC6991
output to reset itself, producing a well-controlled pulse
once each cycle. Figures 13a and 13b show circuits that
produce approximately 1µs pulses once a minute. The
only difference is in the POL bit setting, which controls
whether the pulse is positive or negative.
t
= –R • C • In 1–
PULSE
PW
PW
+
ꢀ
ꢁ
V
t
t
≈ –2.26kΩ • 470pF • In(1 – 0.61)
≈ 1µs
PULSE
PULSE
1µs PULSE WIDTH
60 SECONDS
6991 F13a
Voltage Controlled Frequency
Figure 13a. Self-Resetting Circuit (DIVCODE = 4)
Withoneadditionalresistor,theLTC6991outputfrequency
can be manipulated by an external voltage. As shown in
OUT
R
PW
Figure 14, voltage V
sources/sinks a current through
2.26k
CTRL
RST
GND
SET
OUT
R
VCO
to vary the I current, which in turn modulates the
SET
C
PW
LTC6991
2.25V TO 5.5V
output frequency as described in Equation (3).
470pF
+
V
0.1µF
R1
R
715k
RVCO VCTRL
–
1MHz •50kΩ
1024•NDIV •RVCO
SET
(3)
392k
fOUT
=
• 1+
DIV
RSET VSET
R2
1M
Digital Frequency Control
V
RST(FALLING)
t
= –R • C • In
PW PW
PULSE
+
ꢀ
ꢁ
V
The control voltage can be generated by a DAC (digital-
to-analog converter), resulting in a digitally-controlled
frequency. Many DACs allow for the use of an external
t
t
≈ –2.26kΩ • 470pF • In(0.43)
≈ 0.9µs
PULSE
PULSE
0.9µs PULSE WIDTH
60 SECONDS
reference. If such a DAC is used to provide the V
CTRL
voltage, the V dependency can be eliminated by buffer-
SET
ing V
and using it as the DAC’s reference voltage, as
SET
6991 F13b
shown in Figure 15. The DAC’s output voltage now tracks
any V variation and eliminates it as an error source.
Figure 13b. Self-Resetting Circuit (DIVCODE = 11)
SET
The SET pin cannot be tied directly to the reference input
of the DAC because the current drawn by the DAC’s REF
input would affect the frequency.
RST
GND
SET
OUT
+
LTC6991
V
+
V
C1
0.1µF
R1
I
Extremes (Master Oscillator Frequency Extremes)
SET
R
VCO
V
DIV
CTRL
When operating with I
outside of the recommended
SET
R
SET
R2
1.25µA to 20µA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
6991 F14
Figure 14. Voltage-Controlled Oscillator
6991f
ꢀꢅ
LTC6991
applicaTions inForMaTion
RST
GND
SET
OUT
+
LTC6991
V
+
+
V
V
C1
0.1µF
0.1µF
R1
DIV
+
–
1/2
LTC6078
R2
+
V
6991 F15
0.1µF
1MHz • 50kΩ
R
D
IN
4096
VCO
SET
f
=
• 1 +
–
OUT
ꢀ
ꢁ
1024 • N • R
R
DIV
VCO
V
REF
CC
D
= 0 TO 4095
IN
D
IN
R
VCO
V
OUT
µP
LTC1659
CLK
CS/LD
R
SET
GND
Figure 15. Digitally-Controlled Oscillator
ignores C
(valid for C
< 1nF) and assumes the
The oscillator can still function with reduced accuracy
LOAD
LOAD
output has 50% duty cycle.
for I < 1.25µA. At approximately 500nA, the oscillator
SET
output will be frozen in its current state. The output could
halt in a high or low state. This avoids introducing short
pulses when frequency modulating a very low frequency
output.
V+
V+
IS(TYP) ≈ V+ • fMASTER •7.8pF +
+ 1.8•ISET +50µA
+
420kΩ 2•RLOAD
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Supply Bypassing and PCB Layout Guidelines
The LTC6991 is a 2.2% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Frequency Modulation and Settling Time
The LTC6991 will respond to changes in I up to a –3dB
SET
bandwidth of 0.4 • f
.
OUT
Figure18showsexamplePCBlayoutsforboththeTSOT-23
and DFN packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6991. These layouts are
a guide and need not be followed exactly.
Following a 2× or 0.5× step change in I , the output
SET
frequency takes less than one cycle to settle to within 1%
of the final value.
Power Supply Current
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under
any condition using the following equation. This equation
6991f
ꢀꢆ
LTC6991
applicaTions inForMaTion
RST
GND
SET
OUT
LTC6991
+
+
V
V
C1
0.1µF
R1
R2
DIV
R
SET
+
V
+
C1
V
R1
C1
+
V
OUT
GND
RST
RST
OUT
+
DIV
SET
GND
SET
V
R2
DIV
R1
R
SET
R
SET
R2
6991 F18
DFN PACKAGE
TSOT-23 PACKAGE
Figure 18. Supply Bypassing and PCB Layout
+
1. Connect the bypass capacitor, C1, directly to the V and
GND pins using a low inductance path. The connection
3. Place R
as close as possible to the SET pin and
SET
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
+
from C1 to the V pin is easily done directly on the top
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that,C1’sGNDconnectioncanbeaccomplishedthrough
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
4. Connect R directly to the GND pin. Using a long path
SET
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
6991f
ꢀꢇ
LTC6991
Typical applicaTions
5 Second On/Off Timed Relay Driver
12V
0.1µF
L
C
1
D1
NO
1N4148
RESET
R4
15k
RUN
RELAY ENABLE
COTO 1022 RELAY
9001-12-01
Q1
RST
GND
SET
OUT
2N2219A
LTC6991
5V
+
V
C2
R1
1M
0.1µF
DIV
R2
392k
R3
118k
6991 TA02
1.5ms Radio Control Servo Reference Pulse Generator
5V
20ms
FRAME RATE
GENERATOR
1.5ms
REFERENCE
PULSE
R7
10k
20ms PERIOD
RESET = OPEN
RUN = GND
RST
OUT
TRIG
OUT
1.5ms PULSE
LTC6991
LTC6993-1
5V
5V
+
+
GND
SET
V
GND
SET
V
C1
0.01µF
C2
0.1µF
R4
976k
R1
1M
DIV
DIV
R6
121k
R3
146k
R5
102k
R2
280k
6991 TA03
6991f
ꢀꢈ
LTC6991
Typical applicaTions
Cycling (10 Seconds On/Off) Symmetrical Power Supplies
M2
Si4435DY
15V
15V
IN
OUT
R6
20k
R2
1k
M3
R11
5k
RST
GND
SET
OUT
Si9410
LTC6991
+
5V
V
C1
R8
0.1µF
1M
M4
DIV
Si4435DY
R10
237k
R9
392k
R1
100k
R3
50k
–15V
–15V
OUT
IN
M1
Si9410
F6991 TA04
Isolated AC Load Flasher
5V
0.1µF
R3
5
+
R4
R5
U2
40W LAMP
10k
215Ω
5.94k
MOC3041M
V
1
2
1
6
4
6
4
OPEN = OFF
GND = ON
HOT
117V AC
RST
OUT
R1
LTC6991
R7
100Ω
1M
3
U3
NTE5642
SET
DIV
5V
ZERO
CROSSING
GND
2
R
SET
R2
392k
C2
0.022µF
237k
R6
10k
NEUTRAL
AC
10 SECONDS ON/OFF
6991 TA05
ISOLATION BARRIER = 7500V
6991f
ꢁ0
LTC6991
Typical applicaTions
Interval (Wiper) Timer
2s
5s
15s
30s
5V
+
V
1m
2m
4m
OFF
OUTPUT
0.1µF
RST
GND
SET
OUT
TRIG
OUT
66.5k
280k
182k
2s
LTC6991
LTC6993-1
+
+
+
+
2s
V
V
V
GND
SET
V
5s
15s
t
0.1µF
INTERVAL
1M
1M
2 SECONDS TO
4 MINUTES
30s
DIV
DIV
1m
2m
4m
383k
681k
2s
18.2k
182k
OFF
6991 TA06
2s
280k
113k
133k
5s
15s
30s
1m
2m
4m
OFF
6991f
ꢁꢀ
LTC6991
package DescripTion
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
0.70 p0.05
1.65 p0.05
3.55 p0.05
(2 SIDES)
2.15 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
1.35 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
2.00 p0.10
(2 SIDES)
0.40 p 0.10
R = 0.05
TYP
4
6
3.00 p0.10 1.65 p 0.10
(2 SIDES)
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R0.20 OR 0.25
s 45o CHAMFER
(DCB6) DFN 0405
3
1
0.25 p 0.05
0.50 BSC
0.75 p0.05
0.200 REF
1.35 p0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
6991f
ꢁꢁ
LTC6991
package DescripTion
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.4 MIN
1.50 – 1.75
2.80 BSC
3.85 MAX 2.62 REF
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302 REV B
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
6991f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢁꢂ
LTC6991
Typical applicaTion
Intervalometer for Time-Lapse Photography
ACTIVATES SHUTTER AT
8SEC TO 8.5MIN INTERVALS
R
PW
100k
SHUTTER
RST
GND
SET
OUT
C
PW
LTC6991
33µF
+
V
1µF
R1A
R1B
1M
R
S3
332k
95.3k
DIV
“SLOW RANGE”
1.1MIN TO 8.5 MIN
8SEC TO
64SEC
R
R
S1
S2
1M
2M
R2
130k
6991 TA07
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTC1799
1MHz to 33MHz ThinSOT Silicon Oscillator
1MHz to 20MHz ThinSOT Silicon Oscillator
Wide Frequency Range
Low Power, Wide Frequency Range
LTC6900
LTC6906/LTC6907
LTC6930
10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillators
Fixed Frequency Oscillator, 32.768kHz to 8.192MHz
TimerBlox: Voltage-Controlled Silicon Oscillator
Micropower, I
= 35µA at 400kHz
SUPPLY
0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
Fixed-Frequency or Voltage-Controlled Operation
Simple PWM with Wide Frequency Range
LTC6990
LTC6992
TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM)
TimerBlox: Monostable Pulse Generator (One Shot)
TimerBlox: Delay Block/Debouncer
LTC6993
Resistor Programmable Pulse Width of 1µs to 34sec
Delays Rising, Falling or Both Edges 1µs to 34sec
LTC6994
6991f
LT 0910 • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
ꢁꢃ
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
相关型号：
LTC6991IS6#TRMPBF
LTC6991 - TimerBlox: Resettable, Low Frequency Oscillator; Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C
Linear
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