LTC6993 [Linear]
TimerBlox: Long Timer, Low Frequency Oscillator;
| 型号： | LTC6993 |
| 厂家： | 
Linear |
| 描述： | TimerBlox: Long Timer, Low Frequency Oscillator |
| 文件： | 总28页 (文件大小：367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6995-1/LTC6995-2
TimerBlox: Long Timer, Low
Frequency Oscillator
FeaTures
DescripTion
The LTC®6995 is a silicon oscillator with a programmable
periodrangeof1.024msto9.54hours(29.1µHzto977Hz),
specifically intended for long duration timing events. The
LTC6995 is part of the TimerBlox® family of versatile
silicon timing devices.
n
Period Range: 1ms to 9.5 Hours
n
Timing Reset by Power-On or Reset Input
n
Configured with 1 to 3 Resistors
n
<1.5% Maximum Frequency Error
n
Programmable Output Polarity
n
2.25V to 5.5V Single Supply Operation
A single resistor, R , programs the LTC6995’s internal
SET
n
55µA to 80µA Supply Current
master oscillator frequency. The output clock period
is determined by this master oscillator and an internal
(2ms to 9.5hr Clock Period)
n
500µs Start-Up Time
frequency divider, N , programmable to eight settings
DIV
n
CMOS Output Driver Sources/Sinks 20mA
21
from 1 to 2 .
n
–55°C to 125°C Operating Temperature Range
NDIV •RSET
n
Available in Low Profile (1mm) SOT-23 (ThinSOT™)
tOUT
=
•1.024ms, NDIV = 1,8,64,...,221
and 2mm × 3mm DFN Packages
50kΩ
When oscillating, the LTC6995 generates a 50% duty
cycle square wave output. A reset function is provided
to stop the master oscillator and clear internal dividers.
Removing reset initiates a full output clock cycle which
is useful for programmable power on reset and watchdog
timer applications.
applicaTions
n
Power-On Reset Timer
n
Long Time One Shot
n
“Heartbeat” Timers
Watchdog Timers
Periodic “Wake-Up” Call
High Vibration, High Acceleration Environments
n
n
The LTC6995 has two versions of reset functionality. The
reset input is active high for the LTC6995-1 and active low
for the LTC6995-2. The polarity of the output when reset
is selectable for both versions.
n
L, LT, LTC, LTM, Linear Technology, TimerBlox and the Linear logo are registered trademarks
and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
OUTPUT (OSCILLATOR START STATE)
RST/RST POLARITY
LTC6995-1
Oscillating (Low)
0 (Reset)
LTC6995-2
0 (Reset)
0
1
0
1
0
0
1
1
Oscillating (Low)
1 (Reset)
Oscillating (High)
1 (Reset)
Oscillating (High)
Typical applicaTion
Active Low Power-On Reset Timer
+
RST
GND
SET
OUT
V
LTC6995-1
+
+
V
V
5 SECONDS
1/2 t
0.1µF
OUT
TIMER STOPPED
1M
OUT
DIV
POWER-ON RESET
(1ms TO 4.8 HOURS)
118k
392k
699512 TA01
699512f
1
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
absoluTe MaxiMuM raTings (Note 1)
+
Supply Voltage (V ) to GND ........................................6V
Specified Temperature Range (Note 3)
Maximum Voltage
LTC6995C................................................ 0°C to 70°C
LTC6995I .............................................–40°C to 85°C
LTC6995H.......................................... –40°C to 125°C
LTC6995MP....................................... –55°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
+
on Any Pin ................(GND – 0.3V) ≤ V ≤ (V + 0.3V)
PIN
Operating Temperature Range (Note 2)
LTC6995C............................................–40°C to 85°C
LTC6995I .............................................–40°C to 85°C
LTC6995H.......................................... –40°C to 125°C
LTC6995MP....................................... –55°C to 125°C
S6 Package...........................................................300°C
pin conFiguraTion
LTC6995-1/LTC6995-2
LTC6995-1/LTC6995-2
TOP VIEW
TOP VIEW
+
6
5
4
OUT
V
1
2
3
RST/RST 1
GND 2
6 OUT
7
GND
DIV
SET
GND
+
5 V
RST/RST
SET 3
4 DIV
DCB PACKAGE
S6 PACKAGE
6-LEAD (2mm × 3mm) PLASTIC DFN
= 150°C, θ = 64°C/W, θ = 9.6°C/W
6-LEAD PLASTIC TSOT-23
T
= 150°C, θ = 192°C/W, θ = 51°C/W
T
JMAX
JMAX
JA
JC
JA
JC
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL
orDer inForMaTion
Lead Free Finish
TAPE AND REEL (MINI)
LTC6995CDCB-1#TRMPBF LTC6995CDCB-1#TRPBF LGJM
LTC6995IDCB-1#TRMPBF LTC6995IDCB-1#TRPBF LGJM
TAPE AND REEL
PART MARKING* PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
LTC6995HDCB-1#TRMPBF LTC6995HDCB-1#TRPBF LGJM
LTC6995CDCB-2#TRMPBF LTC6995CDCB-2#TRPBF LGJP
LTC6995IDCB-2#TRMPBF LTC6995IDCB-2#TRPBF
LGJP
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC6995HDCB-2#TRMPBF LTC6995HDCB-2#TRPBF LGJP
LTC6995CS6-1#TRMPBF LTC6995CS6-1#TRPBF
LTC6995IS6-1#TRMPBF LTC6995IS6-1#TRPBF
LTC6995HS6-1#TRMPBF LTC6995HS6-1#TRPBF
LTGJN
LTGJN
LTGJN
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
–55°C to 125°C
0°C to 70°C
6-Lead Plastic TSOT-23
LTC6995MPS6-1#TRMPBF LTC6995MPS6-1#TRPBF LTGJN
6-Lead Plastic TSOT-23
LTC6995CS6-2#TRMPBF LTC6995CS6-2#TRPBF
LTC6995IS6-2#TRMPBF LTC6995IS6-2#TRPBF
LTC6995HS6-2#TRMPBF LTC6995HS6-2#TRPBF
LTGJQ
LTGJQ
LTGJQ
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
–55°C to 125°C
6-Lead Plastic TSOT-23
LTC6995MPS6-2#TRMPBF LTC6995MPS6-2#TRPBF LTGJQ
6-Lead Plastic TSOT-23
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
699512f
2
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V for LTC6995-1,
RST = V+ for LTC6995-2, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
1.024m
29.1µ
TYP
MAX
34,360
977
UNITS
Seconds
Hz
t
f
Output Clock Period
Output Frequency
OUT
OUT
∆f
Frequency Accuracy (Note 4)
29.1µHz ≤ f
≤ 977Hz
OUT
0.8
1.5
2.2
%
%
OUT
l
l
∆f /∆T
Frequency Drift Over Temperature
Frequency Drift Over Supply
0.005
%/°C
OUT
+
+
l
l
∆f /∆V
V = 4.5V to 5.5V
0.23
0.06
0.55
0.16
%/V
%/V
OUT
+
V = 2.25V to 4.5V
Long-Term Frequency Stability
Period Jitter (Note 10)
(Note 11)
90
ppm/√kHr
N
DIV
N
DIV
= 1
= 8
15
7
ppm
ppm
RMS
RMS
BW
Frequency Modulation Bandwidth
0.4 • f
Hz
OUT
t
Frequency Change Settling Time (Note 9)
1
Cycle
S
Analog Inputs
l
l
l
l
l
V
Voltage at SET Pin
0.97
1.00
75
1.03
800
V
µV/°C
kΩ
SET
∆V /∆T
V
Drift Over Temperature
SET
SET
R
Frequency-Setting Resistor
DIV Pin Voltage
50
0
SET
DIV
+
V
V
V
+
∆V /∆V
DIV Pin Valid Code Range (Note 5)
Deviation from Ideal
DIV
1.5
%
DIV
+
V
/V = (DIVCODE + 0.5)/16
l
DIV Pin Input Current
10
nA
Power Supply
+
l
l
V
Operating Supply Voltage Range
Power-On Reset Voltage
Supply Current
2.25
5.5
V
V
1.95
+
+
l
l
I
R = ∞, R = 50k
V = 5.5V
135
105
170
135
µA
µA
S
L
SET
V = 2.25V
+
+
l
l
R = ∞, R = 100k
V = 5.5V
100
80
130
105
µA
µA
L
SET
V = 2.25V
+
+
l
l
R = ∞, R = 800k
V = 5.5V
65
55
100
85
µA
µA
L
SET
V = 2.25V
+
+
R = ∞, I = 0µA
V = 5.5V
60
52
µA
µA
L
SET
V = 2.25V
699512f
3
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V for LTC6995-1,
RST = V+ for LTC6995-2, DIVCODE = 0 to 15 (NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital I/O
RST Pin Input Capacitance
RST Pin Input Current
2.5
pF
nA
V
+
RST = 0V to V
(Note 6)
10
+
l
l
V
V
High Level RST Pin Input Voltage
Low Level RST Pin Input Voltage
Output Output Current
0.7 • V
IH
+
(Note 6)
+
0.3 • V
V
IL
I
V = 2.7V to 5.5V
20
mA
OUT(MAX)
+
l
l
V
High Level Output Voltage (Note 7)
V = 5.5V
I
I
= –1mA
5.45
4.84
5.48
5.15
V
V
OH
OUT
OUT
= –16mA
+
l
l
V = 3.3V
I
I
= –1mA
= –10mA
3.24
2.75
3.27
2.99
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= –1mA
= –8mA
2.17
1.58
2.21
1.88
V
V
OUT
OUT
+
l
l
V
OL
Low Level Output Voltage (Note 7)
Reset Propagation Delay
V = 5.5V
I
I
= 1mA
= 16mA
0.02
0.26
0.04
0.54
V
V
OUT
OUT
+
l
l
V = 3.3V
I
I
= 1mA
= 10mA
0.03
0.22
0.05
0.46
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= 1mA
= 8mA
0.03
0.26
0.07
0.54
V
V
OUT
OUT
+
t
V = 5.5V
16
24
40
ns
ns
ns
RST
+
V = 3.3V
+
V = 2.25V
+
t
t
Minimum Input Pulse Width
Output Rise Time (Note 8)
V = 3.3V
5
ns
WIDTH
r
+
V = 5.5V
1.1
1.7
2.7
ns
ns
ns
+
V = 3.3V
+
V = 2.25V
+
t
Output Fall Time (Note 8)
V = 5.5V
1.0
1.6
2.4
ns
ns
ns
f
+
V = 3.3V
+
V = 2.25V
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6995C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 9: Settling time is the amount of time required for the output to settle
within 1% of the final frequency after a 0.5× or 2× change in I
.
Note 3: The LTC6995C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6995C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6995I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6995H is guaranteed
to meet specified performance from –40°C to 125°C. The LTC6995MP is
guaranteed to meet specified performance from –55°C to 125°C.
SET
Note 10: Jitter is the ratio of the deviation of the period to the mean of the
period. This specification is based on characterization and is not 100%
tested.
Note 11: Long-term drift of silicon oscillators is primarily due to the
movement of ions and impurities within the silicon and is tested at 30°C
under otherwise nominal operating conditions. Long-term drift is specified
as ppm/√kHr due to the typically nonlinear nature of the drift. To calculate
drift for a set time period, translate that time into thousands of hours, take
the square root and multiply by the typical drift number. For instance, a
year is 8.77kHr and would yield a drift of 266ppm at 90ppm/√kHr. Drift
without power applied to the device may be approximated as 1/10th of the
drift with power, or 9ppm/√kHr for a 90ppm/√kHr device.
Note 4: Frequency accuracy is defined as the deviation from the f
OUT
equation, assuming R is used to program the frequency.
SET
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
Note 6: The RST pin has hysteresis to accommodate slow rising or falling
+
signals. The threshold voltages are proportional to V . Typical values can
+
be estimated at any supply voltage using V
≈ 0.55 • V + 185mV
RST(RISING)
+
and V
≈ 0.48 • V – 155mV.
RST(FALLING)
699512f
4
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Frequency Error vs Temperature
Frequency Error vs Temperature
Frequency Error vs Temperature
3
3
2
1
0
3
2
1
0
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MAX OVER TEMPERATURE
2
R
= 800k
R
= 50k
R
= 200k
SET
SET
SET
3 PARTS
3 PARTS
3 PARTS
1
0
–1
–2
–3
–1
–2
–3
–1
–2
–3
GUARANTEED MIN OVER TEMPERATURE
GUARANTEED MIN OVER TEMPERATURE
GUARANTEED MIN OVER TEMPERATURE
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
699512 G03
699512 G01
699512 G02
Frequency Error vs RSET
Frequency Drift vs Supply Voltage
Typical VSET Distribution
0.5
0.4
3
2
250
200
150
100
50
2 LOTS
DFN AND SOT-23
1274 UNITS
GUARANTEED MAX OVER TEMPERATURE
3 PARTS
0.3
0.2
1
0
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–1
–2
–3
+
REFERENCED TO V = 4.5V
R
SET
R
SET
R
SET
= 50k
= 200k
= 800k
GUARANTEED MIN OVER TEMPERATURE
0
0
200
400
(kΩ)
600
800
2
3
4
5
6
0.98
0.996
V
1.004
(V)
1.012
1.02
0.988
SUPPLY VOLTAGE (V)
R
SET
SET
699512 G06
699512 G04
699512 G05
VSET Drift vs ISET
VSET Drift vs Supply
VSET vs Temperature
1.0
0.8
1.0
0.8
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
3 PARTS
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
+
REFERENCED TO I
= 10µA
REFERENCED TO V = 4V
SET
0
10
(µA)
15
20
5
2
4
5
6
–50
0
25
50
75 100 125
3
–25
I
SUPPLY (V)
TEMPERATURE (°C)
SET
699512 G07
699512 G08
699512 G09
699512f
5
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Supply Current
vs RST Pin Voltage
Supply Current vs Supply Voltage
Supply Current vs Temperature
150
125
100
75
250
200
150
100
50
150
125
R
= 800k
SET
R
= 50k
SET
5V
5V
RST FALLING
RST RISING
5V, R
= 100k
= 100k
SET
100
75
R
SET
= 100k
2.5V, R
SET
R
R
= 200k
= 800k
SET
3.3V
3.3V
RST RISING
5V, R
= 800k
= 800k
SET
RST FALLING
SET
2.5V, R
50
25
0
50
25
0
SET
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
0
0.2
0.4
0.6
0.8
1.0
2
3
4
5
6
+
SUPPLY VOLTAGE (V)
V
/V (V/V)
RST
699512 G11
699512 G12
699512 G10
RST Threshold Voltage
vs Supply Voltage
Supply Current vs RSET
Typical ISET Current Limit vs V+
150
125
1000
800
600
400
200
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
SET PIN SHORTED TO GND
+
POSITIVE-GOING
V
= 5V
100
75
+
V
= 3.3V
= 2.5V
NEGATIVE-GOING
+
V
50
25
0
0
200
400
(kΩ)
600
800
2
3
4
5
6
2
3
4
5
6
R
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SET
699512 G14
699512 G15
699512 G13
Reset Propagation Delay (tRST
)
Rise and Fall Time
vs Supply Voltage
Typical Frequency Error
vs Time (Long-Term Drift)
vs Supply Voltage
50
45
40
35
30
25
20
15
10
5
3.0
2.5
2.0
1.5
1.0
0.5
0
200
150
100
50
C
= 5pF
65 UNITS
C
LOAD
= 5pF
LOAD
SOT-23 AND DFN PARTS
T
= 30°C
A
t
RISE
0
–50
t
FALL
–100
–150
–200
0
2
3
4
5
6
2
3
4
5
6
0
400 800 1200 1600 2000 2400 2800
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TIME (h)
699512 G17
699512 G18
699512 G16
699512f
6
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
Typical perForMance characTerisTics
V+ = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Output Resistance
vs Supply Current
50
Typical LTC6995-1 Start-Up with
POL = 1
45
+
V
40
35
30
25
20
15
10
5
5V/DIV
RST
5V/DIV
OUTPUT SOURCING CURRENT
RESET RELEASED,
OUT
5V/DIV
100Hz OUTPUT CLOCK
OUTPUT RESET
4ms START-UP
+
699512 G20
V
= 5V
5ms/DIV
OUTPUT SINKING CURRENT
DIVCODE = 15
= 499k
R
SET
0
2
3
4
5
6
SUPPLY VOLTAGE (V)
699512 G19
pin FuncTions (DCB/S6)
V (Pin1/Pin5):SupplyVoltage(2.25Vto5.5V).Thissup-
ply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1µF capacitor.
+
50ppm/°C or better temperature coefficient. For lower ac-
curacy applications an inexpensive 1% thick film resistor
may be used.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
+
Input. An internal A/D converter (referenced to V ) moni-
tors the DIV pin voltage (V ) to determine a 4-bit result
DIV
(DIVCODE). V may be generated by a resistor divider
regulating the V voltage.
DIV
SET
+
between V and GND. Use 1% resistors to ensure an ac-
curateresult. TheDIVpinandresistorsshouldbeshielded
from the OUT pin or any other traces that have fast edges.
Limit the capacitance on the DIV pin to less than 100pF
RST
LTC6995-1/
LTC6995-2
OUT
+
V
+
GND
V
C1
0.1µF
so that V settles quickly. The MSB of DIVCODE (POL)
DIV
R1
R2
determines the polarity of the OUT pin.
SET
DIV
699512 PF
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
R
SET
on the SET pin (V ) is regulated to 1V above GND. The
SET
amount of current sourced from the SET pin (I ) pro-
SET
RST or RST (Pin 4/Pin 1): Output Reset. The reset input
is used to stop the output oscillator and to clear internal
dividers. When reset is released the oscillator starts with
a full half period time interval. The output logic state when
reset is determined by the programmed DIVCODE. The
LTC6995-1 has an active high RST input. The LTC6995-2
has an active low RST input.
grams the master oscillator frequency. The I
current
SET
range is 1.25µA to 20µA. The output oscillation will stop
if I drops below approximately 500nA. A resistor con-
SET
nected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
699512f
7
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LTC6995-1/LTC6995-2
pin FuncTions (DCB/S6)
GND(Pin5/Pin2):Ground.Tie toalowinductanceground
plane for best performance.
30Ω. When driving an LED or other low impedance load
a series output resistor should be used to limit source/
sink current to 20mA.
OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
+
fromGNDtoV withanoutputresistanceofapproximately
(S6 package pin numbers shown)
block DiagraM
5
+
V
R1
POL BIT
DIV
4-BIT A/D
CONVERTER
DIGITAL
FILTER
4
R2
MASTER OSCILLATOR
1µs
50kΩ
V
SET
FIXED
DIVIDER
÷ 1024
MCLK
=
t
=
PROGRAMMABLE
DIVIDER
OUT
MASTER
OUTPUT
POLARITY
I
SET
6
t
÷1, 8, 64, 512
OUT
15 18 21
4096, 2 , 2 , 2
HALT OSCILLATOR
OUTPUT
DIVIDER
RESET
IF I
< 500nA
SET
I
SET
POR
+
LTC6995-2
ONLY
–
+
–
1V
GND
V
= 1V
SET
RST
SET
1
3
2
699512 BD
I
SET
R
SET
699512f
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operaTion
The LTC6995 is built around a master oscillator with a
DIVCODE
1MHz maximum frequency. The oscillator is controlled
+
TheDIVpinconnectstoaninternal,V referenced4-bitA/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6995:
by the SET pin current (I ) and voltage (V ), with a
SET
SET
1MHz • 50k conversion factor that is accurate to 0.8%
under typical conditions.
1. DIVCODE determines the output frequency divider set-
1
ISET
VSET
ting, N
.
fMASTER
=
= 1MHz • 50kΩ •
DIV
tMASTER
2. DIVCODE determines the polarity of the RST and OUT
pins, via the POL bit.
A feedback loop maintains V at 1V 30mV, leaving I
SET
SET
+
as the primary means of controlling the output frequency.
The simplest way to generate I is to connect a resistor
V
may be generated by a resistor divider between V
DIV
SET
and GND as shown in Figure 1.
(R ) between SET and GND, such that I = V /R .
SET
SET
SET SET
2.25V TO 5.5V
The master oscillator equation reduces to:
+
V
1
1MHz • 50kΩ
fMASTER
=
=
LTC6995
R1
R2
tMASTER
RSET
DIV
From this equation, it is clear that V drift will not affect
SET
GND
theoutputfrequencywhenusingasingleprogramresistor
699512 F01
(R ). Error sources are limited to R
tolerance and
of the LTC6995.
SET
SET
the inherent frequency accuracy ∆f
Figure 1. Simple Technique for Setting DIVCODE
OUT
R
may range from 50k to 800k (equivalent to I
SET
SET
Table 1 offers recommended 1% resistor values that ac-
curatelyproducethecorrectvoltagedivisionaswellasthe
between 1.25µA and 20µA).
Before reaching the OUT pin, the oscillator frequency
passes through a fixed ÷1024 divider. The LTC6995 also
includes a programmable frequency divider which can
correspondingN andPOLvaluesfortherecommended
DIV
resistor pairs. Other values may be used as long as:
+
1. The V /V ratio is accurate to 1.5% (including resis-
15
DIV
further divide the frequency by 1, 8, 64, 512, 4096, 2 ,
tor tolerances and temperature effects)
18
21
2 or 2 . The divider ratio N is set by a resistor divider
DIV
attached to the DIV pin.
2. Thedrivingimpedance(R1||R2)doesnotexceed500kΩ.
1MHz • 50kΩ ISET
1024 •NDIV VSET
If the voltage is generated by other means (i.e., the output
fOUT
=
=
•
, or
+
of a DAC) it must track the V supply voltage. The last
column in Table 1 shows the ideal ratio of V
to the
DIV
1
NDIV VSET
supply voltage, which can also be calculated as:
tOUT
=
•
•1.024ms
fOUT 50kΩ ISET
VDIV DIVCODE+0.5
=
1.5%
V+
16
with R in place of V /I the equation reduces to:
SET
SET SET
Forexample,ifthesupplyis3.3VandthedesiredDIVCODE
NDIV •RSET
50kΩ
tOUT
=
•1.024ms
is 4, V = 0.281 • 3.3V = 928mV 50mV.
DIV
Figure 2 illustrates the information in Table 1, showing
that N is symmetric around the DIVCODE midpoint.
DIV
699512f
9
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Table 1. DIVCODE Programming
+
DIVCODE
POL
0
N
RECOMMENDED t
R1 (kΩ)
Open
976
R2 (kΩ)
Short
102
V
/V
DIV
DIV
OUT
0
1
1
1.024ms to 16.384ms
8.192ms to 131ms
65.5ms to 1.05sec
524ms to 8.39sec
4.19sec to 67.1sec
33.6sec to 537sec
268sec to 4,295sec
2,147sec to 34,360sec
2,147sec to 34,360sec
268sec to 4,295sec
33.6sec to 537sec
4.19sec to 67.1sec
524ms to 8.39sec
65.5ms to 1.05sec
8.192ms to 131ms
1.024ms to 16.384ms
≤0.03125 0.015
0.09375 0.015
0.15625 0.015
0.21875 0.015
0.28125 0.015
0.34375 0.015
0.40625 0.015
0.46875 0.015
0.53125 0.015
0.59375 0.015
0.65625 0.015
0.71875 0.015
0.78125 0.015
0.84375 0.015
0.90625 0.015
≥0.96875 0.015
0
8
2
0
64
512
976
182
3
0
1000
1000
1000
1000
1000
887
280
4
0
4,096
32,768
262,144
2,097,152
2,097,152
262,144
32,768
4,096
512
392
5
0
523
6
0
681
7
0
887
8
1
1000
1000
1000
1000
1000
976
9
1
681
10
11
12
13
14
15
1
523
1
392
1
280
1
64
182
1
8
102
976
1
1
Short
Open
POL BIT = 0
POL BIT = 1
10000
1000
100
10
7
8
6
9
5
10
11
4
12
3
1
2
13
0.1
1
14
0.01
0.001
0
15
+
+
0V
0.5•V
V
INCREASING V
DIV
699512 F02
Figure 2. Frequency Range and POL Bit vs DIVCODE
699512f
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Reset and Polarity Bit Functions
With the POL bit programmed to be 0, the output will be
forced low when reset. When reset is released by chang-
ing state, the oscillator starts. The next rising edge at the
output follows a precise half cycle delay.
The Reset input, RST for the LTC6995-1 and RST for the
LTC6995-2, forces the output to a fixed state and resets
the internal clock dividers. The output state when reset is
determined by the polarity bit as selected by through the
DIVCODE setting.
With the POL bit programmed to be 1, the output will be
forced high when reset. When reset is released by chang-
ing state, the oscillator starts. The next falling edge at the
output follows a precise half cycle delay.
OUTPUT (OSCILLATOR START STATE)
RST/RST POLARITY
LTC6995-1
Oscillating (Low)
0 (Reset)
LTC6995-2
0 (Reset)
0
1
0
1
0
0
1
1
Oscillating (Low)
1 (Reset)
Oscillating (High)
1 (Reset)
Oscillating (High)
t
t
WIDTH
WIDTH
RST
RST
t
t
RST
RST
OUT REMAINS LOW
WHILE RST IS HIGH
OUT REMAINS LOW
WHILE RST IS LOW
OUT
OUT
699512 F03
t
t
OUT
OUT
1/2 t
1/2 t
OUT
OUT
LTC6995-1
LTC6995-2
Figure 3. Reset Timing Diagram (POL Bit = 0)
t
t
WIDTH
WIDTH
RST
RST
OUT
t
t
RST
RST
OUT REMAINS HIGH
WHILE RST IS LOW
OUT REMAINS HIGH
WHILE RST IS HIGH
OUT
699512 F04
t
t
OUT
OUT
1/2 t
1/2 t
OUT
OUT
LTC6995-1
LTC6995-2
Figure 4. Reset Timing Diagram (POL Bit = 1)
699512f
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Changing DIVCODE After Start-Up
voltagesarenotstable. Forthisreason, itisrecommended
to minimize the capacitance on the DIV pin so it will prop-
Following start-up, the A/D converter will continue moni-
+
erly track V . Less than 100pF will not affect performance.
toring V
for changes. The LTC6995 will respond to
DIV
DIVCODE changes in less than one cycle.
Start-Up Behavior
t
< 500 • t < t
DIVCODE
MASTER
OUT
Whenfirstpoweredup,theoutputisheldlow.Ifthepolarity
issetfornon-inversion(POL=0)andtheoutputisenabled
at the end of the start-up time, OUT will begin oscillating.
If the output is being reset (RST = 1 for LTC6995-1 and
RST = 0 for LTC6995-2) at the end of the start-up time,
it will remain low due to the POL bit = 0. When reset is
released the oscillator starts and the output remains low
for precisely one half cycle of the programmed period.
The output may have an inaccurate pulse width during the
frequency transition. But the transition will be glitch-free
and no high or low pulse can be shorter than the mas-
ter clock period. A digital filter is used to guarantee the
DIVCODEhassettledtoanewvaluebeforemakingchanges
to the output.
Start-Up Time
In inverted operation (POL = 1), the start-up sequence is
similar. However, the LTC6995 does not know the correct
DIVCODE setting when first powered up, so the output
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, t
. A supply
START
voltage of typically 1.4V (1.2V to 1.5V over temperature)
initiates the start-up sequence. The OUT pin is held low
defaults low. At the end of t
, the value of DIVCODE is
START
recognizedandOUTgoeshigh(inactive)becausePOL = 1.
If the output is being reset (RST = 1 for LTC6995-1 and
RST = 0 for LTC6995-2) at the end of the start-up time,
it will remain high due to the POL bit = 1. When reset is
released the oscillator starts and the output remains high
for precisely one half cycle of the programmed period.
during this time. The typical value for t
ranges from
START
0.5msto8msdependingonthemasteroscillatorfrequency
(independent of N ):
DIV
t
= 500 • t
MASTER
START(TYP)
During start-up, the DIV pin A/D converter must deter-
mine the correct DIVCODE before the output is enabled.
The start-up time may increase if the supply or DIV pin
Figures7to10detailthepossiblestart-upsequences.
DIV
200mV/DIV
+
V
1V/DIV
500µs
OUT
1V/DIV
OUT
1V/DIV
+
+
699512
699512 F06
V
R
= 3.3V
= 200k
10ms/DIV
V
= 2.5V
250µs/DIV
F05
DIVCODE = 15
= 50k
SET
R
SET
Figure 5. DIVCODE Change from 1 to 0
Figure 6. Typical Start-Up LTC6995-1 with RST = 0V
699512f
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RST
RST
OUT
OUT
t
t
t
t
START
OUT
START
OUT
1/2 t
1/2 t
OUT
OUT
LTC6995-1
LTC6995-2
699512 F07
699512 F08
699512 F09
699512 F10
Figure 7. Start-Up Timing Diagram (Reset = 0, POL Bit = 0)
RST
OUT
RST
OUT
t
t
t
t
OUT
START
OUT
START
1/2 t
1/2 t
OUT
OUT
LTC6995-1
LTC6995-2
Figure 8. Start-Up Timing Diagram (Reset = 1, POL Bit = 0)
RST
OUT
RST
OUT
t
t
t
t
START
OUT
START
OUT
1/2 t
1/2 t
OUT
OUT
LTC6995-1
LTC6995-2
Figure 9. Start-Up Timing Diagram (Reset = 0, POL Bit = 1)
RST
OUT
RST
OUT
t
t
t
t
OUT
START
OUT
START
1/2 t
1/2 t
OUT
OUT
LTC6995-1
LTC6995-2
Figure 10. Start-Up Timing Diagram (Reset = 1, POL Bit = 1)
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Basic Operation
Example: Design a 1Hz oscillator with minimum power
consumption, an active-high reset input, and the OUT pin
low during reset.
The simplest and most accurate method to program the
LTC6995 is to use a single resistor, R , between the
SET
SET and GND pins. The design procedure is a 3-step
Step 1: Select the LTC6995 Version and POL Bit Setting
process. First select the POL bit setting and N value,
DIV
For active-high reset select the LTC6995-1. For OUT low
during reset choose POL bit = 0.
then calculate the value for the R resistor.
SET
Step 1: Select the LTC6995 Version and POL Bit Setting
Step 2: Select the N Frequency Divider Value
DIV
Determine if the application requires an active-high,
LTC6995-1 or active-low, LTC6995-2 reset function.
Otherwise the two versions share identical functionality.
Choose an N
value that meets the requirements of
DIV
Equation (1), using t
= 1000ms:
OUT
61.04 ≤ N ≤ 976.6
The OUT pin polarity depends on the setting of the POL
bit. To force OUT = 0 during reset, choose POL bit = 0. To
force OUT = 1 during reset, choose POL bit = 1.
DIV
Potential settings for N include 64 and 512. N = 64
DIV
DIV
is the best choice, as it minimizes supply current by us-
ing a large R resistor. POL = 0 and N = 64 requires
SET
DIV
Step 2: Select the N Frequency Divider Value
DIV
DIVCODE = 2. Using Table 1, choose R1 = 976k and
R2 = 182k values to program DIVCODE = 2.
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the N
DIV
should be
Step 3: Select R
value. For a given output clock period, N
selected to be within the following range.
SET
DIV
Calculate the correct value for R using Equation (2).
SET
tOUT
16.384ms
tOUT
1.024ms
50k
1.024ms
1000ms
64
≤NDIV
≤
(1)
RSET
=
•
= 763k
To minimizesupplycurrent,choosethelowestN value
DIV
Since 763k is not available as a standard 1% resistor,
substitute 768k if a –0.7% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 576k + 187k to attain a more precise resistance.
(generally recommended). Alternatively, use Table 1
as a guide to select the best N
application.
value for the given
DIV
With POL already chosen, this completes the selection of
The completed design is shown in Figure 11.
DIVCODE. Use Table 1 to select the proper resistor divider
+
or V /V ratio to apply to the DIV pin.
DIV
RST
RST
GND
SET
OUT
Step 3: Calculate and Select R
SET
LTC6995-1
2.25V TO 5.5V
The final step is to calculate the correct value for R
using the following equation.
+
SET
V
R1
976k
DIVCODE = 2
R2
182k
DIV
50k
tOUT
RSET
=
•
R
763k
SET
(2)
1.024ms NDIV
699512 F11
Select the standard resistor value closest to the calculated
value.
Figure 11. 1Hz Oscillator
699512f
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Power-On Reset (POR) Function
RST
GND
SET
OUT
POR
When power is applied to the LTC6995 the output is held
LTC6995-1
low for t
, then takes on the value of the POL bit as the
START
+
V
2.25V TO 5.5V
0.1µF
clock cycle begins. If POL = 0 (DIVCODE < 8) the output
R1
R
SET
1M
will remain low for a programmable interval of t
+
191k
START
DIV
1/2 t , assuming the RST pin is inactive. This makes the
OUT
R2
+
280k
LTC6995 useful as a programmable long-time power-on
reset (POR), with the low output used to hold a system
in reset for a fixed period after power is applied. Timing
RST = V FOR LTC6995-2
t
= 1 SECOND FOR VALUES SHOWN
POR
POL = 0
DIVCODE = 3
NDIV = 512
+
begins when the V supply exceeds approximately 1.4V.
To preventadditionaloutputtransitionsaftertheinitialPOR
time, the oscillator can be disabled by removing the SET
pin current. This prevents the internal master oscillator
output from clocking the frequency dividers or output,
while keeping it biased so it can resume operation quickly.
The easiest way to implement this feature is to connect
+
V
t
START
~1.4V STARTS TIMER
t
DELAY
OUT
OUT
POL = 0
(1/2 t
)
TIMER STOPPED
POWER-ON RESET
699512 F12
R
between the SET and OUT pins.
SET
Figure 12. Active Low Power-On Reset
(1 Second Interval Example)
Figure 12 shows the basic power-on reset function. When
the half cycle times out, the output goes high, eliminates
the SET pin current, and stops additional OUT pin transi-
tions. The output remains high until the device is reset by
driving the RST input or power is cycled off then back on.
The POR interval is only one half of an oscillator period so
component selection is slightly different. Table 2 provides
the component values required for one half cycle time
intervals. Timing starts after a short startup delay time
+
following the application of the V supply.
Table 2. Power-On Reset (POR). One Shot, One Half Cycle Delay Programming
Output Low During Time Interval, POL = 0
DIVCODE
t
TIME INTERVAL (1/2 t
512µs to 8.2ms
)
R1 (kΩ)
Open
976
R2 (kΩ)
Short
102
~R (kΩ)
SET
DELAY
OUT
0
1
2
3
4
5
6
7
t
t
• 97.6
DELAY(MS)
DELAY(MS)
4.1ms to 65.5ms
32.8ms to 524.3ms
262.1ms to 4.2sec
2.1sec to 33.6sec
16.8sec to 4.5min
2.2min to 35.8min
17.9min to 4.8hrs
• 12.2
• 1.5
976
182
t
DELAY(MS)
1000
1000
1000
1000
1000
280
t
• 190.7
• 23.8
DELAY(SEC)
392
t
DELAY(SEC)
523
t
• 178.6
• 22.7
DELAY(MIN)
681
t
DELAY(MIN)
887
t
• 167.6
DELAY(HR)
Note: Power-On Reset Time = t
+ t
START
DELAY
699512f
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For shorter power on reset times (1ms to 73ms) the timer
Long Timer One Shots and Delay Generators
startup delay becomes a significant part of the total POR
The POR circuit of Figure 12 is also useful when the reset
inputsaredriven.Thiscreatesedgetriggeredtimingevents
that are active low and can either be re-triggered or can
stop after one programmed interval. The programmed
time interval can range from only 500µs to over 4 hours
with just resistor value changes.
time. To take this delay into account the value for R can
SET
be modified from the values shown in Table 2. For a POR
time in the range from 1ms to 16ms (DIVCODE = 0), R
SET
should be t (ms) • 49.5. For a POR time in the range
POR
from 4.5ms to 73ms (DIVCODE = 1), R
is t (ms) •
SET
POR
10.9. For longer POR times (DIVCODE 2 through 7) the
startup time is insignificant. After power on, the delay fol-
lowingaresetconditionwillbeinthesamerangeasshown
The circuits in Figure 13 show how a POR or active low
intervalcanbere-startedtoprovideafullsystemresettime.
for t
in Table 2 for these two DIVCODE selections.
DELAY
The Figure 14 circuit requires an indication from the
system being reset that it is ready before timing out. The
LTC6995-2 can accommodate an active high OK signal.
For short POR times, a more precise estimation of the
startup time can be found from the following:
By forcing a reset condition at power on the LTC6995 can
be used to create a long time delayed rising edge triggered
byeitherafallingedgesignal(LTC6995-1)orarisingedge
signal (LTC6995-2) as show in Figure 15.
RSET(kΩ)
tSTART(µs) = 256 +16 •(12 –DIVCODE)
(
)
50
+80
Supply bounce resets the internal timer so the POR circuit
automatically debounces supply noise. POR timing starts
fromthetimethattheV supplyhasreachedapproximately
+
1.4 volts.
+
+
V
V
100k
RST
GND
SET
OUT
POR
RST
GND
SET
OUT
POR
LTC6995-1
LTC6995-2
100k
+
+
+
+
V
V
0.1µF
V
V
0.1µF
R1
R2
R1
R2
R
R
SET
SET
DIV
DIV
ACTIVE HIGH RESET
ACTIVE LOW RESET
+
V
+
V
RESET
RESET
RST
RST
OUT
POL = 0
OUT
POL = 0
TIMER
STOPPED
TIMER
STOPPED
t
+
OUT
t
+
OUT
START
START
1/2 t
1/2 t
1/2 t
1/2 t
OUT
OUT
POR
POR
POR
POR
TIMER
STOPPED
TIMER
STOPPED
699512 F13
Figure 13. System Resets On Command with Full POR Time Interval. Reset Pulse Is Debounced Automatically
699512f
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SYSTEM OK
+
V
POR
RST
GND
SET
OUT
SYSTEM
LTC6995-1
RST
SYSTEM OK
+
+
V
V
0.1µF
R1
R2
R
SET
t
+
OUT
TIMER
STOPPED
OUT
POL = 0
START
DIV
1/2 t
1/2 t
OUT
POR
POR EXTENDED
POR
699512 F14
Figure 14. Extended POR. Timer Reset During Initial POR Interval. Full POR Interval Provided Once System Signals the OK
TRIGGER
RST
GND
SET
OUT
OUTPUT
TRIGGER
RST
GND
SET
OUT
OUTPUT
LTC6995-1
LTC6995-2
+
+
+
+
V
V
0.1µF
V
V
0.1µF
R1
R2
R1
R2
R
R
SET
SET
DIV
DIV
FALLING EDGE TRIGGERED
POL = 0
RISING EDGE TRIGGERED
POL = 0
+
+
V
V
TRIGGER
OUTPUT
TRIGGER
OUTPUT
1/2 t
1/2 t
1/2 t
1/2 t
OUT
OUT
OUT
OUT
699512 F15
Figure 15. Long Time Delayed Rising Edge. Delay Time Can Range from 500µs to 4.8 Hours
699512f
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Watchdog Timers
returns to issuing watchdog pulses. Figure 16 shows the
timing for this application.
Using the same circuits as shown in Figure 15 with pe-
riodic pulsing of the reset input can create an effective
watchdog timer. A watchdog pulse is required from a
system within each timing interval. The watchdog timeout
interval can be programmed from 500µs to 4.8 hours. If a
pulse is missed the output goes high to indicate that the
system software may be caught in an infinite loop. This
high level can be used to initiate software diagnostic or
restart procedures. The LTC6995 internal clock stops and
the output remains high until the software recovers and
Watchdog timers are used to detect if a system operating
software is diverted from the designed program sequence
for any reason. It is always a possibility that the software
could get stuck in a way that keeps the watchdog pulse in
the state that holds the timer in the reset so it can never
timeout.Inthisconditionthewatchdogtimerisineffective
and will never force corrective action. To help to prevent
this a second one shot can be used to reset the watchdog
timer as shown in Figure 17.
+
V
MISSED PULSE
RST (LTC6995-1)
WATCHDOG PULSES
RST (LTC6995-2)
OUTPUT
SERVICE WATCHDOG
TIMER RESTARTS
TIMEOUT
RESUME
699512 F16
Figure 16. Watchdog Timer. Same Circuits as Shown in Figure 15
100µs ONE SHOT
50ms WATCHDOG TIMER
SYSTEM POSITIVE
WATCHDOG PULSE
TRG
GND
SET
OUT
RST
GND
SET
OUT
OUTPUT
LTC6993-1
LTC6995-1
+
+
+
+
V
V
V
V
R1
0.1µF
R
SET
976k
604k
DIV
DIV
R
SET
R2
619k
102k
RISING EDGE TRIGGERED
POSITIVE OUTPUT PULSE
DIVCODE = 1
FALLING EDGE TRIGGERED
POL = 0
DIVCODE = 1
699512 F17
Figure 17. Extra-Reliable Watchdog Timer. Allows Timeout if System Watchdog Pulse Gets Stuck in the Timer Reset State.
Both Timer Devices Can Share the Same DIVCODE Setting
699512f
18
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
applicaTions inForMaTion
Gated Oscillators
A simple application of this technique allows the LTC6995
output to reset itself, producing a well-controlled pulse
once each cycle. Figures 19a and 19b show circuits that
produceapproximately1µspulsesonceaminute.Theonly
difference is the version of LTC6995 used and the POL
bit setting, which controls whether the pulse is positive
or negative.
The reset input (RST) clears all internal dividers so that,
when released, the output will start clocking with a full
programmed period. This edge can be used to gate the
output ON and OFF at a known starting point for the clock.
Circuits which count clock cycles for further timing pur-
poses will always have an accurate count of full cycles
until reset. The output clock is always at 50% duty cycle
and the period of each cycle can range from 1ms to 9.5
hours. Depending on the polarity bit selection the output
clock can start high or low as shown in Figure 18.
Voltage Controlled Frequency
Withoneadditionalresistor,theLTC6995outputfrequency
can be manipulated by an external voltage. As shown in
Figure 20, voltage V
sources/sinks a current through
CTRL
R
to vary the I current, which in turn modulates the
Self-Resetting Circuits
VCO
SET
output frequency as described in Equation (3).
TheRSTpinhashysteresistoaccommodateslow-changing
inputvoltages.Furthermore,thetrippointsareproportional
to the supply voltage (see Note 6 and the RST Threshold
Voltage vs Supply Voltage curve in Typical Performance
Characteristics). This allows an RC time constant at the
RST input to generate a delay that is nearly independent
of the supply voltage.
RVCO VCTRL
–
1MHz •50kΩ
1024•NDIV •RVCO
(3)
fOUT
=
• 1+
RSET VSET
LTC6995-1
LTC6995-2
ACTIVE HIGH RESET
ACTIVE LOW RESET
RST FALLING EDGE STARTS THE CLOCK
RST RISING EDGE STARTS THE CLOCK
RST
OUT
RST
OUT
POL = 0
POL = 0
1/2 t
1/2 t
1/2 t
OUT
OUT
OUT
1/2 t
OUT
OUT
POL = 1
OUT
POL = 1
699512 F18
Figure 18. Gated Oscillators. First One-Half Cycle Time Always Accurate
699512f
19
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
applicaTions inForMaTion
OUT
R
PW
RST
GND
SET
OUT
2.26k
+
LTC6995-1
V
RST
GND
SET
OUT
+
C
PW
V
LTC6995-1
2.25V TO 5.5V
470pF
C1
0.1µF
R1
R2
+
V
R
VCO
0.1µF
R1
1M
V
DIV
R
178k
CTRL
SET
R
SET
DIV
R2
523k
699512 F20
Figure 20. Voltage-Controlled Oscillator
V
RST(RISING)
t
= –R • C • In 1–
PULSE
PW
PW
+
(
)
V
Digital Frequency Control
t
t
≈ –2.26kΩ • 470pF • In(1 – 0.61)
PULSE
PULSE
≈ 1µs
The control voltage can be generated by a DAC (digital-
to-analog converter), resulting in a digitally-controlled
frequency. Many DACs allow for the use of an external
1µs PULSE WIDTH
60 SECONDS
reference. If such a DAC is used to provide the V
CTRL
699512 F19a
voltage, the V dependency can be eliminated by buffer-
SET
ing V
and using it as the DAC’s reference voltage, as
Figure 19a. Self-Resetting Circuit (DIVCODE = 4)
SET
shown in Figure 21. The DAC’s output voltage now tracks
any V variation and eliminates it as an error source.
The SET pin cannot be tied directly to the reference input
of the DAC because the current drawn by the DAC’s REF
input would affect the frequency.
SET
OUT
R
PW
2.26k
RST
GND
SET
OUT
C
PW
LTC6995-2
2.25V TO 5.5V
470pF
+
V
I
Extremes (Master Oscillator Frequency Extremes)
SET
0.1µF
R1
R
SET
523k
178k
When operating with I
outside of the recommended
SET
DIV
1.25µA to 20µA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
R2
1M
V
RST(FALLING)
t
= –R • C • In
PW PW
PULSE
+
(
)
V
The oscillator can still function with reduced accuracy for
t
t
≈ –2.26kΩ • 470pF • In(0.43)
≈ 0.9µs
PULSE
PULSE
I
<1.25µA.Atapproximately500nA,theoscillatoroutput
SET
will be frozen in its current state. The output could halt in
a high or low state. This avoids introducing short pulses
when frequency modulating a very low frequency output.
0.9µs PULSE WIDTH
60 SECONDS
699512 F19b
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Figure 19b. Self-Resetting Circuit (DIVCODE = 11)
699512f
20
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
applicaTions inForMaTion
RST
GND
SET
OUT
+
LTC6995
V
+
+
V
V
C1
0.1µF
0.1µF
R1
R2
DIV
+
–
1/2
LTC6078
+
V
0.1µF
1MHz • 50kΩ
R
D
IN
4096
VCO
SET
f
=
• 1 +
–
OUT
(
)
1024 • N • R
R
DIV
VCO
V
REF
CC
D
= 0 TO 4095
IN
D
IN
R
VCO
V
OUT
µP
LTC1659
CLK
CS/LD
R
SET
GND
699512 F21
Figure 21. Digitally-Controlled Oscillator
and by following a few rules, the expected performance is
easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Frequency Modulation and Settling Time
The LTC6995 will respond to changes in I up to a –3dB
SET
bandwidth of 0.4 • f
.
OUT
Figure22showsexamplePCBlayoutsforboththeTSOT-23
and DFN packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6995. These layouts are
a guide and need not be followed exactly.
Following a 2× or 0.5× step change in I , the output
SET
frequency takes less than one cycle to settle to within 1%
of the final value.
Power Supply Current
+
1. Connect the bypass capacitor, C1, directly to the V and
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under
any condition using the following equation. This equation
GND pins using a low inductance path. The connection
+
from C1 to the V pin is easily done directly on the top
layer. For the DFN package, C1’s connection to GND is
alsosimplydoneonthetoplayer.FortheTSOT-23,OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that,C1’sGNDconnectioncanbeaccomplishedthrough
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
ignores C
(valid for C
< 1nF) and assumes the
LOAD
LOAD
output has 50% duty cycle.
V+
V+
IS(TYP) ≈ V+ • fMASTER • 7.8pF+
+ 1.8 •ISET +50µA
+
420kΩ 2 •RLOAD
Supply Bypassing and PCB Layout Guidelines
The LTC6995 is a 2.2% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
699512f
21
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
applicaTions inForMaTion
RST
GND
SET
OUT
LTC6995
+
+
V
V
C1
0.1µF
R1
R2
DIV
R
SET
+
+
V
+
C1
V
R1
C1
V
OUT
GND
RST
RST
OUT
+
DIV
SET
GND
SET
V
R2
DIV
R1
R
SET
R
R2
SET
699512 F22
DFN PACKAGE
TSOT-23 PACKAGE
Figure 22. Supply Bypassing and PCB Layout
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
4. Connect R directly to the GND pin. Using a long path
SET
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
3. Place R
as close as possible to the SET pin and
SET
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
699512f
22
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
Typical applicaTions
Timed Power Switches, Auto Shutoff After One Hour
P-CHANNEL
MOSFET
*
TO LOAD
CURRENT DEPENDS
ON PMOS SELECTION
3V TO 36V
0.1µF
5V
C
OUT
LTC4412HV
SENSE
V
IN
PUSH TO ACTIVATE
GND GATE
CTL STAT
*DRAIN-SOURCE DIODE OF MOSFET
LOW = ON
HIGH = OFF
RST
GND
SET
OUT
LTC6995-1
100k
+
V
5V
0.1µF
R1
R
SET
TO LOAD
1M
169k
2.6V TO 5.5V
1µF
IN
OUT
LTC4411
UP TO 2.6A
DIV
C
OUT
R2
887k
4.7µF
GND
CTL
ACTIVE HIGH RESET
1/2 t = 1 HOUR
OUT
STAT
699512 TA08
5 Second On/Off Timed Relay Driver
12V
0.1µF
L
C
D1
NO
1N4148
RESET
RST
1
R4
15k
RUN
RELAY ENABLE
COTO 1022 RELAY
9001-12-01
Q1
OUT
2N2219A
LTC6995-1
5V
+
GND
V
C2
0.1µF
R1
1M
SET
DIV
R2
392k
R3
118k
699512 TA02
699512f
23
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
Typical applicaTions
1.5ms Radio Control Servo Reference Pulse Generator
5V
20ms
FRAME RATE
GENERATOR
1.5ms
REFERENCE
PULSE
R7
10k
20ms PERIOD
RESET = OPEN
RUN = GND
RST
OUT
TRIG
OUT
1.5ms PULSE
LTC6995-1
LTC6993-1
5V
5V
+
+
GND
SET
V
GND
SET
V
C1
0.01µF
C2
0.1µF
R4
976k
R1
1M
DIV
DIV
R6
121k
R3
146k
R5
102k
R2
280k
699512 TA03
Cycling (10 Seconds On/Off) Symmetrical Power Supplies
M2
Si4435DY
15V
15V
IN
OUT
R6
20k
R2
1k
M3
R11
5k
RST
GND
SET
OUT
Si9410
LTC6995-1
+
5V
V
C1
R8
0.1µF
1M
M4
DIV
Si4435DY
R10
237k
R9
392k
R1
100k
R3
50k
–15V
IN
–15V
OUT
M1
Si9410
699512 TA04
Isolated AC Load Flasher
5V
0.1µF
R3
5
+
R4
R5
5.94k
U2
40W LAMP
10k
215Ω
MOC3041M
V
1
2
1
6
4
6
4
OPEN = OFF
GND = ON
HOT
117V AC
RST
OUT
R1
LTC6995-1
R7
100Ω
1M
3
U3
NTE5642
SET
DIV
5V
ZERO
CROSSING
GND
2
R
SET
R2
392k
C2
0.022µF
237k
R6
10k
NEUTRAL
AC
10 SECONDS ON/OFF
699512 TA05
ISOLATION BARRIER = 7500V
699512f
24
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
Typical applicaTions
Interval (Wiper) Timer
2s
5s
15s
30s
5V
+
V
1m
2m
4m
OFF
OUTPUT
0.1µF
RST
GND
SET
OUT
TRIG
OUT
24.9k
178k
59k
2s
LTC6995-1
LTC6993-1
+
+
+
+
2s
V
V
V
GND
SET
V
5s
15s
t
0.1µF
INTERVAL
1M
1M
2 SECONDS TO
4 MINUTES
30s
DIV
DIV
1m
2m
4m
383k
681k
2s
29.4k
90.9k
OFF
699512 TA06
2s
280k
113k
133k
154k
5s
15s
30s
1m
2m
4m
OFF
Adjustable Time Lapse Photography Intervalometer
SHUTTER
OPEN
TIME LAPSE
TIME LAPSE
RST
GND
SET
OUT
TRG
OUT
OUTPUT
LTC6995-1
LTC6993-3
+
+
+
+
V
V
GND
SET
V
V
0.1µF
3s TO
1M
66.5k
56.2k
30m TO
3Hrs
DIV
DIV
30s
SHORT
SHORT
LONG
LONG TIMER
3s TO 3Hrs
NON-RETRIGGERABLE
ONE SHOT TIMER
0.3s TO 30s
1M
2M
30s TO
3m
3m TO
30m
1M
2M
392k
967k
LONG
523k
681k
0.3s TO
3s
3s TO
30s
681k
887k
1M
TIME LAPSE
EXPOSURE TIME
699512 TA09
699512f
25
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-ꢀ7ꢀ5 Rev A)
0.70 0.05
ꢀ.65 0.05
3.55 0.05
(2 SIDES)
2.ꢀ5 0.05
PACKAGE
OUTLINE
0.25 0.05
0.50 BSC
ꢀ.35 0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.ꢀꢀ5
2.00 0.ꢀ0
(2 SIDES)
0.40 0.ꢀ0
TYP
R = 0.05
TYP
4
6
3.00 0.ꢀ0 ꢀ.65 0.ꢀ0
(2 SIDES)
(2 SIDES)
PIN ꢀ BAR
TOP MARK
(SEE NOTE 6)
PIN ꢀ NOTCH
R0.20 OR 0.25
× 45° CHAMFER
(DCB6) DFN 0405
3
ꢀ
0.25 0.05
0.50 BSC
0.75 0.05
0.200 REF
ꢀ.35 0.ꢀ0
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
ꢀ. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
699512f
26
For more information www.linear.com/6995
LTC6995-1/LTC6995-2
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.4 MIN
1.50 – 1.75
(NOTE 4)
2.80 BSC
3.85 MAX 2.62 REF
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
699512f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
27
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC6995-1/LTC6995-2
Typical applicaTion
Sentry Timer
+
V
Q
CLK
D
+
V
FF
+
Q
V
100k
CLR
PUSH BUTTON
EVERY 4 HOURS OR
ALARM SOUNDS
RST
GND
SET
OUT
LTC6995-2
15Ω
32Ω
+
+
800Hz
ALARM TONE
DIVCODE = 0
V
V
4 HOUR TIMER
DIVCODE = 7
R1
887k
DIV
R2
49.9k
60.4k
332k
75k
699512 TA07
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
Wide Frequency Range
Low Power, Wide Frequency Range
Micropower, I = 35µA at 400kHz
LTC1799
1MHz to 33MHz ThinSOT Silicon Oscillator
1MHz to 20MHz ThinSOT Silicon Oscillator
LTC6900
LTC6906/LTC6907 10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillators
SUPPLY
LTC6930
LTC6990
LTC6991
LTC6992
LTC6993
LTC6994
Fixed Frequency Oscillator, 32.768kHz to 8.192MHz
TimerBlox: Voltage-Controlled Silicon Oscillator
TimerBlox: Very Low Frequency Oscillator with Reset
0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
Fixed-Frequency or Voltage-Controlled Operation
Cycle Time from 1ms to 9.5 Hours, No Capacitors, 2.2% Accurate
Simple PWM with Wide Frequency Range
TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM)
TimerBlox: Monostable Pulse Generator (One Shot)
TimerBlox: Delay Block/Debouncer
Resistor Programmable Pulse Width of 1µs to 34sec
Delays Rising, Falling or Both Edges 1µs to 34sec
699512f
LT 0213 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
LINEAR TECHNOLOGY CORPORATION 2013
(408)432-1900 FAX: (408) 434-0507 www.linear.com/6995
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