LTC6994-1 [Linear]
TimerBlox: Delay Block/ Debouncer; TimerBlox系列：延迟模块/去抖
| 型号： | LTC6994-1 |
| 厂家： | 
Linear |
| 描述： | TimerBlox: Delay Block/ Debouncer |
| 文件： | 总24页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC6994-1/LTC6994-2
TimerBlox: Delay Block/
Debouncer
FEATURES
DESCRIPTION
The LTC®6994 is a programmable delay block with a
range of 1µs to 33.6 seconds. The LTC6994 is part of the
TimerBlox™ family of versatile silicon timing devices.
n
Delay Range: 1µs to 33.6 Seconds
n
Configured with 1 to 3 Resistors
n
Delay Max Error:
– <2.3% for Delay > 512µs
A single resistor, R , programs an internal master os-
SET
– <3.4% for Delay of 8µs to 512µs
– <5.1% for Delay of 1µs to 8µs
cillator frequency, setting the LTC6994’s time base. The
input-to-output delay is determined by this master oscil-
n
Delay One or Both Rising/Falling Edges
lator and an internal clock divider, N , programmable to
DIV
n
2.25V to 5.5V Single Supply Operation
21
eight settings from 1 to 2 :
n
70µA Supply Current at 10µs Delay
n
NDIV •RSET
500µs Start-Up Time
tDELAY
=
•1µs, NDIV = 1, 8, 64,...,221
n
CMOS Output Driver Sources/Sinks 20mA
50kΩ
n
–40°C to 125°C Operating Temperature Range
The output (OUT) follows the input (IN) after delaying the
rising and/or falling transitions. The LTC6994-1 will delay
the rising or falling edge. The LTC6994-2 will delay both
transitions, and adds the option to invert the output.
n
Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN
APPLICATIONS
DEVICE
DELAY FUNCTION
n
Noise Discriminators/Pulse Qualifiers
LTC6994-1
or
n
Delay Matching
n
Switch Debouncing
n
High Vibration, High Acceleration Environments
LTC6994-2
or
n
Portable and Battery-Powered Equipment
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
TimerBlox and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
The LTC6994 also offers the ability to dynamically adjust
the delay time via a separate control voltage.
The LTC6994 is available in the 6-lead SOT-23 (ThinSOT)
and 6-lead 2mm × 3mm DFN packages.
TYPICAL APPLICATION
Noise Discriminator
NOISY
INPUT
QUALIFIED
OUTPUT
IN
2V/DIV
IN
OUT
LTC6994-2
3.3V
+
1.5µs
1.5µs
GND
SET
V
0.1µF
OUT
2V/DIV
DIV
R
SET
699412 TA01b
699412 TA01a
20µs/DIV
75k
699412f
1
LTC6994-1/LTC6994-2
ABSOLUTE MAXIMUM RATINGS (Note 1)
+
Supply Voltage (V ) to GND ........................................6V
Specified Temperature Range (Note 3)
Maximum Voltage on Any Pin
LTC6994C ................................................ 0°C to 70°C
LTC6994I .............................................–40°C to 85°C
LTC6994H.......................................... –40°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
+
..................................(GND – 0.3V) ≤ V ≤ (V + 0.3V)
PIN
Operating Temperature Range (Note 2)
LTC6994C ............................................–40°C to 85°C
LTC6994I .............................................–40°C to 85°C
LTC6994H.......................................... –40°C to 125°C
S6 Package.......................................................300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
+
6
5
4
OUT
GND
IN
V
1
2
3
IN 1
GND 2
SET 3
6 OUT
7
DIV
SET
+
5 V
4 DIV
DCB PACKAGE
S6 PACKAGE
6-LEAD (2mm × 3mm) PLASTIC DFN
= 150°C, θ = 64°C/W, θ = 10.6°C/W
6-LEAD PLASTIC TSOT-23
T
T
JMAX
= 150°C, θ = 192°C/W, θ = 51°C/W
JMAX
JA
JC
JA
JC
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
LTC6994CDCB-1#TRMPBF LTC6994CDCB-1#TRPBF LFCT
LTC6994IDCB-1#TRMPBF LTC6994IDCB-1#TRPBF LFCT
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC6994HDCB-1#TRMPBF LTC6994HDCB-1#TRPBF LFCT
LTC6994CDCB-2#TRMPBF LTC6994CDCB-2#TRPBF LFCW
LTC6994IDCB-2#TRMPBF LTC6994IDCB-2#TRPBF
LFCW
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
LTC6994HDCB-2#TRMPBF LTC6994HDCB-2#TRPBF LFCW
LTC6994CS6-1#TRMPBF
LTC6994IS6-1#TRMPBF
LTC6994HS6-1#TRMPBF
LTC6994CS6-2#TRMPBF
LTC6994IS6-2#TRMPBF
LTC6994HS6-2#TRMPBF
LTC6994CS6-1#TRPBF
LTC6994IS6-1#TRPBF
LTC6994HS6-1#TRPBF
LTC6994CS6-2#TRPBF
LTC6994IS6-2#TRPBF
LTC6994HS6-2#TRPBF
LTFCV
LTFCV
LTFCV
LTFCX
LTFCX
LTFCX
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
0°C to 70°C
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
6-Lead Plastic TSOT-23
–40°C to 85°C
–40°C to 125°C
6-Lead Plastic TSOT-23
TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
699412f
2
LTC6994-1/LTC6994-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
Delay Time
1µ
33.55
sec
DELAY
Delay Accuracy (Note 4)
N
≥ 512
1.7
2.4
3.8
2.3
3.0
%
%
∆t
DELAY
DIV
l
l
l
8 ≤ N ≤ 64
3.4
4.4
%
%
DIV
N
DIV
= 1
5.1
6.2
%
%
l
l
Delay Drift Over Temperature
Delay Change With Supply
N
N
≥ 512
≤ 64
0.006
0.008
%/°C
%/°C
∆t /∆T
DELAY
DIV
DIV
+
+
l
l
N
≥ 512
V = 4.5V to 5.5V
–0.6
–0.4
–0.2
–0.1
%
%
DIV
V = 2.25V to 4.5V
+
+
l
l
l
8 ≤ N ≤ 64
V = 4.5V to 5.5V
–0.9
–0.7
–1.1
–0.2
–0.2
–0.1
%
%
%
DIV
V = 2.7V to 4.5V
0.4
0.9
+
V = 2.25V to 2.7V
+
+
Delay Jitter (Note 10)
N
DIV
= 1
V = 5.5V
1.0
0.5
%
P-P
%
P-P
V = 2.25V
N
N
N
N
= 8
0.20
0.05
0.20
0.03
%
%
%
%
DIV
P-P
P-P
P-P
= 64
DIV
= 512
= 4096
DIV
DIV
P-P
t
Delay Change Settling Time (Note 9)
t
= t
/N
6 • t
µs
S
MASTER
DELAY DIV
MASTER
Power Supply
+
l
l
V
Operating Supply Voltage Range
Power-On Reset Voltage
Supply Current (Idle)
2.25
5.5
V
V
1.95
+
+
l
l
I
R = ∞, R = 50k, N ≤ 64
V = 5.5V
165
125
200
160
µA
µA
S(IDLE)
L
SET
DIV
V = 2.25V
+
+
l
l
R = ∞, R = 50k, N ≥ 512 V = 5.5V
135
105
175
140
µA
µA
L
SET
DIV
V = 2.25V
+
+
l
l
R = ∞, R = 800k, N ≤ 64 V = 5.5V
70
60
110
95
µA
µA
L
SET
DIV
V = 2.25V
+
+
l
l
R = ∞, R = 800k, N ≥ 512 V = 5.5V
65
55
100
90
µA
µA
L
SET
DIV
V = 2.25V
Analog Inputs
l
l
l
l
l
V
Voltage at SET Pin
0.97
1.00
75
1.03
V
SET
V
Drift Over Temperature
µV/°C
kΩ
V
∆V /∆T
SET
SET
R
Frequency-Setting Resistor
DIV Pin Voltage
50
0
800
SET
DIV
+
V
V
+
DIV Pin Valid Code Range (Note 5)
Deviation from Ideal
DIV
1.5
%
∆V /∆V
DIV
+
V
/V = (DIVCODE + 0.5)/16
l
DIV Pin Input Current
10
nA
699412f
3
LTC6994-1/LTC6994-2
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, IN = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital I/O
IN Pin Input Capacitance
IN Pin Input Current
2.5
pF
nA
V
+
IN = 0V to V
10
+
l
l
V
V
High Level IN Pin Input Voltage
Low Level IN Pin Input Voltage
Output Current
(Note 6)
(Note 6)
0.7 • V
IH
+
0.3 • V
V
IL
+
I
V = 2.7V to 5.5V
20
mA
OUT(MAX)
+
l
l
V
High Level Output Voltage (Note 7)
V = 5.5V
I
I
= –1mA
= –16mA
5.45
4.84
5.48
5.15
V
V
OH
OUT
OUT
+
l
l
V = 3.3V
I
I
= –1mA
= –10mA
3.24
2.75
3.27
2.99
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= –1mA
= –8mA
2.17
1.58
2.21
1.88
V
V
OUT
OUT
+
l
l
V
Low Level Output Voltage (Note 7)
V = 5.5V
I
I
= 1mA
= 16mA
0.02
0.26
0.04
0.54
V
V
OL
OUT
OUT
+
l
l
V = 3.3V
I
I
= 1mA
= 10mA
0.03
0.22
0.05
0.46
V
V
OUT
OUT
+
l
l
V = 2.25V
I
I
= 1mA
= 8mA
0.03
0.26
0.07
0.54
V
V
OUT
OUT
+
t
PD
Propagation Delay
V = 5.5V
10
14
24
ns
ns
ns
+
V = 3.3V
+
V = 2.25V
+
t
t
Minimum Recognized Input Pulse Width
Output Rise Time (Note 8)
V = 3.3V
5
ns
WIDTH
r
+
V = 5.5V
1.1
1.7
2.7
ns
ns
ns
+
V = 3.3V
+
V = 2.25V
+
t
Output Fall Time (Note 8)
V = 5.5V
1.0
1.6
2.4
ns
ns
ns
f
+
V = 3.3V
+
V = 2.25V
Note 6: The IN pin has hysteresis to accommodate slow rising or falling
signals. The threshold voltages are proportional to V . Typical values can
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
+
be estimated at any supply voltage using:
+
+
V
≈ 0.55 • V + 185mV and V
≈ 0.48 • V – 155mV
IN(RISING)
IN(FALLING)
Note 2: The LTC6994C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 3: The LTC6994C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6994C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6994I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6994H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Settling time is the amount of time required for the output to settle
within 1% of the final delay after a 0.5× or 2× change in I
.
SET
Note 10: Jitter is the ratio of the deviation of the programmed delay to the
mean of the delay. This specification is based on characterization and is
not 100% tested.
Note 4: Delay accuracy is defined as the deviation from the t
DELAY
equation, assuming R is used to program the delay.
SET
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
699412f
4
LTC6994-1/LTC6994-2
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
Delay Drift vs Temperature
(NDIV ≤ 64)
Delay Drift vs Temperature
(NDIV ≤ 64)
Delay Drift vs Temperature
(NDIV ≤ 64)
1.5
1.0
0.5
0
1.5
1.5
1.0
0.5
0
R
SET
= 50k
R
SET
= 800k
R
SET
= 200k
3 PARTS
3 PARTS
3 PARTS
1.0
0.5
0
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
699412 G01
699412 G03
699412 G02
Delay Drift vs Temperature
(NDIV ≥ 512)
Delay Drift vs Temperature
(NDIV ≥ 512)
Delay Drift vs Temperature
(NDIV ≥ 512)
1.5
1.0
0.5
0
1.5
1.0
0.5
0
1.5
1.0
0.5
0
R
SET
= 200k
R
SET
= 800k
R
SET
= 50k
3 PARTS
3 PARTS
3 PARTS
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
75
–50 –25
0
25
75
699412 G05
699412 G06
699412 G04
Delay Drift vs Supply Voltage
(NDIV = 1)
Delay Drift vs Supply Voltage
(NDIV = 1)
Delay Drift vs Supply Voltage
(NDIV > 1)
1.0
0.8
1.0
0.8
1.0
0.8
+
RISING EDGE DELAY
FALLING EDGE DELAY
REFERENCED TO V = 4V
+
+
REFERENCED TO V = 4V
REFERENCED TO V = 4V
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
R
R
R
= 50k
= 200k
= 800k
R
R
R
= 50k
= 200k
= 800k
R
R
R
= 50k, N = 8
DIV
SET
SET
SET
SET
SET
SET
SET
SET
SET
= 50k TO 800k, N ≥ 512
DIV
= 800k, N = 8
DIV
2
3
4
5
6
2
3
4
5
6
2
3
4
6
5
SUPPLY (V)
SUPPLY (V)
SUPPLY (V)
699412 G07
699412 G08
699412 G09
699412f
5
LTC6994-1/LTC6994-2
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
Delay Error vs RSET
(8 ≤ NDIV ≤ 64)
Delay Error vs RSET (NDIV = 1)
Delay Error vs RSET (NDIV ≥ 512)
5
4
5
4
5
4
3 PARTS
RISING EDGE DELAY
3 PARTS
3 PARTS
3
3
3
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
50
100
200
(kΩ)
400
800
50
100
200
(kΩ)
400
800
50
100
200
(kΩ)
400
800
R
R
R
SET
SET
SET
699412 G12
699412 G10
699412 G11
Delay Error vs RSET (NDIV =1)
Delay Error vs DIVCODE
Delay Error vs DIVCODE
5
4
5
4
5
4
FALLING EDGE DELAY
3 PARTS
LTC6994-1
LTC6994-1
R
= 50k
R
= 800k
SET
SET
3 PARTS
3 PARTS
3
3
3
2
2
2
1
1
1
0
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
RISING EDGE
FALLING EDGE
DELAY
RISING EDGE
FALLING EDGE
DELAY
DELAY
DELAY
50
100
200
(kΩ)
400
800
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
R
DIVCODE
DIVCODE
SET
699412 G13
699412 G14
699412 G15
VSET Drift vs ISET
VSET Drift vs Supply Voltage
VSET vs Temperature
1.0
0.8
1.0
0.8
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
3 PARTS
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
+
REFERENCED TO I
= 10µA
REFERENCED TO V = 4V
SET
20
2
4
5
6
0
10
(µA)
15
3
5
–50
0
25
50
75 100 125
–25
I
SUPPLY (V)
TEMPERATURE (°C)
SET
699412 G16
699412 G17
699412 G18
699412f
6
LTC6994-1/LTC6994-2
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
Typical VSET Distribution
Supply Current vs Supply Voltage
Supply Current vs Temperature
250
200
150
100
50
250
200
150
100
50
300
250
2 LOTS
DFN AND SOT-23
1274 UNITS
LTC6994-1
LTC6994-1
R
= 50k,
SET
I
MEASURED
I
MEASURED
S(ACTIVE)
÷1, ACTIVE
S(ACTIVE)
WITH f = 1/(2 • t
)
WITH f = 1/(2 • t
)
IN
DELAY
IN
DELAY
R
SET
= 50k, ÷1, ACTIVE
200
150
R
SET
= 50k,
÷1, IDLE
R
= 50k, ÷1, IDLE
SET
R
= 100k, ÷8, ACTIVE
= 100k, ÷8, IDLE
SET
R
SET
= 100k, ÷8, ACTIVE
R
100
50
0
SET
R
= 100k, ÷8, IDLE
SET
R
SET
= 800k, ÷512
R
SET
= 800k, ÷512
C
R
= 5pF
= ∞
C
R
= 5pF
= ∞
LOAD
LOAD
LOAD
LOAD
0
0
–50 –25
0
25
50
75 100 125
0.98
0.996
V
1.004
(V)
1.012
1.02
0.988
2
3
4
5
6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SET
699412 G19
699412 G21
699412 G20
Supply Current vs IN Pin Voltage
Supply Current vs tDELAY (5V)
Supply Current vs tDELAY (2.5V)
250
200
150
100
50
250
200
150
100
50
250
200
150
100
50
ACTIVE CURRENT MEASURED
USING LTC6994-1 WITH
ACTIVE CURRENT MEASURED
USING LTC6994-1 WITH
f
IN
= 1/(2 • t
)
f
= 1/(2 • t
)
DELAY
5V
5V
IN RISING
IN
DELAY
IN FALLING
÷1
÷8
÷1
+
3.3V
IN RISING
3.3V
IN FALLING
÷8
+
V
= 5V
V
= 2.5V
C
R
= 5pF
= ∞
C
= 5pF
= ∞
C
= 5pF
= ∞
ACTIVE
IDLE
ACTIVE
IDLE
LOAD
LOAD
LOAD
LOAD
R
R
LOAD
LOAD
0
0
0
0
0.2
0.4
0.6
/V (V/V)
0.8
1.0
0.001
0.01
0.1
1
(ms)
10
100
0.001
0.01
0.1
t
DELAY
1
(ms)
10
100
+
t
V
DELAY
IN
699412 G23
699412 G24
699412 G22
IN Threshold Voltage
vs Supply Voltage
Typical ISET Current Limit vs V+
Peak-to-Peak Jitter vs tDELAY
1.2
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1000
800
600
400
200
0
SET PIN SHORTED TO GND
PEAK-TO-PEAK
DELAY
MEASURED OVER
30s INTERVALS
÷1, 5.5V
t
VARIATION
1.0
0.8
POSITIVE GOING
NEGATIVE GOING
0.6
0.4
÷1, 2.25V
÷8, 5.5V
÷512
0.2
0
÷64
÷4096
÷8, 2.25V
0.01
2
3
4
5
6
0.001
0.1
t
1
10
100
2
3
4
5
6
SUPPLY VOLTAGE (V)
(ms)
SUPPLY VOLTAGE (V)
DELAY
699412 G25
699412 G27
699412 G26
699412f
7
LTC6994-1/LTC6994-2
TYPICAL PERFORMANCE CHARACTERISTICS
V+ = 3.3V, RSET = 200k and TA = 25°C unless otherwise noted.
Input Propagation Delay (tPD
)
Rise and Fall Time
vs Supply Voltage
Output Resistance
vs Supply Voltage
vs Supply Voltage
3.0
2.5
2.0
1.5
1.0
0.5
0
50
45
40
35
30
25
20
15
10
5
25
20
15
10
5
C
= 5pF
C
= 5pF
LOAD
LOAD
OUTPUT SOURCING CURRENT
t
RISE
t
FALL
OUTPUT SINKING CURRENT
0
0
2
3
4
5
6
2
3
4
5
6
2
3
4
5
6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
699412 G29
699412 G30
699412 G28
Start-Up, RSET = 800k
(LTC6994-1)
Start-Up, RSET = 50k
(LTC6994-2, POL = 1)
+
+
V
V
7.2ms
500µs
2V/DIV
2V/DIV
IN
2V/DIV
IN
2V/DIV
OUT
2V/DIV
OUT
2V/DIV
+
+
699412 G31
699412 G32
V
= 2.5V
1ms/DIV
V
= 2.5V
100µs/DIV
PIN FUNCTIONS
V (Pin1/Pin5):SupplyVoltage(2.25Vto5.5V).Thissup-
ply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1µF capacitor.
(DCB/S6)
+
SET (Pin 3/Pin 3): Delay Setting Input. The voltage on the
SET pin (V ) is regulated to 1V above GND. The amount
SET
of current sourced from the SET pin (I ) programs the
SET
master oscillator frequency. The I
current range is
SET
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
1.25µA to 20µA. The delayed output transition will be not
occur if I drops below approximately 500nA. Once I
Input. The DIV pin voltage (V ) is internally converted
DIV
SET
SET
into a 4-bit result (DIVCODE). V may be generated by
DIV
increases above 500nA the delayed edge will transition.
A resistor connected between SET and GND is the most
accurate way to set the delay. For best performance, use
a precision metal or thin film resistor of 0.5% or better
toleranceand50ppm/°Corbettertemperaturecoefficient.
For lower accuracy applications an inexpensive 1% thick
film resistor may be used.
+
a resistor divider between V and GND. Use 1% resistors
to ensure an accurate result. The DIV pin and resistors
should be shielded from the OUT pin or any other traces
that have fast edges. Limit the capacitance on the DIV pin
to less than 100pF so that V settles quickly. The MSB
DIV
of DIVCODE (POL) selects the delay functionality. For the
LTC6994-1, POL = 0 will delay the rising transition and
POL = 1 will delay the falling transition. For the LTC6994-
2, both transitions are delayed so POL = 1 can be used
to invert the output.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
699412f
8
LTC6994-1/LTC6994-2
PIN FUNCTIONS (DCB/S6)
than 100pF maintains the stability of the feedback circuit
IN(Pin4/Pin1):LogicInput.Dependingontheversionand
POL bit setting, rising or falling edges on IN will propagate
to OUT after a programmable delay. The LTC6994-1 will
delay only the rising or falling edge. The LTC6994-2 will
delay both edges.
regulating the V voltage.
SET
+
V
IN
OUT
LTC6994
+
V
GND(Pin5/Pin2):Ground.Tietoalowinductanceground
plane for best performance.
+
GND
SET
V
C1
0.1µF
R1
R2
OUT (Pin 6/Pin 6): Output. The OUT pin swings from
DIV
+
GND to V with an output resistance of approximately
699412 PF
R
SET
30Ω. When driving an LED or other low impedance load a
series output resistor should be used to limit source/sink
current to 20mA.
BLOCK DIAGRAM (S6 package pin numbers shown)
5
+
V
R1
POL
DIV
IN
4-BIT A/D
CONVERTER
DIGITAL
FILTER
4
1
R2
INPUT
BUFFER
EDGE-
OUTPUT
OUT
CONTROLLED
DELAY
6
POLARITY
MASTER OSCILLATOR
(LTC6994-2)
LOGIC
1µs
50kΩ
V
I
SET
SET
PROGRAMMABLE DIVIDER
t
=
•
MASTER
MCLK
÷1, 8, 64, 512, 4096,
15 18 21
2
, 2 , 2
POR
HALT OSCILLATOR
IF I < 500nA
SET
I
SET
+
–
+
1V
V
SET
= 1V
–
SET
3
GND
2
699412 BD
I
SET
R
SET
699412f
9
LTC6994-1/LTC6994-2
OPERATION
The LTC6994 is built around a master oscillator with a 1µs
DIVCODE
minimum period. The oscillator is controlled by the SET
+
TheDIVpinconnectstoaninternal,V referenced4-bitA/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6994:
pin current (I ) and voltage (V ), with a 1µs/50kΩ
SET
SET
conversion factor that is accurate to 1.7% under typical
conditions.
1. DIVCODE determines the frequency divider setting,
VSET
1µs
50kΩ ISET
N .
DIV
tMASTER
=
•
2. The DIVCODE MSB is the POL bit, and configures a
different polarity setting on the two versions.
A feedback loop maintains V at 1V 30mV, leaving I
SET
SET
as the primary means of controlling the input-to-output
a. LTC6994-1:POLselectsrisingorfalling-edgedelays.
POL = 0 will delay rising-edge transitions. POL = 1
will delay falling-edge transitions.
delay. The simplest way to generate I is to connect a
SET
resistor (R ) between SET and GND, such that I
=
SET
SET
V
/R . The master oscillator equation reduces to:
SET SET
b. LTC6994-2: POL selects the output inversion.
POL = 1 inverts the output signal.
RSET
50kΩ
tMASTER = 1µs•
V
may be generated by a resistor divider between V+
DIV
and GND as shown in Figure 1.
From this equation, it is clear that V drift will not affect
SET
the input-to-output delay when using a single program
2.25V TO 5.5V
resistor (R ). Error sources are limited to R
toler-
of the LTC6994.
SET
SET
+
V
ance and the inherent accuracy ∆t
DELAY
R1
R2
LTC6994
R
may range from 50k to 800k (equivalent to I
SET
SET
DIV
between 1.25µA and 20µA).
GND
When the input makes a transition that will be delayed
(as determined by the part version and POL bit setting),
the master oscillator is enabled to time the delay. When
the desired duration is reached, the output is allowed to
transition.
699412 F01
Figure 1. Simple Technique for Setting DIVCODE
Table 1 offers recommended 1% resistor values that ac-
curatelyproducethecorrectvoltagedivisionaswellasthe
correspondingN andPOLvaluesfortherecommended
resistor pairs. Other values may be used as long as:
The LTC6994 also includes a programmable frequency
divider which can further divide the frequency by 1, 8, 64,
DIV
15 18
21
512, 4096, 2 , 2 or 2 . This extends the delay duration
by those same factors. The divider ratio N is set by a
resistor divider attached to the DIV pin.
DIV
+
1. The V /V ratio is accurate to 1.5% (including resis-
DIV
tor tolerances and temperature effects)
VSET
50kΩ ISET
NDIV
2. The driving impedance (R1||R2) does not exceed
500kΩ.
tDELAY
=
•
•1µs
With R in place of V /I the equation reduces to:
SET
SET SET
NDIV •RSET
tDELAY
=
•1µs
50kΩ
699412f
10
LTC6994-1/LTC6994-2
OPERATION
If the voltage is generated by other means (i.e., the output
Forexample,ifthesupplyis3.3VandthedesiredDIVCODE
+
of a DAC) it must track the V supply voltage. The last
is 4, V = 0.281 • 3.3V = 928mV ± 50mV.
DIV
column in Table 1 shows the ideal ratio of V
to the
DIV
Figure2illustratestheinformationinTable1,showingthat
supply voltage, which can also be calculated as:
N
is symmetric around the DIVCODE midpoint.
DIV
VDIV
V+
DIVCODE+ 0.5
=
± 1.5%
16
Table 1. DIVCODE Programming
+
DIVCODE
POL
0
N
Recommended t
R1 (k)
Open
976
R2 (k)
Short
102
V
DIV
/V
DIV
DELAY
0
1
1
1µs to 16µs
≤ 0.03125 0.015
0.09375 0.015
0.15625 0.015
0.21875 0.015
0.28125 0.015
0.34375 0.015
0.40625 0.015
0.46875 0.015
0.53125 0.015
0.59375 0.015
0.65625 0.015
0.71875 0.015
0.78125 0.015
0.84375 0.015
0.90625 0.015
≥ 0.96875 0.015
0
8
8µs to 128µs
64µs to 1.024ms
2
0
64
512
976
182
3
0
512µs to 8.192ms
4.096ms to 65.54ms
32.77ms to 524.3ms
262.1ms to 4.194sec
2.097sec to 33.55sec
2.097sec to 33.55sec
262.1ms to 4.194sec
32.77ms to 524.3ms
4.096ms to 65.54ms
512µs to 8.192ms
64µs to 1.024ms
1000
1000
1000
1000
1000
887
280
4
0
4,096
32,768
262,144
2,097,152
2,097,152
262,144
32,768
4,096
512
392
5
0
523
6
0
681
7
0
887
8
1
1000
1000
1000
1000
1000
976
9
1
681
10
11
12
13
14
15
1
523
1
392
1
280
1
64
182
1
8
8µs to 128µs
102
976
1
1
1µs to 16µs
Short
Open
POL BIT = 0
POL BIT = 1
10000
7
8
6
9
1000
100
10
5
10
11
4
12
3
1
2
13
0.1
1
14
0.01
0.001
0
15
+
+
0V
0.5•V
V
INCREASING V
DIV
699412 F02
Figure 2. Delay Range and POL Bit vs DIVCODE
699412f
11
LTC6994-1/LTC6994-2
OPERATION
Edge-Controlled Delay
low for the duration of t
. If IN stays high then OUT
DELAY
will transition high after this time. If the input doesn’t
remain high long enough for OUT to transition high then
the timing will restart on each successive rising edge. In
this way, the LTC6994-1 can serve as a pulse qualifier,
filtering out noisy or short signals.
The LTC6994 is a programmable delay or pulse qualifier. It
can perform noise filtering, which distinguishes it from a
delay line (which simply delays all input transitions).
WhenthevoltageontheLTC6994inputpin(IN)transitions
low or high, the LTC6994 can delay the corresponding
output transition by any time from 1µs to 33.6 seconds.
On a falling edge at the input, the output will follow im-
mediately (after a short propagation delay t ).Note that
PD
the output pulse width may be extremely short if IN falls
LTC6994-1 Functionality
immediately after OUT rises.
Figures3detailsthebasicoperationoftheLTC6994-1when
configured to delay rising edge transitions (POL = 0). A
rising edge on the IN pin initiates the timing. OUT remains
Figure 4 details the operation of the LTC6994-1 when
configured to delay falling edges (POL = 1).
t
WIDTH
IN
t
PD
t
PD
t
PD
t
PD
t
PD
t
PD
OUT
699412 F03
t
t
t
DELAY
DELAY
DELAY
Figure 3. Rising-Edge Delayed Timing Diagram (LTC6994-1, POL = 0)
t
WIDTH
IN
t
PD
t
PD
t
PD
t
PD
t
PD
t
PD
OUT
699412 F04
t
t
DELAY
t
DELAY
DELAY
Figure 4. Falling-Edge Delayed Timing Diagram (LTC6994-1, POL = 1)
699412f
12
LTC6994-1/LTC6994-2
OPERATION
LTC6994-2 Functionality
Iftheinputdoesn’tremainhighorlowlongenoughforOUT
to follow, the timing will restart on the next transition.
Figures 5 details the basic operation of the LTC6994-2
when configured for noninverting operation (POL = 0). As
before, a rising edge on the IN pin initiates the timing and,
Also unlike the LTC6994-1, the output pulse width can
never be less than t
. Therefore, the LTC6994-2 can
DELAY
if IN remains high, OUT will transition high after t
.
generate pulses with a defined minimum width.
DELAY
Unlike the LTC6994-1, falling edges are delayed in the
same way. When IN transitions low, OUT will follow after
DELAY
Figure 6 details the operation of the LTC6994-2 when the
output is inverted (POL = 1).
t
.
t
WIDTH
IN
t
PD
t
PD
t
PD
t
PD
t
PD
OUT
699412 F05
t
t
t
DELAY
t
DELAY
DELAY
DELAY
Figure 5. Both Edges Delayed Timing Diagram (LTC6994-2, POL = 0)
t
WIDTH
IN
t
PD
t
PD
t
PD
t
PD
t
PD
699412 F06
OUT
t
t
t
t
DELAY
DELAY
DELAY
DELAY
Figure 6. Both Edges Delayed (Inverting) Timing Diagram (LTC6994-2, POL = 1)
699412f
13
LTC6994-1/LTC6994-2
OPERATION
Changing DIVCODE After Start-Up
Start-Up Time
Following start-up, the A/D converter will continue
When power is first applied, the power-on reset (POR)
monitoring V for changes. Changes to DIVCODE will
circuit will initiate the start-up time, t
. The OUT pin
DIV
START
be recognized slowly, as the LTC6994 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
is held low during this time and the IN pin has no control
over the output. The typical value for t ranges from
START
0.5msto8msdependingonthemasteroscillatorfrequency
(independent of N ):
DIV
t
= 500 • t
MASTER
START(TYP)
t
= 16 • (∆DIVCODE + 6) • t
MASTER
DIVCODE
Duringstart-up,theDIVpinA/Dconvertermustdetermine
the correct DIVCODE before the LTC6994 can respond
to an input. The start-up time may increase if the supply
or DIV pin voltages are not stable. For this reason, it is
recommended to minimize the capacitance on the DIV
AchangeinDIVCODEwillnotberecognizeduntilitisstable,
andwillnotpassthroughintermediatecodes.Adigitalfilter
is used to guarantee the DIVCODE has settled to a new
value before making changes to the output. However, if
the delay timing is active during the transition, the actual
delay can take on a value between the two settings.
+
pin so it will properly track V . Less than 100pF will not
extend the start-up time.
At the end of t
the DIVCODE and IN pin settings are
START
DIV
500mV/DIV
recognized, and the state of the IN pin is transferred to the
512µs
output (without additional delay). If IN is high at the end of
IN
2V/DIV
t
, OUT will go high. Otherwise OUT will remain low.
START
4µs
256µs
The LTC6994-2 with POL = 1 is the exception because it
inverts the signal. At this point, the LTC6994 is ready to
respond to rising/falling edges on the input.
OUT
2V/DIV
699412 F07a
LTC6994-1
500µs/DIV
+
V
= 3.3V
= 200k
R
SET
+
V
Figure 7a. DIVCODE Change from 0 to 2
IN
DIV
500mV/DIV
512µs
t
PD
t
START
IF IN = 1 AT END OF t
*
*
IN
2V/DIV
START
(IN IGNORED)
OUT
IF IN = 0 AT END OF t
START
256µs
4µs
699412 F08
OUT
2V/DIV
*LTC6994-2 WITH POL = 1 INVERTS THE OUTPUT
Figure 8. Start-Up Timing Diagram
699412 F07b
LTC6994-1
+
500µs/DIV
V
R
= 3.3V
= 200k
SET
Figure 7b. DIVCODE Change from 2 to 0
699412f
14
LTC6994-1/LTC6994-2
APPLICATIONS INFORMATION
Basic Operation
Example: Design a circuit to delay falling edges by
DELAY
t
= 100µs with minimum power consumption.
The simplest and most accurate method to program the
LTC6994 is to use a single resistor, R , between the
SET
Step 1: Select the LTC6994 Version and POL Bit Setting.
SET and GND pins. The design procedure is a 3-step
To delay negative transitions, choose the LTC6994-1 with
POL = 1.
process.
Step 1: Select the LTC6994 Version and POL Bit Setting.
Step 2: Select the N Frequency Divider Value.
DIV
Choose LTC6994-1 to delay one (rising or falling) input
transition. The POL bit then defines which edge is to be
delayed. POL = 0 delays rising edges. POL = 1 delays
falling edges.
Choose an N
value that meets the requirements of
DIV
Equation (1), using t
= 100µs:
DELAY
6.25 ≤ N ≤ 100
DIV
Choose LTC6994-2 to delay rising and falling edges. Set
POL = 0 for normal operation, or POL = 1 to invert the
output.
Potential settings for N include 8 and 64. N = 8 is
DIV
DIV
the best choice, as it minimizes supply current by us-
ing a large R resistor. POL = 1 and N = 8 requires
SET
DIV
DIVCODE = 14. Using Table 1, choose R1 = 102k and R2
= 976k values to program DIVCODE = 14.
Step 2: Select the N Frequency Divider Value.
DIV
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
Step 3: Select R
.
SET
N
value. For a given delay time (t
), N should
DIV
DELAY DIV
Calculate the correct value for R using Equation (2).
SET
be selected to be within the following range:
50k 100µs
1µs
RSET
=
•
= 625k
tDELAY
16µs
tDELAY
1µs
8
≤ NDIV
≤
(1)
Since 625k is not available as a standard 1% resistor,
To minimize supply current, choose the lowest N value.
DIV
substitute 619k if a –0.97% shift in t is acceptable.
DELAY
However,insomecasesahighervalueforN willprovide
DIV
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
better accuracy (see Electrical Characteristics).
Table 1 can also be used to select the appropriate N
DIV
The completed design is shown in Figure 9.
values for the desired t
.
DELAY
With POL already chosen, this completes the selection of
IN
OUT
LTC6994-1
DIVCODE. Use Table 1 to select the proper resistor divider
2.25V TO 5.5V
+
or V /V ratio to apply to the DIV pin.
+
DIV
GND
SET
V
R1
102k
0.1µF
Step 3: Calculate and Select R
.
SET
DIVCODE = 14
DIV
R
SET
R2
The final step is to calculate the correct value for R
using the following equation:
SET
625k
976k
699412 F09
tDELAY
1µs NDIV
50k
Figure 9. 100µs Negative-Edge Delay
RSET
=
•
(2)
Select the standard resistor value closest to the calculated
value.
699412f
15
LTC6994-1/LTC6994-2
APPLICATIONS INFORMATION
Voltage-Controlled Delay
Digital Delay Control
With one additional resistor, the LTC6994 output delay
can be manipulated by an external voltage. As shown in
The control voltage can be generated by a DAC (digital-to-
analog converter), resulting in a digitally-controlled delay.
Many DACs allow for the use of an external reference. If
Figure 10, voltage V
sources/sinks a current through
CTRL
R
MOD
to vary the I
current, which in turn modulates
such a DAC is used to provide the V
voltage, the V
SET
CTRL SET
the delay as described in Equation (3):
dependencycanbeeliminatedbybufferingV andusing
SET
it as the DAC’s reference voltage, as shown in Figure 11.
NDIV •RMOD
50kΩ
1µs
TheDAC’soutputvoltagenowtracksanyV variationand
tDELAY
=
•
(3)
SET
RMOD VCTRL
eliminates it as an error source. The SET pin cannot be tied
directlytothereferenceinputoftheDACbecausethecurrent
drawn by the DAC’s REF input would affect the delay.
1+
–
RSET VSET
IN
OUT
LTC6994
I
Extremes (Master Oscillator Frequency Extremes)
SET
+
V
When operating with I
outside of the recommended
+
SET
GND
V
C1
0.1µF
1.25µA to 20µA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
R1
R
MOD
V
SET
DIV
CTRL
R
R2
SET
The oscillator will still function with reduced accuracy for
SET
stop. Under this condition, the delay timing can still be
699412 F10
I
< 1.25µA. At approximately 500nA, the oscillator will
Figure 10. Voltage-Controlled Delay
initiated, but will not terminate until I
the master oscillator starts again.
increases and
SET
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
IN
OUT
LTC6994
+
V
+
+
V
GND
SET
V
0.1µF
C1
0.1µF
R1
DIV
+
–
1/2
LTC6078
R2
+
699412 F11
V
0.1µF
N
• R
50kΩ
1µs
DIV
MOD
t
=
•
DELAY
R
R
D
IN
4096
MOD
1+
–
V
CC
REF
SET
D
IN
D
IN
= 0 TO 4095
R
MOD
V
OUT
CLK
µP
LTC1659
CS/LD
R
SET
GND
Figure 11. Digitally Controlled Delay
699412f
16
LTC6994-1/LTC6994-2
APPLICATIONS INFORMATION
Settling Time
Even an excellent layout will allow some coupling between
IN and SET. Additional error is included in the specified
Following a 2× or 0.5× step change in ISET, the out-
put delay takes approximately six master clock cycles
(6 • tMASTER) to settle to within 1% of the final value.
An example is shown in Figure 12, using the circuit in
Figure 10.
accuracy for N = 1 to account for this. Figure 13 shows
DIV
that ÷1 supply variation is dependent on coupling from
rising or falling inputs.
A very poor layout can actually degrade performance
further. The PCB layout should avoid routing SET next to
IN (or any other fast-edge, wide-swing signal).
V
CTRL
2V/DIV
IN
5V/DIV
OUT
1.0
0.8
5V/DIV
DELAY
2µs/DIV
0.6
FALLING EDGE DELAY
0.4
699412 F12
LTC6994-1
20µs/DIV
+
V
= 3.3V
0.2
0
DIVCODE = 0
R
R
OUT
= 200k
= 464k
SET
MOD
RISING EDGE DELAY
–0.2
t
= 3µs AND 6µs
–0.4
–0.6
Figure 12. Typical Settling Time
R
N
= 50k
= 1
SET
DIV
–0.8
–1.0
Coupling Error
2
4
5
6
3
The current sourced by the SET pin is used to bias the in-
ternalmasteroscillator.TheLTC6994respondstochanges
SUPPLY (V)
699412 F13
in I
almost immediately, which provides excellent
Figure 13. Delay Drift vs Supply Voltage
SET
settling time. However, this fast response also makes the
SET pin sensitive to coupling from digital signals, such
as the IN input.
699412f
17
LTC6994-1/LTC6994-2
APPLICATIONS INFORMATION
Power Supply Current
∆I
canbeestimatedusingtheequationsinTable 3,
S(ACTIVE)
assuming a periodic input with frequency f . The equa-
IN
The Electrical Characteristics table specifies the supply
current while the part is idle (waiting for an input transi-
tions assume the input pulse width is greater than t
otherwise, the output will not transition (and the increase
in supply current will be less).
;
DELAY
tion). I
varies with the programmed t
and the
S(IDLE)
DELAY
supply voltage, as described by the equations in Table 2,
valid for both the LTC6994-1 and LTC6994-2.
Table 3. Active Increase in Supply Current
CONDITION
DEVICE
TYPICAL ∆I
*
S(ACTIVE)
Table 2. Approximate Idle Supply Current Equations
+
LTC6994-1
LTC6994-2
f
• V • (N • 5pF + 18pF + C
)
IN
DIV
LOAD
CONDITION
TYPICAL I
S(IDLE)
N
DIV
≤ 64
+
f
IN
• V • (N • 10pF + 22pF + C
)
DIV
LOAD
V+ • N •7pF + 4pF
V+
500kΩ
(
)
+
+
DIV
N
DIV
≥ 512 Either Version
f
• V • C
N
DIV
≤ 64
+ 2.2•ISET + 50µA
IN
LOAD
tDELAY
*Ignoring resistive loads (assumes R
= ∞)
LOAD
V+ •NDIV •7pF
V+
500kΩ
+
+ 1.8•ISET + 50µA
N
DIV
≥ 512
Figures 14 and 15 show how the supply current increases
tDELAY
from I
) as the input frequency increases. At higher
S(IDLE
N
settings, the increase in active current is smaller.
DIV
When an input transition starts the delay timing circuity,
the instantaneous supply current increases to I
.
S(ACTIVE)
I
= I
+ ∆I
S(IDLE) S(ACTIVE)
S(ACTIVE)
250
+
250
+
V
= 3.3V
V
= 3.3V
f
< 1/(2 • t
) TO ALLOW RISING AND
IN
DELAY
INPUT PULSE WIDTH = 1.1 • t
DELAY
FALLING DELAYS TO REACH THE OUTPUT
200
150
100
50
200
÷1, R
= 50k
÷1, R
= 50k
SET
SET
÷8, R
= 50k
SET
÷8, R
= 50k
SET
150
100
50
÷1, R
÷1, R
= 100k
= 800k
SET
÷1, R
÷1, R
= 100k
= 800k
SET
SET
SET
C
= 5pF
C
= 5pF
LOAD
LOAD
LOAD
LOAD
R
= ∞
R
= ∞
0
0
“IDLE”
0.1
0.2
f
0.3
0.4
0.5
“IDLE”
0.2
0.4
f
0.6
0.8
1.0
• t
• t
IN DELAY
IN DELAY
699412 F15
699412 F14
Figure 14. IS(ACTIVE) vs Input Frequency, LTC6994-1
Figure 15. IS(ACTIVE) vs Input Frequency, LTC6994-2
699412f
18
LTC6994-1/LTC6994-2
APPLICATIONS INFORMATION
Supply Bypassing and PCB Layout Guidelines
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
TheLTC6994isanaccuratemonostablemultivibratorwhen
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
3. Place R as close as possible tothe SETpinand make
SET
adirect,shortconnection.TheSETpinisacurrentsum-
ming node and currents injected into this pin directly
modulate the output delay. Having a short connection
minimizes the exposure to signal pickup.
Figure16showsexamplePCBlayoutsforboththeSOT-23
andDCBpackagesusing0603sizedpassivecomponents.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6994. These layouts are
a guide and need not be followed exactly.
4. Connect R directly to the GND pin. Using a long path
SET
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
+
1. Connect the bypass capacitor, C1, directly to the V and
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
GND pins using a low inductance path. The connection
from C1 to the V pin is easily done directly on the top
+
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
layer. For the DCB package, C1’s connection to GND is
also simply done on the top layer. For the SOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that,C1’sGNDconnectioncanbeaccomplishedthrough
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
IN
OUT
LTC6994
+
+
GND
V
V
C1
0.1µF
R1
R2
SET
DIV
R
SET
+
+
V
+
C1
V
R1
C1
V
OUT
GND
IN
IN
OUT
+
DIV
SET
GND
V
R2
SET
DIV
R1
R
SET
R
SET
R2
699412 F16
DCB PACKAGE
TSOT-23 PACKAGE
Figure 16. Supply Bypassing and PCB Layout
699412f
19
LTC6994-1/LTC6994-2
TYPICAL APPLICATIONS
Delayed One-Shot
IN
DELAYED PULSE OUT
5V
IN
OUT
LTC6994-1
TRIG
OUT
LTC6993-1
5V
+
+
GND
SET
V
GND
SET
V
0.1µF
0.1µF
1M
DIV
DIV
604k
121k
392k
t
_
= 50ms
t
= 10ms
RISE DELAY
ONESHOT
IN
DELAY
50ms
SHOT
10ms
OUT
DELAY
SHOT
699412 TA02
Pulse Stretcher
IN
OUT
IN
OUT
LTC6994-1
+
+
GND
SET
V
V
0.1µF
182k
976k
DIV
= 1ms
787k
t
MIN
OUTPUT PULSE DURATION = t
_
+ 1ms
PULSE IN
IN
OUT
t
t
MIN
MIN
699412 TA03
Switch/Relay Debouncer
+
V
OUT
IN
OUT
LTC6994-2
OR
+
V
CHATTER STABLE
OR
+
+
GND
SET
V
V
0.1µF
1M
CHATTER STABLE
DIV
154k
523k
t = 100ms
699412 TA04
OUTPUT GOES TO SAME FINAL LEVEL OF INPUT
AFTER STABLE FOR 100ms
699412f
20
LTC6994-1/LTC6994-2
TYPICAL APPLICATIONS
Edge Chatter Filter
IN
OUT
IN
OUT
LTC6994-2
+
+
V
GND
V
0.1µF
SET
DIV
499k
10µs
INPUT MUST BE STABLE FOR AT LEAST 10µs
IN
OUT
10µs
10µs
10µs
NOISY EDGES
10µs
699412 TA05
NORMAL
Crossover Gate—Break-Before-Make Interval Timer
+
V
LOAD
LOW
100k
FALLING
DELAYED
P
IN
IN
OUT
LTC6994-1
TP0610
LOAD
LOAD
HIGH
+
+
V
GND
SET
V
+
+
IN
V
V
0.1µF
100k
DIV
= 1ms
+
V
LOAD
OFF OFF
OFF
V /2
V
LOAD
787k
442k
t
DELAY
GND
1ms OFF INTERVAL
AT EACH TRANSITION
100k
RISING
DELAYED
N
IN
OUT
LTC6994-1
2N7000
100k
+
+
V
GND
SET
V
699412 TA06
0.1µF
DIV
= 1ms
787k
t
DELAY
699412f
21
LTC6994-1/LTC6994-2
PACKAGE DESCRIPTION
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
0.70 ±0.05
1.65 ±0.05
(2 SIDES)
3.55 ±0.05
2.15 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
2.00 ±0.10
(2 SIDES)
0.40 ± 0.10
R = 0.05
TYP
4
6
3.00 ±0.10 1.65 ± 0.10
(2 SIDES)
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
(DCB6) DFN 0405
3
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
1.35 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
699412f
22
LTC6994-1/LTC6994-2
PACKAGE DESCRIPTION
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
2.90 BSC
(NOTE 4)
0.62
MAX
0.95
REF
1.22 REF
1.4 MIN
1.50 – 1.75
2.80 BSC
3.85 MAX 2.62 REF
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302 REV B
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
699412f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC6994-1/LTC6994-2
TYPICAL APPLICATION
Press-and-Hold (0.3s to 4s) Delay Timer
+
V
+
V
ACTIVE HIGH
ACTIVE LOW
100k
OUT
OUT
IN
OUT
LTC6994-1
IN
OUT
LTC6994-1
100k
+
+
V
V
+
+
GND
SET
V
GND
SET
V
0.1µF
0.1µF
681k
1M
DIV
DIV
R
R
SET
576k
SET
681k
1M
576k
t
≅ 3s
t
≅ 3s
DELAY
DELAY
BOUNCE
BOUNCE
IN
IN
HOLD
HOLD
OUT
OUT
DELAY
DELAY
699412 TA07
R
SET
(kΩ) = 190 • t
(SECONDS)
DELAY
RELATED PARTS
PART NUMBER
LTC1799
DESCRIPTION
COMMENTS
Wide Frequency Range
Low Power, Wide Frequency Range
Micropower, I = 35µA at 400kHz
1MHz to 33MHz ThinSOT Silicon Oscillator
1MHz to 20MHz ThinSOT Silicon Oscillator
LTC6900
LTC6906/LTC6907
LTC6930
10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillator
Fixed Frequency Oscillator, 32.768kHz to 8.192MHz
TimerBlox: Voltage-Controlled Silicon Oscillator
TimerBlox: Resettable Low Frequency Oscillator
SUPPLY
0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
Fixed-Frequency or Voltage-Controlled Operation
Clock Periods up to 9.5 hours
LTC6990
LTC6991
LTC6992
TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM)
TimerBlox: Monostable Pulse Generator (One-Shot)
Simple PWM with Wide Frequency Range
Resistor-Programmable Pulse Width of 1µs to 34s
LTC6993
699412f
LT 1010 • PRINTED IN USA
24 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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