LTM2220-AA [Linear]
12-Bit, 170Msps ADC; 12位，170Msps ADC
| 型号： | LTM2220-AA |
| 厂家： | 
Linear |
| 描述： | 12-Bit, 170Msps ADC |
| 文件： | 总12页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM2220-AA
12-Bit, 170Msps ADC
FEATURES
DESCRIPTION
The LTM®2220-AA is a 170Msps sampling 12-bit A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTM2220-AA is perfect for
demanding communications applications with AC per-
formance that includes 66.2dB SNR and 84dB spurious
free dynamic range.
■
Pin Compatible with the AD9430
■
Sample Rate: 170Msps
■
66.2dB SNR, 84dB SFDR
■
No Missing Codes
Single 3.3V supply
■
■
Power Dissipation: 1050mW
■
LVDS Digital Outputs
DC specs include 0.ꢀLSB ꢁNL ꢂtypꢃ, 0.ꢄLSB DNL ꢂtypꢃ
and no missing codes over temperature.
■
1.ꢀꢄ6V ꢁnput Range
PP
■
■
■
■
■
Clock Duty Cycle Stabilizer
The CLK+ and CLK- inputs may be driven differentially or
single ended with a sine wave, PECL, TTL or CMOS inputs.
A clock duty cycle stabilizer allows high performance at
full speed for a wide range of clock duty cycles.
Out-of-Range ꢁndicator
Data Ready Output Clock
ꢁntegrated Bypass Capacitors
100-Pin SiPLGA Package
TheLTM2220-AAispincompatiblewiththeAD94ꢄ0when
used with LVDS outputs, 2’s complement output format
APPLICATIONS
and the 1.ꢀꢄ6V input range.
PP
■
Wireless and Wired Broadband Communication
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
■
Spectral Analysis
TYPICAL APPLICATION
3.3V
AV
DD
3.3V
DRVDD
REFERENCE
D11
+
12-BIT
PIPELINED
ADC CORE
•
•
•
CORRECTION
LOGIC
LVDS
OUTPUTS
ANALOG
INPUT
OUTPUT
DRIVERS
INPUT
S/H
–
D0
DRGND
CLOCK/DUTY
CYCLE
CONTROL
2220 TA01
AGND
CLOCK
INPUT
2220aaf
1
LTM2220-AA
ABSOLUTE MAXIMUM RATINGS
AVDD = DRVDD (Notes 1, 2)
Supply Voltage ꢂAVDD, DRVDDꢃ.................................4V Power Dissipation............................................ 1ꢀ00mW
Analog ꢁnput Voltage ꢂNote ꢄꢃ.... -0.ꢄV to ꢂAVDD + 0.ꢄVꢃ Operating Temperature Range ..................-40°C to 8ꢀ°C
Digital ꢁnput Voltage................... -0.ꢄV to ꢂAVDD + 0.ꢄVꢃ Storage Temperature Range....................-6ꢀ°C to 12ꢀ°C
Digital Output Voltage ............. -0.ꢄV to ꢂDRVDD + 0.ꢄVꢃ
PACKAGE/ORDER INFORMATION
TOP VIEW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
NC
NC
1
2
3
4
5
6
7
8
9
DRVDD
DRGND
NC
73 D8+
72
71
70
69
AGND
NC
D8–
D7+
D7–
D6+
NC
NC
AVDD
AGND
68 D6–
67 DRGND
AGND
AGND
66
NC 10
NC 11
D5+
65 D5–
64
63
AGND 12
AGND 13
DCO+
DCO–
AVDD
AVDD
62 DRVDD
61 DRGND
60 D4+
14
15
AGND 16
AGND 17
AVDD 18
AVDD 19
AGND
AGND
59 D4–
58 D3+
57 D3–
AGND
+
56 D2+
20
21
22
V
D2–
55
IN
–
V
54 DRVDD
53 DRGND
52 D1+
IN
AGND 23
AVDD 24
AGND 25
51 D1–
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SiPLGA PACKAGE
100-LEAD (16mm × 16mm)
T
= 12ꢀ°C, θ = 20°C/W
JA
JMAX
EXPOSED PADS ARE AGND
ORDER PART NUMBER
LTM2220ꢁV-AA#PBF
LGA PART MARKꢁNG
LTM2220V-AA
Consult LTC Marketing for parts specified with wider operating temperature ranges.
2220aaf
2
LTM2220-AA
CONVERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
12
TYP
MAX
UNITS
Bits
●
●
●
Resolution ꢂNo Missing Codesꢃ
ꢁntegral Linearity Error
Differential Linearity Error
Offset Error
ꢂNote ꢀꢃ
–1.ꢀ
–1
0.ꢀ
0.ꢄ
ꢄ
1.ꢀ
1
LSB
LSB
mV
ꢂNote 6ꢃ
–ꢄꢀ
ꢄꢀ
Gain Error
0.ꢀ
%FS
ANALOG INPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
+
–
●
●
V
V
Differential ꢁnput Range
Common Mode ꢁnput Range
Lower –ꢄdB Frequency
Upper –ꢄdB Frequency
Sample and Hold Jitter
V
ꢁN
– V
ꢁN
1.ꢀꢄ6
ꢁN
+
–
ꢂV + V ꢃ/2
0
ꢄ.6
V
ꢁN, CM
ꢁN
ꢁN
f
f
t
1.6
19ꢀ
0.2
kHz
MHz
L
R = 7ꢀΩ
S
H
ps
JꢁTTER
RMS
DYNAMIC ACCURACY The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
10MHz ꢁnput
70MHz ꢁnput
10MHz ꢁnput
70MHz ꢁnput
10MHz ꢁnput
70MHz ꢁnput
10MHz ꢁnput
70MHz ꢁnput
MIN
6ꢄ.ꢀ
6ꢄ.2
70
TYP
66.2
66.1
66.1
6ꢀ.9
84
MAX
UNITS
dB
SNR
Signal-to-Noise Ratio
●
●
●
●
dB
SꢁNAD
SFDR
SFDR
ꢁMD
Signal to Noise Plus Distortion Ratio
dB
dB
Spurious Free Dynamic Range: 2nd or
ꢄrd Harmonic
dB
84
dB
Spurious Free Dynamic Range: 4th
Harmonic or Higher
90
dB
78
90
dB
ꢁntermodulation Distortion
f
ꢁN1
= 1ꢄ8MHz, f = 140MHz
81
dB
ꢁN2
2220aaf
3
LTM2220-AA
DIGITAL INPUTS AND OUTPUTSThe ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK ꢁNPUTS ꢂCLK+, CLK–ꢃ
●
●
V
V
Differential ꢁnput Voltage
0.2
1.1
V
ꢁD
Common Mode ꢁnput Voltage
ꢁnternally Set
Externally Set
1.6
1.6
V
V
ꢁCM
2.ꢀ
R
ꢁnput Resistance
ꢁnput Capacitance
6
ꢄ
kΩ
ꢁN
C
ꢂNote 7ꢃ
pF
ꢁN
DꢁGꢁTAL LOGꢁC OUTPUTS
●
●
V
OD
V
OS
Differential Output Voltage
100Ω Load
247
ꢄꢀ0
4ꢀ4
mV
V
Output Common Mode Voltage
1.12ꢀ
1.2ꢀ0
1.ꢄ7ꢀ
POWER REQUIREMENTS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
AVDD
PARAMETER
CONDITIONS
ꢂNote 8ꢃ
MIN
ꢄ.1
TYP
ꢄ.ꢄ
MAX
ꢄ.ꢀ
UNITS
V
●
●
●
●
●
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current
Digital Supply Current
Power Dissipation
DRVDD
ꢁAVDD
ꢁDVDD
PDꢁSS
ꢂNote 8ꢃ
ꢄ.0
ꢄ.ꢄ
ꢄ.6
V
264
ꢀꢀ
288
70
mA
mA
mW
10ꢀ0
1182
TIMING CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
1
TYP
MAX
170
ꢀ00
ꢀ00
UNITS
MHz
ns
●
●
●
f
t
t
t
t
t
Sampling Frequency
CLK Low Time
S
ꢂNote 7ꢃ
ꢂNote 7ꢃ
2
2.94
2.94
0
L
CLK High Time
2
ns
H
AP
D
C
Sample-and-Hold Aperture Delay
CLK to DATA Delay
CLK to DCO Delay
DATA to DCO Skew
Rise Time
ns
●
●
●
ꢂNote 7ꢃ
ꢂNote 7ꢃ
1.ꢀ
1.ꢀ
ꢄ
4.ꢄ
4.ꢄ
0.6
ns
ꢄ
ns
ꢂt – t ꢃ, ꢂNote 7ꢃ
–0.6
0
ns
C
D
0.ꢀ
0.ꢀ
ꢀ
ns
Fall Time
ns
Pipeline Latency
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: AVDD = DRVDD = ꢄ.ꢄV, f
= 2Vpp sine wave, differential analog inputs, unless otherwise noted.
Note 5: ꢁntegral nonlinearity is defined as the deviation of a code from a
“best fit straight line” fit to the transfer curve. The deviation is measured
from the center of the quantization band.
=170MHz, differential CLK+/CLK-
SAMPLE
Note 2: All voltage values are with respect to ground with AGND and
DRGND wired together ꢂunless otherwise notedꢃ.
Note 6: Offset error is the offset voltage measured from -0.ꢀ LSB when the
Note 3: When these pin voltages are taken below GND or above V , they
output code flickers between 0000 0000 0000 and 1111 1111 1111.
DD
will be clamped by internal diodes. This product can handle input currents
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
of greater than 100mA below GND or above V without latchup.
DD
2220aaf
4
LTM2220-AA
TYPICAL PERFORMANCE CHARACTERISTICS
8192 Point FFT, fIN = 5MHz, –1dB,
170Msps
8192 Point FFT, fIN = 30MHz,
–1dB, 170Msps
8192 Point FFT, fIN = 70MHz,
–1dB, 170Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
20 30 40 50 60 70 80
10
0
20 30 40 50
FREQUENCY (MHz)
80
0
20 30 40 50
FREQUENCY (MHz)
80
10
60 70
10
60 70
FREQUENCY (MHz)
2220 G01
2220 G02
2220 G03
8192 Point FFT, fIN = 140MHz,
–1dB, 170Msps
INL Error
DNL Error
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
– 0.2
– 0.4
– 0.6
– 0.8
– 1.0
0
20 30 40 50 60 70 80
10
0
1024
2048
3072
4096
0
1024
2048
3072
4096
FREQUENCY (MHz)
OUTPUT CODE
OUTPUT CODE
2220 G04
2220 G05
2220 G06
2220aaf
5
LTM2220-AA
PIN FUNCTIONS
NC (Pins 1, 2, 3, 5, 6, 7, 10, 11, 33, 42, 43, 44, 45, 46):
Pin is not connected internally.
D3+ (Pin 58): Dꢄ True Output Bit.
D4- (Pin 59): D4 Complement Output Bit.
D4+ (Pin 60): D4 True Output Bit.
AGND (Pins 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30,
31, 32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100):
Analog Ground.
DCO- (Pin 63): Data Clock Output Complement.
DCO+ (Pin 64): Data Clock Output True.
D5- (Pin 65): Dꢀ Complement Output Bit.
D5+ (Pin 66): Dꢀ True Output Bit.
AVDD (Pins 8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40,
88, 89, 90, 94, 95, 98, 99): ꢄ.ꢄV Analog Supply.
+
V
V
(Pin 21): Positive Analog ꢁnput.
(Pin 22): Negative Analog ꢁnput.
IN
IN
-
D6- (Pin 68): D6 Complement Output Bit.
D6+ (Pin 69): D6 True Output Bit.
CLK+ (Pin 36): Clock ꢁnput. The input sample starts on
the positive edge.
D7- (Pin 70): D7 Complement Output Bit.
D7+ (Pin 71): D7 True Output Bit.
CLK-(Pin37):ClockComplementꢁnput.Conversionstarts
on the negative edge. Bypass to ground with a 0.1µF
ceramic for a single-ended clock.
D8- (Pin 72): D8 Complement Output Bit.
D8+ (Pin 73): D8 True Output Bit.
DRVDD (Pins 47, 54, 62, 75, 83): ꢄ.ꢄV Digital Output
Driver Supply.
D9- (Pin 76): D9 Complement Output Bit.
D9+ (Pin 77): D9 True Output Bit.
DRGND (Pins 48, 53, 61, 67, 74, 82): Digital Output
Driver Ground.
D10- (Pin 78): D10 Complement Output Bit.
D10+ (Pin 79): D10 True Output Bit.
D11- (Pin 80): D11 Complement Output Bit ꢂMSBꢃ.
D11+ (Pin 81): D11 True Output Bit ꢂMSBꢃ.
OR- (Pin 84): Overrange Output Complement.
OR+ (Pin 85): Overrange Output True.
D0- (Pin 49): D0 Complement Output Bit ꢂLSBꢃ.
D0+ (Pin 50): D0 True Output Bit ꢂLSBꢃ.
D1- (Pin 51): D1 Complement Output Bit.
D1+ (Pin 52): D1 True Output Bit.
D2- (Pin 55): D2 Complement Output Bit.
D2+ (Pin 56): D2 True Output Bit.
GND (Exposed Pads): The exposed pads on the bottom of
the package need to be soldered to Analog Ground.
D3- (Pin 57): Dꢄ Complement Output Bit.
TIMING DIAGRAM
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
CLK–
CLK+
t
D
N – 5
N – 4
N – 3
N – 2
N – 1
D0-D11, OR
t
C
–
DCO
2220 TD01
+
DCO
2220aaf
6
LTM2220-AA
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
Lower and Upper –3dB Frequencies
The input frequencies at which the amplitude of the re-
constructed fundamental is reduced by ꢄdB for a full scale
input signal. Note that the analog input has a bandpass
response.
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/ꢂN + Dꢃ] is
the ratio between the RMS amplitude of the fundamen-
tal input frequency and the RMS amplitude of all other
frequency components at the ADC output. The output is
band limited to frequencies above DC to below half the
sampling frequency.
Aperture Delay Time
ThetimefromwhenarisingCLK+equalstheCLK–voltage
to the instant that the input signal is held by the sample
and hold circuit.
Signal-to-Noise Ratio
The signal-to-noise ratio ꢂSNRꢃ is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
Intermodulation Distortion
SNR
= –20log ꢂ2π • f • t
ꢃ
JꢁTTER
ꢁN JꢁTTER
ꢁf the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion ꢂꢁMDꢃ in addition to
Total Harmonic Distortion ꢂTHDꢃ. ꢁMD is the change in
one sinusoidal input caused by the presence of another
sinusoidal input at a different frequency.
CONVERTER OPERATION
TheLTM2220-AAisaCMOSpipelinedmultistepconverter.
The converter has five pipelined ADC stages; a sampled
analog input will result in a digitized value five cycles later
ꢂsee the Timing Diagram sectionꢃ. For optimal AC perfor-
mance the analog inputs should be driven differentially.
For cost sensitive applications, the analog inputs can be
driven single-ended with slightly worse harmonic distor-
tion. The clock input is differential for improved common
mode noise immunity.
ꢁf two pure sine waves of frequencies fa and fb are ap-
plied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa nfb, where m and n = 0,
1, 2, ꢄ, etc. The ꢄrd order intermodulation products are
2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodula-
tion distortion is defined as the ratio of the RMS value of
either input tone to the RMS value of the largest ꢄrd order
intermodulation product.
TheLTM2220-AAispincompatiblewiththeAD94ꢄ0when
used with LVDS outputs, 2’s complement output format
and the 1.ꢀꢄ6V input range.
PP
The LTM2220-AA package contains power supply bypass
capacitors, which makes the part easy to use since it is
insensitive to the PC board layout.
Spurious Free Dynamic Range (SFDR)
Spuriousfreedynamicrangeisthepeakharmonicorspuri-
ousnoisethatisthelargestspectralcomponentexcluding
theinputsignalandDC.Thisvalueisexpressedindecibels
relative to the RMS value of a full scale input signal.
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7
LTM2220-AA
APPLICATIONS INFORMATION
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Input Drive Impedance
As with all high performance, high speed ADCs, the dy-
namic performance of the LTM2220-AA can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can influence SFDR.
Sample/Hold Operation
Figure 1 shows an equivalent circuit for the LTM2220-AA
CMOSdifferentialsample-and-hold.Theanaloginputsare
AC coupled to the sample and hold circuit through 0.1µF
capacitors and 1k bias resistors. The 2ꢀΩ resistor and
0.ꢀpF capacitor serve two purposes: isolating the drive
circuitry from the sample and hold charging glitches and
limiting the wideband noise at the converter input.
The source impedance should be matched for the dif-
ferential inputs. Poor matching will result in higher even
order harmonics, especially the second.
Input Drive Circuits
Single-Ended Input
Figure 2 shows the LTM2220-AA being driven by an RF
transformerwithacentertappedsecondary.Thesecondary
center tap is grounded as shown, but it can also be con-
nectedtoanyDCbiasvoltagefrom0Vtoꢄ.6V. Terminating
onthetransformersecondaryisdesirable,asthisprovides
a common mode path for charging glitches caused by the
sample and hold.
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and ꢁNL will degrade, but the SNR and
DNL will remain unchanged.
Common Mode Bias
Foroptimalperformancetheanaloginputsshouldbedriven
differentially. Each input should swing 0.ꢄ84V around a
common mode voltage of between 0V and ꢄ.6V.
Driving the Clock Inputs
ThenoiseperformanceoftheLTM2220-AAcandependon
the encode signal quality as much as on the analog input.
The CLK+/CLK– inputs are intended to be driven differen-
tially, primarily for noise immunity from common mode
noise sources. Each input is biased through a 6k resistor
to a 1.6V bias. The bias resistors set the DC operating
point for transformer coupled drive circuits and can set
the logic threshold for single-ended drive circuits.
LTM2220-AA
V
DD
C
SAMPLE
1.6pF
0.1µF
25Ω
15Ω
15Ω
+
–
V
V
IN
IN
V
DD
0.5pF
C
SAMPLE
1.6pF
0.1µF
25Ω
1k
1k
0.1µF T1
1:1
ANALOG
INPUT
+
V
DD
V
IN
25Ω
25Ω
V
REF
LTM2220-AA
–
1.6V
V
IN
6k
T1 = M/A-COM ETC1-1T OR EQUIVALENT
2220 F02
CLK+
CLK–
Figure 2. Single-Ended to Differential
Conversion Using a Transformer
6k
1.6V
2220 F01
Figure 1. Equivalent Input Circuit
2220aaf
8
LTM2220-AA
APPLICATIONS INFORMATION
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
Maximum and Minimum Encode Rates
ThemaximumencoderatefortheLTM2220-AAis170Msps.
For the ADC to operate properly, the encode signal should
have a ꢀ0% ꢂ 20%ꢃ duty cycle. Each half cycle must have
at least 2ns for the ADC internal circuitry to have enough
settling time for proper operation.
ꢁn applications where jitter is critical ꢂhigh input frequen-
ciesꢃ take the following into consideration:
1. Differential drive should be used.
ꢁf the clock is turned off for a long period of time, the duty
cyclestabilizercircuitwillrequireonehundredclockcycles
for the PLL to lock onto the input clock.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the ampli-
tude.
The lower limit of the LTM2220-AA sample rate is de-
termined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
dischargethecapacitors.Thespecifiedminimumoperating
frequency for the LTM2220-AA is 1Msps.
ꢄ. ꢁf the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encodeinputssothatanycouplednoisewillappearatboth
inputs as common mode noise. The clock inputs have a
common mode range of 1.1V to 2.ꢀV. Each input may be
driven from ground to VDD for single-ended drive.
CLK+
V
= 1.6V
THRESHOLD
LTM2220-AA
1.6V
CLK–
V
LTM2220-AA
DD
0.1µF
TO INTERNAL
ADC CIRCUITS
2220 F04
Figure 4. Single-Ended CLK Drive,
Not Recommended for Low Jitter
1.6V BIAS
V
V
DD
DD
6k
3.3V
CLK+
CLK–
0.1µF
50Ω
3.3V
MC100LVELT22
D0
1:4
CLOCK
INPUT
130Ω
Q0
130Ω
1.6V BIAS
6k
CLK+
LTM2220-AA
CLK–
Q0
83Ω
83Ω
2220 F05
2220 F03
Figure 3. Transformer Driven CLK+/CLK–
Figure 5. CLK Drive Using a CMOS to PECL Translator
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9
LTM2220-AA
APPLICATIONS INFORMATION
DIGITAL OUTPUTS
Output Clock
The ADC has a delayed version of the CLK+ input avail-
able as a digital output, DCO. The DCO pin can be used to
synchronize the converter data to the digital system. This
is necessary when using a sinusoidal clock. Data will be
updated as DCO+/DCO– rises and can be latched on the
falling edge of DCO+/DCO–.
Table 1. Output Codes vs Input Voltage
+
–
VIN – VIN
OR
D11 – D0
>+0.768000V
+0.768000V
+0.76762ꢀV
1
0
0
0111 1111 1111
0111 1111 1111
0111 1111 1110
+0.000ꢄ7ꢀV
0.000000V
–0.000ꢄ7ꢀV
–0.0007ꢀ0V
0
0
0
0
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
Output Driver Power
–0.76762ꢀV
–0.768000V
<–0.768000V
0
0
1
1000 0000 0001
1000 0000 0000
1000 0000 0000
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. DRVDD
should be connected to a ꢄ.ꢄV supply and DRGND should
be connected to GND.
Digital Output Buffers
Figure 6 shows an equivalent circuit for a differential
output pair in the LVDS output mode. A ꢄ.ꢀmA current is
GROUNDING AND BYPASSING
+
–
The LTM2220-AA requires a printed circuit board with a
clean unbroken ground plane. A multilayer board with an
internal ground plane is recommended. Layout for the
printed circuit board should ensure that digital and analog
signallinesareseparatedasmuchaspossible.ꢁnparticular,
careshouldbetakennottorunanydigitalsignalalongside
an analog signal or underneath the ADC.
steered from OUT to OUT or vice versa which creates a
ꢄꢀ0mV differential voltage across the 100Ω termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.2ꢀV. For proper
operation each LVDS output pair needs an external 100Ω
termination resistor, even if the signal is not used ꢂsuch
as OR+/OR– or DCO+/DCO–ꢃ. To minimize noise the PC
board traces for each LVDS output pair should be routed
close together. To minimize clock skew all LVDS PC board
traces should have about the same length.
The LTM2220-AA differential inputs should run parallel
and close to each other. The input traces should be as
shortaspossibletominimizecapacitanceandtominimize
noise pickup.
Data Format
The LTM2220-AA package contains power supply bypass
capacitors on AVDD and DRVDD. External bypass ca-
pacitors can be added for additional low-frequency noise
rejection, but they are not required if the power supplies
come from quiet linear voltage regulators.
TheLTM2220-AAparalleldigitaloutputhas2’scomplement
format. Table1showstherelationshipbetweentheanalog
input voltage, the digital data bits and the overrange bit.
LTM2220-AA
DRVDD
HEAT TRANSFER
D
D
D
Most of the heat generated by the LTM2220-AA is trans-
ferred from the die through the bottom-side exposed
pads and package leads onto the printed circuit board.
For good electrical and thermal performance, the exposed
pads should be soldered to a large grounded pad on the
PC board. ꢁt is critical that all ground pins are connected
to a ground plane of sufficient area.
+
OUT
–
+
10k
10k
100Ω
1.25V
LVDS
RECEIVER
–
OUT
D
3.5mA
DRGND
2220 F06
Figure 6. Digital Output
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10
LTM2220-AA
PACKAGE DESCRIPTION
SiPLGA Package
100-Lead (16mm × 16mm)
ꢂReference LTC DWG # 0ꢀ-08-1802 Rev Øꢃ
aaa
Z
15.90 – 16.10
X
Y
(2X)
26
50
25
6.000
PAD 1
CORNER
4
51
5.500
5.000
4.500
4.000
3.500
3.1245
1.045
3.1245
1.045
3.000
2.500
2.000
1.500
1.000
0.500
15.9 – 16.1
0.000
0.500
1.000
1.500
2.000
2.500
3.000
3.500
4.000
4.500
5.000
5.500
6.000
1.045
1.045
3.1245
3.1245
75
1
aaa
Z
(2X)
100
76
DETAILED PAD LAYOUT
TOP VIEW
11.90 – 12.10
1.93 – 2.13
eee M
X
Y
0.315 – 0.385
0.218 – 0.278 (b)
26
50
ROWS
AF
0.05 – 0.15
25
51
AE
AC
AA
W
U
1.120 – 1.180
1.313 – 1.383
AD
AB
Y
PAD
V
0.5
BASIC
DETAIL B
T
S
R
N
L
11.90 – 12.10
P
M
K
J
MOLD
CAP
SUBSTRATE
H
G
E
F
D
0.33 – 0.43
C
1.60 – 1.70
B
75
DETAIL B
1
5
A
3
100
76
DETAIL A
1
3
5
7
9
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
DETAIL A
COLUMNS
2
4
6
8
BOTTOM VIEW
NOTES:
SYMBOL TOLERANCE
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
aaa
bbb
eee
0.10
0.10
0.03
2. ALL DIMENSIONS ARE IN MILLIMETERS
3
4
LAND DESIGNATION PER JESD MO-222, SPP-010
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD
OR MARKED FEATURE
10_10_06
5
PRIMARY DATUM -Z- IS SEATING PLANE
6. DIMENSION (b) IS MEASURED AT THE MAXIMUM LAND
WIDTH, PARALLEL TO PRIMARY DATUM -Z-
7. TOTAL NUMBER OF PADS: 104 TOTAL (100 PERIPHERAL + 4 COMMON CENTER)
2220aaf
ꢁnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTM2220-AA
RELATED PARTS
PART NUMBER
LTC2220
DESCRIPTION
COMMENTS
12-Bit, 170Msps, ꢄ.ꢄV ADC, LVDS Outputs
12-Bit, 2ꢀ0Msps, 2.ꢀV ADC, LVDS Outputs
High Speed Differential Op Amp
890mW, 67.7dB SNR, 84dB SFDR, 64-Pin QFN Package
740mW, 6ꢀ.4dB SNR, 84dB SFDR, 64-Pin QFN Package
800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LTC2242-12
LT199ꢄ-2
2220aaf
LT 0107 • PRINTED IN USA
LinearTechnology Corporation
16ꢄ0 McCarthy Blvd., Milpitas, CA 9ꢀ0ꢄꢀ-7417
12
●
●
© LINEAR TECHNOLOGY CORPORATION 2007
ꢂ408ꢃ 4ꢄ2-1900 FAX: ꢂ408ꢃ 4ꢄ4-0ꢀ07 www.linear.com
相关型号：
LTM2220IV-AA#PBF
IC 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PBCC100, 16 X 16 MM, MO-222, SIPLGA-100, Analog to Digital Converter
Linear
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