LTM8055IY [Linear]
LTM8055 - 36VIN, 8.5A Buck-Boost µModule (Power Module) Regulator; Package: BGA; Pins: 121; Temperature Range: -40°C to 85°C;
| 型号： | LTM8055IY |
| 厂家： | 
Linear |
| 描述： | LTM8055 - 36VIN, 8.5A Buck-Boost µModule (Power Module) Regulator; Package: BGA; Pins: 121; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总26页 (文件大小：1560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM8055/LTM8055-1
36V , 8.5A Buck-Boost
IN
µModule Regulator
FEATURES
DESCRIPTION
The LTM®8055/LTM8055-1 is a 36V , buck-boost
n
Complete Buck-Boost Switch Mode Power Supply
OUT
Wide Input Voltage Range: 5V to 36V
12V/3A Output from 6V
IN
V
Equal, Greater, Less Than V
µModule® (micromodule) regulator. Included in the pack-
age are the switching controller, power switches, inductor
and support components. A resistor to set the switching
frequency, a resistor divider to set the output voltage,
and input and output capacitors are all that are needed
to complete the design. Other features such as input and
output average current regulation may be implemented
with just a few components. The LTM8055/LTM8055-1
operates over an input voltage range of 5V to 36V, and
can regulate output voltages between 1.2V and 36V. The
SYNCinputandCLKOUToutputalloweasysynchronization.
n
IN
n
n
n
n
n
n
n
n
n
n
n
n
n
IN
IN
12V/6A Output from 12V
12V/8.5A Output from 24V
IN
Up to 97.5% Efficient
Adjustable Input and Output Average Current Limits
Input and Output Current Monitors
Parallelable for Increased Output Current
Wide Output Voltage Range: 1.2V to 36V
Selectable Switching Frequency: 100kHz to 800kHz
Synchronization from 200kHz to 700kHz
External Compensation (LTM8055-1)
The LTM8055/LTM8055-1 is housed in a compact over-
molded ball grid array (BGA) package suitable for auto-
mated assembly by standard surface mount equipment.
The LTM8055/LTM8055-1 is RoHS compliant.
15mm × 15mm × 4.92mm BGA Package
Buck-Boost Selection Table
APPLICATIONS
LTM8054
LTM8055/LTM8055-1
LTM8056
n
High Power Battery-Operated Devices
V
V
V
(Operation)
Abs Max
36
40
40
5.4
36
40
40
8.5
58
60
60
5.5
IN
n
Industrial Control
IN
n
Solar Powered Voltage Regulator
Abs Max
OUT
n
Solar Powered Battery Charging
I
(Peak)
OUT
24V , 12V
All registered trademarks and trademarks are the property of their respective owners.
IN
OUT
Package
15 × 11.25mm ×
3.42mm BGA
15 × 15mm × 4.92mm BGA
Pin and Function Compatible
TYPICAL APPLICATION
Maximum Output Current and Efficiency vs VIN
12VOUT from 5VIN to 36VIN Buck-Boost Regulator
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Rev C
1
Document Feedback
For more information www.analog.com
LTM8055/LTM8055-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
V , SV , V , RUN, I , I Voltage.....................40V
IN OUT
ꢈꢆꢑ ꢅꢉꢏꢩ
IN
IN OUT
ꢀꢁꢂꢃ ꢚ
FB, SYNC, CTL, MODE Voltage ...................................6V
ꢌꢅ
ꢅ
ꢉꢂ
ꢉꢂ
I
, I Voltage .............................................6V
INMON OUTMON
ꢒꢒ
ꢒꢓ
ꢔ
LL Voltage.................................................................15V
Maximum Junction Temperature (Notes 2, 3)....... 125°C
Storage Temperature.............................. –55°C to 125°C
Peak Solder Reflow Body Temperature ................. 245°C
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ORDER INFORMATION
PART NUMBER
TERMINAL FINISH
PART MARKING*
PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(SEE NOTE 2)
DEVICE
FINISH CODE
LTM8055EY#PBF
LTM8055IY#PBF
LTM8055IY
SAC305 (RoHS)
SAC305 (RoHS)
SnPb(63/37)
LTM8055Y
LTM8055Y
LTM8055Y
LTM8055Y
LTM8055Y
LTM8055Y-1
LTM8055Y-1
e1
e1
e0
e1
e0
e1
e1
BGA
BGA
BGA
BGA
BGA
BGA
BGA
3
3
3
3
3
3
3
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
LTM8055MPY#PBF
LTM8055MPY
SAC305 (RoHS)
SnPb(63/37)
LTM8055EY-1#PBF
LTM8055IY-1#PBF
SAC305 (RoHS)
SAC305 (RoHS)
• Device temperature grade is indicated by a label on the shipping
container.
This product is not recommended for second side reflow.
This product is moisture sensitive. For more information, go to
Recommended BGA PCB Assembly and Manufacturing Procedures.
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• BGA Package and Tray Drawings
Rev C
2
For more information www.analog.com
LTM8055/LTM8055-1
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. RUN = 1.5V unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
Minimum Input Voltage
Output DC Voltage
V
= SV
5.0
V
IN
IN
FB = V
R
Through 100k
1.2
36
V
V
OUT
= 100k/3.40k
FB
Output DC Current
V
V
= 6V, V
= 12V
OUT
OUT
3
8.5
A
A
IN
IN
= 24V, V
= 12V
Quiescent Current Into V (Tied to SV )
RUN = 0.3V (Disabled)
No Load, MODE = 0.3V (DCM)
No Load, MODE = 1.5V (FCM)
0.1
8
45
1
µA
mA
mA
IN
IN
30
100
Output Voltage Line Regulation
Output Voltage Load Regulation
Output RMS Voltage Ripple
Switching Frequency
5V < V < 36V, I
= 1A
OUT
0.5
0.5
25
%
%
IN
V
V
= 12V, 0.1A < I
< 6A
IN
IN
OUT
= 12V, I
= 3A
mV
OUT
R = 453k
100
800
kHz
kHz
T
R = 24.9k
T
Voltage at FB Pin
1.188
1.176
1.2
25
1.212
1.220
V
V
l
l
RUN Falling Threshold
RUN Hysteresis
LTM8055/LTM8055-1 Stops Switching
LTM8055/LTM8055-1 Starts Switching
LTM8055/LTM8055-1 Disabled
1.15
1.25
V
mV
V
RUN Low Threshold
RUN Pin Current
0.3
RUN = 1V
RUN = 1.6V
2
3
5
100
µA
nA
I
Bias Current
90
µA
mV
µA
IN
l
l
Input Current Sense Threshold (I -V )
44
56
IN IN
I
Bias Current
20
OUT
Output Current Sense Threshold (V -I
)
V
= Open
CTL
54.5
53
61.5
63
mV
mV
OUT OUT
I
I
Voltage
LTM8055/LTM8055-1 in Input Current Limit
LTM8055/LTM8055-1 in Output Current Limit
0.96
1.14
1.04
1.26
V
V
INMON
Voltage
OUTMON
CTL Input Bias Current
SS Pin Current
V
V
= 0V
22
35
µA
µA
V
CTL
= 0V
SS
CLKOUT Output High
CLKOUT Output Low
10k to GND
10k to 5V
4
0.7
0.3
V
SYNC Input Low Threshold
SYNC Input High Threshold
SYNC Bias Current
V
1.5
V
SYNC = 1V
11
µA
V
MODE Input Low Threshold
MODE Input High Threshold
0.3
1.5
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
the full –55°C to 125°C internal operating temperature range. Note that
the maximum internal temperature is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
resistance and other environmental factors.
Note 2: The LTM8055E/LTM8055E-1 is guaranteed to meet performance
specifications from 0°C to 125°C internal. Specifications over the full
–40°C to 125°C internal operating temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTM8055I/LTM8055I-1 is guaranteed to meet specifications over
the full –40°C to 125°C internal operating temperature range. The
LTM8055MP/LTM8055MP-1 is guaranteed to meet specifications over
Note 3: The LTM8055/LTM8055-1 contains overtemperature protection
that is intended to protect the device during momentary overload
conditions. The internal temperature exceeds the maximum operating
junction temperature when the overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Rev C
3
For more information www.analog.com
LTM8055/LTM8055-1
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Current
Efficiency vs Output Current
(5VOUT
Efficiency vs Output Current
(8VOUT
(3.3VOUT
)
)
)
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Efficiency vs Output Current
(12VOUT
Efficiency vs Output Current
(18VOUT
Efficiency vs Output Current
(24VOUT
)
)
)
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ꢑꢎꢓꢓ ꢔꢎꢏ
Efficiency vs Output Current
Input Current vs Output Current
Input Current vs Output Current
(5VOUT
(36VOUT
)
(3.3VOUT
)
)
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ꢀꢁꢂꢃꢁꢂ CꢁRRꢄꢅꢂ ꢆꢇꢈ
ꢀꢁꢂꢃꢁꢂ CꢁRRꢄꢅꢂ ꢆꢇꢈ
ꢏꢎꢒꢒ ꢕꢎꢐ
ꢒꢑꢋꢋ ꢓꢑꢒ
ꢌꢋꢐꢐ ꢑꢋꢒ
Rev C
4
For more information www.analog.com
LTM8055/LTM8055-1
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Input Current vs Output Current
Input Current vs Output Current
(12VOUT
Input Current vs Output Current
(18VOUT
(8VOUT
)
)
)
ꢊꢋ
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ꢊꢋ
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ꢀꢁꢂꢃꢁꢂ CꢁRRꢄꢅꢂ ꢆꢇꢈ
ꢀꢁꢂꢃꢁꢂ CꢁRRꢄꢅꢂ ꢆꢇꢈ
ꢌꢋꢐꢐ ꢑꢊꢊ
ꢌꢋꢐꢐ ꢑꢊꢏ
ꢌꢋꢐꢐ ꢑꢊꢋ
Input Current vs Output Current
(24VOUT
Input Current vs Output Current
)
(36VOUT
)
Maximum Output Current vs VIN
ꢊꢋ
ꢊ
ꢋ
ꢌ
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ꢍ
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ꢏ
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ꢅꢆꢇ
ꢒꢑꢕ
ꢑꢍꢕ
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ꢉꢅ
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ꢅꢆꢇ
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ꢀꢁꢂꢃꢁꢂ CꢁRRꢄꢅꢂ ꢆꢇꢈ
ꢀ
ꢁꢂ
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ꢍꢌꢐꢐ ꢑꢋꢐ
Temperature Rise vs Output
Temperature Rise vs Output
Current (5VOUT)
Maximum Output Current vs VIN
Current (3.3VOUT
)
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Rev C
5
For more information www.analog.com
LTM8055/LTM8055-1
TA = 25°C, unless otherwise noted.
TYPICAL PERFORMANCE CHARACTERISTICS
Temperature Rise vs Output
Current (8VOUT
Temperature Rise vs Output
Current (12VOUT
Temperature Rise vs Output
Current (18VOUT
)
)
)
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ꢏꢎꢓꢓ ꢔꢒꢍ
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Temperature Rise vs Output
Current (24VOUT
Temperature Rise vs Output
Current (36VOUT
Output Voltage Ripple, Unmodified
DC2017A Demo Board 12VOUT
)
)
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ꢏꢎꢓꢓ ꢔꢒꢒ
ꢏꢎꢓꢓ ꢔꢒꢕ
Maximum Output Current vs
CTL Voltage, Unmodified
DC2017A, 12VIN
Start-Up Behavior, DC2017A,
24VIN, 3A Resistive Load
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C
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C
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ꢌꢔꢏꢏ ꢅꢒꢎ
Rev C
6
For more information www.analog.com
LTM8055/LTM8055-1
PIN FUNCTIONS
GND (Bank 1, Pin L1): Tie these GND pins to a local
ground plane below the LTM8055/LTM8055-1 and the
circuit components. In most applications, the bulk of the
heatflowoutoftheLTM8055/LTM8055-1isthroughthese
pads, so the printed circuit design has a large impact on
the thermal performance of the part. See the PCB Layout
and Thermal Considerations sections for more details.
MODE (Pin G2): Switching Mode Input. The LTM8055/
LTM8055-1 operates in forced continuous mode when
MODE is open, and can operate in discontinuous switch-
ing mode when MODE is low. In discontinuous switching
mode, the LTM8055/LTM8055-1 will block reverse induc-
tor current. This pin is normally left open or tied to LL.
This pin may be tied to GND for the purpose of blocking
reverse current if no output current sense resistor is used.
Return the R /R feedback divider to this net.
FB1 FB2
RT (PinH1):TimingResistor.TheRT pinisusedtoprogram
the switching frequency of the LTM8055/LTM8055-1 by
connecting a resistor from this pin to ground. The range
of oscillation is 100kHz to 800kHz. The Applications
Information section of the data sheet includes a table
to determine the resistance value based on the desired
switching frequency. Minimize capacitance at this pin.
V
(Bank 2): Power Output Pins. Apply output filter
OUT
capacitors between these pins and GND pins.
V (Bank 3): Input Power. The V pin supplies current to
IN
IN
the LTM8055/LTM8055-1’s internal power switches and
to one terminal of the optional input current sense resis-
tor. This pin must be locally bypassed with an external,
low ESR capacitor; see Table 1 for recommended values.
SYNC(PinH2):ExternalSynchronizationInput.TheSYNC
pin has an internal pull-down resistor. See the Synchroni-
zation section in Applications Information for details. Tie
this pin to GND when not used.
I
(Pin D1): Output Current Sense. Tie this pin to the
OUT
output current sense resistor. The output average current
sense threshold is 58mV, so the LTM8055/LTM8055-1
will regulate the output current to 58mV/R
R
, where
SENSE
FB (Pin J1): Output Voltage Feedback. The LTM8055/
LTM8055-1 regulates the FB pin to 1.2V. Connect the FB
pin to a resistive divider between the output and GND to
set the output voltage. See Table 1 for recommended FB
divider resistor values.
is the value of the output current sense resistor
SENSE
in ohms. The load is powered through the sense resistor
connected at this pin. Tie this pin to V if no output
current sense resistor is used. Keep this pin within 0.5V
of V under all conditions.
OUT
OUT
COMP (Pin J2): Compensation Pin. The LTM8055 is
equipped with internal compensation that works well with
most applications, so this pin is usually left open. Some
applications, however, may benefit from a compensation
network other than the one integrated into the LTM8055.
In such cases, use the LTM8055-1, which has no internal
compensation network and apply an appropriate external
compensation network for optimal and proper operation.
LL (Pin F1): Light Load Indicator. This open drain pin
indicates that the output current, as sensed through the
resistorconnectedbetweenV andI ,isapproximately
OUT
OUT
equivalent to 6mV or less. Its state is meaningful only if a
current sense resistor is applied between V and I
.
OUT
OUT
This is useful to change the switching behavior of the
LTM8055/LTM8055-1 in light load conditions.
SV (Pins F10, F11): Controller Power Input. Apply a
IN
SS (Pin K1): Soft-Start. Connect a capacitor from this pin
to GND to increase the soft-start time. Soft-start reduces
the input power source’s surge current by gradually in-
creasing the controller’s current limit. Larger values of the
soft-start capacitor result in longer soft-start times. If no
soft-start is required, leave this pin open.
separate voltage above 5V if the LTM8055/LTM8055-1
is required to operate when the main power input (V )
IN
is below 5V. Bypass these pins with a high quality, low
ESR capacitor. If a separate supply is not used, connect
these pins to V .
IN
CLKOUT (Pin G1): Clock Output. Use this pin as a clock
source when synchronizing other devices to the switching
frequencyoftheLTM8055/LTM8055-1.Whenthisfunction
is not used, leave this pin open.
CTL (Pin K2): Current Sense Adjustment. Apply a voltage
below 1.2V to reduce the current limit threshold of I
.
OUT
Drive CTL to less than 50mV to stop switching. The CTL
pin has an internal pull-up resistor to 2V. If not used,
leave open.
Rev C
7
For more information www.analog.com
LTM8055/LTM8055-1
PIN FUNCTIONS
I
(Pin L2): Output Current Monitor. This pin pro-
(typical), but below 6V, the RUN pin input bias current is
less than 1μA. Below 1.2V and above 0.3V, the RUN pin
sinks 3μA so the user can define the hysteresis with the
externalresistorselection.Thiswillalsoresetthesoft-start
function. If RUN is 0.3V or less, the LTM8055/LTM8055-1
OUTMON
duces a voltage that is proportional to the voltage between
and I . I will equal 1.2V when V – I
OUT
V
OUT
OUT OUTMON
OUT
= 58mV. This feature is generally useful only if a current
sense resistor is applied between V and I . This is
OUT
OUT
a high impedance output. Use a buffer to drive a load.
is disabled and the SV quiescent current is below 1μA.
IN
I
(Pin L3): Input Current Monitor. This pin produces
I (Pin L9): Input Current Sense. Tie this pin to the input
INMON
IN
a voltage that is proportional to the voltage between I
current sense resistor. The input average current sense
IN
and V . I
will equal 1V when I – V = 50mV. This
threshold is 50mV, so the LTM8055/LTM8055-1 will
IN INMON
IN IN
feature is generally useful only if a current sense resistor
is applied between V and I .
regulate the input current to 50mV/R
, where R
SENSE SENSE
is the value of the input current sense resistor in ohms.
IN
IN
Tie to V when not used. Keep this pin within 0.5V of
IN
RUN(PinL4):LTM8055/LTM8055-1Enable.RaisetheRUN
pin voltage above 1.2V for normal operation. Above 1.2V
V under all conditions.
IN
BLOCK DIAGRAM
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ꢈꢀꢉ
ꢀꢁꢂꢃꢄ
Rꢕꢒ
ꢚꢒꢘ
ꢂꢉ
ꢊꢀꢀꢓ ꢊꢀꢀꢓ
ꢄꢗ
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Cꢌꢙꢍꢕꢋ
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Rꢋ
ꢐꢑꢒC
ꢖꢀꢈꢈ ꢗꢘ
Rev C
8
For more information www.analog.com
LTM8055/LTM8055-1
OPERATION
The LTM8055/LTM8055-1 is a standalone nonisolated
buck-boostswitchingDC/DCpowersupply.Thebuck-boost
topology allows the LTM8055/LTM8055-1 to regulate its
output voltage for input voltages both above and below
themagnitudeoftheoutput. Themaximumoutputcurrent
depends upon the input voltage. Higher input voltages
yield higher maximum output current.
Furthermore, while the LTM8055/LTM8055-1 does not
requireanoutputsenseresistortooperate,itusesinforma-
tion from the sense resistor to optimize its performance.
If an out-put sense resistor is not used, the efficiency
or output ripple may degrade, especially if the current
through the integrated inductor is discontinuous. In some
cases, an output sense resistor is required to adequately
protecttheLTM8055/LTM8055-1againstoutputoverload
or short-circuit.
This converter provides a precisely regulated output volt-
age programmable via an external resistor divider from
1.2V to 36V. The input voltage range is 5V to 36V, but
the LTM8055/LTM8055-1 may be operated at lower input
A voltage less than 1.2V applied to the CTL pin reduces
the maximum output current. Drive CTL to about 50mV
to stop switching. The current flowing through the sense
voltages if SV is powered by a voltage source above 5V.
IN
A simplified block diagram is given on the previous page.
resistorisreflectedbytheoutputvoltageoftheI
pin.
OUTMON
The LTM8055/LTM8055-1 contains a current mode con-
troller, power switching elements, power inductor and
a modest amount of input and output capacitance. The
LTM8055/LTM8055-1isafixedfrequencyPWM regulator.
Theswitchingfrequencyissetbyconnectingtheappropri-
ate resistor value from the RT pin to GND.
Driving the SYNC pin will synchronize the LTM8055/
LTM8055-1 to an external clock source. The CLKOUT
pin sources a signal that is the same frequency but ap-
proximately 180° out of phase with the internal oscillator.
If more output current is required than a single LTM8055/
LTM8055-1 can provide, multiple devices may be oper-
ated in parallel. Refer to the Parallel Operation section of
Applications Information for more details.
The output voltage of the LTM8055/LTM8055-1 is set by
connecting the FB pin to a resistor divider between V
and GND.
OUT
Aninternalregulatorprovidespowertothecontrolcircuitry
and the gate driver to the power MOSFETs. This internal
In addition to regulating its output voltage, the LTM8055/
LTM8055-1isequippedwithaveragecurrentcontrolloops
for both the input and output. Add a current sense resistor
regulator draws power from the SV pin. The RUN pin
IN
is used to place the LTM8055/LTM8055-1 in shutdown,
disconnecting the output and reducing the input current
to less than 1μA.
between I and V to limit the input current below some
IN
IN
maximumvalue.TheI
though the sense resistor between I and V .
pinreflectsthecurrentflowing
INMON
IN
IN
The LTM8055/LTM8055-1 is equipped with a thermal
shutdown that inhibits power switching at high junction
temperatures. The activation threshold of this function is
above 125°C to avoid interfering with normal operation,
so prolonged or repetitive operation under a condition in
which the thermal shutdown activates may damage or
impair the reliability of the device.
A current sense resistor between V
and I
allows
OUT
OUT
theLTM8055/LTM8055-1toaccuratelyregulateitsoutput
current to a maximum value set by the value of the sense
resistor. When the resistor is present, the I
reflects the output current flowing through V
pin
OUTMON
.
OUT
Ingeneral,theLTM8055/LTM8055-1shouldbeusedwithan
outputsenseresistortolimitthemaximumoutputcurrent,
as buck-boost regulators are capable of delivering large
currents when the output voltage is lower than the input,
if demanded.
TheLTM8055featuresanintegratedcompensationnetwork
thatworkswellundermostconditions.Someapplications,
however, benefit from a different compensation network.
In such cases, use the LTM8055-1, which has no internal
compensation network. Apply an appropriate external
compensation network for optimal and proper operation.
Rev C
9
For more information www.analog.com
LTM8055/LTM8055-1
APPLICATIONS INFORMATION
For most applications, the design process is straight for-
ward, summarized as follows:
the graphs in the Typical Performance Characteristics
section for guidance.
Themaximumfrequency(andattendantR value)atwhich
1. Look at Table 1 and find the row that has the desired
input range and output voltage.
T
the LTM8055/LTM8055-1 should be allowed to switch is
giveninTable1inthef
column,whiletherecommended
MAX
2. Apply the recommended C , C , R /R and R
IN OUT FB1 FB2
T
frequency (and R value) for optimal efficiency over the
T
values.
given input condition is given in the f
column.
OPTIMAL
3. Applytheoutputsenseresistortosettheoutputcurrent
limit. The output current is limited to 58mV/R
There are additional conditions that must be satisfied if
the synchronization function is used. Please refer to the
Synchronization section for details.
,
SENSE
where R
is the value of the output current sense
SENSE
resistor in ohms.
Note that Table 1 calls out both ceramic and electrolytic
output capacitors. Both of the capacitors called out in
the table must be applied to the output. The electrolytic
capacitors in Table 1 are described by voltage rating,
value and ESR. The voltage rating of the capacitor may
be increased if the application requires a higher voltage
stress derating. The LTM8055/LTM8055-1 can tolerate
variation in the ESR; other capacitors with different ESR
may be used, but the user must verify proper operation
over line, load and environmental conditions. Table 2
4. WhenusingtheLTM8055-1,placetheexternalcompen-
sation network as close as possible to the COMP pin.
Whilethesecomponentcombinationshavebeentested
for proper operation, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions. Bear in mind that
the maximum output current is limited by junction tem-
perature, the relationship between the input and output
voltage magnitude and other factors. Please refer to
Table 1. Recommended Component Values and Configuration (TA = 25°C)
RANGE
V
V
OUT
C
C
OUT
R /R
FB1 FB2
f
(kHz)
R
f
(kHz)
R
T(MAX)
IN
IN
OPTIMAL
T(OPTIMAL)
MAX
5V to 24V
5V to 28V
5V to 31V
5V to 36V
5V to 36V
5V to 36V
3.3V 2 × 4.7µF, 50V, X5R, 0805 22µF, 6.3V, X5R, 0805
100µF, 6V, 75mΩ, Electrolytic
5V 2 × 4.7µF, 50V, X5R, 0805 22µF, 6.3V, X5R, 0805
100µF, 6V, 75mΩ, Electrolytic
8V 2 × 4.7µF, 50V, X5R, 0805 47µF, 10V, X5R, 1206
100µF, 16V, 100mΩ, Electrolytic
12V 2 × 4.7µF, 50V, X5R, 1210 22µF, 25V, X5R, 0805
68µF, 16V, 200mΩ, Electrolytic
18V 2 × 4.7µF, 50V, X7R, 1210 2 x 22µF, 25V, X5R, 1210
47µF, 25V, 900mΩ, Electrolytic
24V 2 × 4.7µF, 50V, X7R, 1210 22µF, 25V, X5R, 1210
33µF, 35V 300mΩ, Electrolytic
100k/56.2k
100k/31.6k
100k/17.4k
100k/11k
600
36.5k
800
24.9k
24.9k
24.9k
24.9k
24.9k
24.9k
24.9k
550
500
600
500
650
650
39.2k
45.3k
36.5k
45.3k
31.6k
31.6k
800
800
800
800
800
800
100k/6.98k
100k/5.23k
100k/3.40k
5.5V to 36V 36V 2 × 4.7µF, 50V, X7R, 1210 10µF, 50V, X5R, 1206
10µF, 50V 120mΩ, Electrolytic
Notes: An input bulk capacitor is required. The output capacitance uses a combination of a ceramic and electrolytic in parallel. Other combinations of
resistor values for the RFB network are acceptable.
Table 2. Electrolytic Caps Used in LTM8055/LTM8055-1 Testing
DESCRIPTION
MANUFACTURER
PART NUMBER
100µF, 6V, 75mΩ, Tantalum C Case
100µF, 16V, 100mΩ, Tantalum Y Case
68µF, 16V, 200mΩ, Tantalum C Case
47µF, 25V, 900mΩ, Tantalum D Case
33µF, 35V, 300mΩ, Tantalum D Case
10µF, 50V, 120mΩ, Aluminum 6.3 × 6mm case
AVX
AVX
AVX
AVX
AVX
TPSC107M006R0075
TPSY107M016R0100
TPSC686M016R0200
TAJD476M025R
TPSD336M035R0300
50HVP10M
Suncon
Rev C
10
For more information www.analog.com
LTM8055/LTM8055-1
APPLICATIONS INFORMATION
gives the description and part numbers of electrolytic
capacitorsusedintheLTM8055/LTM8055-1development
testing and design validation.
Table 3. Switching Frequency vs RT Value
FREQUENCY
100
R VALUE (kΩ)
T
453
147
84.5
59
200
Capacitor Selection Considerations
300
The C and C
capacitor values in Table 1 are the
400
IN
OUT
minimum recommended values for the associated oper-
ating conditions. Applying capacitor values below those
indicated in Table 1 is not recommended, and may result
in undesirable operation. Using larger values is generally
acceptable, and can yield improved dynamic response, if
it is necessary. Again, it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental conditions.
500
45.3
36.5
29.4
24.9
600
700
800
An external resistor from RT to GND is required. Do not
leave this pin open, even when synchronizing to an ex-
ternal clock. When synchronizing the switching of the
LTM8055/LTM8055-1 to an external signal source, the
frequency range is 200kHz to 700kHz.
Ceramic capacitors are small, robust and have very low
ESR. However, not all ceramic capacitors are suitable.
X5R and X7R types are stable over temperature and ap-
plied voltage and give dependable service. Other types,
including Y5V and Z5U have very large temperature and
voltage coefficients of capacitance. In an application cir-
cuit they may have only a small fraction of their nominal
capacitanceresultinginmuchhigheroutputvoltageripple
than expected.
Operating Frequency Trade-Offs
It is recommended that the user apply the optimal R
T
value given in Table 1 for the input and output operating
condition. System level or other considerations, however,
may necessitate another operating frequency. While the
LTM8055/LTM8055-1isflexibleenoughtoaccommodate
a wide range of operating frequencies, a haphazardly
chosen one may result in undesirable operation under
certain operating or fault conditions. A frequency that is
too high can reduce efficiency, generate excessive heat
or even damage the LTM8055/LTM8055-1 if the output
is overloaded or short circuited. A frequency that is too
low can result in a final design that has too much output
ripple, too large of an output capacitor or is unstable.
A final precaution regarding ceramic capacitors concerns
the maximum input voltage rating of the LTM8055/
LTM8055-1. A ceramic input capacitor combined with
trace or cable inductance forms a high Q (underdamped)
tank circuit. If the LTM8055/LTM8055-1 circuit is plugged
into a live supply, the input voltage can ring to twice its
nominal value, possibly exceeding the device’s rating.
This situation is easily avoided; see the Hot-Plugging
Safely section.
Parallel Operation
Two or more LTM8055/LTM8055-1s may be combined to
provide increased output current by configuring them as a
master and a slave, as shown in Figure 1. Each LTM8055/
Frequency Selection
The LTM8055/LTM8055-1 uses a constant frequency
PWM architecturethatcanbeprogrammedtoswitchfrom
100kHz to 800kHz by tying a resistor from the RT pin to
ground. Table 3 provides a list of R resistor values and
their re-sultant frequencies.
LTM8055-1 is equipped with an I
and a CTL pin.
OUTMON
The I
pin’s 0 to 1.2V signal reflects the current
OUTMON
T
passing through the output sense resistor, while a voltage
less than 1.2V applied to the CTL pin will limit the current
passing through the output sense resistor. By applying
the voltage of the master’s I
pin to the slave’s CTL
OUTMON
Rev C
11
For more information www.analog.com
LTM8055/LTM8055-1
APPLICATIONS INFORMATION
pin, the two units will source the same current to the load,
assumingeachLTM8055/LTM8055-1outputcurrentsense
resistor is the same value.
Paralleled LTM8055/LTM8055-1s should normally be al-
lowed to switch in discontinuous mode to prevent current
from flowing from the output of one unit into another; that
is, the MODE pin should be tied to LL. In some cases,
operating the master in forced continuous (MODE open)
and the slaves in discontinuous mode (MODE = LL) is
desirable. If so, current from the output can flow into the
master’s input. Please refer to Input Precaution in this
section for a discussion of this behavior.
ꢆꢇꢃꢉꢇꢃ CꢇRRꢄꢊꢃ
ꢂꢄꢊꢂꢄ RꢄꢂꢈꢂꢃꢆR
ꢀꢁꢂꢃꢄR
ꢃꢆ ꢏꢆꢁꢐ
ꢅ
ꢆꢇꢃ
ꢆꢇꢃ
ꢈ
ꢈ
ꢆꢇꢃꢀꢆꢊ
ꢇꢊꢈꢃꢋ ꢌꢁꢈꢊ
ꢍꢇꢎꢎꢄR
Minimum Input Voltage and RUN
Cꢃꢏ
ꢆꢇꢃꢉꢇꢃ CꢇRRꢄꢊꢃ
ꢂꢄꢊꢂꢄ RꢄꢂꢈꢂꢃꢆR
The LTM8055/LTM8055-1 needs a minimum of 5V for
proper operation, but system parameters may dictate that
the device operate only above some higher input voltage.
For ex-ample, a LTM8055/LTM8055-1 may be used to
ꢂꢏꢁꢅꢄ
ꢅ
ꢆꢇꢃ
ꢈ
ꢆꢇꢃ
ꢑꢒꢓꢓ ꢎꢒꢔ
produce 12V , but the input power source may not be
OUT
Figure 1. Two or More LTM8055/LTM8055-1s May Be Connected
in a Master/Slave Configuration for Increased Output Current
budgeted to provide enough current if the input supply
voltage is below 8V.
The design of a master-slave configuration is straight
forward:
The RUN pin has a typical falling voltage threshold of
1.2V and a typical hysteresis of 25mV. In addition, the
pin sinks 3µA below the RUN threshold. Based upon the
above information and the circuit shown in Figure 2, the
1. Apply the FB resistor network to the master, choosing
the proper values for the desired output voltage. Sug-
gested values for popular output voltages are provided
in Table 1.
V rising (turn-on) threshold is:
IN
R1+R2
V = 3µA •R1 +1.225V
(
)
2. Apply a FB resistor network to the individual slaves
so that the resulting output is higher than the desired
output voltage.
IN
R2
and the V falling turn-off threshold is:
IN
3. Apply the appropriate output current sense resistors
R1+R2
V = 1.2
IN
between V
and I . If the same value is used for the
OUT
OUT
master and slave units, they will share current equally.
ꢂꢃꢄꢅꢆꢇꢇꢈ
ꢂꢃꢄꢅꢆꢇꢇꢉꢊ
4. Connect the master I to the slaves’ CTL pin
OUTMON
ꢋ
ꢌꢁ
through a unity gain buffer. The unity gain buffer is re-
quiredtoisolatetheoutputimpedanceoftheLTM8055/
LTM8055-1fromtheintegratedpull-upontheCTLpins.
Rꢊ
Rꢍ
Rꢀꢁ
ꢅꢆꢇꢇ ꢎꢆꢍ
5. Tie the outputs together.
Figure 2. This Simple Resistor Network Sets the Minimum
Operating Input Voltage Threshold with Hysteresis
Note that this configuration does not require the inputs to
be tied together, making it simple to power a single heavy
load from multiple input sources. Ensure that each input
power source has sufficient voltage and current sourcing
capability to provide the necessary power. Please refer
to the Maximum Output Current vs V and Input Current
vs Output Current curves in the Typical Performance
Characteristics section for guidance.
Minimum Input Voltage and SV
IN
The minimum input voltage of the LTM8055/LTM8055-1
is 5V, but this is only if V and SV are tied to the same
IN
IN
IN
voltage source. If SV is powered from a power source
IN
at or above 5VDC, V can be allowed to fall below 5V and
IN
Rev C
12
For more information www.analog.com
LTM8055/LTM8055-1
APPLICATIONS INFORMATION
theLTM8055/LTM8055-1canstilloperateproperly.Some
examples of this are provided in the Typical Applications
section.
tying the LL and MODE pins together can improve perfor-
mance—see Switching Mode in this section.
In high step-down voltage regulator applications, the
internal current limit can be quite high to allow proper
operation. This can potentially damage the LTM8055/
LTM8055-1 in overload or short-circuit conditions. Ap-
ply an output current sense resistor to set an appropriate
current limit to protect the LTM8055/LTM8055-1 against
these fault conditions.
Soft-Start
Soft-start reduces the input power sources’ surge cur-
rents by gradually increasing the controller’s current. As
indicated in the Block Diagram, the LTM8055/LTM8055-1
hasaninternalsoft-startRCnetwork. Dependinguponthe
load and operating conditions, the internal network may
be sufficient for the application. To increase the soft-start
time, simply add a capacitor from SS to GND.
Output Current Limit Control (CTL)
Use the CTL input to reduce the output current limit from
thevaluesetbytheexternalsenseresistorappliedbetween
Output Current Limit (I
)
OUT
V
and I . The typical control range is between 0V
OUT
OUT
and 1.2V. The CTL pin does not directly affect the input
current limit. If this function is not used, leave CTL open.
Drive CTL to less than about 50mV to stop switching. The
CTL pin has an internal pull-up resistor to 2V.
The LTM8055/LTM8055-1 features an accurate average
outputcurrentlimitsetbyanexternalsenseresistorplaced
between V
and I
as shown in Figure 3. V
and
OUT
OUT
OUT
I
internally connect to a differential amplifier that limits
the current when the voltage V -I
OUT
reaches 58mV.
OUT OUT
Input Current Limit (I )
IN
The current limit is:
SomeapplicationsrequirethatLTM8055/LTM8055-1draw
nomorethansomepredeterminedcurrentfromthepower
source. Current limited power sources and power sharing
are two examples. The LTM8055/LTM8055-1 features
an accurate input current limit set by an external sense
58mV
I
=
OUT(LIM)
R
SENSE
where R
is the value of the sense resistor in ohms.
SENSE
Most applications should use an output sense resistor as
shown in Figure 3, if practical. The internal buck-boost
power stage is current limited, but is nonetheless capable
of delivering large amounts of current in an overload
condition, especially when the output voltage is much
lower than the input and the power stage is operating as
a buck converter.
resistor placed between I and V as shown in Figure
IN
IN
4. V and I internally connect to a differential amplifier
IN
IN
that limits the current when the voltage I -V reaches
IN IN
50mV. The current limit is:
50mV
I
=
IN(LIM)
R
SENSE
where R
is the value of the sense resistor in ohms.
ꢄꢃꢅꢆꢇꢈꢈꢉ
ꢄꢃꢅꢆꢇꢈꢈꢊꢋ
SENSE
R
ꢍꢎꢏꢍꢎ
Ifinputcurrentlimitingisnotrequired,simplytieI toV .
ꢌ
ꢁꢂꢃ
IN
IN
ꢄꢁꢒꢓ
ꢀ
ꢁꢂꢃ
ꢂꢃꢄꢅꢆꢇꢇꢈ
ꢆꢇꢈꢈ ꢐꢇꢑ
R
ꢋꢌꢁꢋꢌ
ꢂꢃꢄꢅꢆꢇꢇꢉꢊ
ꢎꢏꢐꢌR
ꢋꢏꢑRCꢌ
ꢍ
ꢀꢁ
Figure 3. Set The LTM8055/LTM8055-1 Output Current Limit with
an External Sense Resistor
ꢀ
ꢀꢁ
When the voltage across the output sense resistor falls
to about 1/10th of full scale, the LL pin pulls low. If there
ꢅꢆꢇꢇ ꢒꢆꢓ
Figure 4. Set the LTM8055/LTM8055-1 Input Current
Limit with an External Sense Resistor
is no output sense resistor, and I
is tied to V , LL
OUT
OUT
will be active low. Applying an output sense resistor and
Rev C
13
For more information www.analog.com
LTM8055/LTM8055-1
APPLICATIONS INFORMATION
Input Current Monitor (I
)
chronous switching converter, it delivers this energy to
the input. If there is nothing on the LTM8055/LTM8055-1
input to consume this energy, the input voltage may rise.
If the input voltage rises without intervention, it may rise
above the absolute maximum rating, damaging the part.
Carefully examine the input voltage behavior to see if the
application causes it to rise.
INMON
The I
pin produces a voltage equal to approximately
INMON
20 times the voltage of I – V . Since the LTM8055/
IN
IN
LTM8055-1 input current limit engages when I – V =
50mV, I
IN
IN
will be 1V at maximum input current.
INMON
Output Current Monitor (I
)
OUTMON
Inmanycases,thesystemloadontheLTM8055/LTM8055-
1inputbuswillbesufficienttoabsorbtheenergydelivered
by the μModule regulator. The power required by other
devices will consume more than enough to make up for
what the LTM8055/LTM8055-1 delivers. In cases where
the LTM8055/LTM8055-1 is the largest or only power
converter, thismaynotbetrueandsomemeansmayneed
to be devised to prevent the LTM8055/LTM8055-1’s input
from rising too high. Figure 5a shows a passive crowbar
circuit that will dissipate energy during momentary input
overvoltage conditions. The break-down voltage of the
Zener diode is chosen in conjunction with the resistor R to
set the circuit’s trip point. The trip point is typically set well
The I
pin produces a voltage proportional to the
OUTMON
voltage of V
– I . Since the LTM8055/LTM8055-1
OUT
OUT
output current limit engages when V
– I
= 58mV,
OUT
OUT
I
will be 1.2V at maximum output current.
OUTMON
Synchronization
The LTM8055/LTM8055-1 switching frequency can be
synchronized to an external clock using the SYNC pin.
Driving SYNC with a 50% duty cycle waveform is a good
choice, otherwise maintain the duty cycle between about
10% and 90%. When synchronizing, a valid resistor value
(that is, a value that results in a free-running frequency of
100kHz to 800kHz) must be connected from RT to GND.
above the maximum V voltage under normal operating
IN
While an RT resistor is required for proper operation, the
value of this resistor is independent of the frequency of
the externally applied SYNC signal. Be aware, however,
thattheLTM8055/LTM8055-1willswitchatthefrequency
prescribed by the RT value if the SYNC signal terminates,
so choose an appropriate resistor value.
conditions. This circuit does not have a precision thresh-
old, and is subject to both part-to-part and temperature
variations, so it is most suitable for applications where
the maximum input voltage is much less than the 40V
IN
absolute maximum. As stated earlier, this type of circuit
is best suited for momentary overvoltages.
Figure 5a is a crowbar circuit, which attempts to prevent
theinputvoltagefromrisingabovesomelevelbydumping
energy to GND through a power device. In some cases,
it is possible to simply turn off the LTM8055/LTM8055-1
when the input voltage exceeds some threshold. An ex-
ampleofthiscircuitisshowninFigure5b.Whenthepower
CLKOUT
The CLKOUT signal reflects the internal switching clock
of the LTM8055/LTM8055-1. It is phase shifted by ap-
proximately 180° with respect to the leading edge of the
internal clock. If CLKOUT is connected to the SYNC input
of another LTM8055/LTM8055-1, the two devices will
switch about 180° out of phase.
source on the output drives V above a predetermined
IN
threshold, the comparator pulls down on the RUN pin
and stops switching in the LTM8055/LTM8055-1. When
this happens, the input capacitance needs to absorb the
energy stored within the LTM8055/LTM8055-1’s internal
inductor, resulting in an additional voltage rise. This volt-
age rise depends upon the input capacitor size and how
much current is flowing from the LTM8055/LTM8055-1
output to input.
Input Precaution
In applications where the output voltage is deliberately
pulled up above the set regulation voltage or the FB pin is
abruptlydriventoanewvoltage,theLTM8055/LTM8055-1
may attempt to regulate the voltage by removing energy
from the load for a short period of time after the output
is pulled up. Since the LTM8055/LTM8055-1 is a syn-
Rev C
14
For more information www.analog.com
LTM8055/LTM8055-1
APPLICATIONS INFORMATION
from buck, buck-boost or boost operating modes, espe-
cially at lighter loads. In such a case, it can be desirable
to operate in forced continuous mode except when the
internal inductor current is about to reverse. If so, apply
ꢍꢆꢓꢅ
CꢔRRꢄꢂꢎ
ꢀ
ꢀ
ꢆꢔꢎ
ꢁꢂ
ꢍꢎꢏꢈꢉꢊꢊꢐ
ꢍꢎꢏꢈꢉꢊꢊꢑꢒ
ꢃꢄꢂꢄR
ꢅꢁꢆꢅꢄ
ꢕꢂꢅ
ꢖꢆꢔRCꢁꢂꢕ
ꢍꢆꢓꢅ
ꢇ
a current sense resistor between V
and I
and tie
OUT
OUT
R
the LL and MODE pins together. The LL pin is low when
the current through the output sense resistor is about
one-tenth the full-scale maximum. When the output cur-
rent falls to this level, the LL pin will pull the MODE pin
down, puttingtheLTM8055/LTM8055-1indiscontinuous
mode, preventing reverse current from flowing from the
output to the input. In the case where MODE and LL are
tied together, a small capacitor (~0.1µF) from these pins
to GND may improve the light load transient response by
delaying the transition from the discontinuous to forced
continuous switching modes. MODE may be tied to GND
for the purpose of blocking reverse current if no output
current sense resistor is used.
ꢈꢉꢊꢊ ꢋꢉꢊꢌ
Figure 5a. The MOSFET Q Dissipates Momentary Energy to
GND. The Zener Diode and Resistor Are Chosen to Ensure That
the MOSFET Turns On Above the Maximum VIN Voltage Under
Normal Operation
ꢋꢐꢑꢒ
CꢃRRꢓꢂꢌ
ꢀ
ꢀ
ꢐꢃꢌ
ꢋꢌꢍꢄꢅꢆꢆꢎ
ꢋꢌꢍꢄꢅꢆꢆꢏꢉ
ꢁꢂ
ꢔꢂꢒ
Rꢃꢂ
ꢕꢐꢃRCꢁꢂꢔ
ꢋꢐꢑꢒ
ꢉꢅꢊꢇ
ꢘ
ꢗ
ꢓꢖꢌꢓRꢂꢑꢋ
RꢓꢇꢓRꢓꢂCꢓ
ꢀꢐꢋꢌꢑꢔꢓ
FB Resistor Divider and Load Regulation
ꢄꢅꢆꢆ ꢇꢅꢆꢈ
The LTM8055/LTM8055-1 regulates its FB pin to 1.2V,
using a resistor divider to sense the output voltage. The
location at which the output voltage is sensed affects
the load regulation. If there is a current sense resistor
Figure 5b. This Comparator Circuit Turns Off the LTM8055/
LTM8055-1 if the Input Rises Above a Predetermined
Threshold. When the LTM8055/LTM8055-1 Turns Off, the
Energy Stored in the Internal Inductor Will Raise VIN a Small
Amount Above the Threshold
between V
and I , and the output is sensed at V
,
OUT
OUT
OUT
the voltage at the load will drop by the value of the cur-
rent sense resistor multiplied by the output current. If the
Switching Mode
output voltage can be sensed at I , the load regulation
OUT
TheMODEpinallowstheusertoselecteitherdiscontinuous
mode or forced continuous mode switching operation. In
forcedcontinuousmode,theLTM8055/LTM8055-1willnot
skip cycles, even when the internal inductor current falls
to zero or even reverses direction. This has the advantage
of operating at the same fixed frequency for all load condi-
tions,whichcanbeusefulwhendesigningtoEMIoroutput
noise specifications. Forced continuous mode, however,
usesmorecurrentatlightloads,andallowscurrenttoflow
from the load back into the input if the output is raised
above the regulation point. This reverse current can raise
the input voltage and be hazardous if the input is allowed
to rise uncontrollably. Please refer to Input Precautions
in this section for a discussion of this behavior.
may be improved.
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8055/LTM8055-1. The LTM8055/
LTM8055-1isneverthelessaswitchingpowersupply,and
care must be taken to minimize EMI and ensure proper
operation. Even with the high level of integration, you may
failtoachievespecifiedoperationwithahaphazardorpoor
layout. See Figure 6 for a suggested layout. Ensure that
the grounding and heat sinking are acceptable.
A few rules to keep in mind are:
Forcedcontinuousoperationmayprovideimprovedoutput
regulation when the LTM8055/LTM8055-1 transitions
1. Place the R and R resistors as close as possible to
FB
T
their respective pins.
Rev C
15
For more information www.analog.com
LTM8055/LTM8055-1
APPLICATIONS INFORMATION
2. Place the C capacitor as close as possible to the V
board. Pay attention to the location and density of the
thermal vias in Figure 6. The LTM8055/LTM8055-1 can
benefit from the heat sinking afforded by vias that con-
nect to internal GND planes at these locations, due to
theirproximitytointernalpowerhandlingcomponents.
The optimum number of thermal vias depends upon
the printed circuit board design. For example, a board
might use very small via holes. It should employ more
thermal vias than a board that uses larger holes.
IN
IN
and GND connection of the LTM8055/LTM8055-1.
3. Place the C
capacitor as close as possible to the
OUT
V
andGNDconnectionoftheLTM8055/LTM8055-1.
OUT
4. Minimize the trace resistance between the optional
outputcurrentsenseresistor,R ,andV .Minimize
OUT
OUT
the loop area of the I
trace and the trace from V
OUT
OUT
to R
.
OUT
5. Minimizethetraceresistancebetweentheoptionalinput
current sense resistor, R and V . Minimize the loop
Hot-Plugging Safely
IN
IN
area of the I trace and the trace from V to R .
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypasscapacitorofLTM8055/LTM8055-1.However,these
capacitorscancauseproblemsiftheLTM8055/LTM8055-1
is plugged into a live supply (see Linear Technology Ap-
plication Note 88 for a complete discussion). The low
loss ceramic capacitor combined with stray inductance
in series with the power source forms an underdamped
IN
IN
IN
6. Place the C and C
capacitors such that their
OUT
IN
ground current flow directly adjacent or underneath
the LTM8055/LTM8055-1.
7. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8055/LTM8055-1.
tank circuit, and the voltage at the V pin of the LTM8055/
IN
LTM8055-1 can ring to more than twice the nominal input
voltage, possibly exceeding the LTM8055/LTM8055-1’s
rating and damaging the part. If the input supply is poorly
controlledortheLTM8055/LTM8055-1ishot-pluggedinto
8. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
C
ꢈꢆ
ꢉꢆꢌ
ꢄꢇ
ꢈꢆ
ꢇ
ꢈꢆ
R
ꢈꢆ
ꢉꢆꢌꢍꢂꢎꢅRꢏꢊꢋ ꢇꢈꢊꢄ
ꢈꢆꢃꢁꢂ
ꢄꢅꢆꢄꢅ
ꢈ
ꢈꢆ
C
ꢀꢁꢂ
ꢈꢆꢃꢁꢂ
Rꢁꢆ
ꢇ
ꢄꢈꢉꢆꢊꢋ ꢇꢈꢊ
ꢀꢁꢂ
ꢇ
ꢏꢀꢌꢅ ꢄꢕꢆC
Rꢂ ꢓꢖ
ꢀꢁꢂ
ꢈ
ꢀꢁꢂ
ꢋꢋ
R
ꢀꢁꢂ
ꢀꢁꢂꢃꢁꢂ
ꢄꢅꢆꢄꢅ
ꢉꢆꢌ
ꢈ
ꢀꢁꢂ
ꢇ
ꢀꢁꢂ
ꢄꢈꢉꢆꢊꢋ ꢇꢈꢊ
ꢐꢑꢒꢒ ꢓꢑꢔ
Figure 6. Layout Showing Suggested External Components,
GND Plane and Thermal Vias
Rev C
16
For more information www.analog.com
LTM8055/LTM8055-1
APPLICATIONS INFORMATION
θ
– Thermal resistance from junction to the printed
anenergizedsupply,theinputnetworkshouldbedesigned
JB
to prevent this overshoot. This can be accomplished by
circuit board.
installing a small resistor in series with V , but the most
IN
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confusion
and inconsistency. These definitions are given in JESD
51-12, and are quoted or paraphrased below:
popular method of controlling input voltage overshoot is
to add an electrolytic bulk capacitor to the V net. This
IN
capacitor’s relatively high equivalent series resistance
damps the circuit and eliminates the voltage overshoot.
The extra capacitor improves low frequency ripple filter-
ing and can slightly improve the efficiency of the circuit,
thoughitislikelytobethelargestcomponentinthecircuit.
θ
is the natural convection junction-to-ambient air
JA
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted to
a JESD 51-9 defined test board, which does not reflect an
actual application or viable operating condition.
Thermal Considerations
The LTM8055/LTM8055-1 output current may need to be
derated if it is required to operate in a high ambient tem-
perature or deliver a large amount of continuous power.
The amount of current derating is dependent upon the
inputvoltage,outputpowerandambienttemperature.The
temperature rise curves given in the Typical Performance
Characteristicssectioncanbeusedasaguide.Thesecurves
were generated by a LTM8055/LTM8055-1 mounted to a
θ
is the thermal resistance between the junction
JCbottom
andbottomofthepackagewithallofthecomponentpower
dissipation flowing through the bottom of the package. In
the typical µModule converter, the bulk of the heat flows
out the bottom of the package, but there is always heat
flow out into the ambient environment. As a result, this
thermal resistance value may be useful for comparing
packages but the test conditions don’t generally match
the user’s application.
2
58cm 4-layer FR4 printed circuit board. Boards of other
sizesandlayercountcanexhibitdifferentthermalbehavior,
so it is incumbent upon the user to verify proper operation
over the intended system’s line, load and environmental
operating conditions.
θ
isdeterminedwithnearlyallofthecomponentpower
JCtop
dissipation flowing through the top of the package. As the
electricalconnectionsofthetypicalµModuleconverterare
on the bottom of the package, it is rare for an application
to operate such that most of the heat flows from the junc-
tion to the top of the part. As in the case of θ
value may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
ThethermalresistancenumberslistedinthePinConfigura-
tion of the data sheet are based on modeling the µModule
package mounted on a test board specified per JESD 51-9
(TestBoardsforAreaArraySurfaceMountPackageThermal
Measurements). Thethermalcoefficientsprovidedonthis
page are based on JESD 51-12 (Guidelines for Reporting
and Using Electronic Package Thermal Information).
, this
JCbottom
θ
JB
is the junction-to-board thermal resistance where
Forincreasedaccuracyandfidelitytotheactualapplication,
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration of the data sheet typi-
cally gives four thermal coefficients:
almost all of the heat flows through the bottom of the
µModule converter and into the board, and is really the
sum of the θ
bottom of the part through the solder joints and through a
portion of the board. The board temperature is measured
a specified distance from the package, using a 2-sided,
2-layer board. This board is described in JESD 51-9.
and the thermal resistance of the
JCbottom
θ
JA
– Thermal resistance from junction to ambient.
θ
–Thermalresistancefromjunctiontothebottom
JCbottom
of the product case.
θ
– Thermal resistance from junction to top of the
JCtop
product case.
Rev C
17
For more information www.analog.com
LTM8055/LTM8055-1
APPLICATIONS INFORMATION
ꢏꢉꢌCꢎꢐꢇꢌꢑꢎꢇꢑꢒꢆꢗꢐꢋꢌꢎ RꢋꢓꢐꢓꢎꢒꢌCꢋ ꢔꢏꢋꢓꢈ ꢂꢘꢑꢙ ꢈꢋꢃꢐꢌꢋꢈ ꢗꢇꢒRꢈꢖ
ꢏꢉꢌCꢎꢐꢇꢌꢑꢎꢇꢑCꢒꢓꢋ ꢔꢎꢇꢕꢖ
RꢋꢓꢐꢓꢎꢒꢌCꢋ
Cꢒꢓꢋ ꢔꢎꢇꢕꢖꢑꢎꢇꢑꢒꢆꢗꢐꢋꢌꢎ
RꢋꢓꢐꢓꢎꢒꢌCꢋ
ꢏꢉꢌCꢎꢐꢇꢌꢑꢎꢇꢑꢗꢇꢒRꢈ RꢋꢓꢐꢓꢎꢒꢌCꢋ
ꢏꢉꢌCꢎꢐꢇꢌ
ꢒꢆꢗꢐꢋꢌꢎ
ꢏꢉꢌCꢎꢐꢇꢌꢑꢎꢇꢑCꢒꢓꢋ
ꢔꢗꢇꢎꢎꢇꢆꢖ RꢋꢓꢐꢓꢎꢒꢌCꢋ
Cꢒꢓꢋ ꢔꢗꢇꢎꢎꢇꢆꢖꢑꢎꢇꢑꢗꢇꢒRꢈ
ꢗꢇꢒRꢈꢑꢎꢇꢑꢒꢆꢗꢐꢋꢌꢎ
RꢋꢓꢐꢓꢎꢒꢌCꢋ
RꢋꢓꢐꢓꢎꢒꢌCꢋ
ꢀꢁꢂꢂ ꢃꢁꢄ
ꢅꢆꢇꢈꢉꢊꢋ CꢇꢌꢍꢋRꢎꢋR
Figure 7
Giventhesedefinitions,itshouldnowbeapparentthatnone
of these thermal coefficients reflects an actual physical
operating condition of a µModule converter. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature versus load graphs
givenintheproduct’sdatasheet.Theonlyappropriateway
to use the coefficients is when running a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
The blue resistances are contained within the µModule
converter, and the green are outside.
The die temperature of the LTM8055/LTM8055-1 must be
lower than the maximum rating of 125°C, so care should
be taken in the layout of the circuit to ensure good heat
sinking of the LTM8055/LTM8055-1. The bulk of the heat
flowoutoftheLTM8055/LTM8055-1isthroughthebottom
oftheμModuleconverterandtheBGApadsintotheprinted
circuit board. Consequently a poor printed circuit board
design can cause excessive heating, resulting in impaired
performance or reliability. Please refer to the PCB Layout
section for printed circuit board design suggestions.
A graphical representation of these thermal resistances
is given in Figure 7.
Rev C
18
For more information www.analog.com
LTM8055/LTM8055-1
TYPICAL APPLICATIONS
12VOUT Fan Power from 3VIN to 36VIN with Analog
Current Control and 2A Input Current Limiting
Maximum Output Current
vs CTL Voltage
1µF
50V
ꢌꢍꢎ
ꢌꢍꢏ
ꢏꢍꢐ
ꢏꢍꢑ
ꢏꢍꢒ
ꢏꢍꢎ
ꢏ
ꢌꢎꢂ
ꢕꢋ
SV
0.022Ω
0.05Ω
IN
LTM8055/
V
V
V
IN
OUT
V
IN
OUT
LTM8055-1
3V TO 36V
12V MAX
I
I
IN
OUT
FAN
100k
10µF
50V
22µF
25V
RUN
COMP
SS
SYNC
CTL
RT
+
CLKOUT
68µF
25V
I
INMON
I
OUTMON
FB
36.5k
11.0k
LL MODE
DAC
GND
8055 TA02a
ꢏ
ꢏꢍꢎ
ꢏꢍꢒ
ꢏꢍꢑ
ꢏꢍꢐ
ꢌ
ꢌꢍꢎ
f
= 600kHz
SW
Cꢀꢁ ꢂꢃꢁꢀꢄꢅꢆ ꢇꢂꢈ
ꢐꢏꢓꢓ ꢀꢄꢏꢎꢔ
FAN CONTROL
0.2V TO 1.2V
CONTROL RANGE
24VOUT from 7VIN to 36VIN with 2.1A Accurate Current Limit
Output Voltage vs Output Current
0.027Ω
LTM8055/
LTM8055-1
V
V
V
IN
OUT
V
IN
OUT
ꢌꢍ
ꢌꢏ
ꢎꢍ
ꢎꢏ
ꢍ
7V TO 36V
24V
SV
I
IN
OUT
ꢎꢌꢉ
ꢔꢅ
I
IN
22µF
25V
10µF
50V
RUN
COMP
SS
100k
+
CLKOUT
33µF
35V
SYNC
CTL
RT
I
INMON
I
36.5k
OUTMON
FB
5.23k
LL MODE GND
8055 TA03a
f
= 600kHz
SW
ꢏ
ꢏ
ꢏꢓꢍ
ꢎ
ꢎꢓꢍ
ꢌ
ꢌꢓꢍ
ꢀꢁꢂꢃꢁꢂ CꢁRRꢄꢅꢂ ꢆꢇꢈ
ꢐꢏꢍꢍ ꢂꢇꢏꢑꢒ
Rev C
19
For more information www.analog.com
LTM8055/LTM8055-1
TYPICAL APPLICATIONS
3.3VOUT from 9VIN to 24VIN with 5A Accurate Current Limit and
Output Current Monitor
Output Voltage vs Output Current
ꢌꢍꢎ
ꢏꢍꢑ
ꢏꢍꢎ
ꢐꢍꢑ
ꢐꢍꢎ
0.011Ω
V
V
LTM8055/
V
IN
OUT
V
IN
OUT
LTM8055-1
9V TO 24V
3.3V
SV
I
IN
OUT
I
IN
10µF
50V
RUN
CTL
SS
SYNC
COMP
RT
+
100k
22µF
6.3V
OUTPUT
CURRENT
MONITOR
100µF
6.3V
CLKOUT
I
INMON
ꢒꢍꢑ
ꢒꢍꢎ
ꢎꢍꢑ
ꢎ
I
OUTMON
FB
36.5k
LL MODE GND
56.2k
8055 TA04a
ꢎ
ꢒ
ꢐ
ꢏ
ꢌ
ꢑ
ꢕ
f
= 600kHz
SW
ꢀꢁꢂꢃꢁꢂ CꢁRRꢄꢅꢂ ꢆꢇꢈ
ꢓꢎꢑꢑ ꢂꢇꢎꢌꢔ
Two LTM8055/LTM8055-1s Paralleled to Get More Output Current. The Two
µModules Are Synchronized and Switching 180° Out Of Phase
I
OUTMON Voltage vs Output Current
for Each Channel, 12VIN
0.008Ω
V
V
LTM8055/
LTM8055-1
(MASTER)
V
IN
OUT
V
IN
OUT
7V TO 36V
ꢑꢒꢓ
ꢑꢒꢔ
ꢔꢒꢕ
ꢔꢒꢖ
ꢔꢒꢗ
ꢔꢒꢓ
ꢔ
12V
SV
I
IN
OUT
I
IN
10µF
50V
RUN
CTL
SS
SYNC
COMP
RT
+
22µF
25V
68µF
25V
100k
I
INMON
47pF
I
36.5k
OUTMON
FB
+
ꢁꢌꢉꢈꢅR
ꢉꢍꢌꢐꢅ
CLKOUT
11k
LL MODE GND
LT1636
ꢔ
ꢘ
ꢑꢔ
ꢑꢘ
0.008Ω
V
V
LTM8055/
LTM8055-1
(SLAVE)
IN
OUT
Cꢀꢁꢂꢃꢄꢅꢆ CꢇRRꢅꢄꢈꢉ ꢀꢊ ꢂꢀꢈꢋ Cꢋꢌꢄꢄꢅꢍꢉ ꢎꢌꢏ
ꢕꢔꢘꢘ ꢈꢌꢔꢘꢙ
SV
I
IN
OUT
I
IN
+
22µF
25V
47pF
68µF
25V
10µF
50V
RUN
COMP
SS
CTL
CLKOUT
100k
SYNC
I
INMON
I
36.5k
OUTMON
FB
9.31k
RT
LL MODE GND
8055 TA05a
f
= 600kHz
SW
Rev C
20
For more information www.analog.com
LTM8055/LTM8055-1
TYPICAL APPLICATIONS
Two LTM8055/LTM8055-1s Powered from Different Input Sources to Run a Single Load. Each LTM8055/LTM8055-1 Draws No More
Than 1.8A from Its Respective Power Source, and Are Synchronized 180° Out Of Phase with Each Other
0.025Ω
V
V
LTM8055/
LTM8055-1
SUPPLY 1
IN
OUT
6V TO 36V
3A MAX
IN
SV
IN
I
V
OUT
OUT
I
IN
12V
22µF
25V
+
68µF
35V
10µF
50V
RUN
CTL
SS
SYNC
COMP
RT
I
INMON
47pF
I
OUTMON
FB
36.5k
100k
11k
CLKOUT
LL MODE GND
0.025Ω
V
V
LTM8055/
LTM8055-1
IN
OUT
SUPPLY 2
6V TO 36V
IN
SV
I
OUT
IN
I
IN
100k
10µF
50V
22µF
25V
RUN
CTL
SS
CLKOUT
I
INMON
47pF
SYNC
COMP
RT
I
OUTMON
FB
36.5k
11k
LL
GND
MODE
8055 TA06a
f
= 600kHz
SW
Input Current and Output Voltage vs
Output Current 12VIN
ꢎꢐ
ꢎꢋ
ꢎꢏ
ꢑ
ꢋꢌꢍ
ꢋꢌꢏ
ꢎꢌꢍ
ꢎꢌꢏ
ꢏꢌꢍ
ꢏ
ꢒ
ꢐ
ꢊ
ꢀꢁꢂ
ꢉꢅꢃꢁꢂ CꢁRRꢄꢅ ꢕ
RꢄꢖꢁꢗꢇꢂꢀR ꢎ
ꢉꢅꢃꢁꢂ CꢁRRꢄꢅ ꢕ
RꢄꢖꢁꢗꢇꢂꢀR ꢋ
ꢋ
ꢏ
ꢏ
ꢎ
ꢋ
ꢔ
ꢐ
ꢀꢁꢂꢃꢁꢂ CꢁRRꢄꢅꢂ ꢆꢇꢈ
ꢑꢏꢍꢍ ꢂꢇꢏꢒꢓ
Rev C
21
For more information www.analog.com
LTM8055/LTM8055-1
PACKAGE DESCRIPTION
Table 4. LTM8055/LTM8055-1 Pin Assignment (Arranged by Pin Number)
PIN ID
A1
FUNCTION
PIN ID
B1
FUNCTION
PIN ID
C1
FUNCTION
PIN ID
D1
FUNCTION
PIN ID
E1
FUNCTION
GND
PIN ID
F1
FUNCTION
LL
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
I
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
A2
B2
C2
D2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E2
GND
F2
GND
GND
GND
GND
GND
GND
GND
GND
A3
B3
C3
D3
E3
GND
F3
A4
B4
C4
D4
E4
GND
F4
A5
B5
C5
D5
E5
GND
F5
A6
B6
C6
D6
E6
GND
F6
A7
GND
GND
GND
GND
GND
B7
GND
GND
GND
GND
GND
C7
GND
GND
GND
GND
GND
D7
E7
GND
F7
A8
B8
C8
D8
E8
GND
F8
A9
B9
C9
D9
E9
GND
F9
A10
A11
B10
B11
C10
C11
D10
D11
E10
E11
GND
F10
F11
SV
IN
SV
IN
GND
PIN ID
G1
FUNCTION
CLKOUT
MODE
GND
PIN ID
H1
FUNCTION
RT
PIN ID
J1
FUNCTION
FB
PIN ID
K1
FUNCTION
SS
PIN ID
L1
FUNCTION
GND
G2
H2
SYNC
GND
J2
COMP
GND
K2
CTL
L2
I
OUTMON
G3
H3
J3
K3
GND
GND
GND
GND
GND
GND
GND
L3
I
INMON
G4
GND
H4
GND
J4
GND
K4
L4
RUN
G5
GND
H5
GND
J5
GND
K5
L5
GND
GND
GND
GND
G6
GND
H6
GND
J6
GND
K6
L6
G7
GND
H7
GND
J7
GND
K7
L7
G8
GND
H8
GND
J8
GND
K8
L8
G9
GND
H9
GND
J9
GND
K9
L9
I
IN
G10
G11
V
V
H10
H11
V
V
J10
J11
V
IN
V
IN
K10
K11
V
IN
V
IN
L10
L11
V
IN
V
IN
IN
IN
IN
IN
Rev C
22
For more information www.analog.com
LTM8055/LTM8055-1
PACKAGE PHOTO
Rev C
23
For more information www.analog.com
LTM8055/LTM8055-1
PACKAGE DESCRIPTION
ꢒ
ꢯ ꢯ ꢲ ꢲ ꢲ
ꢒ
ꢡ ꢬ ꢗ ꢠ ꢟ
ꢠ ꢬ ꢟ ꢝ ꢟ
ꢗ ꢬ ꢝ ꢍ ꢟ
ꢜ ꢬ ꢠ ꢊ ꢟ
ꢍ ꢬ ꢜ ꢢ ꢟ
ꢟ ꢬ ꢗ ꢍ ꢢ ꢠ
ꢟ ꢬ ꢗ ꢍ ꢢ
ꢍ ꢬ ꢜ ꢢ ꢟ
ꢟ ꢬ ꢟ ꢟ ꢟ
ꢜ ꢬ ꢠ ꢊ ꢟ
ꢗ ꢬ ꢝ ꢍ ꢟ
ꢠ ꢬ ꢟ ꢝ ꢟ
ꢡ ꢬ ꢗ ꢠ ꢟ
Rev C
24
For more information www.analog.com
LTM8055/LTM8055-1
REVISION HISTORY
REV
DATE
01/16 Added Buck-Bost Selection Table
05/17 Added text to I (pin L2)
DESCRIPTION
PAGE NUMBER
A
1
8
B
OUTMON
C
08/18 Added LTM8055-1
1, 2, 7, 9, 10,
23
Rev C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
25
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTM8055/LTM8055-1
TYPICAL APPLICATION
Input Current vs Input Voltage,
14.4V, 3A Lead-Acid Battery Charger Input Current Limited to 2.1A
IOUT = 3A
ꢍꢎꢏ
ꢍꢎꢐ
ꢑꢎꢏ
ꢑꢎꢐ
ꢐꢎꢏ
ꢐ
1µF
50V
SV
0.022Ω
0.02Ω
IN
V
V
LTM8055/
V
IN
OUT
V
IN
3V TO 36V
OUT
LTM8055-1
14.4V
I
I
IN
OUT
+
100k
47µF
25V
10µF
50V
RUN
CTL
SS
SYNC
COMP
RT
CLKOUT
22µF
25V
I
INMON
I
OUTMON
FB
36.5k
9.09k
ꢐ
ꢑꢐ
ꢍꢐ
ꢕꢐ
ꢖꢐ
LL MODE GND
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
8055 TA07a
ꢒꢐꢏꢏ ꢄꢈꢐꢓꢔ
f
= 600kHz
SW
DESIGN RESOURCES
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
Manufacturing:
• Quick Start Guide/Demo Manual
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
Digital Power System Management
Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTM4605
LTM4607
Higher Power Buck-Boost (Up to 60W)
Higher Power Buck-Boost (Up to 60W)
External Inductor, Synchronous Switching Buck-Boost; Up to 36V , 0.8V ≤ V
≤ 16V
≤ 24V
IN
OUT
External Inductor, Synchronous Switching Buck-Boost; Up to 36V , 0.8V ≤ V
IN
OUT
LTM4609
LTM8045
LTM8046
Higher Power Buck-Boost (Up to 60W)
Smaller, Lower Power
External Inductor, Synchronous Switching Buck-Boost; Up to 36V , 0.8V ≤ V
≤ 34V
IN
OUT
SEPIC and Inverting; 700mA, 6.25mm × 11.25mm × 4.92mm BGA
Isolated, Lower Power
Flyback Topology, 550mA (5V , 24V ), UL60950, 2kVAC
OUT IN
Rev C
D17085-0-8/18(C)
www.analog.com
26
ANALOG DEVICES, INC. 2015-2018
相关型号：
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