LTM9001CV-AA#PBF [Linear]
LTM9001-A and -B - 16-Bit IF/Baseband Receiver Subsystem; Package: LGA; Pins: 81; Temperature Range: 0°C to 70°C;
| 型号： | LTM9001CV-AA#PBF |
| 厂家： | 
Linear |
| 描述： | LTM9001-A and -B - 16-Bit IF/Baseband Receiver Subsystem; Package: LGA; Pins: 81; Temperature Range: 0°C to 70°C |
| 文件： | 总28页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM9001
16-Bit IF/Baseband
Receiver Subsystem
FEATURES
DESCRIPTION
The LTM®9001 is an integrated System in a Package (SiP)
that includes a high-speed 16-bit A/D converter, matching
network, anti-aliasing filter and a low noise, differential
amplifier with fixed gain. It is designed for digitizing wide
dynamicrangesignalswithanintermediatefrequency(IF)
range up to 300MHz. The amplifier allows either AC- or
DC-coupled input drive. A low-pass or bandpass filter
network can be implemented with various bandwidths.
Contact Linear Technology regarding semi-custom con-
figurations.
n
Integrated 16-Bit, High-Speed ADC, Passive Filter
and Fixed Gain Differential Amplifier
n
Up to 300MHz IF Range
Low-Pass and Bandpass Filter Versions
n
Low Noise, Low Distortion Amplifiers
Fixed Gain: 8dB, 14dB, 20dB or 26dB
50Ω, 200Ω or 400Ω Input Impedance
n
72dB SNR, 82dB SFDR (LTM9001-AA)
n
Integrated Bypass Capacitance, No External
Components Required
Optional Internal Dither
n
The LTM9001 is perfect for IF receivers in demanding
communications applications, with AC performance that
includes 72dBFS noise floor and 82dB spurious free dy-
namic range (SFDR) at 162.5MHz (LTM9001-AA).
n
Optional Data Output Randomizer
n
LVDS or CMOS Outputs
n
3.3V Single Supply
n
Power Dissipation: 1.65W
n
n
The digital outputs can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.3V.
Clock Duty Cycle Stabilizer
11.25mm × 11.25mm × 2.32mm LGA Package
APPLICATIONS
n
Telecommunications
n
+
–
High Sensitivity Receivers
The differential ENC and ENC inputs may be driven with
asinewave, PECL, LVDS, TTLorCMOSinputs. Anoptional
clock duty cycle stabilizer allows high performance at full
speed with a wide range of clock duty cycles.
n
Cellular Base Stations
Spectrum Analyzers
n
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
TYPICAL APPLICATION
Simplified IF Receiver Channel
64k Point FFT, FIN = 162.4MHz,
–1dBFS, PGA = 1
V
V
DD
= 3.3V
CC
SENSE
0
LTM9001
0V = 0.5V TO 3.6V
DD
–20
–40
D15
CMOS
•
–60
•
OR
•
–
+
LVDS
IN
ANTI-ALIAS
FILTER
16-BIT
130Msps ADC
D0
RF
HD3
HD2
–80
SAW
CLKOUT
OF
IN
–100
–120
LO
DIFFERENTIAL
FIXED GAIN
AMPLIFIER
OGND
9001 TA01
0
4096
12288
20480
28672
GND
+
ENC ENC
–
FFT BIN NUMBER (32k TOTAL)
ADC CONTROL PINS
9001 TA01b
9001fa
1
LTM9001
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
ALL ELSE
= GND
TOP VIEW
DATA
Supply Voltage (V ) ................................ –0.3V to 3.6V
CC
CONTROL
Supply Voltage (V ) ................................... –0.3V to 4V
DD
1
2
3
4
5
6
7
8
9
Digital Output Supply Voltage (OV ).......... –0.3V to 4V
DD
J
OGND
+
–
Analog Input Current (IN , IN )............................ 10mA
–
IN
IN
H
G
F
Digital Input Voltage
+
OV
DD
(Except AMPSHDN)..................–0.3V to (V + 0.3V)
DD
Digital Input Voltage
E
V
CC
(AMPSHDN)..............................–0.3V to (V + 0.3V)
Digital Output Voltage ................ –0.3V to (OV + 0.3V)
D
C
B
A
CC
DD
DNC
+
ENC
–
Operating Temperature Range
ENC
LTM9001C................................................ 0°C to 70°C
LTM9001I............................................. –40°C to 85°C
Storage Temperature Range................... –45°C to 125°C
Maximum Junction Temperature........................... 125°C
OGND
CONTROL
V
OGND OV
DD DD
LGA PACKAGE
T
= 125°C, θ = 15°C/W, θ = 19°C/W
JMAX
JA JC
θ
JA
DERIVED FROM 60mm × 70mm PCB WITH 4 LAYERS
WEIGHT = 0.71g
ORDER INFORMATION
LEAD FREE FINISH
LTM9001CV-AA#PBF
LTM9001IV-AA#PBF
LTM9001CV-BA#PBF
LTM9001IV-BA#PBF
PART MARKING*
LTM9001V-AA
LTM9001V-AA
LTM9001V-BA
LTM9001V-BA
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
81-Lead (11.25mm × 11.25mm × 2.3mm) LGA
81-Lead (11.25mm × 11.25mm × 2.3mm) LGA
81-Lead (11.25mm × 11.25mm × 2.3mm) LGA
81-Lead (11.25mm × 11.25mm × 2.3mm) LGA
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
G
DIFF
Gain
DC, LTM9001-AA
IN
19.1
19.7
19
20.3
dB
dB
f
= 162.5MHz (Note 3)
DC, LTM9001-BA
7.1
8.2
7.8
9.4
dB
dB
f
IN
= 140MHz (Note 3)
G
Gain Temperature Drift
V
= Maximum, (Note 3)
2
mdB/°C
V
TEMP
INCM
IN
IN
+
–
V
V
Input Common Mode Voltage Range
Input Voltage Range at –1dBFS
(IN + IN )/2
1.0–1.6
LTM9001-AA at 162.5MHz
LTM9001-BA at 140MHz
233
820
mV
mV
P-P
P-P
9001fa
2
LTM9001
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
INDIFF
Differential Input Impedance
LTM9001-AA
LTM9001-BA
200
400
Ω
Ω
C
V
Differential Input Capacitance
Offset Error (Note 6)
Includes Parasitic
1
pF
INDIFF
OS
l
l
Including Amplifier and ADC (LTM9001-AA)
Including Amplifier and ADC (LTM9001-BA)
–8
–20
–3.2
–10
–0.5
–0.5
mV
mV
Offset Drift
Including Amplifier and ADC
10
μV/°C
Full-Scale Drift
Internal Reference
External Reference
30
15
ppm/°C
ppm/°C
CMRR
Common Mode Rejection Ratio
60
dB
μA
μA
μA
ns
l
I
I
I
t
t
SENSE Input Leakage Current
0V < SENSE < V
–3
3
SENSE
MODE
LVDS
AP
DD
MODE Pin Pull-Down Current to GND
LVDS Pin Pull-Down Current to GND
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Time Jitter
10
10
1
70
fs
RMS
JITTER
CONVERTER CHARACTERISTICS The l indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
Resolution (No Missing Codes)
Integral Linearity Error
16
Bits
l
l
Differential Input LTM9001-AA (Notes 5, 7)
Differential Input LTM9001-BA (Notes 5, 7)
2.4
8
10
LSB
LSB
l
Differential Linearity Error
Transition Noise
Differential Input (Notes 5, 7)
External Reference
0.3
1
1
LSB
LSB
RMS
DYNAMIC ACCURACY The l indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SNR
Signal-to-Noise Ratio
162.5MHz Input (PGA = 0) LTM9001-AA
162.5MHz Input (PGA = 1) LTM9001-AA
72
dBFS
dBFS
l
l
67.2
67
68.5
140MHz Input (PGA = 0) LTM9001-BA
140MHz Input (PGA = 1) LTM9001-BA
69.2
67.2
dBFS
dBFS
SFDR
SFDR
Spurious Free Dynamic Range, 2nd or 3rd
Harmonic
162.5MHz Input (PGA = 0) LTM9001-AA
162.5MHz Input (PGA = 1) LTM9001-AA
78
82
dBc
dBc
l
l
72
64
140MHz Input (PGA = 0) LTM9001-BA
140MHz Input (PGA = 1) LTM9001-BA
72
82
dBc
dBc
Spurious Free Dynamic Range 4th or Higher
162.5MHz Input (PGA = 0) LTM9001-AA
162.5MHz Input (PGA = 1) LTM9001-AA
95
95
dBc
dBc
l
l
86
86
140MHz Input (PGA = 0) LTM9001-BA
140MHz Input (PGA = 1) LTM9001-BA
95
104
dBc
dBc
9001fa
3
LTM9001
DYNAMIC ACCURACY The l indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
162.5MHz Input (PGA = 0) LTM9001-AA
162.5MHz Input (PGA = 1) LTM9001-AA
71.4
68
dBFS
dBFS
l
l
67
64
140MHz Input (PGA = 0) LTM9001-BA
140MHz Input (PGA = 1) LTM9001-BA
67.5
66.4
dBFS
dBFS
SFDR
SFDR
Spurious Free Dynamic Range at –25dBFS,
Dither “OFF”
162.5MHz Input (PGA = 0) LTM9001-AA
162.5MHz Input (PGA = 1) LTM9001-AA
90
93
dBFS
dBFS
Spurious Free Dynamic Range at –15dBFS,
Dither “OFF”
140MHz Input (PGA = 0) LTM9001-BA
140MHz Input (PGA = 1) LTM9001-BA
91
92
dBFS
dBFS
Spurious Free Dynamic Range at –25dBFS,
Dither “ON”
162.5MHz Input (PGA = 0) LTM9001-AA
162.5MHz Input (PGA = 1) LTM9001-AA
95
100
dBFS
dBFS
l
l
90
90
Spurious Free Dynamic Range at –15dBFS,
Dither “ON”
140MHz Input (PGA = 0) LTM9001-BA
140MHz Input (PGA = 1) LTM9001-BA
95
96
dBFS
dBFS
IMD
Third Order Intermodulation Distortion;
1MHz Tone Spacing, 2 Tones at –7dBFS
f
IN
f
IN
= 162.5MHz LTM9001-AA
= 140MHz LTM9001-BA
–78
–84
dB
dB
3
IIP
3
Equivalent Third Order Input Intercept Point,
2 Tone
f
IN
f
IN
= 162.5MHz LTM9001-AA
= 140MHz LTM9001-BA
24
29.2
dBm
dBm
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
Encode Inputs (ENC , ENC )
l
V
V
Differential Input Voltage
0.2
1.2
V
ID
Common Mode Input Voltage
Internally Set
Externally Set
1.6
V
V
ICM
3.1
R
Input Resistance
Input Capacitance
100
3
Ω
IN
C
(Note 7)
pF
IN
Logic Inputs (DITH, PGA, ADCSHDN, RAND)
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 3.3V
= 3.3V
2
2
V
V
IH
IL
DD
DD
IN
0.8
10
I
= 0V to V
μA
pF
IN
DD
C
Input Capacitance
(Note 7)
1.5
IN
Logic Inputs (AMPSHDN)
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input High Current
V
V
V
V
= 3.3V
= 3.3V
= 2V
V
V
IH
IL
CC
CC
IN
0.8
I
IH
I
IL
1.3
0.1
1.5
μA
μA
pF
Input Low Current
= 0.8V
IN
C
Input Capacitance
(Note 7)
IN
Logic Outputs (CMOS Mode)
OV = 3.3V
DD
V
High Level Output Voltage
V
V
= 3.3V, I = –10μA
3.299
3.29
V
V
OH
DD
DD
O
= 3.3V, I = –200μA
l
l
3.1
O
V
Low Level Output Voltage
V
DD
V
DD
= 3.3V, I = 10μA
0.01
0.1
V
V
OL
O
= 3.3V, I = 1.6mA
0.4
O
9001fa
4
LTM9001
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
–50
50
MAX
UNITS
mA
I
Output Source Current
Output Sink Current
V
= 0V
SOURCE
SINK
OUT
OUT
I
V
= 3.3V
mA
OV = 2.5V
DD
V
High Level Output Voltage
Low Level Output Voltage
V
V
= 3.3V, I = –200μA
2.49
0.1
V
V
OH
OL
DD
O
V
= 3.3V, I = 1.6mA
DD
O
OV = 1.8V
DD
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
V
V
= 3.3V, I = –200μA
1.79
0.1
V
V
DD
O
= 3.3V, I = 1.6μA
DD
O
Logic Outputs (LVDS Mode)
Standard LVDS
l
l
V
Differential Output Voltage
100Ω Differential Load
100Ω Differential Load
247
350
1.2
454
mV
V
OD
OS
V
Output Common Mode Voltage
1.125
1.375
Low Power LVDS
l
l
V
Differential Output Voltage
100Ω Differential Load
100Ω Differential Load
125
175
1.2
250
mV
V
OD
OS
V
Output Common Mode Voltage
1.125
1.375
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
3.135
2.85
TYP
MAX
3.465
3.5
UNITS
V
l
l
V
DD
V
CC
ADC Analog Supply Voltage
Amplifier Supply Voltage
Amplifier Supply Current
Total Shutdown Power
(Note 9)
3.3
V
I
CC
100
10
136
mA
mW
P
AMPSHDN = ADCSHDN = 3.3V
(Note 9)
SHDN
Standard LVDS Output Mode
l
OV
Output Supply Voltage
Analog Supply Current
3
3
3.3
3.6
V
DD
l
l
I
LTM9001-AA
LTM9001-BA
400
465
500
550
mA
mA
VDD
l
I
Output Supply Current
Power Dissipation
74
90
mA
OVDD
l
l
P
DISS
LTM9001-AA
LTM9001-BA
1564
1779
1947
2112
mW
mW
Low Power LVDS Output Mode
l
OV
DD
Output Supply Voltage
Analog Supply Current
(Note 9)
3.3
3.6
V
l
l
I
LTM9001-AA
LTM9001-BA
400
465
500
550
mA
mA
VDD
l
I
Output Supply Current
Power Dissipation
41
50
mA
OVDD
l
l
P
LTM9001-AA
LTM9001-BA
1455
1670
1815
1980
mW
mW
DISS
CMOS Output Mode
OV
l
Output Supply Voltage
Analog Supply Current
(Note 9)
0.5
3.6
V
DD
l
l
I
LTM9001-AA
LTM9001-BA
380
460
450
530
mA
mA
VDD
9001fa
5
LTM9001
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
P
ADC Power Dissipation
LTM9001-AA
LTM9001-BA
1320
1584
1650
1914
mW
mW
DISS
P
Total Power Dissipation
LTM9001-AA
LTM9001-BA
1650
1914
mW
mW
DISS(TOTAL)
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
f
Sampling Frequency (Note 9)
LTM9001-AA
LTM9001-BA
1
1
130
160
MHz
MHz
S
l
l
l
l
t
ENC Low Time (Note 7)
ENC High Time (Note 7)
Duty Cycle Stabilizer Off (LTM9001-AA)
Duty Cycle Stabilizer Off (LTM9001-BA)
Duty Cycle Stabilizer On (LTM9001-AA)
Duty Cycle Stabilizer On (LTM9001-BA)
3.65
2.97
2.6
3.846
3.125
3.846
3.125
1000
1000
1000
1000
ns
ns
ns
ns
L
2.1
l
l
l
l
t
Duty Cycle Stabilizer Off (LTM9001-AA)
Duty Cycle Stabilizer Off (LTM9001-BA)
Duty Cycle Stabilizer On (LTM9001-AA)
Duty Cycle Stabilizer On (LTM9001-BA)
3.65
2.97
2.6
3.846
3.125
3.846
3.125
1000
1000
1000
1000
ns
ns
ns
ns
H
2.1
LVDS Output Mode (Standard and Low Power)
l
l
l
t
t
t
t
t
ENC to DATA Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Output Rise Time
Output Fall Time
(Note 7)
(Note 7)
1.3
1.3
2.7
2.7
4.3
0.5
0.5
7
4
4
ns
ns
D
C
(t – t ) (Note 7)
10
ns
SKEW
RISE
FALL
C
D
ns
ns
Data Latency
Cycles
CMOS Output Mode
l
l
l
t
t
t
ENC to DATA Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Data Latency
(Note 7)
(Note 7)
1.3
1.3
2.7
2.7
4.3
4
4
ns
ns
ns
D
C
(t – t ) (Note 7)
10
SKEW
C
D
Full Rate CMOS
Demuxed
7
7
Cycles
Cycles
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: Integral nonlinearity is defined as the deviation of a code from
a “best fit straight line” to the transfer curve. The deviation is measured
from the center of the quantization band.
Note 6: Offset error is the voltage applied between the IN and IN pins
required to make the output code flicker between 0000 0000 0000 0000
and 1111 1111 1111 1111.
+
–
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
+
–
Note 3: Gain is measured from IN /IN through the ADC. The amplifier
provides approximately 20dB of gain and the filter has 1dB loss
(LTM9001-AA).
Note 7: Guaranteed by design, not subject to test.
Note 8: Amplifier dynamic performance tests are done from IN /IN
+
–
through the DNC pins without using the ADC.
Note 4: V = V = 3.3V, f
differential ENC /ENC = 2V with 1.6V common mode, input range =
= maximum sample frequency,
CC
DD
+
SAMPLE
Note 9: Recommended operating conditions.
–
P-P
–1dBFS with PGA = 0 with differential drive, AC-coupled inputs, unless
otherwise noted.
9001fa
6
LTM9001
TIMING DIAGRAM
LVDS Output Mode Timing
All Outputs are Differential and Have LVDS Levels
t
AP
N + 1
N + 4
ANALOG
INPUT
N + 3
N
N + 2
t
H
t
L
–
ENC
+
ENC
t
D
N – 7
N – 6
N – 5
N – 4
N – 3
D0-D15, OF
t
C
+
CLKOUT
9001 TD01
–
CLKOUT
Full-Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
t
AP
N + 1
N + 4
ANALOG
INPUT
N + 3
N
N + 2
t
H
t
L
–
ENC
+
ENC
t
D
N – 7
N – 6
N – 5
N – 4
N – 3
DA0-DA15, OFA
t
C
CLKOUTA
CLKOUTB
HIGH IMPEDANCE
DB0-DB15, OFB
9001 TD02
9001fa
7
LTM9001
TIMING DIAGRAM
Demultiplexed CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
t
AP
N + 1
N + 4
ANALOG
INPUT
N + 3
N
N + 2
t
H
t
L
–
ENC
+
ENC
t
t
D
D
N – 8
N – 6
N – 4
DA0-DA15, OFA
DB0-DB15, OFB
N – 7
N – 5
N – 3
t
C
CLKOUTA
CLKOUTB
9001 TD03
9001fa
8
LTM9001
(LTM9001-AA)
TYPICAL PERFORMANCE CHARACTERISTICS
Shorted Inputs Histogram with
130k Samples
IF Frequency Response
Input Impedance vs Frequency
250
200
150
100
50
0
0
–2
–4
9000
8000
7000
6000
5000
4000
3000
2000
MAGNITUDE
PHASE
–45
–90
–6
–8
1000
0
–10
10
100
1000
160
33524
33504
ADC OUTPUT CODE
120 130 140 150
170 180 190 200
33484
33544
FREQUENCY (MHz)
FREQUENCY (MHz)
9001 G02
9001 G01
9001 G03
Best Fit Integral Non-Linearity
(INL) vs Output Code
Differential Non-Linearity (DNL)
vs Output Code
64k Point FFT, FIN = 162.4MHz,
–1dBFS, PGA = 0
0
–20
5
4
0.5
0.4
0.3
0.2
0.1
0
3
2
–40
1
–60
0
–1
–2
–0.1
–0.2
HD3
HD2
–80
–3
–4
–5
–0.3
–0.4
–0.5
–100
–120
65536
6553
0
16384
32768
49152
0
16384
32768
49152
0
4096
12288
20480
28672
ADC OUTPUT CODE
ADC OUTPUT CODE
FFT BIN NUMBER (32k TOTAL)
9001 G04
9001 G05
9001 G06
64k Point FFT, FIN = 162.4MHz,
–1dBFS, PGA = 1
64k Point 2-Tone FFT, FIN = 161.5MHz,
and 163.5MHz, –7dBFS, PGA = 0
0
–20
0
–20
–40
–40
–60
–60
HD3
HD2
–80
–80
–100
–120
–100
–120
0
4096
12288
20480
28672
0
4096
12288
20480
28672
FFT BIN NUMBER (32k TOTAL)
FFT BIN NUMBER (32k TOTAL)
9001 G07
9001 G08
9001fa
9
LTM9001
(LTM9001-AA)
TYPICAL PERFORMANCE CHARACTERISTICS
64k Point FFT, FIN = 162.4MHz,
–15dBFS, PGA = 0, Dither “Off”
64k Point FFT, FIN = 162.4MHz,
–15dBFS, PGA = 0, Dither “On”
64k Point 2-Tone FFT, FIN = 161.5MHz,
and 163.5MHz, –15dBFS, PGA = 0
0
–20
0
–20
0
–20
–40
–40
–40
–60
–60
–60
–80
–80
–80
–100
–100
–120
–100
–120
–120
0
4096
12288
20480
28672
0
4096
12288
20480
28672
0
4096
12288
20480
28672
FFT BIN NUMBER (32k TOTAL)
FFT BIN NUMBER (32k TOTAL)
FFT BIN NUMBER (32k TOTAL)
9001 G09
9001 G10
9001 G11
SFDR vs Input Level, FIN = 162.4MHz,
PGA = 0, Dither = “On”
SFDR and SNR vs Sample Rate,
FIN = 162.4MHz, –1dBFS, PGA = 0
SFDR vs Input Level, FIN = 162.4MHz,
PGA = 0, Dither = “Off”
140
120
100
80
140
120
100
80
84
80
76
SFDR dBc
SFDR dBFS
SNR
SFDR
SFDR dBc
SFDR dBFS
60
60
72
68
64
40
20
0
40
20
0
200
ADC SAMPLE RATE (Msps)
0
50
100
150
250
–50
–50
–90 –80 –70 –60
–40 –30 –20 –10
0
–90 –80 –70 –60
–40 –30 –20 –10
0
INPUT LEVEL (dBFS)
INPUT LEVEL (dBFS)
9001 G14
9001 G13
9001 G12
SFDR vs VCC Supply Voltage,
FIN = 162.4MHz, –1dBFS,
PGA = 0
SFDR vs Input Common-Mode Voltage,
FIN = 162.4MHz, –1dBFS, PGA = 0
81.0
80.5
80.0
79.5
79.0
78.5
78.0
77.5
77.0
76.5
76.0
75.5
90
85
80
75
70
65
60
3.2 3.3 3.4
INPUT COMMON-MODE VOLTAGE (V)
2.8
2.9 3.0 3.1
3.5
2.5
INPUT COMMON-MODE VOLTAGE (V)
0.5
1.0
1.5
2.0
3.0
9001 G16
9001 G15
9001fa
10
LTM9001
(LTM9001-BA)
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Non-Linearity (DNL)
vs Output Code
Best Fit Integral Non-Linearity
(INL) vs Output Code
SNR vs Frequency
1.0
0.8
4.0
3.5
71
69
67
65
63
61
59
57
55
53
51
3.0
2.5
0.6
2.0
0.4
1.5
1.0
0.2
0.5
0.0
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
49152
65536
0
16384
32768
49152
65536
1
10
100
1000
OUTPUT CODE
IF FREQUENCY (MHz)
OUTPUT CODE
9001 G19
9001 G17
9001 G18
Input Impedance vs Frequency
IF Frequency Response
400
350
300
250
200
150
100
50
0
0
MAGNITUDE
–5
–10
–15
–20
–25
–30
–8
PHASE
–16
–24
–32
0
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
IF FREQUENCY (MHz)
9001 G20
9001 G21
64k Point FFT, fIN = 140MHz,
–1dBFS, PGA = 0, RAND “Off”,
Dither “Off”
64k Point FFT, fIN = 250MHz,
–1dBFS, PGA = 0, RAND “Off”,
Dither “Off”
64k Point 2-Tone FFT, fIN = 136MHz,
–7dBFS Per Tone, PGA = 0, RAND
“Off”, Dither “Off”
0
–10
0
–10
0
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
HD3
–50
–50
–50
–60
–60
–60
HD2
–70
–70
–70
HD3
HD2
40
–80
–80
–80
–90
–90
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
10 20 30 40 50 60 70 80
0
10
20
30
40
50
60
0
10
20
30
50
60
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
9001 G23
9001 G24
9001 G22
9001fa
11
LTM9001
PIN FUNCTIONS
Supply Pins
AMPSHDN (Pin H3): Power Shutdown Pin for Amplifier.
This pin is a logic input referenced to analog ground.
AMPSHDN = low results in normal operation. AMPSHDN
= high results in powered down amplifier with typically
3mA amplifier supply current.
V
(Pins E1, E2): 3.3V Analog Supply Pin for Amplifier.
CC
The voltage on this pin provides power for the amplifier
stage only and is internally bypassed to GND.
V
(Pins E5, D5): 3.3V Analog Supply Pin for ADC. This
DD
MODE (Pin G3): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
supply is internally bypassed to GND.
OV (Pins A6, G9): Positive Supply for the ADC Output
DD
Drivers. This supply is internally bypassed to OGND.
cyclestabilizer. ConnectingMODEto1/3V selectsoffset
DD
binary output format and enables the clock duty cycle sta-
GND(PinsA1,A2,A4,B2,B4,C2,C4,D1,D2,D4,E4,F1,
F2, F4, G2, G4, H2, H4, J1, J2, J4): Analog Ground.
bilizer.ConnectingMODEto2/3V selects2’scomplement
DD
output format and enables the clock duty cycle stabilizer.
OGND (Pins A5, A9, G8, J9): ADC Output Driver Ground.
Connecting MODE to V selects 2’s complement output
DD
format and disables the clock duty cycle stabilizer.
Analog Inputs
RAND (Pin F3): Digital Output Randomization Selection
Pin. RAND = low results in normal operation. RAND =
high selects D1 to D15 to be EXCLUSIVE-ORed with D0
(the LSB). The output can be decoded by again applying
an XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.
+
IN (Pin G1): Positive (Non-Inverting) Amplifier Input.
–
IN (Pin H1): Negative (Inverting) Amplifier Input.
DNC (Pins C3, D3): Do Not Connect. These pins are used
for testing and should not be connected on the PCB. They
may be soldered to unconnected pads and should be well
isolated. The DNC pins connect to the signal path prior to
the ADC inputs; therefore, care should be taken to keep
other signals away from these sensitive nodes.
PGA (Pin E3): Programmable Gain Amplifier Control Pin.
PGA = low selects the normal (maximum) input voltage
range. PGA = high selects a 3.5dB reduced input range
for slightly better distortion performance at the expense
of SNR.
+
ENC (Pin C1): Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC .
This input is internally biased to 1.6V through a 6.2k
resistor. Output data can be latched on the rising edge
of ENC . The Encode pins have a differential 100Ω input
impedance.
+
ADCSHDN (Pin B3): Power Shutdown Pin for ADC.
ADCSHDN = low results in normal operation. ADCSHDN
= high results in powered down analog circuitry and the
digital outputs are placed in a high impedance state.
+
–
ENC (Pin B1): Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC .
Thisinputisinternallybiasedto1.6Vthrougha6.2kresistor.
Bypasstogroundwitha0.1μFcapacitorforasingle-ended
Encode signal. The Encode pins have a differential 100Ω
input impedance.
–
DITH (Pin A3): Internal Dither Enable Pin. DITH = low
disablesinternaldither.DITH=highenablesinternaldither.
RefertoInternalDithersectionofthisdatasheetfordetails
on dither operation.
LVDS (Pin F5): Data Output Mode Select Pin. Connecting
LVDSto0VselectsfullrateCMOSmode.ConnectingLVDS
Control Inputs
to1/3V selectsdemultiplexedCMOSmode. Connecting
DD
SENSE (Pin J3): Reference Mode Select and External
Reference Input. Tie SENSE to V to select the internal
2.5V bandgap reference. An external reference of 2.5V
or 1.25V may be used; both reference values will set the
maximum full scale input range.
LVDS to 2/3V selects Low Power LVDS mode. Connect-
DD
ing LVDS to V selects Standard LVDS mode.
DD
DD
9001fa
12
LTM9001
PIN FUNCTIONS
Digital Outputs
CLKOUTB(PinE7):DataValidOutput.CLKOUTBwilltoggle
at the sample rate in full rate CMOS mode or at 1/2 the
sample rate in demultiplexed mode. Latch the data on the
falling edge of CLKOUTB.
For CMOS Mode, Full Rate or Demultiplexed
DA0 to DA15 (Pins E9 to H5): Digital Outputs, A Bus.
DA15 is the MSB. Output bus for full rate CMOS mode
and demultiplexed mode.
OFA (Pin G5): Over/Under Flow Digital Output for the A
Bus. OFA is high when an over or under flow has occurred
on the A bus.
CLKOUTA (Pin E8): Inverted Data Valid Output. CLKOUTA
will toggle at the sample rate in full rate CMOS mode or
at 1/2 the sample rate in demultiplexed mode. Latch the
data on the rising edge of CLKOUTA.
For LVDS Mode, STANDARD or LOW POWER
–
+
–
+
D0 /D0 to D15 /D15 (Pins B5 to G6): LVDS Digital Out-
puts.AllLVDSoutputsrequiredifferential100Ωtermination
resistors at the LVDS receiver. D15 /D15 is the MSB.
OFB (Pin E6): Over/Under Flow Digital Output for the B
Bus. OFB is high when an over or under flow has occurred
on the B bus. OFB is in a high impedance state in full rate
CMOS mode.
+
–
–
+
CLKOUT /CLKOUT (PinsE6,E7):LVDSDataValidOutput.
+
Latch data on the rising edge of CLKOUT , falling edge
of CLKOUT .
–
DB0toDB15(PinsB5toD9):DigitalOutputs,BBus.DB15
is the MSB. Active in demultiplexed mode. The B bus is in
a high impedance state in full rate CMOS mode.
–
+
OF /OF (Pins H5, G5): Over/Under Flow Digital Output.
OF is high when an over or under flow has occurred.
Pin Configuration (LVDS Outputs/CMOS Outputs)
1
2
3
SENSE
AMPSHDN
MODE
RAND
PGA
4
5
6
7
8
9
+
–
+
–
J
H
G
F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D14 /DA12
D14 /DA11
D12 /DA8
D12 /DA7
OGND
–
–
–
–
–
+
IN
OF /DA15
D15 /DA13
D13 /DA9
D11 /DA5
D11 /DA6
+
+
+
+
IN
OF /OFA
D15 /DA14
D13 /DA10
OGND
OV
DD
–
+
–
+
GND
LVDS
D9 /DA1
D9 /DA2
D10 /DA3
D10 /DA4
–
+
–
+
E
V
CC
V
V
CLKOUT /OFB CLKOUT /CLKOUTB D8 /CLKOUTA
D8 /DA0
CC
DD
DD
–
+
–
+
D
C
B
A
GND
GND
GND
GND
GND
DNC
V
D6 /DB12
D6 /DB13
D7 /DB14
D7 /DB15
+
+
–
+
–
+
ENC
ENC
DNC
D0 /DB1
D4 /DB8
D4 /DB9
D5 /DB10
D5 /DB11
–
–
–
+
+
–
ADCSHDN
DITH
D0 /DB0
D1 /DB2
D1 /DB3
D3 /DB7
D3 /DB6
–
GND
OGND
OV
D2 /DB4
D2+/DB5
OGND
DD
9001fa
13
LTM9001
PIN FUNCTIONS
Top View of LGA Pinout (Looking Through Component)
ALL ELSE
= GND
TOP VIEW
DATA
CONTROL
1
2
3
4
5
6
7
8
9
J
OGND
–
IN
IN
H
G
F
+
OV
DD
E
V
CC
D
C
B
A
DNC
+
ENC
–
ENC
OGND
9001 LGA01
CONTROL
V
OGND OV
DD DD
9001fa
14
LTM9001
FUNCTIONAL BLOCK DIAGRAM
9001fa
15
LTM9001
OPERATION
DYNAMIC PERFORMANCE DEFINITIONS
distortion products at the sum and difference frequencies
of mfa nfb, where m and n = 0, 1, 2, 3, etc.
Signal-to-Noise Plus Distortion Ratio
For example, the 3rd order IMD terms include (2fa + fb),
(fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is
defined as the ration of the RMS value of either input tone
to the RMS value of the largest 3rd order IMD product.
The signal-to-noise plus distortion ratio [S/(N+D)] is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the ADC output.
Spurious Free Dynamic Range (SFDR)
Signal-to-Noise Ratio
The ratio of the RMS input signal amplitude to the RMS
value of the peak spurious spectral component expressed
in dBc. SFDR may also be calculated relative to full scale
and expressed in dBFS.
The signal-to-noise (SNR) is the ratio between the RMS
amplitudeofthefundamentalinputfrequencyandtheRMS
amplitude of all other frequency components, except the
first five harmonics.
Aperture Delay Time
Total Harmonic Distortion
+
Aperture Delay is the time from when a rising ENC equals
–
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
the ENC voltage to the instant that the input signal is held
by the sample and-hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
⎛
⎞
THD= –20Log (V22 + V32 + V42 +...Vn2)/V1
⎝
⎠
where V1 is the RMS amplitude of the fundamental
frequency and V2 through Vn are the amplitudes of the
second through nth harmonics.
SNR
= –20log (2π • f • t
)
JITTER
IN JITTER
DESCRIPTION
Intermodulation Distortion
The LTM9001 is an integrated System in a Package (SiP)
μModule™ receiver that includes a high-speed, sampling
16-bitA/Dconverter, matchingnetwork, anti-aliasingfilter
and a low noise, differential amplifier with fixed gain. It
is designed for digitizing high frequency, wide dynamic
range signals with an Intermediate Frequency (IF) range
up to 300MHz.
If the input signal consists of more than one spectral
component,thetransferfunctionnonlinearitycanproduce
intermodulationdistortion(IMD)inadditiontoTHD.IMDis
the change in one sinusoidal input caused by the presence
of another sinusoidal input at a different frequency.
If two pure sine waves of frequencies fa and fb are applied
totheinput,nonlinearitiesinthetransferfunctioncancreate
μModule is a trademark of Linear Technology Corporation.
9001fa
16
LTM9001
OPERATION
The following sections describe in further detail the func-
tionaloperationoftheLTM9001.TheSiPtechnologyallows
the LTM9001 to be customized and this is described in
the first section. The remaining outline follows the basic
functional elements as shown in Figure 1.
However, other options are possible through Linear
Technology’s semi-custom development program. Linear
Technology has in place a program to deliver other speed,
resolution, IF range, gain and filter configurations for a
widerangeofapplications.SeeTable1fortheLTM9001-AA
configuration and potential options. These semi-custom
designs are based on existing ADCs and amplifiers with
an appropriately modified matching network. The final
subsystem is then tested to the exact parameters defined
for the application. The final result is a fully integrated,
accurately tested and reliable solution. For more details
onthesemi-customreceiversubsystemprogram,contact
Linear Technology.
ADC
AMPLIFIER
INPUT
ADC
NETWORK
9001 F01
Figure 1. Basic Functional Elements
Note that not all combinations of options in Table 1 are
possible at this time and specified performance may differ
significantly from existing values.
SEMI-CUSTOM OPTIONS
The μModule construction affords a new level of flexibility
in application-specific standard products. Standard ADC
and amplifier components can be integrated regardless
of their process technology and matched with passive
components to a particular application. The LTM9001-AA,
as the first example, is configured with a 16-bit ADC sam-
pling at rates up to 130Msps. The amplifier gain is 20dB
with an input impedance of 200Ω and an input range of
AMPLIFIER INFORMATION
The amplifiers used in the LTM9001 are low noise and low
distortion fully differential ADC drivers. The amplifiers are
very flexible in terms of I/O coupling. They can be AC- or
DC-coupled at the inputs. Users are advised to keep the
input common mode voltage between 1V and 1.6V for
proper operation. If the inputs are AC-coupled, the input
common mode voltage is automatically biased. The input
signalcanbeeithersingle-endedordifferentialwithalmost
no difference in distortion performance.
250mV . The matching network is designed to optimize
P-P
the interface between the amplifier output and the ADC
undertheseconditions.Additionally,thereisa2-poleband
pass filter designed for 162.5MHz 25MHz.
Table 1. Semi-Custom Options
AMPLIFIER IF
RANGE
AMPLIFIER INPUT
IMPEDANCE
AMPLIFIER GAIN
FILTER
ADC SAMPLE
RATE
ADC
RESOLUTION
PART NUMBER
300MHz
300MHz
200Ω
400Ω
14dB
8dB
162.5MHz BPF, 50MHz BW
DC-300MHz LPF
130Msps
160Msps
16-bit
16-bit
LTM9001-AA
LTM9001-BA
Select Combination of Options from Columns Below
DC-300MHz
DC-140MHz
DC-70MHz
DC-35MHz
50Ω
200Ω
200Ω
400Ω
200Ω
26dB
20dB
14dB
8dB
LPF TBD
BPF TBD
160Msps
130Msps
105Msps
80Msps
65Msps
40Msps
25Msps
10Msps
16-bit
14-bit
6dB
9001fa
17
LTM9001
OPERATION
ADC INPUT NETWORK
CONVERTER INFORMATION
The passive network between the amplifier output stage
and the ADC input stage can be configured for bandpass
or low-pass response with different cut-off frequencies
and bandwidths. The LTM9001-AA, for example, imple-
ments a 2-pole band-pass filter centered at 162.5MHz
with 50MHz bandwidth. Note that the filter attenuates the
signal at 162.5MHz by 1dB, making the overall gain of the
subsystem 19dB.
Theanalog-to-digitalconverter(ADC)isaCMOSpipelined
multistep converter with a front-end PGA. As shown in the
FunctionalBlockDiagram, theconverterhasfivepipelined
ADCstages;asampledanaloginputwillresultinadigitized
value seven cycles later (see the Timing Diagram section).
The encode input is differential for improved common
mode noise immunity.
For production test purposes the filter is designed to allow
DC inputs into the ADC.
APPLICATIONS INFORMATION
INPUT SPAN
LTM9001
The LTM9001 is configured with a fixed input span and
inputimpedance.WiththeamplifiergainandtheADCinput
network described above for LTM9001-AA, the full-scale
Z
/2
R
F
IN
25Ω
+
IN
input range of the driver circuit is 250mV . The recom-
P-P
V
IN
+
mended ADC input span is achieved by tying the SENSE
R
T
–
pin to V . However, the ADC input span can be changed
DD
by applying a DC voltage to the SENSE pin.
R
F
25Ω
–
Z /2
IN
IN
Input Impedance and Matching
9001 F02
The differential input impedance of the LTM9001 can be
50Ω, 200Ω or 400Ω. In some applications the differential
inputs may need to be terminated to a lower value imped-
ance, e.g. 50Ω, in order to provide an impedance match
for the source. Several choices are available.
Figure 2. Input Termination for Differential 50Ω Input Impedance
Using Shunt Resistor (See Table 2 for RT Values)
LTM9001
+
IN
R
F
25Ω
Z /2
IN
One approach is to use a differential shunt resistor
(Figure 2). Another approach is to employ a wide band
transformer(Figure3). Bothmethodsprovideawideband
match. The termination resistor or the transformer must
be placed close to the input pins in order to minimize the
reflection due to input mismatch.
• •
V
IN
+
–
R
25Ω
Z /2
IN
–
IN
F
Table 2. Differential Amplifier Input Termination Values
Z
IN
R FIG 2
T
9001 F03
400ꢁ
200ꢁ
50ꢁ
57ꢁ
66.5ꢁ
None
Figure 3. Input Termination for Differential 50Ω
Input Impedance Using a Wideband Transformer
9001fa
18
LTM9001
APPLICATIONS INFORMATION
Alternatively, one could apply a narrowband impedance
match at the inputs for frequency selection and/or noise
reduction.
R
LTM9001
S
0.1μF
R
50Ω
+
IN
Z /2
IN
F
V
IN
+
–
R
T
Referring to Figure 4, amplifier inputs can be easily con-
figured for single-ended input without a balun. The signal
is fed to one of the inputs through a matching network
while the other input is connected to the same imped-
ance. In general, the single-ended input impedance and
0.1μF
0.1μF
R /R
S
R
T
Z
/2
–
IN
F
IN
terminationresistorR aredeterminedbythecombination
T
9001 F04
of R , Z /2 and R .
S
IN
F
Figure 4. Input Termination for Differential
50Ω Input Impedance Using Shunt Resistor
Table 3. Single-Ended Amplifier Input Termination Values
Z
IN
R FIG 4
T
400ꢁ
200ꢁ
50ꢁ
59ꢁ
68.5ꢁ
150ꢁ
LTM9001
Z
/2
R
F
IN
R /2
s
+
IN
The LTM9001 amplifier is stable with all source imped-
ances.Theoveralldifferentialgainisaffectedbythesource
impedance in Figure 5:
V
IN
+
R
T
–
A = | V /V | = (1000/(R + Z /2))
V
OUT IN
S
IN
R
R /2
s
–
Z /2
IN
Thenoiseperformanceoftheamplifieralsodependsupon
the source impedance and termination. For example, an
input 1:4 transformer in Figure 3 improves the input noise
figure by adding 6dB voltage gain at the inputs.
F
IN
9001 F05
Figure 5. Calculate Differential Gain
Reference and SENSE Pin Operation
Figure6showstheconverterreferencecircuitryconsisting
of a 2.5V bandgap reference, a programmable gain ampli-
fier and control circuit. There are three modes of reference
operation: Internal Reference, 1.25V external reference
or 2.5V external reference. To use the internal reference,
tie the SENSE pin to V . To use an external reference,
DD
simplyapplyeithera1.25Vor2.5Vreferencevoltagetothe
SENSE input pin. Both 1.25V and 2.5V applied to SENSE
will result in the maximum full scale range.
RANGE
SELECT
AND GAIN
CONTROL
TIE TO V TO USE
DD
INTERNAL
ADC
INTERNAL 2.5V
REFERENCE
REFERENCE
OR INPUT FOR
EXTERNAL 2.5V
REFERENCE
OR INPUT FOR
EXTERNAL 1.25V
REFERENCE
SENSE
PGA
2.5V
BANDGAP
REFERENCE
9001 F06
Figure 6. Reference Circuit
9001fa
19
LTM9001
APPLICATIONS INFORMATION
PGA Pin
3. If the ADC is clocked with a fixed frequency sinusoidal
signal, filter the encode signal to reduce wideband
noise.
The PGA pin selects between two gain settings for the
ADC front-end. PGA = low selects the maximum input
span; PGA = high selects a 3.5dB lower input span. The
high input range has the best SNR. For applications with
high linearity requirements, the low input range will have
improveddistortion;however,theSNRwillbe1.8dBworse.
See the Typical Performance Characteristics section.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.2V
to V . Each input may be driven from ground to V for
DD
DD
single-ended drive.
Driving the Encode Inputs
The encode clock inputs have a differential 100Ω input
impedance. For 50Ω inputs e.g. signal generators, an
additional 100Ω impedance will provide an impedance
match, as shown in Figure 7b.
The noise performance of the converter can depend on
the encode signal quality as much as the analog input.
The encode inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point
fortransformercoupleddrivecircuitsandcansetthelogic
threshold for single-ended drive circuits.
Maximum and Minimum Encode Rates
ThemaximumencoderatefortheLTM9001-AAis130Msps
and 160Msps for LTM9001-BA. For the ADC to operate
properly the encode signal should have a 50% ( 5%)
duty cycle. Each half cycle must have at least 3.65ns
(LTM9001-AA, or 2.97ns for LTM9001-BA) for the ADC
internal circuitry to have enough settling time for proper
operation. Achieving a precise 50% duty cycle is easy with
differential sinusoidal drive using a transformer or using
symmetric differential logic such as PECL or LVDS. When
usingasingle-endedencodesignalasymmetricriseandfall
times can result in duty cycles that are far from 50%.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter. In applications where jitter
is critical (high input frequencies), take the following into
consideration:
1. Differential drive should be used.
2. Usethelargestamplitudepossible.Ifusingtransformer
coupling, use a higher turns ratio to increase the am-
plitude.
LTM9001
V
DD
TO INTERNAL
ADC CLOCK
DRIVERS
LTM9001
0.1μF
0.1μF
+
ENC
1.6V
6k
V
DD
50Ω
50Ω
T1
100Ω
+
ENC
8.2pF
1.6V
6k
V
100Ω
DD
–
0.1μF
ENC
–
ENC
9001 F07b
T1 = M/A-COM ETC1-1-13
9001 F07a
Figure 7b. Transformer Driven Encode
Figure 7a. Equivalent Encode Input Circuit
9001fa
20
LTM9001
APPLICATIONS INFORMATION
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
DIGITAL OUTPUTS
Digital Output Modes
The LTM9001 can operate in four digital output modes:
standard LVDS, low power LVDS, full rate CMOS, and
demultiplexed CMOS. The LVDS pin selects the mode of
operation. This pin has a four level logic input, centered at
0, 1/3V , 2/3V and V . An external resistive divider
DD
DD
DD
can be used to set the 1/3V and 2/3V logic levels.
DD
DD
Table 4 shows the logic states for the LVDS pin.
Table 4. LVDS Pin Function
connected to 1/3V or 2/3V using external resistors.
DD
DD
LVDS
DIGITAL OUTPUT MODE
Full-Rate CMOS
Demultiplexed CMOS
Low Power LVDS
LVDS
The lower limit of the sample rate is determined by the
droop of the sample and hold circuits. The pipelined ar-
chitecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
thecapacitors.Thespecifiedminimumoperatingfrequency
for the LTM9001 is 1Msps.
0V(GND)
1/3V
2/3V
DD
DD
V
DD
Digital Output Buffers (CMOS Modes)
Figure 10 shows an equivalent circuit for a single output
buffer in CMOS Mode, Full-Rate or Demultiplexed. Each
+
ENC
V
= 1.6V
THRESHOLD
buffer is powered by OV and OGND, isolated from the
DD
–
LTM9001
1.6V
ENC
ADCpowerandground.TheadditionalN-channeltransistor
intheoutputdriverallowsoperationdowntolowvoltages.
The internal resistor in series with the output makes the
output appear as 50Ω to external circuitry and eliminates
the need for external damping resistors.
0.1μF
9001F8
Figure 8. Single-Ended ENC Drive,
Not Recommended for Low Jitter
LTM9001
OV
DD
0.5V
TO 3.6V
V
V
DD
DD
3.3V
3.3V
MC100LVELT22
D0
261Ω
Q0
261Ω
LTM9001
100Ω
OV
DD
+
ENC
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
–
ENC
Q0
165Ω
OGND
165Ω
9001 F09
9001 F10
Figure 9. ENC Drive Using a CMOS to PECL Translator
Figure 10. Equivalent Circuit for a Digital Output Buffer
9001fa
21
LTM9001
APPLICATIONS INFORMATION
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTM9001 should drive a minimum
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
output may be used but is not required since the ADC has
a series resistor of 43Ω on chip.
In Low Power LVDS Mode 1.75mA is steered between
the differential outputs, resulting in 175mV at the LVDS
receiver’s 100Ω termination resistor. The output common
mode voltage is 1.2V, the same as standard LVDS Mode.
Data Format
The LTM9001 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MODE pin. This pin has a four level
logic input, centered at 0, 1/3V , 2/3V and V . An
DD
DD
DD
external resistive divider can be used to set the 1/3V
Lower OV voltages will also help reduce interference
DD
DD
and 2/3V logic levels. Table 5 shows the logic states
from the digital outputs.
DD
for the MODE pin.
Digital Output Buffers (LVDS Modes)
Table 5. MODE Pin Function
Figure 11 shows an equivalent circuit for an LVDS output
MODE
OUTPUT FORMAT
Offset Binary
CLOCK DUTY CYCLE STABILIZER
+
–
pair. A 3.5mA current is steered from OUT to OUT or vice
versa, which creates a 350mV differential voltage across
the 100Ω termination resistor at the LVDS receiver.
0V(GND)
Off
On
On
Off
1/3V
2/3V
Offset Binary
DD
DD
2’s Complement
2’s Complement
A feedback loop regulates the common mode output volt-
age to 1.2V. For proper operation each LVDS output pair
must be terminated with an external 100Ω termination
V
DD
Overflow Bit
+
–
resistor, even if the signal is not used (such as OF /OF or
An overflow output bit (OF) indicates when the converter is
over-ranged or under-ranged. In CMOS mode, a logic high
on the OFA pin indicates an overflow or underflow on the
A data bus, while a logic high on the OFB pin indicates an
overflowontheBdatabus.InLVDSmode,adifferentiallogic
+
–
CLKOUT /CLKOUT ). To minimize noise the PC board
traces for each LVDS output pair should be routed close
together. To minimize clock skew all LVDS PC board traces
should have about the same length.
+
–
high on OF /OF pins indicates an overflow or underflow.
LTM9001
OV
DD
3.3V
3.5mA
V
DD
V
DD
OV
DD
43Ω
43Ω
DATA
FROM
LATCH
10k
10k
PREDRIVER
LOGIC
LVDS
RECEIVER
OV
DD
100Ω
+
–
1.20V
OGND
9001 F11
Figure 11. Equivalent Output Buffer in LVDS Mode
9001fa
22
LTM9001
APPLICATIONS INFORMATION
Output Clock
LTM9001
CLKOUT
CLKOUT
OF
TheADChasadelayedversionoftheencodeinputavailable
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal encode.
OF
D15
D15/D0
D14/D0
In both CMOS modes, A bus data will be updated as CLK-
OUTA falls and CLKOUTB rises. In demultiplexed CMOS
mode the B bus data will be updated as CLKOUTA falls
and CLKOUTB rises.
D14
•
•
•
In Full Rate CMOS Mode, only the A data bus is active;
data may be latched on the rising edge of CLKOUTA or
the falling edge of CLKOUTB.
D2
D1
D2/D0
D1/D0
In demultiplexed CMOS mode CLKOUTA and CLKOUTB
will toggle at 1/2 the frequency of the encode signal. Both
the A bus and the B bus may be latched on the rising edge
of CLKOUTA or the falling edge of CLKOUTB.
RAND = HIGH,
RANDOMIZER
ENABLED
RAND
D0
D0
9001 F12
Digital Output Randomizer
Figure 12. Functional Equivalent of Digital Output Randomizer
Interference from the ADC digital outputs is sometimes
unavoidable. Interference from the digital outputs may
be from capacitive or inductive coupling or coupling
through the ground plane. Even a tiny coupling factor can
result in discernible unwanted tones in the ADC output
spectrum.
PC BOARD
FPGA
CLKOUT
OF
By randomizing the digital output before it is transmitted
offchip,theseunwantedtonescanberandomized,trading
a slight increase in the noise floor for a large reduction in
unwanted tone amplitude.
D15 ⊕ D0
D15
D14 ⊕ D0
D14
The digital output is “Randomized” by applying an exclu-
sive-ORlogicoperationbetweentheLSBandallotherdata
output bits. To decode, the reverse operation is applied;
that is, an exclusive-OR operation is applied between the
LSB and all other bits. The LSB, OF and CLKOUT output
are not affected. The output Randomizer function is active
when the RAND pin is high.
•
LTM9001
•
D2 ⊕ D0
•
D2
D1 ⊕ D0
D1
D0
D0
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV , should be tied
DD
9001 F13
to the same power supply as for the logic being driven.
Figure 13. Derandomizing a Randomized Digital Output
9001fa
23
LTM9001
APPLICATIONS INFORMATION
For example, if the converter is driving a DSP powered
dither signal will be seen at the output. The dither signal
thatdoesleakthroughwillappearaswhitenoise.Thedither
DAC will cause a small elevation in the noise floor of the
ADC, as compared to the noise floor with dither off.
by a 1.8V supply, then OV should be tied to that same
DD
1.8V supply. In CMOS mode OV can be powered with
DD
any logic voltage up to the 3.6V. OGND can be powered
with any voltage from ground up to 1V and must be less
For best noise performance with the dither signal on, the
than OV . The logic outputs will swing between OGND
+
–
DD
driving impedance connected across pins IN /IN should
closely match that of the module (see Table 1). A source
impedancethatisresistiveandmatchesthatofthemodule
within 10% will give the best results.
and OV . In LVDS Mode, OV should be connected to
DD
DD
a 3.3V supply and OGND should be connected to GND.
Internal Dither
The LTM9001 is a 16-bit receiver subsystem with a very
linear transfer function; however, at low input levels even
slight imperfections in the transfer function will result in
unwanted tones. Small errors in the transfer function are
usually a result of ADC element mismatches. An optional
internaldithermodecanbeenabledtorandomizetheinput
location on the ADC transfer curve, resulting in improved
SFDR for low signal levels.
Supply Sequencing
TheV pinprovidesthesupplytotheamplifierandtheV
CC
DD
pin provides the supply to the ADC. The amplifier and the
ADC are separate integrated circuits within the LTM9001;
however, there are no supply sequencing considerations
beyond standard practice. It is recommended that the am-
plifier and ADC both use the same low noise, 3.3V supply,
but the amplifier may be operated from a lower voltage
level if desired. Both devices can operate from the same
3.3V linear regulator but place a ferrite bead between the
As shown in Figure 14, the output of the sample-and-hold
amplifier is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
number generator; the random number fed to the dither
DAC is also subtracted from the ADC result. If the dither
DAC is precisely calibrated to the ADC, very little of the
V
and V pins. Separate linear regulators can be used
CC
DD
withoutadditionalsupplysequencingcircuitryiftheyhave
common input supplies.
LTM9001
CLKOUT
OF
+
D15
IN
16-BIT
PIPELINED
ADC CORE
•
•
•
DIGITAL
SUMMATION
OUTPUT
DRIVERS
S/H
AMP
–
IN
D0
CLOCK/DUTY
CYCLE
CONTROL
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
PRECISION
DAC
GENERATOR
9001 F14
+
–
ENC
ENC
DITH
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
Figure 14. Functional Equivalent Block Diagram of Internal Dither Circuit
9001fa
24
LTM9001
APPLICATIONS INFORMATION
Grounding and Bypassing
Recommended Layout
The LTM9001 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTM9001 has been optimized for a flow-through layout
so that the interaction between inputs and digital outputs
is minimized. A continuous row of ground pads facilitate
a layout that ensures that digital and analog signal lines
are separated as much as possible.
The high integration of the LTM9001 makes the PC board
layoutverysimpleandeasy.However,tooptimizeitselectri-
cal and thermal performance, some layout considerations
are still necessary, see Figures 15-18.
• Use large PCB copper areas for ground. This helps to
dissipate heat in the package through the board and
also helps to shield sensitive on-board analog signals.
Common ground (GND) and output ground (OGND)
are electrically isolated on the LTM9001, but can be
connected on the PCB underneath the part to provide
a common return path.
TheLTM9001isinternallybypassedwiththeamplifier(V )
CC
and ADC (V ) supplies returning to a common ground
DD
(GND). The digital output supply (0V ) is returned to
DD
OGND. Additional bypass capacitance is optional and may
• Use multiple ground vias. Using as many vias as pos-
sible helps to improve the thermal performance of the
boardandcreatesnecessarybarriersseparatinganalog
and digital traces on the board at high frequencies.
be required if power supply noise is significant.
Thedifferentialinputsshouldrunparallelandclosetoeach
other. The input traces should be as short as possible to
minimize capacitance and to minimize noise pickup.
• Separate analog and digital traces as much as pos-
sible, using vias to create high-frequency barriers.
This will reduce digital feedback that can reduce the
signal-to-noise ratio (SNR) and dynamic range of the
LTM9001.
Heat Transfer
Most of the heat generated by the LTM9001 is transferred
through the bottom-side ground pads. For good electrical
and thermal performance, it is critical that all ground pins
are connected to a ground plane of sufficient area with as
many vias as possible.
The quality of the paste print is an important factor in
producing high yield assemblies. It is recommended to
useatype3or4printingno-cleansolderpaste. Thesolder
stencil design should follow the guidelines outlined in
Application Note 100.
The LTM9001 employs gold-finished pads for use with
Pb-basedortin-basedsolderpaste.ItisinherentlyPb-free
and complies with the JEDEC (e4) standard. The materi-
als declaration is available online at http://www.linear.
com/designtools/leadfree/mat_dec.jsp.
9001fa
25
LTM9001
APPLICATIONS INFORMATION
Figure 15. Layer 1
Figure 16. Layer 2
Figure 17. Layer 3
Figure 18. Layer 4
9001fa
26
LTM9001
PACKAGE DESCRIPTION
LGA Package
81-Lead (11.25mm × 11.25mm × 2.32mm)
(Reference LTC DWG # 05-08-1809 Rev A)
Z
b b b
Z
5 . 0 8 0
3 . 8 1 0
2 . 5 4 0
1 . 2 7 0
0 . 0 0 0
0 . 9 5 2 5
1 . 5 8 7 5
1 . 2 7 0
2 . 5 4 0
3 . 8 1 0
5 . 0 8 0
a a a
Z
9001fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTM9001
TYPICAL APPLICATIONS
LTM9001 with Ground-Referenced Single-Ended Input
3.3V
75Ω
75Ω
R
50Ω
V
S
CC
+
GROUND–
REFERENCED
SOURCE
IN LTM9001
–
IN
+
–
0V
51.1Ω
9001 TA02
RELATED PARTS
PART NUMBER
LTC2202
DESCRIPTION
COMMENTS
16-Bit, 10Msps ADC
16-Bit, 25Msps ADC
16-Bit, 40Msps ADC
16-Bit, 65Msps ADC
16-Bit, 80Msps ADC
140mW, 81.6dB SNR, 100dB SFDR
220mW, 81.6dB SNR, 100dB SFDR
480mW, 79.1dB SNR, 100dB SFDR
610mW, 79dB SNR, 100dB SFDR
725mW, 77.9dB SNR, 100dB SFDR
900mW, 77.9dB SNR, 100dB SFDR
1250mW, 77.7dB SNR, 100dB SFDR
1450mW, 77.1dB SNR, 100dB SFDR
LTC2203
LTC2204
LTC2205
LTC2206
LTC2207
16-Bit, 105Msps ADC
16-Bit, 130Msps ADC
16-BIT, 160Msps ADC
LTC2208
LTC2209
LTC6400-20/LTC6400-26
Low Noise, Low Distortion Differential Amplifier for 3V, 90mA, 39.5dBm OIP3 at 300MHz, 6dB NF
300MHz IF, Fixed Gain of 20dB or 26dB
LTC6401-20/LTC6401-26
Low Noise, Low Distortion Differential Amplifier for 3V, 45mA, 45.5dBm OIP3 at 140MHz, 6dB NF
140MHz IF, Fixed Gain of 20dB or 26dB
9001fa
LT 1108 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
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●
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