LTM9002IV-AAPBF [Linear]
14-Bit Dual-Channel IF/Baseband Receiver Subsystem; 14位双通道IF /基带接收器子系统
| 型号： | LTM9002IV-AAPBF |
| 厂家： | 
Linear |
| 描述： | 14-Bit Dual-Channel IF/Baseband Receiver Subsystem |
| 文件： | 总28页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM9002
14-Bit Dual-Channel IF/
Baseband Receiver Subsystem
FEATURES
DESCRIPTION
The LTM®9002 is a 14-bit dual-channel IF receiver sub-
system. Utilizing an integrated system in a package (SiP)
technology, it includes a dual high-speed 14-bit A/D con-
verter, matching network, anti-aliasing filter and two low
noise, differential amplifiers. It is designed for digitizing
widedynamicrangesignalswithanintermediatefrequency
(IF) up to 300MHz. The amplifiers allow either AC- or DC-
coupled input drive. Lowpass or bandpass filter networks
can be implemented with various bandwidths. Contact
Linear Technology regarding customization.
n
Integrated Dual 14-Bit, High-Speed ADC, Passive
Filters and Fixed Gain Differential Amplifiers
n
Up to 300MHz IF Range
Lowpass and Bandpass Filter Versions
Integrated Low Noise, Low Distortion Amplifiers
n
Fixed Gain: 8dB, 14dB, 20dB or 26dB
50Ω, 200Ω or 400Ω Input Impedance
n
Integrated Bypass Capacitance, No External
Components Required
n
66dB SNR Up to 140MHz Input (LTM9002-AA)
n
76dB SFDR Up to 140MHz Input (LTM9002-AA)
The LTM9002 is perfect for demanding communications
applications,withACperformancethatincludes66dBSNR
and 76dB spurious free dynamic range (SFDR). Auxiliary
DACs allow gain balancing between channels.
n
Auxiliary 12-Bit DACs for Gain Adjustment
n
Clock Duty Cycle Stabilizer
Single 3V to 3.3V Supply
n
n
Low Power: 1.3W (665mW/ch.)
n
A single 3V supply allows low power operation. A separate
outputsupplyallowstheoutputstodrive0.5Vto3.3Vlogic.
An optional multiplexer allows both channels to share a
digital output bus. Two single-ended CLK inputs can be
driven together or independently. An optional clock duty
cycle stabilizer allows high performance at full speed for
a wide range of clock duty cycles.
Shutdown and Nap Modes
n
15mm × 11.25mm LGA Package
APPLICATIONS
n
Telecommunications
n
Direct Conversion Receivers
n
Main and Diversity Receivers
Cellular Base Stations
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
TYPICAL APPLICATION
Dual Channel IF Receiver
64k Point FFT, fIN = 15MHz, –1dBFS,
SENSE = VDD, Channel A (LTM9002-LA)
V
CC
= 3V
V
DD
0
OV
DD
0.5V TO 3.6V
–10
–20
V
REF
–30
+
–
INA
–40
MAIN
RF
14-BIT
125Msps ADC
FILTER
DAC
SAW
INA
–50
–60
LO
CLKOUT
–70
ADC CLK
SPI
MUX
OF
DIFFERENTIAL
AMPLIFIERS
–80
–90
DAC
–100
–110
–120
+
INB
14-BIT
125Msps ADC
DIVERSITY
RF
FILTER
SAW
–
INB
0
5
10
15
20
25
30
LO
FREQUENCY (MHz)
9002 TA01b
9002 TA01
OGND
GND
9002f
1
LTM9002
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
SENSEB SENSEA
ALL OTHERS = GND
Supply Voltage (V ) ................................ –0.3V to 3.6V
CC
J
Supply Voltage (V , OV )......................... –0.3V to 4V
DD
DD
OV
DD
+
–
INA
INA
H
G
F
Digital Output Ground Voltage (OGND)........ –0.3V to 1V
+
–
Input Current (IN , IN )........................................ 10mA
DAC Digital Input Voltage
OGND
V
CC
V
DD
(CS/LD, SDI, SCK) ................................... –0.3V to 6V
Digital Input Voltage
E
D
C
B
A
OGND
(Except AMPSHDN)................. –0.3V to (V + 0.3V)
DD
–
INB
INB
Digital Input Voltage
+
(AMPSHDN)..............................–0.3V to (V + 0.3V)
CC
OV
DD
Digital Output Voltage ................–0.3V to (OV + 0.3V)
DD
1
2
3
4
5
6
7
8
9
10
11
12
Operating Temperature Range
CLKA CLKB
DATA
CONTROL
LTM9002C................................................ 0°C to 70°C
LTM9002I.............................................–40°C to 85°C
Storage Temperature Range...................–65°C to 125°C
LGA PACKAGE
108-LEAD (15mm × 11.25mm × 2.32mm)
T
JA
= 125°C, θ = 19°C/W, θ
= 16°C/W, θ
= 6°C/W
JMAX
JA
JCTOP
JCBOT
θ
DERIVED FROM 101.5mm × 114.5mm PCB WITH 4 LAYERS
WEIGHT = 0.935g
ORDER INFORMATION
LEAD FREE FINISH
LTM9002CV-AA#PBF
LTM9002CV-LA#PBF
LTM9002IV-AA#PBF
LTM9002IV-LA#PBF
TRAY
PART MARKING*
LTM9002VAA
LTM9002VLA
LTM9002VAA
LTM9002VLA
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTM9002CV-AA#PBF
LTM9002CV-LA#PBF
LTM9002IV-AA#PBF
LTM9002IV-LA#PBF
108-Lead (15mm × 11.25mm × 2.3mm) LGA
108-Lead (15mm × 11.25mm × 2.3mm) LGA
108-Lead (15mm × 11.25mm × 2.3mm) LGA
108-Lead (15mm × 11.25mm × 2.3mm) LGA
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
9002f
2
LTM9002
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Unless otherwise noted. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
G
DIFF
Gain
DC, LTM9002-AA
IN
25
26
25
27
dB
dB
f
= 140MHz
l
l
Channel A, DC (LTM9002-LA)
= 15MHz
19.4
7.5
20
19
8
20.6
8.5
dB
dB
dB
dB
f
IN
Channel B, DC (LTM9002-LA)
f
IN
= 15MHz
7
G
Gain Temperature Drift
Gain Matching
V
= MAX, (Note 3)
1.5
5
mdB/°C
mdB
TEMP
IN
IN
External Reference
Both Channels, f = 140MHz (LTM9002-AA)
V
Input Voltage Range for –1dBFS
100
200
800
mV
mV
mV
IN
P-P
P-P
Channel A, f = 15MHz (LTM9002-LA)
IN
Channel B, f = 15MHz (LTM9002-LA)
IN
P-P
V
Input Common Mode Voltage Range
Differential Input Impedance
1
1.5
V
INCM
R
Both Channels (LTM9002-AA)
50
Ω
INDIFF
Channel A (LTM9002-LA)
Channel B (LTM9002-LA)
200
400
Ω
Ω
C
V
Differential Input Capacitance
Offset Error (Note 5)
Includes Parasitic
1
pF
INDIFF
OS
l
Including Amplifier and ADC
–5
0.3
0.3
10
50
5
mV
mV
μV/°C
dB
Offset Matching
Offset Drift
Including Amplifier and ADC
0V < SENSE < 1V
CMRR
Common Mode Rejection Ratio
SENSE Input Leakage
l
l
I
I
t
t
–3
–3
3
3
μA
SENSE
MODE
AP
MODE Input Leakage
0V < MODE < V
μA
DD
Sample and Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Time Jitter
0
ns
0.2
ps
RMS
JITTER
CONVERTER CHARACTERISTICS The l indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ADC Characteristics
l
l
Resolution (No Missing Codes)
LTM9002-AA
LTM9002-LA
LTM9002-AA
LTM9002-LA
LTM9002-AA
LTM9002-LA
14
12
Bits
Bits
LSB
LSB
LSB
LSB
INL
Integral Linearity Error (Note 4)
Differential Linearity Error
1.5
0.3
0.6
0.2
l
l
DNL
–1
–1
1
1
9002f
3
LTM9002
DYNAMIC ACCURACY The l indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. Input = –1dBFS. (Note 3)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SNR
Signal-to-Noise Ratio
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
66
66
dBFS
dBFS
l
61.5
l
l
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
67.7
68.5
69.9
71.1
dBFS
dBFS
SFDR
SFDR
S/(N+D)
IMD3
Spurious Free Dynamic Range, 2nd or 3rd
Harmonic
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
82
76
dBc
dBc
l
67.5
l
l
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
75
72.7
86.2
85.5
dBc
dBc
Spurious Free Dynamic Range 4th or Higher
Signal-to-Noise Plus Distortion Ratio
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
90
90
dBc
dBc
l
74.2
l
l
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
78.8
79.8
88.5
90.7
dBc
dBc
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
66
66
dBFS
dBFS
l
60.7
l
l
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
67.1
67.9
69.7
70.8
dBFS
dBFS
Third Order Inter-Modulation Distortion;
1MHz Tone Spacing, Two Tones –7dBFS
70MHz Input, LTM9002-AA
140MHz Input, LTM9002-AA
77
73
dBc
dBc
15MHz Input, LTM9002-LA
140MHz Input, LTM9002-AA
15MHz Input, LTM9002-LA
77
dBc
dB
Crosstalk
–110
–110
dB
AUXILIARY DAC CHARACTERISTICS The l indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Not applicable for LTM9002-LA) (Note 3)
PARAMETER
Resolution
CONDITIONS
MIN
12
TYP
MAX
UNITS
Bits
Bits
V
l
l
Monotonicity
Full-Scale Range
Settling Time
12
Internal Reference
1.5
0.024ꢀ ( 1LSB at 12 Bits),
No External Sense Capacitor
83.5
μs
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Logic Inputs (CLK, OE, ADCSHDN, MUX, CS/LD, SCK, SDI)
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 3V
2
V
V
IH
DD
DD
IN
= 3V
0.8
10
IL
I
= 0V to V
–10
μA
pF
IN
DD
C
IN
Input Capacitance
(Note 6)
3
9002f
4
LTM9002
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
Logic Inputs (AMPSHDN)
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
l
V
V
Low Level Input Voltage
High Level Input Voltage
Input Low Current
0.8
V
V
IL
2.4
IH
I
I
AMPSHDN = 0.8V
AMPSHDN = 2.4V
0.5
3
μA
μA
IL
IH
Input High Current
1.4
Logic Outputs
OV = 3V
DD
C
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
OE = 3V (Note 6)
3
pF
mA
mA
OZ
I
I
V
OUT
V
OUT
= 0V
= 3V
50
50
SOURCE
SINK
V
High Level Output Voltage
I = –10μA
O
2.995
2.99
V
V
OH
O
I = –200μA
l
l
2.7
V
OL
Low Level Output Voltage
I = 10μA
0.005
0.09
V
V
O
I = 1.6mA
0.4
O
OV = 2.5V
DD
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I = –200μA
2.49
0.09
V
V
O
I = 1.6mA
O
OV = 1.8V
DD
V
High Level Output Voltage
Low Level Output Voltage
I = –200μA
1.79
0.1
V
V
OH
OL
O
V
I = 1.6mA
O
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 7)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
Amplifier and Auxiliary DAC
Operating Supply Range
2.85
3.0
3.4
V
CC
l
l
l
l
V
ADC Analog Supply Voltage
Output Supply Voltage
Amplifier
2.85
0.5
3.0
3.0
180
90
3.5
3.6
V
V
DD
O
VDD
I
DAC Powered Up, Both Amplifiers Enabled, LTM9002-AA
Both Amplifiers Enabled, LTM9002-LA
AMPSHDN = 3V, DAC Powered Down
LTM9002-AA
207
120
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
CC
I
I
Amplifier Shutdown Supply Current
ADC Supply Current
0.7
263
140
2
CC(SHDN)
l
l
313
159
DD(ADC)
LTM9002-LA
P
P
P
ADC Shutdown Power (Each Channel) ADCSHDN = AMPSHDN = 3V, OE = 3V, No CLK
ADC Nap Mode Power (Each Channel) ADCSHDN = AMPSHDN = 3V, OE = 0V, No CLK
D(SHDN)
D(NAP)
D(AMP)
15
Amplifier Power Dissipation
ADC Power Dissipation
Total Power Dissipation
DAC Powered Up, LTM9002-AA
LTM9002-LA
540
270
790
420
l
l
P
P
LTM9002-AA
939
477
D(ADC)
LTM9002-LA
f
f
= MAX, LTM9002-AA
= MAX, LTM9002-LA
1329
690
mW
mW
D(TOTAL)
SAMPLE
SAMPLE
9002f
5
LTM9002
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 6) (Not applicable for LTM9002-LA)
SYMBOL
PARAMETER
CONDITIONS
LTM9002-AA
LTM9002-LA
MIN
1
TYP
MAX
125
65
UNITS
MHz
l
l
f
Sampling Frequency
S
1
MHz
l
l
t
t
t
t
CLK Low Time
CLK High Time
CLK Low Time
CLK High Time
Duty Cycle Stabilizer Off (Note 6), LTM9002-AA
Duty Cycle Stabilizer On (Note 6), LTM9002-AA
3.8
3
4
4
500
500
ns
ns
L
l
l
Duty Cycle Stabilizer Off (Note 6), LTM9002-AA
Duty Cycle Stabilizer On (Note 6), LTM9002-AA
3.8
3
4
4
500
500
ns
ns
H
L
l
l
Duty Cycle Stabilizer Off (Note 6), LTM9002-LA
Duty Cycle Stabilizer On (Note 6), LTM9002-LA
7.3
5
7.7
7.7
500
500
ns
ns
l
l
Duty Cycle Stabilizer Off (Note 6), LTM9002-LA
Duty Cycle Stabilizer On (Note 6), LTM9002-LA
7.3
5
7.7
7.7
500
500
ns
ns
H
t
t
t
Absolute Aperture Delay
CLK to DATA Delay
0
ns
ns
AP
l
l
l
l
l
l
C = 5pF (Note 6)
1.4
1.4
2.7
2.7
0
5.4
5.4
0.6
5.4
10
D
L
CLK to CLKOUT Delay
DATA to CLKOUT Skew
MUX to DATA Delay
C = 5pF (Note 6)
L
ns
C
(t – t ) (Note 6)
–0.6
1.4
ns
D
C
t
MD
C = 5pF (Note 6)
L
2.7
4.3
3.3
5
ns
C = 5pF (Note 6)
L
ns
DATA Access Time After OE↓
BUS Relinquish Time
(Note 6)
8.5
ns
Pipeline Latency
SPI Interface for Aux DACs, V = 2.7V to 3.6V
Cycles
DD
t
t
t
t
t
t
t
t
SDI Valid to SCK Setup
SDI Valid to SCK Hold
SCK High Time
4
4
ns
ns
1
2
9
ns
3
SCK Low Time
9
ns
4
CS/LD Pulse Width
10
7
ns
5
LSB SCK High to CS/LD
CS/LD Low to SCK High
CS/LD High to SCK Positive Edge
SCK Frequency 50ꢀ Duty Cycle
ns
6
7
ns
7
7
ns
10
50
MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 5: Offset error is the output code resulting when the inputs are
Note 2: All voltage values are with respect to ground with GND and OGND
shorted together. The output code is converted to millivolts.
wired together (unless otherwise noted).
Note 6: Guaranteed by design, not subject to test.
Note 3: OV = V = V = 3V, f
with differential drive, CLKA = CLKB, V
ADCSHDN = 0V, unless otherwise noted.
= MAX, input range = V
IN
DD
CC
DD
SAMPLE
Note 7: V = 3V, f
The supply current and power dissipation are the sum total for both
channels with both channels active.
= MAX, input range = V with differential drive.
DD
SAMPLE
IN
= 1.25V, AMPSHDN =
INCM
9002f
6
LTM9002
TIMING DIAGRAMS
Dual Digital Output Bus Timing
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 1
N + 3
N + 5
t
t
H
L
CLKA = CLKB
t
D
N – 5
N – 4
N – 3
N – 2
N – 1
N
D0-D13, OF
CLKOUT
t
C
9002 TD01
Multiplexed Digital Output Bus Timing
t
APA
A + 4
A + 2
B + 2
ANALOG
INPUT A
A
B
A + 1
B + 1
A + 3
B + 3
t
APB
B + 4
ANALOG
INPUT B
t
t
L
H
CLKA = CLKB = MUX
DA0-DA13
A – 5
B – 5
A – 5
A – 4
B – 4
B – 4
A – 3
B – 3
B – 3
A – 2
B – 2
B – 2
A – 1
B – 1
t
t
MD
D
B – 5
A – 4
A – 3
A – 2
DB0-DB13
CLKOUT
t
C
9002 TD02
9002f
7
LTM9002
TIMING DIAGRAMS
Auxiliary DAC Timing
t
1
t
6
t
t
3
t
4
2
SCK
SDI
1
2
3
23
24
t
10
C3
C2
C1
D1
D0
t
t
7
5
CS/LD
9002 TD03
TYPICAL PERFORMANCE CHARACTERISTICS
(LTM9002-AA)
Differential Non-Linearity (DNL)
vs Output Code
Integral Non-Linearity (INL),
Best Fit vs Output Code
SNR vs Frequency
72
71
70
69
68
67
66
65
64
63
62
4.0
3.0
1.0
0.8
0.6
2.0
0.4
1.0
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
–2.0
–3.0
–4.0
1
10
100
1000
0
4096
8192
12288
16384
0
4096
8192
12288
16384
IF FREQUENCY (MHz)
OUTPUT CODE
OUTPUT CODE
9002 G03
9002 G02
9002 G01
Input Impedance vs Frequency
IF Frequency Response
60
55
50
45
40
35
30
25
20
15
10
5
10
0
–2
9
MAGNITUDE
8
–4
7
–6
6
–8
5
4
–10
–12
–14
–16
–18
–20
3
2
PHASE
1
0
–1
–2
0
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
IF FREQUENCY (MHz)
9002 G04
9002 G05
9002f
8
LTM9002
TYPICAL PERFORMANCE CHARACTERISTICS
(LTM9002-AA)
64k Point 2-Tone FFT,
fIN = 70MHz and fIN = 74MHz,
–7dBFS Per Tone, SENSE = VDD
64k Point FFT, fIN = 70MHz,
–1dBFS, SENSE = VDD
0
–10
0
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
FREQUENCY (MHz)
FREQUENCY (MHz)
9002 G06
9002 G07
64k Point 2-Tone FFT,
fIN = 136MHz and fIN = 140MHz,
–7dBFS Per Tone, SENSE = VDD
64k Point FFT, fIN = 140MHz,
–1dBFS, SENSE = VDD
0
–10
0
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
FREQUENCY (MHz)
FREQUENCY (MHz)
9002 G09
9002 G08
(LTM9002-LA)
Differential Non-Linearity (DNL)
vs Output Code
Integral Non-Linearity (INL),
Best Fit vs Output Code
SNR vs Frequency (Channel A)
0.5
1.0
0.8
72
71
70
69
68
67
66
65
64
63
62
0.4
0.3
0.6
0.2
0.4
0.1
0.2
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
4096
0
1024
2048
3072
4096
1
10
100
OUTPUT CODE
OUTPUT CODE
IF FREQUENCY (MHz)
9002 G11
9002 G10
9002 G12
9002f
9
LTM9002
TYPICAL PERFORMANCE CHARACTERISTICS
(LTM9002-LA)
Input Impedance vs Frequency
(Channel A)
SNR vs Frequency (Channel B)
72
71
70
69
68
67
66
65
64
63
62
200
175
150
125
100
75
8
7
6
5
4
3
2
1
0
MAGNITUDE
50
PHASE
25
0
1
10
100
1
10
100
1000
IF FREQUENCY (MHz)
FREQUENCY (MHz)
9002 G13
9002 G14
Input Impedance vs Frequency
(Channel B)
64k Point FFT, fIN = 15MHz,
IF Frequency Response
–1dBFS, SENSE = VDD (Channel A)
400
350
300
250
200
150
100
50
32
28
24
20
16
12
8
0
–2
0
–10
–20
MAGNITUDE
–30
–4
–40
–50
–6
–60
–8
–70
–80
–10
–12
–14
–90
PHASE
–100
–100
–120
4
0
0
1
10
100
1000
0.1
1
10
100
0
5
10
15
20
25
30
35
FREQUENCY (MHz)
IF FREQUENCY (MHz)
FREQUENCY (MHz)
9002 G15
9002 G16
9002 G17
64k Point 2-Tone FFT, fIN = z and fIN
= 15MHz, –7dBFS Per Tone,
SENSE = VDD (Channel A)
64k Point 2-Tone FFT, fIN = 14MHz
and fIN = 15MHz, –7dBFS Per Tone,
SENSE = VDD (Channel B)
64k Point FFT, fIN = 15MHz,
–1dBFS, SENSE = VDD (Channel B)
0
–10
0
–10
0
–10
–20
–20
–20
–30
–30
–30
–40
–40
–40
–50
–50
–50
–60
–60
–60
–70
–70
–70
–80
–80
–80
–90
–90
–90
–100
–100
–120
–100
–100
–120
–100
–100
–120
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
9002 G18
9002 G19
9002 G20
9002f
10
LTM9002
PIN FUNCTIONS
Supply Pins
DNC3 (Pin C5): Do Not Connect. These pins are used for
testing and should not be connected on the PCB. They
should be soldered to unconnected pads and should be
well isolated. The DNC pins connect to the signal path
prior to the ADC inputs; therefore, care should be taken
to keep other signals away from these sensitive nodes.
DNC3 connects near the channel B positive differential
analog input.
GND (Pins A1-2, A5-7, B2-4, B6, C2-3, C6, D1-3, D5-7,
D9-10, E5-6, E9-10, F1-2, F5-7, F9-10, G2-3, G6, H2-4,
H6, J1-2, J5-7): ADC Power Ground.
OGND (Pins A12, C9, G9, J12): Output Driver Ground.
OV (Pins B12, H12): Positive supply for the ADC output
DD
drivers.Thespecifiedoperatingrangeis0.5Vto3.6V.OV
DD
is internally bypassed to OGND.
DNC4 (Pin B5): Do Not Connect. These pins are used for
testing and should not be connected on the PCB. They
should be soldered to unconnected pads and should be
well isolated. The DNC pins connect to the signal path
prior to the ADC inputs; therefore, care should be taken
to keep other signals away from these sensitive nodes.
DNC4 connects near the channel B negative differential
analog input.
V
(PinsE3,E4):AmplifierandAuxiliaryDACPowerSup-
CC
ply. The specified operating range is 2.85V to 3.465V. The
voltage on this pin provides power for the amplifier stage
andauxiliaryDACsonlyandisinternallybypassedtoGND.
Note that LTM9002-LA does not have auxiliary DACs.
V
(PinsE7,E8):Analog3VSupplyforADC.Thespecified
DD
operating range is 2.7V to 3.6V. V is internally bypassed
DD
DNC5 (Pin G4): Do Not Connect. This pin is used for test-
ing and should not be connected on the PCB. It should
be soldered to an unconnected pad and should be well
isolated. ThisisatestpointfortheauxiliaryDACchannelA
voltage output.
to GND.
Analog Inputs
CLKA (Pin A3): Channel A ADC Clock Input. The input
sample starts on the positive edge.
DNC6 (Pin C4): Do Not Connect. This pin is used for test-
ing and should not be connected on the PCB. It should
be soldered to an unconnected pad and should be well
isolated. ThisisatestpointfortheauxiliaryDACchannelB
voltage output.
CLKB (Pin A4): Channel B ADC Clock Input. The input
sample starts on the positive edge.
DNC1 (Pin H5): Do Not Connect. These pins are used for
testing and should not be connected on the PCB. They
should be soldered to unconnected pads and should be
well isolated. The DNC pins connect to the signal path
prior to the ADC inputs; therefore, care should be taken
to keep other signals away from these sensitive nodes.
DNC1 connects near the channel A positive differential
analog input.
–
INA (Pin G1): Channel A Negative (Inverting) Amplifier
Input.
+
INA (Pin H1): Channel A Positive (Noninverting) Am-
plifier Input.
–
INB (Pin C1): Channel B Negative (Inverting) Amplifier
Input.
DNC2 (Pin G5): Do Not Connect. These pins are used for
testing and should not be connected on the PCB. They
should be soldered to unconnected pads and should be
well isolated. The DNC pins connect to the signal path
prior to the ADC inputs; therefore, care should be taken
to keep other signals away from these sensitive nodes.
DNC2 connects near the channel A negative differential
analog input.
+
INB (Pin B1): Channel B Positive (Noninverting) Am-
plifier Input.
9002f
11
LTM9002
PIN FUNCTIONS
Control Pins
MUX (Pin C8): Digital Output Multiplexer Control. If MUX
= high, channel A comes out on DAx; channel B comes
out on DBx. If MUX = low, the output busses are swapped
and channel A comes out on DBx; channel B comes out
on DAx. To multiplex both channels onto a single output
bus, connect MUX, CLKA and CLKB together.
ADCSHDNA (Pin G7): Channel A Shutdown Mode Selec-
tion Pin. Connecting ADCSHDNA to GND and OEA to GND
results in normal operation with the outputs enabled.
Connecting ADCSHDNA to GND and OEA to V results
DD
in normal operation with the outputs at high impedance.
Connecting ADCSHDNA to V and OEA to GND results in
OEA (Pin F8): Channel A Output Enable Pin. Refer to
ADCSHDNA pin function.
DD
napmodewiththeoutputsathighimpedance. Connecting
ADCSHDNA to V and OEA to V results in sleep mode
DD
DD
OEB (Pin D8): Channel B Output Enable Pin. Refer to
ADCSHDNB pin function.
with the outputs at high impedance.
ADCSHDNB (Pin C7): Channel B Shutdown Mode Selec-
tion Pin. Connecting ADCSHDNB to GND and OEB to GND
results in normal operation with the outputs enabled.
SENSEA(PinJ4):ChannelAReferenceProgrammingPin.
Connecting SENSEA to V selects the internal reference
DD
and the higher input range. Connecting to 1.5V selects the
lower range. An external reference greater than 0.5V and
less than 1V applied to SENSEA selects an input range of
Connecting ADCSHDNB to GND and OEB to V results
DD
in normal operation with the outputs at high impedance.
Connecting ADCSHDNB to V and OEB to GND results in
DD
V
/GAIN. See SENSE Pin Operation section.
SENSEA
napmodewiththeoutputsathighimpedance. Connecting
SENSEB(PinJ3):ChannelBReferenceProgrammingPin.
ADCSHDNB to V and OEB to V results in sleep mode
DD
DD
Connecting SENSEB to V selects the internal reference
with the outputs at high impedance.
DD
and the higher input range. Connecting to 1.5V selects the
lower range. An external reference greater than 0.5V and
less than 1V applied to SENSEB selects an input range of
AMPSHDNA (Pin E1): Power Shutdown Pin for Channel A
Amplifier. This pin is a logic input referenced to analog
ground. AMPSHDN = low results in normal operation.
AMPSHDN = high results in powered down amplifier with
a <1mA amplifier supply current.
V
/GAIN. See SENSE Pin Operation section.
SENSEB
Digital Inputs (Not Connected on LTM9002-LA)
AMPSHDNB (Pin E2): Power Shutdown Pin for Channel B
Amplifier. This pin is a logic input referenced to analog
ground. AMPSHDN = low results in normal operation.
AMPSHDN = high results in powered down amplifier with
a <1mA amplifier supply current.
CS/LD (Pin F3): Serial Interface Chip Select/Load Input
for Auxiliary DAC. When CS/LD is low, SCK is enabled
for shifting data on SDI into the register. When CS/LD is
taken high, SCK is disabled and the specified command
(see Table 3) is executed.
MODE (Pin G8): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels.ConnectingMODEtoGNDselectsstraightbinary
output format and turns the clock duty cycle stabilizer off.
SCK (Pin F4): Serial Interface Clock Input for Auxiliary
DAC. CMOS and TTL compatible.
SDI (Pin D4): Serial Interface Data Input for Auxiliary
DAC. Data is applied to SDI for transfer to the device at
the rising edge of SCK. The auxiliary DAC accepts input
word lengths of either 24 or 32 bits.
1/3 V selects straight binary output format and turns
DD
the clock duty cycle stabilizer on. 2/3 V selects 2’s
DD
complement output format and turns the clock duty cycle
stabilizer on. V selects 2’s complement output format
DD
and turns the clock duty cycle stabilizer off.
9002f
12
LTM9002
PIN FUNCTIONS
Digital Outputs
DB0–DB13(RefertoPinConfigurationTable):ChannelB
ADC Digital Outputs. DB13 is the MSB for LTM9002-AA;
DB11 is the MSB for LTM9002-LA.
CLKOUT (Pin E12, LTM9002-AA): ADC Data Ready Clock
Output. LatchdataonthefallingedgeofCLKOUT. CLKOUT
is derived from CLKB. Tie CLKA to CLKB for simultaneous
operation.
OF (Pin H7, LTM9002-AA): Overflow/Underflow Output.
High when an overflow or underflow has occurred on
either channel A or channel B.
OFB(PinE12,LTM9002-LA):Overflow/UnderflowOutput.
High when an overflow or underflow has occurred on
channel B.
OFA (Pin H7, LTM9002-LA): Overflow/Underflow Output.
High when an overflow or underflow has occurred on
channel A.
DA0–DA13(RefertoPinConfigurationTable):ChannelA
ADC Digital Outputs. DA13 is the MSB for LTM9002-AA;
DA11 is the MSB for LTM9002-LA.
Pin Configuration (LTM9002-AA)
1
2
3
4
5
6
7
8
9
10
11
12
J
GND
GND
GND
GND
SENSEB
GND
SENSEA
GND
GND
DNC1
DNC2
GND
GND
GND
GND
OF
DA8
DA5
DA6
DA7
DA9
DA4
OGND
+
H
G
INA
DA10
MODE
DA12
OGND
DA11
DA13
OV
DD
–
INA
GND
DNC5
ADC
SHDNA
DA3
F
E
GND
GND
CS/LD
SCK
GND
GND
GND
GND
GND
OEA
GND
GND
GND
GND
DA2
DA0
DA1
AMP
SHDNA
AMP
SHDNB
V
CC
V
V
V
DD
CLKOUT
CC
DD
D
C
GND
GND
GND
GND
GND
SDI
GND
GND
GND
GND
OEB
GND
GND
DB1
DB13
DB11
DB12
DB10
–
INB
DNC6
DNC3
ADC
SHDNB
MUX
OGND
+
B
A
INB
GND
GND
GND
GND
DNC4
GND
GND
GND
DB0
GND
DB4
DB6
DB2
DB9
DB3
DB8
DB5
DB7
OV
DD
GND
CLKA
CLKB
OGND
Pin Configuration (LTM9002-LA)
1
2
3
4
5
6
7
8
9
10
11
12
J
GND
GND
GND
GND
SENSEB
GND
SENSEA
GND
GND
DNC1
DNC2
GND
GND
GND
GND
OFA
DA6
DA8
MODE
DA3
DA4
DA9
DA11
DA5
DA7
DA2
OGND
+
H
G
INA
DA10
OGND
OV
DD
–
INA
GND
DNC5
ADC
SHDNA
DA1
F
E
GND
GND
NC
NC
GND
GND
GND
GND
GND
OEA
GND
GND
GND
GND
DA0
NC
NC
AMP
SHDNA
AMP
SHDNB
V
CC
V
V
V
DD
OFB
CC
DD
D
C
GND
GND
GND
GND
GND
NC
GND
GND
GND
GND
OEB
GND
GND
NC
DB11
DB9
DB10
DB8
–
INB
DNC6
DNC3
ADC
SHDNB
MUX
OGND
+
B
A
INB
GND
GND
GND
GND
DNC4
GND
GND
GND
NC
DB2
DB4
DB0
DB7
DB1
DB6
DB3
DB5
OV
DD
GND
CLKA
CLKB
GND
OGND
9002f
13
LTM9002
BLOCK DIAGRAM
Functional Block Diagram (Only One Channel is Shown)
V
CC
V
DD
V
DD
V
CC
OV
DD
PIPELINED ADC SECTIONS
+
IN
ADC
DRIVER
INPUT
S/H
FILTER
OF*
1st
2nd
3rd
4th
5th
6th
–
IN
OUTPUT
DRIVERS
D13 … D0
*
CLKOUT
SHIFT REGISTER AND ERROR CORRECTION
VOLTAGE
REFERENCE
AMPSHDN
OGND
INTERNAL
VOLTAGE
REFERENCE
REFH
REFL
CLOCK SIGNALS
REF
BUFFER
DIFF
REF
AMP
DIFFERENTIAL
INPUT
CONTROL
LOGIC
LOW JITTER
CLOCK DRIVER
DAC
9001 BD
SENSE
*OFA AND OFB ON LTM9002-LA
SDI SCK CS/LD
GND
CLK
MODE ADC
SHDN
OE
9002f
14
LTM9002
OPERATION
DYNAMIC PERFORMANCE DEFINITIONS
If two pure sine waves of frequencies fa and fb are ap-
plied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa nfb, where m and n = 0,
1, 2, 3, etc. The 3rd order intermodulation products are
2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodula-
tion distortion is defined as the ratio of the RMS value of
either input tone to the RMS value of the largest 3rd order
intermodulation product.
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamen-
tal input frequency and the RMS amplitude of all other
frequency components at the ADC output. The output is
band limited to frequencies above DC to below half the
sampling frequency.
Spurious Free Dynamic Range (SFDR)
Signal-to-Noise Ratio
Spuriousfreedynamicrangeisthepeakharmonicorspuri-
ousnoisethatisthelargestspectralcomponentexcluding
theinputsignalandDC.Thisvalueisexpressedindecibels
relative to the RMS value of a full-scale input signal.
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Aperture Delay Time
Total Harmonic Distortion
The time from when CLK reaches mid supply to the in-
stant that the input signal is held by the sample and hold
circuit.
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal-to-noise ratio due
to the jitter alone will be:
THD= 20Log V22 + V32 + V42 +KVn2 / V1
(
)
where V1 is the RMS amplitude of the fundamental
frequency and V2 through Vn are the amplitudes of the
secondthroughnthharmonics.TheTHDcalculatedinthis
data sheet uses all the harmonics up to the fifth.
SNRJITTER = –20log (2π) • f • t
IN JITTER
Crosstalk
The amount of signal coupled from one channel into the
other. This is measured by applying a full-scale sinusoidal
input on channel A, shorting the inputs of channel B and
taking the ratio of the signal powers in an FFT.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
9002f
15
LTM9002
OPERATION
Description
Semi-Custom Options
TheLTM9002isanintegratedsysteminapackage(SiP)that
includes two high-speed 14-bit A/D converters, matching
networks, anti-aliasing filters and two low noise, differen-
tial amplifiers with fixed gain. These amplifiers need not
be the same, so that the gains and input impedances of
the two channels are different. Also included is a pair of
auxiliary DACs to allow for digital, full-scale adjustment
of each channel. The LTM9002 is designed for digitizing
high frequency, wide dynamic range signals with input
frequencies up to 300MHz. Typical applications include
digitizing in-phase and quadrature channels or main and
diversity channels in base station applications.
The μModule construction affords a new level of flexibility
in application-specific standard products. Standard ADC
and amplifier components can be integrated regardless
of their process technology and matched with passive
components to a particular application. The LTM9002-AA,
as the first example, is configured with a dual 14-bit ADC
sampling at rates up to 125Msps. The amplifier gain is
26dB with an input impedance of 50Ω and an input range
of100mV (–16dBm).Thematchingnetworkisdesigned
P-P
to optimize the interface between the amplifier output
and the ADC under these conditions. Additionally, there
is a 3rd order lowpass filter with a cutoff at 170MHz. The
auxiliary DACs allow adjustment of the full-scale range
with 12-bit resolution.
The following sections describe in further detail the op-
eration of each section. The SiP technology allows the
LTM9002 to be customized and this is described in the
first section. The outline of the remaining sections follows
the basic functional elements as shown in Figure 1.
However, other options are possible through Linear
Technology’s semi-custom development program. Linear
Technology has in place a program to deliver other speed,
resolution,IFrange,gainandfilterconfigurationsfornearly
any specified application. These semi-custom designs are
basedonexistingADCsandamplifierswithanappropriately
modified matching network. The final subsystem is then
tested to the exact parameters defined for the application.
The final result is a fully integrated, accurately tested and
optimized solution in the same package. For more details
onthesemi-customreceiversubsystemprogram,contact
Linear Technology.
AUXILIARY
DAC
ADC
AMPLIFIER
INPUT
ADC
NETWORK
9002 F01
Figure 1. Basic Functional Elements
Table 1. Semi-Custom Options
AMPLIFIER IF
RANGE
AMPLIFIER INPUT
IMPEDANCE
ADC SAMPLE
RATE
ADC
AUXILIARY
DAC
AMPLIFIER GAIN
FILTER
RESOLUTION
PART NUMBER
LTM9002-AA
LTM9002-LA
300MHz
140MHz
50Ω
26dB
170MHz LPF
25MHz LPF
125Msps
65Msps
14-Bit
12-Bit
12-Bit, SPI
None
200Ω (Channel A) 20dB (Channel A)
400Ω (Channel B) 8dB (Channel B)
Select Combination of Options from Columns Below
2
DC-300MHz
DC-140MHz
DC-70MHz
DC-35MHz
50Ω
200Ω
200Ω
400Ω
26dB
20dB
14dB
8dB
TBD
125Msps
105Msps
80Msps
65Msps
40Msps
25Msps
10Msps
14-Bit
12-Bit
10-Bit
12-Bit, I C
None
9002f
16
LTM9002
OPERATION
Note that not all combinations in Table 1 are possible at
thistimeandspecifiedperformancemaydiffersignificantly
from existing values.
analog input will result in a digitized value six cycles
later (see the Timing Diagram section). The CLK inputs
are single-ended. The ADC has two phases of operation,
determined by the state of the CLK input pins.
AMPLIFIER OPERATION
EachpipelinedstageshownintheBlockDiagramcontains
an ADC, a reconstruction DAC and an interstage residue
amplifier. In operation, the ADC quantizes the input to
the stage and the quantized value is subtracted from the
input by the DAC to produce a residue. The residue is
amplified and output by the residue amplifier. Successive
stages operate out of phase so that when the odd stages
are outputting their residue, the even stages are acquiring
that residue and visa versa.
The amplifiers used in the LTM9002 are low noise and
low distortion fully differential op amps/ADC drivers with
operation from DC to 2GHz (–3dB bandwidth). The ampli-
fiers are composed of fully differential amplifiers with on
chip feedback and output common mode voltage control
circuitry. Differential gain and input impedance are set by
internal resistors in the feedback network.
Table 2. Amplifier Gain and Input Impedance
WhenCLKislow, theanaloginputissampleddifferentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the Block Diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H dur-
ing this high phase of CLK. When CLK goes back low, the
first stage produces its residue which is acquired by the
secondstage. Atthesametime, theinputS/Hgoesbackto
acquiring the analog input. When CLK goes back high, the
secondstageproducesitsresiduewhichisacquiredbythe
third stage. An identical process is repeated for the third,
fourth and fifth stages, resulting in a fifth stage residue
that is sent to the sixth stage ADC for final evaluation.
GAIN (dB)
GAIN (V/V)
Z
(DIFFERENTIAL)
400Ω
IN
8
2.5
5
14
20
26
200Ω
10
20
200Ω
50Ω
The amplifiers are very flexible in terms of I/O coupling.
They can be AC- or DC-coupled at the inputs. Due to the
internal connection between input and output, users are
advised to keep input common mode voltage between 1V
and1.7Vforproperoperation.IftheinputsareAC-coupled,
the input common mode voltage is automatically biased
close to the ADC input common mode voltage and thus no
external circuitry is needed for bias. The input signal can
be either single-ended or differential with some difference
in distortion performance.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
thattheresultscanbeproperlycombinedinthecorrection
logic before being sent to the output buffer.
ADC INPUT NETWORK
The passive network between the amplifier output stage
and the ADC input stage provides a 3rd order topology
that can be configured for bandpass or lowpass response
anddifferentcutofffrequenciesandbandwidths.LTM9002-
AA, for example, implements a lowpass filter designed
for 170MHz.
AUXILIARY DAC OPERATION
The full-scale voltage span of each ADC is controlled by an
auxiliary voltage output DAC connected to SENSE. Series
resistance in the DAC output allows an external voltage
to override the DAC.
CONVERTER OPERATION
As shown in the Block Diagram, the analog-to-digital con-
verter(ADC)isadualCMOSpipelinedmultistepconverter.
The converter has six pipelined ADC stages; a sampled
The internal reference sets both auxiliary DACs to a full-
scale range to 1.5V. Programming the DAC to generate
an internal voltage greater than or less than the external
9002f
17
LTM9002
OPERATION
reference adjusts the ADC span proportionately; see
Adjusting the full-scale input range. Powering down the
auxiliary DAC disables the ADC span trim control. When
the auxiliary DAC is powered down, connect SENSE to
converted to an analog voltage at the DAC output. The
update operation also powers up the selected DAC if it had
been in power-down mode. The data path and registers
are shown in the Block Diagram.
V
or an external reference.
DD
Whiletheminimuminputwordis24-bits,itmayoptionally
be extended to 32-bits to accommodate microprocessors
which have a minimum word width of 16 bits (2 bytes). To
usethe32-bitwordwidth, 8don’t-carebitsaretransferred
to the device first, followed by the 24-bit word as just
described. Figure 4 shows the 32-bit sequence.
Power-On Reset
The auxiliary DACs clear the outputs to zero-scale when
power is first applied, making system initialization con-
sistent and repeatable.
Transfer Function
Power-Down Mode
The digital-to-analog transfer function is;
Either or both DAC channels can be put into power-down
mode by using command 0100b in combination with
the appropriate DAC address, n. The 16-bit data word is
ignored.
N
V
= ( k/2 ) V
OUT(IDEAL)
REF
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and V
reference voltage of the ADC.
is 1.5V, the internal
REF
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 3.
The selected DAC is powered up as its voltage output is
updated. If both DACs are powered down, then the main
bias generation circuit block has been automatically shut
down in addition to the individual DAC amplifiers and
reference inputs. In this case, the power-up delay time is
Serial Interface
Allserialinterfacepins(CS/LD,SCKandSDI)haveTTLinput
levels and are 5V tolerant. The CS/LD input is level trig-
gered. When this input is taken low, it acts as a chip-select
signal,activatingtheSDIandSCKbuffersandenablingthe
input shift register. Data (SDI input) is transferred at the
next 24 rising SCK edges. The 4-bit command, C3-C0, is
loaded first; then the 4-bit DAC address, A3-A0; and finally
the 16-bit data word. The data word comprises the 12-bit
inputcode,orderedMSB-to-LSB,followedby4don’t-care
bits. Data can only be transferred to the device when the
CS/LD signal is low. The rising edge of CS/LD ends the
data transfer and causes the device to carry out the action
specified in the 24-bit input word. The complete sequence
is shown in Figure 3.
700μs (for V = 3V).
CC
Table 3. Auxiliary DAC Commands
COMMAND*
C3
0
C2
0
C1
0
C0
0
Write to Input Register n
0
0
0
1
Update (Power-Up) DAC Register n
0
0
1
0
Write to Input Register n, Update
(Power Up) All n
0
0
1
0
1
1
1
0
1
1
0
1
Write to and Update (Power-Up) n
Power Down n
No Operation
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 3. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 12-bit input code, and is
ADDRESS (n)*
A3
0
A2
0
A1
0
A0
0
DAC A
0
0
0
1
DAC B
1
1
1
1
All DACs
*Command and address codes not shown are reserved and should not
be used.
9002f
18
LTM9002
OPERATION
9002f
19
LTM9002
APPLICATIONS INFORMATION
INPUT SPAN
LTM9002
Z
/2
500Ω
IN
25Ω
+
IN
The LTM9002 is configured with a given input span and
input impedance. With the amplifier gain and the ADC
input network described above for LTM9002-AA, the
V
IN
+
full-scale input range of the driver circuit is 0.1V . The
R
P-P
T
–
recommended ADC input span is achieved by tying the
SENSE pin to V . However, the ADC input span can be
DD
500Ω
25Ω
–
Z /2
IN
changed if required for the application. The resulting input
IN
+
–
span at the IN /IN pins is the ADC input span divided by
the gain.
9002 F04
Figure 4. Input Termination for Differential 50Ω
Input Impedance Using Shunt Resistor
+
The LTM9002 is intended to be driven through the IN and
–
IN pins. The DNC pins are used for test purposes and are
not intended to be used in the application. These are test
points within the ADC input filter network. However, care
should be taken with these pins as they connect directly
to the internal signal path. They should be soldered to an
unconnected pad and should be well isolated.
LTM9002
+
500Ω
25Ω
Z /2
IN
IN
1:4
• •
V
IN
+
R
T
–
Input Impedance and Matching
The input impedance of the amplifier is 50Ω, 200Ω or
400Ω depending on the gain of the amplifier. In some
applications the differential inputs may need to be ter-
minated to a lower value impedance, e.g. 50Ω, in order
to provide an impedance match for the source. Several
choices are available.
500Ω
25Ω
Z /2
IN
–
IN
9002 F05
Figure 5. Input Termination for Differential 50Ω
Input Impedance Using a Balun
Referring to Figure 6, amplifier inputs can be easily con-
figured for single-ended input without a balun. The signal
is fed to one of the inputs through a matching network
while the other input is connected to the same matching
network and a source resistor. Because the return ratios
of the two feedback paths are equal, the two outputs have
the same gain and thus symmetrical swing. In general,
the single-ended input impedance and termination resis-
One approach is to use a differential shunt resistor
(Figure 4). Another approach is to employ a wide band
transformer and shunt resistor (Figure 5). Both methods
provide a wide band match. The termination resistor or
the transformer must be placed close to the input pins in
order to minimize the reflection due to input mismatch.
Alternatively, one could apply a narrowband impedance
match at the inputs for frequency selection and/or noise
reduction.
tor R are determined by the combination of R , R and
T
S
G
R , see Table 5.
F
Table 4. Differential Amplifier Input Termination Values
Table 5. Single-Ended Amplifier Input Termination Values
GAIN (dB)
Z /2
IN
R FIGURE 4
T
R FIGURE 5
T
GAIN (dB)
Z /2
IN
R FIGURE 6
T
8
200Ω
100Ω
100Ω
25Ω
57Ω
66.5Ω
66.5Ω
None
400Ω
None
None
None
8
200Ω
100Ω
100Ω
25Ω
59Ω
14
20
26
14
20
26
68.5Ω
66.5Ω
150Ω
9002f
20
LTM9002
APPLICATIONS INFORMATION
R
LTM9002
LTM9002
S
0.1μF
R /2
S
Z /2
IN
500Ω
500Ω
50Ω
+
Z /2
IN
+
IN
IN
V
IN
+
–
R
T
V
IN
+
R
T
0.1μF
–
R
S
0.1μF
500Ω
500Ω
50Ω
Z
/2
R /2
S
–
Z /2
IN
–
IN
IN
IN
R
T
9002 F06
9002 F07
Figure 6. Input Termination for Differential
50Ω Input Impedance Using Shunt Resistor
Figure 7. Calculate Differential Gain
The amplifier is unconditionally stable, i.e. differential
stability factor Kf > 1 and stability measure B1 > 0. How-
ever, the overall differential gain is affected by the source
impedance in Figure 7:
Input Range
The input range can be set based on the application. The
0.1V input range (LTM9002-AA) will provide the best SNR
performancewhilemaintainingexcellentSFDR. Thelower
inputrangewillhaveslightlybetterSFDRperformance,but
theSNRwilldegradeby5dB. SeetheTypicalPerformance
Characteristics section.
AV = | V /V | = (500/(R + Z /2)
OUT IN
S
IN
The noise performance of the amplifier also depends
uponthesourceimpedanceandtermination. Forexample,
an input 1:4 transformer in Figure 5 improves the input
noise figure by adding 6dB gain at the inputs. A trade-off
between gain and noise is obvious when constant noise
figure circle and constant gain circle are plotted within
the input Smith Chart, based on which users can choose
the optimal source impedance for a given gain and noise
requirement.
Adjusting the Full-Scale Input Range
To trim the full-scale range of one channel to match that
of the other channel, first set the desired range for both
channels by applying an external reference to SENSEA
and SENSEB as shown in Figure 8. Set the DAC codes to
approximately match the external reference voltage. Ap-
ply a full-scale voltage to the input of each channel. Read
the output of both channels and adjust the setting for the
DAC of one channel until the desired channel matching
has been achieved.
SENSE Pin Operation
The internal voltage reference can be configured for two
pin-selectable input ranges of 0.1V ( 50mV differential)
or 0.5V ( 25mV differential) for LTM9002-AA. Tying the
Theadjustmentrangeandstepsizedependsontheresistor
values chosen for or the source resistance of the external
reference circuit. The external reference is connected to
the SENSE pin which has 10k ( 1ꢀ) series impedance
with the internal DAC voltage. For the circuit shown in Fig-
ure 8, the step size is 76μV and the code representing 1V
is 0xAAB (0.666748 decimal). In this example, the SENSE
voltage trim range is from approximately 0.79V to 1.1V
including offset and gain errors. Therefore, the effective
input span can be trimmed from 39.6mV to 55.2mV with
a step size of 3.8μV. However, it is not recommended to
SENSEpintoV selectsthehigherrange;tyingtheSENSE
DD
pin to 1.5V selects the lower range. For other versions of
LTM9002, the input span is either 2V divided by the
P-P
gain or 1V divided by the gain.
P-P
An external reference can be used by applying its output
directly or through a resistive divider to SENSE. It is not
recommended to drive the SENSE pin with a logic device.
The SENSE pin should be tied to the appropriate level as
close to the converter as possible. The SENSE pin is inter-
nally bypassed to ground with a 1μF ceramic capacitor.
9002f
21
LTM9002
APPLICATIONS INFORMATION
exceed 50mV. The internal 1000pF capacitor provides a
corner frequency of 64kHz when used with the 2.5k ex-
ternal resistor. An additional 0.1μF bypass capacitor may
be required at the SENSE pin.
Driving the Clock Inputs
The CLK inputs can be driven directly with a CMOS or TTL
levelsignal.Asinusoidalclockcanalsobeusedalongwitha
low-jitter squaring circuit before the CLK pin (Figure 9).
The auxiliary DACs can be used without an external ref-
erence in applications that are not sensitive to close-in
phase noise such as CCD imaging or oversampling of low
amplitude signals. Without an external reference, the DAC
step size will be 366μV at the SENSE pin which results in
a 18μV step for the input span. In this case, the SENSE
pin may be bypassed with 0.1μF capacitor.
ThenoiseperformanceoftheADCcandependontheclock
signal quality as much as on the analog input. Any noise
present on the CLK signal will result in additional aperture
jitter that will be RMS summed with the inherent ADC
aperture jitter. In applications where jitter is critical, such
as when digitizing high input frequencies, use as large an
amplitude as possible. Also, if the ADC is clocked with a
sinusoidal signal, filter the CLK signal to reduce wideband
noise and distortion products generated by the source.
The auxiliary DACs must be subsequently set each time
the LTM9002 is powered up.
LTM9002
RANGE
SELECT
1.5V
REFERENCE
1.25V
REF
2.5k
REF
BUFFER
1V (OPEN CIRCUIT,
4k THEVENIN
SENSE
RESISTANCE)
1000pF
10k
10k
SDI
SCK
DAC
CS/LD
9002 F08
Figure 8. Using an External Reference
CLEAN
SUPPLY
FERRITE
BEAD
4.7μF
0.1μF
CLK
1k
0.1μF
LTM9002
SINUSOIDAL
CLOCK
INPUT
50Ω 1k
NC7SVU04
9002 F09
Figure 9. Sinusoidal Single-Ended CLK Driver
9002f
22
LTM9002
APPLICATIONS INFORMATION
It is recommended that CLKA and CLKB are shorted
together and driven by the same clock source. If a small
time delay is desired between when the two channels
sample the analog inputs, CLKA and CLKB can be driven
by two different signals. If this time delay exceeds 1ns,
the performance of the part may degrade. CLKA and CLKB
should not be driven by asynchronous signals.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may
be desirable in cases where lower voltage differential
signals are considered. The center tap may be bypassed
to ground through a capacitor close to the ADC if the
differential signals originate on a different plane. The
use of a capacitor at the input may result in peaking, and
depending on transmission line length may require a 10Ω
to 20Ω series resistor to act as both a lowpass filter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for reflections.
Figure 10 and Figure 11 show alternatives for converting
a differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
providelittledegradationbelow70MHz,butat140MHzwill
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bear-
ing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full-scale, the use of these translators will have
a lesser impact.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTM9002-AA is
125Msps and the LTM9002-LA is 65Msps. The lower
limit of the sample rate is determined by the droop of the
sample-and-hold circuits. The pipelined architecture of
this ADC relies on storing analog signals on small valued
capacitors. Junction leakage will discharge the capaci-
tors. The specified minimum operating frequency for the
LTM9002 is 1Msps.
CLEAN
SUPPLY
FERRITE
BEAD
4.7μF
0.1μF
ETC1-1T
CLK
LTM9002
5pF TO
30pF
CLK
LTM9002
DIFFERENTIAL
CLOCK
100Ω
INPUT
9002 F11
0.1μF
9002 F10
FERRITE
BEAD
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
V
CM
Figure 10. CLK Driver Using an LVDS or PECL to CMOS Converter
Figure 11. LVDS or PECL CLK Driver Using a Transformer
9002f
23
LTM9002
APPLICATIONS INFORMATION
Clock Duty Cycle Stabilizer
Digital Output Modes
An optional clock duty cycle stabilizer circuit ensures high
performance even if the input clock has a non 50ꢀ duty
cycle.Usingtheclockdutycyclestabilizerisrecommended
formostapplications.Tousetheclockdutycyclestabilizer,
Figure 12 shows an equivalent circuit for a single output
buffer.EachbufferispoweredbyO
andOGND,isolated
VDD
fromtheADCpowerandground.TheadditionalN-channel
transistor in the output driver allows operation down to
lowvoltages.Theinternalresistorinserieswiththeoutput
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
the MODE pin should be connected to 1/3V or 2/3V
DD
DD
using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and
the internal falling edge is generated by a phase-locked
loop. The input clock duty cycle can vary from 40ꢀ to
60ꢀ and the clock duty cycle stabilizer will maintain a
constant 50ꢀ internal duty cycle. If the clock is turned off
for a long period of time, the duty cycle stabilizer circuit
will require a hundred clock cycles for the PLL to lock
onto the input clock.
Aswithallhighspeed/highresolutionconvertersthedigital
output loading can affect the performance. The digital
outputs of the ADC should drive a minimal capacitive load
to avoid possible interaction between the digital outputs
and sensitive input circuitry. For full-speed operation, the
capacitive load should be kept under 10pF.
Lower OV voltages will also help reduce interference
DD
from the digital outputs.
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. If
thedutycyclestabilizerisdisabled,careshouldbetakento
make the sampling clock have a 50ꢀ ( 5ꢀ) duty cycle.
LTM9002
OV
DD
0.5V
TO 3.6V
V
V
DD
DD
0.1μF
43Ω
DIGITAL OUTPUTS
OV
DD
DATA
FROM
LATCH
Table 6 shows the relationship between the analog input
voltage, thedigitaldatabits, andtheoverflowbit. Notethat
OF is high when an overflow or underflow has occurred
on either channel A or channel B.
PREDRIVER
LOGIC
TYPICAL
DATA
OUTPUT
OE
OGND
Table 6. Output Codes vs Input Voltage, 100mV Input Span
9002 F12
+
–
IN – IN
(SENSE = V
D13 - D0
(OFFSET BINARY)
D13 - D0
(2’S COMPLEMENT)
)
DD
OF
Figure 12. Digital Output Buffer
≥ 50mV
1
0
0
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
0
0
0
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
0.000000V
≤ –50mV
0
0
1
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
9002f
24
LTM9002
APPLICATIONS INFORMATION
Data Format
OV can be powered with any voltage from 500mV up to
DD
3.6V, independent of V . OGND can be powered with any
DD
Using the MODE pin, the ADC parallel digital output can
be selected for offset binary or 2’s complement format.
Note that MODE controls both channel A and channel B.
Connecting MODE to GND or 1/3 V selects straight
binary output format. Connecting MODE to 2/3 V or
voltage from GND up to 1V and must be less than OV .
DD
The logic outputs will swing between OGND and OV .
DD
DD
Output Enable
DD
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to allow
the outputs to be enabled and disabled during full-speed
operation. The output Hi-Z state is intended for use during
test or initialization. Channels A and B have independent
output enable pins (OEA, OEB.)
V
selects 2’s complement output format. An external
DD
resistive divider can be used to set the 1/3 V or 2/3
DD
DD
V
logic values. Table 7 shows the logic states for the
MODE pin.
Table 7. MODE Pin Function
CLOCK DUTY CYCLE
STABILIZER
MODE PIN
OUTPUT FORMAT
0
Straight Binary
Straight Binary
2’s Complement
2’s Complement
Off
On
On
Off
Sleep and Nap Modes
1/3V
2/3V
DD
The converter may be placed in shutdown or nap modes
to conserve power. Connecting ADCSHDN to GND results
DD
V
DD
in normal operation. Connecting ADCSHDN to V and
DD
OE to V results in sleep mode, which powers down all
DD
Overflow Bit
circuitry including the reference and the ADC typically
dissipates 1mW. When exiting sleep mode, it will take
700μs to 1ms for the output data to become valid because
the reference capacitors have to recharge and stabilize.
For LTM9002-AA, when OF outputs a logic high the con-
verter is either overranged or underranged on channel A
or channel B. Note that both channels share a common
OF pin. OF is disabled when channel A is in sleep or nap
mode. For LTM9002-LA, OFA and OFB indicate either
condition for the respective channel.
Connecting ADCSHDN to V and OE to GND results in
DD
nap mode and the ADC typically dissipates 30mW. In nap
mode, the on-chip reference circuit is kept on, so that
recovery from nap mode is faster than that from sleep
mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Output Clock
The LTM9002-AA has a delayed version of the CLKB input
available as a digital output, CLKOUT. The falling edge of
the CLKOUT pin can be used to latch the digital output
data. CLKOUT is disabled when channel B is in sleep or
nap mode.
Channels A and B have independent ADCSHDN pins
(ADCSHDNA, ADCSHDNB.) Channel A is controlled by
ADCSHDNA and OEA, and channel B is controlled by
ADCSHDNB and OEB. The nap, sleep and output enable
modes of the two channels are completely independent,
so it is possible to have one channel operating while the
other channel is in nap or sleep mode.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV , should be tied
DD
to the same supply that powers the logic being driven.
Digital Output Multiplexer
For example, if the converter drives a DSP powered by a
The digital outputs of the ADC can be multiplexed onto a
single data bus. The MUX pin is a digital input that swaps
the two data busses. If MUX is high, channel A comes
out on DAx; channel B comes out on DBx. If MUX is low,
1.8V supply, then OV should be tied to that same 1.8V
DD
supply.
9002f
25
LTM9002
APPLICATIONS INFORMATION
the output busses are swapped and channel A comes
out on DBx; channel B comes out on DAx. To multiplex
both channels onto a single output bus, connect MUX,
CLKA and CLKB together (see the Timing Diagram for
the multiplexed mode.) The multiplexed data is available
on either data bus – the unused data bus can be disabled
with its OE pin.
Heat Transfer
Most of the heat generated by the LTM9002 is transferred
through the bottom-side ground pads. For good electrical
and thermal performance, it is critical that all ground pins
are connected to a ground plane of sufficient area with as
many vias as possible.
Recommended Layout
Supply Sequencing
The high integration of the LTM9002 makes the PC board
layoutverysimpleandeasy.However,tooptimizeitselectri-
cal and thermal performance, some layout considerations
are still necessary.
The V pin provides the supply to the amplifier and the
CC
auxiliary DAC while the V pin provides the supply to the
DD
ADC.Theamplifier,ADCandtheDACareseparateintegrated
circuits within the LTM9002; however, there are no supply
sequencing considerations beyond standard practice. It is
recommended that the amplifier, ADC and DAC all use the
• Use large PCB copper areas for ground. This helps
to dissipate heat in the package through the board
and also helps to shield sensitive on-board analog
signals. Common ground (GND) and output ground
(OGND) are electrically isolated on the LTM9002, but
can be connected on the PCB underneath the part to
provide a common return path.
samelownoise,3.0Vsupply,butV maybeoperatedfrom
CC
a different voltage level if desired. Both rails can operate
fromthesame3.0Vlinearregulatorbutplaceaferritebead
between the V and V pins. Separate linear regulators
CC
DD
canbeusedwithoutadditionalsupplysequencingcircuitry
if they have common input supplies.
• Use multiple ground vias. Using as many vias as
possible helps to improve the thermal performance
of the board and creates necessary barriers separat-
ing analog and digital traces on the board at high
frequencies.
Grounding and Bypassing
The LTM9002 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTM9002 has been optimized for a flow-through layout
so that the interaction between inputs and digital outputs
is minimized. A continuous row of ground pads facilitate
a layout that ensures that digital and analog signal lines
are separated as much as possible.
• Separate analog and digital traces as much as pos-
sible, using vias to create high-frequency barriers.
This will reduce digital feedback that can reduce the
signal-to-noise ratio (SNR) and dynamic range of the
LTM9002.
The quality of the paste print is an important factor in
producing high yield assemblies. It is recommended to
useatype3or4printingno-cleansolderpaste. Thesolder
stencil design should follow the guidelines outlined in
Application Note 100.
TheLTM9002isinternallybypassedwiththeADC,(V )and
DD
amplifier and DAC (V ) supplies returning to a common
CC
ground(GND).Thedigitaloutputsupply(OV )isreturned
DD
to OGND. Additional bypass capacitance is optional and
may be required if power supply noise is significant.
The LTM9002 employs gold-finished pads for use with
Pb-basedortin-basedsolderpaste.ItisinherentlyPb-free
and complies with the JEDEC (e4) standard. The materi-
als declaration is available online at http://www.linear.
com/leadfree/mat_dec.jsp.
Thedifferentialinputsshouldrunparallelandclosetoeach
other. The input traces should be as short as possible to
minimize capacitance and to minimize noise pickup.
9002f
26
LTM9002
PACKAGE DESCRIPTION
LGA Package
108-Lead (15mm × 11.25mm × 2.32mm)
(Reference LTC DWG # 05-08-1757 Rev Ø)
DETAIL A
aaa
Z
15
BSC
X
13.97
BSC
2.22 – 2.42
0.22 × 45°
CHAMFER
Y
J
H
G
F
MOLD
SUBSTRATE
CAP
11.25
BSC
10.16
BSC
E
D
C
B
A
0.27 – 0.37
1.95 – 2.05
1.27
BSC
PAD 1
CORNER
DETAIL B
4
aaa
Z
PADS
12
11
10
9
8
7
6
5
4
3
2
1
DIA (0.635)
PAD 1
SEE NOTES
PACKAGE TOP VIEW
3
PACKAGE BOTTOM VIEW
DETAIL B
0.630 0.025 SQ. 108x
eee
S X Y
5.080
3.810
2.540
1.270
0.000
1.270
2.540
3.810
5.080
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
LTMXXXXXX
μModule
2. ALL DIMENSIONS ARE IN MILLIMETERS
3
4
LAND DESIGNATION PER JESD MO-222, SPP-010
COMPONENT
PIN “A1”
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
TRAY PIN 1
BEVEL
SUGGESTED PCB LAYOUT
TOP VIEW
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. THE TOTAL NUMBER OF PADS: 108
PACKAGE IN TRAY LOADING ORIENTATION
LGA 108 0707 REV Ø
SYMBOL TOLERANCE
aaa
bbb
eee
0.15
0.10
0.05
9002f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTM9002
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1994
Low Noise, Low Distortion Fully Differential Input/
Output Amplifier/Driver
Low Distortion: –94dBc at 1MHz
LTC2205
LTC2206
LTC2207
LTC2208
LTC2240-12
LTC2241-12
LTC2242-12
LTC2248
LTC2249
LTC2254
LTC2255
LTC2282
LTC2283
LTC2284
LTC2285
LTC2293
LTC2294
LTC2295
LTC2296
LTC2297
LTC2298
LTC2299
LT5557
16-Bit, 65Msps ADC
530mW, 79dB SNR, 100dB SFDR
16-Bit, 80Msps ADC
725mW, 77.9dB SNR, 100dB SFDR
16-Bit, 105Msps ADC
900mW, 77.9dB SNR, 100dB SFDR
16-Bit, 130Msps ADC
1250mW, 77.7dB SNR, 100dB SFDR
12-Bit, 170Msps, 2.5V ADC, LVDS Outputs
12-Bit, 210Msps, 2.5V ADC, LVDS Outputs
12-Bit, 250Msps, 2.5V ADC, LVDS Outputs
14-Bit, 65Msps ADC
445mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN
585mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN
745mW, 65.6dB SNR, 80dB SFDR, 64-Pin QFN
210mW, 74dB SNR, 5mm × 5mm QFN
230mW, 73dB SNR, 5mm × 5mm QFN
320mW, 72.5dB SNR, 88dB SFDR, 5mm × 5mm QFN
395mW, 72.4dB SNR, 88dB SFDR, 5mm × 5mm QFN
540mW, 70.1dB SNR, 88dB SFDR, 64-Pin QFN
790mW, 70.2dB SNR, 88dB SFDR, 64-Pin QFN
540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
790mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN
410mW, 71dB SNR, 9mm × 9mm QFN
445mW, 70.6dB SNR, 9mm × 9mm QFN
120mW, 74.4dB SNR, 9mm × 9mm QFN
150mW, 74dB SNR, 9mm × 9mm QFN
240mW, 74dB SNR, 9mm × 9mm QFN
410mW, 74dB SNR, 9mm × 9mm QFN
445mW, 73dB SNR, 9mm × 9mm QFN
14-Bit, 80Msps ADC
14-Bit, 105Msps ADC
14-Bit, 125Msps ADC
Dual 12-Bit, 105Msps ADC
Dual 12-Bit, 125Msps ADC
Dual 14-Bit, 105Msps ADC
Dual 14-Bit, 125Msps ADC
Dual 12-Bit, 65Msps ADC
Dual 12-Bit, 80Msps ADC
Dual 14-Bit, 10Msps ADC
Dual 14-Bit, 25Msps ADC
Dual 14-Bit, 40Msps ADC
Dual 14-Bit, 65Msps ADC
Dual 14-Bit, 80Msps ADC
400MHz to 3.8GHz 3.3V High Linearity
Downconverting RF Mixer
24.7dBm IIP3 at 1.9GHz, NF = 11.7dB, Single-Ended RF and LO Ports,
3.3V Supply
LT5575
800MHz to 2.7GHz High Linearity Direct Conversion 60dBm IIP2 at 1.9GHz, NF = 12.7dB, Low DC Offsets
Quadrature Demodulator
LTC6400-8/LTC6400-14/
LTC6400-20/LTC6400-26
Low Noise, Low Distortion Differential Amplifier for 3V, 90mA, 39.5dBm OIP3 at 300MHz, 6dB NF
300MHz IF, Fixed Gain of 8dB, 14dB, 20dB or 26dB
LTC6401-8/LTC6401-14/
LTC6401-20/LTC6401-26
Low Noise, Low Distortion Differential Amplifier for 3V, 45mA, 45.5dBm OIP3 at 140MHz, 6dB NF
140MHz IF, Fixed Gain of 8dB, 14dB, 20dB or 26dB
9002f
LT 0509 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
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