LTM9100CY#PBF [Linear]
LTM9100 - Anyside™ High Voltage Isolated Switch Controller with I<sup>2</sup>C Command and Telemetry; Package: BGA; Pins: 42; Temperature Range: 0°C to 70°C;
| 型号： | LTM9100CY#PBF |
| 厂家： | 
Linear |
| 描述： | LTM9100 - Anyside™ High Voltage Isolated Switch Controller with I<sup>2</sup>C Command and Telemetry; Package: BGA; Pins: 42; Temperature Range: 0°C to 70°C |
| 文件： | 总54页 (文件大小：1953K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM9100
Anyside™ High Voltage
Isolated Switch Controller with
2
I C Command and Telemetry
FeaTures
DescripTion
The LTM®9100 µModule® (micromodule) controller is a
n
UL-CSA Recognition Pending: 5kV
for One
RMS
2
Minute
complete, galvanically isolated switch controller with I C
n
Reinforced Insulation
interface,foruseasaloadswitchorhotswapcontroller.The
loadissoftstartedandcontrolledbyanexternalN-channel
MOSFET switch. Overcurrent protection minimizes
MOSFET stress during start-up, input step and output
short-circuit conditions. Owing to the isolated, floating
character of the switch, it is easily configured for use in
high side, low side and floating applications.
n
Integrated Isolated Power Supply
n
Adjustable Turn-On Ramp Rate and Current Limit
2
n
n
I C/SMBus Interface
10-Bit ADC Monitors Current and Two
Uncommitted Channels
n
n
n
n
n
n
n
n
High Common Mode Transient Immunity: ≥ 30kV/μs
Fault Status Alert and Power Good Outputs
Independent 3V to 5.5V Logic Supply
±20kV ESD Across the Isolation ꢀarrier
A single 5V supply powers both sides of the switch con-
troller through an integrated, isolated DC/DC converter.
A separate logic supply input allows easy interfacing with
logic levels from 3V to 5.5V, independent of the main
supply. Isolated measurements of load current and two
additional voltage inputs are made by a 10-bit ADC, and
Maximum Continuous Working Voltage: 690V
14.6mm Creepage Distance
Low Current Shutdown Mode (<10µA)
22mm × 9mm × 5.16mm ꢀGA Package
RMS
2
accessed via the I C interface.
2
applicaTions
The logic and I C interface is separated from the switch
controller by a 5kV
isolation barrier, making the
n
RMS
High Voltage DC Hot Swap
LTM9100 ideal for systems where the switch operates on
n
Live ꢀackplane Insertion
buses up to 1000V , as well as for providing galvanic
n
DC
Isolated Distributed Power Systems
isolation in systems where a ground path is broken to al-
low large common mode voltage swings. Uninterrupted
communicationisguaranteedforcommonmodetransients
of up to 30kV/μs.
n
Power Monitors
n
Industrial Control Systems
n
ꢀreaking Ground Loops
L, LT, LTC, LTM, Linear Technology, µModule, LTspice and the Linear logo are registered
trademarks and PowerPath and Anyside are trademarks of Linear Technology Corporation. All
other trademarks are the property of their respective owners.
Typical applicaTion
Isolated High Side Load Switch Driver
270V Load Soft-Start
10nF, 400V
5%
V
UVH
UVL
CC2
1k
EN
RAMP
270V
5V/DIV
1M
LTM9100
DRAIN
V
5V
V
LOAD
100V/DIV
CC
V
Q1
L
GATE
1.5k
FDA50N50
ON
SCL
SDA
I
LOAD
200mA/DIV
+
SENSE
0.01Ω
1%
PG
5V/DIV
GATE
ENABLE
EN
–
SENSE
OV
GND
9100 TA01b
25ms/DIV
LOAD(s)
V
EE
PINS NOT USED IN THIS CIRCUIT:
100µF
400V
ADIN, ADIN2, ADR0, ADR1, ALERT,
ALERT2, EN2, PG, PG2, PGIO, SCL2,
SDA2, SS, TMR, V
S
270V RTN
9100 TA01a
9100f
1
For more information www.linear.com/LTM9100
LTM9100
Table oF conTenTs
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 3
Pin Configuration .......................................... 3
Order Information.......................................... 3
Electrical Characteristics................................. 4
Switching Characteristics ................................ 6
Isolation Characteristics.................................. 8
Typical Performance Characteristics ................... 9
Pin Functions..............................................12
Block Diagram.............................................15
Test Circuits ...............................................16
Applications Information ................................17
Overview................................................................. 17
µModule Technology............................................... 18
DC/DC Converter .................................................... 18
Powering the LTM9100 from the ꢀus ..................... 18
Low Side Applications ............................................ 19
High Side Applications............................................ 19
Switching the PowerPath™.....................................20
FET Short Fault.......................................................27
External Fault Monitor ............................................27
Fault Alerts .............................................................27
Resetting Faults......................................................28
Data Converter........................................................28
Configuring the PGIO Pin........................................28
Design Procedure ...................................................28
Design Example #1.................................................30
Design Example #2.................................................31
External Switch.......................................................32
ꢀoosting Gate Voltage ............................................33
Negative Gate ꢀias..................................................33
Paralleling Switches................................................34
DC ꢀus with AC Ripple (Rectified AC).....................34
2
Inter-IC Communication ꢀus (I C) ..........................36
START and STOP Conditions..................................37
Stuck-ꢀus Reset .....................................................37
2
I C Device Addressing ............................................38
Acknowledge ..........................................................38
Write Protocol.........................................................38
Read Protocol.........................................................38
Alert Response Protocol.........................................39
Single-Wire ꢀroadcast Mode ..................................39
Register Addresses and Contents...........................40
RF, Magnetic Field Immunity ..................................43
PCꢀ Layout.............................................................43
Typical Applications......................................45
Package Description .....................................53
Typical Application .......................................54
Related Parts..............................................54
V Logic Supply......................................................20
L
Hot Plugging Safely ................................................20
Channel Timing Uncertainty ...................................20
Initial Start-Up and Inrush Control..........................20
Power Good Monitors.............................................21
Turn-Off Sequence and Auto-Retry.........................21
Turning the GATE Pin (External FET) On.................23
Overcurrent Protection and Overcurrent Fault ........23
Overvoltage Fault....................................................25
Undervoltage Comparator and Undervoltage
Fault........................................................................25
9100f
2
For more information www.linear.com/LTM9100
LTM9100
absoluTe MaxiMuM raTings
(Notes 1, 2)
UVL, UVH to V ....................................... –0.3V to 10V
EE
V
to GND .................................................. –0.3V to 6V
CC
PGIO to V ............................................... –0.3V to 80V
EE
+
–
–
V to GND .................................................... –0.3V to 6V
L
SENSE to SENSE .................................... –0.3V to 0.3V
V
CC2
to V ............................................... –0.3V to 5.5V
EE
SENSE to V ......................................... –0.3V to 0.3V
EE
V to V (Note 3) ................................. –0.3V to 10.65V
S
EE
Ambient Operating Temperature Range (Note 5)
DRAIN to V (Note 4) ............................. –0.3V to 3.5V
EE
LTM9100C ............................................... 0°C to 70°C
LTM9100I ............................................–40°C to 85°C
LTM9100H......................................... –40°C to 105°C
Maximum Internal Operating Temperature............ 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak ꢀody Reflow Temperature ............................ 245°C
PG, ALERT, EN, SDA, SCL,
ON to GND ......................................–0.3V to (V + 0.3V)
L
SCL2, SDA2, ADR0, ADR1, ALERT2, PG2, ADIN, ADIN2,
RAMP, OV, SS, EN2,
TMR to V .................................–0.3V to (V
+ 0.3V)
EE
CC2
GATE to V .................................. –0.3V to (V + 0.3V)
EE
S
pin conFiguraTion
TOP VIEW
7
V
L
V
V
UVL
UVH
OV
S
CC2
6
V
ON
SCL
PGIO
SCL2
ADIN
CC
5
4
3
2
1
V
EE
ADIN2
SDA
EN
SDA2 ADR0 ADR1 RAMP
EN2
TMR DRAIN
ALERT
ALERT2
SS
GATE
–
+
V
EE
PG
GND
B
PG2
SENSE SENSE
A
C
D
E
F
G
H
J
K
L
M
N
P
R
S
T
BGA PACKAGE
42-LEAD (22mm × 9mm × 5.16mm)
T
JMAX
= 125°C, PCꢀ = JESD51-9 2s2p: θ = 25.6°C/W, θ
= 24.8°C/W, θ
JCbottom Jꢀ
= 11.7°C/W, θ = 12.1°C/W
JA
JCtop
= 100%, θ
JCbottom Jꢀ
= 100%, θ = 100% WEIGHT = 2g
HEAT FLOW: θ = NORMAL, θ
JA
JCtop
orDer inForMaTion
http://www.linear.com/product/LTM9100#orderinfo
PART MARKING
PACKAGE
MSL
RATING
PART NUMBER
LTM9100CY#PꢀF
LTM9100IY#PꢀF
LTM9100HY#PꢀF
PAD OR BALL FINISH
DEVICE
FINISH CODE
TYPE
TEMPERATURE RANGE
0°C to 70°C
SAC305 (RoHS)
LTM9100Y
e1
ꢀGA
3
–40°C to 85°C
–40°C to 105°C
•ꢀ Device temperature grade is indicated by a label on the shipping
container.
•ꢀ Recommended ꢀGA PCꢀ Assembly and Manufacturing Procedures:
www.linear.com/ꢀGA-assy
•ꢀ ꢀGA Package and Tray Drawings: www.linear.com/packaging
•ꢀ Pad or ball finish code is per IPC/JEDEC J-STD-609.
•ꢀ Terminal Finish Part Marking: www.linear.com/leadfree
•ꢀ This product is moisture sensitive. For more information, go to:
www.linear.com/ꢀGA-assy
•ꢀ This product is not recommended for second side reflow. For more
information, go to www.linear.com/ꢀGA-assy
9100f
3
For more information www.linear.com/LTM9100
LTM9100
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, and GND = VEE = 0V, ON = VL unless otherwise noted.
SYMBOL
Supplies
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
Input Supply Range
Input Supply Current
4.5
5.5
V
CC
l
l
I
CC
ON = 0V
0
50
10
70
µA
mA
ON = V , No Load
L
l
V
L
Logic Input Supply Range
Logic Input Supply Current
3
5.5
V
l
l
ON = 0V
0
3.2
10
4.5
µA
mA
ON = V
L
l
V Undervoltage Lockout Threshold V Rising
2.3
2.7
V
L
L
V Undervoltage Lockout
100
mV
L
Hysteresis
l
l
l
l
l
V
V
Regulated Output Voltage
Shunt Regulator Voltage at V
I
= 0mA to 35mA
9.65
10.4
10.4
11.2
370
7
11.15
12
V
V
S
LOAD
I = 10mA, V = 0V
S
Z
S
CC
Shunt Regulator Load Regulation
V Supply Current
I = 10mA to 25mA, V = 0V
S
600
12
mV
mA
V
CC
I
S
V = 10.4V, V = 0V
S CC
S
V Undervoltage Lockout
V Rising, V = 0V
8.5
0.3
9
9.5
S
S
CC
Threshold
l
l
V Undervoltage Lockout
V
= 0V
0.7
5
1.1
V
V
S
CC
Hysteresis
V
CC2
Regulated Output Voltage
I
= 0mA to 15mA
4.75
5.25
LOAD
Gate Drive (EN = V , UVL = UVH = V , OV = 0V, unless otherwise noted)
L
CC2
l
l
V
GATE Pin Output High Voltage
GATE Pin Pull-Up Current
GATE Turn-Off Current
V = 10.4V, V = 0V
9.75
–7.5
10
10.25
–15.5
V
GATEH
S
CC
I
I
V
V
= 4V
–11.5
µA
GATE(UP)
GATE(OFF)
GATE
l
l
= 400mV, V
= 4V
45
120
100
175
150
250
mA
mA
SENSE
GATE
EN = 0V, V
= 4V
GATE
l
l
t
SENSE High to Current Limit
Propagation Delay
V
SENSE
V
SENSE
= 100mV to GATE Low
= 300mV to GATE Low
0.5
0.2
1.5
0.5
µs
µs
PHL(SENSE)
l
l
GATE Off Propagation Delay
0.2
1.4
0.5
2
µs
µs
EN↓ to GATE Low
OV↑, UVL↓ to GATE Low
l
l
l
l
l
Circuit ꢀreaker Gate Off Delay
RAMP Pin Current
440
–18
2.43
–7
530
–20
2.56
–10
12
620
–22
2.69
–13
20
µs
µA
V
V
V
= 300mV to PG2↑
SENSE
I
= 2.56V
RAMP
SS
V
SS Pin Clamp Voltage
SS Pin Pull-Up Current
SS Pin Pull-Down Current
SS
V
SS
= 0V
µA
mA
EN = 0V, V = 2.56V
6
SS
Input Pins
l
EN, ON Input Threshold Voltage
EN, ON Input Hysteresis
UVH Threshold Voltage
UVL Threshold Voltage
UV Hysteresis
0.33ꢀ•ꢀV
0.67ꢀ•ꢀV
V
mV
V
L
L
(Note 6)
150
2.56
2.291
269
l
l
l
V
V
V
UVH
V
UVL
Rising
Falling
2.518
2.248
236
2.598
2.328
304
UVH(TH)
V
UVL(TH)
∆V
UV(HYST)
UVH and UVL Tied Together
mV
mV
V
UVH, UVL Hysteresis
15
δV
UV
l
l
UVL Reset Threshold Voltage
UVL Reset Hysteresis
OV Pin Threshold Voltage
V
V
Falling
1.12
1.21
60
1.30
UVL
mV
V
V
Rising
OV
1.735
1.770
1.805
OV(TH)
9100f
4
For more information www.linear.com/LTM9100
LTM9100
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, and GND = VEE = 0V, ON = VL unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
18
TYP
37.5
50
MAX
62
UNITS
mV
l
l
OV Pin Hysteresis
+
–
Current Limit Sense Voltage
Threshold
SENSE – SENSE
45
55
mV
l
PGIO Pin Input Threshold Voltage
PGIO Pin Input Hysteresis
Input Current
V
Rising
1.10
1.25
100
1.40
V
PGIO
mV
+
l
l
ON, EN, UVH, UVL, OV, SENSE
SENSE
0
–10
±2
–20
µA
µA
–
Timer
l
l
l
TMR Pin High Threshold
TMR Pin Low Threshold
TMR Pin Pull-Up Current
V
V
Rising
Falling
2.43
40
2.56
75
2.69
110
–13
V
mV
µA
TMR
TMR
Turn-On and Auto-Retry (Except OC) Delays,
= 0.2V
–7
–10
V
TMR
l
Power Good and OC Auto-Retry Delays,
= 0.2V
–3.5
–5
–7
µA
V
TMR
l
l
TMR Pin Pull-Down Current
Delays Except OC Auto-Retry, V
= 2.56V
6
3
12
5
20
7
mA
µA
TMR
OC Auto-Retry Delays, V
= 2.56V
TMR
Output Pins
l
V
OH
V
OL
Output High Voltage
Output Low Voltage
ALERT, I
ALERT, I
= –4mA, PG, I
= –2mA
V – 0.4
L
V
LOAD
LOAD
l
l
l
= 4mA, PG, I
= 2mA
0.4
1.6
0.4
V
V
V
LOAD
LOAD
PGIO, I
= 3mA
0.8
0.15
LOAD
ALERT2, PG2, PGIO, I
= 500µA
LOAD
l
l
Input Current
PGIO = 80V
0
10
µA
Short-Circuit Current
0V ≤ ALERT ≤ V
±85
mA
mA
mA
mA
L
0V ≤ PG ≤ V
±30
±30
L
0V ≤ ALERT2, PG2 ≤ V
CC2
l
l
0V ≤ EN2 ≤ V
±2
CC2
ADC
Resolution (No Missing Codes)
Integral Nonlinearity
(Note 6)
10
ꢀits
l
l
INL
SENSE
ADIN, ADIN2
±0.5
±0.25
±2.5
±1.25
LSꢀ
LSꢀ
l
l
Offset Error
SENSE
ADIN, ADIN2
±2.25
±1.25
LSꢀ
LSꢀ
l
l
Full-Scale Voltage
Total Unadjusted Error
Conversion Rate
SENSE
62.8
64
65.2
mV
V
ADIN, ADIN2
2.514
2.560
2.606
l
l
SENSE
ADIN, ADIN2
±1.8
±1.6
%
%
l
l
l
5.5
2
7.3
10
0
9
Hz
MΩ
µA
ADIN, ADIN2 Pin Input Resistance ADIN, ADIN2 = 1.28V
ADIN, ADIN2 Pin Input Current
ADIN, ADIN2 = 2.56V
±2
2
I C Interface
l
l
ADR0, ADR1 Input High Threshold
ADR0, ADR1 Input Low Threshold
ADR0, ADR1 Input Current
V
– 0.8
V
CC2
– 0.5 V – 0.3
V
V
CC2
CC2
0.3
0.5
0.8
l
l
ADR0, ADR1 = 0V, V
±80
µA
µA
CC2
CC2
ADR0, ADR1 = 0.8V, (V
– 0.8V)
±10
0.3ꢀ•ꢀV
l
l
Input Threshold Voltage
SCL, SDA
SDA2
0.7ꢀ•ꢀV
V
V
L
L
0.3ꢀ•ꢀV
0.7ꢀ•ꢀV
CC2
CC2
9100f
5
For more information www.linear.com/LTM9100
LTM9100
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, and GND = VEE = 0V, ON = VL unless otherwise noted.
SYMBOL
PARAMETER
Input Current
Input Hysteresis
CONDITIONS
MIN
TYP
MAX
UNITS
l
SCL, SDA = V or 0V
±2
µA
L
SCL, SDA
SDA2
0.05ꢀ•ꢀV
0.05ꢀ•ꢀV
mV
mV
L
CC2
l
V
V
Output High Voltage
Output Low Voltage
SCL2, I
= –2mA
V – 0.4
CC2
V
OH
LOAD
l
l
SDA, I
= 3mA, SCL2, I
= 2mA
LOAD
0.4
0.45
V
V
OL
LOAD
SDA2, No Load, SDA = 0V
l
Input Pin Capacitance
ꢀus Capacitive Load
SCL, SDA, SDA2 (Note 6)
10
pF
l
l
l
l
SCL2, Standard Speed (Note 6)
SCL2, Fast Speed
SDA, SDA2, SR ≥ 1V/µs, Standard Speed (Note 6)
SDA, SDA2, SR ≥ 1V/µs, Fast Speed
400
200
400
200
pF
pF
pF
pF
Minimum ꢀus Slew Rate
Short-Circuit Current
SDA, SDA2
1
V/µs
l
SDA2 = 0, SDA = V
100
mA
mA
mA
mA
L
0V ≤ SCL2 ≤ V
±30
6
–1.8
CC2
SDA = 0, SDA2 = V
CC2
SDA = V , SDA2 = 0
L
ESD (HBM) (Note 6)
Isolation ꢀoundary
(V , V , V ) to (V , V , GND) in Any Combination
±20
±8
kV
kV
CC2
S
EE
CC
L
Isolated Side Interface Pins
GATE to (V , V ) in Any Combination
S EE
+
–
(RAMP, DRAIN, SENSE , SENSE ) to (V , V ) in
CC2 EE
Any Combination
All Other Pins
±3.5
kV
swiTching characTerisTics
The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, and GND = VEE = 0V, ON = VL unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Logic Timing
l
t
, t
Propagation Delay
Rise and Fall Time
ON Enable Time
ON Disable Time
(PG2, ALERT2) to (PG, ALERT), C = 15pF (Figure 1)
35
60
150
ns
PHL PLH
L
EN to EN2ꢀ(0.5ꢀ•ꢀV toꢀ0.1ꢀ•ꢀV ), C = 15pF (Figure 1)
L
CC2
L
l
l
t , t
ALERT, C = 15pF (Figure 1)
7
30
30
50
ns
ns
R
F
L
PG, C = 15pF (Figure 1)
L
l
t
, t
320
µs
ON↑ to (PG, ALERT), R = 1kΩ, C = 15pF
PZH PZL
L
L
(Figure 2)
l
t
, t
70
ns
ON↓ to (PG, ALERT), R = 1kΩ, C = 15pF (Figure 2)
PHZ PLZ
L
L
2
I C Interface Timing
l
Maximum Data Rate
(Note 7)
SCL to SCL2, C = 15pF (Figure 1)
400
1.3
kHz
l
l
l
t
, t
Propagation Delay
150
150
300
225
250
500
ns
ns
ns
PHL PLH
L
SDA to SDA2, R = Open, C = 15pF (Figure 3)
L
L
SDA2 toSDA, R = 1.1kΩ, C = 15pF (Figure 3)
L
L
Low Period of SCL Clock
(Note 6)
µs
9100f
6
For more information www.linear.com/LTM9100
LTM9100
swiTching characTerisTics
The l denotes the specifications which apply over the specified operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, and GND = VEE = 0V, ON = VL unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
MIN
600
600
600
TYP
MAX UNITS
High Period of SCL Clock
Hold Time (Repeated) Start
Set-Up Time Repeated Start
Data Hold Time
ns
ns
ns
ns
ns
ns
µs
t
t
600
HD(DAT)
Data Set-Up Time
100
600
1.3
SU(DAT)
Set-Up Time for Stop
Stop to Start ꢀus Free Time
Rise Time
l
l
l
t
t
SDA2, C = 200pF (Figure 3)
40
40
350
250
250
ns
ns
ns
R
L
SDA, R = 1.1kΩ, C = 200pF (Figure 3)
L
L
SCL2, C = 200pF (Figure 1)
L
l
l
l
Fall Time
SDA2, C = 200pF (Figure 3)
40
40
250
250
250
ns
ns
ns
F
L
SDA, R = 1.1kΩ, C = 200pF (Figure 3)
L
L
SCL2, C = 200pF (Figure 1)
L
l
l
l
t
t
ON Enable Time
ON Disable Time
320
70
µs
ns
ns
ON↑ to SDA, R = 1kΩ, C = 15pF (Figure 2)
PZL
PLZ
L
L
ON↓ to SDA, R = 1kΩ, C = 15pF (Figure 2)
L
L
Pulse Width of Spikes Suppressed by
Input Filter
SDA, SDA2, SCL
0
50
Power Supply
l
l
Power-Up Time
0.2
0.2
1.5
2
ms
ms
ON↑ to V (Min)
S
ON↑ to V
(Min)
CC2
9100f
7
For more information www.linear.com/LTM9100
LTM9100
isolaTion characTerisTics
Specifications are at TA = 25°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Rated Dielectric Insulation Voltage
1 Minute, Derived from 1 Second Test
1 Second (Notes 8, 9)
5
6
kV
kV
RMS
RMS
Common Mode Transient Immunity
V
= V = ON = 5V, ∆V = 1kV,
30
50
kV/µs
CC
L
CM
∆t = 33ns (Note 6)
V
Maximum Continuous Working Voltage
(Notes 6,10)
1000
690
V
PEAK
RMS
IORM
V
Partial Discharge
V
= 1840V
(Note 8)
5
pC
PD
PEAK
CTI
DTI
Comparative Tracking Index
Depth of Erosion
IEC 60112 (Note 6)
IEC 60112 (Note 6)
(Note 6)
600
1
V
RMS
0.017
0.2
5
mm
Distance Through Insulation
Input to Output Resistance
Input to Output Capacitance
Creepage Distance
mm
TΩ
pF
(Notes 6, 8)
(Notes 6, 8)
5
(Note 6)
14.6
mm
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to 0V
unless otherwise noted.
active. Continuous operation above specified maximum operating junction
temperature may result in device degradation or failure. Thermal shutdown
will result in the loss of the internally generated supply voltages (V and
S
V
CC2
) and subsequent shutdown of the GATE pin. Thermal shutdown is
not internally latched, the part will automatically restart once the junction
2
temperature decreases and start-up conditions are met. Note that any I C
data configuration is lost on power failure.
Note 6: Guaranteed by design and not subject to production test.
Note 7: Maximum data rate is guaranteed by other measured parameters
and is not tested directly.
Note 3: An internal shunt regulator limits the V pin to a minimum of
S
10.65V. Driving this pin to voltages beyond 10.65V may damage the part.
The pin can be safely tied to higher voltages through a resistor that limits
the current to less than 50mA.
Note 4: An internal clamp limits the DRAIN pin to a minimum of 3.5V.
Driving this pin to voltages beyond the clamp may damage the part. The
pin can be safely tied to higher voltages through a resistor that limits the
current to less than 2mA.
Note 8: Device is considered a 2-terminal device. Pin group A1 through ꢀ7
shorted together and pin group P1 through T7 shorted together.
Note 9: The rated dielectric insulation voltage should not be interpreted as
a continuous voltage rating.
Note 5: This µModule includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is
Note 10: The DC continuous working voltage is equivalent to the peak
value.
9100f
8
For more information www.linear.com/LTM9100
LTM9100
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
VCC Supply Current vs
Temperature
VS Output Voltage vs Load
Current
VS Output Voltage vs
Temperature
75
65
55
45
35
25
11.0
10.7
10.4
10.1
9.8
10.50
10.25
10.00
9.75
9.50
9.25
9.00
8.75
8.50
V
V
V
= 4.5V
= 5V
= 5.5V
CC
CC
CC
9.5
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
LOAD CURRENT (mA)
9100 G01
9100 G03
9100 G02
VS Efficiency and Power Loss vs
Load Current
VCC2 Output Voltage vs Load
Current
VCC2 Output Voltage vs
Temperature
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
70
60
50
40
30
20
10
0
2.0
1.7
1.4
1.1
0.9
0.6
0.3
0
5.06
5.04
5.02
5.00
4.98
4.96
4.94
4.92
4.90
V
V
V
= 4.5V
= 5V
= 5.5V
CC
CC
CC
EFFICIENCY
POWER LOSS
100 200
–50 –25
0
25
50
75 100 125
1
10
0
5
10
15
20
25
30
TEMPERATURE (°C)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
9100 G06
9100 G04
9100 G05
Gate Output High Voltage vs
Temperature
Gate Pull-Up Current vs Gate
Voltage
Gate Turn-Off Current vs SENSE
Voltage
–12
–10
–8
–6
–4
–2
0
10.2
10.1
10.0
9.9
100
10
1
V
= 4V
V
= 10.4V
GATE
S
9.8
9.7
0
2
4
6
8
10
12
–50 –25
0
25
50
75 100 125
100
200
300
400
500
0
GATE VOLTAGE (V)
TEMPERATURE (°C)
V
(mV)
SENSE
9100 G08
9100 G07
9100 G09
9100f
9
For more information www.linear.com/LTM9100
LTM9100
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Ramp Pin Current vs Temperature
UVH Threshold vs Temperature
UVL Threshold vs Temperature
–21.0
–20.5
–20.0
–19.5
–19.0
–18.5
–18.0
2.575
2.570
2.565
2.560
2.555
2.550
2.545
2.315
2.310
2.305
2.300
2.295
2.290
2.285
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
9100 G10
9100 G11
9100 G12
Current Limit Voltage vs
Temperature
OV Threshold vs Temperature
OV Hysteresis vs Temperature
1.785
1.780
1.775
1.770
1.765
1.760
1.755
55
50
45
40
35
30
25
51.0
50.5
50.0
49.5
49.0
48.5
48.0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
9100 G13
9100 G14
9100 G15
Current Limit Propagation Delay
(tPHL(SENSE)) vs VSENSE
PG2, PGIO Output Low Voltage vs
Load Current
Logic Input Threshold vs VL
Supply Voltage
6
5
4
3
2
1
0
1000
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
C
= 1pF
PGIO, T = 25°C
GATE
A
PGIO, T = 100°C
A
PG2, T = 25°C
A
INPUT RISING
INPUT FALLING
PG2, T = 100°C
A
100
0
2
4
6
8
10
0
100
200
V
300
400
500
3
3.5
4
4.5
5
5.5
6
LOAD CURRENT (mA)
V
SUPPLY VOLTAGE (V)
(mV)
L
SENSE
9100 G17
9100 G18
9100 G16
9100f
10
For more information www.linear.com/LTM9100
LTM9100
Typical perForMance characTerisTics
TA = 25°C, unless otherwise noted.
Logic Output Voltage vs Load
Current
ADC Total Unadjusted Error vs
Code (ADIN Pin)
ADC Full-Scale Error vs
Temperature (ADIN Pin)
3
2
6
5
4
3
2
1
0
1.0
0.5
V
V
= 5.5V
= 3.3V
L
L
1
0
0
–1
–2
–3
–0.5
–1.0
–50 –25
0
25
50
75 100 125
0
1
2
3
4
5
6
7
8
9
10
512
768
0
1024
256
TEMPERATURE (°C)
LOAD CURRENT (mA)
CODE
9100 G21
9100 G19
9100 G20
Input Current vs Shunt Regulator
Voltage
ADC INL vs Code (ADIN Pin)
ADC DNL vs Code (ADIN Pin)
1.0
0.5
1.0
0.5
25
20
15
10
5
T
T
T
= –50°C
= 25°C
= 125°C
A
A
A
0
0
–0.5
–1.0
–0.5
–1.0
0
512
768
512
768
0
1024
0
1024
256
256
9.8
10.2
10.6
11.0
11.4
11.8
SHUNT REGULATOR VOLTAGE AT V (V)
CODE
CODE
S
9100 G24
9100 G22
9100 G23
Derating for 125°C Maximum
Internal Operating Temperature
Power-On Sequence
500
450
400
350
300
250
200
150
100
50
V
S
2.5V/DIV
V
CC2
2.5V/DIV
ON
5V/DIV
9100 G25
60µs/DIV
0
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
9100 G26
9100f
11
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LTM9100
pin FuncTions
Logic Side
ON (A6): Module Enable Pin. Enables power and data
communication through the isolation barrier. If ON is high
the part is enabled and power and communications are
functional to the isolated side. If ON is low the logic side
is held in reset, all digital outputs are in a high impedance
state, and the isolated side is unpowered. The ON pin may
be used to enable the isolated side power switch driver by
PG(A1):PowerGoodStatusOutput, ReferencedtoV and
L
GND. This logic pin pulls low and stays latched two timer
delays after the isolated side power switch is on (when
GATE reaches approximately 9.5V and DRAIN is within
1.77V of V ). The power good output is reset in all GATE
EE
pull-down events except an overvoltage fault. Under the
conditionofanisolationcommunicationfailurethisoutput
is in a high impedance state. A communication failure may
occur due to extreme electromagnetic events including
common mode transients or electrical overstress. Com-
munication is automatically re-established if permanent
damage has not occurred.
connecting EN to V . A low to high transition of ON would
L
then enable the isolated side gate drive after the internal
isolated side supply voltage exceeds approximately 9V
followed by a timer delay. Connect to V if not used.
L
V (A7): Logic Supply. Interface supply voltage for pins
L
PG, ALERT, EN, SDA, SCL, and ON. Operating voltage is
3V to 5.5V. Internally bypassed with 1µF.
ALERT(A2):FaultAlertOutput,ReferencedtoV andGND.
L
This logic pin pulls low when an isolated side fault occurs
GND (B1 TO B5): Circuit Ground.
2
as configured by the I C ALERT register. See Applications
V
(B6, B7): Isolated Power Converter Supply Voltage.
CC
Information. Under the condition of an isolation commu-
nication failure this output is in a high impedance state.
Operatingvoltageis4.5Vto5.5V.Internallybypassedwith
1µF. This pin may be left unconnected or grounded if V
is driven by an external voltage.
S
EN (A3): GATE Enable Input, Referenced to V and GND.
L
A rising edge turns on the isolated side GATE pin while a
falling edge turns it off. This pin is also used to configure
Isolated Side
2
the state of bit 3 (GATE_CTRL) in the I C CONTROL (D)
PG2 (P1): Power Good Status Output, Referenced to V
CC2
register(andhencetheGATEpin)atpower-up.Forexample
if EN is tied high, then register bit D3 goes high one timer
cycle after power-up. Likewise, if the EN pin is tied low,
then the GATE pin remains low after power-up until the EN
pin is transitioned high. The GATE pin may be controlled
and V . This logic pin pulls low and stays latched two
EE
timer delays after the power switch is on (when GATE
reaches approximately 9.5V and DRAIN is within 1.77V of
V ). ThepowergoodoutputisresetinallGATEpull-down
EE
events except an overvoltage fault. Internally connected
2
directly by I C via register bit D3. A high to low transition
to V
by a 10k resistor.
CC2
clears any driver faults. Connect to V if not used.
L
ALERT2 (P2): Fault Alert Output, Referenced to V and
CC2
2
SDA (A4): Serial I C Data Pin, Referenced to V and GND.
L
V . This logic pin pulls low when an isolated side fault
EE
2
BidirectionallogicpinconnectedtoisolatedsideSDA2pin
and configurable switch driver through isolation barrier.
An external pull-up resistor or current source is required.
Under the condition of an isolation communication failure
occurs as configured by the I C ALERT register. See
Applications Information. Internally connected to V
through a 10k resistor.
CC2
EN2 (P3): Enable Output, Referenced to V
and V .
EE
CC2
this pin is in a high impedance state. Connect to V if not
used.
L
Logic output connected to logic side EN pin through isola-
tion barrier and 4k resistor and to the switch driver. EN2
may be driven externally, see Applications Information.
2
SCL (A5): Serial I C Clock Pin, Referenced to V and
L
GND. Logic input connected to isolated side SCL2 pin
and configurable switch driver through isolation barrier.
An external pull-up resistor or current source is required.
Internally connected to V through 4k and 10k resistors.
EE
2
SDA2 (P4): Serial I C Data Pin, Referenced to V
EE
and
CC2
V . Bidirectional logic pin connected to logic side SDA
Connect to V if not used.
L
pin through isolation barrier and to the switch driver. Al-
2
lows for I C bus expansion. Output is biased high by a
9100f
12
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LTM9100
pin FuncTions
1.8mA current source. Under the condition of an isolation
communication failure this output defaults to a high state.
age fault). Pin connected internally to a 47nF capacitor,
additional external capacitance (C
) may be added to
TMR
extend the nominal delay beyond 12ms. Internal pull-up
currents of 10µA and 5µA and pull-down currents of 5µA
and 12mA configure the delay periods as multiples of a
2
SCL2(P5):SerialI CClockOutput,ReferencedtoV and
CC2
V . Logic output connected to logic side SCL pin through
isolationbarrierandtotheswitchdriver.AllowsforI Cbus
expansion. Clock is unidirectional from logic to isolated
side. Under the condition of an isolation communication
failure this output defaults to a high state.
EE
2
nominal delay t = 12ms + 256msꢀ•ꢀC
/µF. Delays for
D
TMR
power-up and auto-retry following an undervoltage fault
are the same as the nominal delay. Delays for sequenced
power good outputs are twice the nominal delay. Delay
for auto-retry following overcurrent fault are four times
the nominal delay.
PGIO (P6): General Purpose Input/Output. Logic input
and open-drain output. Default is output which pulls low
two timer delays after the PG pin goes low to indicate a
secondpowergoodoutput.ConfigureaccordingtoTable4.
ADIN2, ADIN (S5, S6): ADC Inputs, Referenced to V .
EE
A voltage between 0V and 2.56V applied to these pins is
V (P7): 10.4V Nominal Isolated Supply Output Voltage.
measured by the internal module ADC. Connect to V if
S
EE
Internally generated from V by an isolated DC/DC con-
unused.
CC
verter and regulated to 10.4V. V may be driven by an
S
V
(S7): 5V Nominal Isolated Supply Output Voltage.
CC2
external supply if V is not connected or grounded. If
CC
Linear regulated output generated from V with a UVLO
S
drivenexternallyconnectpintoapositivesupplythrougha
threshold of 4.25V. This voltage powers up the isolated
data converter and logic control circuitry. Internally by-
passed with 1µF.
droppingresistor,seeApplicationsInformation.Aninternal
shunt regulator clamps V (V ) at 11.2V. An undervoltage
S
Z
lockout (UVLO) circuit holds GATE low until V is above
S
+
9V. Internally bypassed with 1µF.
SENSE (T1): Positive Current Limit Sense Input. Load
current through an external current sense resistor (R ) is
S
V
EE
(R1 to R3, R5 to R7): Isolated Circuit Common.
monitoredandcontrolledbyanactivecurrentlimitamplifier
ADR0, ADR1 (R4, S4): Serial Bus Address Inputs, Refer-
encedtoV andV . ConnectingthesepinstoV , V
or floating configures one of nine possible addresses. See
Table 1 in Applications Information.
to 50mV/R . Once V
reaches 50mV, a circuit breaker
S
SENSE
,
EE CC2
timer starts and turns off the switch after 530µs. In the
event of a catastrophic short-circuit, if V crosses
CC2
EE
SENSE
250mV, a fast response comparator immediately pulls
the GATE pin down to turn off the MOSFET. Internally
filtered with 220pF.
–
SENSE (S1): Negative Current Limit Sense Input. Kelvin
connection for external current sense resistor (R ). Inter-
S
nally filtered with 220pF.
GATE (T2): N-Channel MOSFET Switch (FET) Gate Drive
Output. This pin is pulled up by an internal current source
SS (S2): Soft-Start Input. This pin is used to ramp inrush
currentduringstart-up,therebyeffectingcontroloverdi/dt.
Pin connected internally to a 220nF capacitor, additional
I
(11.5µA when the SS pin reaches its clamping volt-
GATE
age). GATE stays low until V and V
cross the UVLO
S
CC2
thresholds, EN is high, UV and OV conditions are satisfied
and the adjustable power-up timer delay expires. During
turn-off,causedbyfaultsorundervoltagelockout,a110mA
externalcapacitance(C )maybeadded.Aninternal10µA
SS
current source charges the internal and external capaci-
tance creating a voltage ramp. This voltage is converted
to a current to charge the GATE pin up and to ramp the
output voltage down. The SS pin is internally clamped
pull-down current between GATE and V is activated.
EE
Internally filtered with 220pF. Under the condition of an
isolation communication failure the switch is turned off.
to 2.56V limiting I
to 11.5µA and I
to 20µA.
GATE(UP)
RAMP
DRAIN (T3): Drain Sense Input. Connect an external re-
sistor between this pin and the drain terminal of the FET.
Size the resistor for 50µA nominal current, do not exceed
TMR (S3): Delay Timer Input. This pin is used to create
timing delays at power-up, when power good outputs pull
downandwhenauto-retryingafterfaults(exceptovervolt-
9100f
13
For more information www.linear.com/LTM9100
LTM9100
pin FuncTions
2mA. The voltage at this pin is internally clamped to 4V.
When the DRAIN pin voltage is less than 1.77V and the
GATE pin voltage is approximately 9.5V the power good
outputisassertedaftertwotimerdelays. Internallyfiltered
with 220pF.
OV (T5): Overvoltage Detection Input. Connect this pin
to an external resistive divider from V . If the voltage
EE
at this pin rises above 1.77V, the FET is turned off. The
overvoltage condition does not affect the status of the
powergoodoutputs.Internallyfilteredwith10nF.Connect
to V if not used.
EE
RAMP (T4): Inrush Current Ramp Control Pin. The inrush
current is adjusted by placing a capacitor (C ) between
UVH(T6):UndervoltageHighLevelInput.Connectthispin
R
the RAMP pin and the drain terminal of the FET. At start-
to an external resistive divider from V . If the voltage at
EE
up, the GATE pin is pulled up by I
begins to turn on. A current, I
until the FET
, then flows through
the UVH pin rises above 2.56V and UVL is above 2.291V,
GATE(UP)
RAMP
the FET is allowed to turn on. Internally filtered with 10nF.
C to ramp down the drain voltage. The value of I
R
is
Connect to V
if not used.
RAMP
CC2
controlled by the SS pin voltage. When the SS pin reaches
its clamp voltage (2.56V), I = 20µA. For a capacitive
UVL (T7): Undervoltage Low Level Input. Connect this pin
RAMP
to an external resistive divider from V . If the voltage at
EE
load the RAMP rate of the FET drain voltage (V
) and
DRAIN
INRUSH
the UVL pin drops below 2.291V and UVH is below 2.56V,
the FET is turned off and the power good outputs go high.
Pulling this pin below 1.21V resets faults and allows the
the load capacitor C set the inrush current: I
= (C
L
L
/C )ꢀ•ꢀI
. Internallyfilteredwith10nF;seeApplications
R
RAMP
Information.
FET to turn back on. Connect to V
if unused.
CC2
9100f
14
For more information www.linear.com/LTM9100
LTM9100
block DiagraM
V
CC
V
S
REGULATOR
1µF
V
L
61.9k
1µF
1µF
GND
8.2k
V
EE
10nF
10nF
10nF
1µF
V
DC/DC
CONVERTER
CC2
V
CC
ISOLATED
COMMUNICATIONS
INTERFACE
ISOLATED
COMMUNICATIONS
INTERFACE
ON
10k
10k
10k
UVL
UVH
OV
SCL
SDA
EN
4k
RAMP
DRAIN
GATE
SWITCH
CONTROLLER
PG
+
SENSE
ALERT
–
SENSE
V
L
220pF
220pF
220pF
220pF
220nF
ISOLATION
BARRIER
47nF
SS
ALERT2
PG2
SDA2
SCL2
EN2
ADR0
ADR1 ADIN
ADIN2
PGIO
TMR
9100 BD
9100f
15
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LTM9100
TesT circuiTs
V
L
EN
1/2 V
L
SCL
0V
t
t
PHL
PLH
EN2
SCL2
EN
SCL
V
OH
C
L
90%
10%
EN2
SCL2
1/2 V
CC2
10%
90%
V
OL
t
R
t
F
PG
ALERT
V
CC2
PG2
ALERT2
PG2
ALERT2
1/2 V
CC2
C
L
0V
t
t
PLH
PHL
V
OH
90%
10%
PG
ALERT
1/2 V
L
10%
90%
V
OL
t
R
t
F
9100 F01
Figure 1. Logic Timing Measurements
V
L
1/2 V
ON
L
V
OR 0V
L
0V
t
t
PHZ
PZH
R
L
V
OH
PG2
ALERT2
SDA2
PG
ALERT
SDA
V
– 0.5V
OH
1/2 V
L
0V
PG
ALERT
SDA
C
t
PLZ
L
t
PZL
ON
V
L
1/2 V
L
V
+ 0.5V
OL
V
OL
9100 F02
Figure 2. ON Enable/Disable Time
V
L
V
L
SDA
1/2 V
L
R
0V
L
t
t
PLH
PHL
SDA2
V
OH
30%
70%
SDA
C
1/2 V
CC2
70%
L
SDA2
30%
V
OL
t
F
t
R
V
L
V
CC2
1/2 V
SDA2
CC2
R
L
0V
SDA
t
t
PLH
PHL
C
SDA2
L
V
OH
30%
70%
1/2 V
70%
L
SDA
30%
V
OL
t
R
t
F
9100 F03
Figure 3. I2C Timing Measurements
9100f
16
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LTM9100
applicaTions inForMaTion
Overview
The isolated side logic circuits are powered by an inter-
nally generated 5V supply (V ). Prior to turning on the
CC2
The LTM9100 µModule switch controller provides a
galvanically-isolatedrobustdriverinterface,completewith
decoupling capacitors. The LTM9100 is ideal for use in
networks where grounds can take on different voltages.
Isolation in the LTM9100 blocks high voltage differences
and eliminates ground loops and is extremely tolerant of
common mode transients between ground planes. Error-
freeoperationismaintainedthroughcommon-modeevents
as fast as 70kV/μs providing excellent noise isolation.
FET, both the internal gate drive supply voltage V and
S
V
voltages must exceed their undervoltage lockout
CC2
thresholds. In addition, the control inputs UVH, UVL, OV
and EN are monitored. The FET is held off until all start-up
conditions are met.
A 10-bit analog-to-digital converter (ADC) is included in
the LTM9100. The ADC measures the SENSE voltage as
well as voltages at the ADIN2 and ADIN pins, for auxiliary
functionssuchassensingbusvoltageortemperature,etc.
The LTM9100 is designed to turn a supply voltage on and
off in a controlled manner. In normal operation after initial
power up and time delay (TMR), the GATE pin turns on a
FET passing power to the load. The GATE pin is powered
by an internal isolated DC/DC converter with output volt-
2
An I C interface is provided to read the ADC data registers.
It also allows the host to poll the device and determine
if a fault has occurred. If the ALERT line is used as an
interrupt, the host can respond to a fault in real time. Two
three-state pins, ADR0 and ADR1, are used to program
eight possible device addresses.
age (V ) of approximately 10.4V.
S
An amplifier connected to the SENSE pins is used for
overcurrent and short-circuit protection. It monitors the
The interface can also be pin configured for a single-wire
broadcastmode,sendingADCdataandfaultstatusthrough
the SDA pin to the host without clocking the SCL line.
This single-wire, one-way communication can simplify
system design.
load current through an external sense resistor R . In an
S
overcurrent condition, the current is limited to 50mV/R
S
by regulating GATE. If the overcurrent condition remains
for more than 530μs, GATE is turned off.
TheDRAINandGATEvoltagesaremonitoredtodetermine
if the FET is fully enhanced. Upon successful turn on of
the FET, two power good signals are presented on the PG
and PGIO pins. They allow enabling and sequencing of
loads. The PGIO pin can also be configured for a general
purpose input or output.
The LTM9100 is ideally suited for distributed DC power
systems and off-line power converter systems requiring
an isolated communication and control interface. A basic
200W –48V distributed power application circuit using
the LTM9100 is shown in Figure 4.
9100f
17
For more information www.linear.com/LTM9100
LTM9100
applicaTions inForMaTion
µModule Technology
primary voltage, and is rectified by a symmetric voltage
doubler. This topology reduces common mode voltage
perturbations on the isolated side ground, and eliminates
transformer saturation caused by secondary imbalances.
The LTM9100 utilizes isolator µModule technology to
translate signals and power across an isolation barrier.
Signalsoneithersideofthebarrierareencodedintopulses
and translated across the isolation boundary using core-
less transformers formed in the µModule substrate. This
system, complete with data refresh, error checking, safe
shutdown on fail, and extremely high common mode im-
munity, provides a robust solution for bidirectional signal
isolation. The µModule technology provides the means to
combinetheisolatedsignalingwithmultipleregulatorsand
powerful isolated DC/DC converter in one small package.
The DC/DC converter is connected to a low dropout
regulator (LDO) to provide a regulated 10.4V output (V )
S
for the GATE driver supply. V is decoupled internally by
S
a 1µF capacitor.
The data converter and logic control circuits are powered
by an internal linear regulator that derives 5V from the
V supply. The 5V output is available at the V
pin for
S
CC2
driving external circuits (up to 15mA load current). V
CC2
is decoupled internally by a 1µF capacitor.
DC/DC Converter
TheLTM9100containsafullyintegratedDC/DCconverter,
includingthetransformer,sothatnoexternalcomponents
are necessary for powering the isolated side. The logic
side contains a full-bridge driver, running at 2MHz, and is
AC-coupled to a single transformer primary. A series DC
blocking capacitor prevents transformer saturation due to
driver duty cycle imbalance. The transformer scales the
Powering the LTM9100 from the Bus
The internal isolated power converter may be disabled by
floatingorgroundingtheV pin.Isolatedpowermaythen
CC
be derived from the external bus voltage by using either a
low or high side circuit depending upon the application’s
location of the LTM9100.
–48V RTN
R3
453k
1%
R2
16.9k, 1%
R1
11.8k, 1%
+
V
IN
MODULE 2
UVH
UVL
OV
+
V
IN
4.5V TO 5.5V
3V TO 5.5V
V
V
ON
CC
L
PGIO
ON
–
MODULE 1
Q2
BSS123
V
IN
ON
1.5k
1.5k
PG2
–
V
IN
LTM9100
STANDARD
LOGIC
SCL
SDA
SCL
SDA
EN
ALERT
PG
V
CC2
C
L
LEVEL GATE ENABLE
FAULT ALERT
(3V TO 5.5V) POWER GOOD
330µF
100V
R4
10k, 1%
SIGNALING
ADIN
–
+
GND
V
EE
SENSE SENSE
GATE DRAIN RAMP
R , 10Ω
G
R
1k
R
R5
402k
1%
R
D
C
G
C
10nF
5%
1M
R
47nF
R
S
100V
–48V INPUT
9100 F04
0.008Ω
1%
Q1
IRF1310
PINS NOT USED IN THIS CIRCUIT:
ADIN2, ADR0, ADR1, ALERT2, EN2,
SCL2, SDA2, SS, TMR, V
S
Figure 4. –48V/200W Low Side Hot Swap Controller Using LTM9100 with Current and Input Voltage
Monitoring (5.6A Current Limit, 0.66A Inrush)
9100f
18
For more information www.linear.com/LTM9100
LTM9100
applicaTions inForMaTion
Low Side Applications
near V . Initially the LTM9100 can be powered directly
EE
from the bus until the FET drain drops below the minimum
Isolated power may be derived through a current limiting
V voltage for operation. Note the V supply current flows
S
S
resistor (R ) to the V pin (Figure 5) for low side con-
LIM
S
through the load and will charge any load capacitance
even when GATE is off. If the LTM9100 is configured to
turn on the GATE upon application of bus voltage this is
not an issue.
figurations where V is referenced to the negative side of
EE
thebussupplyvoltage. Aninternalshuntregulatorclamps
the voltage at V to 11.2V (V ) and provides power to the
S
Z
GATE driver. R should be chosen to accommodate the
LIM
maximum isolated side supply current requirement of
the LTM9100 (10mA), plus the supply current required
by any external devices connected to V and V , at the
minimum VBUS operation voltage. Alternative means of
current limiting can also be used, e.g. an analog (active)
current limiter (ACL).
For bus voltages ≤100V the circuit of Figure 7 may be
used. The step-up converter circuit provides an output
voltage ~12V higher than the bus voltage, connecting to
S
CC2
V through an ACL (depletion MOSFET Q1, R ). For bus
S
LIM
voltages >100V it is necessary to preregulate the input
voltage to the step up converter, as shown in Figure 8.
Any type of step up converter can be used to provide the
boosted voltage: flyback, boost, charge pump, etc. Tran-
sistors Q1, Q3, and diode D1 must be selected based on
the bus voltage and power dissipation.
VBUS(MIN) – VZ(MAX)
RLIM
≤
IS(EXT) + ICC2(EXT) + 10mA
+
VBUS
R
LIM
V
S
V
CC
R
Q1
LIM
1µF
50Ω BSP129
+
VBUS
D1
BAS21
LTM9100
150µH*
V
S
V
CC
V
SW
IN
EN
LT8300
GND
V
EE
LTM9100
130k
9100 F05
1µF
RFB
GND
–
VBUS
Figure 5. Isolated Side Power Derived From External Bus
–
GND
VBUS
V
EE
*COILCRAFT LPS4018-154
9100 F07
2
[VBUS(MAX) – VZ(MIN)
]
PMAX
=
Figure 7. VS Supply for VBUS ≤ 100V
RLIM
1µF
+
+
VBUS
VBUS
D1
BAS21
Q2
150µH*
100Ω
MMDT5401
V
OR V
CC2
BCP56
9.7V OR 4.3V
S
DZ
91V
V
IN
EN
SW
9100 F06
130k
LT8300
RFB
1µF
Figure 6. NPN Buffer Relieves RLIM of Excessive Dissipation
when Supplying External Loads
GND
Q3
*COILCRAFT LPS4018-154
High Side Applications
100k
–
For high side applications it is necessary to generate a
VBUS
9100 F08
voltage > V volts above the bus voltage to power the
Z
Figure 8. Preregulator for VBUS > 100V
LTM9100 once the FET is fully conducting; drain voltage
9100f
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LTM9100
applicaTions inForMaTion
Switching the PowerPath™
Hot Plugging Safely
For either low side or high side configuration, the internal
DC/DC converter may be subsequently enabled and ex-
ternal isolated side converter disabled to minimize power
dissipation. The circuit of Figure 9 uses the power good
signals to automatically switch the power converter path
once the main FET is on.
Caution must be exercised in applications where power is
plugged into the LTM9100’s power supplies, V or V ,
CC
L
due to the integrated ceramic decoupling capacitors. The
parasitic cable inductance along with the high-Q char-
acteristics of ceramic capacitors can cause substantial
ringing which could exceed the maximum voltage ratings
and damage the LTM9100. Refer to Linear Technology
Application Note AN88, entitled Ceramic Input Capacitors
CanCauseOvervoltageTransientsforadetaileddiscussion.
Q1
BSP129
R
, 50Ω
LIM
100k
V
S
5V
V
L
ON
EN
PGIO
LTM9100
Channel Timing Uncertainty
V
CC
Multiplechannelsaresupportedacrosstheisolationbound-
ary by encoding and decoding of the inputs and outputs.
Up to three signals are assembled as a serial packet and
transferred across the isolation barrier. The time required
to transfer all three bits is 50ns typical, and sets the limit
for how often a signal can change on the opposite side of
the barrier. The technique used assigns SCL on the logic
side and PG2 on the isolated side the highest priority such
that there is no jitter on the associated output channels,
only delay. This preemptive scheme will produce a certain
amountofuncertaintyontheotherisolationchannels. The
resulting pulse width uncertainty on these low priority
channels is typically ±±ns, but may vary up to ±ꢀꢀns if
the low priority channels are not encoded within the same
high priority serial packet.
100k
Q2
PG
GND
V
EE
9100 F09
Figure 9. External-to-Internal PowerPath Switch-Over
V Logic Supply
L
A separate logic supply pin V allows the LTM9100 to
L
interface with any logic signal from 3V to 5.5V as shown
inFigure10.SimplyconnectthedesiredlogicsupplytoV .
L
There is no interdependency between V and V ; they
CC
L
may simultaneously operate at any voltage within their
specified operating ranges and sequence in any order.
V
CC
and V are decoupled internally by 1µF capacitors.
L
Initial Start-Up and Inrush Control
SeveralconditionsmustbesatisfiedbeforetheFETturn-on
ANY VOLTAGE FROM
3V TO 5.5V
4.5V TO 5.5V
sequence is started. First the voltage at V must exceed
S
its 9V undervoltage lockout level. Next the internal sup-
V
V
V
CC
1.5k 1.5k
CC
L
ply V must cross its ꢀ.25V undervoltage lockout level.
CC2
LTM9100
ON
This generates a 100μs to 1±0μs power-on-reset pulse
during which the FAULT register bits are cleared and the
CONTROL register bits are set or cleared as described in
the register section. After the power-on-reset pulse, the
voltages at the UVH, UVL and OV pins must satisfy UVH
> 2.5±V, UVL > 2.291V and OV < 1.77V. All the above
conditions must be satisfied throughout the duration of
the start-up delay that is set by a combination of internal
EXTERNAL
DEVICE
SCL
SDA
EN
ALERT
PG
GND
GND
9100 F10
Figure 10. VCC and VL Are Independent
and external (C
) capacitance connected to the TMR
TMR
pin. C
is charged with a pull-up current of 10µA until
TMR
9100f
20
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LTM9100
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the voltage at TMR reaches 2.5±V. C
is then quickly
Duringliveboardinsertionorinputpowerstep, aninternal
TMR
discharged with a 12mA current. The initial delay expires
when TMR is brought below 75mV. The duration of the
start-up delay is given by:
clamp turns on to hold the RAMP pin low. Resistor R
R
and an internal 10nF capacitor to V suppress noise at
EE
the RAMP pin. For proper operation, R ꢀ•ꢀC should not
R
R
exceed 50µs. Additional capacitance may be added from
CTMR
tD ≅ 12ms + 25±ms•
1µF
RAMP to V for additional noise filtering.
EE
Power Good Monitors
If any of the above conditions is violated before the start-
When the voltage across the FET falls below 1.77V and
GATE pulls above approximately 9V, an internal power
good signal is latched and a series of two delay cycles
are started as shown in Figure 11. When the first delay
up delay expires, C
is quickly discharged and the
TMR
turn-on sequence is restarted. After all the conditions
are validated throughout the start-up delay, the EN pin
is then checked. If it is high, the FET will be turned on.
Otherwise, the FET will be turned on when the EN pin is
raised or bit 3 (GATE_CTRL) in the CONTROL (D) register
cycle with a duration of 2t expires, the PG2 and PG pins
D
pull low as power good signals. When the second delay
2
cycle (2t ) expires, the PGIO pin pulls low as another
D
is set to 1 through the I C interface, when configured for
2
power good signal. The 2t timer delay is obtained by
D
I C only control.
charging the capacitance on TMR with a 5µA current and
discharging with 12mA when TMR reaches 2.5±V. The
power good signals at PG and PGIO are reset in all FET
turn-off conditions except the overvoltage fault.
The FET turn-on sequence follows by charging an internal
and external (C ) capacitor at the SS pin with a 10µA
SS
pull-up current and the voltage at SS (V ) is converted
SS
to a current (I
) of 11.5μAꢀ•ꢀV /2.5±V for GATE
GATE(UP)
SS
pull-up. When the GATE reaches the FET threshold volt-
age, current starts to flow through the FET and a current
Turn-Off Sequence and Auto-Retry
In any of the following conditions, the FET is turned off by
pulling down GATE with a 110mA current, and the capaci-
tancesatSSandTMRaredischargedwith12mAcurrents.
(I
) of 20μAꢀ•ꢀV /2.5±V flows out of the RAMP pin
RAMP
SS
andthroughanexternalcapacitor(C )connectedbetween
R
RAMP and the drain voltage. The SS voltage is clamped
to 2.5±V, which corresponds to I
= 11.5µA and
GATE(UP)
1. The EN (or EN2) pin is low or register bit D3 is set to 0.
I
= 20μA. The RAMP pin voltage is regulated at 1.1V
RAMP
2. The voltage at UVL is lower than 2.291V and the voltage
at UVH is lower than 2.5±V (undervoltage fault).
and the ramp rate of V
for capacitive load:
determines the inrush current
DRAIN
3. The voltage at OV is higher than 1.77V (overvoltage
fault).
CL
CR
IINRUSH =20µA •
ꢀ. The voltage at V is lower than 8.5V (V undervoltage
S
S
lockout).
The ramp rate of V determines the di/dt of the inrush
SS
current:
5. ThevoltageatV islowerthanꢀ.25V(V undervolt-
CC2
CC2
age lockout).
±. V
dI
CL
1µF
INRUSH
dt
=20µA •
•
> 50mV and the condition lasts longer than
CR 25±ms•(C +220nF)
SENSE
SS
530μs (overcurrent fault).
If C is absent externally, the SS ramps from 0V to 2.5±V
SS
For conditions 1, ꢀ, 5, after the condition is cleared, the
LTM9100willautomaticallyentertheFETturn-onsequence
as previously described.
in approximately 5±ms.
When V
is ramped down to V , I
returns
GATEH
DRAIN
EE GATE
to the GATE pin and pulls the GATE up to V
.
Figure11illustratesthestart-upsequenceoftheLTM9100.
9100f
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LTM9100
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For any of the fault conditions 2, 3, ±, the FET off mode is
programmable by the corresponding auto-retry bit in the
CONTROL register. If the auto-retry bit is set to 0, the FET
is latched off upon the fault condition. If the auto-retry bit
is set to 1, after the fault condition is cleared, the delay
timer is started. After the timer expires, the FET enters the
auto-retry mode and GATE is pulled up. The auto-retry
delay following the undervoltage fault has a duration of
D
t . The auto-retry delay following the overcurrent fault has
a duration of ꢀt for extra cooling time. The auto-retry
D
following the overvoltage fault does not have a delay.
The auto-retry control bits and their defaults at power up
are listed in Table ꢀ. Note that the LTM9100 defaults to
latch-off following the overcurrent fault.
UVLO
V
= V
CC
L
ON
UVLO
UVLO
V
S
V
CC2
INTERNAL POR
PG2
PG
PGIO
DRAIN
1.77V
2.56V
UVH
2.291V
UVL
1.77V
OV
TMR
EN
START-UP
1x DELAY
2x
2x
4x
EN2
SS
GATEH
V
GATE
TH
LOAD1 + LOAD2
50mV
di/dt
LOAD1
SENSE
INRUSH
INTERNAL POWER GOOD
9100 F11
Figure 11. LTM9100 Turn-On Sequence
9100f
22
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LTM9100
applicaTions inForMaTion
Turning the GATE Pin (External FET) On
voltage is applied provided the EN pin is tied high, without
interfering with the GATE signal.
Many methods of on/off control are possible using the
2
ON, EN, EN2, UV/OV or PGIO pins along with the I C port.
Ejector Switch or Loop-Through Connection Sense:
Floating switch contacts, or a connection sense loop work
well with the EN or EN2 pins. Figure 12c illustrates this
configuration using the EN2 pin and includes a debounce
delay.
The EN pin works well with logic inputs or floating switch
2
contacts; I C control is intended for systems where the
board operates only under command of a central control
processor and the ON pin is useful with systems with low
standby current requirements. The UV (UVH, UVL) and
Short Pin to RTN: Figure 12d uses the UV divider string
to detect board insertion. The short pin connection could
also be wired to work in conjunction with either the ON
or EN pins.
OV pins are useful with signals referenced to V . PGIO
EE
2
controls nothing directly, but is useful for I C monitoring
of connection sense or other important signals.
2
2
On/off control is possible with or without I C intervention.
2
I C Only Control: To lock out EN and ON, use the configu-
Even when operating autonomously, the I C port can still
ration shown in Figure 12e and control the GATE pin with
register bit D3. The circuit defaults off at power up with
exercise control over the GATE output, although depend-
ing on how they are connected, EN, EN2, and ON could
EN2 tied to V . To default on, do not connect EN2. The
EE
2
subsequently override conditions set by I C. UV, OV and
PGIO pin can be used as an input to monitor a connec-
tion sense or other control signal. PGIO is configured as
an input by setting register bits D± and D7 high; its input
state is stored at register bit A±.
other fault conditions seize control as needed to turn off
the GATE output, regardless of the state of EN, EN2, ON
2
or the I C port. Figure 12 shows five configurations of on/
off control of the LTM9100.
Overcurrent Protection and Overcurrent Fault
Logic Control with Isolation: Figure 12a shows an
application using logic signal control. Rising and falling
edges of either the ON pin or EN pin, with alternate pin
tied high, turn the GATE output on and off. Rising edge
control of ON results in a delay of the GATE signal by
The LTM9100 features two levels of protection from
short-circuit and overcurrent conditions. Load current is
monitored by the SENSE pins and resistor R . There are
S
two distinct thresholds for the voltage at SENSE: 50mV
for engaging the active current limit loop and starting a
530μs circuit breaker timer and 250mV for a fast GATE
pull-downtolimitpeakcurrentintheeventofacatastrophic
short-circuit or an input step.
the power converter turn-on time and one t period, the
D
fallingedgewillalsobedelayedbytheconverterdischarge
time (stored energy) and supply loading on V and V
.
S
CC2
The GATE will respond immediately to changes on the
EN pin. The status of EN can be examined or overridden
2
In an overcurrent condition, when the voltage drop across
through the I C port at register bit D3. Register bit D3 is
R exceeds 50mV, the current limit loop is engaged and
S
set low whenever V
drops below its UVLO threshold.
CC2
an internal 530μs circuit breaker timer is started. The
The status of the GATE pin output is indicated by register
bit A7 (GATE_STAT), which is equal to register bit D3 and
the absence of UV, OV, and other faults.
current limit loop servos the GATE to maintain a constant
output current of 50mV/R . When the circuit breaker
S
timer expires, the FET is turned off by pulling GATE down
with a 110mA current, the capacitors at SS and TMR are
discharged and the power good signals are reset. At this
time, the overcurrent present bit A2 and the overcurrent
fault bit B2 are set, and the circuit breaker timer is reset.
BootstrappedPowerConnection:Figure12bshowsalow
sideapplicationwithcontrolpowerderivedontheisolated
side. With EN2 tied high on the isolated side, GATE rises
one t period after power is applied. The logic supply (V )
D
L
or ON pin may be toggled either before or after the bus
9100f
23
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LTM9100
applicaTions inForMaTion
5V
V
V
5V
V
V
CC
L
CC
L
EN
ON
ON
EN
ON
OFF
ON
OFF
GND
GND
9100 F12a
12(a) Logic Input Control
+
VBUS
R
LIM
V
S
3V TO 5.5V
OR 0V
V
ON
EN
V
L
CC2
EN2
LTM9100
V
CC
GND
V
EE
9100 F12b
–
VBUS
12(b) Bootstrapped Power Connection
5V
V
V
ON
EN
EN2
LTM9100
CC
L
10nF
100k
2N7002
V
CC2
GND
V
EE
9100 F12c
12(c) Contact Debounce Delay Upon Insertion for Use with an Ejector
Switch or Loop-Through Style Connection Sense
–48V
RTN
453k
5V
V
V
EN2
CC
L
CONNECTION FOR DEFAULT OFF
NO CONNECT FOR DEFAULT ON
5V
INPUT
UVL
UVH
V
V
CC
L
ON
ON
EN
LTM9100
EN
SCL
SDA
28.7k
LTM9100
2
I C
GND
V
EE
5V
RTN
GND
V
EE
9100 F12e
–48V
INPUT
9100 F12d
12(e) I2C Only Control
12(d) Short Pin Connection Sense to RTN
Figure 12. On/Off Control of the LTM9100
9100f
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LTM9100
applicaTions inForMaTion
After the FET is turned off, the overcurrent condition
register bit A2 is cleared. If the overcurrent auto-retry
register bit D2 has been set, the switch will turn on again
between GATE and V , as shown in Figure 4. The sug-
EE
gested value for C is 47nF. This value should work for
G
most FETs (Q1).
automatically after a cooling time of 4t . Otherwise, the
D
Overvoltage Fault
FET will remain off until the overcurrent fault register bit
B2 is reset. When the overcurrent fault bit is reset (see
Resetting Faults), the FET is allowed to turn on again after
An overvoltage fault occurs when the OV pin rises above
its 1.77V threshold. This shuts off the FET immediately,
sets the overvoltage present register bit A0 and the over-
voltage fault register bit B0, and pulls the SS pin down.
Note that the power good signals are not affected by the
overvoltage fault. If the OV pin subsequently falls back
below the threshold, the FET will be allowed to turn on
again immediately (without delay) unless the overvoltage
auto-retry has been disabled by clearing register bit D0.
a delay of 4t . The 4t cooling time associated with the
D
D
overcurrent fault will not be interrupted by any other fault
condition. See Figure 13 for operation of LTM9100 under
overcurrent condition followed by auto-retry.
In the case of a low impedance short-circuit on the load
side or an input step during battery replacement, current
overshoot is inevitable. A fast SENSE comparator with a
thresholdof250mVdetectstheovershootandimmediately
pulls GATE low. Once the SENSE voltage drops to 50mV,
the current limit loop takes over and servos the current
aspreviouslydescribed. Iftheshort-circuitconditionlasts
longer than 530μs, the FET is shut down and the overcur-
rent fault is registered.
Undervoltage Comparator and Undervoltage Fault
The LTM9100 provides two undervoltage pins, UVH and
UVL, for adjustable UV threshold and hysteresis. The UVH
and UVL pin have the following accurate thresholds:
for UVH rising, V
for UVL falling, V
= 2.56V, turn-on
= 2.291V, turn-off
UVH(TH)
UVL(TH)
In the case of an input step, after an internal clamp pulls
the RAMP pin down to 1.1V, the inrush control circuit
takes over and the current limit loop is disengaged before
the circuit breaker timer expires. From this point on, the
The UVH and UVL pins have a hysteresis of δV (15mV
UV
typical). In either a rising or a falling input supply, the
undervoltage comparator works in such a way that both
the UVH and the UVL pins have to cross their thresholds
for the comparator output to change state.
device works as in the initial start-up: V
is ramped
DRAIN
down at the rate set by I
and C followed by GATE
RAMP
R
pull-up. The power good signals on the PG and PGIO pins,
the TMR pin, and the SS pin are not interrupted through
theinputstepsequence.ThewaveforminFigure14shows
how the LTM9100 responds to an input step.
TheUVH,UVL,andOVthresholdratioisdesignedtomatch
the standard telecom operating range of 43V to 71V and
UVhysteresisof4.5VwhenUVHandUVLaretiedtogether
as in Figure 4, where the built-in UV hysteresis referred
to the UVL pin is:
Note that the current limit threshold should be set suf-
ficiently high to accommodate the sum of the load current
and the inrush current to avoid engagement of the current
limitloopintheeventofaninputstep. Themaximumvalue
of the inrush current is given by:
∆V
= V
– V
= 0.269V
UVL(TH)
UV(HYST)
UVH(TH)
Using R1 = 11.8k, R2 = 16.9k and R3 = 453k as in Figure 4
gives a typical operating range of 43.0V to 70.7V, with
an undervoltage shutdown threshold of 38.5V and an
overvoltage shutdown threshold of 72.3V.
45mV
RS
IINRUSH ≤0.8•
–ILOAD
where the 0.8 factor is used as a worst-case margin
combined with the minimum SENSE threshold (45mV).
The UV hysteresis can be adjusted by separating the UVH
and UVL pins with a resistor R (Figure 15). To increase
H
the UV hysteresis, the UVL tap should be placed above
the UVH tap as in Figure 15a. To reduce the UV hysteresis,
The active current limit circuit is compensated using the
capacitor C with a series resistor R (10Ω) connected
G
G
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PG2
PG
PGIO
DRAIN
1.77V
TMR
4x
2x
2x
SS
GATEH
GATE
V
TH
50mV
di/dt
SENSE
530µs
INRUSH
9100 F13
Figure 13. Overcurrent Fault and Auto-Retry
72V
VBUS
PG2
PG
36V
0V
0V
0V
PGIO
DRAIN
TMR
0V
SS
GATEH
GATE
V
TH
50mV
LOAD + INRUSH
SENSE
LOAD
LOAD
9100 F14
Figure 14. 36V to 72V Step Response
9100f
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place the UVL tap under the UVH tap as in Figure 15b. UV
hysteresis referred to the UVL pin is given by:
When power is applied to the device, if UVL is below the
2.291V threshold and UVH is below 2.56V – δV after
UV
V
crosses its undervoltage lock out threshold (4.25V),
CC2
for V
≥ V
UVH
an undervoltage fault will be logged in the fault register.
UVL
R
H
Because of the compromises of selecting from a table of
discrete resistor values (1% resistors in 2% increments,
0.1% resistors in 1% increments), best possible OV and
UV accuracy is achieved using separate dividers for each
pin.Thisincreasesthetotalnumberofresistorsfromthree
or four to as many as six, but maximizes accuracy, greatly
simplifies calculations and facilitates running changes to
accommodatemultiplestandardsorcustomizationwithout
any board changes.
V
= V
+ 2.56V •
– 2.56V •
UVL(HYST)
UV(HYST)
R1+R2
or for V
< V
UVH
UVL
R
H
V
= V
UV(HYST)
UVL(HYST)
R1+R2+R
H
For V
< V , the minimum UV hysteresis allowed is
UVH
the minimum hysteresis at UVH and UVL: δV = 15mV
UVL
UV
when R
ꢀ=ꢀ0.11ꢀ•ꢀ(R1 + R2).
H(MAX)
FET Short Fault
+
+
VBUS
VBUS
A FET short fault will be reported if the data converter
measures a current sense voltage greater than or equal
to 2mV while the FET is turned off. This condition sets the
FET_STATregisterbitA5andtheFET_FAULTregisterbitB5.
R3
R3
453k
1%
453k
1%
UVL
UVH
OV
UVH
UVL
OV
TURN-ON = 46V
TURN-OFF = 38.5V
HYSTERESIS = 7.5V
TURN-ON = 43V
TURN-OFF = 41.2V
HYSTERESIS = 1.8V
R
R
H
H
1.91k
1.91k
1%
1%
R2
15k
1%
R2
15k
1%
External Fault Monitor
R1
11.8k
1%
R1
11.8k
1%
ThePGIOpin,whenconfiguredasageneralpurposeinput,
allows the monitoring of external fault conditions such as
broken fuses. In this case, if the voltage at PGIO is above
1.25V, both register bit A6 and register bit B6 are set,
though there is no alert bit associated with this fault. An
external fault condition on PGIO does not directly affect
the GATE control functions.
–
–
VBUS
VBUS
9100 F15
(15a)
(15b)
Figure 15. Adjustment of Undervoltage Thresholds for Larger
(15a) or Smaller (15b) Hysteresis
Fault Alerts
The design of the LTM9100 protects the UV comparator
from chattering even when R is larger than R
.
When any of the fault bits in the FAULT (B) register are
set, an optional bus alert can be generated by setting the
appropriate bit in the ALERT (C) register. This allows only
selected faults to generate alerts. At power-up the default
state is not to alert on faults. If an alert is enabled, the
correspondingfaultwillcausetheALERT2andALERTpins
to pull low. After the bus master controller broadcasts the
alert response address, the LTM9100 will respond with its
address on the SDA line and release ALERT as shown in
Figure 30. If there is a collision between two LTM9100’s
responding with their addresses simultaneously, then
H
H(MAX)
An undervoltagefault occurs when theUVL pinfalls below
2.291V and the UVH pin falls below 2.56V – δV . This
UV
activatestheFETturn-offandsetstheundervoltagepresent
register bit A1 and the undervoltage fault register bit B1.
The power good signals at PG and PGIO are also reset.
The undervoltage present register bit A1 is cleared when
theUVHpinrisesabove2.56VandtheUVLpinrisesabove
2.291V + δV . After a delay of t , the FET will turn on
UV
D
againunlesstheundervoltageauto-retryhasbeendisabled
by clearing register bit D1.
9100f
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the device with the lower address wins arbitration and
responds first. The ALERT line will also be released if the
device is addressed by the bus master.
–
and SENSE pins is monitored with a 64mV full-scale and
62.5μVresolution, andthedataisstoredinregistersEand
F. The ADIN and ADIN2 pins are monitored with a 2.56V
full-scale and 2.5mV resolution. The data for the ADIN2
pin is stored in registers G and H. The data for the ADIN
pin is stored in registers I and J.
Once the ALERT signal has been released for one fault,
it will not be pulled low again until the FAULT register
indicates a different fault has occurred, or the original
fault is cleared and it occurs again. Note that this means
repeated or continuing faults will not generate alerts until
the associated FAULT register bit has been cleared.
The results in registers E, F, G, H, I and J are updated at
a frequency of 7.3Hz. Setting register bit D5 invokes a
test mode that halts updating these registers so that they
can be written to and read from for software testing. By
invoking the test mode right before reading the ADC data
registers, the 10-bit data separated in two registers are
synchronized.
Resetting Faults
Faults are reset with any of the following conditions. First,
writingzerostotheFAULTregisterwillcleartheassociated
faultbits.Second,theentireFAULTregisterisclearedwhen
either the EN2 pin or register bit D3 goes from high to low,
The ADIN and ADIN2 pins can be used to monitor input
and output voltages or temperature of the controller as
shown in Figures 33 to 35, 39, 40, 43, and 45.
or if V falls below its 4.25V undervoltage lockout. Pull-
CC2
ing the UVL pin below its 1.21V reset threshold also clears
the entire FAULT register. When the UVL pin is brought
back above 1.21V but below 2.291V, the undervoltage
fault register bit B1 is set if the UVH pin is below 2.56V.
This can be avoided by holding the UVH pin above 2.56V
while toggling the UVL pin to reset faults.
Configuring the PGIO Pin
Table 4 describes the possible states of the PGIO pin us-
ing register bits D6 and D7. At power-up the default state
is for the PGIO pin to pull low when the second power
good signal is ready. Other uses for the PGIO pin are to go
high impedance when the second power good is ready, a
generalpurposeoutputandageneralpurposeinput.When
the PGIO pin is configured as a general purpose output,
the status of register bit C6 is sent out to the pin. When
it is configured as a general purpose input, if the input
voltage at PGIO is higher than 1.25V, both register bits A6
and B6 are set. If the input voltage at PGIO subsequently
drops below 1.25V, register bit A6 is cleared. Register
bit B6 can be cleared by resetting the FAULT register as
described previously.
Fault bits with associated conditions that are still present
(asindicatedintheSTATUS(A)Register)cannotbecleared.
The FAULT register will not be cleared when auto-retrying.
When auto-retry is disabled, the existence of register bits
B0 (overvoltage), B1 (undervoltage) or B2 (overcurrent)
keeps the FET off. After the fault bit is cleared and a delay
of t expires, the FET will turn on again. Note that if the
D
overvoltagefaultregisterbitB0isclearedbywritingazero
2
through I C, the FET is allowed to turn on without a delay.
If auto-retry is enabled, then a high value in register bits
A0, A1 or A2 will hold the FET off and the FAULT register
is ignored. Subsequently, when register bits A0, A1 and
A2 are cleared, the FET is allowed to turn on again.
Design Procedure
1. Using the load current (I
) requirement of the ap-
LOAD
plication, calculate the sense resistor (R ) value using
S
Data Converter
the minimum SENSE threshold voltage of 45mV.
The LTM9100 incorporates a 10-bit ∆∑ analog-to-digital
converter(ADC)thatcontinuouslymonitorsthreedifferent
voltages at (in the sequence of) SENSE, ADIN2 and ADIN.
The∆∑architectureinherentlyaveragessignalnoiseduring
45mV
R =
S
I
LOAD
55mV
I
=
+
MAX
themeasurementperiod.ThevoltagebetweentheSENSE
R
S
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2. For a capacitive load (C ) set the inrush (I
) cur-
L
INRUSH
VBUS•I
INRUSH
P
t
=
TON
rent by calculating the ramp capacitor (C ) value.
R
2
I
20µA
I
INRUSH
C •VBUS C •VBUS
RAMP
R
L
C = C •
= C •
L
=
=
R
L
INRUSH
I
I
I
INRUSH
INRUSH
RAMP(min)
=
P t P
t
The inrush current and ramp capacitor may need to be
iterated based upon the selected switch safe operating
area (SOA).
TON
INRUSH
b.Loadshort-circuitturn-onpowerdissipation(P
)
SCTON
,thisistheMOSFET
consistsofacurrentramptoI
MAX
For resistive or inductive loads the turn-on voltage rate
of change is calculated by:
transconductanceperiod(t ),followedbythecircuit
fs
MAX
breaker period (t ) at I
voltage. Ignoring slow start:
, each at constant bus
CB
dV I
dt
20µA
C
R
RAMP
=
=
C
R
VBUS•I
MAX
P =
fs
3. SelectanN-channelswitch(Q1);MOSFET,SiCMOSFET,
IGBT, etc. Switch selection is based upon maximum
2
P =
VBUS•I
CB
MAX
operating voltage (with margin), ON state power dis-
2
C +C
•2•I
MAX
(
)
sipation (I
ꢀ•ꢀR
or I ꢀ•ꢀV ), and SOA. The
G
I
iss(max)
t
MAX
DSON
MAX CESAT
fs
=
maximumONstatepowerdissipation(P )iscalculated
g
ON
GATE(min) fs(min)
•
usingthemaximumloadcurrentandmaximumexpected
switchR
.Themaximumswitchresistanceat125°C
where I
= 7.5µA, C is the MOSFET gate
iss
DSON
GATE(min)
is generally 2× the data sheet electrical table maximum
input capacitance, and g is the MOSFET forward
fs
ON resistance at 25°C junction temperature.
transconductance.
2
P
= I
ꢀ•ꢀR
ON
MAX
DSON(125°C)
t
CB
= 620µs (Maximum)
Multiple cases must be considered for the switch SOA
including; normal inrush turn-on, turn-on into a short
circuit, input voltage steps, and short-circuit while con-
ducting. To evaluate the switch SOA between multiple
manufacturers and operating cases the calculated data,
and constant power (diagonally decreasing) portion of
the data sheet SOA curves, can be normalized by cal-
Calculate the total power dissipation over the event:
P •t +P •t
fs fs CB CB
P
=
SCTON
t +t
fs CB
=
P t P
t +t
SCTON fs CB
c. Power dissipation for an input voltage step (P
)
2
STEP
to ≈ 0V with
culating P t or P√t and comparing. Switches designed
consists of a voltage ramp from V
STEP
and characterized for linear or DC operation are most
suitable. These are generally switches fabricated using
a planar process, as opposed to a high density vertical
process (e.g. trench).
constant current of I
= I
+ I
. Assum-
MAX
INRUSH
LOAD
ing load current is constant with operating voltage:
V
•I
2
STEP MAX
P
=
STEP
a. Normal switch turn-on power dissipation (P
)
TON
consists of a voltage ramp from VBUS to ≈ 0V with
constant charging current of I . Assuming no
C •V
C •V
L
R
STEP
STEP
I
INRUSH
t
STEP
=
=
INRUSH
I
RAMP(min)
load current and ignoring slow start:
=
P t P
t
STEP STEP
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d. Load short-circuit while conducting power dissipa-
e. Thecurrentinthedivideratthresholdofundervoltage
event is:
tion (P
) consists of a constant bus voltage at
SCON
maximum current for the circuit breaker period.
VBUS
VBUS
UV
I
= I
•
DIV(UV) DIV(NOM)
P
SCON
= VBUSꢀ•ꢀI
NOM
MAX
f. Calculate R2:
t
CB
= 620µs
P t =P
t
V
UV(TH)
SCON
CB
R2=
–R1
I
DIV(UV)
On inspection case d will always result in a lower
value than case b and will not need to be calculated.
g. Calculate R3:
4. Select the GATE compensation capacitance (C ). The
G
VBUS
NOM
R3=
–R1–R2
total capacitance on the GATE pin should be ≈ 47nF to
compensate the active current limit circuit. The total
capacitance is equal to:
I
DIV(NOM)
6. Size resistor to the DRAIN pin, the suggested bias cur-
rent is 50μA, limit the value to < 2mA.
C
= C + C ≈ 47nF
G iss
G(TOTAL)
5. Size divider resistors for undervoltage and overvoltage
trip points, assuming UVL and UVH pins tied together,
and one divider for both functions (Figure 4). These
functions may be disabled by tying UVL and UVH to
VBUS
NOM
R =
D
50µA
Design Example #1
V
, and OV to V .
CC2
EE
For this design example, consider the 200W application
a. Choose a nominal current to run in the divider
(I ). Typically this is 100μA.
with C = 330μF as shown in Figure 4. The operating volt-
L
DIV(NOM)
age range is from 43V to 71V with a UV turn-off threshold
of 38.5V. For the purposes of calculation the minimum
operating voltage is 36V and maximum is 72V. The design
musttolerateshortcircuitsandaninputvoltagestepof36V.
b. The current in the divider during an overvoltage
condition is:
VBUS
OV
I
= I
•
DIV(OV) DIV(NOM)
1. The sense resistor is calculated using the minimum
sense threshold, minimum operating voltage, and ap-
plication power:
VBUS
NOM
where VBUS
is the nominal bus voltage and
NOM
VBUS is the bus voltage in the overvoltage condi-
OV
tion.
45mV •36V
R =
= 0.008Ω
S
c. Calculate R1:
200W
V
I
1.77V
55mV
OV(TH)
R =
=
I
=
=6.875A
1
MAX
I
0.008
DIV(OV) DIV(OV)
2. Set the inrush current to 0.66A.
d. Choose the undervoltage bus voltage (VBUS ).
UV
Undervoltage may be set using the rising threshold
(UVH) of 2.56V, the bus voltage where the system
startstooperate,orfallingthreshold(UVL)of2.291V,
the bus voltage where the system ceases to operate,
depending on the system requirements.
20µA
C = C •
= 10nF
R
L
0.66A
R is chosen to be 1k as discussed previously.
R
9100f
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3. Select a MOSFET and compare the calculated power
dissipationunderallconditions.TheIRF1310isselected,
worst case conduction loss is:
5. SetthenominalUV/OVdividerstringto100µA,resistors
are rounded to the nearest 1% value.
72
IDIV(OV) =100µA • =150µA
48
2
2
P
ON
= I
ꢀ•ꢀR
= 6.875 ꢀ•ꢀ72mΩ = 3.4W
MAX
DSON(125°C)
From the data sheet SOA curve the P√t for 10ms opera-
43
IDIV(UV) =100µA • =89.6µA
48
tion is ≈ 25W√s (V = 50V, I = 5A).
DS
D
Case 3a:
1.77
150µA
72•0.66 330µ•72
R1=
R2=
=11.8kΩ
P t =
=4.5W s
2
0.66
2.56
89.6µA
Case 3b:
11.8kΩ=16.9kΩ
–
72•6.875
P =
=248W,P =72•6.875=495W
CB
fs
2
48
100µA
R3=
–11.8kΩ –16.9kΩ=453kΩ
(47n+1.9n)•2•6.875
7.5µA •14
t =
=
6.4ms
fs
6. The DRAIN pin resistor is set to 1MΩ.
248•6.4m+495•620µ
P
=
=270W
s
SCTON
Design Example #2
6.4m+620µ
For this design example, consider the 380V application
with C = 330μF as shown on the back page. The operat-
ing voltage range is from 260V to 420V with a UV turn-off
threshold of 235V, and OV threshold of 435V. The design
must tolerate short circuits, and be designed to maximize
the available load current with an off-the-shelf MOSFET.
P t =270 6.4m+620µ
Case 3c:
.
=22 6W
L
36•6.875
330µ•36
.
=16 6W
s
P
t =
2
0.66
With a 435V maximum operating voltage a MOSFET
with 600V drain to source voltage is desired. In order to
All cases are satisfied with P√t values < 25W√s.
4. The FET selected in step 3 has an input capacitance of
maximize load current, minimum R
and excellent
DSON
1.9nF, so the C value of 47nF is appropriate.
G
SOA are needed. A device survey shows than an IXYS,
IXTH30N60L2, is a good candidate. A reasonable, heat-
sinkable, board level conduction loss (P ) is 5W. The
ON
maximum operating current can now be calculated:
P
5
0.48
ON
DSON(125°C)
I
=
=
=3.25A
MAX
R
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1. Calculate the sense resistor:
the input resistors to minimize current and power dis-
sipation;3.3MΩischosen,thedividerresistorsarethen
3.3MΩ/102.3 = 32.4kΩ. As noted on the schematic
the ADIN voltage should be 2.56V at 435V, and the OV
voltage should be 1.77V at 435V. Set the maximum
divider string current to 200µA.
55mV
3.25A
R =
=0.017Ω
S
2. Settheinrushcurrent,bychoosinganoperatingcurrent
below the DC SOA operating curve at 400V.
1.77
200µA
2.56
200µA
VBUS
R1=
R2=
=8.87kΩ
20µA
0.3A
I
=0.3A,C =330µ•
=22nF
INRUSH
R
–8.87kΩ=3.92kΩ
3. The P√t of the device is ≈ 80W√s at a case temperature
of 75°C.
OV
Case 3a:
102.3
R3=
–8.87kΩ –3.92kΩ=8.45kΩ
200µA
430•0.3
330µ•430
=44W
s
P
t =
6. The DRAIN pin resistor is set to 3.3MΩ.
2
0.3
External Switch
Case 3b:
430•3.25
While the primary application of the LTM9100 is the con-
trol of an external N-Channel MOSFET switch, insulated
gate bipolar transistors (IGBTs) may be used. This is of
particular interest in voltage applications greater than
250V where traditional FETs with sufficient SOA and low
Pfs =
=700W,P =430•3.25=1.4kW
CB
2
(39n+10.7n)•2•3.25
7.5µA •10
t =
=4.3ms
fs
R
DSON
are not available.
700•4.3m+1400•620µ
IGBTs are readily available with voltage ratings of 600V,
1200V, and higher. Not all IGBTs are suitable, only those
specified for DC or near DC operation as indicated in the
data sheet SOA operating curves. Two additional areas of
concern are the collector to emitter saturation voltage and
gate to emitter threshold voltage.
P
=
=788W
SCTON
4.3m+620µ
P t =788 4.3m+620µ =55W s
Case 3c is not calculated since an input step was not
specified.
The LTM9100 monitors the collector voltage of the IGBT,
via the DRAIN pin and series resistor, to insure the IGBT is
turned on before the power good signals are transitioned.
The DRAIN pin threshold is 1.77V. The saturation voltage,
4. The FET selected has an input capacitance of 10.7nF,
so the C value of 39nF is appropriate.
G
5. In this example the bus voltage must be level shifted
V
, of the IGBT may be higher than this necessitat-
CE(SAT)
and referenced to V to utilize the UV, OV, and analog
EE
ing a voltage divider on the DRAIN monitor input pin as
shown in Figure 16.
inputs. This is accomplished by the differential ampli-
fier stage using the LTC®2054. Since the output of the
amplifier connects to the UV pins, the amplifier divide
ratio is set for an output voltage of 2.291V at the UV
turn-off threshold of 235V; 235/2.291=102.3. Choose
Resistor R1 is sized based on the bus voltage and maxi-
mum DRAIN current of 2mA. Resistor R2 is then chosen
to provide a voltage less than 1.77V on the DRAIN pin with
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400V
also impacts Q1’s gate charging current. This additional
current must be accounted for in the load current inrush
R1
DRAIN
R2
calculation and sizing of C .
R
LTM9100
1200V
IGBT
GATE
+
SENSE
C
R
R
S
1k
RAMP
–
SENSE
V
EE
LTM9100
Q2
2N7002
C
LOAD
Q1
GATE
400V RTN
R1
9100 F16
V
S
V
BOOST
Figure 16. LTM9100 DRAIN Monitor Resistive Divider for
IGBT Collector Sense
9100 F17
Figure 17. Simple Gate Voltage Booster
margin for the worst-case load current and V voltage of
CE
the IGBT at the minimum GATE voltage.
VBOOST – VQ1(threshold)
IRAMP ≈ 20µA + 2 •
The IGBT gate to emitter threshold voltage must also be
considered. The IGBT should be selected with a maximum
R1
IRAMP
IINRUSH
gate to emitter threshold voltage, V
, corresponding
GE(th)
CR = CL •
to the minimum LTM9100 GATE power good condition or
V minimum UVLO voltage of 8.5V. The threshold voltage
S
presented in the device data sheet electrical table is often
at very low collector currents. Plots are typically provided
for collector current vs gate-emitter voltage, and gate-
emitter voltage vs gate charge. The IGBT characteristics
must be carefully evaluated to ensure compatibility with
the LTM9100.
Negative Gate Bias
While the GATE signal is strongly pulled to V in the
EE
off state, additional voltage margin may still be desired
to further reduce the risk of capacitance coupled switch
turn on. In this situation, a negative gate off bias may also
be incorporated as shown in Figure 18. Q4 enables the
negative bias when EN transitions low, Q3 blocks current
Boosting Gate Voltage
from the V based GATE pin, and Q2 connects an external
EE
Higher gate voltage may be desired for two primary rea-
sons.First,toreducethesensitivityofdV/dtcouplingfrom
the drain or collector to gate via the Miller capacitance,
providing additional noise margin. Secondly to optimize
negative voltage (–V
) to the switch.
BIAS
Q3
BSS84
Q1
GATE
the R
or V which in turn reduces power dissipation.
DSON
CE
Q2
LTM9100
Figure 17 shows a simple method to increase the gate
voltage. Q2 remains on until the LTM9100 GATE pin volt-
2N7002
Q4
BSS84
100k
V
CC2
age, relative to V , reaches the V threshold of Q2. When
S
GS
–V
Q2 turns off, the gate of Q1 continues to charge through
R1 to an external supply voltage (V ). The value of
BIAS
EN2
9100 F18
BOOST
R1 should be selected to insure that the Q1 gate is near
full voltage before PG2 transitions, one timer delay after
the LTM9100 GATE pin reaches ~9V. The value of R1
Figure 18. Negative Gate Bias Controlled by EN
9100f
33
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The application circuit of Figure 36, shows a method to
Typically a series inductor is added to reduce the AC ripple
and smooth the capacitor charging current. The input
LC filter must be carefully designed based on the source
impedance, load requirements, etc., and it’s design is
beyond the scope of this discussion.
generate both the boosted voltage supply and negative
bias supply from V .
S
Paralleling Switches
It is not recommended to connect switches in parallel to
increase the SOA during turn-on. The LTM9100 does not
include any provisions to insure current sharing between
multipleswitches.Differencesinswitchturn-oncharacter-
istics will inevitably result in one switch conducting most
of the turn-on current until fully enhanced.
Ifaninductiveinputfilterisnotdesired,andtheloadrequire-
ments are such that the peak capacitor charging currents
after initial turn-on are tolerable, then the LTM9100 may
be configured to charge the load capacitance, see Figure
19. The RAMP pin is not used due to coupling of the AC
voltage onto the GATE, instead transistor Q2 is added with
the ramp capacitor placed in series to control GATE as
the load capacitor is charged. Diode D5 resets the ramp
capacitor at turn-off and transistor Q3 isolates GATE after
the turn-on sequence completes to prevent further GATE
modulation during normal operation.
This also holds for FET modules which are composed of
multipledietoachievehighercurrentratings.Themodules
do not employ any dynamic current sharing methods.
Switch threshold matching is insufficient to guarantee
current sharing.
The sense resistor is sized for the peak capacitor charg-
ing current during normal operation to avoid engaging
the internal current limit and circuit breaker functions,
otherwise excessive power dissipation and FET destruc-
tion may result. This is particularly true during the inrush
charging period where the FET has up to the full input bus
voltage across it.
DC Bus with AC Ripple (Rectified AC)
TheLTM9100isprimarilyintendedtocontrolthecharging
of a capacitor by linearly ramping the drain voltage of an
external FET which produces a constant charging current.
If the DC bus voltage includes an AC component, then the
capacitor is only charged when the rectified input voltage
exceeds the capacitor voltage, producing high peak cur-
rents in short intervals.
The internal circuit breaker time of 530μs results in exces-
sive power dissipation during turn-on with a short-circuit
R
Q1
S
+
LOAD
D5
1N4148
Q3
2N7002
D1
D3
1Ω
Q2
2N3904
10Ω
SENSEP
SENSEN
GND
C
G
1M
DRAIN GATE
LTC4213
+
–
SENSE SENSE
READY
V
UVH
EE
OV
UVL
V
CC
ON
V
C
R
C
L
AC
LTM9100
10k
V
EN2
CC2
PG2
ISOLATION BARRIER
V
V
L
ON EN
GND
CC
D2
D4
1µF
5V
GATE
ENABLE
–
LOAD
PINS NOT USED IN THIS CIRCUIT:
ADIN, ADIN2, ADR0, ADR1, ALERT,
ALERT2, PG, PGIO, SCLIN, SCLOUT,
PINS NOT USED IN
LTC4213 CIRCUIT:
9100 F19
GATE, I
SEL
SDA, SDA2, SS, TMR, V
S
Figure 19. Rectified AC High Side Charging Circuit
9100f
34
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Table 1. Component Values for 13.4% Ripple Single Phase and 3.4% Ripple Three Phase
V
Q1
VOLTAGE
150V
C
I
C
C
R
S
AC
G
LOAD
L
R
PART #
FQA90N15
FQA55N25
FDL100N50F
R
DSON(25°C)
1φ
3φ
48
0.018
39nF
47nF
33nF
8
6
5
5600µF
1500µF
680µF
56nF
39nF
6.8nF
0.0008
0.001
0.001
0.0016
0.002
0.002
120
240
250V
0.04
500V
0.055
condition. If short-circuit protection during turn-on is
required then an external electronic circuit breaker is
required, LTC4213 of Figure 19.
predicting the maximum junction temperature, provided
an accurate FET transient thermal impedance model is
available. Table 1 shows the component values for both
single and three phase voltage inputs at three different
input voltage levels. The load charging voltage, current,
and junction temperature of Q1 are shown in Figure 20
The load charging current (I
) is chosen based on
INRUSH
the FET SOA. The ramp capacitor (C ), and ramp time
R
(t
) are calculated as before using the GATE current
INRUSH
for the 120V case of Table 1.
AC
instead of the RAMP current:
The sense resistors specified for the examples in Table
1 are based on a source impedance of 0Ω and therefore
represent the minimum value, in practice the peak capaci-
tor charging currents will be lower and the sense resistor
shouldbesizedappropriately.Inaddition,theloadcapacitor
must be selected to handle the high RMS charging cur-
rent, and will typically be composed of multiple parallel
capacitors for this reason.
I
11.5µA
I
INRUSH
GATE
C = C •
= C •
L
R
L
I
INRUSH
V
V
I
PEAK
PEAK
= C •
= C •
L
t
R
INRUSH
I
INRUSH
GATE
The charging time may need to be extended to reduce
transient thermal excursions during turn-on. Circuit
simulation software, such as LTspice®, can be useful in
AMBIENT TEMPERATURE = 85°C
30V/DIV
1.5A/DIV
10°C/DIV
9100 F20a
9100 F20b
9100 F20c
60ms/DIV
60ms/DIV
60ms/DIV
Figure 20(a). Load Capacitor Voltage
Figure 20(b). Load Capacitor Current
Figure 20(c). Q1 Junction Temperature
Figure 20. Load Capacitor Charging Voltage, Current, and Junction Temperature
9100f
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SLAVE ACK
SDA
SDA2
SCL
1
8
9
SCL2
START
STOP
9100 F21
t
PROP
t
t
HD(DAT)
t
SU(DAT)
SU(ACK)
Figure 21. I2C Timing Diagram
2
Inter-IC Communication Bus (I C)
1.8mA
GLITCH FILTER
2
TO
LOGIC
SIDE
TheLTM9100providesanI Ccompatibleisolatedinterface;
clock (SCL→SCL2) is unidirectional, supporting master
mode only, and data (SDA↔SDA2) is bidirectional. The
SDA2
FROM
LOGIC
SIDE
2
I CinterfaceprovidesaccesstotheADCdataregistersand
9100 F22
four other registers for the monitoring and control of the
2
FET. In addition, the isolated side I C pins are accessible,
Figure 22. Isolated SDA2 Pin Schematic
allowing additional serial device expansion.
30
V = 3V
2
The maximum I C data rate is 400kHz, fast-mode capable,
limited by the slave acknowledge setup time (t
V = 3.3V
25
20
15
10
5
V = 3.6V
),
V = 4.5V TO 5.5V
SU(ACK)
consisting of the system propagation delay, glitch filter,
andfixedisolateddatadelayofapproximately500ns. Tim-
ing is detailed in Figure 21. The total setup time reduces
2
the I C data hold time (t
) to a maximum of 175ns,
HD(DAT)
guaranteeing sufficient data setup time (t
).
SU(DAT)
The isolated side bidirectional serial data pin, SDA2,
simplified schematic is shown in Figure 22. An internal
1.8mA current source provides a pull-up for SDA2. Do not
connect any other pull-up device to SDA2. This current
source is sufficient to satisfy the system requirements for
bus capacitances greater than 200pF in FAST mode and
greater than 400pF in STANDARD mode.
0
10
100
(pF)
1000
C
BUS
9100 F23
Figure 23. Maximum Standard Speed Pull-Up Resistance on SDA
10
V = 3V
9
8
7
6
5
4
3
2
1
0
V = 3.3V
V = 3.6V
V = 4.5V TO 5.5V
Additional proprietary circuitry monitors the slew rate on
the SDA and SDA2 signals to manage directional control
across the isolation barrier. Slew rates on both pins must
be greater than 1V/µs for proper operation.
The logic side bidirectional serial data pin, SDA, requires a
pull-up resistor or current source connected to V . Follow
L
10
100
(pF)
1000
the requirements in Figures 23 and 24 for the appropri-
C
BUS
9100 F24
ate pull-up resistor on SDA that satisfies the desired rise
Figure 24. Maximum Fast Speed Pull-Up Resistance on SDA
time specifications and V maximum limits for FAST and
OL
9100f
36
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STANDARD modes. The resistance curves represent the
maximum resistance boundary; any value may be used
to the left of the appropriate curve.
START and STOP Conditions
When the bus is idle, both SCL and SDA must be high. A
bus master signals the beginning of a transmission with a
START condition by transiting SDA from high to low while
SCLishigh.Whenthemasterhasfinishedcommunicating
with the slave, it issues a STOP condition by transitioning
SDA from low to high while SCL is high. The bus is then
free for another transmission.
The isolated side clock pin, SCL2 has a weak push-
pull output driver; do not connect an external pull-up
2
device. SCL2 is compatible with I C devices without
clock stretching. On lightly loaded connections, a
100pF capacitor from SCL2 to V or RC low pass filter
EE
(R = 500Ω, C = 100pF) can be used to increase the rise
Stuck-Bus Reset
and fall times and minimize noise.
2
TheLTM9100I Cinterfacefeaturesastuck-busresettimer.
The LTM9100 is a read-write slave device and supports
SMBus bus read byte, write byte, read word and write
word commands. The second word in a read word com-
mand will be identical to the first word. The second word
in a write word command is ignored. The data formats for
these commands are shown in Figures 25 to 28.
The low conditions of the SCL2 and SDA2 pins are ORed
to start the timer. The timer is reset when both SCL2 and
SDA2 are pulled high. If the SCL2 pin or the SDA2 pin is
held low for over 66ms, the stuck-bus timer will expire
2
and the internal I C state machine will be reset to allow
S
ADDRESS
W
A
COMMAND
A
DATA
A
P
S
ADDRESS
W
A
COMMAND
A
DATA
A
DATA
A
P
001a3:a0
0
0
XXXXb3:b0
0
b7:b0
0
001a3:a0
0
0
XXXXb3:b0
0
b7:b0
0
0
XXXXXXXX
9100 F25
9100 F26
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 26. LTM9100 Serial Bus SDA Write Word Protocol
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
Figure 25. LTM9100 Serial Bus SDA Write Byte Protocol
S
ADDRESS
W
A
COMMAND
A
S
ADDRESS
R
A
DATA
A
P
001a3:a0
0
0
XXXXb3:b0
0
001a3:a0
1
0
b7:b0
1
9100 F27
Figure 27. LTM9100 Serial Bus SDA Read Byte Protocol
S
ADDRESS
W
A
COMMAND
A
S
ADDRESS
R
A
DATA
A
DATA
A
P
001a3:a0
0
0
XXXXb3:b0
0
001a3:a0
1
0
b7:b0
0
b7:b0
1
9100 F28
Figure 28. LTM9100 Serial Bus SDA Read Word Protocol
9100f
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normal communication after the stuck-low condition is
cleared. When the SCL2 pin and the SDA2 pin are held
low alternately, if the ORed low period of SCL2 and SDA2
exceeds66msbeforethetimerresetcondition(bothSCL2
and SDA2 are high) occurs, the stuck-bus timer will expire
Acknowledge
The acknowledge signal is used for handshaking between
the transmitter and the receiver to indicate that the last
byte of data was received. The transmitter always releases
the SDA line during the acknowledge clock pulse. When
the slave is the receiver, it must pull down the SDA2 line
so that it remains low during this pulse to acknowledge
receipt of the data. If the slave fails to acknowledge by
leavingSDA2high,thenthemastercanabortthetransmis-
sion by generating a STOP condition. When the master is
receiving data from the slave, the master must pull down
the SDA line during the clock pulse to indicate receipt of
the data. After the last byte has been received the master
will leave the SDA line high (not acknowledge) and issue
a STOP condition to terminate the transmission.
2
and the I C state machine is reset.
2
I C Device Addressing
2
Any of eight distinct I C bus addresses are selectable
using the three-state pins ADR0 and ADR1, as shown in
Table 2. Note that the configuration of ADR0 = L and
ADR1 = H is used to enable the single-wire broadcasting
2
mode. For the eight I C bus addresses, address bits b7,
b6 and b5 are configured to (001) and the least signifi-
cant bit b0 is the R/W bit. In addition, the LTM9100 will
respond to two special addresses. Address (0011 111)
is a mass write used to write to all LTM9100s, regardless
of their individual address settings. Address (0001 100)
is the SMBus alert response address. If the LTM9100 is
pulling low on the ALERT pin, it will acknowledge this
address using the SMBus alert response protocol. Note,
if multiple LTM9100’s are configured to share a single
ALERT bus then the addition of an open drain buffer is
necessary, see Figure 29.
Write Protocol
ThemasterbeginscommunicationwithaSTARTcondition
followed by the seven bit slave address and the R/W bit set
to zero. The addressed LTM9100 acknowledges this and
then the master sends a command byte which indicates
which internal register the master wishes to write. The
LTM9100 acknowledges this and then latches the lower
four bits of the command byte into its internal register ad-
dress pointer. The master then delivers the data byte and
the LTM9100 acknowledges once more and latches the
data into its internal register. The transmission is ended
when the master sends a STOP condition. If the master
continues sending a second data byte, as in a write word
command, the second data byte will be acknowledged by
the LTM9100 but ignored.
5V
V
V
ON
CC
L
1.5k
1.5k
1.5k
SCL
SDA
SCL
SDA
EN
OPEN DRAIN BUFFER
ALERT
ALERT
PG
GND
Read Protocol
9100 F29
ThemasterbeginsareadoperationwithaSTARTcondition
followed by the seven bit slave address and the R/W bit
set to zero. The addressed LTM9100 acknowledges this
and then the master sends a command byte that indicates
which internal register the master wishes to read. The
LTM9100 acknowledges this and then latches the lower
four bits of the command byte into its internal register
address pointer. The master then sends a repeated START
Figure 29. Open Drain Buffer for Shared ALERT Bus
9100f
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condition followed by the same seven bit address with the
R/W bit now set to one. The LTM9100 acknowledges and
sendsthecontentsoftherequestedregister.Thetransmis-
sion is ended when the master sends a STOP condition.
If the master acknowledges the transmitted data byte, as
in a read word command, the LTM9100 will repeat the
requested register as the second data byte. Note that the
register address pointer is not cleared at the end of the
transaction. Thus the receive byte protocol can be used
to repeatedly read a specific register.
The ALERT signals will not be pulled low again until the
FAULTregisterindicatesadifferentfaulthasoccurredorthe
original fault is cleared and it occurs again. Note that this
meansrepeatedorcontinuingfaultswillnotgeneratealerts
until the associated FAULT register bit has been cleared.
Single-Wire Broadcast Mode
The LTM9100 provides a single-wire broadcast mode in
which selected register data are sent out to the SDA pin
without clocking the SCL line (Figure 31). The single-wire
broadcast mode is enabled by setting the ADR1 pin high
Alert Response Protocol
2
and the ADR0 pin low (the I C interface is disabled). At
The LTM9100 implements the SMBus alert response pro-
tocol as shown in Figure 30. If enabled to do so through
theALERT(C)register, theLTM9100willrespondtofaults
by pulling the ALERT pins low. Multiple LTM9100s can
share a common ALERT2 line on the isolated side, or a
common ALERT line on the logic side with the addition
of open drain buffers. The protocol allows a master to
determine which LTM9100 is pulling the line low. The
master begins by sending a START bit followed by the
special alert response address (0001 100) with the R/W
bit set to one. Any LTM9100 that is pulling its ALERT pins
lowwillacknowledgeandbeginsendingbackitsindividual
slave address.
the end of each conversion of the three ADC channels,
a stream of eighteen bits are broadcasted to SDA with a
serial data rate of 15.3kHz ±20ꢀ in a format as illustrated
in Figure 32. The data bits are encoded with an internal
clock in a way similar to Manchester encoding that can
be easily decoded by a microcontroller or FPGA. Each
data bit consists of a noninverting phase and an invert-
ing phase. During the conversion of each ADC channel,
SDA will idle high. At the end of the conversion, the SDA
pin pulls low. The START bit indicates the beginning of
data broadcasting and is used along with the dummy bit
(DMY) to measure the internal clock cycle (i.e., the serial
data rate). Following the DMY bit are two channel code
bits CH1 and CH0 labeling the ADC channel (see Table
3). Ten data bits of the ADC channel (ADC9 to ADC0) and
three FAULT register bits (B2, B1 and B0) are then sent
out. A parity bit (PRTY) ends each data stream. After that
the SDA line enters the idle mode with SDA pulled high.
ALERT
RESPONSE
ADDRESS
DEVICE
ADDRESS
R
A
A
P
S
0001100
1
0
001a3:a00
1
9100 F30
The following data reception procedure is recommended:
1. Wait for SDA falling edge.
Figure 30. LTM9100 Serial Bus SDA Alert Response Protocol
An arbitration scheme ensures that the LTM9100 with the
lowest address will have priority; all others will abort their
response. The successful responder will then release its
ALERT pins while any others will continue to hold their
ALERT pins low. Polling may also be used to search for
any LTM9100 that have detected faults. Any LTM9100
pulling its ALERT pins low will also release them if it is
individually addressed during a read or write transaction.
2. The first falling edge could be a glitch, so check again
after a delay of 10μs. If back to high, wait again. If still
low, it is the START bit.
3. Use the following low-to-high and high-to-low transi-
tions to measure 1/2 of the internal clock cycle.
4. Wait for the second low-to-high transition (middle of
DMY bit).
9100f
39
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5. Wait 3/4 of a clock cycle.
if it takes more than double the typical time (1.2ms) for
all 18 bits to be clocked out.
6. Sample bit CH1, wait for transition.
7. Wait 3/4 of a clock cycle.
A typical application circuit with the LTM9100 in the
broadcast mode is illustrated in Figure 35, where input
8. Sample bit CH0, wait for transition.
9. Wait 3/4 of a clock cycle.
voltage, V of the FET and V
are monitored.
DS
SENSE
Register Addresses and Contents
10. Sample ADC9, wait for transition.
11. Continue until all bits are read.
The device addresses and register contents are detailed
in Table 2 and Table 4. The function of each register bit is
described in Table 4.
Theaboveprocedurecanbeportedtoamicrocontrolleror
used to design a state machine in an FPGA. Code should
have timeouts in case an edge is missed. Abort the read
5V
V
CC2
V
V
ON
CC
L
ADR1
ADIN
ADIN2
LTM9100
2.56V FULL-SCALE, CH1 = 0, CH0 = 1 ANALOG INPUT
2.56V FULL-SCALE, CH1 = 1, CH0 = 0 ANALOG INPUT
1.5k
MICROCONTROLLER
EN
SCL
SDA
+
SENSE
SENSE
D
IN
64mV FULL-SCALE, CH1 = CH0 = 0 ANALOG INPUT
–
ADR0
GND
V
EE
9100 F31
PINS NOT USED IN THIS CIRCUIT:
ALERT, ALERT2, DRAIN, EN2, GATE, OV, PG, PG2, PGIO, RAMP,
SCL2, SDA2, SS, TMR, UVL, UVH, V
S
Figure 31. Single-Wire Broadcast Mode
INTERNAL
CLK
.. .. ..
DATA
SDA
START DMY
CH1
CH0 ADC9
ADC0
OC
UV
OV
PRTY
9100 F32
START
Figure 32. Single-Wire Broadcast Data Format
9100f
40
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Table 2. LTM9100 Device Addressing
HEX DEVICE
ADDRESS
LTM9100
ADDRESS PINS
DESCRIPTION
BINARY DEVICE ADDRESS
h
b7
0
0
0
0
0
0
0
0
0
0
b6
0
0
0
0
0
0
0
0
0
0
b5
1
0
1
1
1
1
1
1
1
1
b4
1
1
0
0
0
0
0
0
0
0
b3
1
1
0
0
0
0
1
1
1
1
b2
1
0
0
0
1
1
0
0
1
1
b1
1
0
0
1
0
1
0
1
0
1
b0 (R/W)
ADR1
X
ADR0
X
Mass Write
3E
19
20
22
24
26
28
2A
2C
2E
0
1
X
X
X
X
X
X
X
X
X
Alert Response
X
X
0
1
2
3
4
5
6
7
8
L
L
L
NC
NC
H
H
L
NC
NC
H
L
NC
H
NC
H
H
Single-Wire Broadcast Mode
L
H = Tie to V ; L = Tie to V ; NC = No connect, open; X = Don’t care
CC2
EE
Table 3. ADC Channel Labeling for Single-Wire Broadcast Mode
CH1
0
CH2
0
ADC CHANNEL
SENSE Voltage
ADIN2 Voltage
ADIN Voltage
0
1
1
0
9100f
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Table 4. Register Map
REG*
NAME
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DEFAULT
0x00
STATUS (A)
GATE_STAT PGIO_IN
FET_STAT
SENSE
Reserved Reserved
OC_STAT
UV_STAT
OV_STAT
0000,0000
(Read System Status State of
State of
V
>
Overcurrent Undervoltage Overvoltage
Only)
0x01
Information
GATE Pin
PGIO Pin as 2mV with
Condition
Condition
Condition
Input
GATE Off
1=On
0=Off
1=OC
0=No OC
1=UV
0=No UV
1=OV
0=No OV
1=High
0=Low
1=Short
0=No Short
FAULT (B)
Fault Log and
PGIO Input
Reserved
Reserved
PGIO_HIGH
PGIO as
Input High
Transition
Detected
FET_FAULT Reserved Reserved
FET Short
Detected
OC_FAULT UV_FAULT
OV_FAULT 0000,0000
Overcurrent Undervoltage Overvoltage
Fault
Occurred
Fault
Occurred
Fault
Occurred
1=Fault
0=No Fault
1=Fault
0=No Fault 0=No Fault
1=Fault
1=Fault
0=No Fault
1=High
0=Low
0x02
0x03
ALERT (C)
Controls if
PGIO_OUT
Controls
PGIO Pin
State as
Output
FET_ALERT Reserved Reserved
OC_ALERT UV_ALERT
OV_ALERT 0000,0000
Enables
Alert for
Enable Alert
for FET
Short Fault
Enables
Alert for
Enables
Alert for
ALERT Pin is
Pulled Low
After a Fault is
Logged in the
Fault Register
and PGIO
Overcurrent Undervoltage Overvoltage
Fault
Fault
Fault
1=Enable
0=Disable
1=High
0=Low
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
Output
CONTROL (D) PGIO_CONFIG
ADC_WRITE Reserved GATE_CTRL OC_AUTO
UV_AUTO
Enables
OV_AUTO
Enables
Auto-Retry
After an
0000,y011
Controls for
Auto-Retry
after Faults
and GATE
Configures Behavior of
PGIO Pin
Halts ADC
Operation
and Enables
Writes
to ADC
Registers
Turns Gate Enables
On and Off Auto-Retry Auto-Retry
y=EN2 Pin
State After
Start-Up
Delay
After an
After an
1=ON
0=OFF
00=Power Good Low,
Open Drain
10=Power Good High,
Open Drain
01=General Purpose
Output, PGIO=C6
11=General Purpose Input,
PGIO=Hi-Z
Overcurrent Undervoltage Overvoltage
Switch State
Fault
Fault
Fault
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
1=Enable
0=Disable
0x04
0x05
SENSE (E)
SENSE (F)
SENSE_MSBS
xxxx,xxxx
xx00,0000
10-Bit ADC Current Sense Voltage Data (8 MSBs) with 62.5µV LSB and 64mV Full-Scale
SENSE_LSBS
10-Bit ADC Current Sense
Voltage Data (2 LSBs)
Reserved
Always Returns 0, Not Writable
0x06
0x07
ADIN2 (G)
ADIN2 (H)
ADIN2_MSBS
xxxx,xxxx
xx00,0000
10-Bit ADC ADIN2 Voltage Data (8 MSBs) with 2.5mV LSB and 2.56V Full-Scale
ADIN2_LSBS
Reserved
10-Bit ADC ADIN2 Voltage Always Returns 0, Not Writable
Data (2 LSBs)
0x08
0x09
ADIN (I)
ADIN (J)
ADIN_MSBS
xxxx,xxxx
xx00,0000
10-Bit ADC ADIN Voltage Data (8 MSBs) with 2.5mV LSB and 2.56V Full-Scale
ADIN_LSBS
10-Bit ADC ADIN Voltage
Data (2 LSBs)
Reserved
Always Returns 0, Not Writable
*Register address MSBs b7-b4 are ignored. Register 0x00 read only. Registers 0x04 through 0x09 writable if bit D5 set in Register 0x03.
NOTE: Underlined text denotes the default condition.
9100f
42
For more information www.linear.com/LTM9100
LTM9100
applicaTions inForMaTion
RF, Magnetic Field Immunity
•ꢀ To improve noise immunity, put the resistive divider
to the UV and OV pins close to the module and keep
TheisolatorµModuletechnologyusedwithintheLTM9100
hasbeenindependentlyevaluated,andsuccessfullypassed
the RF and magnetic field immunity testing requirements
per European Standard EN 55024, in accordance with the
following test standards:
traces to V short. Internal 10nF capacitors from the
EE
UVH pin and OV pin to V help reject supply noise.
EE
•ꢀ Under heavily loaded conditions, V and GND current
CC
canexceed300mA.UsesufficientcopperonthePCBto
insure resistive losses do not cause the supply voltage
to drop below the minimum allowed level.
EN 61000-4-3 Radiated, Radio-Frequency,
Electromagnetic Field Immunity
•ꢀ Input supply decoupling is not required, since these
components are integrated within the package. An ad-
ditionalbulkcapacitorwithavalueof6.8µFto22µFand
ESR of 1Ω to 3Ω is recommended. The high ESR of
thiscapacitorreducesboardresonancesandminimizes
voltage spikes caused by hot plugging of the supply
voltage. For EMI sensitive applications, an additional
low ESL ceramic capacitor of 1µF to 4.7µF, placed as
close to the power and ground terminals as possible,
is recommended. Alternatively, a number of smaller
value parallel capacitors may be used to reduce ESL
and achieve the same net capacitance.
EN 61000-4-8 Power Frequency Magnetic Field
Immunity
EN 61000-4-9 Pulsed Magnetic Field Immunity
Tests were performed using an unshielded test card de-
signed per the data sheet PCB layout recommendations.
Specific limits per test are detailed in Table 5.
Table 5. Test Frequency Field Strength
TEST
FREQUENCY
80MHz to 1GHz
1.4MHz to 2GHz
2GHz to 2.7GHz
50Hz and 60Hz
60Hz
FIELD STRENGTH
10V/m
EN 61000-4-3 Annex D
3V/m
1V/m
•ꢀ Do not place copper on the PCB between the inner col-
umnsofpads.Thisareamustremainopentowithstand
the rated isolation voltage.
EN 61000-4-8 Level 4
EN 61000-4-8 Level 5
EN 61000-4-9 Level 5
*non IEC method
30A/m
100A/m*
1000A/m
Pulse
•ꢀ The use of solid ground planes for GND and V is
EE
recommended for non-EMI critical applications to
optimize signal fidelity, thermal performance, and to
minimize RF emissions due to uncoupled PCB trace
conduction. The drawback of using ground planes,
where EMI is of concern, is the creation of a dipole
antenna structure, which can radiate differential volt-
PCB Layout
The high integration of the LTM9100 simplifies PCB lay-
out. However, to optimize its electrical performance and
isolation characteristics, EMI, and thermal performance,
some layout considerations are necessary.
ages formed between GND and V . If ground planes
EE
•ꢀ To achieve accurate current sensing, a Kelvin connec-
tionisrecommended.Theminimumtracewidthfor1oz
copper foil is 0.02" per amp to minimize temperature
rise. Using 0.03" per amp or wider is recommended.
Note that 1oz copper exhibits a sheet resistance of
about 530µV/square. Small resistances add up quickly
in high current applications.
are used it is recommended to minimize their area, and
use contiguous planes as any openings or splits can
increase RF emissions.
9100f
43
For more information www.linear.com/LTM9100
LTM9100
applicaTions inForMaTion
•ꢀ For large ground planes a small capacitance (≤ 330pF)
and eliminates the other component selection issues;
however, the PCB must be four or more layers. Care
mustbeexercisedinapplyingeithertechniquetoensure
the voltage rating of the barrier is not compromised.
from GND to V , either discrete or embedded within
EE
thesubstrate, providesalowimpedancecurrentreturn
path for common mode current conducted through
the module parasitic capacitance, minimizing any high
frequencydifferentialvoltagesandsubstantiallyreduc-
ingradiatedemissions.Discretecapacitancewillnotbe
as effective due to parasitic ESL. In addition, voltage
rating, leakage, and clearance must be considered
for component selection. Embedding the capacitance
withinthePCBsubstrateprovidesanearidealcapacitor
•ꢀ In applications without an embedded PCB substrate
capacitance, a slot may be added between the logic
side and isolated side device pins. The slot extends
the creepage path between terminals on the PCB side,
andmayreduceleakagecausedbyPCBcontamination.
The slot should be placed in the middle of the device
terminals and extend beyond the package perimeter.
9100f
44
For more information www.linear.com/LTM9100
LTM9100
Typical applicaTions
Q1
R
S
+
+
VBUS
LOAD
C
R
10Ω
47nF
R4
1k
1M
+
–
RAMP DRAIN
ADIN
GATE
SENSE SENSE
R3
V
OV
EE
LTC2054
V
CC2
5V
V
V
ON
SCL
SDA
EN
ALERT
PG
UVH
UVL
ADIN2
C
CC
L
L
+
LTM9100
–
SCL
SDA
GATE ENABLE
INTERRUPT
POWER GOOD
R2
GND
R1
–
–
VBUS
LOAD
9100 F33
PINS NOT USED IN THIS CIRCUIT:
ADR0, ADR1, ALERT2, EN2, PG2, PGIO, SCL2, SDA2, SS, TMR, V
S
Figure 33. High Side Inrush Current Control with Switch Voltage Sense (R3, R4 to ADIN)
and Load Voltage Sense (R1, R2 Buffered/Inverted to ADIN2)
9100f
45
For more information www.linear.com/LTM9100
LTM9100
Typical applicaTions
R
Q1
S
+
+
LOAD
VBUS
10Ω
C
R
47nF
1k
1M
DRAIN GATE
+
–
RAMP
SENSE SENSE
LTC2054
V
UVH
V
EE
OV
CC2
R1
UVL
ADIN2
+
C
L
–
R2
V
5V
CC
V
ON
SCL
L
LTM9100
R2
SCL
SDA
EN
ALERT
PG
SDA
GATE ENABLE
INTERRUPT
POWER GOOD
R1
GND
–
–
LOAD
VBUS
9100 F34
PINS NOT USED IN THIS CIRCUIT:
ADIN, ADR0, ADR1, ALERT2, EN2, PG2, PGIO, SCL2, SDA2, SS, TMR, V
S
Figure 34. High Side Inrush Current Control with Line/Load Voltage Sense
+
+
LOAD
VBUS
R1
R2
R3
ADIN2 UVH UVL
OV
5V
V
V
ON
CC
L
ADR0
1.5k
SCL
SDA
EN
ALERT
PG
ADR1
LTM9100
V
CC2
C
L
GATE ENABLE
INTERRUPT
POWER GOOD
R4
ADIN
DRAIN RAMP
–
+
GND
SENSE SENSE GATE
V
EE
10Ω
1M
1k
R5
47nF
C
R
R
S
–
–
VBUS
LOAD
Q1
9100 F35
PINS NOT USED IN THIS CIRCUIT:
ALERT2, EN2, PG2, PGIO, SCL2, SDA2, SS, TMR, V
S
Figure 35. Low Side Inrush Current Control with Line/Load Voltage Sense (R1, R2, R3 to ADIN2)
and Switch Voltage Sense (R4, R5 to ADIN), Configured for 1 Wire Broadcast Mode
9100f
46
For more information www.linear.com/LTM9100
LTM9100
Typical applicaTions
+
VBUS
C
R
1k
1M
RAMP
DRAIN
100k
–V
LTC3261
BSS84
S
V
V
EN2
IN
OUT
1µF
EN
C
+
MODE
RT
GND
1µF
V
CC2
UVL
UVH
–
C
1µF
LTM9100
2N7002
1µF
1N4148
1N4148
2V
S
V
S
1M
2N7002
Q1
GATE
BSS84
10Ω
47nF
5V
V
V
CC
L
+
ON
SENSE
SCL
SDA
SCL
SDA
EN
ALERT
PG
R
S
–
GATE ENABLE
INTERRUPT
POWER GOOD
SENSE
OV
V
GND
EE
C
L
–
9100 F36
VBUS
PINS NOT USED IN THIS CIRCUIT:
ADIN, ADIN2, ADR0, ADR1, ALERT2, PG2, PGIO, SCL2, SDA2, SS, TMR
Figure 36. Boosted Gate Drive with Negative Off Bias
9100f
47
For more information www.linear.com/LTM9100
LTM9100
Typical applicaTions
+
VBUS
5V
V
V
V
CC2
UVH
CC
L
C
R
1.5k
ON
UVL
RAMP
1k
SCL
SDA
EN
LTM9100
1M
GATE
ENABLE
DRAIN
GATE
Q1
+
SENSE
R
S
–
SENSE
OV
GND
V
EE
Q2
LOAD(s)
10Ω
47nF
C
L
PINS NOT USED IN THIS CIRCUIT:
ADIN, ADIN2, ADR0, ADR1, ALERT, ALERT2, EN2,
PG, PG2, PGIO, SCL2, SDA2, SS, TMR, V
S
–
9100 F37
VBUS
Figure 37. Switch Control with Reverse Conduction Blocking
5V
V
V
V
CC2
UVH
CC
L
C
R
1.5k
ON
EN
SCL
SDA
UVL
RAMP
1k
LTM9100
1M
DRAIN
GATE
OUTP
Q1
1Ω
TG1
TG2
10Ω
47nF
LT4320
MOTOR DRIVE – INVERTER
IN1
IN2
+
SENSE
BG2
R
S
1µF
48V
BG1
–
M
OUTN
SENSE
OV
GND
V
EE
9100 F38
PINS NOT USED IN THIS CIRCUIT:
ADIN, ADIN2, ADR0, ADR1, ALERT, ALERT2, EN2,
PG, PG2, PGIO, SCLOUT, SDA2, SS, TMR, V
S
Figure 38. Bi-Directional Battery — Inverter Inrush Current Limiter
9100f
48
For more information www.linear.com/LTM9100
LTM9100
Typical applicaTions
2.15k, 0.1%
5V
V
V
ON
SCL
SDA
EN
V
CC2
UVH
UVL
CC
L
47k
1.5k
1.5k
B25/85 = 3960k
VISHAY
NTCS0805E473FHT
47.5k
0.1%
SCL
SDA
LTM9100
ADIN
OV
1.21k
0.1%
+
SENSE
SENSE
–
GND
V
EE
PINS NOT USED IN THIS CIRCUIT:
ADIN2, ADR0, ADR1, ALERT, ALERT2, DRAIN, EN2, GATE,
PG, PG2, PGIO, RAMP, SCL2, SDA2, SS, TMR, V
S
10mV
°C
V
=
, RANGE = 0°C TO 150°C, RESOLUTION = 0.25°C, ACCURACY = 2.5°C
9100 F39
ADIN
Figure 39. Linear 10-Bit Remote (or Local) Thermistor Temperature Sense
LTC2997
5V
V
V
ON
V
CC2
UVL
UVH
CC
L
–
V
D
CC
1.5k
1.5k
470pF
MMBT3904
SCL
SDA
EN
LTM9100
SCL
SDA
VPTAT
GND
ADIN
+
D
OV
+
SENSE
SENSE
–
GND
V
EE
PINS NOT USED IN THIS CIRCUIT:
ADIN2, ADR0, ADR1, ALERT, ALERT2, DRAIN, EN2, GATE,
PG, PG2, PGIO, RAMP, SCL2, SDA2, SS, TMR, V , V
S
REF
4mV
K
V
=
, RANGE = –55°C TO 150°C, RESOLUTION = 0.625°C, ACCURACY = 1°C
9100 F40
ADIN
Figure 40. Precision 10-Bit Remote Temperature Sense
9100f
49
For more information www.linear.com/LTM9100
LTM9100
Typical applicaTions
5V
V
V
ON
SCL
SDA
EN
V
CC2
V
CC
V4
CC
L
UVL
UVH
SCL2
SDA2
OV
LTC2990
1.5k
1.5k
470pF
MMBT3904
LTM9100
SCL
SDA
SCL
SDA
V3
V2
+
SENSE
SENSE
470pF
MMBT3904
–
ADR0
ADR1
GND
GND
V
EE
V1
PINS NOT USED IN THIS CIRCUIT:
ADIN, ADIN2, ADR0, ADR1, ALERT, ALERT2, DRAIN, EN2, GATE,
PG, PG2, PGIO, RAMP, SS, TMR, V
S
9100 F41
RANGE = –55°C TO 150°C, RESOLUTION = 0.06°C, ACCURACY = 0.5°C
Figure 41. I2C Precision 14-Bit Remote (or Local) Dual Temperature Sense
5V
V
V
V
CC2
UVH
CC
L
C
R
1.5k
ON
EN
SCL
SDA
UVL
RAMP
1k
LTM9100
1M
DRAIN
GATE
D1
D3
Q1
10Ω
AC SUPPLY
1Ω
47nF
TO LOAD(S)
1µF
+
SENSE
R
S
–
D2
D4
SENSE
OV
GND
9100 F42
V
EE
PINS NOT USED IN THIS CIRCUIT:
ADIN, ADIN2, ADR0, ADR1, ALERT, ALERT2, EN2,
PG, PG2, PGIO, SCL2, SDA2, SS, TMR, V
S
n(# OF LINE CYCLES) • 1/60Hz • 20µA
n • 16.7ms • 20µA
C
=
=
R
V
V
AC(PK)
AC(PK)
Figure 42. Transformer Inrush Current Limiter, n Line Cycle Ramp
9100f
50
For more information www.linear.com/LTM9100
LTM9100
Typical applicaTions
+
VBUS
R2
R1
INDUCTIVE
LOAD
D1
C
R
1k
ADIN
RAMP
5V
V
V
ON
SCL
SDA
EN
CC
L
1M
DRAIN
GATE
1.5k
LTM9100
Q1
ENABLE
V
CC2
10Ω
UVH
UVL
47nF
+
SENSE
R
S
–
SENSE
OV
GND
V
EE
–
VBUS
9100 F43
PINS NOT USED IN THIS CIRCUIT:
ADIN2, ADR0, ADR1, ALERT, ALERT2, EN2,
PG, PG2, PGIO, SCL2, SDA2, SS, TMR, V
S
∆t • 20µA
C
=
R
V
BUS
Figure 43. Inductive Load Current Limiter – Controlled Turn-On
AC
Q1
5V
V
V
ON
SCL
SDA
EN
GATE
CC
L
Q3
2N7002
V
CC2
1.5k
10Ω
47nF
UVH
UVL
LTM9100
GATE
GATE ENABLE
V
S
V
UV
DD
LT1640L
SENSE
V
EE
OV
+
SENSE
SENSE
R
S
–
GND
OV
V
EE
Q2
PINS NOT USED IN THIS CIRCUIT:
ADIN, ADIN2, ADR0, ADR1, ALERT, ALERT2, DRAIN, EN2,
PG, PG2, PGIO, RAMP, SCL2, SDA2, SS, TMR
9100 F44
AC
Figure 44. AC Circuit Breaker
9100f
51
For more information www.linear.com/LTM9100
LTM9100
Typical applicaTions
+
LOAD
R1
C
R
1Ω
D1
D3
R2
R3
ADIN2 UVH UVL
OV
1N4148
5V
V
V
CC
L
ON
SCL
SDA
EN
ALERT
PG
SCL
Q2
AC
SUPPLY
C
LTM9100
L
SDA
GATE ENABLE
INTERRUPT
PG2
GATE DRAIN
POWER GOOD
–
+
GND
V
EE
SENSE SENSE
2N3904
10Ω
2N7002 2N3904
1µF
D2
D4
47nF
1M
R
S
–
LOAD
Q1
9100 F45
PINS NOT USED IN THIS CIRCUIT:
ADIN, ADR0, ADR1, ALERT2, EN2, PGIO,
RAMP, SCL2, SDA2, SS, TMR, V , V
CC2
S
C
L
I
≈ 10µA •
, Q2 VOLTAGE RATING > V
AC(PK)
INRUSH
C
R
Figure 45. Low Side Switch Controller with Rectified AC-DC Link (DC Bus with Ripple)
+
C
R
LOAD
1k
RAMP
DRAIN
GATE
V
5V
CC
1M
V
L
C
D3
D5
D1
L1
ON
SCL
SDA
EN
1.5k
Q1
LTM9100
GATE
ENABLE
V
UVH
UVL
CC2
1Ω
10Ω
47nF
AC
SUPPLY
+
–
SENSE
1µF
R
S
SENSE
OV
C
D4
D6
D2
L2
GND
V
EE
9100 F46
–
LOAD
PINS NOT USED IN THIS CIRCUIT:
ADIN, ADIN2, ADR0, ADR1, ALERT, ALERT2, EN2,
PG, PG2, PGIO, SCL2, SDA2, SS, TMR, V
S
Figure 46. Inrush Current Limiting for AC Voltage Doubler
9100f
52
For more information www.linear.com/LTM9100
LTM9100
package DescripTion
Please refer to http://www.linear.com/product/LTM9100#packaging for the most recent package drawings.
BGA Package
42-Lead (22mm × 9mm × 5.16mm)
(Reference LTC DWG# 05-08-1973 Rev Ø)
Z
SEE NOTES
DETAIL A
A
aaa
Z
7
E
Y
A2
X
SEE NOTES
3
7
6
5
4
3
2
1
PIN 1
A
B
C
D
E
PIN “A1”
CORNER
A1
b
4
ccc
Z
b1
MOLD
CAP
F
SUBSTRATE
H1
G
H
J
H2
DETAIL B
D
F
K
L
Øb (42 PLACES)
ddd
eee
M
M
Z
Z
X Y
M
N
P
R
S
T
DETAIL A
e
aaa
Z
e
b
G
PACKAGE TOP VIEW
DETAIL B
PACKAGE SIDE VIEW
PACKAGE BOTTOM VIEW
NOTES:
10.16
8.89
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
0.635 0.025 Ø 42ꢀ
3
4
BALL DESIGNATION PER JESD MS-028 AND JEP95
DIMENSIONS
NOM
5.16
SYMBOL
A
A1
A2
b
b1
D
E
MIN
4.91
0.50
4.41
0.60
0.60
MAX
5.41
0.70
4.71
0.90
0.66
NOTES
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
0.60
4.56
0.75
0.63
22.0
9.0
1.27
5. PRIMARY DATUM -Z- IS SEATING PLANE
6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu
7
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
e
0.00
F
G
20.32
7.62
H1
H2
aaa
bbb
ccc
ddd
eee
0.46
3.95
0.56
4.00
0.66
4.05
0.15
0.10
0.15
0.15
0.08
LTMXXXXXX
µModule
6.35
7.62
8.89
10.16
COMPONENT
PIN “A1”
TOTAL NUMBER OF BALLS: 42
TRAY PIN 1
BEVEL
9.84
PACKAGE IN TRAY LOADING ORIENTATION
10.48
BGA 42 0714 REV Ø
SUGGESTED PCB LAYOUT
TOP VIEW
9100f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
53
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTM9100
Typical applicaTion
High Side 380V Bus Inrush Current Limiter with Line Voltage Monitor and I2C Only Control
IXTH30N60L2
0.017Ω
+
LOAD
380V
10Ω
22nF
1k
RAMP
39nF
3.3M
DRAIN GATE
+
–
SENSE SENSE
LTC2054
V
V
EE
EN2
CC2
3.3M
2.29V AT
330µF
+
–
235V 100Ω
UVH
UVL
32.4k
V
V
5V
LTM9100
CC
L
8.45k
1.5k
1.5k
ON
EN
SCL
SDA
GND
32.4k
2.56V AT
ADIN
435V
SCL
SDA
3.92k
3.3M
1.77V AT
435V
OV
8.87k
–
LOAD
380V RTN
9100 TA02
PINS NOT USED IN THIS CIRCUIT:
ADIN2, ADR0, ADR1, ALERT, ALERT2, PG, PG2, PGIO, SCL2, SDA2, SS, TMR, V
S
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LTM2881
Isolated RS485/RS422 µModule Transceiver with Integrated DC/DC
Converter
20Mbps 2500V
Package
Isolation with Power in LGA/BGA
RMS
LTM2882
LTM2883
Dual Isolated RS232 µModule Transceiver with Integrated DC/DC Converter 2500V
Isolation with Power in LGA/BGA Package
Isolation with Power in BGA Package
RMS
RMS
2
SPI/Digital or I C Isolated µModule with Adjustable 5V, and ±12.5V
Nominal Voltage Rails
2500V
LTM2884
LTM2885
Isolated High Speed USB µModule with Integrated DC/DC Converter
2500V
Isolation with Power in BGA Package
RMS
Isolated RS485/RS422 µModule Transceiver with integrated DC/DC
converter
20Mbps 6500V
Isolation with Power in BGA Package
RMS
2
LTM2886
SPI/Digital or I C Isolated µModule with Adjustable 5V, and Fixed ±5V
2500V
Isolation with Power in BGA Package
RMS
Power Rails
2
LTM2887
LTM2889
LTM2892
LTM2893
LTM2894
LTC1535
LTC4260
LTC4261
SPI/Digital or I C Isolated µModule with Two Adjustable 5V Rails
2500V
Isolation with Power in BGA Package
RMS
Isolated CAN µModule Transceiver with Integrated DC/DC Converter
4Mbps 2500V
Isolation with Power in BGA Package
RMS
2
SPI/Digital or I C Isolated µModule
3500V
6000V
7500V
2500V
Isolation in BGA Package
RMS
RMS
RMS
RMS
Complete 100MHz SPI ADC µModule Isolator
Complete Isolated USB µModule Transceiver
Isolated RS485 Transceiver
Isolation in Surface Mount BGA
Isolation in Surface Mount Package
Isolation with External Transformer Drive
2
Positive High Voltage Hot Swap Controller
Negative High Voltage Hot Swap Controller
With I C and ADC, Supplies from 8.5V to 80V
2
With I C and ADC, Supplies from –12V to –100V
9100f
LT 0217 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
54
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM9100
●
●
LINEAR TECHNOLOGY CORPORATION 2017
相关型号：
LTM9100HY#PBF
LTM9100 - Anyside™ High Voltage Isolated Switch Controller with I<sup>2</sup>C Command and Telemetry; Package: BGA; Pins: 42; Temperature Range: -40°C to 125°C
Linear
LTM9100IY#PBF
LTM9100 - Anyside™ High Voltage Isolated Switch Controller with I<sup>2</sup>C Command and Telemetry; Package: BGA; Pins: 42; Temperature Range: -40°C to 85°C
Linear
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