LTVA_技术文档

LTC2421/LTC2422

1-/2-Channel 20-Bit µPower

No Latency ∆Σ^TMADCs in MSOP-10

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FEATURES

DESCRIPTIO

■

20-Bit ADCs in Tiny MSOP-10 Packages

TheLTC^®2421/LTC2422are1-and2-channel2.7Vto5.5V

micropower 20-bit analog-to-digital converters with an

integrated oscillator, 8ppm INL and 1.2ppm RMS noise.

■

1- or 2-Channel Inputs

■

Single Supply 2.7V to 5.5V Operation

Low Supply Current (200µA) and Auto Shutdown

■

These ultrasmall devices use delta-sigma technology and

■

Automatic Channel Selection (Ping-Pong) (LTC2422) anewdigitalfilterarchitecturethatsettlesinasinglecycle.

No Latency: Digital Filter Settles in a

Single Conversion Cycle

8ppm INL, No Missing Codes

4ppm Full-Scale Error

0.5ppm Offset

1.2ppm Noise

Zero Scale and Full Scale Set for Reference

and Ground Sensing

Internal Oscillator—No External Components Required

110dB Min, 50Hz/60Hz Notch Filter

Reference Input Voltage: 0.1V to V_CC

Live Zero—Extended Input Range Accommodates

12.5% Overrange and Underrange

Pin Compatible with LTC2401/LTC2402

This eliminates the latency found in conventional ∆Σ

converters and simplifies multiplexed applications.

■

Through a single pin, the LTC2421/LTC2422 can be

configured for better than 110dB rejection at 50Hz or

60Hz ±2%, or can be driven by an external oscillator for

a user defined rejection frequency in the range 1Hz to

120Hz. The internal oscillator requires no external fre-

quency setting components.

■

These converters accept an external reference voltage

from 0.1V to V_CC. With an extended input conversion

range of –12.5% V_REFto 112.5% V_REF(V_REF= FS_SET

ZS_SET), the LTC2421/LTC2422 smoothly resolve the off-

set and overrange problems of preceding sensors or

signal conditioning circuits.

–

■

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APPLICATIO S

The LTC2421/LTC2422 communicate through a 2- or

3-wire digital interface that is compatible with SPI and

MICROWIRE^TMprotocols.

, LTC and LT are registered trademarks of Linear Technology Corporation.

No Latency ∆Σ is a trademark of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

■

Weight Scales

■

Direct Temperature Measurement

■

Gas Analyzers

Strain Gauge Transducers

Instrumentation

Data Acquisition

Industrial Process Control

■

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Pseudo Differential Bridge Digitizer

TYPICAL APPLICATIO

2.7V TO 5.5V

1

V

CC

1µF

V

CC

= INTERNAL OSC/50Hz REJECTION

1

10

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

LTC2422

SET

V

F

O

CC

LTC2422

2

4

3

5

FS

9

SCK

SDO

CS

2

3

4

5

9

8

7

6

REFERENCE VOLTAGE

ZS + 0.1V TO V

FS

SET

SCK

SDO

CS

8

3-WIRE

SPI INTERFACE

CH0

CH1

ZS

SET

CC

3-WIRE

SPI INTERFACE

ANALOG INPUT RANGE

CH1

CH0

ZS

7

ZS

– 0.12V

TO

SET

FS

REF

+ 0.12V

SET

REF

10

(V

= FS

– ZS

)

REF

SET

F

SET

O

INTERNAL OSCILLATOR

60Hz REJECTION

GND

6

0V TO FS

– 100mV

GND

SET

24212 TA01

24012TA02

24212f

1

LTC2421/LTC2422

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ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Operating Temperature Range

Supply Voltage (V_CC) to GND.......................–0.3V to 7V

Analog Input Voltage to GND ....... –0.3V to (V_CC+ 0.3V)

Reference Input Voltage to GND .. –0.3V to (V_CC+ 0.3V)

Digital Input Voltage to GND........ –0.3V to (V_CC+ 0.3V)

Digital Output Voltage to GND ..... –0.3V to (V_CC+ 0.3V)

LTC2421/LTC2422C ................................ 0°C to 70°C

LTC2421/LTC2422I ............................ –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

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PACKAGE/ORDER INFORMATION

ORDER PART NUMBER

TOP VIEW

LTC2421CMS

LTC2421IMS

V

CC

10 F

1

2

3

4

5

10 F

O

LTC2422CMS

LTC2422IMS

V

SET

V

1

2

3

CC

O

FS

9

8

7

6

SCK

SDO

CS

9

8

7

6

SCK

SDO

CS

SET

CH1

CH0

IN

NC 4

SET

ZS

SET

ZS

5

GND

MS10 PART MARKING

MS10 PACKAGE

10-LEAD PLASTIC MSOP

MS10 PACKAGE

10-LEAD PLASTIC MSOP

LTUX

LTUY

LTUZ

LTVA

T_JMAX= 125°C, θ_JA= 130°C/W

Consult factory for parts specified with wider operating temperature ranges.

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CONVERTER CHARACTERISTICS _{The ● denotes specifications which apply over the full operating}

temperature range, otherwise specifications are at T_A= 25°C. V_REF= FS_SET– ZS_SET. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

20

TYP

MAX

UNITS

Bits

Resolution

●

No Missing Codes Resolution

Integral Nonlinearity

0.1V ≤ FS

≤ V , ZS = 0V (Note 5)

SET

20

Bits

SET

CC

FS = 2.5V, ZS = 0V (Note 6)

●

4

8

10

20

ppm of V

SET

REF

FS = 5V, ZS = 0V (Note 6)

SET

Offset Error

2.5V ≤ FS

≤ V , ZS = 0V

●

0.5

0.04

4

10

ppm of V

SET

CC

SET

REF

Offset Error Drift

Full-Scale Error

2.5V ≤ FS

≤ V , ZS = 0V

ppm of V /°C

REF

CC

SET

≤ V , ZS = 0V

●

10

ppm of V

REF

CC

SET

Full-Scale Error Drift

Total Unadjusted Error

≤ V , ZS = 0V

0.04

ppm of V /°C

REF

CC

SET

FS = 2.5V, ZS = 0V

8

16

ppm of V

SET

REF

FS = 5V, ZS = 0V

SET

Output Noise

V

IN

= 0V (Note 13)

6

µV

RMS

Normal Mode Rejection 60Hz ±2%

Normal Mode Rejection 50Hz ±2%

Power Supply Rejection, DC

(Note 7)

(Note 8)

●

110

130

100

110

dB

FS = 2.5V, ZS = 0V, V = 0V

SET

IN

Power Supply Rejection, 60Hz ±2% FS = 2.5V, ZS = 0V, V = 0V, (Notes 7, 15)

SET

IN

Power Supply Rejection, 50Hz ±2% FS = 2.5V, ZS = 0V, V = 0V, (Notes 8, 15)

SET

IN

24212f

2

LTC2421/LTC2422

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A ALOG I PUT A D REFERE CE

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_REF= FS_SET– ZS_SET. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

ZS – 0.12V

TYP

MAX

FS + 0.12V

REF

UNITS

V

Input Voltage Range

(Note 14)

●

IN

SET

REF

SET

FS

SET

Full-Scale Set Range

Zero-Scale Set Range

Input Sampling Capacitance

Reference Sampling Capacitance

Input Leakage Current

0.1 + ZS

0

V

CC

ZS

FS – 0.1

SET

V

SET

C

1

1.5

1

pF

nA

S(IN)

S(REF)

I

CS = V

●

–100

100

IN(LEAK)

REF(LEAK)

CC

V

= 2.5V, CS = V

1

^{Reference Leakage Curre}U ^nt

REF

CC

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The ● denotes specifications which apply over the full

DIGITAL I PUTS A D DIGITAL OUTPUTS

operating temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

2.7V ≤ V ≤ 5.5V

MIN

TYP

MAX

UNITS

V

High Level Input Voltage

●

2.5

2.0

V

IH

IL

IH

IL

CC

CS, F

2.7V ≤ V ≤ 3.3V

O

CC

Low Level Input Voltage

CS, F

4.5V ≤ V ≤ 5.5V

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V

O

CC

High Level Input Voltage

SCK

2.7V ≤ V ≤ 5.5V (Note 9)

2.5

2.0

V

CC

2.7V ≤ V ≤ 3.3V (Note 9)

CC

Low Level Input Voltage

SCK

4.5V ≤ V ≤ 5.5V (Note 9)

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V (Note 9)

CC

I

Digital Input Current

0V ≤ V ≤ V

CC

–10

10

µA

pF

V

IN

CS, F

O

Digital Input Current

SCK

0V ≤ V ≤ V (Note 9)

10

IN

CC

C

V

Digital Input Capacitance

10

IN

CS, F

O

Digital Input Capacitance

SCK

(Note 9)

IN

High Level Output Voltage

SDO

I = –800µA

O

●

V

– 0.5

OH

OL

OH

OL

CC

Low Level Output Voltage

SDO

I = 1.6mA

O

0.4

V

High Level Output Voltage

SCK

I = –800µA (Note 10)

O

– 0.5

V

CC

Low Level Output Voltage

SCK

I = 1.6mA (Note 10)

O

0.4

10

V

I

High-Z Output Leakage

SDO

–10

µA

OZ

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POWER REQUIRE E TS

The ● denotes specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

Supply Voltage

Supply Current

CONDITIONS

MIN

TYP

MAX

UNITS

V

●

2.7

5.5

V

CC

I

CC

Conversion Mode

Sleep Mode

CS = 0V (Note 12)

●

200

20

300

30

µA

CS = V (Note 12)

CC

24212f

3

LTC2421/LTC2422

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TI I G CHARACTERISTICS ^The● denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

2.56

0.5

TYP

MAX

307.2

390

UNITS

kHz

µs

f

t

External Oscillator Frequency Range

External Oscillator High Period

External Oscillator Low Period

Conversion Time

●

EOSC

HEO

0.5

390

µs

LEO

F

= 0V

O

●

130.86

157.03

133.53

160.23

EOSC

136.20

163.44

(in kHz)

ms

CONV

F = V

O

CC

External Oscillator (Note 11)

20510/f

f

Internal SCK Frequency

Internal Oscillator (Note 10)

External Oscillator (Notes 10, 11)

19.2

kHz

ISCK

f

/8

EOSC

D

Internal SCK Duty Cycle

(Note 10)

(Note 9)

45

55

%

kHz

ns

ISCK

f

t

External SCK Frequency Range

External SCK Low Period

●

2000

ESCK

250

1.23

LESCK

External SCK High Period

ns

HESCK

DOUT_ISCK

Internal SCK 24-Bit Data Output Time

Internal Oscillator (Notes 10, 12)

External Oscillator (Notes 10, 11)

●

1.25

1.28

ms

192/f

(in kHz)

EOSC

t

External SCK 24-Bit Data Output Time

CS ↓ to SDO Low Z

CS ↑ to SDO High Z

CS ↓ to SCK ↓

(Note 9)

●

24/f

(in kHz)

ms

ns

DOUT_ESCK

ESCK

0

150

1

2

(Note 10)

(Note 9)

0

3

CS ↓ to SCK ↑

50

4

SCK ↓ to SDO Valid

SDO Hold After SCK ↓

SCK Set-Up Before CS ↓

SCK Hold After CS ↓

200

KQMAX

KQMIN

(Note 5)

15

50

t

5

6

50

Note 1: Absolute Maximum Ratings are those values beyond which the

life of the device may be impaired.

Note 2: All voltage values are with respect to GND.

Note 9: The converter is in external SCK mode of operation such that

the SCK pin is used as digital input. The frequency of the clock signal

driving SCK during the data output is f_ESCKand is expressed in kHz.

Note 10: The converter is in internal SCK mode of operation such that

the SCK pin is used as digital output. In this mode of operation, the

SCK pin has a total equivalent load capacitance C_LOAD= 20pF.

Note 11: The external oscillator is connected to the F_Opin. The external

oscillator frequency, f_EOSC, is expressed in kHz.

Note 3: V_CC= 2.7 to 5.5V unless otherwise specified. Input source

resistance = 0Ω.

Note 4: Internal Conversion Clock source with the F_Opin tied

to GND or to V_CCor to external conversion clock source with

f

_EOSC= 153600Hz unless otherwise specified.

Note 12: The converter uses the internal oscillator.

Note 5: Guaranteed by design, not subject to test.

F_O= 0V or F_O= V_CC

.

Note 6: Integral nonlinearity is defined as the deviation of a code from

a straight line passing through the actual endpoints of the transfer

curve. The deviation is measured from the center of the quantization

band.

Note 13: The output noise includes the contribution of the internal

calibration operations.

Note 14: V_REF= FS_SET– ZS_SET. The minimum input voltage is limited

to –0.3V and the maximum to V_CC+ 0.3V.

Note 7: F_O= 0V (internal oscillator) or f_EOSC= 153600Hz ±2%

(external oscillator).

Note 15: V_CC(DC) = 4.1V, V_CC(AC) = 2.8V_P-P.

Note 8: F_O= V_CC(internal oscillator) or f_EOSC= 128000Hz ±2%

(external oscillator).

24212f

4

LTC2421/LTC2422

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TYPICAL PERFOR A CE CHARACTERISTICS

Negative Extended Input Range

Total Unadjusted Error (3V Supply)

INL (3V Supply)

10

8

10

8

10

8

V

= 3V

REF

T

= 90°C

V

= 3V

REF

V

= 3V

CC

= 2.5V

REF

CC

A

CC

= 2.5V

T

= 25°C

A

6

T

= –45°C

4

A

2

0

T

A

= –55°C

–2

–4

–6

–8

–10

–2

–4

–6

–8

–10

–2

–4

–6

–8

–10

T

= –55°C, –45°C, 25°C, 90°C

T

= –55°C, –45°C, 25°C, 90°C

A

0

–0.05

–0.15 –0.20 –0.25 –0.30

0

0.5

1.0

1.5

2.0

2.5

0

0.5

1.0

1.5

2.0

2.5

–0.10

INPUT VOLTAGE (V)

24212 G03

24212 G01

24212 G02

Positive Extended Input Range

Total Unadjusted Error (3V Supply)

Total Unadjusted Error (5V Supply)

INL (5V Supply)

10

8

10

8

10

8

V

= 3V

REF

CC

V

= 5V

REF

V

= 5V

REF

CC

= 2.5V

= 5V

6

4

2

0

–2

–4

–6

–8

–10

–2

–4

–6

–8

–10

–2

–4

–6

–8

–10

T

= –55°C, –45°C, 25°C, 90°C

T

A

= –55°C, –45°C, 25°C, 90°C

T

A

= –55°C, –45°C, 25°C, 90°C

A

2.50 2.55

2.65 2.70 2.75 2.80

2.60

0

1

2

3

4

5

0

1

2

3

4

5

INPUT VOLTAGE (V)

24212 G04

24212 G05

24212 G06

Negative Extended Input Range

Total Unadjusted Error (5V Supply)

Positive Extended Input Range

Total Unadjusted Error (5V Supply)

Offset Error vs Reference Voltage

10

8

150

120

90

60

30

0

10

8

T

= 25°C

V

= 5V

V

= 5V

V

A

= 5V

CC

A

CC

REF

CC

REF

T

= 25°C

T

= 90°C

= –45°C

A

6

A

6

4

T

= –55°C

A

2

0

–2

–4

–6

–8

–10

–2

–4

–6

–8

–10

T

= –55°C

= –45°C

A

T

= 90°C

T = 25°C

A

0

–0.05

–0.15 –0.20 –0.25 –0.30

INPUT VOLTAGE (V)

–0.10

5.00 5.05

5.15 5.20 5.25 5.30

INPUT VOLTAGE (V)

0

1

2

3

4

5

5.10

REFERENCE VOLTAGE (V)

24212 G07

24212 G08

24212 G09

24212f

5

LTC2421/LTC2422

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TYPICAL PERFOR A CE CHARACTERISTICS

RMS Noise vs Reference Voltage

Offset Error vs V_CC

RMS Noise vs V_CC

60

50

10

5

10.0

7.5

V

T

= 5V

V

T

= 2.5V

V

= 2.5V

REF

CC

REF

= 25°C

T

= 25°C

A

40

30

0

5.0

20

10

0

–5

2.5

–10

0

1

2

3

4

5

2.7

3.2

3.7

4.2

(V)

4.7

5.2 5.5

2.7

3.2

3.7

4.2

(V)

4.7

5.2 5.5

REFERENCE VOLTAGE (V)

V

CC

V

CC

24212 G10

24212 G11

24212 G12

Noise Histogram

RMS Noise vs Code Out

Offset Error vs Temperature

350

300

250

200

150

100

50

5.00

3.75

2.50

1.25

10

5

V

= 5V

V

= 5V

V

= 5

REF

= 0

CC

REF

IN

CC

REF

= 0V

IN

CC

= 5

= 0.3V TO 5.3V

IN

T

= 25°C

A

0

–5

0

–10

0

4

–55 –30 –5

20

45

70

95 120

–2

0

2

6

0

7FFFF

FFFFF

CODE OUT (HEX)

TEMPERATURE (°C)

OUTPUT CODE (ppm)

24212 G13

24212 G14

24212 G15

Full-Scale Error

vs Reference Voltage

Full-Scale Error vs Temperature

Full-Scale Error vs V_CC

0

10

5

10

5

V

= 5V

REF

= 5V

V

= 2.5V

REF

CC

= 5V

V

= 2.5V

IN

–25

T

A

= 25°C

IN

–50

–75

0

–100

–125

–150

–5

V

= 5V

REF

CC

IN

= V

–10

0

1

2

3

4

5

–55 –30 –5

20

45

70

95 120

2.7

3.2

3.7

4.2

(V)

4.7

5.2 5.5

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

V

CC

24212 G17

24212 G16

24212 G18

24212f

6

LTC2421/LTC2422

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TYPICAL PERFOR A CE CHARACTERISTICS

Conversion Current

vs Temperature

Sleep Current vs Temperature

Rejection vs Frequency at V_CC

30

20

10

0

230

220

210

200

190

180

170

160

150

V

T

= 4.1V

= 0V

CC

IN

A

–20

= 25°C

V

= 5.5V

= 4.1V

= 2.7V

CC

F

= 0

O

V

CC

= 2.7V

–40

–60

V

CC

V

CC

= 5V

–80

–100

–120

V

1

100

10k

1M

–30

–5

45

70

95 120

–55 –30 –5

20

45

70

95 120

–55

20

TEMPERATURE (°C)

FREQUENCY AT V (Hz)

TEMPERATURE (°C)

CC

24212 G23

24212 G19

24212 G20

Rejection vs Frequency at V_CC

Rejection vs Frequency at V_IN

–20

–40

0

–20

0

V

T

= 4.1V

= 0V

V

T

= 4.1V

= 0V

CC

IN

V

F

= 5V

CC

IN

CC

= 5V

REF

= 25°C

–20

= 25°C

A

O

= 2.5V

A

O

IN

F

= 0

F

= 0

O

–40

–60

–80

–100

–120

–100

–120

–100

–120

1

50

100

150

200

250

15200

15300 15350 15400 15450 15500

1

50

100

150

200

250

15250

FREQUENCY AT V (Hz)

CC

FREQUENCY AT V (Hz)

IN

CC

24212 G21

24212 G22

24212 G24

Rejection vs Frequency at V_IN

0

–60

–70

0

–20

–40

V

= 5V

CC

= 5V

REF

–20

= 2.5V

IN

F

= 0

O

–80

–40

–60

–90

–60

–80

–100

–110

–120

–130

–140

–80

–100

–120

–100

–120

–140

SAMPLE RATE = 15.36kHz ±2%

15100

15200

15300

15400

15500

–12

–8

–4

0

4

8

12

0

f /2

S

f

S

FREQUENCY AT V (Hz)

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

INPUT FREQUENCY

IN

24212 G26

24212 G25

24212 G27

24212f

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LTC2421/LTC2422

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TYPICAL PERFOR A CE CHARACTERISTICS

INL vs Output Rate

Resolution vs Output Rate

24

22

20

18

16

20

18

16

20

18

16

V

F

= 3V

REF

= EXTERNAL

V

F

= 5V

CC

REF

= 2.5V

= EXTERNAL

O

T

= –45°C

A

T

= –45°C

A

T

= 25°C

A

14

12

10

14

12

10

T

= 25°C

V

O

= 5V

REF

= EXTERNAL

A

CC

T

= 90°C

T

= 90°C

A

= 5V

T

= 25°C

= 90°C

= –45°C

f

A

STANDARD DEVIATION

OF 100 SAMPLES

0 7.5

25

50

75

100

0

10 20 30 40 50 60 70 80 90 100

0

10 20 30 40 50 60 70 80 90 100

OUTPUT RATE (Hz)

24212 G30

24212 G29

24212 G28

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PIN FUNCTIONS

V_CC(Pin 1): Positive Supply Voltage. Bypass to GND

(Pin 6) with a 10µF tantalum capacitor in parallel with

0.1µF ceramic capacitor as close to the part as possible.

be connected directly to a ground plane through a mini-

mum length trace or it should be the single-point-ground

in a single-point grounding system.

FS_SET(Pin 2): Full-Scale Set Input. This pin defines the

full-scale input value. When V_IN= FS_SET, the ADC outputs

full scale (FFFFF_H). The total reference voltage is

CS (Pin 7): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion, the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW on CS wakes up the ADC. A

LOW-to-HIGH transition on this pin disables the SDO

digitaloutput.ALOW-to-HIGHtransitiononCSduringthe

Data Output transfer aborts the data transfer and starts a

new conversion.

FS_SET– ZS_SET

.

CH0, CH1 (Pins 4, 3): Analog Input Channels. The input

voltage range is –0.125 • V_REFto 1.125 • V_REF. For

V_REF> 2.5V, the input voltage range may be limited by the

absolute maximum rating of –0.3V to V_CC+ 0.3V. Conver-

sions are performed alternately between CH0

and CH1 for the LTC2422. Pin 4 is a No Connect (NC) on

the LTC2421.

SDO (Pin 8): Three-State Digital Output. During the data

output period, this pin is used for serial data output. When

the chip select CS is HIGH (CS = V_CC), the SDO pin is in a

high impedance state. During the Conversion and Sleep

periods, this pin can be used as a conversion status out-

put. The conversion status can be observed by pulling CS

LOW.

ZS_SET(Pin 5): Zero-Scale Set Input. This pin defines the

zero-scale input value. When V_IN= ZS_SET, the ADC

outputs zero scale (00000_H).

GND (Pin 6): Ground. Shared pin for analog ground,

digitalground,referencegroundandsignalground.Should

24212f

8

LTC2421/LTC2422

U

PIN FUNCTIONS

SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal

SerialClockOperationmode, SCKisusedasdigitaloutput

fortheinternalserialinterfaceclockduringthedataoutput

period. In the External Serial Clock Operation mode, SCK

is used as digital input for the external serial interface. An

internal pull-up current source is automatically activated

in Internal Serial Clock Operation mode. The Serial Clock

mode is determined by the level applied to SCK at power

up and the falling edge of CS.

F_O(Pin 10): Frequency Control Pin. Digital input that

controls the ADC’s notch frequencies and conversion

time. When the F_Opin is connected to V_CC(F_O= V_CC), the

converter uses its internal oscillator and the digital filter’s

first null is located at 50Hz. When the F_Opin is connected

to GND (F_O= 0V), the converter uses its internal oscillator

and the digital filter’s first null is located at 60Hz. When F_O

isdrivenbyanexternalclocksignalwithafrequencyf_EOSC

,

the converter uses this signal as its clock and the digital

filter first null is located at a frequency f_EOSC/2560.

U

W

FUNCTIONAL BLOCK DIAGRA

INTERNAL

OSCILLATOR

V

CC

GND

AUTOCALIBRATION

AND CONTROL

F

O

(INT/EXT)

V

IN

∫

SDO

SERIAL

INTERFACE

∑

ADC

SCK

CS

V

REF

DECIMATING FIR

DAC

24212 FD

TEST CIRCUITS

V

CC

3.4k

C

SDO

= 20pF

3.4k

C

= 20pF

LOAD

Hi-Z TO V

OL

OH

V

TO V

OL

V

OL

V

OH

TO V

OH

OL

TO Hi-Z

24212 TC02

TO Hi-Z

24212 TC01

24212f

9

LTC2421/LTC2422

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APPLICATIO S I FOR ATIO

The LTC2421/LTC2422 are pin compatible with the

LTC2401/LTC2402. The devices are designed to allow the

user to incorporate either device in the same design with

nomodifications.WhiletheLTC2421/LTC2422outputword

length is 24 bits (as opposed to the 32-bit output of the

LTC2401/LTC2402), its output clock timing can be identi-

cal to the LTC2401/LTC2402. As shown in Figure 1, the

LTC2421/LTC2422 data output is concluded on the falling

edge of the 24th serial clock (SCK). In order to maintain

drop-in compatibility with the LTC2401/LTC2402, it is

possibletoclocktheLTC2421/LTC2422withanadditional

8serialclockpulses.Thisresultsin8additionaloutputbits

which are always logic HIGH.

Once CS is pulled LOW and SCK rising edge is applied, the

devicebeginsoutputtingtheconversionresult.Thereisno

latency in the conversion result. The data output corre-

sponds to the conversion just performed. This result is

shifted out on the serial data out pin (SDO) under the

control of the serial clock (SCK). Data is updated on the

falling edge of SCK allowing the user to reliably latch data

on the rising edge of SCK, see Figure 4. The data output

state is concluded once 24 bits are read out of the ADC or

when CS is brought HIGH. The device automatically

initiates a new conversion and the cycle repeats.

Through timing control of the CS and SCK pins, the

LTC2421/LTC2422offerseveralflexiblemodesofopera-

tion (internal or external SCK and free-running conver-

sion modes). These various modes do not require

programming configuration registers; moreover, they do

not disturb the cyclic operation described above. These

modes of operation are described in detail in the Serial

Interface Timing Modes section.

Converter Operation Cycle

The LTC2421/LTC2422 are low power, delta-sigma ana-

log-to-digital converters with an easy to use 3-wire serial

interface. Their operation is simple and made up of three

states. The converter operating cycle begins with the con-

version,followedbythesleepstateandconcludedwiththe

dataoutput(seeFigure2). The3-wireinterfaceconsistsof

serial data output (SDO), a serial clock (SCK) and a chip

select (CS).

CONVERT

SLEEP

Initially,theLTC2421/LTC2422performaconversion.Once

the conversion is complete, the device enters the sleep

state. While in this sleep state, power consumption is re-

duced by an order of magnitude if CS is HIGH. The part

remains in the sleep state as long as CS is logic HIGH. The

conversion result is held indefinitely in a static shift regis-

ter while the converter is in the sleep state.

1

CS AND

SCK

0

DATA OUTPUT

24212 F02

Figure 2. LTC2421/LTC2422 State Transition Diagram

CS

8

8 (OPTIONAL)

SCK

SDO

EOC = 1

EOC = 0

SLEEP

EOC = 1

DATA OUT

4 STATUS BITS 20 DATA BITS

LAST 8 BITS ALWAYS 1

CONVERSION

DATA OUTPUT

CONVERSION

24212 F01

Figure 1. LTC2421/LTC2422 Compatible Timing with the LTC2401/LTC2402

24212f

10

LTC2421/LTC2422

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APPLICATIO S I FOR ATIO

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Conversion Clock

above. The first conversion result following POR is accu-

rate within the specifications of the device.

A major advantage delta-sigma converters offer over con-

ventional type converters is an on-chip digital filter (com-

monly known as Sinc or Comb filter). For high resolution,

low frequency applications, this filter is typically designed

to reject line frequencies of 50Hz or 60Hz plus their har-

monics. In order to reject these frequencies in excess of

110dB,ahighlyaccurateconversionclockisrequired.The

LTC2421/LTC2422 incorporate an on-chip highly accu-

rate oscillator. This eliminates the need for external fre-

quency setting components such as crystals or oscilla-

tors. Clocked by the on-chip oscillator, the LTC2421/

LTC2422 reject line frequencies (50Hz or 60Hz ±2%) a

minimum of 110dB.

Reference Voltage Range

TheLTC2421/LTC2422canacceptareferencevoltage(V_REF

= FS_SET– ZS_SET) from 0V to V_CC. The converter output

noise is determined by the thermal noise of the front-end

circuits, and as such, its value in microvolts is nearly con-

stant with reference voltage. A decrease in reference volt-

age will not significantly improve the converter’s effective

resolution. On the other hand, a reduced reference voltage

will improve the overall converter INL performance. The

recommended range for the LTC2421/LTC2422 voltage

reference is 100mV to V_CC.

Input Voltage Range

Ease of Use

Theconverterisabletoaccommodatesystemleveloffset

and gain errors as well as system level overrange situa-

tions due to its extended input range, see Figure 3. The

LTC2421/LTC2422 convert input signals within the ex-

tended input range of –0.125 • V_REFto 1.125 • V_REF

(V_REF= FS_SET– ZS_SET).

The LTC2421/LTC2422 data output has no latency, filter

settling or redundant data associated with the conver-

sion cycle. There is a one-to-one correspondence be-

tween the conversion and the output data. Therefore,

multiplexing an analog input voltage is easy.

The LTC2421/LTC2422 perform offset and full-scale cali-

brations every conversion cycle. This calibration is trans-

parenttotheuserandhasnoeffectonthecyclicoperation

describedabove. Theadvantageofcontinuouscalibration

is extreme stability of offset and full-scale readings with

respect to time, supply voltage change and temperature

drift.

For large values of V_REF(V_REF= FS_SET– ZS_SET), this range

is limited by the absolute maximum voltage range of

–0.3V to (V_CC+ 0.3V). Beyond this range, the input ESD

protection devices begin to turn on and the errors due to

the input leakage current increase rapidly.

Input signals applied to V_INmay extend below ground by

–300mV and above V_CCby 300mV. In order to limit any

Power-Up Sequence

V

+ 0.3V

CC

TheLTC2421/LTC2422automaticallyenteraninternalreset

state when the power supply voltage V_CCdrops below

approximately 2.2V. This feature guarantees the integrity

of the conversion result and of the serial interface mode

selection which is performed at the initial power-up. (See

the2-wireI/OsectionsintheSerialInterfaceTimingModes

section.)

FS

+ 0.12V

FS

SET

REF

SET

ABSOLUTE

MAXIMUM

INPUT

NORMAL

INPUT

RANGE

EXTENDED

INPUT

RANGE

ZS

SET

REF

When the V_CCvoltage rises above this critical threshold,

the converter creates an internal power-on-reset (POR)

signal with duration of approximately 0.5ms. The POR

signal clears all internal registers. Following the POR sig-

nal,theLTC2421/LTC2422start anormalconversioncycle

and follows the normal succession of states described

ZS

SET

– 0.12V

–0.3V

24212 F03

(V

REF

= FS

– ZS

)

SET

Figure 3. LTC2421/LTC2422 Input Range

24212f

11

LTC2421/LTC2422

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APPLICATIO S I FOR ATIO

fault current, a resistor of up to 5k may be added in series

with the V_INpin without affecting the performance of the

device. In the physical layout, it is important to maintain

the parasitic capacitance of the connection between this

series resistance and the V_INpin as low as possible; there-

fore, the resistor should be located as close as practical to

the V_INpin. The effect of the series resistance on the con-

verter accuracy can be evaluated from the curves pre-

sented in the Analog Input/Reference Current section. In

addition, a series resistor will introduce a temperature de-

pendent offset error due to the input leakage current. A

1nA input leakage current will develop a 1ppm offset error

on a 5k resistor if V_REF= 5V. This error has a very strong

temperature dependency.

0 ≤ V_IN≤ V_REF, this bit is LOW. If the input is outside the

normal input range, V_IN> V_REFor V_IN< 0, this bit is HIGH.

The function of these bits is summarized in Table 1.

Table 1. LTC2421/LTC2422 Status Bits

Bit 23

EOC

Bit 22

Bit 21

SIG

Bit 20

EXR

Input Range

> V

CH0/CH1

V

0

*0/1

1

0

1

IN

REF

0 < V ≤ V

IN

REF

–

+

V

= 0 /0

1/0

0

IN

< 0

*Bit 22 displays the channel number for the LTC2422. Bit 22 is always

0 for the LTC2421

Bit 19 (fifth output bit) is the most significant bit (MSB).

Bits 19-0 are the 20-bit conversion result MSB first.

Bit 0 is the least significant bit (LSB).

Output Data Format

TheLTC2421/LTC2422serialoutputdatastreamis24bits

long. The first 4 bits represent status information indicat-

ing the sign, selected channel, input range and conversion

state. Thenext20bitsaretheconversionresult, MSBfirst.

DataisshiftedoutoftheSDOpinundercontroloftheserial

clock (SCK), see Figure 4. Whenever CS is HIGH, SDO

remains high impedance and any SCK clock pulses are

ignored by the internal data out shift register.

Bit 23 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

In order to shift the conversion result out of the device, CS

mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe

deviceonceCSispulledLOW.EOCchangesrealtimefrom

HIGH to LOW at the completion of a conversion. This sig-

nal may be used as an interrupt for an external microcon-

troller.Bit23(EOC)canbecapturedonthefirstrisingedge

of SCK. Bit 22 is shifted out of the device on the first falling

edge of SCK. The final data bit (Bit 0) is shifted out on the

falling edge of the 23rd SCK and may be latched on the

risingedgeofthe24thSCKpulse.Onthefallingedgeofthe

24th SCK pulse, SDO goes HIGH indicating a new conver-

sion cycle has been initiated. This bit serves as EOC (Bit

23) for the next conversion cycle. Table 2 summarizes the

output data format.

Bit 22 (second output bit) for the LTC2422, this bit is LOW

if the last conversion was performed on CH0 and HIGH for

CH1. This bit is always LOW for the LTC2421.

Bit 21 (third output bit) is the conversion result sign indi-

cator (SIG). If V_INis >0, this bit is HIGH. If V_INis <0, this

bitisLOW.Thesignbitchangesstateduringthezerocode.

Bit20(fourthoutputbit)istheextendedinputrange(EXR)

indicator. If the input is within the normal input range

CS

BIT 23

EOC

BIT 22

BIT 21

SIG

BIT 20

EXT

BIT 19

MSB

BIT 4

BIT 0

SDO

SCK

LSB

20

CH0/CH1

Hi-Z

1

2

3

4

5

19

20

24

SLEEP

DATA OUTPUT

CONVERSION

24212 F04

Figure 4. Output Data Timing

24212f

12

LTC2421/LTC2422

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APPLICATIO S I FOR ATIO

U

Table 2. LTC2421/LTC2422 Output Data Format

Bit 23

EOC

Bit 22*

CH0/CH1

Bit 21

SIG

Bit 20

EXR

Bit 19

MSB

Bit 18

Bit 17

Bit 16

Bit 15

…

Bit 0

LSB

Input Voltage

> 9/8 • V

V

0

CH0/CH1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

...

1

0

1

0

1

0

1

0

1

0

1

0

IN

REF

9/8 • V

1

REF

V

+ 1LSB

1

REF

1

3/4V

1/2V

1/4V

+ 1LSB

1

REF

1

+

–

0 /0

1/0**

–1LSB

0

–1/8 • V

REF

V

< –1/8 • V

REF

IN

*Bit 22 is always 0 for the LTC2421 **The sign bit changes state during the 0 code.

As long as the voltage on the V_INpin is maintained within

the –0.3V to (V_CC+ 0.3V) absolute maximum operating

range, a conversion result is generated for any input value

from –0.125 • V_REFto 1.125 • V_REF. For input voltages

greaterthan1.125•V_REF,theconversionresultisclamped

to the value corresponding to 1.125 • V_REF. For input volt-

agesbelow–0.125•V_REF,theconversionresultisclamped

When a fundamental rejection frequency different from

50Hz or 60Hz is required or when the converter must be

synchronized with an outside source, the LTC2421/

LTC2422 can operate with an external conversion clock.

The converter automatically detects the presence of an

external clock signal at the F_Opin and turns off the internal

oscillator. The frequency f_EOSCof the external signal must

be at least 2560Hz (1Hz notch frequency) to be detected.

The external clock signal duty cycle is not significant as

long as the minimum and maximum specifications for the

high and low periods t_HEOand t_LEOare observed.

to the value corresponding to –0.125 • V_REF

.

Frequency Rejection Selection (F_OPin Connection)

The LTC2421/LTC2422 internal oscillator provides better

than 110dB normal mode rejection at the line frequency

and all its harmonics for 50Hz ±2% or 60Hz ±2%. For

60Hz rejection, F_O(Pin 10) should be connected to GND

(Pin 6) while for 50Hz rejection the F_Opin should be con-

nected to V_CC(Pin 1).

While operating with an external conversion clock of a

frequencyf_EOSC,theLTC2421/LTC2422providebetterthan

110dB normal mode rejection in a frequency range f_EOSC

/

2560 ±4% and its harmonics. The normal mode rejection

as a function of the input frequency deviation from f_EOSC

2560 is shown in Figure 5.

/

The selection of 50Hz or 60Hz rejection can also be made

by driving F_Oto an appropriate logic level. A selection

change during the sleep or data output states will not

disturb the converter operation. If the selection is made

duringtheconversionstate, theresultoftheconversionin

progress may be outside specifications but the following

conversions will not be affected.

Whenever an external clock is not present at the F_Opin, the

converterautomaticallyactivatesitsinternaloscillatorand

enters the Internal Conversion Clock mode. The LTC2421/

LTC2422 operation will not be disturbed if the change of

conversion clock source occurs during the sleep state or

during the data output state while the converter uses an

24212f

13

LTC2421/LTC2422

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APPLICATIO S I FOR ATIO

–60

synchronous 3-wire interface. During the conversion and

sleep states, this interface can be used to assess the con-

verter status and during the data output state, it is used to

read the conversion result.

–70

–80

–90

–100

–110

–120

–130

–140

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 9) is used to

synchronizethedatatransfer.Eachbitofdataisshiftedout

the SDO pin on the falling edge of the serial clock.

–12

–8

–4

0

4

8

12

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2421/LTC2422 create their own serial

clock by dividing the internal conversion clock by 8. In the

External SCK mode of operation, the SCK pin is used as

input. The internal or external SCK mode is selected on

power-up and then reselected every time a HIGH-to-LOW

transition is detected at the CS pin. If SCK is HIGH or

floating at power-up or during this transition, the con-

verter enters the internal SCK mode. If SCK is LOW at

power-up or during this transition, the converter enters

the external SCK mode.

INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)

24212 F05

Figure 5. LTC2421/LTC2422 Normal Mode Rejection When

Using an External Oscillator of Frequency f_EOSC

external serial clock. If the change occurs during the con-

version state, the result of the conversion in progress may

be outside specifications but the following conversions

will not be affected. If the change occurs during the data

output state and the converter is in the Internal SCK mode,

the serial clock duty cycle may be affected but the serial

data stream will remain valid.

Serial Data Output (SDO)

Table 3 summarizes the duration of each state as a func-

tion of F_O.

The serial data output pin, SDO (Pin 8), drives the serial

data during the data output state. In addition, the SDO pin

is used as an end of conversion indicator during the con-

version and sleep states.

SERIAL INTERFACE

The LTC2421/LTC2422 transmit the conversion results

and receives the start of conversion command through a

When CS (Pin 7) is HIGH, the SDO driver is switched to a

high impedance state. This allows sharing the serial

Table 3. LTC2421/LTC2422 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

F = LOW

(60Hz Rejection)

133ms

O

F = HIGH

O

160ms

(50Hz Rejection)

External Oscillator

F = External Oscillator

20510/f

s

EOSC

O

with Frequency f

kHz

EOSC

(f

EOSC

/2560 Rejection)

SLEEP

As Long As CS = HIGH Until CS = 0 and SCK

DATA OUTPUT

Internal Serial Clock

External Serial Clock with

F = LOW/HIGH

(Internal Oscillator)

As Long As CS = LOW But Not Longer Than 1.28ms

(24 SCK cycles)

O

F = External Oscillator with

As Long As CS = LOW But Not Longer Than 192/f

ms

EOSC

O

Frequency f

kHz

(24 SCK cycles)

EOSC

As Long As CS = LOW But Not Longer Than 24/f ms

SCK

Frequency f

kHz

(24 SCK cycles)

SCK

24212f

14

LTC2421/LTC2422

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APPLICATIO S I FOR ATIO

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interface with other devices. If CS is LOW during the con-

vert or sleep state, SDO will output EOC. If CS is LOW

duringtheconversionphase,theEOCbitappearsHIGHon

the SDO pin. Once the conversion is complete, EOC goes

LOW. The device remains in the sleep state until the first

rising edge of SCK occurs while CS = 0. While in the sleep

state, the device is in a LOW power state if CS is HIGH.

these serial interface timing modes in detail. In all these

cases, the converter can use the internal oscillator (F_O=

LOW or F_O= HIGH) or an external oscillator connected to

the F_Opin. Refer to Table 4 for a summary.

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out

the conversion result and a CS signal to monitor and con-

trol the state of the conversion cycle, see Figure 6.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 7), is used to test the

conversionstatusandtoenablethedataoutputtransferas

described in the previous sections.

The serial clock mode is selected on the falling edge of CS.

Toselecttheexternalserialclockmode,theserialclockpin

(SCK) must be LOW during each CS falling edge.

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer has

been completed. The LTC2421/LTC2422 will abort any

serial data transfer in progress and start a new conversion

cycle anytime a LOW-to-HIGH transition is detected at the

CSpinaftertheconverterhasenteredthedataoutputstate

(i.e., after the first rising edge of SCK occurs with CS = 0).

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is LOW, EOC is output to the SDO pin. EOC = 1

while a conversion is in progress and EOC = 0 if the device

is in the sleep state. Independent of CS, the device auto-

matically enters the sleep state once the conversion is

complete. While in the sleep state, power is reduced an

order of magnitude if CS is HIGH.

Finally, CS can be used to control the free-running modes

of operation, see Serial Interface Timing Modes section.

Grounding CS will force the ADC to continuously convert

at the maximum output rate selected by F_O. Tying a ca-

pacitor to CS will reduce the output rate and power dissi-

pation by a factor proportional to the capacitor’s value,

see Figures 13 to 15.

When the device is in the sleep state (EOC = 0), its

conversion result is held in an internal static shift register.

The device remains in the sleep state until the first rising

edge of SCK is seen while CS is LOW. Data is shifted out

the SDO pin on each falling edge of SCK. This enables

external circuitry to latch the output on the rising edge of

SCK. EOC can be latched on the first rising edge of SCK

and the last bit of the conversion result can be latched on

the 24th rising edge of SCK. On the 24th falling edge of

SCK, thedevicebeginsanewconversion. SDOgoesHIGH

(EOC = 1) indicating a conversion is in progress.

SERIAL INTERFACE TIMING MODES

The LTC2421/LTC2422’s 3-wire interface is SPI and

MICROWIRE compatible. This interface offers several

flexible modes of operation. These include internal/exter-

nal serial clock, 2- or 3-wire I/O, single cycle conversion

and autostart. The following sections describe each of

Table 4. LTC2421/LTC2422 Interface Timing Modes

Conversion

Cycle

Control

Data

Output

Control

Connection

and

Waveforms

SCK

Configuration

Source

External

Internal

External SCK, Single Cycle Conversion

External SCK, 2-Wire I/O

CS and SCK

SCK

CS and SCK

SCK

Figures 6, 7

Figure 8

Internal SCK, Single Cycle Conversion

Internal SCK, 2-Wire I/O, Continuous Conversion

Internal SCK, Autostart Conversion

CS ↓

Figures 9, 10

Figure 11

Continuous

Internal

C

EXT

Figure 12

24212f

15

LTC2421/LTC2422

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APPLICATIO S I FOR ATIO

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z.

As described above, CS may be pulled LOW at any time in

order to monitor the conversion status.

CS HIGH anytime between the first rising edge and the

24th falling edge of SCK, see Figure 7. On the rising edge

of CS, the device aborts the data output state and imme-

diately initiates a new conversion. This is useful for sys-

tems not requiring all 24 bits of output data, aborting an

invalid conversion cycle or synchronizing the start of a

conversion.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

2.7V TO 5.5V

V

CC

1µF

= INTERNAL OSC/50Hz REJECTION

1

10

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

V

F

O

CC

LTC2422

2

9

8

7

6

REFERENCE VOLTAGE

FS

SCK

SDO

CS

SET

ZS

+ 0.1V TO V

SET

CC

3

4

5

3-WIRE

SERIAL I/O

ANALOG INPUT RANGE

CH1

CH0

ZS

– 0.12V

TO

SET

FS

REF

+ 0.12V

SET

REF

(V

= FS

– ZS

)

REF

SET

0V TO FS

– 100mV

GND

SET

CS

TEST EOC

BIT 23

EOC

BIT 22

CH0/CH1

BIT 21

SIG

BIT 20

EXR

BIT 19

MSB

BIT 18

BIT 4

BIT 0

LSB

SDO

20

Hi-Z

SCK

(EXTERNAL)

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

24212 F06

Figure 6. External Serial Clock, Single Cycle Operation

2.7V TO 5.5V

V

CC

1µF

= INTERNAL OSC/50Hz REJECTION

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

1

10

V

F

O

CC

LTC2422

2

3

4

5

9

8

7

6

REFERENCE VOLTAGE

FS

SCK

SDO

CS

SET

ZS

+ 0.1V TO V

SET

CC

3-WIRE

SERIAL I/O

ANALOG INPUT RANGE

CH1

CH0

ZS

– 0.12V

TO

REF

)

SET

FS

REF

+ 0.12V

SET

(V

= FS

– ZS

REF

SET

0V TO FS

– 100mV

GND

SET

CS

TEST EOC

BIT 0

EOC

BIT 23

EOC

BIT 22

BIT 21

SIG

BIT 20

EXR

BIT 19

MSB

BIT 9

BIT 8

SDO

SCK

CH0/CH1

Hi-Z

(EXTERNAL)

SLEEP

CONVERSION

DATA OUTPUT

SLEEP

DATA OUTPUT

CONVERSION

24212 F07

Figure 7. External Serial Clock, Reduced Data Output Length

24212f

16

LTC2421/LTC2422

W U U

APPLICATIO S I FOR ATIO

U

External Serial Clock, 2-Wire I/O

goes HIGH (EOC = 1) indicating a new conversion has

begun.

This timing mode utilizes a 2-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal, see Figure 8. CS

maybepermanentlytiedtoground(Pin6),simplifyingthe

user interface or isolation barrier.

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and con-

trol the state of the conversion cycle, see Figure 9.

The external serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 0.5ms after V_CCexceeds 2.2V. The level

applied to SCK at this time determines if SCK is internal or

external. SCK must be driven LOW prior to the end of POR

in order to enter the external serial clock timing mode.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

Since CS is tied LOW, the end-of-conversion (EOC) can

be continuously monitored at the SDO pin during the

convert and sleep states. EOC may be used as an inter-

rupt to an external controller indicating the conversion

resultisready.EOC=1whiletheconversionisinprogress

and EOC = 0 once the conversion enters the low power

sleep state. On the falling edge of EOC, the conversion

result is loaded into an internal static shift register. The

deviceremainsinthesleepstateuntilthefirstrisingedge

of SCK. Data is shifted out the SDO pin on each falling

edge of SCK enabling external circuitry to latch data on

the rising edge of SCK. EOC can be latched on the first

rising edge of SCK. On the 24th falling edge of SCK, SDO

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state.

WhentestingEOC, iftheconversioniscomplete(EOC=0),

the device will exit the sleep state and enter the data output

state if CS remains LOW. In order to prevent the device

from exiting the low power sleep state, CS must be pulled

2.7V TO 5.5V

V

CC

1µF

= INTERNAL OSC/50Hz REJECTION

1

10

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

V

F

O

CC

LTC2422

2

3

4

5

9

8

7

6

REFERENCE VOLTAGE

FS

SET

SCK

SDO

CS

ZS

+ 0.1V TO V

SET

CC

2-WIRE SERIAL I/O

ANALOG INPUT RANGE

CH1

CH0

ZS

– 0.12V

TO

SET

FS

REF

+ 0.12V

SET

REF

(V

= FS

– ZS

)

REF

SET

0V TO FS

SET

– 100mV

GND

SET

CS

BIT 23

EOC

BIT 22

CH0/CH1

BIT 21

SIG

BIT 20

EXR

BIT 19

MSB

BIT 18

BIT 4

BIT 0

LSB

SDO

20

SCK

(EXTERNAL)

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

24212 F08

Figure 8. External Serial Clock, CS = 0 Operation

24212f

17

LTC2421/LTC2422

APPLICATIO S I FOR ATIO

W U U

U

V

CC

2.7V TO 5.5V

V

CC

1µF

= INTERNAL OSC/50Hz REJECTION

10k

1

10

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

V

F

O

CC

LTC2422

2

9

8

7

6

REFERENCE VOLTAGE

ZS + 0.1V TO V

FS

SCK

SDO

CS

SET

CC

3

4

5

ANALOG INPUT RANGE

CH1

CH0

ZS

– 0.12V

TO

SET

FS

REF

+ 0.12V

SET

REF

(V

= FS

SET

– ZS

)

REF

SET

0V TO FS

SET

– 100mV

GND

SET

<t

EOCtest

CS

TEST EOC

BIT 23

EOC

BIT 22

BIT 21

SIG

BIT 20

EXR

BIT 19

MSB

BIT 18

BIT 4

BIT 0

LSB

SDO

CH0/CH1

20

Hi-Z

SCK

(INTERNAL)

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

24212 F09

Figure 9. Internal Serial Clock, Single Cycle Operation

HIGH before the first rising edge of SCK. In the internal

SCK timing mode, SCK goes HIGH and the device begins

outputting data at time t_EOCtestafter the falling edge of CS

(if EOC = 0) or t_EOCtestafter EOC goes LOW (if CS is LOW

duringthefallingedgeofEOC).Thevalueoft_EOCtestis23µs

if the device is using its internal oscillator (F₀= logic LOW

or HIGH). If F_Ois driven by an external oscillator of fre-

quency f_EOSC, then t_EOCtestis 3.6/f_EOSC. If CS is pulled

HIGH before time t_EOCtest, the device remains in the sleep

state. The conversion result is held in the internal static

shift register.

CS HIGH anytime between the first and24th rising edge of

SCK, see Figure 10. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

new conversion. This is useful for systems not requiring

all 24 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

pulled HIGH while the converter is driving SCK LOW, the

internal pull-up is not available to restore SCK to a logic

HIGH state. This will cause the device to exit the internal

serial clock mode on the next falling edge of CS. This can

be avoided by adding an external 10k pull-up resistor to

theSCKpinorbyneverpullingCSHIGHwhenSCKisLOW.

If CS remains LOW longer than t_EOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shiftedoutoftheSDOpin. Thedataoutputcyclebeginson

this first rising edge of SCK and concludes after the 24th

rising edge. Data is shifted out the SDO pin on each falling

edgeofSCK.Theinternallygeneratedserialclockisoutput

to the SCK pin. This signal may be used to shift the con-

version result into external circuitry. EOC can be latched

on the first rising edge of SCK and the last bit of the con-

version result on the 24th rising edge of SCK. After the

24th rising edge, SDO goes HIGH (EOC = 1), SCK stays

HIGH, and a new conversion starts.

Whenever SCK is LOW, the LTC2421/LTC2422’s internal

pull-up at pin SCK is disabled. Normally, SCK is not exter-

nallydrivenifthedeviceisintheinternalSCKtimingmode.

However,certainapplicationsmayrequireanexternaldriver

on SCK. If this driver goes Hi-Z after outputting a LOW

signal, the LTC2421/LTC2422’s internal pull-up remains

disabled. Hence, SCK remains LOW. On the next falling

edge of CS, the device is switched to the external SCK

timing mode. By adding an external 10k pull-up resistor to

SCK, this pin goes HIGH once the external driver goes

Hi-Z. On the next CS falling edge, the device will remain in

the internal SCK timing mode.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

24212f

18

LTC2421/LTC2422

W U U

APPLICATIO S I FOR ATIO

U

V

CC

2.7V TO 5.5V

V

CC

1µF

= INTERNAL OSC/50Hz REJECTION

10k

1

10

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

V

F

O

CC

LTC2422

2

9

8

7

6

REFERENCE VOLTAGE

ZS + 0.1V TO V

FS

SET

SCK

SDO

CS

SET CC

3

4

5

ANALOG INPUT RANGE

CH1

CH0

ZS

– 0.12V

TO

SET

FS

REF

+ 0.12V

SET

REF

(V

= FS

– ZS

)

REF

SET

0V TO FS

SET

– 100mV

GND

SET

>t

EOCtest

<t

EOCtest

CS

TEST EOC

BIT 0

EOC

BIT 23

EOC

BIT 22

BIT 21

SIG

BIT 20

EXR

BIT 19

MSB

BIT 18

BIT 8

SDO

CH0/CH1

Hi-Z

SCK

(INTERNAL)

SLEEP

CONVERSION

DATA OUTPUT

SLEEP

DATA OUTPUT

CONVERSION

24212 F10

Figure 10. Internal Serial Clock, Reduced Data Output Length

A similar situation may occur during the sleep state when

CS is pulsed HIGH-LOW-HIGH in order to test the conver-

sionstatus.Ifthedeviceisinthesleepstate(EOC=0),SCK

will go LOW. Once CS goes HIGH (within the time period

defined above as t_EOCtest), the internal pull-up is activated.

For a heavy capacitive load on the SCK pin, the internal

pull-up may not be adequate to return SCK to a HIGH level

before CS goes low again. This is not a concern under

normal conditions where CS remains LOW after detecting

EOC = 0. This situation is easily overcome by adding an

external 10k pull-up resistor to the SCK pin.

weak pull-up is active during the POR cycle; therefore, the

internal serial clock timing mode is automatically selected

if SCK is not externally driven LOW (if SCK is loaded such

that the internal pull-up cannot pull the pin HIGH, the ex-

ternal SCK mode will be selected).

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1). Once the conversion is

complete, SCK and SDO go LOW (EOC = 0) indicating the

conversion has finished and the device has entered the

sleepstate.Thepartremainsinthesleepstateaminimum

amount of time (1/2 the internal SCK period) then imme-

diatelybeginsoutputtingdata.Thedataoutputcyclebegins

on the first rising edge of SCK and ends after the 24th

risingedge. DataisshiftedouttheSDOpinoneachfalling

edge of SCK. The internally generated serial clock is out-

put to the SCK pin. This signal may be used to shift the

conversionresultintoexternalcircuitry.EOCcanbelatched

on the first rising edge of SCK and the last bit of the

conversion result can be latched on the 24th rising edge

of SCK. After the 24th rising edge, SDO goes HIGH

(EOC=1)indicatinganewconversionisinprogress. SCK

remains HIGH during the conversion.

Internal Serial Clock, 2-Wire I/O,

Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO)

interface. Theconversionresultisshiftedoutofthedevice

by an internally generated serial clock (SCK) signal, see

Figure 11. CS may be permanently tied to ground (Pin 6),

simplifying the user interface or isolation barrier.

The internal serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 0.5ms after V_CCexceeds 2.2V. An internal

24212f

19

LTC2421/LTC2422

APPLICATIO S I FOR ATIO

W U U

U

V

CC

2.7V TO 5.5V

V

CC

1µF

= INTERNAL OSC/50Hz REJECTION

1

10

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

V

F

O

10k

CC

LTC2422

2

9

8

7

6

REFERENCE VOLTAGE

ZS + 0.1V TO V

FS

SCK

SDO

CS

SET

SET CC

3

4

5

ANALOG INPUT RANGE

CH1

CH0

ZS

– 0.12V

TO

SET

FS

REF

+ 0.12V

SET

REF

(V

= FS

SET

– ZS

)

REF

SET

0V TO FS

– 100mV

GND

SET

CS

BIT 23

EOC

BIT 22

BIT 21

SIG

BIT 20

EXR

BIT 19

MSB

BIT 18

BIT 4

BIT 0

LSB

SDO

CH0/CH1

20

SCK

(INTERNAL)

CONVERSION

DATA OUTPUT

CONVERSION

24212 F11

SLEEP

Figure 11. Internal Serial Clock, Continuous Operation

Internal Serial Clock, Autostart Conversion

It should be noticed that the external capacitor discharge

current is kept very small in order to decrease the con-

verterpowerdissipationinthesleepstate. Intheautostart

mode, the analog voltage on the CS pin cannot be

observed without disturbing the converter operation

using a regular oscilloscope probe. When using this con-

figuration, it is important to minimize the external leakage

current at the CS pin by using a low leakage external ca-

pacitor and properly cleaning the PCB surface.

This timing mode is identical to the internal serial clock,

2-wire I/O described above with one additional feature.

Instead of grounding CS, an external timing capacitor is

tied to CS.

While the conversion is in progress, the CS pin is held

HIGH by an internal weak pull-up. Once the conversion is

complete, the device enters the low power sleep state and

an internal 25nA current source begins discharging the

capacitor tied to CS, see Figure 12. The time the converter

spends in the sleep state is determined by the value of the

external timing capacitor, see Figures 13 and 14. Once the

voltageatCSfallsbelowaninternalthreshold(≈1.4V), the

device automatically begins outputting data. The data out-

put cycle begins on the first rising edge of SCK and ends

on the 24th rising edge. Data is shifted out the SDO pin on

each falling edge of SCK. The internally generated serial

clock is output to the SCK pin. This signal may be used to

shift the conversion result into external circuitry. After the

24th rising edge, CS is pulled HIGH and a new conversion

is immediately started. This is useful in applications re-

quiring periodic monitoring and ultralow power. Figure 15

shows the average supply current as a function of capaci-

tance on CS.

The internal serial clock mode is selected every time the

voltage on the CS pin crosses an internal threshold volt-

age. An internal weak pull-up at the SCK pin is active while

CS is discharging; therefore, the internal serial clock tim-

ing mode is automatically selected if SCK is floating. It is

important to ensure there are no external drivers pulling

SCK LOW while CS is discharging.

DIGITAL SIGNAL LEVELS

The LTC2421/LTC2422’s digital interface is easy to use.

Its digital inputs (F_O, CS and SCK in External SCK mode of

operation)acceptstandardTTL/CMOSlogiclevelsandthe

internal hysteresis receivers can tolerate edge rates as

slowas100µs.However,someconsiderationsarerequired

24212f

20

LTC2421/LTC2422

W U U

APPLICATIO S I FOR ATIO

U

V

CC

2.7V TO 5.5V

V

CC

1µF

= INTERNAL OSC/50Hz REJECTION

10k

1

10

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/60Hz REJECTION

V

F

O

CC

LTC2422

2

9

8

7

6

REFERENCE VOLTAGE

ZS + 0.1V TO V

FS

SCK

SDO

CS

SET

CC

3

4

5

ANALOG INPUT RANGE

CH1

CH0

ZS

– 0.12V

TO

SET

FS

REF

+ 0.12V

SET

REF

(V

= FS

– ZS

)

REF

SET

C

EXT

0V TO FS

– 100mV

GND

SET

V

CC

CS

GND

BIT 23

EOC

BIT 22

BIT 21

SIG

BIT 0

SDO

Hi-Z

SCK

(INTERNAL)

CONVERSION

DATA OUTPUT

CONVERSION

SLEEP

2420 F12

Figure 12. Internal Serial Clock, Autostart Operation

300

250

7

6

250

V

= 5V

= 3V

V

= 5V

= 3V

CC

5

4

3

2

1

0

200

150

200

150

100

50

0

100

50

0

V

= 5V

CC

V

= 3V

CC

1

10

100

1000

10000 100000

1

10

100

1000

10000 100000

10

100

100000

1

1000

10000

CAPACITANCE ON CS (pF)

24212 F15

24212 F13

Figure 13. CS Capacitance vs t_SAMPLE

Figure 14. CS Capacitance

vs Output Rate

Figure 15. CS Capacitance

vs Supply Current

to take advantage of exceptional accuracy and low supply

current.

In order to preserve the LTC2421/LTC2422’s accuracy, it

is very important to minimize the ground path impedance

whichmayappearinserieswiththeinputand/orreference

signal and to reduce the current which may flow through

this path. The GND pin should be connected to a low

24212f

The digital output signals (SDO and SCK in Internal SCK

modeofoperation)arelessofaconcernbecausetheyare

not generally active during the conversion state.

21

LTC2421/LTC2422

W U U

U

APPLICATIO S I FOR ATIO

resistance ground plane through a minimum length trace.

The use of multiple via holes is recommended to further

reduce the connection resistance.

Parallel termination near the LTC2421/LTC2422 pin will

eliminate this problem but will increase the driver power

dissipation.Aseriesresistorbetween27Ωand56Ωplaced

near the driver or near the LTC2421/LTC2422 pin will also

eliminate this problem without additional power dissipa-

tion. The actual resistor value depends upon the trace

impedance and connection topology.

In an alternative configuration, the GND pin of the con-

verter can be the single-point-ground in a single point

grounding system. The input signal ground, the reference

signal ground, the digital drivers ground (usually the digi-

tal ground) and the power supply ground (the analog

ground) should be connected in a star configuration with

the common point located as close to the GND pin as

possible.

Driving the Input and Reference

The analog input and reference of the typical delta-sigma

analog-to-digital converter are applied to a switched ca-

pacitornetwork.Thisnetworkconsistsofcapacitorsswitch-

ingbetweentheanaloginput(V_IN),ZS_SET(Pin5)andFS_SET

(Pin 2). The result is small current spikes seen at both V_IN

and V_REF. A simplified input equivalent circuit is shown in

Figure 16.

The power supply current during the conversion state

should be kept to a minimum. This is achieved by restrict-

ing the number of digital signal transitions occurring dur-

ing this period.

While a digital input signal is in the range 0.5V to

(V_CC– 0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,

when any one of the digital input signals (F_O, CS and SCK

inExternalSCKmodeofoperation)iswithinthisrange,the

LTC2421/LTC2422 power supply current may increase

even if the signal in question is at a valid logic level. For

micropower operation and in order to minimize the poten-

tialerrorsduetoadditionalgroundpincurrent,itisrecom-

mendedtodrivealldigitalinputsignalstofullCMOSlevels

[V_IL< 0.4V and V_OH> (V_CC– 0.4V)].

The key to understanding the effects of this dynamic input

current is based on a simple first order RC time constant

model. Using the internal oscillator, the LTC2421/

LTC2422’s internal switched capacitor network is clocked

at 153,600Hz corresponding to a 6.5µs sampling period.

Fourteentimeconstantsarerequiredeachtimeacapacitor

is switched in order to achieve 1ppm settling accuracy.

Therefore, the equivalent time constant at V_INand V_REF

should be less than 6.5µs/14 = 460ns in order to achieve

1ppm accuracy.

Severe ground pin current disturbances can also occur

due to the undershoot of fast digital input signals. Under-

shoot and overshoot can occur because of the imped-

ance mismatch at the converter pin when the transition

time of an external control signal is less than twice the

propagation delay from the driver to LTC2421/LTC2422.

For reference, on a regular FR-4 board, signal propaga-

tion velocity is approximately 183ps/inch for internal

traces and 170ps/inch for surface traces. Thus, a driver

generating a control signal with a minimum transition

timeof1nsmustbeconnectedtotheconverterpinthrough

a trace shorter than 2.5 inches. This problem becomes

particularly difficult when shared control lines are used

and multiple reflections may occur. The solution is to

carefully terminate all transmission lines close to their

characteristic impedance.

V

CC

R

SW

5k

I

REF(LEAK)

V

REF

V

CC

I

IN

AVERAGE INPUT CURRENT:

= 0.25(V – 0.5 • V )fC

REF EQ

R

SW

5k

I

IN

IN(LEAK)

IN

V

C

EQ

1pF (TYP)

R

SW

5k

24212 F16

GND

SWITCHING FREQUENCY

f = 153.6kHz FOR INTERNAL OSCILLATOR (f = LOGIC LOW OR HIGH)

f = f

O

FOR EXTERNAL OSCILLATORS

EOSC

Figure 16. LTC2421/LTC2422 Equivalent Analog Input Circuit

24212f

22

LTC2421/LTC2422

W U U

APPLICATIO S I FOR ATIO

U

Input Current (V_IN)

If the total capacitance at V_IN(see Figure 18) is small

(<0.01µF), relatively large external source resistances (up

to 80k for 20pF parasitic capacitance) can be tolerated

withoutanyoffset/full-scaleerror. Figures19and20show

a family of offset and full-scale error curves for various

small valued input capacitors (C_IN< 0.01µF) as a function

of input source resistance.

If complete settling occurs on the input, conversion re-

sultswillbeuneffectedbythedynamicinputcurrent. Ifthe

settling is incomplete, it does not degrade the linearity

performance of the device. It simply results in an offset/

full-scale shift, see Figure 17. To simplify the analysis of

input dynamic current, two separate cases are assumed:

large capacitance at V_IN(C_IN> 0.01µF) and small capaci-

tance at V_IN(C_IN< 0.01µF).

For large input capacitor values (C_IN> 0.01µF), the input

spikes are averaged by the capacitor into a DC current. The

gain shift becomes a linear function of input source resis-

tance independent of input capacitance, see Figures 21

and 22. The equivalent input impedance is 16.6MΩ. This

results in ±150nA of input dynamic current at the extreme

values of V_IN(V_IN= 0V and V_IN= V_REF, when V_REF= 5V).

This corresponds to a 0.3ppm shift in offset and full-scale

readings for every 10Ω of input source resistance.

TUE

35

C

= 22µF

IN

= 10µF

30

= 1µF

= 0.1µF

= 0.01µF

= 0.001µF

25

20

15

10

5

ZS

SET

FS

SET

V

IN

24212 F17

V

= 5V

CC

REF

IN

= 5V

= 0V

Figure 17. Offset/Full-Scale Shift

T

= 25°C

A

R

SOURCE

V

IN

INTPUT

LTC2421/

LTC2422

C

PAR

20pF

0

SIGNAL

C

IN

200

400

1000

0

600

800

SOURCE

R

(Ω)

SOURCE

24212 F17

24212 F20

Figure 20. Offset vs R_SOURCE(Large C)

Figure 18. An RC Network at V_IN

50

40

30

20

10

5

0

V

T

= 5V

CC

= 5V

REF

= 0V

IN

A

= 25°C

V

= 5V

CC

–5

= 5V

REF

= 0V

IN

–10

T

= 25°C

A

C

IN

= 1000pF

= 0pF

= 100pF

IN

C

IN

–15

–20

C

= 22µF

IN

C

= 0.01µF

IN

= 10µF

–25

–30

–35

= 1µF

= 0.1µF

= 0.01µF

= 0.001µF

0

1

10

100

1k

10k

100k

200

400

800

0

1000

600

R

(Ω)

SOURCE

R

(Ω)

SOURCE

24212 F19

24212 F21

Figure 21. Full-Scale Error vs R_SOURCE(Large C)

Figure 19. Offset vs R_SOURCE(Small C)

24212f

23

LTC2421/LTC2422

W U U

U

APPLICATIO S I FOR ATIO

60

10

C

= 22µF

VREF

= 10µF

50

= 1µF

0

= 0.1µF

= 0.01µF

= 0.001µF

40

30

–10

C

IN

= 1000pF

= 0pF

= 100pF

V

= 5V

IN

CC

REF

IN

= 5V

C

–20

–30

–40

–50

= 5V

C

IN

20

T

= 25°C

A

10

C

= 0.01µF

IN

V

= 5V

CC

= 5V

REF

0

= 5V

IN

T

= 25°C

A

–10

200

400

1000

0

600

800

(Ω)

1

10

100

R

1k

(Ω)

10k

100k

RESISTANCE AT V

REF

SOURCE

24212 F23

24212 F22

Figure 22. Full-Scale Error vs R_SOURCE(Small C)

Figure 23. Full-Scale Error vs R_VREF(Large C)

In addition to the input current spikes, the input ESD pro-

tection diodes have a temperature dependent leakage cur-

rent. This leakage current, nominally 1nA (±100nA max),

results in a fixed offset shift of 10µV for a 10k source

resistance.

500

V

T

= 5V

CC

= 5V

REF

400

= 5V

IN

A

= 25°C

C

= 1000pF

VREF

300

200

100

0

C

= 100pF

VREF

C

= 0.01µF

The effect of input leakage current is evident for C_IN= 0 in

Figures 19 and 22. A leakage current of 3nA results in a

150µV (30ppm) error for a 50k source resistance. As

R_SOURCEgets larger, the switched capacitor input current

begins to dominate.

VREF

C

= 0pF

VREF

–100

–200

10

100

RESISTANCE AT V

100k

1

1k

10k

(Ω)

Reference Current (V_REF

)

REF

24212 F24

Similar to the analog input, the reference input has a dy-

namic input current. This current has negligible effect on

the offset. However, the reference current at V_IN= V_REFis

similar to the input current at full-scale. For large values of

reference capacitance (C_VREF> 0.01µF), the full-scale er-

ror shift is 0.03ppm/Ω of external reference resistance

independent of the capacitance at V_REF, see Figure 23. If

the capacitance tied to V_REFis small (C_VREF< 0.01µF), an

input resistance of up to 80k (20pF parasitic capacitance

at V_REF) may be tolerated, see Figure 24.

Figure 24. Full-Scale Error vs R_VREF(Small C)

50

V

A

= 5V

REF

= 25°C

CC

= 5V

40

T

30

20

C

= 1000pF

VREF

C

= 100pF

VREF

10

C

VREF

= 0.01µF

0

Unlike the analog input, the integral nonlinearity of the

device can be degraded with excessive external RC time

constants tied to the reference input. If the capacitance at

node V_REFis small (C_VREF< 0.01µF), the reference input

can tolerate large external resistances without reduction

in INL, see Figure 25. If the external capacitance is large

(C_VREF> 0.01µF), the linearity will be degraded by

–10

–20

C

VREF

= 0pF

10

100

100k

1

1k

10k

RESISTANCE AT V

(Ω)

REF

24212 F25

Figure 25. INL Error vs R_VREF(Small C)

24212f

24

LTC2421/LTC2422

W U U

APPLICATIO S I FOR ATIO

0.015ppm/Ω independent of capacitance at V_REF, see

Figure 26.

U

0

–20

–40

Inadditiontothedynamicreferencecurrent, theV_REFESD

protection diodes have a temperature dependent leakage

current.Thisleakagecurrent,nominally1nA(±10nAmax),

results in a fixed full-scale shift of 10µV for a 10k source

resistance.

–60

–80

–100

–120

–140

10

C

VREF

C

VREF

C

VREF

C

VREF

C

VREF

C

VREF

= 22µF

8

6

= 10µF

f /2

S

f

0

S

= 1µF

= 0.1µF

= 0.01µF

= 0.001µF

INPUT FREQUENCY

4

24212 F27

2

Figure 27. Sinc⁴Filter Rejection

V

A

= 5V

REF

= 25°C

CC

0

= 5V

T

–2

–4

–6

–8

–10

The modulator contained within the LTC2421/LTC2422

can handle large-signal level perturbations without satu-

rating. Signal levels up to 40% of V_REFdo not saturate the

analog modulator. These signals are limited by the input

ESDprotectionto300mVbelowgroundand300mVabove

V_CC.

200

400

1000

0

600

800

(Ω)

RESISTANCE AT V

REF

24212 F26

Figure 26. INL Error vs R_VREF(Large C)

Simple Basic Program for Interfacing to the

LTC2421/LTC2422

ANTIALIASING

DTR

V

SCK

SDO

CS

One of the advantages delta-sigma ADCs offer over con-

ventional ADCs is on-chip digital filtering. Combined with

a large oversampling ratio, the LTC2421/LTC2422 signifi-

cantly simplify antialiasing filter requirements.

REF

PC

SERIAL

PORT

CTS

RTS

LTC2421

LTC2422

V

IN

GND

24212 F28

Figure 28

The digital filter provides very high rejection except at

integer multiples of the modulator sampling frequency

(f_S), see Figure 27. The modulator sampling frequency is

256 • F_O, where F_Ois the notch frequency (typically 50Hz

or 60Hz). The bandwidth of signals not rejected by the

digital filter is narrow (≈0.2%) compared to the band-

width of the frequencies rejected.

NOTE this program generates 32 SCK’s for compatibility to 24-bit parts

'For use with most LTC24xy demo boards

designed for the PC Com Port, QBASIC

'Outputs are chan%,signneg%,d2400 (magnitude), PPM, and v (volts)

CLS : ON ERROR GOTO 4970

As a result of the oversampling ratio (256) and the digital

filter, minimal (if any) antialias filtering is required in front

of the LTC2421/LTC2422. If passive RC components are

placed in front of the LTC2421/LTC2422, the input dy-

namic current should be considered (see Input Current

section). In cases where large effective RC time constants

are used, an external buffer amplifier may be required to

minimize the effects of input dynamic current.

cport = 1: REM INPUT "com port number "; cport

GOSUB 1900: timestart$ = TIME$

mcr% = port + 4: msr% = port + 6

COLOR 15: LOCATE 3, 1: PRINT "Hit any key to stop…

FOR np = 1 TO 2000: OUT port, c0%: NEXT np: 'Power Via TxD

DO: '-------------------------START LOOP here--------

";

24212f

25

LTC2421/LTC2422

W U U

U

APPLICATIO S I FOR ATIO

nummeas = nummeas + c1%

LOCATE 5, 21: PRINT "CHANNEL 1": LOCATE 5, 2: PRINT "CHANNEL 0"

FOR n% = port TO port + 7: OUT n%, 0: NEXT n%: ’Init UART regs

CLOSE #1: DEF SEG = 0: RETURN ’--------------------------------------

2000 ’SUB read MSR AND RETURN data dfrm% INTERFACE

LOCATE 2, 2: PRINT "Scan#="; nummeas; " "; DATE$; " "; TIME$;

OUT mcr%, c0%: 'Initialize SCLK=0

k1 = km: d2400 = 0: chan% = c0%: signneg% = c0%

FOR bita% = 31 TO 0 STEP -1: v31 = 1

x3% = INP(msr%) AND c16%: OUT mcr%, c1%

GOSUB 3000: OUT mcr%, c0%

148 GOSUB 2200: v31 = v31 + 1

2040 IF x3% = c16% THEN dfrm% = c1% ELSE dfrm% = c0%

OUT mcr%, c0%: RETURN ’---------------------------------------------

2200 ’SUB READ THE DATA BIT dfrm% does NOT change sclock

x3% = INP(msr%) AND C16%: GOTO 2040: RETURN’----------------

3000 REM delay sub !!!!!!!!!!

150 IF bita% = 31 THEN GOTO 152 ELSE 156

152 IF dfrm% = c0% THEN GOTO 156

155 IF v31 > 2 THEN LOCATE 16, 16: OUT port, c0%: PRINT "waiting for eoc":

IF v31 < 20000 THEN IF dfrm% = c1% THEN GOTO 148

IF dfrm% = 1 THEN LOCATE 17, 16: PRINT "Timed out on EOC,not fatal"

FOR bs = 1 TO 32: ' never got an eoc => clock it 32 times

GOSUB 2000: NEXT bs: GOTO 1800

FOR n8% = 0 TO 1: OUT port, c0%: NEXT n8%: RETURN: ’----------

3700 FOR n = 6 TO 9: LOCATE n, 20

PRINT "

": NEXT n: RETURN’---------------------------

156 LOCATE 16, 16: PRINT"

": GOSUB 2000

3800 ’SUB to convert PPM into Volts and print it

IF bita% = 30 THEN 161 ELSE 171 ' CHANNEL BIT !!!!!!!!!!!!!!!

161 IF dfrm% = c1% THEN chan% = c1%: ch1% = c0%

IF dfrm% = c0% THEN chan% = c0%: ch1% = ch1% + c1%

IF ch1% > c4% THEN GOSUB 3700: ch1% = c1%

v = PPM * (5 / 1000000): v1 = v * 1000000: hz% = (chan% * 20) + 12

IF v <= .1 THEN PRINT v1; " "; : LOCATE rw% + 1, hz%: PRINT "uV "

IF v > .1 THEN PRINT v; " "; : LOCATE rw% + 1, hz%: PRINT "Volts";

RETURN’----------------------------------------------------------------

4970 PRINT "ERROR !!!!!!!!!!!!!!!"

171 IF bita% = 29 THEN IF dfrm% = c0% THEN signneg% = c1%: ' NEG

IF bita% <= 28 THEN d2400 = d2400 + (dfrm% * k1): k1 = k1 / c2%

NEXT bita%: k1 = 1: digin% = c0%: 'MATH BELOW

5000 PRINT : LOCATE 18, 1: PRINT "Ending!!": PRINT "Hit any key to exit."

PRINT "Start ="; timestart$; " End = "; TIME$; " # samples ="; nummeas

1600 PPM = (d2400 / km) * kn: rw% = 6: hz% = (chan% * 20) + 1

IF signneg% = c1% THEN 1700 ELSE 1705

CLOSE #1: END

1700 IF d2400 <> c0% THEN PPM = (PPM - 2000000)

1705 LOCATE rw%, hz%: PRINT PPM; " "; : LOCATE rw%, hz% + 11:

PRINT "PPM";

Single Ended Half-Bridge Digitizer

with Reference and Ground Sensing

Sensorsconvertrealworldphenomena(temperature,pres-

sure, gas levels, etc.) into a voltage. Typically, this voltage

is generated by passing an excitation current through the

sensor. The wires connecting the sensor to the ADC form

parasiticresistorsR_P1andR_P2.Theexcitationcurrentalso

flowsthroughparasiticresistorsR_P1andR_P2, asshownin

Figure 29. The voltage drop across these parasitic resis-

tors leads to systematic offset and full-scale errors.

LOCATE rw% + 1, (chan% * 20) + 1: GOSUB 3800: 'THIS WORKS!

1800 LOOP WHILE INKEY$ = "": REM Works with "DO"

GOTO 5000 ’rem END!!-------------- Subs follow !!----------------!!!

1900 ’ESSENTIAL INITIALIZATIONS

REM set some constants, since they can be accessed much faster

LET c128% = 128: c64% = 64: c32% = 32: c16% = 16: c8% = 8: c4% = 4

LET c3% = 3: c2% = 2: c1% = 1: c0% = 0: km = (2 ^ 30) - 1: kn = 1000000

Inordertoeliminatetheerrorsassociatedwiththesepara-

sitic resistors, the LTC2421/LTC2422 include a full-scale

set input (FS_SET) and a zero-scale set input

(ZS_SET). As shown in Figure 30, the FS_SETpin acts as a

zero current full-scale sense input. Errors due to parasitic

IF cport = 2 THEN OPEN "COM2:300,N,8,1,CD0,CS0,DS0,OP0,RS" FOR

RANDOM AS #1: port = (&H2F8)

IF cport = 1 THEN OPEN "COM1:300,N,8,1,CD0,CS0,DS0,OP0,RS" FOR

RANDOM AS #1: port = (&H3F8)

24212f

26

LTC2421/LTC2422

W U U

APPLICATIO S I FOR ATIO

U

1

resistance R_P1in series with the half-bridge sensor are

removed by the FS_SETinput to the ADC. The absolute full-

scale output of the ADC (data out = FFFFF_HEX) will occur

at V_IN= V_B= FS_SET, see Figure 31. Similarly, the offset

errors due to R_P2are removed by the ground sense input

ZS_SET. The absolute zero output of the ADC (data out =

00000_HEX) occurs at V_IN= V_A= ZS_SET. Parasitic resistors

R_P3to R_P5have negligible errors due to the 1nA (typ)

leakage current at pins FS_SET, ZS_SETand V_IN. The wide

dynamic input range (–300mV to 5.3V) and low noise

(1.2ppm RMS) enable the LTC2421 or the LTC2422 to

directly digitize the output of the bridge sensor.

V

CC

R

I

0

P1

DC

LTC2421

SET

2

3

V

FS

V

B

R

P3

P4

P5

9

8

7

SCK

DC

3-WIRE

I

EXCITATION

SDO

CS

IN

SPI INTERFACE

R

DC

5

6

V

A

ZS

SET

R

10

P2

GND

F

O

24212 F03

Figure 30. Half-Bridge Digitizer with

Zero-Scale and Full-Scale Sense

The LTC2422 is ideal for applications requiring continu-

ous monitoring of two input sensors. As shown in

Figure 32, the LTC2422 can monitor both a thermocouple

temperature probe and a cold junction temperature sen-

sor. Absolute temperature measurements can be

performed with a variety of thermocouples using digital

cold junction compensation.

12.5%

EXTENDED

RANGE

FFFFF

H

+

–

R

P1

V

FULL-SCALE ERROR

+

–

I

SENSOR

SENSOR OUTPUT

EXCITATION

00000

H

12.5%

UNDER

RANGE

+

ZS

FS

SET

R

V

SET

P2

OFFSET ERROR

–

V

24212 F31

IN

24212 F29

Figure 29. Errors Due to Excitation Currents

Figure 31. Transfer Curve with Zero-Scale and Full-Scale Set

2.7V TO 5.5V

LTC2422

1

2

3

4

5

10

V

F

O

CC

9

8

7

6

12k

FS

SCK

SDO

CS

SET

PROCESSOR

COLD JUNCTION

CH1

CH0

ZS

THERMISTOR

24212 F32

100Ω

GND

SET

+

–

ISOLATION

BARRIER

THERMOCOUPLE

Figure 32. Isolated Temperature Measurement

24212f

27

LTC2421/LTC2422

W U U

U

APPLICATIO S I FOR ATIO

TheselectionbetweenCH0andCH1isautomatic. Initially,

after power-up, a conversion is performed on CH0. For

each subsequent conversion, the input channel selection

is alternated. Embedded within the serial data output is a

status bit indicating which channel corresponds to the

conversion result. If the conversion was performed on

CH0, this bit (Bit 22) is LOW and is HIGH if the conversion

was performed on CH1 (see Figure 33).

conversionresultsmaybedigitallysubtractedyieldingthe

differential result.

The LTC2422’s single ended rejection of line frequencies

(±2%) and harmonics is better than 110dB. Since the

device performs two independent single ended conver-

sions each with >110dB rejection, the overall common

mode and differential rejection is much better than the

80dB rejection typically found in other differential input

delta-sigma converters.

There are no extra control or status pins required to per-

form the alternating 2-channel measurements. The

LTC2422onlyrequirestwodigitalsignals(SCKandSDO).

This simplification is ideal for isolated temperature mea-

surements or systems where minimal control signals are

available.

In addition to excellent rejection of line frequency noise,

the LTC2422 also exhibits excellent single ended noise

rejection over a wide range of frequencies due to its 4^th

order sinc filter. Each single ended conversion indepen-

dentlyrejectshighfrequencynoise(>60Hz). Caremustbe

taken to insure noise at frequencies below 15Hz and at

multiples of the ADC sample rate (15,360Hz) are not

present. For this application, it is recommended the

LTC2422 is placed in close proximity to the bridge sensor

in order to reduce the noise injected into the ADC input. By

performingthreesuccessiveconversions(CH0-CH1-CH0),

the drift and low frequency noise can be measured and

compensated for digitally.

Pseudo Differential Applications

Generally, designers choose fully differential topologies

for several reasons. First, the interface to a 4- or 6-wire

bridge is simple (it is a differential output). Second, they

requiregoodrejectionoflinefrequencynoise.Third,they

typically look at a small differential signal sitting on a

large common mode voltage; they need accurate

measurements of the differential signal independent of

the common mode input voltage. Many applications cur-

rently using fully differential analog-to-digital converters

for any of the above reasons may migrate to a pseudo

differential conversion using the LTC2422.

I

EXCITATION

5V

1

I

= 0

DC

V

CC

2

FS

SET

LTC2422

9

SCK

SDO

CS

350Ω

Direct Connection to a Full Bridge

3

4

8

3-WIRE

SPI INTERFACE

CH1

CH0

The LTC2422 interfaces directly to a 4- or 6-wire bridge,

as shown in Figure 34. The LTC2422 includes a FS_SETand

a ZS_SETfor sensing the excitation voltage directly across

the bridge. This eliminates errors due to excitation cur-

rents flowing through parasitic resistors. The LTC2422

also includes two single ended input channels which can

tie directly to the differential output of the bridge. The two

7

350Ω

10

I

= 0

DC

F

O

5

ZS

SET

GND

6

24212 F32

Figure 34. Pseudo Differential Strain Guage Application

SCK

SDO

• • •

CH1 DATA OUT

CH0 DATA OUT

24212 F33

EOC

CH1

CH0

Figure 33. Embedded Selected Channel Indicator

24212f

28

LTC2421/LTC2422

W U U

APPLICATIO S I FOR ATIO

U

Theabsoluteaccuracy(lessthan10ppmtotalerror)ofthe

LTC2422 enables extremely accurate measurement of

small signals sitting on large voltages. Each of the two

pseudo differential measurements performed by the

LTC2422 is absolutely accurate independent of the com-

mon mode voltage output from the bridge. The pseudo

differential result obtained from digitally subtracting the

two single ended conversion results is accurate to within

the noise level of the device (3µV_RMS) times the square

rootof2, independentofthecommonmodeinputvoltage.

resistance changes as a function of temperature (100Ω to

400Ωfor0°Cto800°C). Thesameexcitationcurrentflows

back to the ADC ground and generates another voltage

drop across the return leads. In order to get an accurate

measurementofthetemperature,thesevoltagedropsmust

be measured and removed from the conversion result.

Assumingtheresistanceisapproximatelythesameforthe

forward and return paths (R1 = R2), the auxiliary channel

on the LTC2422 can measure this drop. These errors are

then removed with simple digital correction.

Typically, a bridge sensor outputs 2mV/V full scale. With

a 5V excitation, this translates to a full-scale output of

10mV. Divided by the RMS noise of 8.4µV(= 6µV • 1.414),

this circuit yields 1190 counts with no averaging or ampli-

fication. If more counts are required, several conversions

may be averaged (the number of effective counts is in-

creased by a factor of square root of 2 for each doubling

of averages).

TheresultofthefirstconversiononCH0correspondstoan

input voltage of V_RTD+ R1 • I_EXCITATION.The result of the

second conversion (CH1) is –R1 • I_EXCITATION.Note, the

LTC2422’s input range is not limited to the supply rails, it

has underrange capabilities. The device’s input range is

–300mV to V_REF+ 300mV. Adding the two conversion

results together, the voltage drop across the RTD’s leads

are cancelled and the final result is V_RTD

.

An RTD Temperature Digitizer

An Isolated, 20-Bit Data Acquisition System

RTDs used in remote temperature measurements often

have long lead lengths between the ADC and RTD sensor.

These long lead lengths lead to voltage drops due to exci-

tation current in the interconnect to the RTD. This voltage

drop can be measured and digitally removed using the

LTC2422 (see Figure 35).

TheLTC1535isusefulforsignalisolation.Figure36shows

afullyisolated,20-bitdifferentialinputA/Dconverterimple-

mented with the LTC1535 and LTC2422. Power on the

isolated side is regulated by an LT1761-5.0 low noise, low

dropout micropower regulator. Its output is suitable for

driving bridge circuits and for ratiometric applications.

The excitation current (typically 200µA) flows from the

ADC through a long lead length to the remote temperature

sensor (RTD). This current is applied to the RTD, whose

During power-up, the LTC2422 becomes active at V_CC

2.3V, while the isolated side of the LTC1535 must wait for

V_CC2to reach its undervoltage lockout threshold of 4.2V.

=

5V

1

V

CC

2

4

FS

SET

LTC2422

9

8

7

I

= 200µA

SCK

SDO

CS

EXCITATION

25Ω

5k

3-WIRE

SPI INTERFACE

CH0

CH1

+

–

R1

EXCITATION

1000pF

3

P

t

V

RTD

100Ω

10

I

DC

= 0

F

O

5k

5

ZS

SET

R2

0.1µF

GND

6

24212 F35

Figure 35. RTD Remote Temperature Measurement

24212f

29

LTC2421/LTC2422

W U U

U

APPLICATIO S I FOR ATIO

from the time power is applied to V_CC1until the LT1761’s

output has reached 5V, is approximately 1ms.

Below 4.2V, the LTC1535’s driver outputs Y and Z are in a

high impedance state, allowing the 1kΩ pull-down to de-

fine the logic state at SCK. When the LTC2422 first be-

comes active, it samples SCK; a logic “0” provided by the

1kΩ pull-down invokes the external serial clock mode. In

this mode, the LTC2422 is controlled by a single clock line

from the nonisolated side of the barrier, through the

LTC1535’sdriveroutputY.Theentirepower-upsequence,

DatareturnstothenonisolatedsidethroughtheLTC1535’s

receiver at RO. An internal divider on receiver input B sets

a logic threshold of approximately 3.4V at input A, facili-

tating communications with the LTC2422’s SDO output

without the need for any external components.

1/2 BAT54C

LT1761-5

IN

OUT

+

10µF

16V

SHDN BYP

GND

+

10µF

10V

TANT

T1

1µF

2

10µF

CERAMIC

1/2 BAT54C

LTC1535

+

10µF

10V

TANT

2

LTC2422

ST1 ST2

V

CC2

“SDO”

RO

RE

DE

DI

A

B

Y

Z

F

O

V

CC

SCK FS

SET

“SCK”

V

SDO

CS

CH1

CH0

CC1

G1 G2

1k

LOGIC 5V

GND ZS

SET

+

10µF

10V

TANT

= LOGIC COMMON

1

2

1

2

24212 F36

= FLOATING COMMON

ISOLATION

BARRIER

1

2

T1 = COILTRONICS CTX02-14659

OR SIEMENS B78304-A1477-A3

Figure 36. Complete, Isolated 20-Bit Data Acquisition System

24212f

30

LTC2421/LTC2422

U W

U

PACKAGE I FOR ATIO

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661)

0.889 ± 0.127

(.035 ± .005)

5.23

(.206)

MIN

3.2 – 3.45

(.126 – .136)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

0.497 ± 0.076

(.0196 ± .003)

REF

0.50

3.05 ± 0.38

(.0120 ± .0015)

TYP

(.0197)

10 9

8

7 6

BSC

RECOMMENDED SOLDER PAD LAYOUT

3.00 ± 0.102

(.118 ± .004)

NOTE 4

4.88 ± 0.10

(.192 ± .004)

DETAIL “A”

0.254

(.010)

0° – 6° TYP

GAUGE PLANE

1

2

3

4 5

0.53 ± 0.01

(.021 ± .006)

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.17 – 0.27

(.007 – .011)

0.13 ± 0.05

(.005 ± .002)

0.50

(.0197)

TYP

MSOP (MS) 1001

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

24212f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.

31

LTC2421/LTC2422

U

TYPICAL APPLICATIO

convert either the thermal couple output or the thermistor

cold junction output. After each conversion, the devices

enter their sleep state and wait for the SCK signal before

clocking out data and beginning the next conversion.

Figure 37 shows the block diagram of a demo circuit

(contact LTC for a demonstration) of a multichannel

isolated temperature measurement system. This circuit

decodes an address to select which LTC2422 receives a

24-bit burst of SCK signal. All devices independently

D1

RE

R0

V

CC

FS

SET

LTC1535

A

Y

SDO

LTC2422

SCK

CH1

CH0

ZS

SET

SCK

HC138

D1

RE

R0

V

CC

FS

SET

A

Y

SDO

LTC2422

+

2500V

–

SCK

CH1

CH0

ZS

SET

D1

RE

R0

V

CC

FS

SET

HC138

A

Y

SDO

LTC2422

SCK

CH1

CH0

SD0

ZS

SET

SEE FIGURE 34 FOR

THE COMPLETE CIRCUIT

HC595

ADDRESS

LATCH

24212 F37

D

IN

(ADDRESS

OR COUNTER)

Figure 37. Mulitchannel Isolated Temperature Measurement System

RELATED PARTS

PART NUMBER

LT1019

DESCRIPTION

Precision Bandgap Reference, 2.5V, 5V

COMMENTS

3ppm/°C Drift, 0.05% Max

LTC1050

Precision Chopper Stabilized Op Amp

Precision Bandgap Reference, 5V

8-Channel Multiplexer

No External Components 5µV Offset, 1.6µV Noise

P-P

LT1236A-5

LTC1391

0.05% Max, 5ppm/°C Drift

Low R : 45Ω, Low Charge Injection Serial Interface

ON

LT1461-2.5

LTC1535

Precision Micropower Voltage Reference

Isolated RS485 Transceiver

50µA Supply Current, 3ppm/°C Drift

2500V

Isolation

RMS

LTC2400

24-Bit, No Latency ∆Σ ADC in SO-8

4ppm INL, 10ppm Total Unadjusted Error, 200µA

LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP

LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ∆Σ ADC

0.6ppm Noise, 4ppm INL, Pin Compatible with the LTC2421/LTC2422

4ppm INL, 10ppm Total Unadjusted Error, 200µA

LTC2413

LTC2415

LTC2420

24-Bit, No Latency ∆Σ ADC

Simultaneous 50Hz and 60Hz Rejection, 0.16ppm Noise

15Hz Output Rate at 60Hz Rejection, Pin Conpatible with the LTC2410

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408

0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA

0.29ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

24-Bit, Fully Differential, No Latency ∆Σ ADC

20-Bit, No Latency ∆Σ ADC in SO-8

LTC2424/LTC2428 4-/8-Channel, 20-Bit, No Latency ∆Σ ADC

LTC2430

LTC2431

20-Bit, Fully Differential, No Latency ∆Σ ADC in SSOP-16

24-Bit, Fully Differential, No Latency ∆Σ ADC in MS10

24212f

LT/TP 0202 2K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com

LINEAR TECHNOLOGY CORPORATION 2002


型号：	LTVA
厂家：	Linear
描述：	1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10 1 / 2通道20位微功耗无延迟的ADC ，采用MSOP - 10
文件：	总32页 (文件大小：365K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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