5962-8876403XA [MAXIM]
ADC, Flash Method, 8-Bit, 1 Func, 8 Channel, Parallel, 8 Bits Access, CMOS, CDIP28, CERAMIC, DIP-24;
| 型号： | 5962-8876403XA |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Flash Method, 8-Bit, 1 Func, 8 Channel, Parallel, 8 Bits Access, CMOS, CDIP28, CERAMIC, DIP-24 CD 转换器 |
| 文件： | 总12页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0255; Rev 2; 4/94
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
4/MX728
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ One-Chip Data Acquisition System
The MAX154/MAX158 and MX7824/MX7828 are high-
s p e e d , multi-c ha nne l a na log -to-d ig ita l c onve rte rs
(ADCs). The MAX154 and MX7824 have four analog
input channels, while the MAX158 and MX7828 have
eight channels. Conversion time for all devices is 2.5µs.
The MAX154/MAX158 also feature a 2.5V on-chip refer-
ence, forming a complete high-speed data acquisition
system.
♦ Four or Eight Analog Input Channels
♦ 2.5µs per Channel Conversion Time
♦ Internal 2.5V Reference (MAX154/MAX158 only)
♦ Built-In Track/Hold Function
1
♦
/ LSB Error Specification
2
All four converters include a built-in track/hold, eliminat-
ing the need for an external track/hold with many input
signals. The analog input range is 0V to +5V, although
the ADC operates from a single +5V supply.
♦ Single +5V Supply Operation
♦ No External Clock
♦ New Space-Saving SSOP Package
Microprocessor interfaces are simplified by the ADC’s
ability to appear as a memory location or I/O port without
the need for external logic. The data outputs use latched,
three-state buffer circuitry to allow direct connection to a
microprocessor data bus or system input port.
______________Ord e rin g In fo rm a t io n
ERROR
(LSB)
PART
MX7824LN
MX7824KN
TEMP. RANGE PIN-PACKAGE
The MX7824 a nd MX7828 a re p in c omp a tib le with
Analog Devices’ AD7824 and AD7828. The MAX154
and MAX158, which feature internal references, are also
compatible with these products.
24 Narrow
0°C to +70°C
1
±
/
2
Plastic DIP
24 Narrow
0°C to +70°C
±1
1
Plastic DIP
________________________Ap p lic a t io n s
MX7824LCWG 0°C to +70°C
MX7824KCWG 0°C to +70°C
24 Wide SO
24 Wide SO
24 SSOP
±
/
2
Digital Signal Processing
High-Speed Data Acquisition
Telecommunications
High-Speed Servo Control
Audio Instrumentation
±1
1
MX7824LCAG
MX7824KCAG
0°C to +70°C
0°C to +70°C
±
/
2
24 SSOP
±1
Ordering Information continued on last page.
__________________________________________________________P in Co n fig u ra t io n s
TOP VIEW
AIN6
AIN5
AIN4
AIN3
AIN7
AIN8
V
1
2
28
27
AIN4
AIN3
AIN2
AIN1
V
1
2
24 DD
3
26 DD
NC
23
22
21
20
19
18
17
16
15
14
13
A0
25
4
A0
3
MAX158
MX7828
AIN2
AIN1
A1
5
24
A1
4
23 A2
6
MAX154
MX7824
TP (REF OUT)
DB0
DB7
DB6
DB5
DB4
CS
5
TP (REF OUT)
DB0
DB7
7
22
6
21 DB6
8
DB1
7
DB1
DB2
DB3
RD
DB5
DB4
CS
9
20
19
18
DB2
8
10
11
12
13
14
DB3
RD
9
RDY
10
11
12
17 RDY
INT
V
REF
+
INT
V
+
16
15
REF
GND
V
REF
-
GND
V
-
REF
DIP/SO/SSOP
DIP/SO/SSOP
(
) ARE FOR MAX154/MAX158 ONLY.
________________________________________________________________ Maxim Integrated Products
1
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD to GND........................................0V, +10V
Operating Temperature Ranges
Voltage at Any Other Pins ......................GND - 0.3V, V + 0.3V
MX7824, MX7828
DD
Output Current (REF OUT)..................................................30mA
Power Dissipation (any package) to +75°C ....................450mW
Derate above +25°C by ..............................................6mW/°C
KN/LN/KCW_/LCW_............................................0°C to +70°C
BQ/CQ .............................................................-40°C to +85°C
TQ/UQ............................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +5V, V + = +5V, V - = GND, Mode 0, T = T
to T , unless otherwise noted.)
MAX
DD
REF
REF
A
MIN
4/MX728
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
8
Bits
MAX15_A, MX782_L/C/U
MAX15_B, MX782_K/B/T
±1/2
±1
Total Unadjusted Error (Note 1)
LSB
No Missing Codes Resolution
Channel to Channel Mismatch
REFERENCE INPUT
8
Bits
±1/4
LSB
Reference Resistance
1
4
kΩ
V
V
+ Input Voltage Range
V
-
V
DD
REF
REF
V - Input Voltage Range
REF
GND
V +
REF
V
REFERENCE OUTPUT—MAX154/MAX158 Only (Note 2)
Output Voltage
REF OUT
T
= +25°C
2.47
2.50
-6
2.53
-10
±3
V
A
Load Regulation
I
L
= 0mA to 10mA, T = +25°C
mV
mV
A
Power-Supply Sensitivity
V
±5%, T = +25°C
±1
40
DD
A
MAX15_C
MAX15_E
MAX15_M
70
Temperature Drift (Note 3)
40
70
ppm/°C
60
100
Output Noise
e
200
µV/rms
µF
N
Capacitive Load
0.01
ANALOG INPUT
Analog Input Voltage Range
Analog Input Capacitance
Analog Input Current
A
V
REF
-
V
+
V
pF
INR
REF
C
45
AIN
I
Any channel, AIN = 0V to 5V
±3
µA
AIN
Slew Rate, Tracking
SR
0.7
0.157
V/µs
–—– –—–
LOGIC INPUTS (RD, CS, A0, A1, A2)
Input High Voltage
Input Low Voltage
V
2.4
V
V
INH
V
INL
0.8
1
Input High Current
Input Low Current
I
µA
µA
pF
INH
I
-1
8
INL
Input Capacitance (Note 4)
C
5
IN
2
_______________________________________________________________________________________
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
4/MX728
ELECTRICAL CHARACTERISTICS
(V = +5V, V + = +5V, V - = GND, Mode 0, T = T
to T , unless otherwise noted.)
MAX
DD
REF
REF
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC OUTPUTS
—–—–
Output High Voltage
V
OH
DB0–DB7, INT; I
= -360µA
OUT
4.0
V
V
I
= 1.6mA
= 2.6mA
0.4
0.4
±3
8
OUT
—–—–
Output Low Voltage
V
OL
DB0–DB7, INT; RDY
I
OUT
Three-State Output Current
DB0–DB7, RDY; V
= 0V to V
µA
pF
OUT
DD
Output Capacitance (Note 4)
POWER SUPPLY
C
5
OUT
Supply Voltage
V
5V ±5% for specified performance
4.75
5.25
15
V
DD
–—– –—–
Supply Current
I
DD
CS = RD = 2.4V
mA
mW
LSB
Power Dissipation
25
75
Power-Supply Sensitivity
PSS
V
DD
= ±5%
±1/16
±1/4
Note 1: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 2: Specified with no external load unless otherwise noted.
Note 3: Temperature drift is defined as change in output voltage from +25°C to T
Note 4: Guaranteed by design.
or T
divided by (25 - T
) or (T - 25).
MAX
MIN
MAX
MIN
TIMING CHARACTERISTICS (Note 5)
(V = +5V, V + = +5V, V - = GND, Mode 0, T = T
to T , unless otherwise noted.)
MAX
DD
REF
REF
A
MIN
MAX15_ _C/E
MX782_K/L/B/C MX782_T/U
MAX15_ _M
T
A
= +25°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN TYP MAX
MIN
MAX
MIN
MAX
–—– –—–
CS to RD Setup Time
t
0
0
0
0
0
0
ns
ns
CSS
–—– –—–
CS to RD Hold Time
t
CSH
Multiplexer Address
Setup Time
t
0
0
0
ns
ns
AS
Multiplexer Address
Hold Time
t
30
35
40
AH
–—–
CS to RDY Delay
t
C
= 50pF, R = 5kΩ
30
40
2.0
85
60
2.4
110
60
2.8
120
ns
µs
ns
RDY
L
L
Conversion Time (Mode 0)
t
1.6
CRD
–—–
Data Access Time After RD
t
(Note 6)
(Note 6)
ACC1
Data Access Time
—–—–
t
20
40
50
60
70
ns
ACC2
After INT, Mode 0
–—– —–—–
RD to INT Delay (Mode 1)
t
C
= 50pF
L
75
60
100
70
100
70
ns
ns
INTH
Data Hold Time
t
(Note 7)
DH
Delay Time
t
500
60
500
80
600
80
ns
ns
P
Between Conversions
–—–
RD Pulse Width (Mode 1)
t
600
500
400
RD
Note 5: All input control signals are specified with t = t = 20ns (10% to 90% of +5V) and timed from a 1.6V voltage level.
R
F
Note 6: Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7: Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
_______________________________________________________________________________________
3
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
REFERENCE TEMPERATURE
DRIFT (MAX154/MAX158 ONLY)
2.520
OUTPUT CURRENT
vs. TEMPERATURE
ACCURACY vs. DELAY BETWEEN
CONVERSIONS (t )
p
20
16
2.0
1.5
V
DD
= 5V
V
= 5V
= 5V
DD
V
REF
2.510
2.500
I
V
= 2.4V
SOURCE OUT
12
8
1.0
I
V
= 0.4V
SINK OUT
2.490
2.480
0.5
0
4
4/MX728
0
-100
-50
0
50
100
150
300 400 500
600 700
t (ns)
p
800 900
-50
0
50
100
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
ACCURACY vs. V
REF
(V = V + - V -)
REF REF REF
POWER-SUPPLY CURRENT vs. TEMPERATURE
(NOT INCLUDING REFERENCE LADDER)
2.0
1.5
8
V
DD
= 5V
7
V
DD
= 5.25V
6
5
1.0
V
= 5V
DD
4
0.5
0
V
DD
= 4.75V
3
2
0
1
2
3
4
5
-100
-50
0
50
100
150
V
REF
(V)
AMBIENT TEMPERATURE (°C)
+5V
+5V
3k
3k
DBN
DBN
DBN
DBN
3k
100pF
DGND
100pF
3k
10pF
10pF
DGND
DGND
DGND
a. High-Z to V
b. High-Z to V
OL
OH
a. V to High-Z
OH
b. V to High-Z
OL
Figure 1. Load Circuits for Data-Access Time Test
Figure 2. Load Circuits for Data-Hold Time Test
4
_______________________________________________________________________________________
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
4/MX728
_____________________________________________________________P in De s c rip t io n s
PIN
PIN
NAME
FUNCTION
NAME
FUNCTION
MAX154
MX7824
MAX158
MX7828
1
2
3
4
AIN4
AIN3
AIN2
AIN1
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
1
2
3
4
5
6
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
Analog Input Channel 6
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
REF OUT Reference Output (2.5V) for MAX154.
5
TP
Test point for MX7824. Do not connect.
6
7
8
9
DBO
DB1
DB2
DB3
Three-State Data Output, bit 0 (LSB)
Three-State Data Output, bit 1
Three-State Data Output, bit 2
Three-State Data Output, bit 3
REF OUT
TP
Reference Output (2.5V) for MAX158.
Test point for MX7828. Do not connect.
7
8
9
DB0
DB1
DB2
DB3
Three-State Data Output, bit 0 (LSB)
Three-State Data Output, bit 1
Three-State Data Output, bit 2
Three-State Data Output, bit 3
–—–
10
11
Read Input. RD controls conversions
and data access. See Digital Interface
section.
–—–
RD
10
–—–
Read Input. RD controls conversions
–—–
RD
Interrupt Output. INT going low indi-
cates the completion of a conversion.
See Digital Interface section.
12
and data access. See Digital Interface
section.
11
12
13
INT
Interrupt Output. INT going low indi-
cates the completion of a conversion.
See Digital Interface section.
GND
Ground
13
14
15
INT
Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to V +.
REF
V
REF
-
GND
Ground
Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to V +.
REF
Upper Limit of Reference Span. Sets
the full-scale input voltage.
V
-
REF
14
V +
REF
Range: V - to V
.
REF
DD
Upper Limit of Reference Span. Sets
the full-scale input voltage.
Ready Output. Open-drain output with
16
V
+
REF
no active pull-up device. Goes low
.
Range: V - to V
REF
DD
15
16
RDY
–—–
when CS goes low and high imped-
Ready Output. Open-drain output with
ance at the end of a conversion.
no active pull-up device. Goes low
17
18
RDY
–—–
–—–
when CS goes low and high imped-
Chip-Select Input. CS must be low for
–—–
CS
ance at the end of a conversion.
the device to be selected.
–—–
Chip-Select Input. CS must be low for
17
18
19
20
21
22
23
24
DB4
DB5
DB6
DB7
A1
Three-State Data Output, bit 4
Three-State Data Output, bit 5
Three-State Data Output, bit 6
Three-State Data Output, bit 7 (MSB)
Channel Address 1 Input
Channel Address 0 Input
No Connect
–—–
CS
the device to be selected.
19
20
21
22
23
24
25
26
27
28
DB4
DB5
DB6
DB7
A2
Three-State Data Output, bit 4
Three-State Data Output, bit 5
Three-State Data Output, bit 6
Three-State Data Output, bit 7 (MSB)
Channel Address 2 Input
A0
NC
A1
Channel Address 1 Input
V
DD
Power-Supply Voltage, +5V
A0
Channel Address 0 Input
V
DD
Power-Supply Voltage, +5V
Analog Input Channel 8
AIN8
AIN7
Analog Input Channel 7
_______________________________________________________________________________________
5
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
_______________De t a ile d De s c rip t io n
___________________Dig it a l In t e rfa c e
The MAX154/MAX158 and MX7824/MX7828 use only
Chip Select (CS) and Read (RD) as control inputs. A
READ operation, taking CS and RD low, latches the mul-
tiplexer address inputs and starts a conversion (Table 1).
Co n ve rt e r Op e ra t io n
The MAX154/MAX158 and MX7824/MX7828 use what is
commonly called a “half-flash” conversion technique
(Figure 3). Two 4-bit flash ADC sections are used to
a c hie ve a n 8-b it re s ult. Us ing 15 c omp a ra tors , the
upper 4-bit MS (most significant) flash ADC compares
the unknown input voltage to the reference ladder and
provides the upper four data bits.
Table 1. Truth Table for Input Channel
Selection
MAX154/MX7824
MAX158/MX7828
SELECTED
CHANNEL
An internal DAC uses the MS bits to generate an analog
signal from the first flash conversion. A residue voltage
representing the difference between the unknown input
and the DAC voltage is then compared to the reference
ladder by 15 LS (least significant) flash comparators to
obtain the lower four output bits.
A1
A0
A2
A1
A0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
1
AIN1
AIN2
AIN3
AIN4
4/MX728
1
1
1
1
0
0
1
1
0
1
0
1
AIN5
AIN6
AIN7
AIN8
Op e ra t in g S e q u e n c e
The operating sequence is shown in Figure 4. A con-
version is initiated by a falling edge of RD and CS. The
comparator inputs track the analog input voltage for
approximately 1µs. After this first cycle, the MS flash
result is latched into the output buffers and the LS con-
ve rsion be gins. INT goe s low a pproxima te ly 600ns
later, indicating the end of the conversion, and that the
lower four bits are latched into the output buffers. The
d a ta c a n the n b e a c c e s s e d us ing the CS a nd RD
inputs.
There are two interface modes, which are determined
by the length of the RD input. Mode 0, implemented by
keeping RD low until the conversion ends, is designed
for microprocessors that can be forced into a WAIT
state. In this mode, a conversion is started with a READ
operation (taking CS and RD low), and data is read
when the conversion ends. Mode 1, on the other hand,
DB7
V
+
REF
4-BIT
FLASH
ADC
(4MSB)
DB6
V
REF
-
DB5
DB4
AIN1
AIN4
THREE-
STATE
DRIVERS
4-BIT
DAC
MUX*
V
+
REF
DB3
DB2
DB1
AIN8
4-BIT
FLASH
ADC
16
(4LSB)
DB0
ADDRESS
LATCH
DECODE
REF OUT**
2.5V
REF
TIMING AND CONTROL
CIRCUITRY
INT
A0 A1 A2
RDY
CS
RD
*MAX154/MX7824 – 4-Channel Mux
MAX158/MX7828 – 8-Channel Mux
** REF OUT on MAX154/MAX158 only
Figure 3. Functional Diagram
6
_______________________________________________________________________________________
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
4/MX728
There are two status outputs: Interrupt (INT) and Ready
(RDY). RDY, an open-drain output (no internal pull-up
device), is connected to the processor’s READY/WAIT
INT GOING LOW
INDICATES THAT
RD
CONVERSION IS
COMPLETE AND
THAT DATA CAN
BE READ
input. RDY goes low on the falling edge of CS and goes
high impedance at the end of the conversion, when the
conversion result appears on the data outputs. If the RDY
output is not required, its external pull-up resistor can be
omitted. INT goes low when the conversion is complete
and returns high on the rising edge of CS or RD.
600ns
500ns
1000ns
SETUP TIME REQUIRED
BY THE INTERNAL
COMPARATORS PRIOR TO
STARTING CONVERSION
V
IN
IS SAMPLED
AND THE FOUR MSBs
ARE LATCHED
V
IS TRACKED
IN
In t e rfa c e Mo d e 1
Mode 1 is designed for applications where the micro-
processor is not forced into a WAIT state. Taking CS
and RD low latches the multiplexer address and starts
a conversion (Figure 6). Data from the previous conver-
sion is immediately read from the outputs (DB0–DB7).
BY INTERNAL
COMPARATORS
Figure 4. Operating Sequence
does not require microprocessor WAIT states. A READ
operation simultaneously initiates a conversion and
reads the previous conversion result.
INT goes high at the rising edge of CS or RD and goes
low at the end of the conversion. A second READ oper-
ation is required to read the result of this conversion.
The second READ latches a new multiplexer address
and starts another conversion. A delay of 2.5µs must
be allowed between READ operations. RDY goes low
on the falling edge of CS and goes high impedance at
the rising edge of CS. If RDY is not needed, its external
pull-up resistor can be omitted.
In t e rfa c e Mo d e 0
Figure 5 shows the timing diagram for Mode 0 opera-
tion. This is used with microprocessors that have WAIT
state capability, whereby a READ instruction is extend-
ed to accommodate slow-memory devices. Taking CS
and RD low latches the analog multiplexer address and
starts a conversion. Data outputs DB0–DB7 remain in
the high-impedance condition until the conversion is
complete.
CS
t
t
t
CSH
CSS
CSS
RD
t
P
t
AS
t
AS
ANALOG
CHANNEL
ADDRESS
ADDR
VALID
ADDR
VALID
t
AH
RDY
INT
t
RDY
t
INTH
t
CRD
t
t
DH
ACC2
HIGH IMPEDANCE
DATA
VALID
DATA
Figure 5. Mode 0 Timing Diagram
_______________________________________________________________________________________
7
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
CS
t
t
RD
t
t
CSS
t
t
RD
CSH
CSH
CSS
RD
t
P
t
AS
t
AS
ANALOG
CHANNEL
ADDRESS
ADDR
VALID
ADDR
VALID
t
AH
t
AH
RDY
t
t
RDY
RDY
4/MX728
t
CRD
t
t
INTH
INTH
INT
t
t
DH
t
DH
t
ACCI
ACCI
OLD
DATA
NEW
DATA
DATA
Figure 6. Mode 1 Timing Diagram
_____________An a lo g Co n s id e ra t io n s
OUTPUT
CODE
FULL-SCALE
TRANSITION
Re fe re n c e a n d In p u t
The V + and V - inputs of the converter define the
REF
REF
zero and the full-scale of the ADC. In other words, the
11111111
11111110
11111101
voltage at V - is equal to the input voltage that pro-
REF
duces an output code of all zeros, and the voltage at
V + is equal to input voltage that produces an output
REF
code of all ones (Figure 7).
Figure 8 shows some possible reference configura-
tions . For the MAX154/MAX158, a 0.01µF b yp a s s
capacitor to GND should be used to reduce the high-
frequency output impedance of the internal reference.
Larger capacitors should not be used, as this degrades
the stability of the reference buffer. The 2.5V reference
output is with respect to the GND pin.
1LSB = F8 = V + - V
-
REF
REF
256
256
00000011
00000010
V
+
REF
00000001
00000000
Byp a s s in g
A 47µF electrolytic and 0.1µF ceramic capacitor should
1
2
3
FS
FS–1LSB
be used to bypass the V
pin to GND. These capaci-
DD
V -
REF
AIN INPUT VOLTAGE
(IN TERMS OF LSBs)
tors must have minimum lead length, since excess lead
length may contribute to conversion errors and instability.
If the reference inputs are driven by long lines, they
should be bypassed to GND with 0.1µF capacitors at
the reference input pins.
Figure 7. Transfer Function
8
_______________________________________________________________________________________
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
4/MX728
In p u t Cu rre n t
The converters’ analog inputs behave somewhat differ-
ently from conventional ADCs. The sampled data com-
parators take varying amounts of current from the input,
depending on the cycle they are in. The equivalent cir-
cuit of the converter is shown in Figure 9a. When the
conversion starts, AIN(n) is connected to the MS and
LS comparators. Thus, AIN(n) is connected to thirty-one
1pF capacitors.
AIN (+)
x
V
IN
AIN (-)
x
GND
+5V
V
DD
MAX154
MAX158
REF OUT
0.1µF
47µF
V
REF
+
0.01µF
V
REF
-
To acquire the input signal in approximately 1µs, the
inp ut c a p a c itors mus t c ha rg e to the inp ut volta g e
through the on-resistance of the multiplexer (about
600Ω) and the comparator’s analog switches (2kΩ to
5kΩ per comparator). In addition, about 12pF of stray
capacitance must be charged. The input can be mod-
eled as an equivalent RC network shown in Figure 9b.
Figure 8a. Internal Reference (MAX154/MAX158 only)
AIN (+)
x
V
IN
GND
AIN (-)
x
As R (source impedance) increases, the capacitors
S
take longer to charge.
+5V
0.1µF
V
MX7824
MX7828
DD
Since the length of the input acquisition time is internal-
ly set, large source resistances (greater than 100Ω) will
cause settling errors. The output impedance of an op-
amp is its open-loop output impedance divided by the
loop gain at the frequency of interest. It is important
that the amplifier driving the converter input have suffi-
cient loop gain at approximately 1MHz to maintain low
output impedance.
2.5V
V
REF
+
47µF
MX584
V
REF
-
Figure 8b. External Reference +2.5V Full-Scale
AIN (+)
x
V
IN
In p u t Filt e rin g
The transients in the analog input caused by the sam-
pled data comparators do not degrade the converter’s
performance, since the ADC does not “look” at the
input when these transients occur. The comparator’s
outputs track the input during the first 1µs of the con-
version, and are then latched. Therefore, at least 1µs
will be provided to charge the ADC’s input capaci-
tance. It is not necessary to filter these transients with
an external capacitor on the AIN terminals.
GND
AIN (-)
x
MAX154
MAX158
MX7824
MX7828
+5V
V
DD
V
+
0.1µF
47µF
REF
V
-
REF
Figure 8c. Power Supply as Reference
S in u s o id a l In p u t s
The MAX154/MAX158 and MX7824/MX7828 can mea-
sure input signals with slew rates as high as 157mV/µs
to the rated specifications. This means that the analog
input frequency can be as high as 10kHz without the
aid of an external track/hold. The maximum sampling
* Current path must
still exist from
AIN (+)
x
V
IN
V
IN(-)
to Ground
GND
+5V
0.1µF
V
DD
MAX154
MAX158
MX7824
MX7828
rate is limited by the conversion time (typical t
2µs) plus the time required between conversions (t
500ns). It is calculated as:
=
=
CRD
V
REF
+
47µF
p
2.5V
*
V
REF
-
AIN (-)
x
f
1
1
400kHz
=
MAX =
=
t
+ t
(2.0 + 0.5) µs
CRD
p
Figure 8d. Inputs Not Referenced to GND
_______________________________________________________________________________________
9
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
f
permits a maximum sampling rate of 50kHz per
MAX
channel when using the MAX158/MX7828 and 100kHz
per channel when using the MAX154/MX7824. These
rates are well above the Nyquist requirement of 20kHz
sampling rate for a 10kHz input bandwidth.
3.57k
11.5Ω
10.0k
V
IN
CS
AIN1
Bip o la r In p u t Op e ra t io n
The circuit in Figure 10a can be used for bipolar input
operation. The input voltage is scaled by an amplifier so
that only positive voltages appear at the ADC’s inputs.
An external reference should be used for the MX7824/
MX7828, but is not needed with the MAX154/MAX158.
The analog input range is ±4V and the output code is
complementary offset binary. The ideal input/output
characteristic is shown in Figure 10b.
RDY
MAX154
MAX158
0.01µF
16.2k
RD
V
+
INT
REF
0.01µF
REF OUT
+5V
V
DD
DB0–DB7
V
-
REF
4/MX728
47µF
0.1µF
GND
C
S
2pF
ONLY CHANNEL 1 SHOWN
R
S
R
MUX
R
ON
AIN1
1pF
V
IN
C
12pF
1pF
Figure 10a. Bipolar ±4V Input Operation
S
•
•
•
TO LS
LADDER
15 LSB COMPARATORS
R
ON
1pF
1pF
•
•
•
TO MS
FS = 8V
1LSB = FS / 256
LADDER
11111111
11111110
11111101
16 MSB COMPARATORS
Figure 9a. Equivalent Input Circuit
10000010
10000001
10000000
+FS
2
-FS
+ 1LSB
01111111
2
01111110
R
ON
B MUX
R
S
350Ω
600Ω
00000010
00000001
00000000
AIN1
C
C
S2
2pF
S1
2pF
32pF
V
IN
0V
AIN INPUT VOLTAGE (LSBs)
Figure 9b. RC Network Model
Figure 10b. Transfer Function for ±4V Input Operation
10 ______________________________________________________________________________________
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
4/MX728
+5V
26
A15
A0
ADDRESS BUS
ADDRESS
V
DD
BANDPASS
FILTER 1
6
5
18
12
AIN1
CS
RD
A0
A1
A2*
BANDPASS
FILTER 2
AIN2
EN
DECODE
MREQ
5V
ZBO
MAX158
MX7828
MAX154
MAX158
MX7824
MX7828
CS
5k
SPEECH
INPUT
AMP
DATA
DB0–DB7
WAIT
RD
RDY
RD
BANDPASS
FILTER 7
28
AIN7
AIN8
23
24
A2
A1
DATA BUS
DB0–DB7
D0–D7
BANDPASS
FILTER 8
27
16
25
+5V
V
REF+
A0
V
GND
14
REF-
15
*A2 ON MAX158/MX7828 ONLY.
Figure 12. Speech Analysis Using Real-Time Filtering
Figure 11. Simple Mode 0 Interface
SAMPLE
PULSE
+5V
24
+15V
18
16
CS
10
V
DD
V
DD
RD
4
2
4
3
V
REF
AIN1
15
WR
11
AIN2
INT
V
A
B
C
D
OUT
2
1
1
V
AIN3
AIN4
V
OUT
MAX154
MX7824
MX7226
20
19
6
V
OUT
DB0–DB7
DB0–DB7
14
13
12
V
REF+
OUT
21
22
16
17
V
REF-
A1
A0
A1
A0
DGND
AGND
5
GND
V
SS
3
A0
A1
Figure 13. 4-Channel Fast Sample and Infinite Hold
______________________________________________________________________________________ 11
CMOS , Hig h -S p e e d , 8 -Bit ADCs
w it h Mu lt ip le x e r
_Ord e rin g In fo rm a t io n (c o n t in u e d )
___________________Ch ip To p o g ra p h y
AIN4 AIN6 AIN8
(N.C.) (AIN2) (AIN4)
AIN3 AIN5 AIN7
(N.C.) (AIN1) (AIN3)
ERROR
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
VDD A0
1
MX7824LEAG
MX7824KEAG
MX7824CQ
MX7824BQ
MX7824UQ
MX7824TQ
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
24 SSOP
±
/
2
24 SSOP
±1
1
A1
24 CERDIP
24 CERDIP
±
/
2
A2 (N.C.)
AIN2 (N.C.)
AIN1 (N.C.)
±1
1
0.127"
(3.228mm)
-55°C to +125°C 24 CERDIP
-55°C to +125°C 24 CERDIP
±
/
TP (REF OUT)
2
±1
1
DB7
DB6
DB0
DB1
MX7828LN
MX7828KN
MX7828LCWI
MX7828KCWI
MX7828LCAI
MX7828KCAI
MX7828LP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
28 Plastic DIP
28 Plastic DIP
28 Wide SO
28 Wide SO
28 SSOP
±
/
2
±1
1
±
/
2
DB5
±1
1
4/MX728
DB2
DB3
±
/
DB4
CS
2
28 SSOP
±1
1
28 PLCC
±
/
2
MX7828KP
28 PLCC
±1
1
A0
GND
INT
V
+
ADY
REF
V
-
REF
MX7828LEAI
MX7828KEAI
MX7828CQ
MX7828BQ
MX7828UQ
MX7828TQ
28 SSOP
±
/
2
0.124"
28 SSOP
±1
1
(3.150mm)
28 CERDIP
28 CERDIP
±
/
2
( ) ARE FOR MAX154/MX7824
±1
1
-55°C to +125°C 28 CERDIP
-55°C to +125°C 28 CERDIP
±
/
2
±1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1995 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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