DS1012M-D50 [MAXIM]

Delay Line, 2-Func, 1-Tap, CMOS, PDIP8;
DS1012M-D50
型号: DS1012M-D50
厂家: MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述:

Delay Line, 2-Func, 1-Tap, CMOS, PDIP8

光电二极管 延迟线
文件: 总7页 (文件大小:50K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
DS1012  
DS1012  
2-in-1 Sub-Miniature Silicon  
Delay Line with Logic  
FEATURES  
PIN ASSIGNMENT  
All-silicon time delay  
IN1  
1
2
8
7
V
CC  
53 µW max. CMOS quiescent mode  
OUT3  
OUT1  
IN2  
3
4
6
5
OUT2  
Surface mount 8-pin mini-SOIC and standard 8-pin  
DIP  
GND  
OUT4  
DS1012M 8-PIN DIP (300 MIL)  
See Mech. Drawings  
Section  
2 independent buffered delays per input  
Option of complemented output(s)  
IN1  
1
2
3
4
8
7
6
5
V
CC  
Optionof timed AND, NAND, OR, NOR, XOR, XNOR,  
HALF-XOR and HALF-XNOR logic outputs  
OUT3  
OUT1  
IN2  
OUT2  
Delay tolerance:  
±1.5 ns (delays: 3-10 ns),  
±2.0 ns (delays: 11-40 ns)  
GND  
OUT4  
DS1012Z 8-PIN SOIC (150 MIL)  
See Mech. Drawings  
Section  
Vapor phase, IR and wave solderability  
Economical  
PIN DESCRIPTION  
TTL/CMOS-compatible  
IN1, IN2  
– Inputs  
Quick turn prototypes  
OUT1, OUT2 – Outputs (delays)  
OUT3, OUT4 – Outputs (delays, logic)  
Custom delays and logic options available  
GND  
– Ground  
– +5 Volts  
V
CC  
DESCRIPTION  
In its most simple configuration, the DS1012 2-in-1  
Sub-Miniature Silicon Delay Line Chip provides two in-  
puts, each of which in turn provides independent delays  
to a pair of outputs. The DS1012-1 and DS1012-3 are  
examples of catalog parts having this basic configura-  
tion. Any of the four outputs can be inverted at the time  
of manufacture.  
catalog parts configured with logic functions on OUT3  
and OUT4. Note that DS1012-2 also utilizes an output  
inversion on OUT2.  
Inanyconfiguration, delaysD1(t )andD2(t )canbe  
D1  
D2  
specified within the range of ~3 ns to 10 ns. Delays D3  
(t ) and D4 (t ) can be specified to have values be-  
D3  
D4  
tween ~3 ns and 40 ns. The worst case leading edge  
delay accuracy at nominal voltage and room tempera-  
tureis ±2ns. TheDS1012isofferedintwopackages:an  
8-pin DIP and an 8-pin 150 mil wide mini-SOIC.  
For applications requiring two-input timed logic func-  
tions, at the time of manufacture the simple delay on  
OUT4 can be replaced by one of the following: OR,  
NOR, XOR, or XNOR. Similarly, a timed AND, NAND,  
HALF-XOR (D3 AND D4), or NOT HALF-XOR (D3 OR  
D4) can be substituted for the simple delay on OUT3.  
DS1012-2, DS1012-4, and DS1012-5 are examples of  
Dallas Semiconductor offers the DS1012 in a wide vari-  
etyofcustomdelayandlogicconfigurations. Forspecial  
requests and quick turn delivery, call (972) 371–4348.  
021798 1/7  
DS1012  
LOGIC DIAGRAM Figure 1  
DELAY  
D1  
IN1  
OUT1  
DELAY  
D3  
FUNCTION  
f3  
OUT3  
OUT4  
OUT2  
DELAY  
D4  
FUNCTION  
f4  
DELAY  
D2  
IN2  
Function f3 can be one of the following:  
D3  
D3  
D3 AND D4  
D3 HALF-XOR D4  
D3 NAND D4  
D3 HALF-XNOR D4  
Function f4 can be one of the following:  
D4  
D4  
D3 OR D4  
D3 XOR D4  
D3 NOR D4  
D3 XNOR D4  
NOTE: Any output(s) can be inverted at time of manufacture.  
If D1 > 10 ns, D1 = D3.  
If D2 > 10 ns, D2 = D4.  
021798 2/7  
DS1012  
PART NUMBER DELAY AND CONFIGURATION Table 1  
CATALOG  
P/N  
t
t
t
t
D4  
(ns)  
OUT1  
OUT2  
OUT3  
OUT4  
D1  
D2  
D3  
(ns)  
(ns)  
(ns)  
10  
10  
10  
25  
5
DS1012-1  
5
5
10  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D1  
D2  
D2  
D2  
D2  
D2  
D2  
D2  
D2  
D2  
D2  
D2  
D2  
D2  
D2  
D2  
D2  
D3  
D3.D4  
D3  
D4  
DS1012-2  
5
5
10  
D3+D4  
D4  
DS1012-3  
3
7
40  
DS1012-4  
5
5
25  
D3HXD4  
D3.D4  
D3  
D3XD4  
D3+D4  
D3XD4  
D3XD4  
D3XD4  
D3XD4  
D3XD4  
D3XD4  
D3XD4  
D3+D4  
D3XD4  
D3XD4  
D3+D4  
DS1012-5  
10  
15  
5
10  
4
5
DS1012-7  
4
14  
DS1012–9  
25  
19.6  
16.5  
14  
11.5  
9
5
25  
D3HXD4  
D3.D4  
D3.D4  
D3.D4  
D3.D4  
D3.D4  
D3.D4  
D3.D4  
D3.D4  
D3.D4  
DS1012-D16  
DS1012-D20  
DS1012-D25  
DS1012-D33  
DS1012-D50  
DS1012-V20  
DS1012-V40  
DS1012-V50  
DS1012-V60  
4
4
19.6  
16.5  
14  
4
4
4
4
4
4
11.5  
9
4
4
25  
12.5  
10  
8.3  
50  
25  
20  
8.3  
25  
12.5  
10  
8.3  
50  
25  
20  
8.3  
NOTE: . = AND, + = OR, X = XOR, HX = HALF–XOR  
Contact Dallas Semiconductor for information on custom configurations and timing delays.  
TEST CIRCUIT Figure 2  
START TIP  
(TIME INTERVAL  
PROBE)  
+5V  
Z
= 50  
0
TIME  
INTERVAL  
COUNTER  
PULSE  
GENERATOR  
+5V  
STOP  
TIP  
DEVICE  
UNDER  
TEST  
VHF  
SWITCH  
CONTROL  
UNIT  
Z
= 50 Ω  
0
74F04  
VHF SWITCH  
CONTROL UNIT  
021798 3/7  
DS1012  
TEST SETUP DESCRIPTION  
TEST CONDITIONS  
INPUT:  
Figure 2 illustrates the hardware configuration used for  
measuring the timing parameters on the DS1012. The  
input waveform is produced by a precision pulse gener-  
ator under software control connected to the inputs by  
VHF switch control units. Time delays are measured by  
a time interval counter (20 ps resolution) connected be-  
tween the inputs and the outputs. Outputs are con-  
nected to the counter by a VHF switch control unit. All  
measurements are fully automated, with each instru-  
mentcontrolled by a central computer over an IEEE 488  
bus.  
Ambient Temperature:  
25°C ± 3°C  
5.0V ± 0.1V  
High = 3.0V ± 0.1V  
Low = 0.0V ± 0.1V  
50 ohms max.  
3.0 ns max.  
50 ns  
Supply Voltage (V ):  
CC  
Input Pulse:  
Source Impedance:  
Rise and Fall Time:  
Pulse Width:  
Period:  
100 ns  
OUTPUT:  
Each output is loaded with a 74F04. Delay is measured  
betweenthe1.5Vleveloftherisingedgeoftheinputsig-  
nal and the 1.5V level of the corresponding edge of the  
output.  
NOTE: These conditions are for test only and do  
not restrict the operation of the device un-  
der other data sheet conditions.  
021798 4/7  
DS1012  
ABSOLUTE MAXIMUM RATINGS*  
Voltage on Any Pin Relative to Ground  
Operating Temperature  
-1.0V to +7.0V  
0°C to 70°C  
Storage Temperature  
Soldering Temperature  
-55°C to +125°C  
260°C for 10 seconds  
* This is a stress rating only and functional operation of the device at these or any other conditions above those  
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods of time may affect reliability.  
DC ELECTRICAL CHARACTERISTICS  
(0°C to 70°C; VCC = 5.0V ± 5%)  
PARAMETER  
SYMBOL  
TEST  
MIN  
4.75  
2.2  
TYP  
MAX  
UNITS NOTES  
Supply Voltage  
V
CC  
5.00  
5.25  
V
V
1
1
1
High Level Input Voltage  
Low Level Input Voltage  
Input Leakage Current  
Active Current  
V
IH  
V
+0.5  
CC  
V
IL  
-0.5  
-1.0  
0.8  
V
I
I
0.0V < V < V  
CC  
1.0  
µA  
mA  
I
I
I
V
= MAX;  
40.0  
70.0  
2
5
CC1  
CC  
PERIOD = MIN  
Quiescent Current  
V
= MAX.  
10  
µA  
CC2  
CC  
High Level Output Current  
I
V
V
= MIN  
= 2.4V  
-1.0  
mA  
OH  
CC  
OH  
Low Level Output Current  
I
OL  
V
V
= MIN.  
= 0.5V  
8.0  
mA  
CC  
OL  
AC ELECTRICAL CHARACTERISTICS  
(TA = 25°C; VCC = 5V ± 5%)  
PARAMETER  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
NOTES  
Input Pulse Width  
t
WI  
ns  
6
Input to Output (leading edge)  
t
t
, t  
, t  
D3 D4  
,
ns  
3, 4  
D1 D2  
Power-up Time  
t
0
ns  
ns  
7
PU  
Period  
2(t )  
WI  
CAPACITANCE  
PARAMETER  
(TA = 25°C)  
SYMBOL  
MIN  
TYP  
MAX  
UNITS  
NOTES  
Input Capacitance  
C
5
10  
pF  
IN  
021798 5/7  
DS1012  
DELAY FUNCTION Figure 3  
PERIOD  
IN1  
IN2  
t
WI  
t
WI  
t
D1  
~t  
D1  
OUT1  
OUT2  
t
D2  
t
D2  
t
D3  
~t  
D3  
OUT3  
“INVERT”  
t
D4  
~t  
D4  
OUT4  
“INVERT”  
LOGIC FUNCTIONS Figure 4  
PERIOD  
IN1  
IN2  
t
WI  
t
WI  
t
D4  
~t  
D3  
OUT3  
“AND”  
~t  
D4  
t
t
D3  
OUT4  
“OR”  
t
t
D4  
D3  
OUT3  
“HXOR”  
~t  
D3  
~t  
D4  
D4  
t
D3  
OUT4  
“XOR”  
t
t
D3 < D4  
021798 6/7  
DS1012  
NOTES:  
1. All voltages are referenced to ground.  
2. Measured with outputs open, minimum period. I  
formula:  
(max.) for any value of Period can be calculated using the  
CC1  
I
(max.) = 840/Period + I  
CC2  
CC1  
where I  
, I  
in mA, Period in ns  
CC1 CC2  
Example: If Period = 50 ns then  
(Max) = 840/50 + 0.01 = 16.81 mA  
I
CC1  
3. V = 5V @ 25°C. Delays referenced to leading (input rising) edges are accurate within ±1.5 ns for values  
CC  
between 3 to 10 ns and ±2 ns for values between 11 to 40 ns. Delays referenced to trailing (input falling)  
edges will typically equal the corresponding leading edge delay within ±1 ns.  
4. See the section entitled “Test Conditions.”  
5. For the quiescent mode, both inputs must meet the conditions  
0.3V > V or VI > V - 0.3  
I
CC  
6. For specified accuracy, t (min) is the longer of 3(t ), 3(t ), 3(t ), or 3(t ). Pulse doublers designed for  
WI  
D1  
D2  
D3  
D4  
single frequency use will meet specified accuracies at 50% duty cycle; i.e., 2(t ) = 1/FREQ = PERIOD. Cus-  
WI  
toms will be adjusted to be accurate at customer input width specifications when t is longer than t , t  
,
WI  
D1 D2  
t
D3  
, and t  
.
D4  
7. On power-up, the DS1012 will supply timing and logic functions with specified accuracy as soon as V  
achieves nominal value.  
CC  
021798 7/7  

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