DS1086LU-A12+ [MAXIM]
Analog Circuit, 1 Func, PDSO8, 0.118 INCH, ROHS COMPLIANT, MICRO, SOP-8;
| 型号： | DS1086LU-A12+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, PDSO8, 0.118 INCH, ROHS COMPLIANT, MICRO, SOP-8 光电二极管 |
| 文件： | 总17页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1086L
3.3V Spread-Spectrum EconOscillator
General Description
Features
The DS1086L EconOscillator™ is a 3.3V programmable
clock generator that produces a spread-spectrum
(dithered) square-wave output of frequencies from
130kHz to 66.6MHz. The selectable dithered output
reduces radiated-emission peaks by dithering the fre-
quency 0.5%,1%, 2%, 4%, or 8% below the pro-
grammed frequency. The DS1086L has a power-down
mode and an output-enable control for power-sensitive
applications. All the device settings are stored in non-
volatile (NV) EEPROM memory allowing it to operate in
stand-alone applications.
♦ User-Programmable Square-Wave Generator
♦ Frequencies Programmable from 130kHz to
66.6MHz
♦ 0.5%, 1%, 2%, 4%, or 8% Selectable Dithered
Output
♦ Adjustable Dither Rate
♦ Glitchless Output-Enable Control
♦ 2-Wire Serial Interface
♦ Nonvolatile Settings
Applications
♦ 2.7V to 3.6V Supply
Printers
♦ No External Timing Components Required
♦ Power-Down Mode
Copiers
PCs
Computer Peripherals
Cell Phones
Cable Modems
♦ 5kHz Master Frequency Step Size
♦ EMI Reduction
♦ Industrial Temperature Range: -40°C to +85°C
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PART
DS1086LU
DS1086LU+
PIN-PACKAGE
8 μSOP (118 mils)
8 μSOP (118 mils)
Note: Contact the factory for custom settings.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Operating Circuit
Pin Configuration
V
CC
DITHERED 130kHz TO
66.6MHz OUTPUT
TOP VIEW
μP
SCL*
XTL1/OSC1
XTL2/OSC2
OUT
V
CC
OUT
1
2
3
4
8
7
6
5
SCL
SDA
PDN
OE
SPRD
SDA*
PDN
OE
N.C.
DS1086L
SPRD
V
CC
DS1086L
GND
V
CC
GND
DECOUPLING CAPACITORS
(0.1μF and 0.01μF)
*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086L NEVER NEEDS
TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.
µSOP
EconOscillator is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6226; Rev 2; 3/12
DS1086L
3.3V Spread-Spectrum EconOscillator
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
Relative to Ground ..........-0.5V to +6.0V
Programming Temperature Range.........................0°C to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-55°C to +150°C
Soldering Temperature (reflow)
CC
Voltage Range on SPRD, PDN, OE, SDA, and SCL
Relative to Ground* ..................................-0.5 to (V
+ 0.5V)
CC
Continuous Power Dissipation (T = +70°C)
A
μSOP (derate 4.5mW/°C above +70°C)........................362mW
Operating Temperature Range ...........................-40°C to +85°C
Lead(Pb)-free................................................................+260°C
Containing lead(Pb)......................................................+240°C
*This voltage must not exceed 6.0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(V
CC
= 2.7V to 3.6V, T = -40°C to +85°C.)
A
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
2.7
TYP
3.3
MAX
3.6
UNITS
V
V
(Note 1)
CC
High-Level Input Voltage
(SDA, SCL, SPRD, PDN, OE)
0.7 x
V
+
CC
0.3
V
V
V
IH
V
CC
Low-Level Input Voltage
(SDA, SCL SPRD, PDN, OE)
0.3 x
V
CC
V
-0.3
IL
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V to 3.6V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
= min
CC
MIN
2.4
0
TYP
MAX
UNITS
High-Level Output Voltage (OUT)
V
I
I
= -4mA, V
= 4mA
V
OH
OH
OL
Low-Level Output Voltage (OUT)
V
0.4
0.4
0.6
1
V
OL
V
V
3mA sink current
6mA sink current
0
OL1
OL2
Low-Level Output Voltage (SDA)
V
0
High-Level Input Current
Low-Level Input Current
Supply Current (Active)
I
V
V
= 3.6V
CC
μA
μA
mA
μA
IH
I
= 0V
IL
-1
IL
I
C = 15pF (output at default frequency)
L
10
10
CC
Standby Current (Power-Down)
I
Power-down mode
CCQ
2
Maxim Integrated
DS1086L
3.3V Spread-Spectrum EconOscillator
MASTER OSCILLATOR CHARACTERISTICS
(V
CC
= 2.7V to 3.6V, T = -40°C to +85°C.)
A
PARAMETER
Master Oscillator Frequency
SYMBOL
CONDITIONS
MIN
33.3
TYP
MAX
66.6
UNITS
MHz
f
(Note 2)
OSC
Default Master Oscillator Frequency
f
Factory-programmed default
48.65
MHz
0
V
= 3.3V,
= +25°C
CC
Default frequency(f )
0
-0.5
-0.5
+0.5
+0.5
Master Oscillator Frequency
Tolerance
Δf
0
V
T
%
%
%
T
A
f
0
DAC step size
(Notes 3,17)
Default frequency
DAC step size
Default frequency
66.6MHz
-0.75
-0.75
-2.0
+0.75
+0.75
+0.75
+0.75
+0.75
Δf
Over voltage range,
T = +25°C (Note 4)
A
Voltage Frequency Variation
f
0
Over temperature
range, V = 3.3V
CC
(Note 5)
Δf
Temperature Frequency Variation
-2.0
f
0
33.3MHz
-2.5
Prescaler bits JS2, JS1, JS0 = 000
Prescaler bits JS2, JS1, JS0 = 001
Prescaler bits JS2, JS1, JS0 = 010
Prescaler bits JS2, JS1, JS0 = 100
Prescaler bits JS2, JS1, JS0 = 111
Entire range (Note 7)
0.5
1
Δf
Dither Frequency Range (Note 6)
2
%
f
0
4
8
Integral Nonlinearity of Frequency
DAC Step Size
INL
-0.6
+0.3
%
Δ between two consecutive DAC values
(Note 8)
5
kHz
Frequency range for one offset setting
(Table 2)
DAC Span
5.12
500
MHz
decimal
MHz
DAC Default
Offset Step Size
Factory default register setting
Δ between two consecutive offset values
(Table 2)
2.56
RANGE
(5 LSBs of
RANGE register)
Factory default OFFSET register setting
(5 LSBs) (Table 2)
Offset Default
Dither Rate
OS
hex
Hz
Prescaler bits JS4, JS3 = 00
Prescaler bits JS4, JS3 = 01
Prescaler bits JS4, JS3 = 10
f /8192
0
f /4096
0
f /2048
0
Maxim Integrated
3
DS1086L
3.3V Spread-Spectrum EconOscillator
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.7V to 3.6V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Frequency Stable After Prescaler
Change
1
period
Frequency Stable After DAC or
Offset Change
t
(Note 9)
0.1
0.1
1
ms
ms
μs
DACstab
Power-Up Time
t
+ t
(Note 10)
(Note 18)
0.5
200
por
stab
Enable of OUT After Exiting
Power-Down Mode
t
stab
OUT High-Z After Entering
Power-Down Mode
t
100
μs
pdn
Load Capacitance
C
(Note 11)
15
50
55
1
pF
%
L
Output Duty Cycle (OUT)
Rise and Fall Time (OE, PDN)
Default frequency
45
μs
AC ELECTRICAL CHARACTERISTICS—2-WIRE INTERFACE
(V
CC
= 2.7V to 3.6V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
(Note 12)
MIN
TYP
MAX
400
100
UNITS
Fast mode
Standard mode
Fast mode
SCL Clock Frequency
f
kHz
SCL
1.3
4.7
0.6
Bus Free Time Between a STOP
and START Condition
t
(Note 12)
μs
μs
BUF
Standard mode
Fast mode
Hold Time (Repeated) START
Condition
t
(Notes 12, 13)
HD:STA
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
4.0
1.3
4.7
0.6
4.0
0.6
LOW Period of SCL
HIGH Period of SCL
t
(Note 12)
(Note 12)
μs
μs
LOW
t
HIGH
Setup Time for a Repeated
START
t
(Note 12)
μs
SU:STA
HD:DAT
Standard mode
Fast mode
4.7
Data Hold Time
Data Setup Time
t
(Notes 12, 14, 15)
(Note 12)
0
0.9
μs
ns
ns
Standard mode
Fast mode
Standard mode
Fast mode
100
250
t
SU:DAT
20 + 0.1C
300
1000
300
B
B
B
B
Rise Time of Both SDA and SCL
Signals
t
(Note 16)
R
Standard mode
Fast mode
20 + 0.1C
20 + 0.1C
20 + 0.1C
Fall Time of Both SDA and SCL
Signals
t
F
(Note 16)
ns
Standard mode
1000
4
Maxim Integrated
DS1086L
3.3V Spread-Spectrum EconOscillator
AC ELECTRICAL CHARACTERISTICS—2-WIRE INTERFACE (continued)
(V
CC
= 2.7V to 3.6V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
0.6
TYP
MAX
UNITS
Fast mode
Setup Time for STOP
t
μs
SU:STO
Standard mode
4.0
Capacitive Load for Each Bus
Line
C
(Note 16)
400
10
pF
B
EEPROM Write Cycle Time
Input Capacitance
t
ms
pF
WR
C
5
I
NONVOLATILE MEMORY CHARACTERISTICS
(V
CC
= 2.7V to 3.6V)
PARAMETER
EEPROM Writes
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
+70°C
10,000
Note 1:
Note 2:
All voltages are referenced to ground.
DAC and OFFSET register settings must be configured to maintain the master oscillator frequency within this range.
Correct operation of the device is not guaranteed if these limits are exceeded.
Note 3:
Note 4:
This is the absolute accuracy of the master oscillator frequency at the default settings.
This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at
T
= +25°C.
A
Note 5:
This is the percentage frequency change from the +25°C frequency due to temperature at V = 3.3V. The maximum temper-
CC
ature change varies with the master oscillator frequency setting. The minimum occurs at the default master oscillator frequen-
cy (f ). The maximum occurs at the extremes of the master oscillator frequency range (33.3MHz or 66.6MHz).
default
Note 6:
Note 7:
The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency.
The integral nonlinearity of the frequency is a measure of the deviation from a straight line drawn between the two end-
points (f
to f
) of the range. The error is in percentage of the span.
osc(MIN)
osc(MAX)
Note 8:
Note 9:
This is true when the prescaler = 1.
Frequency settles faster for small changes in value. During a change, the frequency transitions smoothly from the original
value to the new value.
Note 10: This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally
introduced to allow the oscillator to stabilize. t is equivalent to approximately 512 master clock cycles and therefore
stab
depends on the programmed clock frequency.
Note 11: Output voltage swings can be impaired at high frequencies combined with high output loading.
Note 12: A fast-mode device can be used in a standard-mode system, but the requirement t > 250ns must then be met.
SU:DAT
This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line at least t
1000ns + 250ns = 1250ns before the SCL line is released.
+ t
=
R MAX
SU:DAT
Note 13: After this period, the first clock pulse is generated.
Note 14: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
of the SCL
IH MIN
signal) to bridge the undefined region of the falling edge of SCL.
Note 15: The maximum t
need only be met if the device does not stretch the LOW period (t
) of the SCL signal.
HD:DAT
LOW
Note 16: C —total capacitance of one bus line, timing referenced to 0.9 x V
and 0.1 x V
.
B
CC
CC
Note 17: Typical frequency shift due to aging is 0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr
+125°C bake, 168hr 85°C/85%RH moisture soak, and three solder reflow passes +240 +0/-5°C peak) followed by 1000hr
max V
biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, 96hr 130°C/85%RH/3.6V HAST and 168hr
CC
121°C/2 ATM Steam/Unbiased Autoclave.
t is the time required after exiting power-down to the beginning of output oscillations. In addition, a delay of t
stab
Note 18:
DACstab
is required before the frequency will be within its specified tolerance.
Maxim Integrated
5
DS1086L
3.3V Spread-Spectrum EconOscillator
Typical Operating Characteristics
(V
CC
= 3.3V, T = 25°C, unless otherwise noted.)
A
SUPPLY CURRENT vs.
MASTER OSCILLATOR FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. PRESCALER
10
9
7
6
5
4
3
2
1
0
9
8
f
f
= 66MHz
= 50MHz
O
O
15pF LOAD
7
6
5
4
3
2
1
8
7
6
4.7pF LOAD
f
O
= 33.3MHz
5
PRESCALER = 1
15pF LOAD
f = 50MHz
O
15pF LOAD
4
PRESCALER = 1
3
-40
-15
10
35
60
85
1
10
100
1000
33 36 39 42 45 48 51 54 57 60 63 66
MASTER FREQUENCY (MHz)
TEMPERATURE (°C)
PRESCALER
MASTER OSCILLATOR FREQUENCY PERCENT
CHANGE vs. SUPPLY VOLTAGE
MASTER OSCILLATOR FREQUENCY PERCENT
CHANGE vs. TEMPERATURE
DUTY CYCLE vs. TEMPERATURE
55
54
53
52
51
50
0.5
0.50
0.4
0.3
0.25
0
f
O
= 33.3MHz
0.2
f
O
= 66MHz
f
O
= 66MHz
-0.25
-0.50
-0.75
-1.00
-1.25
-1.50
0.1
0
f
= 50MHz
O
-0.1
-0.2
-0.3
-0.4
-0.5
f
= 50MHz
O
f
= 66MHz
O
f
O
= 50MHz
f
O
= 33.3MHz
f
O
= 33.3MHz
PRESCALER = 1
15pF LOAD
PRESCALER = 1
60 85
PRESCALER = 1
3.3
-40
-15
10
35
2.7
3.0
3.6
-40
-15
10
35
60
85
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DUTY CYCLE vs. SUPPLY VOLTAGE
55
54
53
52
51
f
= 66MHz
O
f
O
= 50MHz
f
= 33.3MHz
O
PRESCALER = 1
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
6
Maxim Integrated
DS1086L
3.3V Spread-Spectrum EconOscillator
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, T = 25°C, unless otherwise noted.)
A
POWER-DOWN CURRENT vs.
SUPPLY VOLTAGE
POWER-DOWN CURRENT vs. TEMPERATURE
1.64
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1.62
1.60
1.58
1.56
1.54
1.52
1.50
1.48
1.46
1.44
-40
-15
10
35
60
85
2.7
3.0
3.3
3.6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT WITH OUTPUT
DISABLED vs. TEMPERATURE
SUPPLY CURRENT WITH OUTPUT
DISABLED vs. SUPPLY VOLTAGE
2.7
2.6
2.5
2.4
2.3
2.2
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
f
O
= 66MHz
60
f
O
= 66MHz
-40
-15
10
35
85
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Maxim Integrated
7
DS1086L
3.3V Spread-Spectrum EconOscillator
Pin Description
PIN
1
NAME
OUT
FUNCTION
Oscillator Output. The output frequency is determined by the OFFSET, DAC, and prescaler registers.
2
SPRD
Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled.
3
V
Power Supply
Ground
CC
4
GND
Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is
disabled but the master oscillator is still on.
5
6
7
8
OE
Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master
oscillator is disabled (power-down mode).
PDN
SDA
SCL
2-Wire Serial Data. This pin is for serial data transfer to and from the device. The pin is open drain and
can be wire-ORed with other open-drain or open-collector interfaces.
2-Wire Serial Clock. This pin is used to clock data into the device on rising edges and clock data out on
falling edges.
SPECTRUM COMPARISON
(12OkHz BW, SAMPLE DETECT)
MAXIMUM THERMAL VARIATION vs.
MASTER OSCILLATOR FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
3%
2%
0.5%
8%
NO
SPREAD
2%
1%
0
-1%
-2%
-3%
-4%
-5%
fo = 50MHz
DITHER RATE = fo/4096
43
45
47
49
51
53
33 36 39 42 45 48 51 54 57 60 63 66
MASTER FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 2. Temperature Variation Over Frequency
Figure 1. Clock Spectrum Dither Comparison
Processor-Controlled Mode
Stand-Alone Mode
V
CC
V
CC
DITHERED 130kHz TO
66.6MHz OUTPUT
μP
4.7kΩ
SCL
4.7kΩ
SCL*
XTL1/OSC1
XTL2/OSC2
OUT
DITHERED 260kHz TO
133MHz OUTPUT
V
CC
SPRD
SDA*
PDN
OE
N.C.
DS1086L
2-WIRE
INTERFACE
V
CC
OUT
V
CC
SDA
GND
V
SPRD
CC
DS1086L
V
PDN
OE
CC
DECOUPLING CAPACITORS
(0.1μF and 0.01μF)
GND
*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1086L NEVER NEEDS
TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.
DECOUPLING CAPACITORS
(0.1μF and 0.01μF)
8
Maxim Integrated
DS1086L
3.3V Spread-Spectrum EconOscillator
V
CC
DS1086L
V
CC
EEPROM CONTROL
REGISTERS
SDA
2-WIRE
INTERFACE
SCL
DAC
DAC
OFFSET
ADDR
RANGE
FREQUENCY
CONTROL VOLTAGE
PRESCALER
VOLTAGE-CONTROLLED
OSCILLATOR
PDN
MASTER
OSCILLATOR
OUTPUT
DITHER
CONTROL
PRESCALER
BY 1, 2, 4...256
OUT
OE
TRIANGLE WAVE
GENERATOR
SPRD
GND
DITHER SIGNAL
Figure 3. Block Diagram
happens because the prescaler’s divider function tends
to average the dither in creating the lower frequency.
However, the most stringent spectral emission limits are
imposed on the higher frequencies where the prescaler
is set to a low divider ratio.
Detailed Description
A block diagram of the DS1086L is shown in Figure 3.
The internal master oscillator generates a square wave
with a 33.3MHz to 66.6MHz frequency range. The fre-
quency of the master oscillator can be programmed
with the DAC register over a two-to-one range in 5kHz
steps. The master oscillator range is larger than the
range possible with the DAC step size, so the OFFSET
register is used to select a smaller range of frequencies
over which the DAC spans. The prescaler can then be
set to divide the master oscillator frequency by 2x
(where x equals 0 to 8) before routing the signal to the
output (OUT) pin.
The external control input, OE, gates the clock output
buffer. The PDN pin disables the master oscillator and
turns off the clock output for power-sensitive applica-
tions*. On power-up, the clock output is disabled until
power is stable and the master oscillator has generated
512 clock cycles. Both controls feature a synchronous
enable that ensures there are no output glitches when
the output is enabled.
The control registers are programmed through a 2-wire
interface and are used to determine the output frequen-
cy and settings. Once programmed into EEPROM,
since the register settings are NV, the settings only
need to be reprogrammed if it is desired to reconfigure
the device.
A programmable triangle-wave generator injects an off-
set element into the master oscillator to dither its output
0.5%, 1%, 2%, 4%, or 8%. The dither magnitude is con-
trolled by the JS2, JS1, and JS0 bits in the PRESCALER
word and enabled with the SPRD pin. Futhermore, the
dither rate is controlled by the JS4 and JS3 bits in the
PRESCALER word and determines the frequency of the
dither. The maximum spectral attenuation occurs when
the prescaler is set to 1 and is reduced by 2.7dB for
every factor of 2 that is used in the prescaler. This
*The power-down command must persist for at least two out-
put frequency cycles plus 10μs for deglitching purposes.
Maxim Integrated
9
DS1086L
3.3V Spread-Spectrum EconOscillator
Table 1. Register Summary
FACTORY
DEFAULT
REGISTER
ADDR
MSB
BINARY
JS1 JS0
LSB
ACCESS
PRESCALER
PRESCALER
DAC (MSB)
DAC (LSB)
OFFSET
ADDR
RANGE
WRITE EE
02h
—
08h
—
0Eh
0Dh
37h
3Fh
JS4
P1
b9
JS3
P0
b8
JS2
LO/HiZ
P3
P2
X
X
b2
X
0
b0
A0
b0
01100000
00XXXXX
01111101b
00000000b
111-----b
11110000b
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
X
X
b7
b6
b5
b4
b3
b1
b0
X
X
X
X
X
X
X
X
0
1
1
X
0
0
0
0
X
X
X
X
1
X
1
X
X
b4
X
1
b4
b3
WC
b3
b2
A2
b2
b1
A1
b1
1
1
X
xxx-----b
—
R
—
NO DATA
X = Don’t care, reads as zero.
0
X = Don’t care, reads as one.
1
X = Don’t care, reads indeterminate.
X
X = Don’t care.
DAC value is the value of the DAC register (0 to 1023).
Prescaler is the value of 2x where x = 0 to 8.
Table 2. Offset Settings
OFFSET
OS - 6
OS - 5
OS - 4
OS - 3
OS - 2
OS - 1
OS*
FREQUENCY RANGE (MHz)
30.74 to 35.86
33.30 to 38.42
35.86 to 40.98
38.42 to 43.54
40.98 to 46.10
43.54 to 48.66
46.10 to 51.22
48.66 to 53.78
51.22 to 56.34
53.78 to 58.90
56.34 to 61.46
58.90 to 64.02
61.46 to 66.58
See the Example Frequency Calculations section for a
more in-depth look at using the registers.
________________Register Definitions
The DS1086L registers are used to program the output
frequency, dither percent, dither rate, and 2-wire
address. Table 1 shows a summary of the registers and
detailed descriptions follow below.
PRESCALER (02h)
The PRESCALER word is a two-byte value containing
control bits for the prescaler (P3 to P0), output control
(Lo/HiZ), the jitter rate (JS4 to JS3), as well as control
bits for the jitter percentage (JS2 to JS0). The
PRESCALER word is read and written using two-byte
reads and writes beginning at address 02h.
OS + 1
OS + 2
OS + 3
OS + 4
OS + 5
OS + 6
JS4 to JS3: Jitter Rate. This is the frequency of the tri-
angle wave generator and the modulation frequency
that the output is dithered. It can be programmed to the
*Factory default setting. OS is the integer value of the five LSBs
of the RANGE register.
master oscillator frequency, f
8192, 4096, or 2048.
, divided by either
OSC
The output frequency is determined by the following
equation:
JS4
0
JS3
0
JITTER RATE
/8192
f
OSC
f
(MINFREQUENCY OF SELECTEDOFFSET RANGE)
0
1
f
/4096 (default)
OSC
+ (DAC VALUE × 5kHz STEP SIZE)
OUTPUT =
1
0
f
/2048
OSC
PRESCALER
where: min frequency of selected OFFSET range is the
lowest frequency (shown in Table 2 for the correspond-
ing offset).
10
Maxim Integrated
DS1086L
3.3V Spread-Spectrum EconOscillator
JS2 to JS0: Jitter Percentage. These three bits select
RANGE (37h)
B4 to B0: Range: This read-only, factory programmed
value is a copy of the factory default offset (OS). OS is
required to program new master oscillator frequencies
shown in Table 2. The read-only backup is important
because the offset register is EEPROM and is likely to
be overwritten.
the amount of jitter in percent. The SPRD pin must be a
logic high for the jitter to be enabled. Bit combinations
not shown are reserved.
JS2
0
JS1
0
JS0
0
JITTER %
0.5
0
0
1
1
ADDR (0Dh)
WC: EEPROM Write Control Bit. The WC bit
enables/disables the automatic writing of registers to
EEPROM. This prevents EEPROM wear out and elimi-
nates the EEPROM write cycle time. If WC = 0 (default),
register writes are automatically written to EEPROM. If
WC = 1, register writes are stored in SRAM and only
written into EEPROM when the user sends a WRITE EE
command. If power is cycled to the device, then the
last value stored in EEPROM is recalled. WC = 1 is
ideal for applications that frequently modify the fre-
quency/registers.
0
1
0
2
1
0
0
4
1
1
1
8
Lo/HiZ: Output Low or High-Z. This bit determines the
state of the output pin when the device is in power-
down mode or when the output is disabled. If Lo/HiZ =
0, the output is HiZ when in power-down or disabled. If
Lo/HiZ = 1, the output is held low when in power-down
or disabled.
P3 to P0: Prescaler Divider. These bits divide the
master oscillator frequency by 2x, where x is P3 to P0
and can be from 0 to 8. Any prescaler value entered
greater than 8 decodes as 8.
Regardless of the value of the WC bit, the value of the
ADDR register is always written immediately to EEPROM.
A2 to A0: Device Address Bits. These bits determine
the 2-wire slave address of the device. They allow up to
eight devices to be attached to the same 2-wire bus
and to be addressed individually.
DAC (08h)
B9 to B0: DAC Setting. The DAC word sets the master
oscillator frequency to a specific value within the cur-
rent offset range. Each step of the DAC changes the
master oscillator frequency by 5kHz. The DAC word is
read and written using two-byte reads and writes
beginning at address 08h.
WRITE EE Command (3Fh)
This command can be used when WC = 1 (see the WC
bit in ADDR register) to transfer all registers from SRAM
into EEPROM. The time required to store the values is
one EEPROM write cycle time. This command is not
needed if WC = 0.
OFFSET (0Eh)
B4 to B0: Offset. This value selects the master oscilla-
tor frequency range that can be generated by varying
the DAC word. Valid frequency ranges are shown in
Table 2. Correct operation of the device is not guaran-
teed for values of OFFSET not shown in the table.
The default offset value (OS) is factory trimmed and
can vary from device to device. Therefore, to change
frequency range, OS must be read so the new offset
value can be calculated relative to the default. For
example, to generate a master oscillator frequency
within the largest range (61.4MHz to 66.6MHz), Table 2
indicates that the OFFSET must be programmed to OS
+ 6. This is done by reading the RANGE register and
adding 6 to the value of bits B4 to B0. The result is then
written into bits B4 to B0 of the OFFSET register.
Additional examples are provided in the Example
Frequency Calculations section.
Maxim Integrated
11
DS1086L
3.3V Spread-Spectrum EconOscillator
Valid values of DAC are 0 to 1023 (decimal) and 5kHz
is the step size. Equation 4 is derived from rearranging
Equation 3 and solving for the DAC value.
Example Frequency Calculations
Example #1: Calculate the register values needed to
generate a desired output frequency of 11.0592MHz.
Since the desired frequency is not within the valid mas-
ter oscillator range of 33.3MHz to 66.6MHz, the
prescaler must be used. Valid prescaler values are 2x
where x equals 0 to 8 (and x is the value that is pro-
grammed into the P3 to P0 bits of the PRESCALER reg-
ister). Equation 1 shows the relationship between the
desired frequency, the master oscillator frequency, and
the prescaler.
(f
MASTEROSCILLATOR
−
(4)
MINFREQUENCY OF SELECTED
OFFSET RANGE)
DAC VALUE =
5kHz STEP SIZE
(44.2368MHz − 41.0MHz)
5kHz STEP SIZE
= 647.36 ≈ 647 (decimal)
DAC VALUE =
f
=
f
MASTEROSCILLATOR
DESIRED =
(1)
prescaler
f
MASTEROSCILLATOR
2X
Since the two-byte DAC register is left justified, 647 is
converted to hex (0287h) and bit-wise shifted left six
places. The value to be programmed into the DAC reg-
ister is A1C0h.
By trial and error, x is incremented from 0 to 8 in
Equation 2, finding values of x that yield master oscillator
frequencies within the range of 33.3MHz to 66.6MHz.
In summary, the DS1086L is programmed as follows:
PRESCALER = 0080h
Equation 2 shows that a prescaler of 4 (x = 2) and a
master oscillator frequency of 44.2368MHz generates
our desired frequency. Writing 0080h to the
PRESCALER register sets the PRESCALER to 4. Be
aware that other settings also reside in the PRESCALER
register.
OFFSET = OS - 2 or 10h (if range was read as 12h)
DAC = A1C0h
Notice that the DAC value was rounded. Unfortunately,
this means that some error is introduced. To calculate
how much error, a combination of Equation 1 and
Equation 3 is used to calculate the expected output fre-
quency. See Equation 5.
f
= f
x prescaler = f
x 2X
DESIRED
MASTER OSCILLATOR
DESIRED
(2)
f
2
MASTER OSCILLATOR = 11.0592MHz x 2 = 44.2368MHz
Once the target master oscillator frequency has been
calculated, the value of offset can be determined.
Using Table 2, 44.2368MHz falls within both OS - 1 and
OS - 2. However, choosing OS - 1 would be a poor
choice since 44.2368MHz is so close to OS - 1’s mini-
mum frequency. On the other hand, OS - 2 is ideal
since 44.2368MHz is close to the center of
OS - 2’s frequency span. Before the OFFSET register
can be programmed, the default value of offset (OS)
must be read from the RANGE register (last five bits). In
this example, 12h (18 decimal) was read from the
RANGE register. OS - 2 for this case is 10h (16 deci-
mal). This is the value that is written to the OFFSET reg-
ister.
(MINFREQUENCY OF SELECTEDOFFSET
(5)
RANGE) + (DAC VALUE x 5kHz STEP SIZE)
prescaler
f
=
OUTPUT
(41.0MHz) + (647 x 5kHz)
f
=
=
OUTPUT
4
44.235MHz
4
=11.05875MHz
Finally, the two-byte DAC value needs to be deter-
mined. Since OS - 2 only sets the range of frequencies,
the DAC selects one frequency within that range as
shown in Equation 3.
f
MASTER OSCILLATOR = (MIN FREQUENCY OF SELECTED OFFSET
RANGE) + (DAC value x 5kHz)
(3)
12
Maxim Integrated
DS1086L
3.3V Spread-Spectrum EconOscillator
SDA
MSB
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
9
ACK
ACK
START
CONDITION
STOP
CONDITION
OR REPEATED
START
REPEATED IF MORE BYTES
ARE TRANSFERRED
CONDITION
Figure 4. 2-Wire Data Transfer Protocol
The expected output frequency is not exactly equal to the
desired frequency of 11.0592MHz. The difference is
450Hz. In terms of percentage, Equation 6 shows that the
expected error is 0.004%. The expected error assumes
typical values and does not include deviations from the
typical as specified in the electrical tables.
Finally, the DAC value is calculated as shown in
Equation 8.
(8)
(50.0MHz − 48.6MHz)
5kHz STEP SIZE
DAC VALUE =
= 280.00 (decimal)
The result is then converted to hex (0118h) and then
left-shifted, resulting in 4600h to be programmed into
the DAC register.
f
− f
DESIRED EXPECTED
In summary, the DS1086L is programmed as follows:
PRESCALER = 0000h
%ERROR
EXPECTED
=
×100
f
DESIRED
(6)
OFFSET = OS + 1 or 13h (if RANGE was read as 12h)
DAC = 4600h
11.0592MHz −11.05875MHz
11.0592MHz
%ERROR
EXPECTED
=
×100
450Hz
=
×100 = 0.004%
11.0592MHz
(48.6MHz) + (280 × 5kHz)
f
=
=
OUTPUT
0
Example #2: Calculate the register values needed to
generate a desired output frequency of 50MHz.
Since the desired frequency is already within the valid
master oscillator frequency range, the prescaler is set
to divide by 1, and hence, PRESCALER = 0000h
(9)
2
50.0MHz
= 50.0MHz
1
(currently ignoring the other setting).
Since the expected output frequency is equal to the
desired frequency, the calculated error is 0%.
(7)
f
= 50.0MHz x 20 = 50.0MHz
MASTER OSCILLATOR
Next, looking at Table 2, OS + 1 provides a range of
frequencies centered around the desired frequency. To
determine what value to write to the OFFSET register,
the RANGE register must first be read. Assuming 12h
was read in this example, 13h (OS + 1) is written to the
OFFSET register.
Maxim Integrated
13
DS1086L
3.3V Spread-Spectrum EconOscillator
MSB
1
LSB
R/W
0
1
1
A2
A1
A0
DEVICE
IDENTIFIER
DEVICE
ADDRESS
Figure 5. Slave Address
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
Figure 6. 2-Wire AC Characteristics
in the data line while the clock line is HIGH are
interpreted as control signals.
_______2-Wire Serial Port Operation
2-Wire Serial Data Bus
The DS1086L communicates through a 2-wire serial
interface. A device that sends data onto the bus is
defined as a transmitter, and a device receiving data
as a receiver. The device that controls the message is
called a “master.” The devices that are controlled by
the master are “slaves.” A master device that generates
the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions must con-
trol the bus. The DS1086L operates as a slave on the 2-
wire bus. Connections to the bus are made through the
open-drain I/O lines SDA and SCL.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data
line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer: A change in the state of the data
line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is sta-
ble for the duration of the HIGH period of the clock sig-
nal. The data on the line must be changed during the
LOW period of the clock signal. There is one clock
pulse per bit of data.
The following bus protocol has been defined (see
Figures 4 and 6):
•
Data transfer can be initiated only when the bus is
not busy.
•
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
14
Maxim Integrated
DS1086L
3.3V Spread-Spectrum EconOscillator
data bytes transferred between START and STOP con-
The master device generates all the serial clock pulses
and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the
beginning of the next serial transfer, the bus is not
released.
ditions is not limited, and is determined by the master
device. The information is transferred byte-wise and
each receiver acknowledges with a ninth bit.
Within the bus specifications a standard mode (100kHz
clock rate) and a fast mode (400kHz clock rate) are
defined. The DS1086L works in both modes.
The DS1086L can operate in the following two modes:
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the byte has been received. The master device
must generate an extra clock pulse that is associated
with this acknowledge bit.
Slave receiver mode: Serial data and clock are
received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted. START
and STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is per-
formed by hardware after reception of the slave
address and direction bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge-related clock pulse. Of course,
setup and hold times must be taken into account.
When the DS1086L EEPROM is being written to, it is
not able to perform additional responses. In this case,
the slave DS1086L sends a not acknowledge to any
data transfer request made by the master. It resumes
normal operation when the EEPROM operation is com-
plete.
Slave transmitter mode: The first byte is received and
handled as in the slave receiver mode. However, in this
mode, the direction bit indicates that the transfer direc-
tion is reversed. Serial data is transmitted on SDA by
the DS1086L while the serial clock is input on SCL.
START and STOP conditions are recognized as the
beginning and end of a serial transfer.
Slave Address
Figure 5 shows the first byte sent to the device. It
includes the device identifier, device address, and the
R/W bit. The device address is determined by the
ADDR register.
A master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line HIGH to enable the master to
generate the STOP condition.
Registers/Commands
See Table 1 for the complete list of registers/com-
mands and Figure 7 for an example of using them.
Figures 4, 5, 6, and 7 detail how data transfer is
accomplished on the 2-wire bus. Depending upon the
state of the R/W bit, two types of data transfer are pos-
sible:
__________Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1086L,
decouple the power supply with 0.01μF and 0.1μF
high-quality, ceramic, surface-mount capacitors.
Surface-mount components minimize lead inductance,
which improves performance, and ceramic capacitors
tend to have adequate high-frequency response for
decoupling applications. These capacitors should be
placed as close to pins 3 and 4 as possible.
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master
is the slave address. Next follows a number of
data bytes. The slave returns an acknowledge bit
after each received byte.
2) Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is
transmitted by the master. The slave then returns
an acknowledge bit. Next follows a number of
data bytes transmitted by the slave to the master.
The master returns an acknowledge bit after all
received bytes other than the last byte. At the end
of the last received byte, a not acknowledge is
returned.
Stand-Alone Mode
SCL and SDA cannot be left unconnected when they
are not used. If the DS1086L never needs to be pro-
grammed in-circuit, including during production test-
ing, SDA and SCL can be tied high. The SPRD pin
must be tied either high or low.
Maxim Integrated
15
DS1086L
3.3V Spread-Spectrum EconOscillator
TYPICAL 2-WIRE WRITE TRANSACTION
MSB
1
LSB
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
0
1
1
A2* A1* A0* R/W
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
READ/
WRITE
DEVICE
ADDRESS
COMMAND/REGISTER ADDRESS
DATA
DEVICE IDENTIFIER
EXAMPLE 2-WIRE TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO)
B0h
0Eh
DATA
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
A) SINGLE BYTE WRITE
-WRITE OFFSET REGISTER
STOP
1 0 1 1 0 0 0 0
0 0 0 0 1 1 1 0
OFFSET
START
0Eh
B1h
DATA
B0h
B) SINGLE BYTE READ
-READ OFFSET REGISTER
SLAVE REPEATED
MASTER
NACK
SLAVE
ACK
SLAVE
ACK
STOP
1 0 1 1 0 0 0 1
OFFSET
START 1 0 1 1 0 0 0 0
0 0 0 0 1 1 1 0
ACK
START
DATA
B0h
08h
DATA
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
C) TWO BYTE WRITE
-WRITE DAC REGISTER
SLAVE
ACK
START
START
1 0 1 1 0 0 0 0
DAC MSB
DAC LSB
STOP
0 0 0 0 1 0 0 0
B0h
B1h
08h
DATA
DATA
DAC LSB
D) TWO BYTE READ
-READ DAC REGISTER
SLAVE
ACK
SLAVE REPEATED
ACK
SLAVE
ACK
MASTER
ACK
MASTER
NACK
0 0 0 0 1 0 0 0
1 0 1 1 0 0 0 0
1 0 1 1 0 0 0 1
DAC MSB
STOP
START
*THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST
MATCH THE ADDRESS SET IN THE ADDR REGISTER.
Figure 7. 2-Wire Transactions
Package Information
Chip Information
SUBSTRATE CONNECTED TO GROUND
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 μSOP
U8+1
21-0036
90-0092
16
Maxim Integrated
DS1086L
3.3V Spread-Spectrum EconOscillator
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
11/03
9/07
0
1
Initial release
ꢀ
Updated Table 2
10
Updated the Ordering Information, Absolute Maximum Ratings, and Package
Information
2
3/12
1, 2, 16
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
17
© 2012 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明