DS1087LU-466 [MAXIM]
3.3V Spread-Spectrum EconOscillator;
| 型号： | DS1087LU-466 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.3V Spread-Spectrum EconOscillator |
| 文件： | 总12页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 1; 11/03
3.3V Spread-Spectrum EconOscillator
General Description
Features
The DS1087L is a clock generator that produces a
spread-spectrum (dithered) square-wave output of fre-
quencies from 130kHz to 66.6MHz. The DS1087L is
shipped from the factory programmed at a specific fre-
quency and spread-spectrum percentage. The user still
has access to an internal frequency divider, selectable
2% or 4% dithered output, and programmable output
power-down/disable mode through a 2-wire program-
ming interface. All the device settings are stored in non-
volatile (NV) EEPROM allowing it to operate in
stand-alone applications. The DS1087L has power-
down and output-enable control pins for power-sensi-
tive applications.
♦ Factory Programmed Square-Wave Generator
from 130kHz to 66.6MHz
♦ No External Timing Components Required
♦ EMI Reduction
♦ 2.7V to 3.6V Supply
♦ User Programmable Down to 130kHz with Divider
(Dependent on Master Oscillator Frequency)
♦ 2% or 4% Selectable Dithered Output
♦ Glitchless Output-Enable Control
♦ 2-Wire Serial Interface
♦ Nonvolatile Settings
Applications
♦ Power-Down Mode
Printers
♦ Programmable Output Power-Down/Disable Mode
Copiers
PCs
Computer Peripherals
Cell Phones
Cable Modems
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS1087LU-yxx
-40°C to +85°C
8 µSOP (118 mils)
Standard Frequency Options
Pin Configuration
PART
FREQUENCY (MHz)
SPREAD (%)
TOP VIEW
DS1087LU-202
DS1087LU-402
DS1087LU-210
DS1087LU-216
DS1087LU-266
DS1087LU-466
DS1087LU-yxx
2.0480
2.0480
10.0
2
4
2
OUT
1
2
3
4
8
7
6
5
SCL
SDA
PDN
OE
16.6
2
2
SPRD
66.6
DS1087L
66.6
4
V
CC
Fixed up to 66.6
2 or 4
GND
Custom frequencies and over 20 standard frequencies avail-
able, contact factory.
µSOP (118 mils)
EconOscillator is a trademark of Dallas Semiconductor.
Typical Operating Circuits appear at end of data sheet.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3.3V Spread-Spectrum EconOscillator
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
Relative to Ground ..........-0.5V to +6.0V
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature ..................See IPC/JEDEC J-STD-020A
CC
Voltage Range on SPRD, PDN, OE, SDA, SCL
Relative to Ground* ................................-0.5V to (V
+ 0.5V)
CC
Operating Temperature Range ...........................-40°C to +85°C
*This voltage must not exceed 6.0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(V
= 2.7V to 3.6V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Supply Voltage
V
(Note 1)
2.7
3.6
V
CC
High-Level Input Voltage
(SDA, SCL, SPRD, PDN, OE)
0.7 x
V
+
CC
0.3
V
V
V
IH
V
CC
Low-Level Input Voltage
(SDA, SCL, SPRD, PDN, OE)
0.3 x
V
CC
V
-0.3
IL
DC ELECTRICAL CHARACTERISTICS
(V
= 2.7V to 3.6V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITION
= min
CC
MIN
TYP
MAX
UNITS
High-Level Output Voltage (OUT)
Low-Level Output Voltage (OUT)
V
I
I
= -4mA, V
= 4mA
2.4
V
V
OH
OH
V
0.4
0.4
0.6
1
OL
OL
V
V
3mA sink current
6mA sink current
0
0
OL1
OL2
Low-Level Output Voltage (SDA)
V
High-Level Input Current
Low-Level Input Current
Supply Current (Active)
I
V
V
= 3.6V
CC
µA
µA
mA
µA
IH
I
= 0
IL
-1
IL
I
C = 15pF (output at f )
15
5
CC
L
0
Standby Current (Power-Down)
I
Power-down mode
CCQ
2
_____________________________________________________________________
3.3V Spread-Spectrum EconOscillator
MASTER OSCILLATOR CHARACTERISTICS
(V
= 2.7V to 3.6V, T = -40°C to +85°C.)
CC
A
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Master Oscillator Range
Available
f
0
33.3
66.6
MHz
Master Oscillator Frequency
Tolerance
∆f
0
V
T
T
V
= 3.3V, T = +25°C (Notes 2, 13)
-0.5
-0.75
-0.5
+0.5
+0.75
+0.5
%
%
%
%
CC
A
f
0
Voltage Frequency
Variation
∆f
Over voltage range, T = +25°C (Note 3)
A
f
0
∆f
Temperature Frequency Variation
Temperature Frequency Variation
0°C to +70°C, V
= 3.3V (Note 4)
CC
f
0
∆f
-40°C to +85°C, V
= 3.3V (Note 4)
-1.5
+0.5
CC
f
0
Prescaler bit J0 = 1 (Note 5)
Prescaler bit J0 = 0 (Note 5)
2
4
Dither Frequency Range
Dither Rate
%
f / 4096
0
Hz
AC ELECTRICAL CHARACTERISTICS
(V
= 2.7V to 3.6V, T = -40°C to +85°C.)
A
CC
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Frequency Stable After
PRESCALER Change
1
period
t
t
+
POR
Power-Up Time
(Note 6)
0.1
0.5
500
1
ms
µs
STAB
Enable of OUT After Exiting
Power-Down Mode
t
STAB
OUT Disabled After Entering
Power-Down Mode
t
ms
PDN
Load Capacitance
C
(Note 7)
15
50
55
pF
%
L
Output Duty Cycle (OUT)
T
= +25°C
45
A
_____________________________________________________________________
3
3.3V Spread-Spectrum EconOscillator
AC ELECTRICAL CHARACTERISTICS—2-WIRE INTERFACE
(V
= 2.7V to 3.6V, T = 0°C to +70°C.)
A
CC
PARAMETER
SYMBOL
CONDITION
Fast mode (Note 8)
MIN
TYP
MAX
400
UNITS
SCL Clock Frequency
f
kHz
SCL
Standard mode (Note 8)
Fast mode (Note 8)
100
1.3
4.7
Bus Free Time Between a STOP
and START Condition
t
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
BUF
Standard mode (Note 8)
Fast mode (Notes 8 and 9)
Standard mode (Notes 8 and 9)
Fast mode (Note 8)
0.6
Hold Time (repeated) START
Condition
t
HD:STA
4.0
1.3
LOW Period of SCL
HIGH Period of SCL
t
LOW
Standard mode (Note 8)
Fast mode (Note 8)
4.7
0.6
t
HIGH
Standard mode (Note 8)
Fast mode
4.0
0.6
Setup Time for a Repeated
START
t
SU:STA
HD:DAT
Standard mode
4.7
Fast mode (Notes 8, 10, and 11)
Standard mode (Notes 8, 10, and 11)
Fast mode (Note 8)
0
0.9
0.9
Data Hold Time
Data Setup Time
t
0
100
t
SU:DAT
Standard mode (Note 8)
Fast mode (Note 12)
Standard mode (Note 12)
Fast mode (Note 12)
Standard mode (Note 12)
Fast mode
250
20 + 0.1C
20 + 0.1C
20 + 0.1C
20 + 0.1C
0.6
300
1000
300
B
Rise Time of Both SDA and SCL
Signals
t
R
B
B
B
Fall Time of Both SDA and SCL
Signals
t
F
1000
Setup Time for STOP
t
SU:STO
Standard mode
4.0
Capacitive Load for Each Bus
NV Write Cycle Time
C
(Note 12)
400
10
pF
ms
pF
B
t
WR
Input Capacitance
C
5
I
NONVOLATILE MEMORY CHARACTERISTICS
(V
= 2.7V to 3.6V)
CC
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Writes
+70°C
10,000
4
_____________________________________________________________________
3.3V Spread-Spectrum EconOscillator
Note 1:
Note 2:
Note 3:
All voltages are referenced to ground.
This is the absolute accuracy of the master oscillator frequency at the default settings.
This is the change that is observed in master oscillator frequency with changes in voltage from nominal voltage at
T
= +25°C.
A
Note 4:
This is the percentage frequency change from the +25°C frequency due to temperature at V = 3.3V.
CC
Note 5:
Note 6:
The dither deviation of the master oscillator frequency is unidirectional and lower than the undithered frequency.
This indicates the time elapsed between power-up and the output becoming active. An on-chip delay is intentionally
introduced to allow the oscillator to stabilize. t
is equivalent to approximately 512 master clock cycles and depends
stab
on the programmed master oscillator frequency.
Output voltage swings may be impaired at high frequencies combined with high output loading.
A fast-mode device can be used in a standard-mode system, but the requirement t > 250ns must then be met. This
Note 7:
Note 8:
SU:DAT
is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line at least t
+ t
= 1000ns +
R MAX
SU:DAT
250ns = 1250ns before the SCL line is released.
After this period, the first clock pulse is generated.
Note 9:
Note 10: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the V
of the SCL sig-
IH MIN
nal) to bridge the undefined region of the falling edge of SCL.
Note 11: The maximum t
need only be met if the device does not stretch the LOW period (t
) of the SCL signal.
HD:DAT
LOW
Note 12: C —total capacitance of one bus line, timing referenced to 0.9 x V and 0.1 x V .
CC
B
CC
Note 13: Typical frequency shift due to aging is 0.5%. Aging stressing includes Level 1 moisture reflow preconditioning (24hr
+125°C bake, 168hr 85°C/85%RH moisture soak, and 3 solder reflow passes +240 +0/-5°C peak) followed by 1000hr
max V
biased 125°C HTOL, 1000 temperature cycles at -55°C to +125°C, and 168hr 121°C/2 ATM Steam/Unbiased
CC
Autoclave.
Typical Operating Characteristics
(VCC = 3.3V, T = +25°C, unless otherwise noted.)
A
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE
ACTIVE SUPPLY CURRENT
vs. VOLTAGE
SUPPLY CURRENT vs. PRESCALER
7
6
5
4
3
2
1
0
7.5
7.0
6.5
6.0
5.5
5.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
OUTPUT UNLOADED
V
= 3.3V
FREQUENCY = 66.6MHz
OUTPUT UNLOADED
OE = PDN = V
CC
FREQUENCY = 66.6MHz
OE = PDN = V
CC
CC
15pF LOAD
3.6V
3.3V
2.7V
8.2pF LOAD
4.7pF LOAD
UNLOADED
1
10
100
1000
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VOLTAGE (V)
PRESCALER (DECIMAL)
TEMPERATURE (°C)
_____________________________________________________________________
5
3.3V Spread-Spectrum EconOscillator
Typical Operating Characteristics
(VCC = 3.3V, T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. TEMPERATURE WITH OE = 0
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT vs. PRESCALER
6
5
4
3
2
1
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 3.3V
CC
V
= 2.7V
V
= 3.3V
CC
CC
OUPUT UNLOADED
OUTPUT UNLOADED
OUTPUT UNLOADED
FREQUENCY = 66.6MHz
-40°C, +25°C, +85°C
FREQUENCY = 206.4kHz
1
10
100
1000
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
PRESCALER (DECIMAL)
TEMPERATURE (°C)
TEMPERATURE (°C)
FREQUENCY % CHANGE vs.
SUPPLY VOLTAGE
FREQUENCY % CHANGE vs.
TEMPERATURE
ACTIVE SUPPLY CURRENT
vs. SCL FREQUENCY
1.00
0.80
0.60
0.40
0.20
0
1.50
1.00
0.50
0
7
OUTPUT LOADED WITH
12pF OSCILLOSCOPE PROBE
FREQUENCY = 66.6MHz
V
= 3.3V
V
= SDA = 3.3V
CC
FREQUENCY = 66.6MHz
OUTPUT UNLOADED
CC
6
5
4
3
2
1
0
FREQUENCY = 66.6MHz
OUTPUT LOADED WITH
12pF OSCILLOSCOPE PROBE
-0.20
-0.40
-0.60
-0.80
-1.00
-0.50
-1.00
-1.50
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VOLTAGE (V)
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
0
100
200
300
400
TEMPERATURE (°C)
SCL FREQUENCY (kHz)
DUTY CYCLE vs. VOLTAGE
DUTY CYCLE vs. TEMPERATURE
60
59
58
57
56
55
54
53
52
51
50
60
59
58
57
56
55
54
53
52
51
50
FREQUENCY = 66.6MHz
V
= 3.3V
CC
T = +25°C
FREQUENCY = 66.6MHz
OUTPUT LOADED WITH
12pF OSCILLOSCOPE PROBE
A
OUTPUT LOADED WITH
12pF OSCILLOSCOPE PROBE
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
VOLTAGE (V)
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
6
_____________________________________________________________________
3.3V Spread-Spectrum EconOscillator
Pin Description
PIN
1
NAME
OUT
FUNCTION
Oscillator Output
2
SPRD
Dither Enable. When the pin is high, the dither is enabled. When the pin is low, the dither is disabled.
3
V
Power Supply
Ground
CC
4
GND
Output Enable. When the pin is high, the output buffer is enabled. When the pin is low, the output is
disabled but the internal master oscillator is still on.
5
6
OE
Power-Down. When the pin is high, the master oscillator is enabled. When the pin is low, the master
oscillator is disabled (power-down mode).
PDN
7
8
SDA
SCL
2-Wire Serial Data. This pin is for serial data transfer to and from the device.
2-Wire Serial Clock. This pin is used to clock data into and out of the device.
V
CC
EEPROM CONTROL
REGISTERS
SDA
DS1087L
2-WIRE
INTERFACE
ADDR
SCL
PRESCALER
FACTORY-PROGRAMMED
OSCILLATOR
PDN
MASTER
OSCILLATOR
OUTPUT
DITHER
CONTROL
PRESCALER
BY 1, 2, 4...256
OUT
OE
TRIANGLE WAVE
GENERATOR
SPRD
GND
DITHER SIGNAL
Figure 1. Functional Diagram
_____________________________________________________________________
7
3.3V Spread-Spectrum EconOscillator
Table 1. Register Summary
REGISTER
ADDR
BINARY
FACTORY DEFAULT
ACCESS
LO/
HIZ
PRESCALER
02h
X
X
X
X
J0
P3
P2
A2
P1
A1
P0
A0
110- - - - - b
R/W
1
1
1
1
ADDR
0Dh
3Fh
X
X
WC
11110000b
—
R/W
—
1
1
WRITE EE
No Data
X = Don’t care; read as one.
1
programmed frequency. Although the output frequency
changes when the dither is enabled, the duty cycle
does not change.
Detailed Description
A block diagram of the DS1087L is shown in Figure 1.
Output Frequency
The internal master oscillator can generate a square
wave with a frequency range of 33.3MHz to 66.6MHz.
The master oscillator frequency and output frequency
are factory programmed, although the user can use the
programmable divider to divide the master oscillator
frequency by 2x (where x equals 0 to 8).
The dither is controlled by the J0 bit in the PRESCALER
register and enabled with the SPRD pin. The maximum
spectral attenuation occurs when the prescaler is set to
1. The spectral attenuation is reduced by 2.7dB for
every factor of 2 that is used in the prescaler. This hap-
pens because the prescaler’s divider function tends to
average the dither in creating the lower frequency.
However, the most stringent spectral emission limits are
imposed on the higher frequencies where the prescaler
is set to a low divider ratio.
Output Control and Power-Down
Two user control signals control the output. The output-
enable pin, OE, gates the clock output buffer and the
PDN pin disables the master oscillator and turns off the
output for power-sensitive applications (note: the
power-down command must persist for at least two out-
put frequency cycles plus 10µs for deglitching purpos-
es). On power-up, the output is disabled until power is
stable and the master oscillator has generated 512
clock cycles.
A triangle-wave generator injects an offset element into
the master oscillator to dither its output. The dither rate
(see Equation 1) is based on the master oscillator fre-
quency. Figure 2 shows a plot of the output frequency
versus dither rate.
f
(1)
0
DitherRate =
Both controls feature a synchronous enable, which
ensures there are no output glitches when the output is
enabled. The synchronous enable also ensures a con-
stant time interval (for a given frequency setting) from
an enable signal to the first output transition.
4096
where f = master oscillator frequency
0
Register Summary
The DS1087L registers are used to change the dither
amount, output frequency, and slave address. A sum-
mary of the registers is shown in Table 1. Once pro-
grammed into EEPROM, the settings only need to be
reprogrammed if it is desired to reconfigure the device.
Spread Spectrum
The DS1087L can reduce radiated emission peaks. The
output frequency can be dithered 2% or 4% below the
OUTPUT FREQUENCY
PRESCALER Register
Bit 5:
Output Low or High-Z. The LO/HIZ bit
controls the output. During power-down,
while the output is deactivated, if the
LO/HIZ bit is set to 0, the output is high-Z.
If the LO/HIZ bit is set to 1, the output is
driven low.
f /N
O
(f /N) - 4%
O
DITHER RATE
2f /4096
0
f /4096
O
O
Bit 4:
Dither Control. The J0 bit controls the
dither applied to the output. When J0 is
high, 2% peak dither is selected. When
J0 is low, 4% peak dither is selected.
WHERE N = (2X)
f
0
= FACTORY PROGRAMMED MASTER OSCILLATOR FREQUENCY
Figure 2. Output Frequency vs. Dither Rate
_____________________________________________________________________
8
3.3V Spread-Spectrum EconOscillator
Bits 3 to 0:
Prescaler Divider. The prescaler bits
_______2-Wire Serial Port Operation
(bits P3 to P0) divide the master oscillator
frequency by 2x where x can be from 0 to
8. Any prescaler bit value entered that is
greater than 8 decodes as 8.
2-Wire Serial Data Bus
The DS1087L communicates through a 2-wire serial
interface. A device that sends data onto the bus is
defined as a transmitter, and a device receiving data
as a receiver. The device that controls the message is
called a "master." The devices that are controlled by the
master are "slaves." A master device that generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions must control the
bus. The DS1087L operates as a slave on the 2-wire
bus. Connections to the bus are made through the
open-drain I/O lines SDA and SCL.
ADDR Register
Bit 3:
Write Control. The WC bit determines if
the EEPROM is to be written to after reg-
ister contents have been changed. If WC
= 0 (default), EEPROM is written automat-
ically after a write. If WC = 1, the EEP-
ROM is only written when the WRITE EE
command is issued. See the WRITE EE
Command section for more information.
The following bus protocol has been defined (see
Figures 3 and 5):
Bits 2 to 0:
Address. The A0, A1, A2 bits determine
the lower nibble of the 2-wire slave
address.
•
Data transfer can be initiated only when the bus is
not busy.
WRITE EE Command
•
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH are
interpreted as control signals.
The WRITE EE command is useful in closed-loop appli-
cations where the registers are frequently written. In
applications where the register contents are frequently
written, the WC bit should be set to 1 to prevent wear-
ing out the EEPROM. Regardless of the value of the WC
bit, the value of the ADDR register is always written
immediately to EEPROM. When the WRITE EE com-
mand has been received, the contents of the registers
are copied into the EEPROM, thus locking in the regis-
ter settings.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
HIGH.
Start data transfer: A change in the state of the
data line, from HIGH to LOW, while the clock is
HIGH, defines a START condition.
Stop data transfer: A change in the state of the
data line, from LOW to HIGH, while the clock line
is HIGH, defines the STOP condition.
SDA
MSB
SLAVE ADDRESS
R/W
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
9
ACK
ACK
START
CONDITION
STOP
CONDITION
OR REPEATED
START
REPEATED IF MORE BYTES
ARE TRANSFERRED
CONDITION
Figure 3. 2-Wire Data Transfer Protocol
_____________________________________________________________________
9
3.3V Spread-Spectrum EconOscillator
Figures 3, 4, 5, and 6 detail how data transfer is
accomplished on the 2-wire bus. Depending upon
the state of the R/W bit, two types of data transfer
are possible:
MSB
1
LSB
R/W
0
1
1
A2
A1
A0
DEVICE
IDENTIFIER
DEVICE
ADDRESS
1) Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is
the slave address. Next follows a number of data
bytes. The slave returns an acknowledge bit after
each received byte.
Figure 4. Slave Address
2) Data transfer from a slave transmitter to a master
receiver. The first byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all
received bytes other than the last byte. At the end
of the last received byte, a not acknowledge is
returned.
Data valid: The state of the data line represents
valid data when, after a START condition, the data
line is stable for the duration of the HIGH period of
the clock signal. The data on the line must be
changed during the LOW period of the clock sig-
nal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condi-
tion and terminated with a STOP condition. The
number of data bytes transferred between START
and STOP conditions is not limited, and is deter-
mined by the master device. The information is
transferred byte-wise and each receiver acknowl-
edges with a ninth bit.
The master device generates all the serial clock
pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a
repeated START condition. Since a repeated
START condition is also the beginning of the next
serial transfer, the bus is not released.
Within the bus specifications a standard mode
(100kHz clock rate) and a fast mode (400kHz
clock rate) are defined. The DS1087L works in
both modes.
The DS1087L can operate in the following two modes:
Slave receiver mode: Serial data and clock are
received through SDA and SCL. After each byte is
received, an acknowledge bit is transmitted.
START and STOP conditions are recognized as
the beginning and end of a serial transfer.
Address recognition is performed by hardware
after reception of the slave address and direction
bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowl-
edge after the byte has been received. The master
device must generate an extra clock pulse that is
associated with this acknowledge bit.
A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable LOW during
the HIGH period of the acknowledge-related clock
pulse. Of course, setup and hold times must be
taken into account. When the DS1087L EEPROM
is being written to, it is not able to perform addi-
tional responses. In this case, the slave DS1087L
sends a not acknowledge to any data transfer
request made by the master. It resumes normal
operation when the EEPROM operation is com-
plete.
Slave transmitter mode: The first byte is received
and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates
that the transfer direction is reversed. Serial data
is transmitted on SDA by the DS1087L while the
serial clock is input on SCL. START and STOP
conditions are recognized as the beginning and
end of a serial transfer.
Slave Address
Figure 4 shows the first byte sent to the device. It
includes the device identifier, device address, and the
R/W bit. The device address must match the address
set in the ADDR register (bits A0, A1, and A2).
A master must signal an end of data to the slave
by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to
enable the master to generate the STOP condition.
Registers/Commands
See Table 1 for the complete list of registers/com-
mands and Figure 6 for an example of using them.
10
____________________________________________________________________
3.3V Spread-Spectrum EconOscillator
SDA
SCL
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
Figure 5. 2-Wire AC Characteristics
TYPICAL 2-WIRE WRITE TRANSACTION
MSB
LSB
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
1
0
1
1
A2* A1* A0* R/W
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
READ/
WRITE
DEVICE
ADDRESS
COMMAND/REGISTER ADDRESS
DATA
DEVICE IDENTIFIER
EXAMPLE 2-WIRE TRANSACTIONS (WHEN A0, A1, AND A2 ARE ZERO)
B0h
02h
DATA
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
A) SINGLE BYTE WRITE
-WRITE PRESCALER
REGISTER TO 128
STOP
1 0 1 1 0 0 0 0
0 0 0 0 0 0 1 0
1 0 0 0 0 0 0 0
START
02h
B1h
DATA
1 0 0 0 0 0 0 0
B0h
B) SINGLE BYTE READ
-READ PRESCALER
REGISTER
SLAVE REPEATED
MASTER
NACK
SLAVE
ACK
SLAVE
ACK
STOP
1 0 1 1 0 0 0 1
START 1 0 1 1 0 0 0 0
0 0 0 0 0 0 1 0
ACK
START
*THE ADDRESS DETERMINED BY A0, A1, AND A2 MUST
MATCH THE ADDRESS SET IN THE ADDR REGISTER.
Figure 6. 2-Wire Transactions
decoupling applications. These capacitors should be
placed as close to the VCC and GND pins as possible.
Application Information
Power-Supply Decoupling
To achieve the best results when using the DS1087L,
decouple the power supply with 0.01µF and 0.1µF
high-quality, ceramic, surface-mount capacitors.
Surface-mount components minimize lead inductance,
which improves performance, and ceramic capacitors
tend to have adequate high-frequency response for
Stand-alone Mode
SCL and SDA cannot be left floating even in stand-
alone mode. If the DS1087L never needs to be pro-
grammed in-circuit, including during production
testing, SDA and SCL can be wired high.
____________________________________________________________________ 11
3.3V Spread-Spectrum EconOscillator
Typical Operating Circuits
Processor-Controlled Mode
Stand-Alone Mode
V
CC
V
CC
DITHERED 130kHz TO
66.6MHz OUTPUT
MICRO-
PROCESSOR
4.7kΩ
SCL
4.7kΩ
SCL*
XTL1/OSC1
XTL2/OSC2
OUT
DITHERED 130kHz TO
66.6MHz OUTPUT
V
CC
SPRD
SDA*
PDN
OE
N.C.
DS1087L
2-WIRE
INTERFACE
V
CC
OUT
V
CC
SDA
V
GND
SPRD
CC
DS1087L
V
CC
PDN
OE
DECOUPLING CAPACITORS
GND
(0.1µF and 0.01µF)
*SDA AND SCL CAN BE CONNECTED DIRECTLY HIGH IF THE DS1087L NEVER NEEDS
TO BE PROGRAMMED IN-CIRCUIT, INCLUDING DURING PRODUCTION TESTING.
DECOUPLING CAPACITORS
(0.1µF and 0.01µF)
Chip Topology
Package Information
For the latest package outline information, go to
TRANSISTOR COUNT: 10000
www.maxim-ic.com/DallasPackInfo
SUBSTRATE CONNECTED TO GROUND
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
©2020 ICPDF网 联系我们和版权申明