DS1100LZ-250
更新时间：2024-09-18 18:40:59
品牌：MAXIM
描述：Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, SOP-8
概述
规格参数
数据手册
替代型号DS1100LZ-250 概述
Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, SOP-8 延时时钟芯片 延迟线
DS1100LZ-250 规格参数
| 是否无铅： | 含铅 | 是否Rohs认证： | 不符合 |
| 生命周期： | Obsolete | 零件包装代码： | SOIC |
| 包装说明： | 0.150 INCH, SOP-8 | 针数： | 8 |
| Reach Compliance Code： | not_compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 1 week |
| 风险等级： | 5.43 | Is Samacsys： | N |
| 系列： | 1100 | JESD-30 代码： | R-PDSO-G8 |
| JESD-609代码： | e0 | 长度： | 4.9 mm |
| 逻辑集成电路类型： | SILICON DELAY LINE | 湿度敏感等级： | 1 |
| 功能数量： | 1 | 抽头/阶步数： | 5 |
| 端子数量： | 8 | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 输出阻抗标称值（Z0）： | 50 Ω |
| 输出极性： | TRUE | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | SOP | 封装等效代码： | SOP8,.25 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE |
| 峰值回流温度（摄氏度）： | 245 | 电源： | 3.3 V |
| 最大电源电流（ICC）： | 10 mA | 可编程延迟线： | NO |
| Prop。Delay @ Nom-Sup： | 250 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 1.75 mm | 子类别： | Delay Lines |
| 最大供电电压 (Vsup)： | 3.6 V | 最小供电电压 (Vsup)： | 3 V |
| 标称供电电压 (Vsup)： | 3.3 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | Tin/Lead (Sn/Pb) | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | NOT SPECIFIED | 总延迟标称（td）： | 250 ns |
| 宽度： | 3.9 mm | Base Number Matches： | 1 |
DS1100LZ-250 数据手册
通过下载DS1100LZ-250数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载DS1100L
3.3V 5-Tap Economy Timing Element (Delay Line)
GENERAL DESCRIPTION
FEATURES
The DS1100L is a 3.3V version of the DS1100. It
is characterized for operation over the range 3.0V
to 3.6V. The DS1100L series delay lines have
five equally spaced taps providing delays from
4ns to 500ns. These devices are offered in
surface-mount packages to save PCB area. Low
cost and superior reliability over hybrid
technology is achieved by the combination of a
100% silicon delay line and industry-standard
µMAX® and SO packaging. The DS1100L 5-tap
silicon delay line reproduces the input-logic state
at the output after a fixed delay as specified by
the extension of the part number after the dash.
The DS1100L is designed to reproduce both
leading and trailing edges with equal precision.
Each tap is capable of driving up to 10 74LS
loads.
. All-Silicon Timing Circuit
. Five Taps Equally Spaced
. Delays are Stable and Precise
. Both Leading- and Trailing-Edge Accuracy
. 3.3V Version of the DS1100
. Low-Power CMOS
. TTL-/CMOS-Compatible
. Vapor-Phase and IR Solderable
. Custom Delays Available
. Fast-Turn Prototypes
. Delays Specified Over Both Commercial and
Industrial Temperature Ranges
PIN ASSIGNMENT
IN
TAP 2
TAP 4
GND
1
2
3
4
8
7
6
5
VCC
TAP 1
TAP 3
TAP 5
DS1100L
Maxim Integrated can customize standard
products to meet special needs.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
DS1100LZ SO (150mils)
DS1100LU µMAX
PIN DESCRIPTION
TAP 1 to TAP 5
- TAP Output Number
- +3.3V
- Ground
VCC
GND
IN
- Input
19-5736; Rev 7/15
1 of 7
DS1100L
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground ...........................................-0.5V to +6.0V
Short-Circuit Output Current............................................................................ 50mA for 1s
Continuous Power Dissipation (TA = +70°C)
SO (derate 5.9mW/°C above +70°C) ................................................................ 470.6mW
µMAX (derate 4.5mW/°C above +70°C.............................................................. 362mW
Operating Temperature Range .................................................................... -40°C to +85°C
Storage Temperature Range ...................................................................... -55°C to +125°C
Lead Temperature (soldering, 10s)...........................................................................+300°C
Soldering Temperature (reflow)
Lead(Pb)-free ........................................................................................................+260°C
Containing lead(Pb)...............................................................................................+240°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V; TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER
Supply Voltage
High-Level
Input Voltage
Low-Level
Input Voltage
Input-Leakage
Current
Active Current
High-Level
SYMBOL
CONDITIONS
MIN
3.0
TYP
3.3
MAX UNITS NOTES
VCC
3.6
VCC
0.3
V
5
+
VIH
VIL
2.0
-0.3
-1.0
V
5
0.8
V
5
II
+1.0
-1
μA
mA
mA
0.0V ≤ VI ≤ VCC
ICC
IOH
VCC = Max; Freq. = 1MHz
VCC = Min. VOH = 2.3
10
6, 8
Output Current
Low-Level
Output Current
IOL
VCC = Min. VOL = 0.5
8
mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V; TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
20% of
Tap 5
tPLH
TYP
MAX UNITS NOTES
Input
Pulse Width
tWI
ns
9
1, 3, 4,
7, 10
+25°C 3.3V
-2
-3
Table 1
Table 1
Table 1
Table 1
Table 1
Table 1
2.0
+2
+3
ns
ns
ns
%
%
%
ns
Input-to-Tap
Delay Tolerance
(Delays ≤ 40ns)
tPLH,
tPHL
1, 2, 3,
4, 7, 10
1, 2, 3,
4, 7, 10
1, 3, 4,
7, 10
1, 2, 3,
4, 7, 10
1, 2, 3,
4, 7, 10
0°C to +70°C
-40°C to +85°C
+25°C 3.3V
-4
+4
-5
+5
Input-to-Tap
Delay Tolerance
(Delays > 40ns)
tPLH,
tPHL
0°C to +70°C
-40°C to +85°C
-8
+8
-13
+13
Output Rise or Fall
Time
tOF, tOR
2.5
Power-Up Time
Input Period
tPU
Period
200
μs
ns
2(tWI)
9
2 of 7
DS1100L
CAPACITANCE
(TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input Capacitance
CIN
5
10
pF
NOTES:
1) Initial tolerances are ± with respect to the nominal value at +25°C and VCC = 3.3V for both leading and
trailing edge.
2) Temperature and voltage tolerance is with respect to the nominal delay value over the stated temperature
range, and a supply-voltage range of 3.0V to 3.6V.
3) All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP 1
slows down, all other taps also slow down; TAP 3 can never be faster than TAP 2.
4) Intermediate delay values are available on a custom basis. For further information, contact the factory at
custom.oscillators@maximintegrated.com.
5) All voltages are referenced to ground.
6) Measured with outputs open.
7) See Test Conditions section at the end of this data sheet.
8) Frequencies higher than 1MHz result in higher ICC values.
9) At or near maximum frequency the delay accuracy can vary and will be application sensitive (i.e.,
decoupling, layout).
10) The “-75” version is specified and tested with an additional 2ns of tolerance on the specified minimum
input-to-tap delay tolerance parameters for TAP 1 to TAP 3. Delay values for TAP 4 to TAP 5 meet data
sheet specifications.
Figure 1. LOGIC DIAGRAM
Figure 2. TIMING DIAGRAM: SILICON DELAY LINE
3 of 7
DS1100L
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the
DS1100L. The input waveform is produced by a precision pulse generator under software control. Time
delays are measured by a time interval counter (20ps resolution) connected between the input and each
tap. Each tap is selected and connected to the counter by a VHF switch control unit. All measurements
are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus.
TEST CONDITIONS INPUT:
Ambient Temperature: 25°C ±3°C
Supply Voltage (VCC): 3.3V ±0.1V
Input Pulse:
High = 3.0V ±0.1V
Low = 0.0V ±0.1V
Source Impedance:
Rise and Fall Time:
Pulse Width:
50Ω max
3.0ns max (measured between 10% and 90%)
500ns (1μs for -500 version)
1μs (2μs for -500 version)
Period:
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
Note: Above conditions are for test only and do not restrict the operation of the device under other
data sheet conditions.
4 of 7
DS1100L
Figure 3. TEST CIRCUIT
Table 1. DS1100L PART NUMBER DELAY
NOMINAL DELAYS (ns)
PART
DS1100L-xxx
-20
TAP 1
4
TAP 2
8
TAP 3
12
TAP 4
16
TAP 5
20
25
-25
5
10
15
20
-30
6
12
18
24
30
-35
7
14
21
28
35
-40
8
16
24
32
40
-45
9
18
27
36
45
-50
-60
-75
10
12
15
20
25
30
35
40
50
60
100
20
24
30
40
50
60
70
80
30
36
45
60
75
90
105
120
150
180
300
40
48
60
80
100
120
140
160
200
240
400
50
60
75
-100
-125
-150
-175
-200
-250
-300
-500
100
125
150
175
200
250
300
500
100
120
200
5 of 7
DS1100L
ORDERING INFORMATION
PART
DS1100LZ-xxx
DS1100LZ-xxx/T&R
DS1100LZ-xxx+
DS1100LZ-xxx+T
DS1100LU-xxx
DS1100LU-xxx/T&R
DS1100LU-xxx+
DS1100LU-xxx+T
xxx Denotes total time delay (ns) (see Table 1).
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R and T = Tape and reel.
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 SO
8 SO
8 SO
8 SO
8 µMAX
8 µMAX
8 µMAX
8 µMAX
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0041
LAND PATTERN NO.
90-0096
8 SO (150 mils)
S8+4
U8+1
21-0036
90-0092
8 µMAX
6 of 7
DS1100L
REVISION HISTORY
REVISION
PAGES
CHANGED
DESCRIPTION
DATE
Changed µSOP package type to µMAX; updated the Absolute
Maximum Ratings section; added the customer support email address to
the electrical characteristics Note 4; added the Ordering Information
and Package Information tables
3/11
1−6
Added continuous power dissipation numbers to the Absolute
Maximum Ratings section; added Note 10 to the Input-to-Tap Delay
Tolerance (Delays ≤ 40ns) parameter in the AC Electrical
Characteristics table
10/11
7/15
2, 3
2, 3
Revised Note 10 and revised AC Electrical Characteristics table
7 of 7
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2015 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
DS1100LZ-250 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| DS1100LZ-250+ | MAXIM | Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, S | 完全替代 |
|
DS1100LZ-250 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| DS1100LZ-250+ | MAXIM | Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8 | 获取价格 |
|
| DS1100LZ-250+T | MAXIM | Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8 | 获取价格 |
|
| DS1100LZ-30 | DALLAS | 3.3V 5-Tap Economy Timing Element Delay Line | 获取价格 |
|
| DS1100LZ-30 | MAXIM | Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, SOP-8 | 获取价格 |
|
| DS1100LZ-30+ | MAXIM | Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8 | 获取价格 |
|
| DS1100LZ-30+T | MAXIM | Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8 | 获取价格 |
|
| DS1100LZ-300 | DALLAS | 3.3V 5-Tap Economy Timing Element Delay Line | 获取价格 |
|
| DS1100LZ-300+ | MAXIM | Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8 | 获取价格 |
|
| DS1100LZ-35 | DALLAS | 3.3V 5-Tap Economy Timing Element Delay Line | 获取价格 |
|
| DS1100LZ-35+T | MAXIM | Silicon Delay Line, 1-Func, 5-Tap, True Output, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOP-8 | 获取价格 |
|
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