DS1135Z-20+ [MAXIM]
3-in-1 High-Speed Silicon Delay Line;
| 型号： | DS1135Z-20+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3-in-1 High-Speed Silicon Delay Line 光电二极管 逻辑集成电路 延迟线 |
| 文件： | 总7页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1135
3-in-1 High-Speed Silicon
Delay Line
FEATURES
PIN ASSIGNMENT
. All-Silicon Timing Circuit
. Three Independent Buffered Delays
. Stable and Precise Over Temperature and
Voltage
. Leading and Trailing Edge Precision
Preserves the Input Symmetry
. Vapor Phasing, IR, and Wave Solderable
. Available in Tape and Reel
. Commercial and Industrial Temperature
Ranges Available
VCC
IN1
IN2
1
2
3
8
7
6
5
OUT1
OUT2
IN3
OUT3
GND
4
DS1135Z 8-Pin SO (150 mils)
. 5V Operation (Refer to DS1135L for 3V
Operation)
. Recommended Replacement for DS1013
and DS1035
PIN DESCRIPTION
IN1-IN3
OUT1-OUT3
VCC
- Input Signals
- Output Signals
- +5V Supply
- Ground
GND
DESCRIPTION
The DS1135 series is a low-power, +5V high-speed version of the popular DS1013 and DS1035.
The DS1135 series of delay lines have three independent logic buffered delays in a single package. The
device is our fastest 3-in-1 delay line. It is available in a standard 8-pin 150-mil SO.
The device features precise leading and trailing edge accuracy. It has the inherent reliability of an all-
silicon delay line solution. Each output is capable of driving up to 10 LS loads.
Standard delay values are indicated in Table 1.
1 of 7
19-6411; Rev 8/12
DS1135
LOGIC DIAGRAM Figure 1
IN
OUT
TIME DELAY
ONE OF THREE
PART NUMBER DELAY TABLE (tPLH, tPHL) Table 1
TOLERANCE OVER
TEMP AND VOLTAGE
(Note 2)
DELAY PER
OUTPUT
(ns)
INITIAL
TOLERANCE
(Note 1)
PART NUMBER
0°C to +70°C
-40°C to +85°C
±1.5ns
±1.5ns
±1.5ns
±1.5ns
±2ns
DS1135Z-6+
DS1135Z-8+
DS1135Z-10+
DS1135Z-12+
DS1135Z-15+
DS1135Z-20+
DS1135Z-25+
DS1135Z-30+
6/6/6
8/8/8
±1.0ns
±1.0ns
±1.0ns
±1.0ns
±1.0ns
±1.0ns
±1.5ns
±1.5ns
±1.0ns
±1.0ns
±1.0ns
±1.0ns
10/10/10
12/12/12
15/15/15
20/20/20
25/25/25
30/30/30
±1.5ns
±1.5ns
±2ns
±1.5ns
±2ns
±1.5ns
±2ns
NOTES:
1. Nominal conditions are +25°C and VCC =+5.0V.
2. Voltage range of 4.75V to 5.25V.
3. Delay accuracies are for both leading and trailing edges.
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1135.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20ps resolution) connected to the output. The DS1135 output taps
are selected and connected to the interval counter by a VHF switch control unit. All measurements are
fully automated with each instrument controlled by the computer over an IEEE 488 bus.
2 of 7
DS1135
DS1135 TEST CIRCUIT Figure 2
PULSE
GENERATOR
START
TIME INTERVAL
COUNTER
3
IN
50Ω
STOP
VHF
SWITCH
CONTROL
UNIT
UNIT UNDER
TEST
OUT
50Ω
TAPS 1-3
3 of 7
DS1135
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Short Circuit Output Current
Operating Temperature
Storage Temperature
-1.0V to +6.0V
50mA for 1 second
-40°C to +85°C
-55°C to +125°C
+300°C
Lead Temperature (soldering, 10 seconds)
Soldering Temperature (reflow)
+260°C
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +5V ±5%, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER
Supply Voltage
SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
VCC
ICC
4.75
5.00
5.25
35
V
1
VCC = 5.25V,
period = 1µs
Active Current
mA
VCC
+0.5
0.8
High Level Input Voltage
VIH
2.2
V
1
1
Low Level Input Voltage
Input Leakage
High Level Output
Current
VIL
IL
-0.5
-1.0
V
µA
0V ≤ VI ≤ VCC
VCC = 4.75V,
VOH = 4V
VCC = 4.75V,
VOL= 0.5V
+1.0
ICC
ICC
-1.0
mA
1
1
Low Level Output Current
12
mA
AC ELECTRICAL CHARACTERISTICS
(VCC = +5V ±5%, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Period
tPERIOD
2 (tWI )
100% of
Tap Delay
ns
ns
2
Input Pulse Width
tWI
2
Input-to-Output Delay
Output Rise or Fall Time
Power-up Time
tPLH
tOF, tOR
tPU
,
tPHL
See Table 1
ns
2.5
100
2.0
ns
ms
3
CAPACITANCE
(TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
10
pF
4 of 7
DS1135
TEST CONDITIONS
Ambient Temperature: 25°C ± 3°C
Supply Voltage (VCC): 5.0V ± 0.1V
Input Pulse:
High: 3.0V ± 0.1V
Low: 0.0V ± 0.1V
Source Impedance: 50Ω Max.
Rise and Fall Time: 3.0ns Max. - Measured between 0.6V and 2.4V.
Pulse Width: 500ns
Pulse Period: 1µs
Output Load Capacitance: 15pF
Output: Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
Note: The above conditions are for test only and do not restrict the devices under other data sheet
conditions.
NOTES:
1. All voltages are referenced to ground.
2. Pulse width and duty cycle specifications may be exceeded; however, accuracy will be application
sensitive with respect to decoupling, layout, etc.
3. Power-up time is the time from the application of power to the time stable delays are being produced
at the output.
TIMING DIAGRAM
PERIOD
tRISE
tFALL
80%
20%
1.5V
1.5V
1.5V
IN
tWI
tWI
tPLH
tPHL
tOR
tOF
1.5V
1.5V
OUT
5 of 7
DS1135
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
tWI (Pulse Width): The elapsed time on the pulse between the 1.5-volt point on the leading edge and the
1.5-volt point on the trailing edge or the 1.5-volt point on the trailing edge and the 1.5-volt point on the
leading edge.
t
RISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge on the
input pulse.
t
PLH (Time Delay, Rising): The elapsed time between the 1.5-volt point on the leading edge of the input
pulse and the 1.5-volt point on the leading edge of the output pulse.
t
PHL (Time Delay, Falling): The elapsed time between the 1.5-volt point on the falling edge of the input
pulse and the 1.5-volt point on the falling edge of the output pulse.
ORDERING INFORMATION
DS1135
TIME DELAY (ns): 6, 8, 10, 12, 15, 20,
25, 30
PACKAGE TYPE:
Z = SOIC (150-MIL)
PACKAGE INFORMATION
For
the
latest
package
outline
information
and
land
patterns
(footprints),
go
to
www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of
RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
8 SO
S8+2
21-0041
90-0096
6 of 7
DS1135
REVISION HISTORY
REVISION
PAGES
CHANGED
DESCRIPTION
DATE
Removed the DIP and µSOP packages; updated the Absolute
Maximum Ratings section; added the Package Information section
8/12
1, 2, 4, 6
7 of 7
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated
The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
相关型号：
DS1135Z-30+T&R
Silicon Delay Line, 3-Func, 1-Tap, True Output, PDSO8, 0.150 INCH, MINI, SOIC-8
MAXIM
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