DS1225AB-200IND [MAXIM]
Non-Volatile SRAM Module, 8KX8, 200ns, CMOS, PDMA28, 0.720 INCH, DIP-28;
| 型号： | DS1225AB-200IND |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Non-Volatile SRAM Module, 8KX8, 200ns, CMOS, PDMA28, 0.720 INCH, DIP-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1225AB/AD
64k Nonvolatile SRAM
www.maxim-ic.com
FEATURES
PIN ASSIGNMENT
C 10 years minimum data retention in the
absence of external power
VCC
WE
NC
NC
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
3
4
5
6
7
8
C Data is automatically protected during power
loss
A8
A6
A5
A4
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
C Directly replaces 8k x 8 volatile static RAM
or EEPROM
A3
C Unlimited write cycles
A2
C Low-power CMOS
A1
A0
9
10
C JEDEC standard 28-pin DIP package
C Read and write access times as fast as 70 ns
C Lithium energy source is electrically
disconnected to retain freshness until power
is applied for the first time
DQ0
11
12
DQ1
DQ2
GND
13
14
28-Pin ENCAPSULATED PACKAGE
720-mil EXTENDED
C Full ±10% VCC operating range (DS1225AD)
C Optional ±5% VCC operating range
(DS1225AB)
PIN DESCRIPTION
C Optional industrial temperature range of
-40°C to +85°C, designated IND
A0-A12
- Address Inputs
DQ0-DQ7
- Data In/Data Out
CE
WE
- Chip Enable
- Write Enable
OE
- Output Enable
- Power (+5V)
- Ground
VCC
GND
NC
- No Connect
DESCRIPTION
The DS1225AB and DS1225AD are 65,536-bit, fully static, nonvolatile SRAMs organized as 8192 words
by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which
constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium
energy source is automatically switched on and write protection is unconditionally enabled to prevent
data corruption. The NV SRAMs can be used in place of existing 8k x 8 SRAMs directly conforming to
the popular bytewide 28-pin DIP standard. The devices also match the pinout of the 2764 EPROM and
the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the
number of write cycles that can be executed and no additional support circuitry is required for
microprocessor interfacing.
1 of 10
081203
DS1225AB/AD
READ MODE
The DS1225AB and DS1225AD execute a read cycle whenever WE (Write Enable) is inactive (high) and
CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 13
address inputs (A0 -A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be
available to the eight data output drivers within tACC (Access Time) after the last address input signal is
stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not
satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is
either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1225AB and DS1225AD execute a write cycle whenever the WE and CE signals are active
(low) after address inputs are stable. The later-occurring falling edge of CE or WE will determine the
start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address
inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum
recovery time (tWR ) before another cycle can be initiated. The OE control signal should be kept inactive
(high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and
OE active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1225AB provides full functional capability for VCC greater than 4.75 volts and write protects by
4.5 volts. The DS1225AD provides full-functional capability for VCC greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry.
The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, the power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1225AB and 4.5 volts for the
DS1225AD.
FRESHNESS SEAL
Each DS1225 is shipped from Dallas Semiconductor with the lithium energy source disconnected,
guaranteeing full energy capacity. When VCC is first applied at a level of greater than VTP , the lithium
energy source is enabled for battery backup operation.
2 of 10
DS1225AB/AD
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
-0.3V to +6.0V
0°C to 70°C; -40°C to +85°C for IND parts
-40°C to +70°C; -40°C to +85°C for IND parts
260°C for 10 seconds
Storage Temperature
Soldering Temperature
ꢀ This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA: See Note 10)
PARAMETER
SYMBOL MIN
TYP
5.0
MAX
5.25
5.5
UNITS NOTES
DS1225AB Power Supply Voltage
DS1225AD Power Supply Voltage
Logic 1
VCC
VCC
VIH
VIL
4.75
4.50
2.2
V
V
V
V
5.0
VCC
+0.8
Logic 0
0.0
(TA: See Note 10)
(VCC =5V ± 5% for DS1225AB)
(VCC =5V ± 10% for DS1225AD)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
Input Leakage Current
I/O Leakage Current
IIL
-1.0
+1.0
ꢁA
IIO
-1.0
+1.0
ꢁA
CE > VIH< VCC
Output Current @ 2.4V
IOH
IOL
ICCS1
-1.0
2.0
mA
mA
mA
Output Current @ 0.4V
5.0
3.0
10.0
5.0
Standby Current CE =2.2V
ICCS2
mA
Standby Current CE =VCC -0.5V
Operating Current
(Commercial)
ICC01
75
mA
Operating Current
(Industrial)
ICC01
VTP
VTP
85
mA
V
Write Protection Voltage
(DS1225AB)
4.50
4.25
4.62
4.37
4.75
4.5
Write Protection Voltage
(DS1225AD)
V
CAPACITANCE
PARAMETER
(TA =25°C)
SYMBOL MIN
TYP
MAX
10
UNITS NOTES
Input Capacitance
CIN
5
5
pF
pF
Input/Output Capacitance
CI/O
10
3 of 10
DS1225AB/AD
(TA: See Note 10)
(VCC =5V ± 5% for DS1225AB)
(VCC =5V ± 10% for DS1225AD)
AC ELECTRICAL CHARACTERISTICS
DS1225AB-70 DS1225AB-85
DS1225AD-70 DS1225AD-85
MIN MAX MIN MAX
PARAMETER
SYMBOL
UNITS NOTES
Read Cycle Time
Access Time
OE to Output Valid
tRC
tACC
tOE
70
85
ns
ns
ns
70
35
70
85
45
85
tCO
tCOE
tOD
ns
CE to Output Valid
5
5
5
5
ns
5
5
OE or CE to Output Active
Output High Z from Deselection
Output Hold from Address
Change
25
30
ns
tOH
ns
Write Cycle Time
tWC
tWP
70
55
0
85
65
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
3
Address Setup Time
Write Recovery Time
tAW
tWR1
tWR2
0
0
12
13
10
10
25
30
tODW
5
5
4
Output High Z from WE
5
tOEW
5
Output Active from WE
Data Setup Time
tDS
30
35
Data Hold Time
tDH1
0
0
12
13
tDH2
10
10
4 of 10
DS1225AB/AD
AC ELECTRICAL CHARACTERISTICS (cont’d)
DS1225AB- 150
DS1225AD- 150
DS1225AB-200
DS1225AD-200
PARAMETER
SYMBOL
UNITS NOTES
MIN MAX MIN MAX
Read Cycle Time
Access Time
OE to Output Valid
tRC
tACC
tOE
tCO
tCOE
tOD
150
200
ns
ns
ns
150
70
150
200
100
200
ns
CE to Output Valid
5
5
5
5
ns
ns
5
5
OE or CE to Output Active
Output High Z from Deselection
Output Hold from Address
Change
35
35
tOH
ns
Write Cycle Time
tWC
tWP
150
100
0
200
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
3
Address Setup Time
Write Recovery Time
tAW
tWR1
tWR2
0
0
12
13
10
10
35
35
tODW
5
5
4
Output High Z from WE
5
tOEW
5
Output Active from WE
Data Setup Time
tDS
60
80
Data Hold Time
tDH1
0
0
12
13
tDH2
10
10
5 of 10
DS1225AB/AD
READ CYCLE
SEE NOTE 1
WRITE CYCLE 1
SEE NOTES 2, 3, 4, 6, 7, 8 AND 12
WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
6 of 10
DS1225AB/AD
POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING
(TA : See Note 10)
PARAMETER
SYMBOL MIN
TYP
MAX
UNITS NOTES
tPD
tF
tR
1.5
11
VCC Fail Detect to CE and WE Inactive
VCC slew from VTP to 0V
VCC slew from 0V to VTP
ꢁs
ꢁs
ꢁs
300
300
tPU
tREC
2
125
ms
ms
VCC Valid to CE and WE Inactive
VCC Valid to End of Write Protection
(TA = 25°C)
PARAMETER
Expected Data Retention Time
SYMBOL MIN TYP MAX UNITS NOTES
tDR 10 years
9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
7 of 10
DS1225AB/AD
NOTES:
1. WE is high for a read cycle.
2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance
state.
3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE
going low to the earlier of CE or WE going high.
4. tDS are measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output
buffers remain in a high-impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high-impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high-impedance state during this period.
9. Each DS1225AB and each DS1225AD has a built-in switch that disconnects the lithium source until
VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of
VCC starting from the time power is first applied by the user. This parameter is guaranteed by design
and is not 100% tested.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
11. In a power down condition the voltage on any pin may not exceed the voltage on VCC
12. tWR1 , tDH1 are measured from WE going high.
.
13. tWR2 , tDH2 are measured from CE going high.
14. DS1225 modules are recognized by Underwriters Laboratory (U.L.ꢂ) under file E99151.
DC TEST CONDITIONS
Outputs Open
AC TEST CONDITIONS
Output Load: 100 pF + 1TTL Gate
Input Pulse Levels: 0 - 3.0V
Timing Measurement Reference Levels
Input: 1.5V
Cycle = 200ns for Operating Current
All Voltages Are Referenced to Ground
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
8 of 10
DS1225AB/AD
ORDERING INFORMATION
200: 200 ns
9 of 10
DS1225AB/AD
DS1225AB/AD NONVOLATILE SRAM, 28-PIN, 720-MIL EXTENDED MODULE
PKG
DIM
28-PIN
MIN
MAX
A IN. 1.520
1.540
39.12
0.720
18.29
0.415
10.54
0.130
3.30
MM
B IN.
MM
38.61
0.695
17.65
0.395
10.03
C IN.
MM
D IN. 0.100
MM
E IN.
MM
F IN.
MM
2.54
0.017
0.43
0.030
0.76
0.120
3.05
0.160
4.06
G IN. 0.090
0.110
2.79
MM
H IN
MM
J IN.
MM
2.29
0.590
14.99
0.008
0.20
0.630
16.00
0.012
0.30
K IN. 0.015
MM 0.38
0.021
0.53
10 of 10
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